projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3bace359 JZ |
1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | */ | |
| 23 | #ifndef _HWMGR_H_ | |
| 24 | #define _HWMGR_H_ | |
| 25 | ||
| 28a18bab | 26 | #include <linux/seq_file.h> |
| 3bace359 JZ |
27 | #include "amd_powerplay.h" |
| 28 | #include "pp_instance.h" | |
| 29 | #include "hardwaremanager.h" | |
| 30 | #include "pp_power_source.h" | |
| c82baa28 | 31 | #include "hwmgr_ppt.h" |
| 17c00a2f RZ |
32 | #include "ppatomctrl.h" |
| 33 | #include "hwmgr_ppt.h" | |
| 3bace359 JZ |
34 | |
| 35 | struct pp_instance; | |
| 36 | struct pp_hwmgr; | |
| 37 | struct pp_hw_power_state; | |
| 38 | struct pp_power_state; | |
| 39 | struct PP_VCEState; | |
| c28eae26 | 40 | struct phm_fan_speed_info; |
| 17c00a2f RZ |
41 | struct pp_atomctrl_voltage_table; |
| 42 | ||
| 43 | ||
| 44 | enum DISPLAY_GAP { | |
| 45 | DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ | |
| 46 | DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ | |
| 47 | DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ | |
| 48 | DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ | |
| 49 | }; | |
| 50 | typedef enum DISPLAY_GAP DISPLAY_GAP; | |
| 51 | ||
| 52 | ||
| 53 | struct vi_dpm_level { | |
| 54 | bool enabled; | |
| 55 | uint32_t value; | |
| 56 | uint32_t param1; | |
| 57 | }; | |
| 58 | ||
| 59 | struct vi_dpm_table { | |
| 60 | uint32_t count; | |
| 61 | struct vi_dpm_level dpm_level[1]; | |
| 62 | }; | |
| 3bace359 JZ |
63 | |
| 64 | enum PP_Result { | |
| 65 | PP_Result_TableImmediateExit = 0x13, | |
| 66 | }; | |
| 67 | ||
| 68 | #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 | |
| 69 | #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 | |
| 70 | #define PCIE_PERF_REQ_GEN1 2 | |
| 71 | #define PCIE_PERF_REQ_GEN2 3 | |
| 72 | #define PCIE_PERF_REQ_GEN3 4 | |
| 73 | ||
| 74 | enum PHM_BackEnd_Magic { | |
| 75 | PHM_Dummy_Magic = 0xAA5555AA, | |
| 76 | PHM_RV770_Magic = 0xDCBAABCD, | |
| 77 | PHM_Kong_Magic = 0x239478DF, | |
| 78 | PHM_NIslands_Magic = 0x736C494E, | |
| 79 | PHM_Sumo_Magic = 0x8339FA11, | |
| 80 | PHM_SIslands_Magic = 0x369431AC, | |
| 81 | PHM_Trinity_Magic = 0x96751873, | |
| 82 | PHM_CIslands_Magic = 0x38AC78B0, | |
| 83 | PHM_Kv_Magic = 0xDCBBABC0, | |
| 84 | PHM_VIslands_Magic = 0x20130307, | |
| 85 | PHM_Cz_Magic = 0x67DCBA25 | |
| 86 | }; | |
| 87 | ||
| 3bace359 JZ |
88 | |
| 89 | #define PHM_PCIE_POWERGATING_TARGET_GFX 0 | |
| 90 | #define PHM_PCIE_POWERGATING_TARGET_DDI 1 | |
| 91 | #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 | |
| 92 | #define PHM_PCIE_POWERGATING_TARGET_PHY 3 | |
| 93 | ||
| 94 | typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, | |
| 95 | void *output, void *storage, int result); | |
| 96 | ||
| 97 | typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); | |
| 98 | ||
| 28a18bab RZ |
99 | struct phm_set_power_state_input { |
| 100 | const struct pp_hw_power_state *pcurrent_state; | |
| 101 | const struct pp_hw_power_state *pnew_state; | |
| 102 | }; | |
| 103 | ||
| 3bace359 JZ |
104 | struct phm_acp_arbiter { |
| 105 | uint32_t acpclk; | |
| 106 | }; | |
| 107 | ||
| 108 | struct phm_uvd_arbiter { | |
| 109 | uint32_t vclk; | |
| 110 | uint32_t dclk; | |
| 111 | uint32_t vclk_ceiling; | |
| 112 | uint32_t dclk_ceiling; | |
| 113 | }; | |
| 114 | ||
| 115 | struct phm_vce_arbiter { | |
| 116 | uint32_t evclk; | |
| 117 | uint32_t ecclk; | |
| 118 | }; | |
| 119 | ||
| 120 | struct phm_gfx_arbiter { | |
| 121 | uint32_t sclk; | |
| 122 | uint32_t mclk; | |
| 123 | uint32_t sclk_over_drive; | |
| 124 | uint32_t mclk_over_drive; | |
| 125 | uint32_t sclk_threshold; | |
| 126 | uint32_t num_cus; | |
| 127 | }; | |
| 128 | ||
| 129 | /* Entries in the master tables */ | |
| 130 | struct phm_master_table_item { | |
| 131 | phm_check_function isFunctionNeededInRuntimeTable; | |
| 132 | phm_table_function tableFunction; | |
| 133 | }; | |
| 134 | ||
| 135 | enum phm_master_table_flag { | |
| 136 | PHM_MasterTableFlag_None = 0, | |
| 137 | PHM_MasterTableFlag_ExitOnError = 1, | |
| 138 | }; | |
| 139 | ||
| 140 | /* The header of the master tables */ | |
| 141 | struct phm_master_table_header { | |
| 142 | uint32_t storage_size; | |
| 143 | uint32_t flags; | |
| 144 | struct phm_master_table_item *master_list; | |
| 145 | }; | |
| 146 | ||
| 147 | struct phm_runtime_table_header { | |
| 148 | uint32_t storage_size; | |
| 149 | bool exit_error; | |
| 150 | phm_table_function *function_list; | |
| 151 | }; | |
| 152 | ||
| 153 | struct phm_clock_array { | |
| 154 | uint32_t count; | |
| 155 | uint32_t values[1]; | |
| 156 | }; | |
| 157 | ||
| 158 | struct phm_clock_voltage_dependency_record { | |
| 159 | uint32_t clk; | |
| 160 | uint32_t v; | |
| 161 | }; | |
| 162 | ||
| 163 | struct phm_vceclock_voltage_dependency_record { | |
| 164 | uint32_t ecclk; | |
| 165 | uint32_t evclk; | |
| 166 | uint32_t v; | |
| 167 | }; | |
| 168 | ||
| 169 | struct phm_uvdclock_voltage_dependency_record { | |
| 170 | uint32_t vclk; | |
| 171 | uint32_t dclk; | |
| 172 | uint32_t v; | |
| 173 | }; | |
| 174 | ||
| 175 | struct phm_samuclock_voltage_dependency_record { | |
| 176 | uint32_t samclk; | |
| 177 | uint32_t v; | |
| 178 | }; | |
| 179 | ||
| 180 | struct phm_acpclock_voltage_dependency_record { | |
| 181 | uint32_t acpclk; | |
| 182 | uint32_t v; | |
| 183 | }; | |
| 184 | ||
| 185 | struct phm_clock_voltage_dependency_table { | |
| 186 | uint32_t count; /* Number of entries. */ | |
| 187 | struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ | |
| 188 | }; | |
| 189 | ||
| 190 | struct phm_phase_shedding_limits_record { | |
| 191 | uint32_t Voltage; | |
| 192 | uint32_t Sclk; | |
| 193 | uint32_t Mclk; | |
| 194 | }; | |
| 195 | ||
| 196 | ||
| 197 | extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, | |
| 198 | struct phm_runtime_table_header *rt_table, | |
| 199 | void *input, void *output); | |
| 200 | ||
| 201 | extern int phm_construct_table(struct pp_hwmgr *hwmgr, | |
| 202 | struct phm_master_table_header *master_table, | |
| 203 | struct phm_runtime_table_header *rt_table); | |
| 204 | ||
| 205 | extern int phm_destroy_table(struct pp_hwmgr *hwmgr, | |
| 206 | struct phm_runtime_table_header *rt_table); | |
| 207 | ||
| 208 | ||
| 209 | struct phm_uvd_clock_voltage_dependency_record { | |
| 210 | uint32_t vclk; | |
| 211 | uint32_t dclk; | |
| 212 | uint32_t v; | |
| 213 | }; | |
| 214 | ||
| 215 | struct phm_uvd_clock_voltage_dependency_table { | |
| 216 | uint8_t count; | |
| 217 | struct phm_uvd_clock_voltage_dependency_record entries[1]; | |
| 218 | }; | |
| 219 | ||
| 220 | struct phm_acp_clock_voltage_dependency_record { | |
| 221 | uint32_t acpclk; | |
| 222 | uint32_t v; | |
| 223 | }; | |
| 224 | ||
| 225 | struct phm_acp_clock_voltage_dependency_table { | |
| 226 | uint32_t count; | |
| 227 | struct phm_acp_clock_voltage_dependency_record entries[1]; | |
| 228 | }; | |
| 229 | ||
| 230 | struct phm_vce_clock_voltage_dependency_record { | |
| 231 | uint32_t ecclk; | |
| 232 | uint32_t evclk; | |
| 233 | uint32_t v; | |
| 234 | }; | |
| 235 | ||
| 236 | struct phm_phase_shedding_limits_table { | |
| 237 | uint32_t count; | |
| 238 | struct phm_phase_shedding_limits_record entries[1]; | |
| 239 | }; | |
| 240 | ||
| 241 | struct phm_vceclock_voltage_dependency_table { | |
| 242 | uint8_t count; /* Number of entries. */ | |
| 243 | struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ | |
| 244 | }; | |
| 245 | ||
| 246 | struct phm_uvdclock_voltage_dependency_table { | |
| 247 | uint8_t count; /* Number of entries. */ | |
| 248 | struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ | |
| 249 | }; | |
| 250 | ||
| 251 | struct phm_samuclock_voltage_dependency_table { | |
| 252 | uint8_t count; /* Number of entries. */ | |
| 253 | struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ | |
| 254 | }; | |
| 255 | ||
| 256 | struct phm_acpclock_voltage_dependency_table { | |
| 257 | uint32_t count; /* Number of entries. */ | |
| 258 | struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ | |
| 259 | }; | |
| 260 | ||
| 261 | struct phm_vce_clock_voltage_dependency_table { | |
| 262 | uint8_t count; | |
| 263 | struct phm_vce_clock_voltage_dependency_record entries[1]; | |
| 264 | }; | |
| 265 | ||
| 266 | struct pp_hwmgr_func { | |
| 267 | int (*backend_init)(struct pp_hwmgr *hw_mgr); | |
| 268 | int (*backend_fini)(struct pp_hwmgr *hw_mgr); | |
| 269 | int (*asic_setup)(struct pp_hwmgr *hw_mgr); | |
| 270 | int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); | |
| 28a18bab RZ |
271 | |
| 272 | int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, | |
| 273 | struct pp_power_state *prequest_ps, | |
| 274 | const struct pp_power_state *pcurrent_ps); | |
| 275 | ||
| 276 | int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, | |
| 277 | enum amd_dpm_forced_level level); | |
| 278 | ||
| 279 | int (*dynamic_state_management_enable)( | |
| 280 | struct pp_hwmgr *hw_mgr); | |
| 281 | ||
| 282 | int (*patch_boot_state)(struct pp_hwmgr *hwmgr, | |
| 283 | struct pp_hw_power_state *hw_ps); | |
| 284 | ||
| 285 | int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, | |
| 286 | unsigned long, struct pp_power_state *); | |
| 3bace359 | 287 | int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); |
| 28a18bab RZ |
288 | int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); |
| 289 | int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); | |
| 290 | int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); | |
| 291 | int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); | |
| 292 | int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); | |
| 293 | int (*power_state_set)(struct pp_hwmgr *hwmgr, | |
| 294 | const void *state); | |
| 295 | void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr, | |
| 296 | struct seq_file *m); | |
| 297 | int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr); | |
| e8c7de5b RZ |
298 | int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); |
| 299 | int (*display_config_changed)(struct pp_hwmgr *hwmgr); | |
| b1132013 RZ |
300 | int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); |
| 301 | int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, | |
| 302 | const uint32_t *msg_id); | |
| c28eae26 RZ |
303 | int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); |
| 304 | int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); | |
| 305 | int (*get_temperature)(struct pp_hwmgr *hwmgr); | |
| 306 | int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); | |
| 307 | int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); | |
| 308 | int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); | |
| 309 | int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); | |
| 310 | int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); | |
| 311 | int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); | |
| 312 | int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); | |
| 313 | int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); | |
| 314 | int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); | |
| 315 | int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); | |
| 316 | int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr, | |
| 317 | const void *thermal_interrupt_info); | |
| 09b4c872 RZ |
318 | bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); |
| 319 | int (*check_states_equal)(struct pp_hwmgr *hwmgr, | |
| 320 | const struct pp_hw_power_state *pstate1, | |
| 321 | const struct pp_hw_power_state *pstate2, | |
| 322 | bool *equal); | |
| 73c9f222 RZ |
323 | int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); |
| 324 | int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, | |
| 325 | bool cc6_disable, bool pstate_disable, | |
| 326 | bool pstate_switch_disable); | |
| c4dd206b | 327 | int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, |
| e273b041 RZ |
328 | struct amd_pp_simple_clock_info *info); |
| 329 | int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, | |
| 330 | PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); | |
| 331 | int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, | |
| 332 | const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); | |
| 333 | int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); | |
| 334 | int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); | |
| e1d32e60 | 335 | int (*power_off_asic)(struct pp_hwmgr *hwmgr); |
| f3898ea1 EH |
336 | int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table); |
| 337 | int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size); | |
| 338 | int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level); | |
| 339 | int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); | |
| 3bace359 JZ |
340 | }; |
| 341 | ||
| 342 | struct pp_table_func { | |
| 343 | int (*pptable_init)(struct pp_hwmgr *hw_mgr); | |
| 344 | int (*pptable_fini)(struct pp_hwmgr *hw_mgr); | |
| 345 | int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); | |
| 346 | int (*pptable_get_vce_state_table_entry)( | |
| 347 | struct pp_hwmgr *hwmgr, | |
| 348 | unsigned long i, | |
| 349 | struct PP_VCEState *vce_state, | |
| 350 | void **clock_info, | |
| 351 | unsigned long *flag); | |
| 352 | }; | |
| 353 | ||
| 354 | union phm_cac_leakage_record { | |
| 355 | struct { | |
| 356 | uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ | |
| 357 | uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ | |
| 358 | }; | |
| 359 | struct { | |
| 360 | uint16_t Vddc1; | |
| 361 | uint16_t Vddc2; | |
| 362 | uint16_t Vddc3; | |
| 363 | }; | |
| 364 | }; | |
| 365 | ||
| 366 | struct phm_cac_leakage_table { | |
| 367 | uint32_t count; | |
| 368 | union phm_cac_leakage_record entries[1]; | |
| 369 | }; | |
| 370 | ||
| 371 | struct phm_samu_clock_voltage_dependency_record { | |
| 372 | uint32_t samclk; | |
| 373 | uint32_t v; | |
| 374 | }; | |
| 375 | ||
| 376 | ||
| 377 | struct phm_samu_clock_voltage_dependency_table { | |
| 378 | uint8_t count; | |
| 379 | struct phm_samu_clock_voltage_dependency_record entries[1]; | |
| 380 | }; | |
| 381 | ||
| 382 | struct phm_cac_tdp_table { | |
| 383 | uint16_t usTDP; | |
| 384 | uint16_t usConfigurableTDP; | |
| 385 | uint16_t usTDC; | |
| 386 | uint16_t usBatteryPowerLimit; | |
| 387 | uint16_t usSmallPowerLimit; | |
| 388 | uint16_t usLowCACLeakage; | |
| 389 | uint16_t usHighCACLeakage; | |
| 390 | uint16_t usMaximumPowerDeliveryLimit; | |
| 391 | uint16_t usOperatingTempMinLimit; | |
| 392 | uint16_t usOperatingTempMaxLimit; | |
| 393 | uint16_t usOperatingTempStep; | |
| 394 | uint16_t usOperatingTempHyst; | |
| 395 | uint16_t usDefaultTargetOperatingTemp; | |
| 396 | uint16_t usTargetOperatingTemp; | |
| 397 | uint16_t usPowerTuneDataSetID; | |
| 398 | uint16_t usSoftwareShutdownTemp; | |
| 399 | uint16_t usClockStretchAmount; | |
| 400 | uint16_t usTemperatureLimitHotspot; | |
| 401 | uint16_t usTemperatureLimitLiquid1; | |
| 402 | uint16_t usTemperatureLimitLiquid2; | |
| 403 | uint16_t usTemperatureLimitVrVddc; | |
| 404 | uint16_t usTemperatureLimitVrMvdd; | |
| 405 | uint16_t usTemperatureLimitPlx; | |
| 406 | uint8_t ucLiquid1_I2C_address; | |
| 407 | uint8_t ucLiquid2_I2C_address; | |
| 408 | uint8_t ucLiquid_I2C_Line; | |
| 409 | uint8_t ucVr_I2C_address; | |
| 410 | uint8_t ucVr_I2C_Line; | |
| 411 | uint8_t ucPlx_I2C_address; | |
| 412 | uint8_t ucPlx_I2C_Line; | |
| 413 | }; | |
| 414 | ||
| 415 | struct phm_ppm_table { | |
| 416 | uint8_t ppm_design; | |
| 417 | uint16_t cpu_core_number; | |
| 418 | uint32_t platform_tdp; | |
| 419 | uint32_t small_ac_platform_tdp; | |
| 420 | uint32_t platform_tdc; | |
| 421 | uint32_t small_ac_platform_tdc; | |
| 422 | uint32_t apu_tdp; | |
| 423 | uint32_t dgpu_tdp; | |
| 424 | uint32_t dgpu_ulv_power; | |
| 425 | uint32_t tj_max; | |
| 426 | }; | |
| 427 | ||
| 428 | struct phm_vq_budgeting_record { | |
| 429 | uint32_t ulCUs; | |
| 430 | uint32_t ulSustainableSOCPowerLimitLow; | |
| 431 | uint32_t ulSustainableSOCPowerLimitHigh; | |
| 432 | uint32_t ulMinSclkLow; | |
| 433 | uint32_t ulMinSclkHigh; | |
| 434 | uint8_t ucDispConfig; | |
| 435 | uint32_t ulDClk; | |
| 436 | uint32_t ulEClk; | |
| 437 | uint32_t ulSustainableSclk; | |
| 438 | uint32_t ulSustainableCUs; | |
| 439 | }; | |
| 440 | ||
| 441 | struct phm_vq_budgeting_table { | |
| 442 | uint8_t numEntries; | |
| 443 | struct phm_vq_budgeting_record entries[1]; | |
| 444 | }; | |
| 445 | ||
| 446 | struct phm_clock_and_voltage_limits { | |
| 447 | uint32_t sclk; | |
| 448 | uint32_t mclk; | |
| 449 | uint16_t vddc; | |
| 450 | uint16_t vddci; | |
| 451 | uint16_t vddgfx; | |
| 452 | }; | |
| 453 | ||
| c82baa28 | 454 | /* Structure to hold PPTable information */ |
| 3bace359 | 455 | |
| c82baa28 | 456 | struct phm_ppt_v1_information { |
| 457 | struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; | |
| 458 | struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; | |
| 459 | struct phm_clock_array *valid_sclk_values; | |
| 460 | struct phm_clock_array *valid_mclk_values; | |
| 461 | struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; | |
| 462 | struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; | |
| 463 | struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; | |
| 464 | struct phm_ppm_table *ppm_parameter_table; | |
| 465 | struct phm_cac_tdp_table *cac_dtp_table; | |
| 466 | struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; | |
| 467 | struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; | |
| 468 | struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; | |
| 469 | struct phm_ppt_v1_pcie_table *pcie_table; | |
| 470 | uint16_t us_ulv_voltage_offset; | |
| 471 | }; | |
| 3bace359 JZ |
472 | |
| 473 | struct phm_dynamic_state_info { | |
| 474 | struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; | |
| 475 | struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; | |
| 476 | struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; | |
| 477 | struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; | |
| 478 | struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; | |
| 479 | struct phm_clock_array *valid_sclk_values; | |
| 480 | struct phm_clock_array *valid_mclk_values; | |
| 481 | struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; | |
| 482 | struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; | |
| 483 | uint32_t mclk_sclk_ratio; | |
| 484 | uint32_t sclk_mclk_delta; | |
| 485 | uint32_t vddc_vddci_delta; | |
| 486 | uint32_t min_vddc_for_pcie_gen2; | |
| 487 | struct phm_cac_leakage_table *cac_leakage_table; | |
| 488 | struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; | |
| 489 | ||
| 490 | struct phm_vce_clock_voltage_dependency_table | |
| 9c0bad90 | 491 | *vce_clock_voltage_dependency_table; |
| 3bace359 | 492 | struct phm_uvd_clock_voltage_dependency_table |
| 9c0bad90 | 493 | *uvd_clock_voltage_dependency_table; |
| 3bace359 JZ |
494 | struct phm_acp_clock_voltage_dependency_table |
| 495 | *acp_clock_voltage_dependency_table; | |
| 496 | struct phm_samu_clock_voltage_dependency_table | |
| 497 | *samu_clock_voltage_dependency_table; | |
| 498 | ||
| 499 | struct phm_ppm_table *ppm_parameter_table; | |
| 500 | struct phm_cac_tdp_table *cac_dtp_table; | |
| 501 | struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; | |
| 502 | struct phm_vq_budgeting_table *vq_budgeting_table; | |
| 503 | }; | |
| 504 | ||
| c82baa28 | 505 | struct pp_fan_info { |
| 506 | bool bNoFan; | |
| 507 | uint8_t ucTachometerPulsesPerRevolution; | |
| 508 | uint32_t ulMinRPM; | |
| 509 | uint32_t ulMaxRPM; | |
| 510 | }; | |
| 511 | ||
| 512 | struct pp_advance_fan_control_parameters { | |
| 513 | uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ | |
| 514 | uint16_t usTMed; /* The middle temperature where we change slopes. */ | |
| 515 | uint16_t usTHigh; /* The high temperature for setting the second slope. */ | |
| 516 | uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ | |
| 517 | uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ | |
| 518 | uint16_t usPWMHigh; /* The PWM value at THigh. */ | |
| 519 | uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ | |
| 520 | uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ | |
| 521 | uint16_t usTMax; /* The max temperature */ | |
| 522 | uint8_t ucFanControlMode; | |
| 523 | uint16_t usFanPWMMinLimit; | |
| 524 | uint16_t usFanPWMMaxLimit; | |
| 525 | uint16_t usFanPWMStep; | |
| 526 | uint16_t usDefaultMaxFanPWM; | |
| 527 | uint16_t usFanOutputSensitivity; | |
| 528 | uint16_t usDefaultFanOutputSensitivity; | |
| 529 | uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ | |
| 530 | uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ | |
| 531 | uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ | |
| 532 | uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ | |
| 533 | uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ | |
| 534 | uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ | |
| 535 | uint16_t usFanCurrentLow; /* Low current */ | |
| 536 | uint16_t usFanCurrentHigh; /* High current */ | |
| 537 | uint16_t usFanRPMLow; /* Low RPM */ | |
| 538 | uint16_t usFanRPMHigh; /* High RPM */ | |
| 539 | uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ | |
| 540 | uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ | |
| 541 | uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ | |
| 542 | uint16_t usFanGainEdge; /* The following is added for Fiji */ | |
| 543 | uint16_t usFanGainHotspot; | |
| 544 | uint16_t usFanGainLiquid; | |
| 545 | uint16_t usFanGainVrVddc; | |
| 546 | uint16_t usFanGainVrMvdd; | |
| 547 | uint16_t usFanGainPlx; | |
| 548 | uint16_t usFanGainHbm; | |
| 549 | }; | |
| 550 | ||
| 551 | struct pp_thermal_controller_info { | |
| 552 | uint8_t ucType; | |
| 553 | uint8_t ucI2cLine; | |
| 554 | uint8_t ucI2cAddress; | |
| 555 | struct pp_fan_info fanInfo; | |
| 556 | struct pp_advance_fan_control_parameters advanceFanControlParameters; | |
| 557 | }; | |
| 558 | ||
| 559 | struct phm_microcode_version_info { | |
| 560 | uint32_t SMC; | |
| 561 | uint32_t DMCU; | |
| 562 | uint32_t MC; | |
| 563 | uint32_t NB; | |
| 564 | }; | |
| 565 | ||
| 566 | /** | |
| 567 | * The main hardware manager structure. | |
| 568 | */ | |
| 3bace359 JZ |
569 | struct pp_hwmgr { |
| 570 | uint32_t chip_family; | |
| 571 | uint32_t chip_id; | |
| 572 | uint32_t hw_revision; | |
| 573 | uint32_t sub_sys_id; | |
| 574 | uint32_t sub_vendor_id; | |
| 575 | ||
| 576 | void *device; | |
| 577 | struct pp_smumgr *smumgr; | |
| 578 | const void *soft_pp_table; | |
| 9c0bad90 | 579 | bool need_pp_table_upload; |
| 3bace359 | 580 | enum amd_dpm_forced_level dpm_level; |
| 28a18bab | 581 | bool block_hw_access; |
| 3bace359 JZ |
582 | struct phm_gfx_arbiter gfx_arbiter; |
| 583 | struct phm_acp_arbiter acp_arbiter; | |
| 584 | struct phm_uvd_arbiter uvd_arbiter; | |
| 585 | struct phm_vce_arbiter vce_arbiter; | |
| 586 | uint32_t usec_timeout; | |
| 587 | void *pptable; | |
| 588 | struct phm_platform_descriptor platform_descriptor; | |
| 589 | void *backend; | |
| e1d32e60 | 590 | enum PP_DAL_POWERLEVEL dal_power_level; |
| 3bace359 JZ |
591 | struct phm_dynamic_state_info dyn_state; |
| 592 | struct phm_runtime_table_header setup_asic; | |
| e1d32e60 | 593 | struct phm_runtime_table_header power_down_asic; |
| 3bace359 JZ |
594 | struct phm_runtime_table_header disable_dynamic_state_management; |
| 595 | struct phm_runtime_table_header enable_dynamic_state_management; | |
| 28a18bab RZ |
596 | struct phm_runtime_table_header set_power_state; |
| 597 | struct phm_runtime_table_header enable_clock_power_gatings; | |
| e8c7de5b | 598 | struct phm_runtime_table_header display_configuration_changed; |
| c28eae26 RZ |
599 | struct phm_runtime_table_header start_thermal_controller; |
| 600 | struct phm_runtime_table_header set_temperature_range; | |
| 3bace359 JZ |
601 | const struct pp_hwmgr_func *hwmgr_func; |
| 602 | const struct pp_table_func *pptable_func; | |
| 603 | struct pp_power_state *ps; | |
| 73c9f222 | 604 | enum pp_power_source power_source; |
| 3bace359 | 605 | uint32_t num_ps; |
| c82baa28 | 606 | struct pp_thermal_controller_info thermal_controller; |
| c28eae26 RZ |
607 | bool fan_ctrl_is_in_default_mode; |
| 608 | uint32_t fan_ctrl_default_mode; | |
| 609 | uint32_t tmin; | |
| c82baa28 | 610 | struct phm_microcode_version_info microcode_version_info; |
| 3bace359 JZ |
611 | uint32_t ps_size; |
| 612 | struct pp_power_state *current_ps; | |
| 613 | struct pp_power_state *request_ps; | |
| 614 | struct pp_power_state *boot_ps; | |
| 615 | struct pp_power_state *uvd_ps; | |
| 14f63411 | 616 | struct amd_pp_display_configuration display_config; |
| 3bace359 JZ |
617 | }; |
| 618 | ||
| 619 | ||
| 620 | extern int hwmgr_init(struct amd_pp_init *pp_init, | |
| 621 | struct pp_instance *handle); | |
| 622 | ||
| 623 | extern int hwmgr_fini(struct pp_hwmgr *hwmgr); | |
| 624 | ||
| 625 | extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr); | |
| 626 | ||
| 627 | extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, | |
| 628 | uint32_t value, uint32_t mask); | |
| 629 | ||
| 630 | extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr, | |
| 631 | uint32_t index, uint32_t value, uint32_t mask); | |
| 632 | ||
| c82baa28 | 633 | extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr, |
| 634 | uint32_t indirect_port, uint32_t index); | |
| 3bace359 | 635 | |
| c82baa28 | 636 | extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr, |
| 637 | uint32_t indirect_port, | |
| 638 | uint32_t index, | |
| 639 | uint32_t value); | |
| 3bace359 JZ |
640 | |
| 641 | extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr, | |
| 642 | uint32_t indirect_port, | |
| 643 | uint32_t index, | |
| 644 | uint32_t value, | |
| 645 | uint32_t mask); | |
| 646 | ||
| 647 | extern void phm_wait_for_indirect_register_unequal( | |
| 648 | struct pp_hwmgr *hwmgr, | |
| 649 | uint32_t indirect_port, | |
| 650 | uint32_t index, | |
| 651 | uint32_t value, | |
| 652 | uint32_t mask); | |
| 653 | ||
| 17c00a2f RZ |
654 | extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr); |
| 655 | extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr); | |
| 656 | extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr); | |
| 657 | ||
| 658 | extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table); | |
| 659 | extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); | |
| 660 | extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table); | |
| 661 | extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table); | |
| 662 | extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table); | |
| 663 | extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max); | |
| 664 | extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes); | |
| 665 | extern int32_t phm_get_dpm_level_enable_mask_value(void *table); | |
| 666 | extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage); | |
| 667 | extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci); | |
| 668 | extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); | |
| 669 | extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, | |
| 670 | uint16_t virtual_voltage_id, int32_t *sclk); | |
| 671 | extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); | |
| 672 | extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); | |
| 673 | extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); | |
| 674 | ||
| 28a18bab RZ |
675 | |
| 676 | #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU | |
| 677 | ||
| 3bace359 JZ |
678 | #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT |
| 679 | #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK | |
| 680 | ||
| 681 | #define PHM_SET_FIELD(origval, reg, field, fieldval) \ | |
| 682 | (((origval) & ~PHM_FIELD_MASK(reg, field)) | \ | |
| 683 | (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field)))) | |
| 684 | ||
| 685 | #define PHM_GET_FIELD(value, reg, field) \ | |
| 686 | (((value) & PHM_FIELD_MASK(reg, field)) >> \ | |
| 687 | PHM_FIELD_SHIFT(reg, field)) | |
| 688 | ||
| 689 | ||
| 690 | #define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \ | |
| 691 | phm_wait_on_register(hwmgr, index, value, mask) | |
| 692 | ||
| 693 | #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \ | |
| 694 | phm_wait_for_register_unequal(hwmgr, index, value, mask) | |
| 695 | ||
| 696 | #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
| 697 | phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) | |
| 698 | ||
| 699 | #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
| 700 | phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask) | |
| 701 | ||
| 702 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
| 703 | phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask) | |
| 704 | ||
| 705 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ | |
| 706 | phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask) | |
| 707 | ||
| 708 | /* Operations on named registers. */ | |
| 709 | ||
| 710 | #define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \ | |
| 711 | PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask) | |
| 712 | ||
| 713 | #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ | |
| 714 | PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask) | |
| 715 | ||
| 716 | #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ | |
| 717 | PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
| 718 | ||
| 719 | #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ | |
| 720 | PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
| 721 | ||
| 722 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ | |
| 723 | PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
| 724 | ||
| 725 | #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ | |
| 726 | PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) | |
| 727 | ||
| 728 | /* Operations on named fields. */ | |
| 729 | ||
| 730 | #define PHM_READ_FIELD(device, reg, field) \ | |
| 731 | PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field) | |
| 732 | ||
| 733 | #define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \ | |
| 734 | PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
| 735 | reg, field) | |
| 736 | ||
| 737 | #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \ | |
| 738 | PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
| 739 | reg, field) | |
| 740 | ||
| 741 | #define PHM_WRITE_FIELD(device, reg, field, fieldval) \ | |
| 742 | cgs_write_register(device, mm##reg, PHM_SET_FIELD( \ | |
| 743 | cgs_read_register(device, mm##reg), reg, field, fieldval)) | |
| 744 | ||
| 745 | #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \ | |
| 746 | cgs_write_ind_register(device, port, ix##reg, \ | |
| 747 | PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
| 748 | reg, field, fieldval)) | |
| 749 | ||
| 750 | #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \ | |
| 751 | cgs_write_ind_register(device, port, ix##reg, \ | |
| 752 | PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \ | |
| 753 | reg, field, fieldval)) | |
| 754 | ||
| 755 | #define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \ | |
| 756 | PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \ | |
| 757 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 758 | ||
| 759 | #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ | |
| 760 | PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ | |
| 761 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 762 | ||
| 763 | #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \ | |
| 764 | PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \ | |
| 765 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 766 | ||
| 767 | #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \ | |
| 768 | PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \ | |
| 769 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 770 | ||
| 771 | #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ | |
| 772 | PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \ | |
| 773 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 774 | ||
| 775 | #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \ | |
| 776 | PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \ | |
| 777 | << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field)) | |
| 778 | ||
| 779 | /* Operations on arrays of registers & fields. */ | |
| 780 | ||
| 781 | #define PHM_READ_ARRAY_REGISTER(device, reg, offset) \ | |
| 782 | cgs_read_register(device, mm##reg + (offset)) | |
| 783 | ||
| 784 | #define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \ | |
| 785 | cgs_write_register(device, mm##reg + (offset), value) | |
| 786 | ||
| 787 | #define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \ | |
| 788 | PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask) | |
| 789 | ||
| 790 | #define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \ | |
| 791 | PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask) | |
| 792 | ||
| 793 | #define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \ | |
| 794 | PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field) | |
| 795 | ||
| 796 | #define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \ | |
| 797 | PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \ | |
| 798 | PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \ | |
| 799 | reg, field, fieldvalue)) | |
| 800 | ||
| 801 | #define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \ | |
| 802 | PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \ | |
| 803 | (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \ | |
| 804 | PHM_FIELD_MASK(reg, field)) | |
| 805 | ||
| 806 | #define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \ | |
| 807 | PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \ | |
| 808 | (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \ | |
| 809 | PHM_FIELD_MASK(reg, field)) | |
| 810 | ||
| 811 | #endif /* _HWMGR_H_ */ |