[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_guc_fwif.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef _INTEL_GUC_FWIF_H
#define _INTEL_GUC_FWIF_H

/*
 * This file is partially autogenerated, although currently with some manual
 * fixups afterwards. In future, it should be entirely autogenerated, in order
 * to ensure that the definitions herein remain in sync with those used by the
 * GuC's own firmware.
 *
 * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
 */

#define GFXCORE_FAMILY_GEN9		12
#define GFXCORE_FAMILY_UNKNOWN		0x7fffffff

#define GUC_CTX_PRIORITY_KMD_HIGH	0
#define GUC_CTX_PRIORITY_HIGH		1
#define GUC_CTX_PRIORITY_KMD_NORMAL	2
#define GUC_CTX_PRIORITY_NORMAL		3
#define GUC_CTX_PRIORITY_NUM		4

#define GUC_MAX_GPU_CONTEXTS		1024
#define	GUC_INVALID_CTX_ID		GUC_MAX_GPU_CONTEXTS

#define GUC_RENDER_ENGINE		0
#define GUC_VIDEO_ENGINE		1
#define GUC_BLITTER_ENGINE		2
#define GUC_VIDEOENHANCE_ENGINE		3
#define GUC_VIDEO_ENGINE2		4
#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)

/* Work queue item header definitions */
#define WQ_STATUS_ACTIVE		1
#define WQ_STATUS_SUSPENDED		2
#define WQ_STATUS_CMD_ERROR		3
#define WQ_STATUS_ENGINE_ID_NOT_USED	4
#define WQ_STATUS_SUSPENDED_FROM_RESET	5
#define WQ_TYPE_SHIFT			0
#define   WQ_TYPE_BATCH_BUF		(0x1 << WQ_TYPE_SHIFT)
#define   WQ_TYPE_PSEUDO		(0x2 << WQ_TYPE_SHIFT)
#define   WQ_TYPE_INORDER		(0x3 << WQ_TYPE_SHIFT)
#define WQ_TARGET_SHIFT			10
#define WQ_LEN_SHIFT			16
#define WQ_NO_WCFLUSH_WAIT		(1 << 27)
#define WQ_PRESENT_WORKLOAD		(1 << 28)
#define WQ_WORKLOAD_SHIFT		29
#define   WQ_WORKLOAD_GENERAL		(0 << WQ_WORKLOAD_SHIFT)
#define   WQ_WORKLOAD_GPGPU		(1 << WQ_WORKLOAD_SHIFT)
#define   WQ_WORKLOAD_TOUCH		(2 << WQ_WORKLOAD_SHIFT)

#define WQ_RING_TAIL_SHIFT		20
#define WQ_RING_TAIL_MAX		0x7FF	/* 2^11 QWords */
#define WQ_RING_TAIL_MASK		(WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)

#define GUC_DOORBELL_ENABLED		1
#define GUC_DOORBELL_DISABLED		0

#define GUC_CTX_DESC_ATTR_ACTIVE	(1 << 0)
#define GUC_CTX_DESC_ATTR_PENDING_DB	(1 << 1)
#define GUC_CTX_DESC_ATTR_KERNEL	(1 << 2)
#define GUC_CTX_DESC_ATTR_PREEMPT	(1 << 3)
#define GUC_CTX_DESC_ATTR_RESET		(1 << 4)
#define GUC_CTX_DESC_ATTR_WQLOCKED	(1 << 5)
#define GUC_CTX_DESC_ATTR_PCH		(1 << 6)
#define GUC_CTX_DESC_ATTR_TERMINATED	(1 << 7)

/* The guc control data is 10 DWORDs */
#define GUC_CTL_CTXINFO			0
#define   GUC_CTL_CTXNUM_IN16_SHIFT	0
#define   GUC_CTL_BASE_ADDR_SHIFT	12

#define GUC_CTL_ARAT_HIGH		1
#define GUC_CTL_ARAT_LOW		2

#define GUC_CTL_DEVICE_INFO		3
#define   GUC_CTL_GTTYPE_SHIFT		0
#define   GUC_CTL_COREFAMILY_SHIFT	7

#define GUC_CTL_LOG_PARAMS		4
#define   GUC_LOG_VALID			(1 << 0)
#define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
#define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
#define   GUC_LOG_CRASH_PAGES		1
#define   GUC_LOG_CRASH_SHIFT		4
#define   GUC_LOG_DPC_PAGES		3
#define   GUC_LOG_DPC_SHIFT		6
#define   GUC_LOG_ISR_PAGES		3
#define   GUC_LOG_ISR_SHIFT		9
#define   GUC_LOG_BUF_ADDR_SHIFT	12

#define GUC_CTL_PAGE_FAULT_CONTROL	5

#define GUC_CTL_WA			6
#define   GUC_CTL_WA_UK_BY_DRIVER	(1 << 3)

#define GUC_CTL_FEATURE			7
#define   GUC_CTL_VCS2_ENABLED		(1 << 0)
#define   GUC_CTL_KERNEL_SUBMISSIONS	(1 << 1)
#define   GUC_CTL_FEATURE2		(1 << 2)
#define   GUC_CTL_POWER_GATING		(1 << 3)
#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 4)
#define   GUC_CTL_PREEMPTION_LOG	(1 << 5)
#define   GUC_CTL_ENABLE_SLPC		(1 << 7)
#define   GUC_CTL_RESET_ON_PREMPT_FAILURE	(1 << 8)

#define GUC_CTL_DEBUG			8
#define   GUC_LOG_VERBOSITY_SHIFT	0
#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
/* Verbosity range-check limits, without the shift */
#define	  GUC_LOG_VERBOSITY_MIN		0
#define	  GUC_LOG_VERBOSITY_MAX		3
#define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
#define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
#define   GUC_LOG_DISABLED		(1 << 6)
#define   GUC_PROFILE_ENABLED		(1 << 7)
#define   GUC_WQ_TRACK_ENABLED		(1 << 8)
#define   GUC_ADS_ENABLED		(1 << 9)
#define   GUC_DEBUG_RESERVED		(1 << 10)
#define   GUC_ADS_ADDR_SHIFT		11
#define   GUC_ADS_ADDR_MASK		0xfffff800

#define GUC_CTL_RSRVD			9

#define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */

/**
 * DOC: GuC Firmware Layout
 *
 * The GuC firmware layout looks like this:
 *
 *     +-------------------------------+
 *     |        guc_css_header         |
 *     |                               |
 *     | contains major/minor version  |
 *     +-------------------------------+
 *     |             uCode             |
 *     +-------------------------------+
 *     |         RSA signature         |
 *     +-------------------------------+
 *     |          modulus key          |
 *     +-------------------------------+
 *     |          exponent val         |
 *     +-------------------------------+
 *
 * The firmware may or may not have modulus key and exponent data. The header,
 * uCode and RSA signature are must-have components that will be used by driver.
 * Length of each components, which is all in dwords, can be found in header.
 * In the case that modulus and exponent are not present in fw, a.k.a truncated
 * image, the length value still appears in header.
 *
 * Driver will do some basic fw size validation based on the following rules:
 *
 * 1. Header, uCode and RSA are must-have components.
 * 2. All firmware components, if they present, are in the sequence illustrated
 *    in the layout table above.
 * 3. Length info of each component can be found in header, in dwords.
 * 4. Modulus and exponent key are not required by driver. They may not appear
 *    in fw. So driver will load a truncated firmware in this case.
 */

struct guc_css_header {
	uint32_t module_type;
	/* header_size includes all non-uCode bits, including css_header, rsa
	 * key, modulus key and exponent data. */
	uint32_t header_size_dw;
	uint32_t header_version;
	uint32_t module_id;
	uint32_t module_vendor;
	union {
		struct {
			uint8_t day;
			uint8_t month;
			uint16_t year;
		};
		uint32_t date;
	};
	uint32_t size_dw; /* uCode plus header_size_dw */
	uint32_t key_size_dw;
	uint32_t modulus_size_dw;
	uint32_t exponent_size_dw;
	union {
		struct {
			uint8_t hour;
			uint8_t min;
			uint16_t sec;
		};
		uint32_t time;
	};

	char username[8];
	char buildnumber[12];
	uint32_t device_id;
	uint32_t guc_sw_version;
	uint32_t prod_preprod_fw;
	uint32_t reserved[12];
	uint32_t header_info;
} __packed;

struct guc_doorbell_info {
	u32 db_status;
	u32 cookie;
	u32 reserved[14];
} __packed;

union guc_doorbell_qw {
	struct {
		u32 db_status;
		u32 cookie;
	};
	u64 value_qw;
} __packed;

#define GUC_MAX_DOORBELLS		256
#define GUC_INVALID_DOORBELL_ID		(GUC_MAX_DOORBELLS)

#define GUC_DB_SIZE			(PAGE_SIZE)
#define GUC_WQ_SIZE			(PAGE_SIZE * 2)

/* Work item for submitting workloads into work queue of GuC. */
struct guc_wq_item {
	u32 header;
	u32 context_desc;
	u32 ring_tail;
	u32 fence_id;
} __packed;

struct guc_process_desc {
	u32 context_id;
	u64 db_base_addr;
	u32 head;
	u32 tail;
	u32 error_offset;
	u64 wq_base_addr;
	u32 wq_size_bytes;
	u32 wq_status;
	u32 engine_presence;
	u32 priority;
	u32 reserved[30];
} __packed;

/* engine id and context id is packed into guc_execlist_context.context_id*/
#define GUC_ELC_CTXID_OFFSET		0
#define GUC_ELC_ENGINE_OFFSET		29

/* The execlist context including software and HW information */
struct guc_execlist_context {
	u32 context_desc;
	u32 context_id;
	u32 ring_status;
	u32 ring_lcra;
	u32 ring_begin;
	u32 ring_end;
	u32 ring_next_free_location;
	u32 ring_current_tail_pointer_value;
	u8 engine_state_submit_value;
	u8 engine_state_wait_value;
	u16 pagefault_count;
	u16 engine_submit_queue_count;
} __packed;

/*Context descriptor for communicating between uKernel and Driver*/
struct guc_context_desc {
	u32 sched_common_area;
	u32 context_id;
	u32 pas_id;
	u8 engines_used;
	u64 db_trigger_cpu;
	u32 db_trigger_uk;
	u64 db_trigger_phy;
	u16 db_id;

	struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];

	u8 attribute;

	u32 priority;

	u32 wq_sampled_tail_offset;
	u32 wq_total_submit_enqueues;

	u32 process_desc;
	u32 wq_addr;
	u32 wq_size;

	u32 engine_presence;

	u8 engine_suspended;

	u8 reserved0[3];
	u64 reserved1[1];

	u64 desc_private;
} __packed;

#define GUC_FORCEWAKE_RENDER	(1 << 0)
#define GUC_FORCEWAKE_MEDIA	(1 << 1)

#define GUC_POWER_UNSPECIFIED	0
#define GUC_POWER_D0		1
#define GUC_POWER_D1		2
#define GUC_POWER_D2		3
#define GUC_POWER_D3		4

/* Scheduling policy settings */

/* Reset engine upon preempt failure */
#define POLICY_RESET_ENGINE		(1<<0)
/* Preempt to idle on quantum expiry */
#define POLICY_PREEMPT_TO_IDLE		(1<<1)

#define POLICY_MAX_NUM_WI		15

struct guc_policy {
	/* Time for one workload to execute. (in micro seconds) */
	u32 execution_quantum;
	u32 reserved1;

	/* Time to wait for a preemption request to completed before issuing a
	 * reset. (in micro seconds). */
	u32 preemption_time;

	/* How much time to allow to run after the first fault is observed.
	 * Then preempt afterwards. (in micro seconds) */
	u32 fault_time;

	u32 policy_flags;
	u32 reserved[2];
} __packed;

struct guc_policies {
	struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];

	/* In micro seconds. How much time to allow before DPC processing is
	 * called back via interrupt (to prevent DPC queue drain starving).
	 * Typically 1000s of micro seconds (example only, not granularity). */
	u32 dpc_promote_time;

	/* Must be set to take these new values. */
	u32 is_valid;

	/* Max number of WIs to process per call. A large value may keep CS
	 * idle. */
	u32 max_num_work_items;

	u32 reserved[19];
} __packed;

/* GuC MMIO reg state struct */

#define GUC_REGSET_FLAGS_NONE		0x0
#define GUC_REGSET_POWERCYCLE		0x1
#define GUC_REGSET_MASKED		0x2
#define GUC_REGSET_ENGINERESET		0x4
#define GUC_REGSET_SAVE_DEFAULT_VALUE	0x8
#define GUC_REGSET_SAVE_CURRENT_VALUE	0x10

#define GUC_REGSET_MAX_REGISTERS	25
#define GUC_MMIO_WHITE_LIST_START	0x24d0
#define GUC_MMIO_WHITE_LIST_MAX		12
#define GUC_S3_SAVE_SPACE_PAGES		10

struct guc_mmio_regset {
	struct __packed {
		u32 offset;
		u32 value;
		u32 flags;
	} registers[GUC_REGSET_MAX_REGISTERS];

	u32 values_valid;
	u32 number_of_registers;
} __packed;

struct guc_mmio_reg_state {
	struct guc_mmio_regset global_reg;
	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];

	/* MMIO registers that are set as non privileged */
	struct __packed {
		u32 mmio_start;
		u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
		u32 count;
	} mmio_white_list[GUC_MAX_ENGINES_NUM];
} __packed;

/* GuC Additional Data Struct */

struct guc_ads {
	u32 reg_state_addr;
	u32 reg_state_buffer;
	u32 golden_context_lrca;
	u32 scheduler_policies;
	u32 reserved0[3];
	u32 eng_state_size[GUC_MAX_ENGINES_NUM];
	u32 reserved2[4];
} __packed;

/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
enum host2guc_action {
	HOST2GUC_ACTION_DEFAULT = 0x0,
	HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
	HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
	HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
	HOST2GUC_ACTION_LIMIT
};

/*
 * The GuC sends its response to a command by overwriting the
 * command in SS0. The response is distinguishable from a command
 * by the fact that all the MASK bits are set. The remaining bits
 * give more detail.
 */
#define	GUC2HOST_RESPONSE_MASK		((u32)0xF0000000)
#define	GUC2HOST_IS_RESPONSE(x) 	((u32)(x) >= GUC2HOST_RESPONSE_MASK)
#define	GUC2HOST_STATUS(x)		(GUC2HOST_RESPONSE_MASK | (x))

/* GUC will return status back to SOFT_SCRATCH_O_REG */
enum guc2host_status {
	GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
	GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
	GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
	GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
};

#endif
Commit	Line	Data
2617268f DG	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23	#ifndef _INTEL_GUC_FWIF_H
	24	#define _INTEL_GUC_FWIF_H
	25
	26	/*
	27	* This file is partially autogenerated, although currently with some manual
	28	* fixups afterwards. In future, it should be entirely autogenerated, in order
	29	* to ensure that the definitions herein remain in sync with those used by the
	30	* GuC's own firmware.
	31	*
	32	* EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST.
	33	*/
	34
2617268f	35	#define GFXCORE_FAMILY_GEN9 12
33a732f4	36	#define GFXCORE_FAMILY_UNKNOWN 0x7fffffff
2617268f	37
44a28b1d	38	#define GUC_CTX_PRIORITY_KMD_HIGH 0
2617268f	39	#define GUC_CTX_PRIORITY_HIGH 1
44a28b1d DG	40	#define GUC_CTX_PRIORITY_KMD_NORMAL 2
44a28b1d DG	41	#define GUC_CTX_PRIORITY_NORMAL 3
463704d0	42	#define GUC_CTX_PRIORITY_NUM 4
2617268f DG	43
2617268f DG	44	#define GUC_MAX_GPU_CONTEXTS 1024
aa557ab0	45	#define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS
2617268f	46
397097b0 AD	47	#define GUC_RENDER_ENGINE 0
	48	#define GUC_VIDEO_ENGINE 1
	49	#define GUC_BLITTER_ENGINE 2
	50	#define GUC_VIDEOENHANCE_ENGINE 3
	51	#define GUC_VIDEO_ENGINE2 4
	52	#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
	53
2617268f DG	54	/* Work queue item header definitions */
	55	#define WQ_STATUS_ACTIVE 1
	56	#define WQ_STATUS_SUSPENDED 2
	57	#define WQ_STATUS_CMD_ERROR 3
	58	#define WQ_STATUS_ENGINE_ID_NOT_USED 4
	59	#define WQ_STATUS_SUSPENDED_FROM_RESET 5
	60	#define WQ_TYPE_SHIFT 0
	61	#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
	62	#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
	63	#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
	64	#define WQ_TARGET_SHIFT 10
	65	#define WQ_LEN_SHIFT 16
	66	#define WQ_NO_WCFLUSH_WAIT (1 << 27)
	67	#define WQ_PRESENT_WORKLOAD (1 << 28)
	68	#define WQ_WORKLOAD_SHIFT 29
	69	#define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT)
	70	#define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT)
	71	#define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT)
	72
	73	#define WQ_RING_TAIL_SHIFT 20
0a31afbc DG	74	#define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
0a31afbc DG	75	#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
2617268f DG	76
	77	#define GUC_DOORBELL_ENABLED 1
	78	#define GUC_DOORBELL_DISABLED 0
	79
	80	#define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0)
	81	#define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1)
	82	#define GUC_CTX_DESC_ATTR_KERNEL (1 << 2)
	83	#define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3)
	84	#define GUC_CTX_DESC_ATTR_RESET (1 << 4)
	85	#define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5)
	86	#define GUC_CTX_DESC_ATTR_PCH (1 << 6)
aa557ab0	87	#define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7)
2617268f DG	88
	89	/* The guc control data is 10 DWORDs */
	90	#define GUC_CTL_CTXINFO 0
	91	#define GUC_CTL_CTXNUM_IN16_SHIFT 0
	92	#define GUC_CTL_BASE_ADDR_SHIFT 12
68371a95	93
2617268f DG	94	#define GUC_CTL_ARAT_HIGH 1
2617268f DG	95	#define GUC_CTL_ARAT_LOW 2
68371a95	96
2617268f DG	97	#define GUC_CTL_DEVICE_INFO 3
	98	#define GUC_CTL_GTTYPE_SHIFT 0
	99	#define GUC_CTL_COREFAMILY_SHIFT 7
68371a95	100
2617268f DG	101	#define GUC_CTL_LOG_PARAMS 4
	102	#define GUC_LOG_VALID (1 << 0)
	103	#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
	104	#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
	105	#define GUC_LOG_CRASH_PAGES 1
	106	#define GUC_LOG_CRASH_SHIFT 4
	107	#define GUC_LOG_DPC_PAGES 3
	108	#define GUC_LOG_DPC_SHIFT 6
	109	#define GUC_LOG_ISR_PAGES 3
	110	#define GUC_LOG_ISR_SHIFT 9
	111	#define GUC_LOG_BUF_ADDR_SHIFT 12
68371a95	112
2617268f	113	#define GUC_CTL_PAGE_FAULT_CONTROL 5
68371a95	114
2617268f DG	115	#define GUC_CTL_WA 6
2617268f DG	116	#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
68371a95	117
2617268f DG	118	#define GUC_CTL_FEATURE 7
	119	#define GUC_CTL_VCS2_ENABLED (1 << 0)
	120	#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
	121	#define GUC_CTL_FEATURE2 (1 << 2)
	122	#define GUC_CTL_POWER_GATING (1 << 3)
	123	#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
	124	#define GUC_CTL_PREEMPTION_LOG (1 << 5)
	125	#define GUC_CTL_ENABLE_SLPC (1 << 7)
aa557ab0	126	#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
68371a95	127
2617268f DG	128	#define GUC_CTL_DEBUG 8
	129	#define GUC_LOG_VERBOSITY_SHIFT 0
	130	#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
	131	#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
	132	#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
	133	#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
	134	/* Verbosity range-check limits, without the shift */
	135	#define GUC_LOG_VERBOSITY_MIN 0
	136	#define GUC_LOG_VERBOSITY_MAX 3
68371a95 AD	137	#define GUC_LOG_VERBOSITY_MASK 0x0000000f
	138	#define GUC_LOG_DESTINATION_MASK (3 << 4)
	139	#define GUC_LOG_DISABLED (1 << 6)
	140	#define GUC_PROFILE_ENABLED (1 << 7)
	141	#define GUC_WQ_TRACK_ENABLED (1 << 8)
	142	#define GUC_ADS_ENABLED (1 << 9)
	143	#define GUC_DEBUG_RESERVED (1 << 10)
	144	#define GUC_ADS_ADDR_SHIFT 11
	145	#define GUC_ADS_ADDR_MASK 0xfffff800
	146
aa557ab0	147	#define GUC_CTL_RSRVD 9
2617268f	148
68371a95	149	#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
2617268f	150
feda33ef AD	151	/**
	152	* DOC: GuC Firmware Layout
	153	*
	154	* The GuC firmware layout looks like this:
	155	*
	156	* +-------------------------------+
	157	* \| guc_css_header \|
62cacc79	158	* \| \|
feda33ef AD	159	* \| contains major/minor version \|
	160	* +-------------------------------+
	161	* \| uCode \|
	162	* +-------------------------------+
	163	* \| RSA signature \|
	164	* +-------------------------------+
	165	* \| modulus key \|
	166	* +-------------------------------+
	167	* \| exponent val \|
	168	* +-------------------------------+
	169	*
	170	* The firmware may or may not have modulus key and exponent data. The header,
	171	* uCode and RSA signature are must-have components that will be used by driver.
	172	* Length of each components, which is all in dwords, can be found in header.
	173	* In the case that modulus and exponent are not present in fw, a.k.a truncated
	174	* image, the length value still appears in header.
	175	*
	176	* Driver will do some basic fw size validation based on the following rules:
	177	*
	178	* 1. Header, uCode and RSA are must-have components.
	179	* 2. All firmware components, if they present, are in the sequence illustrated
62cacc79	180	* in the layout table above.
feda33ef AD	181	* 3. Length info of each component can be found in header, in dwords.
feda33ef AD	182	* 4. Modulus and exponent key are not required by driver. They may not appear
62cacc79	183	* in fw. So driver will load a truncated firmware in this case.
feda33ef AD	184	*/
	185
	186	struct guc_css_header {
	187	uint32_t module_type;
	188	/* header_size includes all non-uCode bits, including css_header, rsa
	189	* key, modulus key and exponent data. */
	190	uint32_t header_size_dw;
	191	uint32_t header_version;
	192	uint32_t module_id;
	193	uint32_t module_vendor;
	194	union {
	195	struct {
	196	uint8_t day;
	197	uint8_t month;
	198	uint16_t year;
	199	};
	200	uint32_t date;
	201	};
	202	uint32_t size_dw; /* uCode plus header_size_dw */
	203	uint32_t key_size_dw;
	204	uint32_t modulus_size_dw;
	205	uint32_t exponent_size_dw;
	206	union {
	207	struct {
	208	uint8_t hour;
	209	uint8_t min;
	210	uint16_t sec;
	211	};
	212	uint32_t time;
	213	};
	214
	215	char username[8];
	216	char buildnumber[12];
	217	uint32_t device_id;
	218	uint32_t guc_sw_version;
	219	uint32_t prod_preprod_fw;
	220	uint32_t reserved[12];
	221	uint32_t header_info;
	222	} __packed;
	223
2617268f DG	224	struct guc_doorbell_info {
	225	u32 db_status;
	226	u32 cookie;
	227	u32 reserved[14];
	228	} __packed;
	229
	230	union guc_doorbell_qw {
	231	struct {
	232	u32 db_status;
	233	u32 cookie;
	234	};
	235	u64 value_qw;
	236	} __packed;
	237
	238	#define GUC_MAX_DOORBELLS 256
	239	#define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS)
	240
	241	#define GUC_DB_SIZE (PAGE_SIZE)
	242	#define GUC_WQ_SIZE (PAGE_SIZE * 2)
	243
	244	/* Work item for submitting workloads into work queue of GuC. */
	245	struct guc_wq_item {
	246	u32 header;
	247	u32 context_desc;
	248	u32 ring_tail;
	249	u32 fence_id;
	250	} __packed;
	251
	252	struct guc_process_desc {
	253	u32 context_id;
	254	u64 db_base_addr;
	255	u32 head;
	256	u32 tail;
	257	u32 error_offset;
	258	u64 wq_base_addr;
	259	u32 wq_size_bytes;
	260	u32 wq_status;
	261	u32 engine_presence;
	262	u32 priority;
	263	u32 reserved[30];
	264	} __packed;
	265
	266	/* engine id and context id is packed into guc_execlist_context.context_id*/
	267	#define GUC_ELC_CTXID_OFFSET 0
	268	#define GUC_ELC_ENGINE_OFFSET 29
	269
	270	/* The execlist context including software and HW information */
	271	struct guc_execlist_context {
	272	u32 context_desc;
	273	u32 context_id;
	274	u32 ring_status;
	275	u32 ring_lcra;
	276	u32 ring_begin;
	277	u32 ring_end;
	278	u32 ring_next_free_location;
	279	u32 ring_current_tail_pointer_value;
	280	u8 engine_state_submit_value;
	281	u8 engine_state_wait_value;
	282	u16 pagefault_count;
	283	u16 engine_submit_queue_count;
	284	} __packed;
	285
	286	/Context descriptor for communicating between uKernel and Driver/
	287	struct guc_context_desc {
288	u32 sched_common_area;
289	u32 context_id;
290	u32 pas_id;
291	u8 engines_used;
292	u64 db_trigger_cpu;
293	u32 db_trigger_uk;
294	u64 db_trigger_phy;
295	u16 db_id;
296
397097b0	297	struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
2617268f DG	298
	299	u8 attribute;
	300
	301	u32 priority;
	302
	303	u32 wq_sampled_tail_offset;
	304	u32 wq_total_submit_enqueues;
	305
	306	u32 process_desc;
	307	u32 wq_addr;
	308	u32 wq_size;
	309
	310	u32 engine_presence;
	311
aa557ab0 AD	312	u8 engine_suspended;
	313
	314	u8 reserved0[3];
2617268f DG	315	u64 reserved1[1];
	316
	317	u64 desc_private;
	318	} __packed;
	319
93f25318 AD	320	#define GUC_FORCEWAKE_RENDER (1 << 0)
	321	#define GUC_FORCEWAKE_MEDIA (1 << 1)
	322
a1c41994 AD	323	#define GUC_POWER_UNSPECIFIED 0
	324	#define GUC_POWER_D0 1
	325	#define GUC_POWER_D1 2
	326	#define GUC_POWER_D2 3
	327	#define GUC_POWER_D3 4
	328
463704d0 AD	329	/* Scheduling policy settings */
	330
	331	/* Reset engine upon preempt failure */
	332	#define POLICY_RESET_ENGINE (1<<0)
	333	/* Preempt to idle on quantum expiry */
	334	#define POLICY_PREEMPT_TO_IDLE (1<<1)
	335
	336	#define POLICY_MAX_NUM_WI 15
	337
	338	struct guc_policy {
	339	/* Time for one workload to execute. (in micro seconds) */
	340	u32 execution_quantum;
	341	u32 reserved1;
	342
	343	/* Time to wait for a preemption request to completed before issuing a
	344	* reset. (in micro seconds). */
	345	u32 preemption_time;
	346
	347	/* How much time to allow to run after the first fault is observed.
	348	* Then preempt afterwards. (in micro seconds) */
	349	u32 fault_time;
	350
	351	u32 policy_flags;
	352	u32 reserved[2];
	353	} __packed;
	354
	355	struct guc_policies {
397097b0	356	struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
463704d0 AD	357
	358	/* In micro seconds. How much time to allow before DPC processing is
	359	* called back via interrupt (to prevent DPC queue drain starving).
	360	* Typically 1000s of micro seconds (example only, not granularity). */
	361	u32 dpc_promote_time;
	362
	363	/* Must be set to take these new values. */
	364	u32 is_valid;
	365
	366	/* Max number of WIs to process per call. A large value may keep CS
	367	* idle. */
	368	u32 max_num_work_items;
	369
	370	u32 reserved[19];
	371	} __packed;
	372
5c148e04 AD	373	/* GuC MMIO reg state struct */
	374
	375	#define GUC_REGSET_FLAGS_NONE 0x0
	376	#define GUC_REGSET_POWERCYCLE 0x1
	377	#define GUC_REGSET_MASKED 0x2
	378	#define GUC_REGSET_ENGINERESET 0x4
	379	#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
	380	#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
	381
f3272e7a	382	#define GUC_REGSET_MAX_REGISTERS 25
5c148e04 AD	383	#define GUC_MMIO_WHITE_LIST_START 0x24d0
	384	#define GUC_MMIO_WHITE_LIST_MAX 12
	385	#define GUC_S3_SAVE_SPACE_PAGES 10
	386
	387	struct guc_mmio_regset {
	388	struct __packed {
	389	u32 offset;
	390	u32 value;
	391	u32 flags;
	392	} registers[GUC_REGSET_MAX_REGISTERS];
	393
	394	u32 values_valid;
	395	u32 number_of_registers;
	396	} __packed;
	397
	398	struct guc_mmio_reg_state {
	399	struct guc_mmio_regset global_reg;
397097b0	400	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
5c148e04 AD	401
	402	/* MMIO registers that are set as non privileged */
	403	struct __packed {
	404	u32 mmio_start;
	405	u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
	406	u32 count;
397097b0	407	} mmio_white_list[GUC_MAX_ENGINES_NUM];
5c148e04 AD	408	} __packed;
5c148e04 AD	409
68371a95 AD	410	/* GuC Additional Data Struct */
	411
	412	struct guc_ads {
	413	u32 reg_state_addr;
	414	u32 reg_state_buffer;
	415	u32 golden_context_lrca;
	416	u32 scheduler_policies;
	417	u32 reserved0[3];
397097b0	418	u32 eng_state_size[GUC_MAX_ENGINES_NUM];
68371a95 AD	419	u32 reserved2[4];
	420	} __packed;
	421
2617268f DG	422	/* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
	423	enum host2guc_action {
	424	HOST2GUC_ACTION_DEFAULT = 0x0,
	425	HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
	426	HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
	427	HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
a1c41994 AD	428	HOST2GUC_ACTION_ENTER_S_STATE = 0x501,
a1c41994 AD	429	HOST2GUC_ACTION_EXIT_S_STATE = 0x502,
2617268f DG	430	HOST2GUC_ACTION_SLPC_REQUEST = 0x3003,
	431	HOST2GUC_ACTION_LIMIT
	432	};
	433
	434	/*
	435	* The GuC sends its response to a command by overwriting the
	436	* command in SS0. The response is distinguishable from a command
	437	* by the fact that all the MASK bits are set. The remaining bits
	438	* give more detail.
	439	*/
	440	#define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000)
	441	#define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK)
	442	#define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK \| (x))
	443
	444	/* GUC will return status back to SOFT_SCRATCH_O_REG */
	445	enum guc2host_status {
	446	GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0),
	447	GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10),
	448	GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20),
	449	GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000)
	450	};
	451
	452	#endif