Merge remote-tracking branch 'mmc-uh/next'
authorStephen Rothwell <sfr@canb.auug.org.au>
Tue, 13 Sep 2016 01:16:19 +0000 (11:16 +1000)
committerStephen Rothwell <sfr@canb.auug.org.au>
Tue, 13 Sep 2016 01:16:19 +0000 (11:16 +1000)
1  2 
arch/arm/boot/dts/sun6i-a31.dtsi
arch/arm/boot/dts/sun8i-a23-a33.dtsi
arch/arm/boot/dts/sun8i-h3.dtsi

index 6a84fe7e9ab267c2eb9a5df4280d373c850aa659,0d24f107ede0ba127dae0d1b27206fa523bb192e..ce1960453a0bb96bda88162a50e4826a0fdfb172
                };
  
                mmc0: mmc@01c0f000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
 -                      clocks = <&ahb1_gates 8>,
 -                               <&mmc0_clk 0>,
 -                               <&mmc0_clk 1>,
 -                               <&mmc0_clk 2>;
 +                      clocks = <&ccu CLK_AHB1_MMC0>,
 +                               <&ccu CLK_MMC0>,
 +                               <&ccu CLK_MMC0_OUTPUT>,
 +                               <&ccu CLK_MMC0_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc1: mmc@01c10000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
 -                      clocks = <&ahb1_gates 9>,
 -                               <&mmc1_clk 0>,
 -                               <&mmc1_clk 1>,
 -                               <&mmc1_clk 2>;
 +                      clocks = <&ccu CLK_AHB1_MMC1>,
 +                               <&ccu CLK_MMC1>,
 +                               <&ccu CLK_MMC1_OUTPUT>,
 +                               <&ccu CLK_MMC1_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc2: mmc@01c11000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
 -                      clocks = <&ahb1_gates 10>,
 -                               <&mmc2_clk 0>,
 -                               <&mmc2_clk 1>,
 -                               <&mmc2_clk 2>;
 +                      clocks = <&ccu CLK_AHB1_MMC2>,
 +                               <&ccu CLK_MMC2>,
 +                               <&ccu CLK_MMC2_OUTPUT>,
 +                               <&ccu CLK_MMC2_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc3: mmc@01c12000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c12000 0x1000>;
 -                      clocks = <&ahb1_gates 11>,
 -                               <&mmc3_clk 0>,
 -                               <&mmc3_clk 1>,
 -                               <&mmc3_clk 2>;
 +                      clocks = <&ccu CLK_AHB1_MMC3>,
 +                               <&ccu CLK_MMC3>,
 +                               <&ccu CLK_MMC3_OUTPUT>,
 +                               <&ccu CLK_MMC3_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
index 01d8bbf08749e3f5ae3294fa18e0327e61e2fbfe,e3b196e08ccf575d4c4c1bbd858874b3d6c0a225..09204317535f9dbc63b69c339ffa00ce328da5b3
                };
  
                mmc0: mmc@01c0f000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c0f000 0x1000>;
 -                      clocks = <&ahb1_gates 8>,
 -                               <&mmc0_clk 0>,
 -                               <&mmc0_clk 1>,
 -                               <&mmc0_clk 2>;
 +                      clocks = <&ccu CLK_BUS_MMC0>,
 +                               <&ccu CLK_MMC0>,
 +                               <&ccu CLK_MMC0_OUTPUT>,
 +                               <&ccu CLK_MMC0_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc1: mmc@01c10000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c10000 0x1000>;
 -                      clocks = <&ahb1_gates 9>,
 -                               <&mmc1_clk 0>,
 -                               <&mmc1_clk 1>,
 -                               <&mmc1_clk 2>;
 +                      clocks = <&ccu CLK_BUS_MMC1>,
 +                               <&ccu CLK_MMC1>,
 +                               <&ccu CLK_MMC1_OUTPUT>,
 +                               <&ccu CLK_MMC1_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
                };
  
                mmc2: mmc@01c11000 {
-                       compatible = "allwinner,sun5i-a13-mmc";
+                       compatible = "allwinner,sun7i-a20-mmc";
                        reg = <0x01c11000 0x1000>;
 -                      clocks = <&ahb1_gates 10>,
 -                               <&mmc2_clk 0>,
 -                               <&mmc2_clk 1>,
 -                               <&mmc2_clk 2>;
 +                      clocks = <&ccu CLK_BUS_MMC2>,
 +                               <&ccu CLK_MMC2>,
 +                               <&ccu CLK_MMC2_OUTPUT>,
 +                               <&ccu CLK_MMC2_SAMPLE>;
                        clock-names = "ahb",
                                      "mmc",
                                      "output",
Simple merge
This page took 0.030935 seconds and 5 git commands to generate.