Commit | Line | Data |
---|---|---|
4bf8e196 LP |
1 | /* |
2 | * rcar_du_crtc.c -- R-Car Display Unit CRTCs | |
3 | * | |
2427b303 | 4 | * Copyright (C) 2013-2015 Renesas Electronics Corporation |
4bf8e196 LP |
5 | * |
6 | * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/mutex.h> | |
16 | ||
17 | #include <drm/drmP.h> | |
3e8da87d LP |
18 | #include <drm/drm_atomic.h> |
19 | #include <drm/drm_atomic_helper.h> | |
4bf8e196 LP |
20 | #include <drm/drm_crtc.h> |
21 | #include <drm/drm_crtc_helper.h> | |
22 | #include <drm/drm_fb_cma_helper.h> | |
23 | #include <drm/drm_gem_cma_helper.h> | |
3cb9ae4f | 24 | #include <drm/drm_plane_helper.h> |
4bf8e196 LP |
25 | |
26 | #include "rcar_du_crtc.h" | |
27 | #include "rcar_du_drv.h" | |
28 | #include "rcar_du_kms.h" | |
4bf8e196 LP |
29 | #include "rcar_du_plane.h" |
30 | #include "rcar_du_regs.h" | |
6d62ef3a | 31 | #include "rcar_du_vsp.h" |
4bf8e196 | 32 | |
4bf8e196 LP |
33 | static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg) |
34 | { | |
cb2025d2 | 35 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
36 | |
37 | return rcar_du_read(rcdu, rcrtc->mmio_offset + reg); | |
38 | } | |
39 | ||
40 | static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data) | |
41 | { | |
cb2025d2 | 42 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
43 | |
44 | rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data); | |
45 | } | |
46 | ||
47 | static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) | |
48 | { | |
cb2025d2 | 49 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
50 | |
51 | rcar_du_write(rcdu, rcrtc->mmio_offset + reg, | |
52 | rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); | |
53 | } | |
54 | ||
55 | static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set) | |
56 | { | |
cb2025d2 | 57 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
58 | |
59 | rcar_du_write(rcdu, rcrtc->mmio_offset + reg, | |
60 | rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set); | |
61 | } | |
62 | ||
63 | static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg, | |
64 | u32 clr, u32 set) | |
65 | { | |
cb2025d2 | 66 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
67 | u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg); |
68 | ||
69 | rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set); | |
70 | } | |
71 | ||
f66ee304 LP |
72 | static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc) |
73 | { | |
f66ee304 LP |
74 | int ret; |
75 | ||
76 | ret = clk_prepare_enable(rcrtc->clock); | |
77 | if (ret < 0) | |
78 | return ret; | |
79 | ||
1b30dbde LP |
80 | ret = clk_prepare_enable(rcrtc->extclock); |
81 | if (ret < 0) | |
82 | goto error_clock; | |
83 | ||
cb2025d2 | 84 | ret = rcar_du_group_get(rcrtc->group); |
f66ee304 | 85 | if (ret < 0) |
1b30dbde LP |
86 | goto error_group; |
87 | ||
88 | return 0; | |
f66ee304 | 89 | |
1b30dbde LP |
90 | error_group: |
91 | clk_disable_unprepare(rcrtc->extclock); | |
92 | error_clock: | |
93 | clk_disable_unprepare(rcrtc->clock); | |
f66ee304 LP |
94 | return ret; |
95 | } | |
96 | ||
97 | static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc) | |
98 | { | |
cb2025d2 | 99 | rcar_du_group_put(rcrtc->group); |
1b30dbde LP |
100 | |
101 | clk_disable_unprepare(rcrtc->extclock); | |
f66ee304 LP |
102 | clk_disable_unprepare(rcrtc->clock); |
103 | } | |
104 | ||
17f6b8a0 LP |
105 | /* ----------------------------------------------------------------------------- |
106 | * Hardware Setup | |
107 | */ | |
108 | ||
4bf8e196 LP |
109 | static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) |
110 | { | |
845f4635 | 111 | const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; |
1b30dbde | 112 | unsigned long mode_clock = mode->clock * 1000; |
4bf8e196 LP |
113 | unsigned long clk; |
114 | u32 value; | |
1b30dbde | 115 | u32 escr; |
4bf8e196 LP |
116 | u32 div; |
117 | ||
1b30dbde LP |
118 | /* Compute the clock divisor and select the internal or external dot |
119 | * clock based on the requested frequency. | |
120 | */ | |
f66ee304 | 121 | clk = clk_get_rate(rcrtc->clock); |
1b30dbde | 122 | div = DIV_ROUND_CLOSEST(clk, mode_clock); |
4bf8e196 | 123 | div = clamp(div, 1U, 64U) - 1; |
1b30dbde LP |
124 | escr = div | ESCR_DCLKSEL_CLKS; |
125 | ||
126 | if (rcrtc->extclock) { | |
127 | unsigned long extclk; | |
128 | unsigned long extrate; | |
129 | unsigned long rate; | |
130 | u32 extdiv; | |
131 | ||
132 | extclk = clk_get_rate(rcrtc->extclock); | |
133 | extdiv = DIV_ROUND_CLOSEST(extclk, mode_clock); | |
134 | extdiv = clamp(extdiv, 1U, 64U) - 1; | |
135 | ||
136 | rate = clk / (div + 1); | |
137 | extrate = extclk / (extdiv + 1); | |
138 | ||
139 | if (abs((long)extrate - (long)mode_clock) < | |
140 | abs((long)rate - (long)mode_clock)) { | |
141 | dev_dbg(rcrtc->group->dev->dev, | |
142 | "crtc%u: using external clock\n", rcrtc->index); | |
143 | escr = extdiv | ESCR_DCLKSEL_DCLKIN; | |
144 | } | |
145 | } | |
4bf8e196 | 146 | |
a5f0ef59 | 147 | rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR, |
1b30dbde | 148 | escr); |
a5f0ef59 | 149 | rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0); |
4bf8e196 LP |
150 | |
151 | /* Signal polarities */ | |
152 | value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL) | |
153 | | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL) | |
d792bc77 | 154 | | DSMR_DIPM_DISP | DSMR_CSPM; |
4bf8e196 LP |
155 | rcar_du_crtc_write(rcrtc, DSMR, value); |
156 | ||
157 | /* Display timings */ | |
158 | rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19); | |
159 | rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start + | |
160 | mode->hdisplay - 19); | |
161 | rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end - | |
162 | mode->hsync_start - 1); | |
163 | rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); | |
164 | ||
906eff7f LP |
165 | rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal - |
166 | mode->crtc_vsync_end - 2); | |
167 | rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal - | |
168 | mode->crtc_vsync_end + | |
169 | mode->crtc_vdisplay - 2); | |
170 | rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal - | |
171 | mode->crtc_vsync_end + | |
172 | mode->crtc_vsync_start - 1); | |
173 | rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); | |
4bf8e196 LP |
174 | |
175 | rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start); | |
176 | rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); | |
177 | } | |
178 | ||
ef67a902 LP |
179 | void rcar_du_crtc_route_output(struct drm_crtc *crtc, |
180 | enum rcar_du_output output) | |
4bf8e196 LP |
181 | { |
182 | struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); | |
ef67a902 | 183 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 LP |
184 | |
185 | /* Store the route from the CRTC output to the DU output. The DU will be | |
186 | * configured when starting the CRTC. | |
187 | */ | |
ef67a902 | 188 | rcrtc->outputs |= BIT(output); |
7cbc05cb | 189 | |
0c1c8776 LP |
190 | /* Store RGB routing to DPAD0, the hardware will be configured when |
191 | * starting the CRTC. | |
192 | */ | |
193 | if (output == RCAR_DU_OUTPUT_DPAD0) | |
7cbc05cb | 194 | rcdu->dpad0_source = rcrtc->index; |
4bf8e196 LP |
195 | } |
196 | ||
4407cc02 LP |
197 | static unsigned int plane_zpos(struct rcar_du_plane *plane) |
198 | { | |
ec69a406 | 199 | return to_rcar_plane_state(plane->plane.state)->zpos; |
4407cc02 LP |
200 | } |
201 | ||
5bfcbce0 LP |
202 | static const struct rcar_du_format_info * |
203 | plane_format(struct rcar_du_plane *plane) | |
204 | { | |
ec69a406 | 205 | return to_rcar_plane_state(plane->plane.state)->format; |
5bfcbce0 LP |
206 | } |
207 | ||
52055baf | 208 | static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) |
4bf8e196 | 209 | { |
4bf8e196 | 210 | struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES]; |
6d62ef3a | 211 | struct rcar_du_device *rcdu = rcrtc->group->dev; |
4bf8e196 | 212 | unsigned int num_planes = 0; |
2a57e9b5 LP |
213 | unsigned int dptsr_planes; |
214 | unsigned int hwplanes = 0; | |
4bf8e196 LP |
215 | unsigned int prio = 0; |
216 | unsigned int i; | |
4bf8e196 LP |
217 | u32 dspr = 0; |
218 | ||
d6aed574 | 219 | for (i = 0; i < rcrtc->group->num_planes; ++i) { |
99caede1 | 220 | struct rcar_du_plane *plane = &rcrtc->group->planes[i]; |
4bf8e196 LP |
221 | unsigned int j; |
222 | ||
47094194 | 223 | if (plane->plane.state->crtc != &rcrtc->crtc) |
4bf8e196 LP |
224 | continue; |
225 | ||
226 | /* Insert the plane in the sorted planes array. */ | |
227 | for (j = num_planes++; j > 0; --j) { | |
4407cc02 | 228 | if (plane_zpos(planes[j-1]) <= plane_zpos(plane)) |
4bf8e196 LP |
229 | break; |
230 | planes[j] = planes[j-1]; | |
231 | } | |
232 | ||
233 | planes[j] = plane; | |
5bfcbce0 | 234 | prio += plane_format(plane)->planes * 4; |
4bf8e196 LP |
235 | } |
236 | ||
237 | for (i = 0; i < num_planes; ++i) { | |
238 | struct rcar_du_plane *plane = planes[i]; | |
5ee5a81d | 239 | struct drm_plane_state *state = plane->plane.state; |
ec69a406 | 240 | unsigned int index = to_rcar_plane_state(state)->hwindex; |
4bf8e196 LP |
241 | |
242 | prio -= 4; | |
243 | dspr |= (index + 1) << prio; | |
2a57e9b5 | 244 | hwplanes |= 1 << index; |
4bf8e196 | 245 | |
5bfcbce0 | 246 | if (plane_format(plane)->planes == 2) { |
4bf8e196 LP |
247 | index = (index + 1) % 8; |
248 | ||
249 | prio -= 4; | |
250 | dspr |= (index + 1) << prio; | |
2a57e9b5 | 251 | hwplanes |= 1 << index; |
4bf8e196 LP |
252 | } |
253 | } | |
254 | ||
6d62ef3a LP |
255 | /* If VSP+DU integration is enabled the plane assignment is fixed. */ |
256 | if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) { | |
2427b303 LP |
257 | if (rcdu->info->gen < 3) { |
258 | dspr = (rcrtc->index % 2) + 1; | |
259 | hwplanes = 1 << (rcrtc->index % 2); | |
260 | } else { | |
261 | dspr = (rcrtc->index % 2) ? 3 : 1; | |
262 | hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0); | |
263 | } | |
6d62ef3a LP |
264 | } |
265 | ||
2a57e9b5 LP |
266 | /* Update the planes to display timing and dot clock generator |
267 | * associations. | |
268 | * | |
269 | * Updating the DPTSR register requires restarting the CRTC group, | |
270 | * resulting in visible flicker. To mitigate the issue only update the | |
271 | * association if needed by enabled planes. Planes being disabled will | |
272 | * keep their current association. | |
4bf8e196 | 273 | */ |
2a57e9b5 LP |
274 | mutex_lock(&rcrtc->group->lock); |
275 | ||
276 | dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes | |
277 | : rcrtc->group->dptsr_planes & ~hwplanes; | |
278 | ||
279 | if (dptsr_planes != rcrtc->group->dptsr_planes) { | |
280 | rcar_du_group_write(rcrtc->group, DPTSR, | |
281 | (dptsr_planes << 16) | dptsr_planes); | |
282 | rcrtc->group->dptsr_planes = dptsr_planes; | |
283 | ||
284 | if (rcrtc->group->used_crtcs) | |
285 | rcar_du_group_restart(rcrtc->group); | |
4bf8e196 LP |
286 | } |
287 | ||
2af03944 LP |
288 | /* Restart the group if plane sources have changed. */ |
289 | if (rcrtc->group->need_restart) | |
290 | rcar_du_group_restart(rcrtc->group); | |
291 | ||
2a57e9b5 LP |
292 | mutex_unlock(&rcrtc->group->lock); |
293 | ||
a5f0ef59 LP |
294 | rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, |
295 | dspr); | |
4bf8e196 LP |
296 | } |
297 | ||
17f6b8a0 LP |
298 | /* ----------------------------------------------------------------------------- |
299 | * Page Flip | |
300 | */ | |
301 | ||
17f6b8a0 LP |
302 | static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc) |
303 | { | |
304 | struct drm_pending_vblank_event *event; | |
305 | struct drm_device *dev = rcrtc->crtc.dev; | |
306 | unsigned long flags; | |
307 | ||
308 | spin_lock_irqsave(&dev->event_lock, flags); | |
309 | event = rcrtc->event; | |
310 | rcrtc->event = NULL; | |
311 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
312 | ||
313 | if (event == NULL) | |
314 | return; | |
315 | ||
316 | spin_lock_irqsave(&dev->event_lock, flags); | |
317 | drm_send_vblank_event(dev, rcrtc->index, event); | |
36693f3c | 318 | wake_up(&rcrtc->flip_wait); |
17f6b8a0 LP |
319 | spin_unlock_irqrestore(&dev->event_lock, flags); |
320 | ||
0cd90a54 | 321 | drm_crtc_vblank_put(&rcrtc->crtc); |
17f6b8a0 LP |
322 | } |
323 | ||
36693f3c LP |
324 | static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc) |
325 | { | |
326 | struct drm_device *dev = rcrtc->crtc.dev; | |
327 | unsigned long flags; | |
328 | bool pending; | |
329 | ||
330 | spin_lock_irqsave(&dev->event_lock, flags); | |
331 | pending = rcrtc->event != NULL; | |
332 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
333 | ||
334 | return pending; | |
335 | } | |
336 | ||
337 | static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc) | |
338 | { | |
339 | struct rcar_du_device *rcdu = rcrtc->group->dev; | |
340 | ||
341 | if (wait_event_timeout(rcrtc->flip_wait, | |
342 | !rcar_du_crtc_page_flip_pending(rcrtc), | |
343 | msecs_to_jiffies(50))) | |
344 | return; | |
345 | ||
346 | dev_warn(rcdu->dev, "page flip timeout\n"); | |
347 | ||
348 | rcar_du_crtc_finish_page_flip(rcrtc); | |
349 | } | |
350 | ||
17f6b8a0 LP |
351 | /* ----------------------------------------------------------------------------- |
352 | * Start/Stop and Suspend/Resume | |
353 | */ | |
354 | ||
4bf8e196 LP |
355 | static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) |
356 | { | |
357 | struct drm_crtc *crtc = &rcrtc->crtc; | |
906eff7f | 358 | bool interlaced; |
4bf8e196 LP |
359 | |
360 | if (rcrtc->started) | |
361 | return; | |
362 | ||
4bf8e196 LP |
363 | /* Set display off and background to black */ |
364 | rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0)); | |
365 | rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0)); | |
366 | ||
367 | /* Configure display timings and output routing */ | |
368 | rcar_du_crtc_set_display_timing(rcrtc); | |
2fd22dba | 369 | rcar_du_group_set_routing(rcrtc->group); |
4bf8e196 | 370 | |
52055baf LP |
371 | /* Start with all planes disabled. */ |
372 | rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); | |
4bf8e196 LP |
373 | |
374 | /* Select master sync mode. This enables display operation in master | |
375 | * sync mode (with the HSYNC and VSYNC signals configured as outputs and | |
376 | * actively driven). | |
377 | */ | |
906eff7f LP |
378 | interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; |
379 | rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK, | |
380 | (interlaced ? DSYSR_SCM_INT_VIDEO : 0) | | |
381 | DSYSR_TVM_MASTER); | |
4bf8e196 | 382 | |
cb2025d2 | 383 | rcar_du_group_start_stop(rcrtc->group, true); |
4bf8e196 | 384 | |
6d62ef3a LP |
385 | /* Enable the VSP compositor. */ |
386 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) | |
387 | rcar_du_vsp_enable(rcrtc); | |
388 | ||
0cd90a54 LP |
389 | /* Turn vertical blanking interrupt reporting back on. */ |
390 | drm_crtc_vblank_on(crtc); | |
391 | ||
4bf8e196 LP |
392 | rcrtc->started = true; |
393 | } | |
394 | ||
395 | static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) | |
396 | { | |
397 | struct drm_crtc *crtc = &rcrtc->crtc; | |
4bf8e196 LP |
398 | |
399 | if (!rcrtc->started) | |
400 | return; | |
401 | ||
911316fe LP |
402 | /* Disable all planes and wait for the change to take effect. This is |
403 | * required as the DSnPR registers are updated on vblank, and no vblank | |
404 | * will occur once the CRTC is stopped. Disabling planes when starting | |
405 | * the CRTC thus wouldn't be enough as it would start scanning out | |
406 | * immediately from old frame buffers until the next vblank. | |
407 | * | |
408 | * This increases the CRTC stop delay, especially when multiple CRTCs | |
409 | * are stopped in one operation as we now wait for one vblank per CRTC. | |
410 | * Whether this can be improved needs to be researched. | |
411 | */ | |
412 | rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); | |
413 | drm_crtc_wait_one_vblank(crtc); | |
414 | ||
0cd90a54 LP |
415 | /* Disable vertical blanking interrupt reporting. We first need to wait |
416 | * for page flip completion before stopping the CRTC as userspace | |
417 | * expects page flips to eventually complete. | |
36693f3c LP |
418 | */ |
419 | rcar_du_crtc_wait_page_flip(rcrtc); | |
0cd90a54 | 420 | drm_crtc_vblank_off(crtc); |
36693f3c | 421 | |
6d62ef3a LP |
422 | /* Disable the VSP compositor. */ |
423 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) | |
424 | rcar_du_vsp_disable(rcrtc); | |
425 | ||
4bf8e196 LP |
426 | /* Select switch sync mode. This stops display operation and configures |
427 | * the HSYNC and VSYNC signals as inputs. | |
428 | */ | |
429 | rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH); | |
430 | ||
cb2025d2 | 431 | rcar_du_group_start_stop(rcrtc->group, false); |
4bf8e196 LP |
432 | |
433 | rcrtc->started = false; | |
434 | } | |
435 | ||
436 | void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc) | |
437 | { | |
6d62ef3a LP |
438 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) |
439 | rcar_du_vsp_disable(rcrtc); | |
440 | ||
4bf8e196 | 441 | rcar_du_crtc_stop(rcrtc); |
f66ee304 | 442 | rcar_du_crtc_put(rcrtc); |
4bf8e196 LP |
443 | } |
444 | ||
445 | void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc) | |
446 | { | |
52055baf LP |
447 | unsigned int i; |
448 | ||
6ea22ab4 | 449 | if (!rcrtc->crtc.state->active) |
4bf8e196 LP |
450 | return; |
451 | ||
f66ee304 | 452 | rcar_du_crtc_get(rcrtc); |
4bf8e196 | 453 | rcar_du_crtc_start(rcrtc); |
52055baf LP |
454 | |
455 | /* Commit the planes state. */ | |
6d62ef3a LP |
456 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) { |
457 | rcar_du_vsp_enable(rcrtc); | |
458 | } else { | |
459 | for (i = 0; i < rcrtc->group->num_planes; ++i) { | |
460 | struct rcar_du_plane *plane = &rcrtc->group->planes[i]; | |
52055baf | 461 | |
6d62ef3a LP |
462 | if (plane->plane.state->crtc != &rcrtc->crtc) |
463 | continue; | |
52055baf | 464 | |
6d62ef3a LP |
465 | rcar_du_plane_setup(plane); |
466 | } | |
52055baf LP |
467 | } |
468 | ||
52055baf | 469 | rcar_du_crtc_update_planes(rcrtc); |
4bf8e196 LP |
470 | } |
471 | ||
17f6b8a0 LP |
472 | /* ----------------------------------------------------------------------------- |
473 | * CRTC Functions | |
474 | */ | |
475 | ||
beff155a | 476 | static void rcar_du_crtc_enable(struct drm_crtc *crtc) |
4bf8e196 | 477 | { |
4bf8e196 LP |
478 | struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); |
479 | ||
beff155a LP |
480 | rcar_du_crtc_get(rcrtc); |
481 | rcar_du_crtc_start(rcrtc); | |
beff155a LP |
482 | } |
483 | ||
484 | static void rcar_du_crtc_disable(struct drm_crtc *crtc) | |
485 | { | |
486 | struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); | |
3dbf11e4 | 487 | |
beff155a LP |
488 | rcar_du_crtc_stop(rcrtc); |
489 | rcar_du_crtc_put(rcrtc); | |
4bf8e196 | 490 | |
cf1cc6f2 | 491 | rcrtc->outputs = 0; |
beff155a LP |
492 | } |
493 | ||
4bf8e196 LP |
494 | static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc, |
495 | const struct drm_display_mode *mode, | |
496 | struct drm_display_mode *adjusted_mode) | |
497 | { | |
498 | /* TODO Fixup modes */ | |
499 | return true; | |
500 | } | |
501 | ||
613d2b27 ML |
502 | static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, |
503 | struct drm_crtc_state *old_crtc_state) | |
920888a2 | 504 | { |
d5746642 | 505 | struct drm_pending_vblank_event *event = crtc->state->event; |
920888a2 | 506 | struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); |
d5746642 LP |
507 | struct drm_device *dev = rcrtc->crtc.dev; |
508 | unsigned long flags; | |
920888a2 | 509 | |
d5746642 | 510 | if (event) { |
d5746642 LP |
511 | WARN_ON(drm_crtc_vblank_get(crtc) != 0); |
512 | ||
513 | spin_lock_irqsave(&dev->event_lock, flags); | |
514 | rcrtc->event = event; | |
515 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
516 | } | |
6d62ef3a LP |
517 | |
518 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) | |
519 | rcar_du_vsp_atomic_begin(rcrtc); | |
920888a2 LP |
520 | } |
521 | ||
613d2b27 ML |
522 | static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc, |
523 | struct drm_crtc_state *old_crtc_state) | |
920888a2 LP |
524 | { |
525 | struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); | |
526 | ||
52055baf | 527 | rcar_du_crtc_update_planes(rcrtc); |
6d62ef3a LP |
528 | |
529 | if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) | |
530 | rcar_du_vsp_atomic_flush(rcrtc); | |
920888a2 LP |
531 | } |
532 | ||
4bf8e196 | 533 | static const struct drm_crtc_helper_funcs crtc_helper_funcs = { |
4bf8e196 | 534 | .mode_fixup = rcar_du_crtc_mode_fixup, |
4bf8e196 | 535 | .disable = rcar_du_crtc_disable, |
beff155a | 536 | .enable = rcar_du_crtc_enable, |
920888a2 LP |
537 | .atomic_begin = rcar_du_crtc_atomic_begin, |
538 | .atomic_flush = rcar_du_crtc_atomic_flush, | |
4bf8e196 LP |
539 | }; |
540 | ||
4bf8e196 | 541 | static const struct drm_crtc_funcs crtc_funcs = { |
3e8da87d | 542 | .reset = drm_atomic_helper_crtc_reset, |
4bf8e196 | 543 | .destroy = drm_crtc_cleanup, |
cf1cc6f2 | 544 | .set_config = drm_atomic_helper_set_config, |
d5746642 | 545 | .page_flip = drm_atomic_helper_page_flip, |
3e8da87d LP |
546 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
547 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
4bf8e196 LP |
548 | }; |
549 | ||
17f6b8a0 LP |
550 | /* ----------------------------------------------------------------------------- |
551 | * Interrupt Handling | |
552 | */ | |
553 | ||
554 | static irqreturn_t rcar_du_crtc_irq(int irq, void *arg) | |
555 | { | |
556 | struct rcar_du_crtc *rcrtc = arg; | |
557 | irqreturn_t ret = IRQ_NONE; | |
558 | u32 status; | |
559 | ||
560 | status = rcar_du_crtc_read(rcrtc, DSSR); | |
561 | rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK); | |
562 | ||
563 | if (status & DSSR_FRM) { | |
564 | drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index); | |
565 | rcar_du_crtc_finish_page_flip(rcrtc); | |
566 | ret = IRQ_HANDLED; | |
567 | } | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
572 | /* ----------------------------------------------------------------------------- | |
573 | * Initialization | |
574 | */ | |
575 | ||
cb2025d2 | 576 | int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index) |
4bf8e196 | 577 | { |
a5f0ef59 | 578 | static const unsigned int mmio_offsets[] = { |
6a8c49fc | 579 | DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET |
a5f0ef59 LP |
580 | }; |
581 | ||
cb2025d2 | 582 | struct rcar_du_device *rcdu = rgrp->dev; |
f66ee304 | 583 | struct platform_device *pdev = to_platform_device(rcdu->dev); |
4bf8e196 LP |
584 | struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index]; |
585 | struct drm_crtc *crtc = &rcrtc->crtc; | |
6d62ef3a | 586 | struct drm_plane *primary; |
f66ee304 | 587 | unsigned int irqflags; |
1b30dbde LP |
588 | struct clk *clk; |
589 | char clk_name[9]; | |
f66ee304 LP |
590 | char *name; |
591 | int irq; | |
4bf8e196 LP |
592 | int ret; |
593 | ||
1b30dbde | 594 | /* Get the CRTC clock and the optional external clock. */ |
f66ee304 LP |
595 | if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { |
596 | sprintf(clk_name, "du.%u", index); | |
597 | name = clk_name; | |
598 | } else { | |
599 | name = NULL; | |
600 | } | |
601 | ||
602 | rcrtc->clock = devm_clk_get(rcdu->dev, name); | |
603 | if (IS_ERR(rcrtc->clock)) { | |
604 | dev_err(rcdu->dev, "no clock for CRTC %u\n", index); | |
605 | return PTR_ERR(rcrtc->clock); | |
606 | } | |
607 | ||
1b30dbde LP |
608 | sprintf(clk_name, "dclkin.%u", index); |
609 | clk = devm_clk_get(rcdu->dev, clk_name); | |
610 | if (!IS_ERR(clk)) { | |
611 | rcrtc->extclock = clk; | |
612 | } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) { | |
613 | dev_info(rcdu->dev, "can't get external clock %u\n", index); | |
614 | return -EPROBE_DEFER; | |
615 | } | |
616 | ||
36693f3c LP |
617 | init_waitqueue_head(&rcrtc->flip_wait); |
618 | ||
cb2025d2 | 619 | rcrtc->group = rgrp; |
a5f0ef59 | 620 | rcrtc->mmio_offset = mmio_offsets[index]; |
4bf8e196 | 621 | rcrtc->index = index; |
4bf8e196 | 622 | |
6d62ef3a LP |
623 | if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) |
624 | primary = &rcrtc->vsp->planes[0].plane; | |
625 | else | |
626 | primary = &rgrp->planes[index % 2].plane; | |
627 | ||
628 | ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, | |
f9882876 | 629 | NULL, &crtc_funcs, NULL); |
4bf8e196 LP |
630 | if (ret < 0) |
631 | return ret; | |
632 | ||
633 | drm_crtc_helper_add(crtc, &crtc_helper_funcs); | |
634 | ||
0cd90a54 LP |
635 | /* Start with vertical blanking interrupt reporting disabled. */ |
636 | drm_crtc_vblank_off(crtc); | |
637 | ||
f66ee304 LP |
638 | /* Register the interrupt handler. */ |
639 | if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { | |
640 | irq = platform_get_irq(pdev, index); | |
641 | irqflags = 0; | |
642 | } else { | |
643 | irq = platform_get_irq(pdev, 0); | |
644 | irqflags = IRQF_SHARED; | |
645 | } | |
646 | ||
647 | if (irq < 0) { | |
648 | dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index); | |
6512f5fb | 649 | return irq; |
f66ee304 LP |
650 | } |
651 | ||
652 | ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags, | |
653 | dev_name(rcdu->dev), rcrtc); | |
654 | if (ret < 0) { | |
655 | dev_err(rcdu->dev, | |
656 | "failed to register IRQ for CRTC %u\n", index); | |
657 | return ret; | |
658 | } | |
659 | ||
4bf8e196 LP |
660 | return 0; |
661 | } | |
662 | ||
663 | void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable) | |
664 | { | |
665 | if (enable) { | |
666 | rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL); | |
667 | rcar_du_crtc_set(rcrtc, DIER, DIER_VBE); | |
668 | } else { | |
669 | rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE); | |
670 | } | |
671 | } |