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Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / drivers / gpu / ipu-v3 / ipu-common.c
CommitLineData
aecfbdb1
SH		 1/*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15#include <linux/module.h>
16#include <linux/export.h>
17#include <linux/types.h>
6c64155d 18#include <linux/reset.h>
aecfbdb1
SH		 19#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/list.h>
27#include <linux/irq.h>
de88cbb7 28#include <linux/irqchip/chained_irq.h>
b728766c 29#include <linux/irqdomain.h>
aecfbdb1 30#include <linux/of_device.h>
304e6be6 31#include <linux/of_graph.h>
aecfbdb1 32
7cb17797
PZ		 33#include <drm/drm_fourcc.h>
34
39b9004d 35#include <video/imx-ipu-v3.h>
aecfbdb1
SH		 36#include "ipu-prv.h"
37
38static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
39{
40 return readl(ipu->cm_reg + offset);
41}
42
43static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
44{
45 writel(value, ipu->cm_reg + offset);
46}
47
572a7615
SL		 48int ipu_get_num(struct ipu_soc *ipu)
49{
50 return ipu->id;
51}
52EXPORT_SYMBOL_GPL(ipu_get_num);
53
aecfbdb1
SH		 54void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
55{
56 u32 val;
57
58 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
59 val |= 0x8;
60 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
61}
62EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
63
7cb17797
PZ		 64enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
65{
66 switch (drm_fourcc) {
0cb8b757
PZ		 67 case DRM_FORMAT_ARGB1555:
68 case DRM_FORMAT_ABGR1555:
69 case DRM_FORMAT_RGBA5551:
70 case DRM_FORMAT_BGRA5551:
7cb17797
PZ		 71 case DRM_FORMAT_RGB565:
72 case DRM_FORMAT_BGR565:
73 case DRM_FORMAT_RGB888:
74 case DRM_FORMAT_BGR888:
7d2e8a20 75 case DRM_FORMAT_ARGB4444:
7cb17797
PZ		 76 case DRM_FORMAT_XRGB8888:
77 case DRM_FORMAT_XBGR8888:
78 case DRM_FORMAT_RGBX8888:
79 case DRM_FORMAT_BGRX8888:
80 case DRM_FORMAT_ARGB8888:
81 case DRM_FORMAT_ABGR8888:
82 case DRM_FORMAT_RGBA8888:
83 case DRM_FORMAT_BGRA8888:
84 return IPUV3_COLORSPACE_RGB;
85 case DRM_FORMAT_YUYV:
86 case DRM_FORMAT_UYVY:
87 case DRM_FORMAT_YUV420:
88 case DRM_FORMAT_YVU420:
9a34cef0
SL		 89 case DRM_FORMAT_YUV422:
90 case DRM_FORMAT_YVU422:
91 case DRM_FORMAT_NV12:
92 case DRM_FORMAT_NV21:
93 case DRM_FORMAT_NV16:
94 case DRM_FORMAT_NV61:
7cb17797
PZ		 95 return IPUV3_COLORSPACE_YUV;
96 default:
97 return IPUV3_COLORSPACE_UNKNOWN;
98 }
99}
100EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
101
aecfbdb1
SH		 102enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
103{
104 switch (pixelformat) {
105 case V4L2_PIX_FMT_YUV420:
d3e4e610 106 case V4L2_PIX_FMT_YVU420:
9a34cef0 107 case V4L2_PIX_FMT_YUV422P:
aecfbdb1 108 case V4L2_PIX_FMT_UYVY:
c096ae13 109 case V4L2_PIX_FMT_YUYV:
9a34cef0
SL		 110 case V4L2_PIX_FMT_NV12:
111 case V4L2_PIX_FMT_NV21:
112 case V4L2_PIX_FMT_NV16:
113 case V4L2_PIX_FMT_NV61:
aecfbdb1
SH		 114 return IPUV3_COLORSPACE_YUV;
115 case V4L2_PIX_FMT_RGB32:
116 case V4L2_PIX_FMT_BGR32:
117 case V4L2_PIX_FMT_RGB24:
118 case V4L2_PIX_FMT_BGR24:
119 case V4L2_PIX_FMT_RGB565:
120 return IPUV3_COLORSPACE_RGB;
121 default:
122 return IPUV3_COLORSPACE_UNKNOWN;
123 }
124}
125EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
126
4cea940d
SL		 127bool ipu_pixelformat_is_planar(u32 pixelformat)
128{
129 switch (pixelformat) {
130 case V4L2_PIX_FMT_YUV420:
131 case V4L2_PIX_FMT_YVU420:
9a34cef0
SL		 132 case V4L2_PIX_FMT_YUV422P:
133 case V4L2_PIX_FMT_NV12:
134 case V4L2_PIX_FMT_NV21:
135 case V4L2_PIX_FMT_NV16:
136 case V4L2_PIX_FMT_NV61:
4cea940d
SL		 137 return true;
138 }
139
140 return false;
141}
142EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
143
ae0e9708
SL		 144enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
145{
146 switch (mbus_code & 0xf000) {
147 case 0x1000:
148 return IPUV3_COLORSPACE_RGB;
149 case 0x2000:
150 return IPUV3_COLORSPACE_YUV;
151 default:
152 return IPUV3_COLORSPACE_UNKNOWN;
153 }
154}
155EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
156
6930afdc
SL		 157int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
158{
159 switch (pixelformat) {
160 case V4L2_PIX_FMT_YUV420:
161 case V4L2_PIX_FMT_YVU420:
9a34cef0
SL		 162 case V4L2_PIX_FMT_YUV422P:
163 case V4L2_PIX_FMT_NV12:
164 case V4L2_PIX_FMT_NV21:
165 case V4L2_PIX_FMT_NV16:
166 case V4L2_PIX_FMT_NV61:
6930afdc
SL		 167 /*
168 * for the planar YUV formats, the stride passed to
169 * cpmem must be the stride in bytes of the Y plane.
170 * And all the planar YUV formats have an 8-bit
171 * Y component.
172 */
173 return (8 * pixel_stride) >> 3;
174 case V4L2_PIX_FMT_RGB565:
175 case V4L2_PIX_FMT_YUYV:
176 case V4L2_PIX_FMT_UYVY:
177 return (16 * pixel_stride) >> 3;
178 case V4L2_PIX_FMT_BGR24:
179 case V4L2_PIX_FMT_RGB24:
180 return (24 * pixel_stride) >> 3;
181 case V4L2_PIX_FMT_BGR32:
182 case V4L2_PIX_FMT_RGB32:
183 return (32 * pixel_stride) >> 3;
184 default:
185 break;
186 }
187
188 return -EINVAL;
189}
190EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
191
f835f386
SL		 192int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
193 bool hflip, bool vflip)
194{
195 u32 r90, vf, hf;
196
197 switch (degrees) {
198 case 0:
199 vf = hf = r90 = 0;
200 break;
201 case 90:
202 vf = hf = 0;
203 r90 = 1;
204 break;
205 case 180:
206 vf = hf = 1;
207 r90 = 0;
208 break;
209 case 270:
210 vf = hf = r90 = 1;
211 break;
212 default:
213 return -EINVAL;
214 }
215
216 hf ^= (u32)hflip;
217 vf ^= (u32)vflip;
218
219 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
220 return 0;
221}
222EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
223
224int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
225 bool hflip, bool vflip)
226{
227 u32 r90, vf, hf;
228
229 r90 = ((u32)mode >> 2) & 0x1;
230 hf = ((u32)mode >> 1) & 0x1;
231 vf = ((u32)mode >> 0) & 0x1;
232 hf ^= (u32)hflip;
233 vf ^= (u32)vflip;
234
235 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
236 case IPU_ROTATE_NONE:
237 *degrees = 0;
238 break;
239 case IPU_ROTATE_90_RIGHT:
240 *degrees = 90;
241 break;
242 case IPU_ROTATE_180:
243 *degrees = 180;
244 break;
245 case IPU_ROTATE_90_LEFT:
246 *degrees = 270;
247 break;
248 default:
249 return -EINVAL;
250 }
251
252 return 0;
253}
254EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
255
aecfbdb1
SH		 256struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
257{
258 struct ipuv3_channel *channel;
259
260 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
261
262 if (num > 63)
263 return ERR_PTR(-ENODEV);
264
265 mutex_lock(&ipu->channel_lock);
266
267 channel = &ipu->channel[num];
268
269 if (channel->busy) {
270 channel = ERR_PTR(-EBUSY);
271 goto out;
272 }
273
89bc5be7 274 channel->busy = true;
aecfbdb1
SH		 275 channel->num = num;
276
277out:
278 mutex_unlock(&ipu->channel_lock);
279
280 return channel;
281}
282EXPORT_SYMBOL_GPL(ipu_idmac_get);
283
284void ipu_idmac_put(struct ipuv3_channel *channel)
285{
286 struct ipu_soc *ipu = channel->ipu;
287
288 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
289
290 mutex_lock(&ipu->channel_lock);
291
89bc5be7 292 channel->busy = false;
aecfbdb1
SH		 293
294 mutex_unlock(&ipu->channel_lock);
295}
296EXPORT_SYMBOL_GPL(ipu_idmac_put);
297
aa52f578 298#define idma_mask(ch) (1 << ((ch) & 0x1f))
aecfbdb1 299
e7268c69
SL		 300/*
301 * This is an undocumented feature, a write one to a channel bit in
302 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
303 * internal current buffer pointer so that transfers start from buffer
304 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
305 * only says these are read-only registers). This operation is required
306 * for channel linking to work correctly, for instance video capture
307 * pipelines that carry out image rotations will fail after the first
308 * streaming unless this function is called for each channel before
309 * re-enabling the channels.
310 */
311static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
312{
313 struct ipu_soc *ipu = channel->ipu;
314 unsigned int chno = channel->num;
315
316 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
317}
318
aecfbdb1
SH		 319void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
320 bool doublebuffer)
321{
322 struct ipu_soc *ipu = channel->ipu;
323 unsigned long flags;
324 u32 reg;
325
326 spin_lock_irqsave(&ipu->lock, flags);
327
328 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
329 if (doublebuffer)
330 reg |= idma_mask(channel->num);
331 else
332 reg &= ~idma_mask(channel->num);
333 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
334
e7268c69
SL		 335 __ipu_idmac_reset_current_buffer(channel);
336
aecfbdb1
SH		 337 spin_unlock_irqrestore(&ipu->lock, flags);
338}
339EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
340
4fd1a07a
SL		 341static const struct {
342 int chnum;
343 u32 reg;
344 int shift;
345} idmac_lock_en_info[] = {
346 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
347 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
348 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
349 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
350 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
351 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
352 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
353 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
354 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
355 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
356 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
357 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
358 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
359 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
360 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
361 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
362 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
363};
364
365int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
366{
367 struct ipu_soc *ipu = channel->ipu;
368 unsigned long flags;
369 u32 bursts, regval;
370 int i;
371
372 switch (num_bursts) {
373 case 0:
374 case 1:
375 bursts = 0x00; /* locking disabled */
376 break;
377 case 2:
378 bursts = 0x01;
379 break;
380 case 4:
381 bursts = 0x02;
382 break;
383 case 8:
384 bursts = 0x03;
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
391 if (channel->num == idmac_lock_en_info[i].chnum)
392 break;
393 }
394 if (i >= ARRAY_SIZE(idmac_lock_en_info))
395 return -EINVAL;
396
397 spin_lock_irqsave(&ipu->lock, flags);
398
399 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
400 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
401 regval |= (bursts << idmac_lock_en_info[i].shift);
402 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
403
404 spin_unlock_irqrestore(&ipu->lock, flags);
405
406 return 0;
407}
408EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
409
aecfbdb1
SH		 410int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
411{
412 unsigned long lock_flags;
413 u32 val;
414
415 spin_lock_irqsave(&ipu->lock, lock_flags);
416
417 val = ipu_cm_read(ipu, IPU_DISP_GEN);
418
419 if (mask & IPU_CONF_DI0_EN)
420 val |= IPU_DI0_COUNTER_RELEASE;
421 if (mask & IPU_CONF_DI1_EN)
422 val |= IPU_DI1_COUNTER_RELEASE;
423
424 ipu_cm_write(ipu, val, IPU_DISP_GEN);
425
426 val = ipu_cm_read(ipu, IPU_CONF);
427 val |= mask;
428 ipu_cm_write(ipu, val, IPU_CONF);
429
430 spin_unlock_irqrestore(&ipu->lock, lock_flags);
431
432 return 0;
433}
434EXPORT_SYMBOL_GPL(ipu_module_enable);
435
436int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
437{
438 unsigned long lock_flags;
439 u32 val;
440
441 spin_lock_irqsave(&ipu->lock, lock_flags);
442
443 val = ipu_cm_read(ipu, IPU_CONF);
444 val &= ~mask;
445 ipu_cm_write(ipu, val, IPU_CONF);
446
447 val = ipu_cm_read(ipu, IPU_DISP_GEN);
448
449 if (mask & IPU_CONF_DI0_EN)
450 val &= ~IPU_DI0_COUNTER_RELEASE;
451 if (mask & IPU_CONF_DI1_EN)
452 val &= ~IPU_DI1_COUNTER_RELEASE;
453
454 ipu_cm_write(ipu, val, IPU_DISP_GEN);
455
456 spin_unlock_irqrestore(&ipu->lock, lock_flags);
457
458 return 0;
459}
460EXPORT_SYMBOL_GPL(ipu_module_disable);
461
e9046097
PZ		 462int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
463{
464 struct ipu_soc *ipu = channel->ipu;
465 unsigned int chno = channel->num;
466
467 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
468}
469EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
470
aa52f578
SL		 471bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
472{
473 struct ipu_soc *ipu = channel->ipu;
474 unsigned long flags;
475 u32 reg = 0;
476
477 spin_lock_irqsave(&ipu->lock, flags);
478 switch (buf_num) {
479 case 0:
480 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
481 break;
482 case 1:
483 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
484 break;
485 case 2:
486 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
487 break;
488 }
489 spin_unlock_irqrestore(&ipu->lock, flags);
490
491 return ((reg & idma_mask(channel->num)) != 0);
492}
493EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
494
aecfbdb1
SH		 495void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
496{
497 struct ipu_soc *ipu = channel->ipu;
498 unsigned int chno = channel->num;
499 unsigned long flags;
500
501 spin_lock_irqsave(&ipu->lock, flags);
502
503 /* Mark buffer as ready. */
504 if (buf_num == 0)
505 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
506 else
507 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
508
509 spin_unlock_irqrestore(&ipu->lock, flags);
510}
511EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
512
bce6f087
SL		 513void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
514{
515 struct ipu_soc *ipu = channel->ipu;
516 unsigned int chno = channel->num;
517 unsigned long flags;
518
519 spin_lock_irqsave(&ipu->lock, flags);
520
521 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
522 switch (buf_num) {
523 case 0:
524 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
525 break;
526 case 1:
527 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
528 break;
529 case 2:
530 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
531 break;
532 default:
533 break;
534 }
535 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
536
537 spin_unlock_irqrestore(&ipu->lock, flags);
538}
539EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
540
aecfbdb1
SH		 541int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
542{
543 struct ipu_soc *ipu = channel->ipu;
544 u32 val;
545 unsigned long flags;
546
547 spin_lock_irqsave(&ipu->lock, flags);
548
549 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
550 val |= idma_mask(channel->num);
551 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
552
553 spin_unlock_irqrestore(&ipu->lock, flags);
554
555 return 0;
556}
557EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
558
17075504
PZ		 559bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
560{
561 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
562}
563EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
564
fb822a39 565int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
aecfbdb1
SH		 566{
567 struct ipu_soc *ipu = channel->ipu;
aecfbdb1
SH		 568 unsigned long timeout;
569
fb822a39 570 timeout = jiffies + msecs_to_jiffies(ms);
aecfbdb1
SH		 571 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
572 idma_mask(channel->num)) {
fb822a39
SH		 573 if (time_after(jiffies, timeout))
574 return -ETIMEDOUT;
aecfbdb1
SH		 575 cpu_relax();
576 }
577
fb822a39
SH		 578 return 0;
579}
580EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
581
17075504
PZ		 582int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
583{
584 unsigned long timeout;
585
586 timeout = jiffies + msecs_to_jiffies(ms);
587 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
588 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
589 if (time_after(jiffies, timeout))
590 return -ETIMEDOUT;
591 cpu_relax();
592 }
593
594 return 0;
595}
596EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
597
fb822a39
SH		 598int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
599{
600 struct ipu_soc *ipu = channel->ipu;
601 u32 val;
602 unsigned long flags;
603
aecfbdb1
SH		 604 spin_lock_irqsave(&ipu->lock, flags);
605
606 /* Disable DMA channel(s) */
607 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
608 val &= ~idma_mask(channel->num);
609 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
610
e7268c69
SL		 611 __ipu_idmac_reset_current_buffer(channel);
612
aecfbdb1
SH		 613 /* Set channel buffers NOT to be ready */
614 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
615
616 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
617 idma_mask(channel->num)) {
618 ipu_cm_write(ipu, idma_mask(channel->num),
619 IPU_CHA_BUF0_RDY(channel->num));
620 }
621
622 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
623 idma_mask(channel->num)) {
624 ipu_cm_write(ipu, idma_mask(channel->num),
625 IPU_CHA_BUF1_RDY(channel->num));
626 }
627
628 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
629
630 /* Reset the double buffer */
631 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
632 val &= ~idma_mask(channel->num);
633 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
634
635 spin_unlock_irqrestore(&ipu->lock, flags);
636
637 return 0;
638}
639EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
640
2bcf577e
SL		 641/*
642 * The imx6 rev. D TRM says that enabling the WM feature will increase
643 * a channel's priority. Refer to Table 36-8 Calculated priority value.
644 * The sub-module that is the sink or source for the channel must enable
645 * watermark signal for this to take effect (SMFC_WM for instance).
646 */
647void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
648{
649 struct ipu_soc *ipu = channel->ipu;
650 unsigned long flags;
651 u32 val;
652
653 spin_lock_irqsave(&ipu->lock, flags);
654
655 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
656 if (enable)
657 val |= 1 << (channel->num % 32);
658 else
659 val &= ~(1 << (channel->num % 32));
660 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
661
662 spin_unlock_irqrestore(&ipu->lock, flags);
663}
664EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
665
6c64155d 666static int ipu_memory_reset(struct ipu_soc *ipu)
aecfbdb1
SH		 667{
668 unsigned long timeout;
669
670 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
671
672 timeout = jiffies + msecs_to_jiffies(1000);
673 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
674 if (time_after(jiffies, timeout))
675 return -ETIME;
676 cpu_relax();
677 }
678
aecfbdb1
SH		 679 return 0;
680}
681
ba07975f
SL		 682/*
683 * Set the source mux for the given CSI. Selects either parallel or
684 * MIPI CSI2 sources.
685 */
686void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
687{
688 unsigned long flags;
689 u32 val, mask;
690
691 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
692 IPU_CONF_CSI0_DATA_SOURCE;
693
694 spin_lock_irqsave(&ipu->lock, flags);
695
696 val = ipu_cm_read(ipu, IPU_CONF);
697 if (mipi_csi2)
698 val |= mask;
699 else
700 val &= ~mask;
701 ipu_cm_write(ipu, val, IPU_CONF);
702
703 spin_unlock_irqrestore(&ipu->lock, flags);
704}
705EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
706
707/*
708 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
709 */
710void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
711{
712 unsigned long flags;
713 u32 val;
714
715 spin_lock_irqsave(&ipu->lock, flags);
716
717 val = ipu_cm_read(ipu, IPU_CONF);
718 if (vdi) {
719 val |= IPU_CONF_IC_INPUT;
720 } else {
721 val &= ~IPU_CONF_IC_INPUT;
722 if (csi_id == 1)
723 val |= IPU_CONF_CSI_SEL;
724 else
725 val &= ~IPU_CONF_CSI_SEL;
726 }
727 ipu_cm_write(ipu, val, IPU_CONF);
728
729 spin_unlock_irqrestore(&ipu->lock, flags);
730}
731EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
732
aecfbdb1
SH		 733struct ipu_devtype {
734 const char *name;
735 unsigned long cm_ofs;
736 unsigned long cpmem_ofs;
737 unsigned long srm_ofs;
738 unsigned long tpm_ofs;
2ffd48f2
SL		 739 unsigned long csi0_ofs;
740 unsigned long csi1_ofs;
1aa8ea0d 741 unsigned long ic_ofs;
aecfbdb1
SH		 742 unsigned long disp0_ofs;
743 unsigned long disp1_ofs;
744 unsigned long dc_tmpl_ofs;
745 unsigned long vdi_ofs;
746 enum ipuv3_type type;
747};
748
749static struct ipu_devtype ipu_type_imx51 = {
750 .name = "IPUv3EX",
751 .cm_ofs = 0x1e000000,
752 .cpmem_ofs = 0x1f000000,
753 .srm_ofs = 0x1f040000,
754 .tpm_ofs = 0x1f060000,
2ffd48f2
SL		 755 .csi0_ofs = 0x1f030000,
756 .csi1_ofs = 0x1f038000,
a49e7c0d 757 .ic_ofs = 0x1e020000,
aecfbdb1
SH		 758 .disp0_ofs = 0x1e040000,
759 .disp1_ofs = 0x1e048000,
760 .dc_tmpl_ofs = 0x1f080000,
761 .vdi_ofs = 0x1e068000,
762 .type = IPUV3EX,
763};
764
765static struct ipu_devtype ipu_type_imx53 = {
766 .name = "IPUv3M",
767 .cm_ofs = 0x06000000,
768 .cpmem_ofs = 0x07000000,
769 .srm_ofs = 0x07040000,
770 .tpm_ofs = 0x07060000,
2ffd48f2
SL		 771 .csi0_ofs = 0x07030000,
772 .csi1_ofs = 0x07038000,
a49e7c0d 773 .ic_ofs = 0x06020000,
aecfbdb1
SH		 774 .disp0_ofs = 0x06040000,
775 .disp1_ofs = 0x06048000,
776 .dc_tmpl_ofs = 0x07080000,
777 .vdi_ofs = 0x06068000,
778 .type = IPUV3M,
779};
780
781static struct ipu_devtype ipu_type_imx6q = {
782 .name = "IPUv3H",
783 .cm_ofs = 0x00200000,
784 .cpmem_ofs = 0x00300000,
785 .srm_ofs = 0x00340000,
786 .tpm_ofs = 0x00360000,
2ffd48f2
SL		 787 .csi0_ofs = 0x00230000,
788 .csi1_ofs = 0x00238000,
1aa8ea0d 789 .ic_ofs = 0x00220000,
aecfbdb1
SH		 790 .disp0_ofs = 0x00240000,
791 .disp1_ofs = 0x00248000,
792 .dc_tmpl_ofs = 0x00380000,
793 .vdi_ofs = 0x00268000,
794 .type = IPUV3H,
795};
796
797static const struct of_device_id imx_ipu_dt_ids[] = {
798 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
799 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
800 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
801 { /* sentinel */ }
802};
803MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
804
805static int ipu_submodules_init(struct ipu_soc *ipu,
806 struct platform_device *pdev, unsigned long ipu_base,
807 struct clk *ipu_clk)
808{
809 char *unit;
810 int ret;
811 struct device *dev = &pdev->dev;
812 const struct ipu_devtype *devtype = ipu->devtype;
813
7d2691da
SL		 814 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
815 if (ret) {
816 unit = "cpmem";
817 goto err_cpmem;
818 }
819
2ffd48f2
SL		 820 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
821 IPU_CONF_CSI0_EN, ipu_clk);
822 if (ret) {
823 unit = "csi0";
824 goto err_csi_0;
825 }
826
827 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
828 IPU_CONF_CSI1_EN, ipu_clk);
829 if (ret) {
830 unit = "csi1";
831 goto err_csi_1;
832 }
833
1aa8ea0d
SL		 834 ret = ipu_ic_init(ipu, dev,
835 ipu_base + devtype->ic_ofs,
836 ipu_base + devtype->tpm_ofs);
837 if (ret) {
838 unit = "ic";
839 goto err_ic;
840 }
841
aecfbdb1 842 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
1aa8ea0d 843 IPU_CONF_DI0_EN, ipu_clk);
aecfbdb1
SH		 844 if (ret) {
845 unit = "di0";
846 goto err_di_0;
847 }
848
849 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
850 IPU_CONF_DI1_EN, ipu_clk);
851 if (ret) {
852 unit = "di1";
853 goto err_di_1;
854 }
855
856 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
857 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
858 if (ret) {
859 unit = "dc_template";
860 goto err_dc;
861 }
862
863 ret = ipu_dmfc_init(ipu, dev, ipu_base +
864 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
865 if (ret) {
866 unit = "dmfc";
867 goto err_dmfc;
868 }
869
870 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
871 if (ret) {
872 unit = "dp";
873 goto err_dp;
874 }
875
35de925f
PZ		 876 ret = ipu_smfc_init(ipu, dev, ipu_base +
877 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
878 if (ret) {
879 unit = "smfc";
880 goto err_smfc;
881 }
882
aecfbdb1
SH		 883 return 0;
884
35de925f
PZ		 885err_smfc:
886 ipu_dp_exit(ipu);
aecfbdb1
SH		 887err_dp:
888 ipu_dmfc_exit(ipu);
889err_dmfc:
890 ipu_dc_exit(ipu);
891err_dc:
892 ipu_di_exit(ipu, 1);
893err_di_1:
894 ipu_di_exit(ipu, 0);
895err_di_0:
1aa8ea0d
SL		 896 ipu_ic_exit(ipu);
897err_ic:
2ffd48f2
SL		 898 ipu_csi_exit(ipu, 1);
899err_csi_1:
900 ipu_csi_exit(ipu, 0);
901err_csi_0:
7d2691da
SL		 902 ipu_cpmem_exit(ipu);
903err_cpmem:
aecfbdb1
SH		 904 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
905 return ret;
906}
907
908static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
909{
910 unsigned long status;
b728766c 911 int i, bit, irq;
aecfbdb1
SH		 912
913 for (i = 0; i < num_regs; i++) {
914
915 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
916 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
917
b728766c 918 for_each_set_bit(bit, &status, 32) {
838201aa
ASC		 919 irq = irq_linear_revmap(ipu->domain,
920 regs[i] * 32 + bit);
b728766c
PZ		 921 if (irq)
922 generic_handle_irq(irq);
923 }
aecfbdb1
SH		 924 }
925}
926
bd0b9ac4 927static void ipu_irq_handler(struct irq_desc *desc)
aecfbdb1
SH		 928{
929 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
4d9efdfc 930 struct irq_chip *chip = irq_desc_get_chip(desc);
aecfbdb1 931 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
aecfbdb1
SH		 932
933 chained_irq_enter(chip, desc);
934
935 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
936
937 chained_irq_exit(chip, desc);
938}
939
bd0b9ac4 940static void ipu_err_irq_handler(struct irq_desc *desc)
aecfbdb1
SH		 941{
942 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
4d9efdfc 943 struct irq_chip *chip = irq_desc_get_chip(desc);
aecfbdb1 944 const int int_reg[] = { 4, 5, 8, 9};
aecfbdb1
SH		 945
946 chained_irq_enter(chip, desc);
947
948 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
949
950 chained_irq_exit(chip, desc);
951}
952
861a50c1 953int ipu_map_irq(struct ipu_soc *ipu, int irq)
aecfbdb1 954{
861a50c1 955 int virq;
b728766c 956
861a50c1
PZ		 957 virq = irq_linear_revmap(ipu->domain, irq);
958 if (!virq)
959 virq = irq_create_mapping(ipu->domain, irq);
b728766c 960
861a50c1
PZ		 961 return virq;
962}
963EXPORT_SYMBOL_GPL(ipu_map_irq);
b728766c 964
861a50c1
PZ		 965int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
966 enum ipu_channel_irq irq_type)
967{
968 return ipu_map_irq(ipu, irq_type + channel->num);
aecfbdb1
SH		 969}
970EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
971
972static void ipu_submodules_exit(struct ipu_soc *ipu)
973{
35de925f 974 ipu_smfc_exit(ipu);
aecfbdb1
SH		 975 ipu_dp_exit(ipu);
976 ipu_dmfc_exit(ipu);
977 ipu_dc_exit(ipu);
978 ipu_di_exit(ipu, 1);
979 ipu_di_exit(ipu, 0);
1aa8ea0d 980 ipu_ic_exit(ipu);
2ffd48f2
SL		 981 ipu_csi_exit(ipu, 1);
982 ipu_csi_exit(ipu, 0);
7d2691da 983 ipu_cpmem_exit(ipu);
aecfbdb1
SH		 984}
985
986static int platform_remove_devices_fn(struct device *dev, void *unused)
987{
988 struct platform_device *pdev = to_platform_device(dev);
989
990 platform_device_unregister(pdev);
991
992 return 0;
993}
994
995static void platform_device_unregister_children(struct platform_device *pdev)
996{
997 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
998}
999
1000struct ipu_platform_reg {
1001 struct ipu_client_platformdata pdata;
1002 const char *name;
1003};
1004
304e6be6 1005/* These must be in the order of the corresponding device tree port nodes */
310944d1 1006static struct ipu_platform_reg client_reg[] = {
aecfbdb1 1007 {
304e6be6
PZ		 1008 .pdata = {
1009 .csi = 0,
1010 .dma[0] = IPUV3_CHANNEL_CSI0,
1011 .dma[1] = -EINVAL,
1012 },
88287ec3 1013 .name = "imx-ipuv3-csi",
304e6be6
PZ		 1014 }, {
1015 .pdata = {
1016 .csi = 1,
1017 .dma[0] = IPUV3_CHANNEL_CSI1,
1018 .dma[1] = -EINVAL,
1019 },
88287ec3 1020 .name = "imx-ipuv3-csi",
304e6be6 1021 }, {
aecfbdb1
SH		 1022 .pdata = {
1023 .di = 0,
1024 .dc = 5,
1025 .dp = IPU_DP_FLOW_SYNC_BG,
1026 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
b8d181e4 1027 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
aecfbdb1
SH		 1028 },
1029 .name = "imx-ipuv3-crtc",
1030 }, {
1031 .pdata = {
1032 .di = 1,
1033 .dc = 1,
1034 .dp = -EINVAL,
1035 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1036 .dma[1] = -EINVAL,
1037 },
1038 .name = "imx-ipuv3-crtc",
1039 },
1040};
1041
4ae078d5 1042static DEFINE_MUTEX(ipu_client_id_mutex);
aecfbdb1
SH		 1043static int ipu_client_id;
1044
d6ca8ca7 1045static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
aecfbdb1 1046{
4ae078d5
RK		 1047 struct device *dev = ipu->dev;
1048 unsigned i;
1049 int id, ret;
1050
1051 mutex_lock(&ipu_client_id_mutex);
1052 id = ipu_client_id;
1053 ipu_client_id += ARRAY_SIZE(client_reg);
1054 mutex_unlock(&ipu_client_id_mutex);
aecfbdb1
SH		 1055
1056 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
310944d1 1057 struct ipu_platform_reg *reg = &client_reg[i];
4ae078d5 1058 struct platform_device *pdev;
17e05217
PZ		 1059 struct device_node *of_node;
1060
1061 /* Associate subdevice with the corresponding port node */
1062 of_node = of_graph_get_port_by_id(dev->of_node, i);
1063 if (!of_node) {
1064 dev_info(dev,
1065 "no port@%d node in %s, not using %s%d\n",
1066 i, dev->of_node->full_name,
1067 (i / 2) ? "DI" : "CSI", i % 2);
1068 continue;
1069 }
99ae78c3 1070
304e6be6
PZ		 1071 pdev = platform_device_alloc(reg->name, id++);
1072 if (!pdev) {
1073 ret = -ENOMEM;
1074 goto err_register;
1075 }
1076
1077 pdev->dev.parent = dev;
1078
310944d1 1079 reg->pdata.of_node = of_node;
304e6be6
PZ		 1080 ret = platform_device_add_data(pdev, &reg->pdata,
1081 sizeof(reg->pdata));
1082 if (!ret)
1083 ret = platform_device_add(pdev);
1084 if (ret) {
1085 platform_device_put(pdev);
aecfbdb1 1086 goto err_register;
e4946cdc 1087 }
503fe87b
PZ		 1088
1089 /*
1090 * Set of_node only after calling platform_device_add. Otherwise
1091 * the platform:imx-ipuv3-crtc modalias won't be used.
1092 */
1093 pdev->dev.of_node = of_node;
aecfbdb1
SH		 1094 }
1095
1096 return 0;
1097
1098err_register:
4ae078d5 1099 platform_device_unregister_children(to_platform_device(dev));
aecfbdb1
SH		 1100
1101 return ret;
1102}
1103
aecfbdb1 1104
b728766c
PZ		 1105static int ipu_irq_init(struct ipu_soc *ipu)
1106{
379cdec3
PZ		 1107 struct irq_chip_generic *gc;
1108 struct irq_chip_type *ct;
37f85b26
PZ		 1109 unsigned long unused[IPU_NUM_IRQS / 32] = {
1110 0x400100d0, 0xffe000fd,
1111 0x400100d0, 0xffe000fd,
1112 0x400100d0, 0xffe000fd,
1113 0x4077ffff, 0xffe7e1fd,
1114 0x23fffffe, 0x8880fff0,
1115 0xf98fe7d0, 0xfff81fff,
1116 0x400100d0, 0xffe000fd,
1117 0x00000000,
1118 };
379cdec3
PZ		 1119 int ret, i;
1120
b728766c 1121 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
379cdec3 1122 &irq_generic_chip_ops, ipu);
b728766c
PZ		 1123 if (!ipu->domain) {
1124 dev_err(ipu->dev, "failed to add irq domain\n");
1125 return -ENODEV;
aecfbdb1
SH		 1126 }
1127
379cdec3 1128 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
ca0141de 1129 handle_level_irq, 0, 0, 0);
379cdec3
PZ		 1130 if (ret < 0) {
1131 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1132 irq_domain_remove(ipu->domain);
1133 return ret;
1134 }
1135
510e6426
RK		 1136 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1137 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1138
379cdec3
PZ		 1139 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1140 gc = irq_get_domain_generic_chip(ipu->domain, i);
1141 gc->reg_base = ipu->cm_reg;
37f85b26 1142 gc->unused = unused[i / 32];
379cdec3
PZ		 1143 ct = gc->chip_types;
1144 ct->chip.irq_ack = irq_gc_ack_set_bit;
1145 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1146 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1147 ct->regs.ack = IPU_INT_STAT(i / 32);
1148 ct->regs.mask = IPU_INT_CTRL(i / 32);
1149 }
1150
86f5e733
RK		 1151 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1152 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1153 ipu);
aecfbdb1
SH		 1154
1155 return 0;
1156}
1157
1158static void ipu_irq_exit(struct ipu_soc *ipu)
1159{
b728766c 1160 int i, irq;
aecfbdb1 1161
86f5e733
RK		 1162 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1163 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
aecfbdb1 1164
379cdec3
PZ		 1165 /* TODO: remove irq_domain_generic_chips */
1166
b728766c
PZ		 1167 for (i = 0; i < IPU_NUM_IRQS; i++) {
1168 irq = irq_linear_revmap(ipu->domain, i);
1169 if (irq)
1170 irq_dispose_mapping(irq);
aecfbdb1
SH		 1171 }
1172
b728766c 1173 irq_domain_remove(ipu->domain);
aecfbdb1
SH		 1174}
1175
3feb049f
SL		 1176void ipu_dump(struct ipu_soc *ipu)
1177{
1178 int i;
1179
1180 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1181 ipu_cm_read(ipu, IPU_CONF));
1182 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1183 ipu_idmac_read(ipu, IDMAC_CONF));
1184 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1185 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1186 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1187 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1188 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1189 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1190 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1191 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1192 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1193 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1194 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1195 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1196 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1197 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1198 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1199 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1200 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1201 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1202 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1203 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1204 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1205 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1206 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1207 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1208 for (i = 0; i < 15; i++)
1209 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1210 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1211}
1212EXPORT_SYMBOL_GPL(ipu_dump);
1213
c4aabf8d 1214static int ipu_probe(struct platform_device *pdev)
aecfbdb1
SH		 1215{
1216 const struct of_device_id *of_id =
1217 of_match_device(imx_ipu_dt_ids, &pdev->dev);
572a7615 1218 struct device_node *np = pdev->dev.of_node;
aecfbdb1
SH		 1219 struct ipu_soc *ipu;
1220 struct resource *res;
1221 unsigned long ipu_base;
1222 int i, ret, irq_sync, irq_err;
1223 const struct ipu_devtype *devtype;
1224
1225 devtype = of_id->data;
1226
aecfbdb1
SH		 1227 irq_sync = platform_get_irq(pdev, 0);
1228 irq_err = platform_get_irq(pdev, 1);
1229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230
fd563dbb 1231 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
aecfbdb1
SH		 1232 irq_sync, irq_err);
1233
1234 if (!res || irq_sync < 0 || irq_err < 0)
1235 return -ENODEV;
1236
1237 ipu_base = res->start;
1238
1239 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1240 if (!ipu)
1241 return -ENODEV;
1242
1243 for (i = 0; i < 64; i++)
1244 ipu->channel[i].ipu = ipu;
1245 ipu->devtype = devtype;
1246 ipu->ipu_type = devtype->type;
572a7615 1247 ipu->id = of_alias_get_id(np, "ipu");
aecfbdb1
SH		 1248
1249 spin_lock_init(&ipu->lock);
1250 mutex_init(&ipu->channel_lock);
1251
fd563dbb 1252 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
aecfbdb1 1253 ipu_base + devtype->cm_ofs);
fd563dbb 1254 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
aecfbdb1 1255 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
fd563dbb 1256 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
aecfbdb1 1257 ipu_base + devtype->cpmem_ofs);
2ffd48f2
SL		 1258 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1259 ipu_base + devtype->csi0_ofs);
1260 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1261 ipu_base + devtype->csi1_ofs);
1aa8ea0d
SL		 1262 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1263 ipu_base + devtype->ic_ofs);
fd563dbb 1264 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
aecfbdb1 1265 ipu_base + devtype->disp0_ofs);
fd563dbb 1266 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
aecfbdb1 1267 ipu_base + devtype->disp1_ofs);
fd563dbb 1268 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
aecfbdb1 1269 ipu_base + devtype->srm_ofs);
fd563dbb 1270 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
aecfbdb1 1271 ipu_base + devtype->tpm_ofs);
fd563dbb 1272 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
aecfbdb1 1273 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
fd563dbb 1274 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
aecfbdb1 1275 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
fd563dbb 1276 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
aecfbdb1 1277 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
fd563dbb 1278 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
aecfbdb1
SH		 1279 ipu_base + devtype->vdi_ofs);
1280
1281 ipu->cm_reg = devm_ioremap(&pdev->dev,
1282 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1283 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1284 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1285 PAGE_SIZE);
aecfbdb1 1286
7d2691da 1287 if (!ipu->cm_reg || !ipu->idmac_reg)
be798b2b 1288 return -ENOMEM;
aecfbdb1
SH		 1289
1290 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1291 if (IS_ERR(ipu->clk)) {
1292 ret = PTR_ERR(ipu->clk);
1293 dev_err(&pdev->dev, "clk_get failed with %d", ret);
be798b2b 1294 return ret;
aecfbdb1
SH		 1295 }
1296
1297 platform_set_drvdata(pdev, ipu);
1298
62645a27
FE		 1299 ret = clk_prepare_enable(ipu->clk);
1300 if (ret) {
1301 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1302 return ret;
1303 }
aecfbdb1
SH		 1304
1305 ipu->dev = &pdev->dev;
1306 ipu->irq_sync = irq_sync;
1307 ipu->irq_err = irq_err;
1308
6c64155d
PZ		 1309 ret = device_reset(&pdev->dev);
1310 if (ret) {
1311 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1312 goto out_failed_reset;
1313 }
1314 ret = ipu_memory_reset(ipu);
4d27b2ca
LW		 1315 if (ret)
1316 goto out_failed_reset;
aecfbdb1 1317
596a65d1
DJ		 1318 ret = ipu_irq_init(ipu);
1319 if (ret)
1320 goto out_failed_irq;
1321
aecfbdb1
SH		 1322 /* Set MCU_T to divide MCU access window into 2 */
1323 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1324 IPU_DISP_GEN);
1325
1326 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1327 if (ret)
1328 goto failed_submodules_init;
1329
d6ca8ca7 1330 ret = ipu_add_client_devices(ipu, ipu_base);
aecfbdb1
SH		 1331 if (ret) {
1332 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1333 ret);
1334 goto failed_add_clients;
1335 }
1336
9c2c438c
FE		 1337 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1338
aecfbdb1
SH		 1339 return 0;
1340
1341failed_add_clients:
1342 ipu_submodules_exit(ipu);
1343failed_submodules_init:
6c64155d 1344 ipu_irq_exit(ipu);
aecfbdb1 1345out_failed_irq:
596a65d1 1346out_failed_reset:
aecfbdb1 1347 clk_disable_unprepare(ipu->clk);
aecfbdb1
SH		 1348 return ret;
1349}
1350
8aa1be45 1351static int ipu_remove(struct platform_device *pdev)
aecfbdb1
SH		 1352{
1353 struct ipu_soc *ipu = platform_get_drvdata(pdev);
aecfbdb1
SH		 1354
1355 platform_device_unregister_children(pdev);
1356 ipu_submodules_exit(ipu);
1357 ipu_irq_exit(ipu);
1358
1359 clk_disable_unprepare(ipu->clk);
1360
1361 return 0;
1362}
1363
1364static struct platform_driver imx_ipu_driver = {
1365 .driver = {
1366 .name = "imx-ipuv3",
1367 .of_match_table = imx_ipu_dt_ids,
1368 },
1369 .probe = ipu_probe,
99c28f10 1370 .remove = ipu_remove,
aecfbdb1
SH		 1371};
1372
1373module_platform_driver(imx_ipu_driver);
1374
10f2268d 1375MODULE_ALIAS("platform:imx-ipuv3");
aecfbdb1
SH		 1376MODULE_DESCRIPTION("i.MX IPU v3 driver");
1377MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1378MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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