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Merge drm-fixes into drm-next.
[deliverable/linux.git] / drivers / media / pci / cx88 / cx88-dvb.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 *
3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
5 *
fc40b261 6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
1da177e4
LT		 7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/device.h>
27#include <linux/fs.h>
28#include <linux/kthread.h>
29#include <linux/file.h>
30#include <linux/suspend.h>
31
1da177e4
LT		 32#include "cx88.h"
33#include "dvb-pll.h"
5e453dc7 34#include <media/v4l2-common.h>
41ef7c1e 35
1f10c7af
AQ		 36#include "mt352.h"
37#include "mt352_priv.h"
ecf854df 38#include "cx88-vp3054-i2c.h"
1f10c7af
AQ		 39#include "zl10353.h"
40#include "cx22702.h"
41#include "or51132.h"
42#include "lgdt330x.h"
60464da8 43#include "s5h1409.h"
c21973e8 44#include "xc4000.h"
60464da8 45#include "xc5000.h"
1f10c7af
AQ		 46#include "nxt200x.h"
47#include "cx24123.h"
cd20ca9f 48#include "isl6421.h"
0df31f83 49#include "tuner-simple.h"
827855d3 50#include "tda9887.h"
d893d5dc 51#include "s5h1411.h"
e4aab64c
IL		 52#include "stv0299.h"
53#include "z0194a.h"
54#include "stv0288.h"
55#include "stb6000.h"
5bd1b663 56#include "cx24116.h"
b699c271
IL		 57#include "stv0900.h"
58#include "stb6100.h"
59#include "stb6100_proc.h"
111ac84a 60#include "mb86a16.h"
73f0af44 61#include "ts2020.h"
0cb73639 62#include "ds3000.h"
1da177e4
LT		 63
64MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
65MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
66MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
67MODULE_LICENSE("GPL");
1990d50b 68MODULE_VERSION(CX88_VERSION);
1da177e4 69
ff699e6b 70static unsigned int debug;
1da177e4
LT		 71module_param(debug, int, 0644);
72MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
73
44c6e2a7
AWC		 74static unsigned int dvb_buf_tscnt = 32;
75module_param(dvb_buf_tscnt, int, 0644);
76MODULE_PARM_DESC(dvb_buf_tscnt, "DVB Buffer TS count [dvb]");
77
78e92006
JG		 78DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
79
1da177e4 80#define dprintk(level,fmt, arg...) if (debug >= level) \
6c5be74c 81 printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
1da177e4
LT		 82
83/* ------------------------------------------------------------------ */
84
df9ecb0c 85static int queue_setup(struct vb2_queue *q,
0b6b6302
HV		 86 unsigned int *num_buffers, unsigned int *num_planes,
87 unsigned int sizes[], void *alloc_ctxs[])
1da177e4 88{
0b6b6302 89 struct cx8802_dev *dev = q->drv_priv;
1da177e4 90
0b6b6302 91 *num_planes = 1;
1da177e4 92 dev->ts_packet_size = 188 * 4;
44c6e2a7 93 dev->ts_packet_count = dvb_buf_tscnt;
0b6b6302 94 sizes[0] = dev->ts_packet_size * dev->ts_packet_count;
165d0043 95 alloc_ctxs[0] = dev->alloc_ctx;
0b6b6302 96 *num_buffers = dvb_buf_tscnt;
1da177e4
LT		 97 return 0;
98}
99
0b6b6302
HV		 100static int buffer_prepare(struct vb2_buffer *vb)
101{
2d700715 102 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 103 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 104 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
0b6b6302 105
ccd6f1d4 106 return cx8802_buf_prepare(vb->vb2_queue, dev, buf);
0b6b6302
HV		 107}
108
109static void buffer_finish(struct vb2_buffer *vb)
110{
2d700715 111 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 112 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 113 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
5e7045e3 114 struct cx88_riscmem *risc = &buf->risc;
0b6b6302 115
5e7045e3
HV		 116 if (risc->cpu)
117 pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
118 memset(risc, 0, sizeof(*risc));
0b6b6302
HV		 119}
120
121static void buffer_queue(struct vb2_buffer *vb)
1da177e4 122{
2d700715 123 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0b6b6302 124 struct cx8802_dev *dev = vb->vb2_queue->drv_priv;
2d700715 125 struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
0b6b6302
HV		 126
127 cx8802_buf_queue(dev, buf);
1da177e4
LT		 128}
129
0b6b6302 130static int start_streaming(struct vb2_queue *q, unsigned int count)
1da177e4 131{
0b6b6302
HV		 132 struct cx8802_dev *dev = q->drv_priv;
133 struct cx88_dmaqueue *dmaq = &dev->mpegq;
134 struct cx88_buffer *buf;
135
136 buf = list_entry(dmaq->active.next, struct cx88_buffer, list);
137 cx8802_start_dma(dev, dmaq, buf);
138 return 0;
1da177e4
LT		 139}
140
0b6b6302 141static void stop_streaming(struct vb2_queue *q)
1da177e4 142{
0b6b6302
HV		 143 struct cx8802_dev *dev = q->drv_priv;
144 struct cx88_dmaqueue *dmaq = &dev->mpegq;
145 unsigned long flags;
146
147 cx8802_cancel_buffers(dev);
148
149 spin_lock_irqsave(&dev->slock, flags);
150 while (!list_empty(&dmaq->active)) {
151 struct cx88_buffer *buf = list_entry(dmaq->active.next,
152 struct cx88_buffer, list);
153
154 list_del(&buf->list);
2d700715 155 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
0b6b6302
HV		 156 }
157 spin_unlock_irqrestore(&dev->slock, flags);
1da177e4
LT		 158}
159
0b6b6302
HV		 160static struct vb2_ops dvb_qops = {
161 .queue_setup = queue_setup,
162 .buf_prepare = buffer_prepare,
163 .buf_finish = buffer_finish,
164 .buf_queue = buffer_queue,
165 .wait_prepare = vb2_ops_wait_prepare,
166 .wait_finish = vb2_ops_wait_finish,
167 .start_streaming = start_streaming,
168 .stop_streaming = stop_streaming,
1da177e4
LT		 169};
170
171/* ------------------------------------------------------------------ */
22f3f17d
MK		 172
173static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
174{
175 struct cx8802_dev *dev= fe->dvb->priv;
176 struct cx8802_driver *drv = NULL;
177 int ret = 0;
363c35fc
ST		 178 int fe_id;
179
0b6b6302 180 fe_id = vb2_dvb_find_frontend(&dev->frontends, fe);
363c35fc 181 if (!fe_id) {
2af03eea 182 printk(KERN_ERR "%s() No frontend found\n", __func__);
363c35fc
ST		 183 return -EINVAL;
184 }
185
8a317a87 186 mutex_lock(&dev->core->lock);
22f3f17d
MK		 187 drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
188 if (drv) {
363c35fc
ST		 189 if (acquire){
190 dev->frontends.active_fe_id = fe_id;
22f3f17d 191 ret = drv->request_acquire(drv);
363c35fc 192 } else {
22f3f17d 193 ret = drv->request_release(drv);
363c35fc
ST		 194 dev->frontends.active_fe_id = 0;
195 }
22f3f17d 196 }
1fe70e96 197 mutex_unlock(&dev->core->lock);
22f3f17d
MK		 198
199 return ret;
200}
201
e32fadc4
MCC		 202static void cx88_dvb_gate_ctrl(struct cx88_core *core, int open)
203{
0b6b6302
HV		 204 struct vb2_dvb_frontends *f;
205 struct vb2_dvb_frontend *fe;
e32fadc4
MCC		 206
207 if (!core->dvbdev)
208 return;
209
210 f = &core->dvbdev->frontends;
211
212 if (!f)
213 return;
214
215 if (f->gate <= 1) /* undefined or fe0 */
0b6b6302 216 fe = vb2_dvb_get_frontend(f, 1);
e32fadc4 217 else
0b6b6302 218 fe = vb2_dvb_get_frontend(f, f->gate);
e32fadc4
MCC		 219
220 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
221 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
222}
223
22f3f17d
MK		 224/* ------------------------------------------------------------------ */
225
3d7d027a 226static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
1da177e4 227{
2e4e98e7 228 static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
229 static const u8 reset [] = { RESET, 0x80 };
230 static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
231 static const u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
232 static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
233 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
1da177e4
LT		 234
235 mt352_write(fe, clock_config, sizeof(clock_config));
236 udelay(200);
237 mt352_write(fe, reset, sizeof(reset));
238 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
239
240 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
241 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
242 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
243 return 0;
244}
245
43eabb4e
CP		 246static int dvico_dual_demod_init(struct dvb_frontend *fe)
247{
2e4e98e7 248 static const u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
249 static const u8 reset [] = { RESET, 0x80 };
250 static const u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
251 static const u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
252 static const u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
253 static const u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
43eabb4e
CP		 254
255 mt352_write(fe, clock_config, sizeof(clock_config));
256 udelay(200);
257 mt352_write(fe, reset, sizeof(reset));
258 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
259
260 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
261 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
262 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
263
264 return 0;
265}
266
1da177e4
LT		 267static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
268{
2e4e98e7 269 static const u8 clock_config [] = { 0x89, 0x38, 0x39 };
270 static const u8 reset [] = { 0x50, 0x80 };
271 static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
272 static const u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
f2421ca3 273 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 274 static const u8 dntv_extra[] = { 0xB5, 0x7A };
275 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
1da177e4
LT		 276
277 mt352_write(fe, clock_config, sizeof(clock_config));
278 udelay(2000);
279 mt352_write(fe, reset, sizeof(reset));
280 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
281
282 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
283 udelay(2000);
284 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
285 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
286
287 return 0;
288}
289
2e4e98e7 290static const struct mt352_config dvico_fusionhdtv = {
f7b54b10 291 .demod_address = 0x0f,
3d7d027a 292 .demod_init = dvico_fusionhdtv_demod_init,
1da177e4
LT		 293};
294
2e4e98e7 295static const struct mt352_config dntv_live_dvbt_config = {
1da177e4
LT		 296 .demod_address = 0x0f,
297 .demod_init = dntv_live_dvbt_demod_init,
1da177e4 298};
fc40b261 299
2e4e98e7 300static const struct mt352_config dvico_fusionhdtv_dual = {
f7b54b10 301 .demod_address = 0x0f,
43eabb4e 302 .demod_init = dvico_dual_demod_init,
43eabb4e
CP		 303};
304
2e4e98e7 305static const struct zl10353_config cx88_terratec_cinergy_ht_pci_mkii_config = {
70101a27
SW		 306 .demod_address = (0x1e >> 1),
307 .no_tuner = 1,
308 .if2 = 45600,
309};
310
111ac84a
SI		 311static struct mb86a16_config twinhan_vp1027 = {
312 .demod_address = 0x08,
313};
314
7b34be71 315#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
3d7d027a
CP		 316static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
317{
2e4e98e7 318 static const u8 clock_config [] = { 0x89, 0x38, 0x38 };
319 static const u8 reset [] = { 0x50, 0x80 };
320 static const u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
321 static const u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
3d7d027a 322 0x00, 0xFF, 0x00, 0x40, 0x40 };
2e4e98e7 323 static const u8 dntv_extra[] = { 0xB5, 0x7A };
324 static const u8 capt_range_cfg[] = { 0x75, 0x32 };
3d7d027a
CP		 325
326 mt352_write(fe, clock_config, sizeof(clock_config));
327 udelay(2000);
328 mt352_write(fe, reset, sizeof(reset));
329 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
330
331 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
332 udelay(2000);
333 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
334 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
335
336 return 0;
337}
338
2e4e98e7 339static const struct mt352_config dntv_live_dvbt_pro_config = {
fc40b261
CP		 340 .demod_address = 0x0f,
341 .no_tuner = 1,
3d7d027a 342 .demod_init = dntv_live_dvbt_pro_demod_init,
fc40b261
CP		 343};
344#endif
1da177e4 345
2e4e98e7 346static const struct zl10353_config dvico_fusionhdtv_hybrid = {
f7b54b10 347 .demod_address = 0x0f,
f54376e2 348 .no_tuner = 1,
780dfef3
CP		 349};
350
2e4e98e7 351static const struct zl10353_config dvico_fusionhdtv_xc3028 = {
b3fb91d2
CP		 352 .demod_address = 0x0f,
353 .if2 = 45600,
354 .no_tuner = 1,
355};
356
2e4e98e7 357static const struct mt352_config dvico_fusionhdtv_mt352_xc3028 = {
b3fb91d2
CP		 358 .demod_address = 0x0f,
359 .if2 = 4560,
360 .no_tuner = 1,
361 .demod_init = dvico_fusionhdtv_demod_init,
362};
363
2e4e98e7 364static const struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
f7b54b10 365 .demod_address = 0x0f,
780dfef3 366};
780dfef3 367
2e4e98e7 368static const struct cx22702_config connexant_refboard_config = {
1da177e4 369 .demod_address = 0x43,
38d84c3b 370 .output_mode = CX22702_SERIAL_OUTPUT,
1da177e4
LT		 371};
372
2e4e98e7 373static const struct cx22702_config hauppauge_hvr_config = {
aa481a65
ST		 374 .demod_address = 0x63,
375 .output_mode = CX22702_SERIAL_OUTPUT,
376};
1da177e4 377
4a390558 378static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
1da177e4
LT		 379{
380 struct cx8802_dev *dev= fe->dvb->priv;
381 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
382 return 0;
383}
384
2e4e98e7 385static const struct or51132_config pchdtv_hd3000 = {
f7b54b10
MK		 386 .demod_address = 0x15,
387 .set_ts_params = or51132_set_ts_param,
1da177e4 388};
1da177e4 389
6ddcc919 390static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
0ccef6db
MK		 391{
392 struct cx8802_dev *dev= fe->dvb->priv;
393 struct cx88_core *core = dev->core;
394
32d83efc 395 dprintk(1, "%s: index = %d\n", __func__, index);
0ccef6db
MK		 396 if (index == 0)
397 cx_clear(MO_GP0_IO, 8);
398 else
399 cx_set(MO_GP0_IO, 8);
400 return 0;
401}
402
6ddcc919 403static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
f1798495
MK		 404{
405 struct cx8802_dev *dev= fe->dvb->priv;
406 if (is_punctured)
407 dev->ts_gen_cntrl |= 0x04;
408 else
409 dev->ts_gen_cntrl &= ~0x04;
410 return 0;
411}
412
6ddcc919 413static struct lgdt330x_config fusionhdtv_3_gold = {
f7b54b10
MK		 414 .demod_address = 0x0e,
415 .demod_chip = LGDT3302,
416 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
417 .set_ts_params = lgdt330x_set_ts_param,
0d723c09 418};
e52e98a7 419
2e4e98e7 420static const struct lgdt330x_config fusionhdtv_5_gold = {
f7b54b10
MK		 421 .demod_address = 0x0e,
422 .demod_chip = LGDT3303,
423 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
424 .set_ts_params = lgdt330x_set_ts_param,
e52e98a7 425};
da215d22 426
2e4e98e7 427static const struct lgdt330x_config pchdtv_hd5500 = {
f7b54b10
MK		 428 .demod_address = 0x59,
429 .demod_chip = LGDT3303,
430 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
431 .set_ts_params = lgdt330x_set_ts_param,
da215d22 432};
f1798495 433
4a390558 434static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
fde6d31e
KL		 435{
436 struct cx8802_dev *dev= fe->dvb->priv;
437 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
438 return 0;
439}
440
2e4e98e7 441static const struct nxt200x_config ati_hdtvwonder = {
f7b54b10 442 .demod_address = 0x0a,
f7b54b10 443 .set_ts_params = nxt200x_set_ts_param,
fde6d31e 444};
fde6d31e 445
0fa14aa6
ST		 446static int cx24123_set_ts_param(struct dvb_frontend* fe,
447 int is_punctured)
448{
449 struct cx8802_dev *dev= fe->dvb->priv;
f7b54b10 450 dev->ts_gen_cntrl = 0x02;
0fa14aa6
ST		 451 return 0;
452}
453
f7b54b10 454static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
0df289a2 455 enum fe_sec_voltage voltage)
0e0351e3
VC		 456{
457 struct cx8802_dev *dev= fe->dvb->priv;
458 struct cx88_core *core = dev->core;
459
4a390558 460 if (voltage == SEC_VOLTAGE_OFF)
f7b54b10 461 cx_write(MO_GP0_IO, 0x000006fb);
4a390558 462 else
cd20ca9f 463 cx_write(MO_GP0_IO, 0x000006f9);
cd20ca9f
AQ		 464
465 if (core->prev_set_voltage)
466 return core->prev_set_voltage(fe, voltage);
467 return 0;
0e0351e3
VC		 468}
469
f7b54b10 470static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
0df289a2 471 enum fe_sec_voltage voltage)
c02a34f4
SA		 472{
473 struct cx8802_dev *dev= fe->dvb->priv;
474 struct cx88_core *core = dev->core;
475
476 if (voltage == SEC_VOLTAGE_OFF) {
477 dprintk(1,"LNB Voltage OFF\n");
478 cx_write(MO_GP0_IO, 0x0000efff);
479 }
480
481 if (core->prev_set_voltage)
482 return core->prev_set_voltage(fe, voltage);
483 return 0;
484}
485
af832623 486static int tevii_dvbs_set_voltage(struct dvb_frontend *fe,
0df289a2 487 enum fe_sec_voltage voltage)
af832623
IL		 488{
489 struct cx8802_dev *dev= fe->dvb->priv;
490 struct cx88_core *core = dev->core;
491
ad5f74c0 492 cx_set(MO_GP0_IO, 0x6040);
af832623 493 switch (voltage) {
111ac84a
SI		 494 case SEC_VOLTAGE_13:
495 cx_clear(MO_GP0_IO, 0x20);
496 break;
497 case SEC_VOLTAGE_18:
498 cx_set(MO_GP0_IO, 0x20);
499 break;
500 case SEC_VOLTAGE_OFF:
501 cx_clear(MO_GP0_IO, 0x20);
502 break;
503 }
504
505 if (core->prev_set_voltage)
506 return core->prev_set_voltage(fe, voltage);
507 return 0;
508}
509
510static int vp1027_set_voltage(struct dvb_frontend *fe,
0df289a2 511 enum fe_sec_voltage voltage)
111ac84a
SI		 512{
513 struct cx8802_dev *dev = fe->dvb->priv;
514 struct cx88_core *core = dev->core;
515
516 switch (voltage) {
517 case SEC_VOLTAGE_13:
518 dprintk(1, "LNB SEC Voltage=13\n");
519 cx_write(MO_GP0_IO, 0x00001220);
520 break;
521 case SEC_VOLTAGE_18:
522 dprintk(1, "LNB SEC Voltage=18\n");
523 cx_write(MO_GP0_IO, 0x00001222);
524 break;
525 case SEC_VOLTAGE_OFF:
526 dprintk(1, "LNB Voltage OFF\n");
527 cx_write(MO_GP0_IO, 0x00001230);
528 break;
af832623
IL		 529 }
530
531 if (core->prev_set_voltage)
532 return core->prev_set_voltage(fe, voltage);
533 return 0;
534}
535
2e4e98e7 536static const struct cx24123_config geniatech_dvbs_config = {
f7b54b10
MK		 537 .demod_address = 0x55,
538 .set_ts_params = cx24123_set_ts_param,
c02a34f4
SA		 539};
540
2e4e98e7 541static const struct cx24123_config hauppauge_novas_config = {
f7b54b10
MK		 542 .demod_address = 0x55,
543 .set_ts_params = cx24123_set_ts_param,
0e0351e3
VC		 544};
545
2e4e98e7 546static const struct cx24123_config kworld_dvbs_100_config = {
f7b54b10
MK		 547 .demod_address = 0x15,
548 .set_ts_params = cx24123_set_ts_param,
ef76856d 549 .lnb_polarity = 1,
0fa14aa6 550};
0fa14aa6 551
2e4e98e7 552static const struct s5h1409_config pinnacle_pctv_hd_800i_config = {
60464da8
ST		 553 .demod_address = 0x32 >> 1,
554 .output_mode = S5H1409_PARALLEL_OUTPUT,
555 .gpio = S5H1409_GPIO_ON,
556 .qam_if = 44000,
557 .inversion = S5H1409_INVERSION_OFF,
558 .status_mode = S5H1409_DEMODLOCKING,
4917019d 559 .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
60464da8
ST		 560};
561
2e4e98e7 562static const struct s5h1409_config dvico_hdtv5_pci_nano_config = {
5c00fac0
ST		 563 .demod_address = 0x32 >> 1,
564 .output_mode = S5H1409_SERIAL_OUTPUT,
565 .gpio = S5H1409_GPIO_OFF,
566 .inversion = S5H1409_INVERSION_OFF,
567 .status_mode = S5H1409_DEMODLOCKING,
568 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
569};
570
2e4e98e7 571static const struct s5h1409_config kworld_atsc_120_config = {
99e09eac 572 .demod_address = 0x32 >> 1,
99e09eac
MCC		 573 .output_mode = S5H1409_SERIAL_OUTPUT,
574 .gpio = S5H1409_GPIO_OFF,
575 .inversion = S5H1409_INVERSION_OFF,
576 .status_mode = S5H1409_DEMODLOCKING,
577 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
578};
579
2e4e98e7 580static const struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
60464da8
ST		 581 .i2c_address = 0x64,
582 .if_khz = 5380,
60464da8
ST		 583};
584
2e4e98e7 585static const struct zl10353_config cx88_pinnacle_hybrid_pctv = {
3f6014fc
SV		 586 .demod_address = (0x1e >> 1),
587 .no_tuner = 1,
588 .if2 = 45600,
589};
590
2e4e98e7 591static const struct zl10353_config cx88_geniatech_x8000_mt = {
57069349
MCC		 592 .demod_address = (0x1e >> 1),
593 .no_tuner = 1,
594 .disable_i2c_gate_ctrl = 1,
9507901e
MCC		 595};
596
2e4e98e7 597static const struct s5h1411_config dvico_fusionhdtv7_config = {
d893d5dc
ST		 598 .output_mode = S5H1411_SERIAL_OUTPUT,
599 .gpio = S5H1411_GPIO_ON,
600 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
601 .qam_if = S5H1411_IF_44000,
602 .vsb_if = S5H1411_IF_44000,
603 .inversion = S5H1411_INVERSION_OFF,
604 .status_mode = S5H1411_DEMODLOCKING
605};
606
2e4e98e7 607static const struct xc5000_config dvico_fusionhdtv7_tuner_config = {
d893d5dc
ST		 608 .i2c_address = 0xc2 >> 1,
609 .if_khz = 5380,
d893d5dc
ST		 610};
611
23fb348d
MCC		 612static int attach_xc3028(u8 addr, struct cx8802_dev *dev)
613{
614 struct dvb_frontend *fe;
0b6b6302 615 struct vb2_dvb_frontend *fe0 = NULL;
99e09eac 616 struct xc2028_ctrl ctl;
23fb348d
MCC		 617 struct xc2028_config cfg = {
618 .i2c_adap = &dev->core->i2c_adap,
619 .i2c_addr = addr,
99e09eac 620 .ctrl = &ctl,
23fb348d
MCC		 621 };
622
92abe9ee 623 /* Get the first frontend */
0b6b6302 624 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
363c35fc
ST		 625 if (!fe0)
626 return -EINVAL;
627
628 if (!fe0->dvb.frontend) {
ddd5441d
MCC		 629 printk(KERN_ERR "%s/2: dvb frontend not attached. "
630 "Can't attach xc3028\n",
631 dev->core->name);
632 return -EINVAL;
633 }
634
99e09eac
MCC		 635 /*
636 * Some xc3028 devices may be hidden by an I2C gate. This is known
637 * to happen with some s5h1409-based devices.
638 * Now that I2C gate is open, sets up xc3028 configuration
639 */
640 cx88_setup_xc3028(dev->core, &ctl);
641
363c35fc 642 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, &cfg);
23fb348d
MCC		 643 if (!fe) {
644 printk(KERN_ERR "%s/2: xc3028 attach failed\n",
645 dev->core->name);
363c35fc
ST		 646 dvb_frontend_detach(fe0->dvb.frontend);
647 dvb_unregister_frontend(fe0->dvb.frontend);
648 fe0->dvb.frontend = NULL;
23fb348d
MCC		 649 return -EINVAL;
650 }
651
652 printk(KERN_INFO "%s/2: xc3028 attached\n",
653 dev->core->name);
654
655 return 0;
656}
9507901e 657
c21973e8 658static int attach_xc4000(struct cx8802_dev *dev, struct xc4000_config *cfg)
659{
660 struct dvb_frontend *fe;
0b6b6302 661 struct vb2_dvb_frontend *fe0 = NULL;
c21973e8 662
663 /* Get the first frontend */
0b6b6302 664 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
c21973e8 665 if (!fe0)
666 return -EINVAL;
667
668 if (!fe0->dvb.frontend) {
669 printk(KERN_ERR "%s/2: dvb frontend not attached. "
670 "Can't attach xc4000\n",
671 dev->core->name);
672 return -EINVAL;
673 }
674
675 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, &dev->core->i2c_adap,
676 cfg);
677 if (!fe) {
678 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
679 dev->core->name);
680 dvb_frontend_detach(fe0->dvb.frontend);
681 dvb_unregister_frontend(fe0->dvb.frontend);
682 fe0->dvb.frontend = NULL;
683 return -EINVAL;
684 }
685
686 printk(KERN_INFO "%s/2: xc4000 attached\n", dev->core->name);
687
688 return 0;
689}
690
5bd1b663
ST		 691static int cx24116_set_ts_param(struct dvb_frontend *fe,
692 int is_punctured)
693{
694 struct cx8802_dev *dev = fe->dvb->priv;
695 dev->ts_gen_cntrl = 0x2;
696
697 return 0;
698}
699
b699c271
IL		 700static int stv0900_set_ts_param(struct dvb_frontend *fe,
701 int is_punctured)
702{
703 struct cx8802_dev *dev = fe->dvb->priv;
704 dev->ts_gen_cntrl = 0;
705
706 return 0;
707}
708
5bd1b663
ST		 709static int cx24116_reset_device(struct dvb_frontend *fe)
710{
711 struct cx8802_dev *dev = fe->dvb->priv;
712 struct cx88_core *core = dev->core;
713
714 /* Reset the part */
363c35fc 715 /* Put the cx24116 into reset */
5bd1b663
ST		 716 cx_write(MO_SRST_IO, 0);
717 msleep(10);
363c35fc 718 /* Take the cx24116 out of reset */
5bd1b663
ST		 719 cx_write(MO_SRST_IO, 1);
720 msleep(10);
721
722 return 0;
723}
724
2e4e98e7 725static const struct cx24116_config hauppauge_hvr4000_config = {
5bd1b663
ST		 726 .demod_address = 0x05,
727 .set_ts_params = cx24116_set_ts_param,
728 .reset_device = cx24116_reset_device,
729};
730
2e4e98e7 731static const struct cx24116_config tevii_s460_config = {
af832623
IL		 732 .demod_address = 0x55,
733 .set_ts_params = cx24116_set_ts_param,
734 .reset_device = cx24116_reset_device,
735};
736
0cb73639
IL		 737static int ds3000_set_ts_param(struct dvb_frontend *fe,
738 int is_punctured)
739{
740 struct cx8802_dev *dev = fe->dvb->priv;
741 dev->ts_gen_cntrl = 4;
742
743 return 0;
744}
745
746static struct ds3000_config tevii_ds3000_config = {
747 .demod_address = 0x68,
748 .set_ts_params = ds3000_set_ts_param,
749};
750
73f0af44
KD		 751static struct ts2020_config tevii_ts2020_config = {
752 .tuner_address = 0x60,
b858c331 753 .clk_out_div = 1,
73f0af44
KD		 754};
755
2e4e98e7 756static const struct stv0900_config prof_7301_stv0900_config = {
b699c271
IL		 757 .demod_address = 0x6a,
758/* demod_mode = 0,*/
759 .xtal = 27000000,
760 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
761 .diseqc_mode = 2,/* 2/3 PWM */
762 .tun1_maddress = 0,/* 0x60 */
763 .tun1_adc = 0,/* 2 Vpp */
764 .path1_mode = 3,
765 .set_ts_params = stv0900_set_ts_param,
766};
767
2e4e98e7 768static const struct stb6100_config prof_7301_stb6100_config = {
b699c271
IL		 769 .tuner_address = 0x60,
770 .refclock = 27000000,
771};
772
2e4e98e7 773static const struct stv0299_config tevii_tuner_sharp_config = {
e4aab64c 774 .demod_address = 0x68,
d4305c68 775 .inittab = sharp_z0194a_inittab,
e4aab64c
IL		 776 .mclk = 88000000UL,
777 .invert = 1,
778 .skip_reinit = 0,
779 .lock_output = 1,
780 .volt13_op0_op1 = STV0299_VOLT13_OP1,
781 .min_delay_ms = 100,
d4305c68 782 .set_symbol_rate = sharp_z0194a_set_symbol_rate,
e4aab64c
IL		 783 .set_ts_params = cx24116_set_ts_param,
784};
785
2e4e98e7 786static const struct stv0288_config tevii_tuner_earda_config = {
e4aab64c
IL		 787 .demod_address = 0x68,
788 .min_delay_ms = 100,
789 .set_ts_params = cx24116_set_ts_param,
790};
791
6e0e12f1 792static int cx8802_alloc_frontends(struct cx8802_dev *dev)
1da177e4 793{
0590d91c 794 struct cx88_core *core = dev->core;
0b6b6302 795 struct vb2_dvb_frontend *fe = NULL;
e32fadc4 796 int i;
0590d91c 797
e32fadc4
MCC		 798 mutex_init(&dev->frontends.lock);
799 INIT_LIST_HEAD(&dev->frontends.felist);
800
6e0e12f1
AW		 801 if (!core->board.num_frontends)
802 return -ENODEV;
803
e32fadc4
MCC		 804 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
805 core->board.num_frontends);
806 for (i = 1; i <= core->board.num_frontends; i++) {
0b6b6302 807 fe = vb2_dvb_alloc_frontend(&dev->frontends, i);
6e0e12f1 808 if (!fe) {
e32fadc4 809 printk(KERN_ERR "%s() failed to alloc\n", __func__);
0b6b6302 810 vb2_dvb_dealloc_frontends(&dev->frontends);
6e0e12f1 811 return -ENOMEM;
e32fadc4
MCC		 812 }
813 }
6e0e12f1
AW		 814 return 0;
815}
816
4f3ca2f1
DH		 817
818
2e4e98e7 819static const u8 samsung_smt_7020_inittab[] = {
4f3ca2f1
DH		 820 0x01, 0x15,
821 0x02, 0x00,
822 0x03, 0x00,
823 0x04, 0x7D,
824 0x05, 0x0F,
825 0x06, 0x02,
826 0x07, 0x00,
827 0x08, 0x60,
828
829 0x0A, 0xC2,
830 0x0B, 0x00,
831 0x0C, 0x01,
832 0x0D, 0x81,
833 0x0E, 0x44,
834 0x0F, 0x09,
835 0x10, 0x3C,
836 0x11, 0x84,
837 0x12, 0xDA,
838 0x13, 0x99,
839 0x14, 0x8D,
840 0x15, 0xCE,
841 0x16, 0xE8,
842 0x17, 0x43,
843 0x18, 0x1C,
844 0x19, 0x1B,
845 0x1A, 0x1D,
846
847 0x1C, 0x12,
848 0x1D, 0x00,
849 0x1E, 0x00,
850 0x1F, 0x00,
851 0x20, 0x00,
852 0x21, 0x00,
853 0x22, 0x00,
854 0x23, 0x00,
855
856 0x28, 0x02,
857 0x29, 0x28,
858 0x2A, 0x14,
859 0x2B, 0x0F,
860 0x2C, 0x09,
861 0x2D, 0x05,
862
863 0x31, 0x1F,
864 0x32, 0x19,
865 0x33, 0xFC,
866 0x34, 0x13,
867 0xff, 0xff,
868};
869
870
14d24d14 871static int samsung_smt_7020_tuner_set_params(struct dvb_frontend *fe)
4f3ca2f1 872{
b738ae16 873 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
4f3ca2f1
DH		 874 struct cx8802_dev *dev = fe->dvb->priv;
875 u8 buf[4];
876 u32 div;
877 struct i2c_msg msg = {
878 .addr = 0x61,
879 .flags = 0,
880 .buf = buf,
881 .len = sizeof(buf) };
882
b738ae16 883 div = c->frequency / 125;
4f3ca2f1
DH		 884
885 buf[0] = (div >> 8) & 0x7f;
886 buf[1] = div & 0xff;
887 buf[2] = 0x84; /* 0xC4 */
888 buf[3] = 0x00;
889
b738ae16 890 if (c->frequency < 1500000)
4f3ca2f1
DH		 891 buf[3] |= 0x10;
892
893 if (fe->ops.i2c_gate_ctrl)
894 fe->ops.i2c_gate_ctrl(fe, 1);
895
896 if (i2c_transfer(&dev->core->i2c_adap, &msg, 1) != 1)
897 return -EIO;
898
899 return 0;
900}
901
902static int samsung_smt_7020_set_tone(struct dvb_frontend *fe,
0df289a2 903 enum fe_sec_tone_mode tone)
4f3ca2f1
DH		 904{
905 struct cx8802_dev *dev = fe->dvb->priv;
906 struct cx88_core *core = dev->core;
907
908 cx_set(MO_GP0_IO, 0x0800);
909
910 switch (tone) {
911 case SEC_TONE_ON:
912 cx_set(MO_GP0_IO, 0x08);
913 break;
914 case SEC_TONE_OFF:
915 cx_clear(MO_GP0_IO, 0x08);
916 break;
917 default:
918 return -EINVAL;
919 }
920
921 return 0;
922}
923
924static int samsung_smt_7020_set_voltage(struct dvb_frontend *fe,
0df289a2 925 enum fe_sec_voltage voltage)
4f3ca2f1
DH		 926{
927 struct cx8802_dev *dev = fe->dvb->priv;
928 struct cx88_core *core = dev->core;
929
930 u8 data;
931 struct i2c_msg msg = {
932 .addr = 8,
933 .flags = 0,
934 .buf = &data,
935 .len = sizeof(data) };
936
937 cx_set(MO_GP0_IO, 0x8000);
938
939 switch (voltage) {
940 case SEC_VOLTAGE_OFF:
941 break;
942 case SEC_VOLTAGE_13:
943 data = ISL6421_EN1 | ISL6421_LLC1;
944 cx_clear(MO_GP0_IO, 0x80);
945 break;
946 case SEC_VOLTAGE_18:
947 data = ISL6421_EN1 | ISL6421_LLC1 | ISL6421_VSEL1;
948 cx_clear(MO_GP0_IO, 0x80);
949 break;
950 default:
951 return -EINVAL;
c2c1b415 952 }
4f3ca2f1
DH		 953
954 return (i2c_transfer(&dev->core->i2c_adap, &msg, 1) == 1) ? 0 : -EIO;
955}
956
957static int samsung_smt_7020_stv0299_set_symbol_rate(struct dvb_frontend *fe,
958 u32 srate, u32 ratio)
959{
960 u8 aclk = 0;
961 u8 bclk = 0;
962
963 if (srate < 1500000) {
964 aclk = 0xb7;
965 bclk = 0x47;
966 } else if (srate < 3000000) {
967 aclk = 0xb7;
968 bclk = 0x4b;
969 } else if (srate < 7000000) {
970 aclk = 0xb7;
971 bclk = 0x4f;
972 } else if (srate < 14000000) {
973 aclk = 0xb7;
974 bclk = 0x53;
975 } else if (srate < 30000000) {
976 aclk = 0xb6;
977 bclk = 0x53;
978 } else if (srate < 45000000) {
979 aclk = 0xb4;
980 bclk = 0x51;
981 }
982
983 stv0299_writereg(fe, 0x13, aclk);
984 stv0299_writereg(fe, 0x14, bclk);
985 stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
986 stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
987 stv0299_writereg(fe, 0x21, ratio & 0xf0);
988
989 return 0;
990}
991
992
2e4e98e7 993static const struct stv0299_config samsung_stv0299_config = {
4f3ca2f1
DH		 994 .demod_address = 0x68,
995 .inittab = samsung_smt_7020_inittab,
996 .mclk = 88000000UL,
997 .invert = 0,
998 .skip_reinit = 0,
999 .lock_output = STV0299_LOCKOUTPUT_LK,
1000 .volt13_op0_op1 = STV0299_VOLT13_OP1,
1001 .min_delay_ms = 100,
1002 .set_symbol_rate = samsung_smt_7020_stv0299_set_symbol_rate,
1003};
1004
6e0e12f1
AW		 1005static int dvb_register(struct cx8802_dev *dev)
1006{
1007 struct cx88_core *core = dev->core;
0b6b6302 1008 struct vb2_dvb_frontend *fe0, *fe1 = NULL;
6e0e12f1 1009 int mfe_shared = 0; /* bus not shared by default */
7b0962d3 1010 int res = -EINVAL;
6e0e12f1
AW		 1011
1012 if (0 != core->i2c_rc) {
1013 printk(KERN_ERR "%s/2: no i2c-bus available, cannot attach dvb drivers\n", core->name);
1014 goto frontend_detach;
1015 }
e32fadc4 1016
363c35fc 1017 /* Get the first frontend */
0b6b6302 1018 fe0 = vb2_dvb_get_frontend(&dev->frontends, 1);
363c35fc 1019 if (!fe0)
60a5a927 1020 goto frontend_detach;
1da177e4 1021
8e739090
DB		 1022 /* multi-frontend gate control is undefined or defaults to fe0 */
1023 dev->frontends.gate = 0;
1024
e32fadc4
MCC		 1025 /* Sets the gate control callback to be used by i2c command calls */
1026 core->gate_ctrl = cx88_dvb_gate_ctrl;
1027
8e739090 1028 /* init frontend(s) */
0590d91c 1029 switch (core->boardnr) {
1da177e4 1030 case CX88_BOARD_HAUPPAUGE_DVB_T1:
363c35fc 1031 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 1032 &connexant_refboard_config,
0590d91c 1033 &core->i2c_adap);
363c35fc
ST		 1034 if (fe0->dvb.frontend != NULL) {
1035 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1036 0x61, &core->i2c_adap,
1037 DVB_PLL_THOMSON_DTT759X))
1038 goto frontend_detach;
f54376e2 1039 }
1da177e4 1040 break;
e057ee11 1041 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
1da177e4 1042 case CX88_BOARD_CONEXANT_DVB_T1:
f39624fd 1043 case CX88_BOARD_KWORLD_DVB_T_CX22702:
2b5200a7 1044 case CX88_BOARD_WINFAST_DTV1000:
363c35fc 1045 fe0->dvb.frontend = dvb_attach(cx22702_attach,
f7b54b10 1046 &connexant_refboard_config,
0590d91c 1047 &core->i2c_adap);
363c35fc
ST		 1048 if (fe0->dvb.frontend != NULL) {
1049 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1050 0x60, &core->i2c_adap,
1051 DVB_PLL_THOMSON_DTT7579))
1052 goto frontend_detach;
f54376e2 1053 }
1da177e4 1054 break;
4bd6e9d9 1055 case CX88_BOARD_WINFAST_DTV2000H:
611900c1
ST		 1056 case CX88_BOARD_HAUPPAUGE_HVR1100:
1057 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
a5a2ecfc 1058 case CX88_BOARD_HAUPPAUGE_HVR1300:
363c35fc 1059 fe0->dvb.frontend = dvb_attach(cx22702_attach,
ed355260 1060 &hauppauge_hvr_config,
0590d91c 1061 &core->i2c_adap);
363c35fc
ST		 1062 if (fe0->dvb.frontend != NULL) {
1063 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1064 &core->i2c_adap, 0x61,
1065 TUNER_PHILIPS_FMD1216ME_MK3))
1066 goto frontend_detach;
f54376e2 1067 }
611900c1 1068 break;
27b93d8a
MS		 1069 case CX88_BOARD_WINFAST_DTV2000H_J:
1070 fe0->dvb.frontend = dvb_attach(cx22702_attach,
1071 &hauppauge_hvr_config,
1072 &core->i2c_adap);
1073 if (fe0->dvb.frontend != NULL) {
1074 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
1075 &core->i2c_adap, 0x61,
1076 TUNER_PHILIPS_FMD1216MEX_MK3))
1077 goto frontend_detach;
1078 }
1079 break;
363c35fc 1080 case CX88_BOARD_HAUPPAUGE_HVR3000:
60a5a927
DB		 1081 /* MFE frontend 1 */
1082 mfe_shared = 1;
1083 dev->frontends.gate = 2;
363c35fc
ST		 1084 /* DVB-S init */
1085 fe0->dvb.frontend = dvb_attach(cx24123_attach,
60a5a927
DB		 1086 &hauppauge_novas_config,
1087 &dev->core->i2c_adap);
363c35fc 1088 if (fe0->dvb.frontend) {
60a5a927
DB		 1089 if (!dvb_attach(isl6421_attach,
1090 fe0->dvb.frontend,
1091 &dev->core->i2c_adap,
48a8a03b 1092 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1093 goto frontend_detach;
363c35fc 1094 }
60a5a927 1095 /* MFE frontend 2 */
0b6b6302 1096 fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB		 1097 if (!fe1)
1098 goto frontend_detach;
1099 /* DVB-T init */
1100 fe1->dvb.frontend = dvb_attach(cx22702_attach,
1101 &hauppauge_hvr_config,
1102 &dev->core->i2c_adap);
1103 if (fe1->dvb.frontend) {
1104 fe1->dvb.frontend->id = 1;
1105 if (!dvb_attach(simple_tuner_attach,
1106 fe1->dvb.frontend,
1107 &dev->core->i2c_adap,
1108 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1109 goto frontend_detach;
363c35fc
ST		 1110 }
1111 break;
780dfef3 1112 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
363c35fc 1113 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1114 &dvico_fusionhdtv,
0590d91c 1115 &core->i2c_adap);
363c35fc
ST		 1116 if (fe0->dvb.frontend != NULL) {
1117 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1118 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1119 goto frontend_detach;
780dfef3 1120 break;
f54376e2 1121 }
780dfef3 1122 /* ZL10353 replaces MT352 on later cards */
363c35fc 1123 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1124 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1125 &core->i2c_adap);
363c35fc
ST		 1126 if (fe0->dvb.frontend != NULL) {
1127 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1128 0x60, NULL, DVB_PLL_THOMSON_DTT7579))
1129 goto frontend_detach;
f54376e2 1130 }
c2af3cd6
MK		 1131 break;
1132 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
c2af3cd6
MK		 1133 /* The tin box says DEE1601, but it seems to be DTT7579
1134 * compatible, with a slightly different MT352 AGC gain. */
363c35fc 1135 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1136 &dvico_fusionhdtv_dual,
0590d91c 1137 &core->i2c_adap);
363c35fc
ST		 1138 if (fe0->dvb.frontend != NULL) {
1139 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1140 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1141 goto frontend_detach;
c2af3cd6
MK		 1142 break;
1143 }
c2af3cd6 1144 /* ZL10353 replaces MT352 on later cards */
363c35fc 1145 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1146 &dvico_fusionhdtv_plus_v1_1,
0590d91c 1147 &core->i2c_adap);
363c35fc
ST		 1148 if (fe0->dvb.frontend != NULL) {
1149 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1150 0x61, NULL, DVB_PLL_THOMSON_DTT7579))
1151 goto frontend_detach;
c2af3cd6 1152 }
1da177e4 1153 break;
780dfef3 1154 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
363c35fc 1155 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1156 &dvico_fusionhdtv,
0590d91c 1157 &core->i2c_adap);
363c35fc
ST		 1158 if (fe0->dvb.frontend != NULL) {
1159 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1160 0x61, NULL, DVB_PLL_LG_Z201))
1161 goto frontend_detach;
f54376e2 1162 }
1da177e4
LT		 1163 break;
1164 case CX88_BOARD_KWORLD_DVB_T:
1165 case CX88_BOARD_DNTV_LIVE_DVB_T:
a82decf6 1166 case CX88_BOARD_ADSTECH_DVB_T_PCI:
363c35fc 1167 fe0->dvb.frontend = dvb_attach(mt352_attach,
f7b54b10 1168 &dntv_live_dvbt_config,
0590d91c 1169 &core->i2c_adap);
363c35fc
ST		 1170 if (fe0->dvb.frontend != NULL) {
1171 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend,
0590d91c
MCC		 1172 0x61, NULL, DVB_PLL_UNKNOWN_1))
1173 goto frontend_detach;
f54376e2 1174 }
1da177e4 1175 break;
fc40b261 1176 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
7b34be71 1177#if IS_ENABLED(CONFIG_VIDEO_CX88_VP3054)
f0ad9097 1178 /* MT352 is on a secondary I2C bus made from some GPIO lines */
363c35fc 1179 fe0->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
f0ad9097 1180 &dev->vp3054->adap);
363c35fc
ST		 1181 if (fe0->dvb.frontend != NULL) {
1182 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1183 &core->i2c_adap, 0x61,
1184 TUNER_PHILIPS_FMD1216ME_MK3))
1185 goto frontend_detach;
f54376e2 1186 }
fc40b261 1187#else
0590d91c
MCC		 1188 printk(KERN_ERR "%s/2: built without vp3054 support\n",
1189 core->name);
fc40b261
CP		 1190#endif
1191 break;
780dfef3 1192 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
363c35fc 1193 fe0->dvb.frontend = dvb_attach(zl10353_attach,
f7b54b10 1194 &dvico_fusionhdtv_hybrid,
0590d91c 1195 &core->i2c_adap);
363c35fc
ST		 1196 if (fe0->dvb.frontend != NULL) {
1197 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1198 &core->i2c_adap, 0x61,
1199 TUNER_THOMSON_FE6600))
1200 goto frontend_detach;
f54376e2 1201 }
780dfef3 1202 break;
b3fb91d2 1203 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
363c35fc 1204 fe0->dvb.frontend = dvb_attach(zl10353_attach,
b3fb91d2 1205 &dvico_fusionhdtv_xc3028,
0590d91c 1206 &core->i2c_adap);
363c35fc
ST		 1207 if (fe0->dvb.frontend == NULL)
1208 fe0->dvb.frontend = dvb_attach(mt352_attach,
b3fb91d2 1209 &dvico_fusionhdtv_mt352_xc3028,
0590d91c 1210 &core->i2c_adap);
8765561f
CP		 1211 /*
1212 * On this board, the demod provides the I2C bus pullup.
1213 * We must not permit gate_ctrl to be performed, or
1214 * the xc3028 cannot communicate on the bus.
1215 */
363c35fc
ST		 1216 if (fe0->dvb.frontend)
1217 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
23fb348d 1218 if (attach_xc3028(0x61, dev) < 0)
becd4305 1219 goto frontend_detach;
b3fb91d2 1220 break;
1da177e4 1221 case CX88_BOARD_PCHDTV_HD3000:
363c35fc 1222 fe0->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
0590d91c 1223 &core->i2c_adap);
363c35fc
ST		 1224 if (fe0->dvb.frontend != NULL) {
1225 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1226 &core->i2c_adap, 0x61,
1227 TUNER_THOMSON_DTT761X))
1228 goto frontend_detach;
f54376e2 1229 }
1da177e4 1230 break;
f1798495
MK		 1231 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
1232 dev->ts_gen_cntrl = 0x08;
f1798495 1233
0590d91c 1234 /* Do a hardware reset of chip before using it. */
f1798495
MK		 1235 cx_clear(MO_GP0_IO, 1);
1236 mdelay(100);
0ccef6db 1237 cx_set(MO_GP0_IO, 1);
f1798495 1238 mdelay(200);
0ccef6db
MK		 1239
1240 /* Select RF connector callback */
6ddcc919 1241 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
363c35fc 1242 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1243 &fusionhdtv_3_gold,
0590d91c 1244 &core->i2c_adap);
363c35fc
ST		 1245 if (fe0->dvb.frontend != NULL) {
1246 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1247 &core->i2c_adap, 0x61,
1248 TUNER_MICROTUNE_4042FI5))
1249 goto frontend_detach;
f1798495
MK		 1250 }
1251 break;
0d723c09
MK		 1252 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
1253 dev->ts_gen_cntrl = 0x08;
0d723c09 1254
0590d91c 1255 /* Do a hardware reset of chip before using it. */
0d723c09
MK		 1256 cx_clear(MO_GP0_IO, 1);
1257 mdelay(100);
d975872c 1258 cx_set(MO_GP0_IO, 9);
0d723c09 1259 mdelay(200);
363c35fc 1260 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1261 &fusionhdtv_3_gold,
0590d91c 1262 &core->i2c_adap);
363c35fc
ST		 1263 if (fe0->dvb.frontend != NULL) {
1264 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1265 &core->i2c_adap, 0x61,
1266 TUNER_THOMSON_DTT761X))
1267 goto frontend_detach;
0d723c09
MK		 1268 }
1269 break;
e52e98a7
MCC		 1270 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
1271 dev->ts_gen_cntrl = 0x08;
e52e98a7 1272
0590d91c 1273 /* Do a hardware reset of chip before using it. */
e52e98a7
MCC		 1274 cx_clear(MO_GP0_IO, 1);
1275 mdelay(100);
1276 cx_set(MO_GP0_IO, 1);
1277 mdelay(200);
363c35fc 1278 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1279 &fusionhdtv_5_gold,
0590d91c 1280 &core->i2c_adap);
363c35fc
ST		 1281 if (fe0->dvb.frontend != NULL) {
1282 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1283 &core->i2c_adap, 0x61,
1284 TUNER_LG_TDVS_H06XF))
1285 goto frontend_detach;
363c35fc 1286 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
0590d91c
MCC		 1287 &core->i2c_adap, 0x43))
1288 goto frontend_detach;
e52e98a7
MCC		 1289 }
1290 break;
da215d22
RS		 1291 case CX88_BOARD_PCHDTV_HD5500:
1292 dev->ts_gen_cntrl = 0x08;
da215d22 1293
0590d91c 1294 /* Do a hardware reset of chip before using it. */
da215d22
RS		 1295 cx_clear(MO_GP0_IO, 1);
1296 mdelay(100);
1297 cx_set(MO_GP0_IO, 1);
1298 mdelay(200);
363c35fc 1299 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
f7b54b10 1300 &pchdtv_hd5500,
0590d91c 1301 &core->i2c_adap);
363c35fc
ST		 1302 if (fe0->dvb.frontend != NULL) {
1303 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1304 &core->i2c_adap, 0x61,
1305 TUNER_LG_TDVS_H06XF))
1306 goto frontend_detach;
363c35fc 1307 if (!dvb_attach(tda9887_attach, fe0->dvb.frontend,
0590d91c
MCC		 1308 &core->i2c_adap, 0x43))
1309 goto frontend_detach;
da215d22
RS		 1310 }
1311 break;
fde6d31e 1312 case CX88_BOARD_ATI_HDTVWONDER:
363c35fc 1313 fe0->dvb.frontend = dvb_attach(nxt200x_attach,
f7b54b10 1314 &ati_hdtvwonder,
0590d91c 1315 &core->i2c_adap);
363c35fc
ST		 1316 if (fe0->dvb.frontend != NULL) {
1317 if (!dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
0590d91c
MCC		 1318 &core->i2c_adap, 0x61,
1319 TUNER_PHILIPS_TUV1236D))
1320 goto frontend_detach;
f54376e2 1321 }
0fa14aa6 1322 break;
0fa14aa6
ST		 1323 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
1324 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
363c35fc 1325 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1326 &hauppauge_novas_config,
0590d91c 1327 &core->i2c_adap);
363c35fc 1328 if (fe0->dvb.frontend) {
48a8a03b
MCC		 1329 bool override_tone;
1330
1331 if (core->model == 92001)
1332 override_tone = true;
1333 else
1334 override_tone = false;
1335
363c35fc 1336 if (!dvb_attach(isl6421_attach, fe0->dvb.frontend,
48a8a03b
MCC		 1337 &core->i2c_adap, 0x08, ISL6421_DCL, 0x00,
1338 override_tone))
0590d91c 1339 goto frontend_detach;
cd20ca9f 1340 }
0e0351e3
VC		 1341 break;
1342 case CX88_BOARD_KWORLD_DVBS_100:
363c35fc 1343 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1344 &kworld_dvbs_100_config,
0590d91c 1345 &core->i2c_adap);
363c35fc
ST		 1346 if (fe0->dvb.frontend) {
1347 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1348 fe0->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
cd20ca9f 1349 }
fde6d31e 1350 break;
c02a34f4 1351 case CX88_BOARD_GENIATECH_DVBS:
363c35fc 1352 fe0->dvb.frontend = dvb_attach(cx24123_attach,
f7b54b10 1353 &geniatech_dvbs_config,
0590d91c 1354 &core->i2c_adap);
363c35fc
ST		 1355 if (fe0->dvb.frontend) {
1356 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1357 fe0->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
c02a34f4
SA		 1358 }
1359 break;
60464da8 1360 case CX88_BOARD_PINNACLE_PCTV_HD_800i:
363c35fc 1361 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
60464da8 1362 &pinnacle_pctv_hd_800i_config,
0590d91c 1363 &core->i2c_adap);
363c35fc
ST		 1364 if (fe0->dvb.frontend != NULL) {
1365 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1366 &core->i2c_adap,
30650961 1367 &pinnacle_pctv_hd_800i_tuner_config))
0590d91c 1368 goto frontend_detach;
60464da8
ST		 1369 }
1370 break;
5c00fac0 1371 case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
363c35fc 1372 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
5c00fac0 1373 &dvico_hdtv5_pci_nano_config,
0590d91c 1374 &core->i2c_adap);
363c35fc 1375 if (fe0->dvb.frontend != NULL) {
5c00fac0
ST		 1376 struct dvb_frontend *fe;
1377 struct xc2028_config cfg = {
0590d91c 1378 .i2c_adap = &core->i2c_adap,
5c00fac0 1379 .i2c_addr = 0x61,
5c00fac0
ST		 1380 };
1381 static struct xc2028_ctrl ctl = {
ef80bfeb 1382 .fname = XC2028_DEFAULT_FIRMWARE,
5c00fac0 1383 .max_len = 64,
33e53161 1384 .scode_table = XC3028_FE_OREN538,
5c00fac0
ST		 1385 };
1386
1387 fe = dvb_attach(xc2028_attach,
363c35fc 1388 fe0->dvb.frontend, &cfg);
5c00fac0
ST		 1389 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1390 fe->ops.tuner_ops.set_config(fe, &ctl);
1391 }
1392 break;
d49f7a24 1393 case CX88_BOARD_PINNACLE_HYBRID_PCTV:
3047a176 1394 case CX88_BOARD_WINFAST_DTV1800H:
363c35fc 1395 fe0->dvb.frontend = dvb_attach(zl10353_attach,
3f6014fc 1396 &cx88_pinnacle_hybrid_pctv,
0590d91c 1397 &core->i2c_adap);
363c35fc
ST		 1398 if (fe0->dvb.frontend) {
1399 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
3f6014fc
SV		 1400 if (attach_xc3028(0x61, dev) < 0)
1401 goto frontend_detach;
1402 }
9507901e 1403 break;
8eb79c0b 1404 case CX88_BOARD_WINFAST_DTV1800H_XC4000:
f271a3af 1405 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1406 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1407 &cx88_pinnacle_hybrid_pctv,
1408 &core->i2c_adap);
1409 if (fe0->dvb.frontend) {
1410 struct xc4000_config cfg = {
1411 .i2c_address = 0x61,
1412 .default_pm = 0,
1413 .dvb_amplitude = 134,
1414 .set_smoothedcvbs = 1,
1415 .if_khz = 4560
1416 };
1417 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1418 if (attach_xc4000(dev, &cfg) < 0)
1419 goto frontend_detach;
1420 }
1421 break;
1422 case CX88_BOARD_GENIATECH_X8000_MT:
99e09eac 1423 dev->ts_gen_cntrl = 0x00;
9507901e 1424
363c35fc 1425 fe0->dvb.frontend = dvb_attach(zl10353_attach,
9507901e 1426 &cx88_geniatech_x8000_mt,
0590d91c 1427 &core->i2c_adap);
23fb348d 1428 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1429 goto frontend_detach;
9507901e 1430 break;
99e09eac 1431 case CX88_BOARD_KWORLD_ATSC_120:
363c35fc 1432 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
99e09eac 1433 &kworld_atsc_120_config,
0590d91c 1434 &core->i2c_adap);
99e09eac 1435 if (attach_xc3028(0x61, dev) < 0)
0590d91c 1436 goto frontend_detach;
99e09eac 1437 break;
d893d5dc 1438 case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD:
363c35fc 1439 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
d893d5dc 1440 &dvico_fusionhdtv7_config,
0590d91c 1441 &core->i2c_adap);
363c35fc
ST		 1442 if (fe0->dvb.frontend != NULL) {
1443 if (!dvb_attach(xc5000_attach, fe0->dvb.frontend,
0590d91c 1444 &core->i2c_adap,
30650961 1445 &dvico_fusionhdtv7_tuner_config))
0590d91c 1446 goto frontend_detach;
d893d5dc
ST		 1447 }
1448 break;
5bd1b663 1449 case CX88_BOARD_HAUPPAUGE_HVR4000:
60a5a927
DB		 1450 /* MFE frontend 1 */
1451 mfe_shared = 1;
1452 dev->frontends.gate = 2;
363c35fc
ST		 1453 /* DVB-S/S2 Init */
1454 fe0->dvb.frontend = dvb_attach(cx24116_attach,
60a5a927
DB		 1455 &hauppauge_hvr4000_config,
1456 &dev->core->i2c_adap);
363c35fc 1457 if (fe0->dvb.frontend) {
60a5a927
DB		 1458 if (!dvb_attach(isl6421_attach,
1459 fe0->dvb.frontend,
1460 &dev->core->i2c_adap,
48a8a03b 1461 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1462 goto frontend_detach;
363c35fc 1463 }
60a5a927 1464 /* MFE frontend 2 */
0b6b6302 1465 fe1 = vb2_dvb_get_frontend(&dev->frontends, 2);
60a5a927
DB		 1466 if (!fe1)
1467 goto frontend_detach;
1468 /* DVB-T Init */
1469 fe1->dvb.frontend = dvb_attach(cx22702_attach,
1470 &hauppauge_hvr_config,
1471 &dev->core->i2c_adap);
1472 if (fe1->dvb.frontend) {
1473 fe1->dvb.frontend->id = 1;
1474 if (!dvb_attach(simple_tuner_attach,
1475 fe1->dvb.frontend,
1476 &dev->core->i2c_adap,
1477 0x61, TUNER_PHILIPS_FMD1216ME_MK3))
1478 goto frontend_detach;
363c35fc
ST		 1479 }
1480 break;
5bd1b663 1481 case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
363c35fc 1482 fe0->dvb.frontend = dvb_attach(cx24116_attach,
60a5a927
DB		 1483 &hauppauge_hvr4000_config,
1484 &dev->core->i2c_adap);
363c35fc 1485 if (fe0->dvb.frontend) {
60a5a927
DB		 1486 if (!dvb_attach(isl6421_attach,
1487 fe0->dvb.frontend,
1488 &dev->core->i2c_adap,
48a8a03b 1489 0x08, ISL6421_DCL, 0x00, false))
60a5a927 1490 goto frontend_detach;
5bd1b663
ST		 1491 }
1492 break;
cd3cde12 1493 case CX88_BOARD_PROF_6200:
4b29631d 1494 case CX88_BOARD_TBS_8910:
e4aab64c 1495 case CX88_BOARD_TEVII_S420:
363c35fc 1496 fe0->dvb.frontend = dvb_attach(stv0299_attach,
e4aab64c
IL		 1497 &tevii_tuner_sharp_config,
1498 &core->i2c_adap);
363c35fc
ST		 1499 if (fe0->dvb.frontend != NULL) {
1500 if (!dvb_attach(dvb_pll_attach, fe0->dvb.frontend, 0x60,
e4aab64c
IL		 1501 &core->i2c_adap, DVB_PLL_OPERA1))
1502 goto frontend_detach;
363c35fc
ST		 1503 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1504 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL		 1505
1506 } else {
363c35fc 1507 fe0->dvb.frontend = dvb_attach(stv0288_attach,
e4aab64c
IL		 1508 &tevii_tuner_earda_config,
1509 &core->i2c_adap);
86c330fa
MCC		 1510 if (fe0->dvb.frontend != NULL) {
1511 if (!dvb_attach(stb6000_attach, fe0->dvb.frontend, 0x61,
e4aab64c
IL		 1512 &core->i2c_adap))
1513 goto frontend_detach;
363c35fc
ST		 1514 core->prev_set_voltage = fe0->dvb.frontend->ops.set_voltage;
1515 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
e4aab64c
IL		 1516 }
1517 }
1518 break;
af832623 1519 case CX88_BOARD_TEVII_S460:
363c35fc 1520 fe0->dvb.frontend = dvb_attach(cx24116_attach,
af832623
IL		 1521 &tevii_s460_config,
1522 &core->i2c_adap);
93f26c14 1523 if (fe0->dvb.frontend != NULL)
363c35fc 1524 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
4cd7fb87 1525 break;
0cb73639
IL		 1526 case CX88_BOARD_TEVII_S464:
1527 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1528 &tevii_ds3000_config,
1529 &core->i2c_adap);
73f0af44
KD		 1530 if (fe0->dvb.frontend != NULL) {
1531 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1532 &tevii_ts2020_config, &core->i2c_adap);
0cb73639
IL		 1533 fe0->dvb.frontend->ops.set_voltage =
1534 tevii_dvbs_set_voltage;
73f0af44 1535 }
0cb73639 1536 break;
4cd7fb87 1537 case CX88_BOARD_OMICOM_SS4_PCI:
ee73042c 1538 case CX88_BOARD_TBS_8920:
57f51dbc 1539 case CX88_BOARD_PROF_7300:
4b29631d 1540 case CX88_BOARD_SATTRADE_ST4200:
363c35fc 1541 fe0->dvb.frontend = dvb_attach(cx24116_attach,
ee73042c
OR		 1542 &hauppauge_hvr4000_config,
1543 &core->i2c_adap);
93f26c14 1544 if (fe0->dvb.frontend != NULL)
363c35fc 1545 fe0->dvb.frontend->ops.set_voltage = tevii_dvbs_set_voltage;
af832623 1546 break;
70101a27
SW		 1547 case CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII:
1548 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1549 &cx88_terratec_cinergy_ht_pci_mkii_config,
1550 &core->i2c_adap);
1551 if (fe0->dvb.frontend) {
1552 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
1553 if (attach_xc3028(0x61, dev) < 0)
1554 goto frontend_detach;
1555 }
1556 break;
b699c271
IL		 1557 case CX88_BOARD_PROF_7301:{
1558 struct dvb_tuner_ops *tuner_ops = NULL;
1559
1560 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1561 &prof_7301_stv0900_config,
1562 &core->i2c_adap, 0);
1563 if (fe0->dvb.frontend != NULL) {
1564 if (!dvb_attach(stb6100_attach, fe0->dvb.frontend,
1565 &prof_7301_stb6100_config,
1566 &core->i2c_adap))
1567 goto frontend_detach;
1568
1569 tuner_ops = &fe0->dvb.frontend->ops.tuner_ops;
1570 tuner_ops->set_frequency = stb6100_set_freq;
1571 tuner_ops->get_frequency = stb6100_get_freq;
1572 tuner_ops->set_bandwidth = stb6100_set_bandw;
1573 tuner_ops->get_bandwidth = stb6100_get_bandw;
1574
1575 core->prev_set_voltage =
1576 fe0->dvb.frontend->ops.set_voltage;
1577 fe0->dvb.frontend->ops.set_voltage =
1578 tevii_dvbs_set_voltage;
1579 }
1580 break;
1581 }
4f3ca2f1
DH		 1582 case CX88_BOARD_SAMSUNG_SMT_7020:
1583 dev->ts_gen_cntrl = 0x08;
1584
4f3ca2f1
DH		 1585 cx_set(MO_GP0_IO, 0x0101);
1586
1587 cx_clear(MO_GP0_IO, 0x01);
1588 mdelay(100);
1589 cx_set(MO_GP0_IO, 0x01);
1590 mdelay(200);
1591
1592 fe0->dvb.frontend = dvb_attach(stv0299_attach,
1593 &samsung_stv0299_config,
1594 &dev->core->i2c_adap);
1595 if (fe0->dvb.frontend) {
1596 fe0->dvb.frontend->ops.tuner_ops.set_params =
1597 samsung_smt_7020_tuner_set_params;
1598 fe0->dvb.frontend->tuner_priv =
1599 &dev->core->i2c_adap;
1600 fe0->dvb.frontend->ops.set_voltage =
1601 samsung_smt_7020_set_voltage;
1602 fe0->dvb.frontend->ops.set_tone =
1603 samsung_smt_7020_set_tone;
1604 }
1605
1606 break;
111ac84a
SI		 1607 case CX88_BOARD_TWINHAN_VP1027_DVBS:
1608 dev->ts_gen_cntrl = 0x00;
1609 fe0->dvb.frontend = dvb_attach(mb86a16_attach,
1610 &twinhan_vp1027,
1611 &core->i2c_adap);
1612 if (fe0->dvb.frontend) {
1613 core->prev_set_voltage =
1614 fe0->dvb.frontend->ops.set_voltage;
1615 fe0->dvb.frontend->ops.set_voltage =
1616 vp1027_set_voltage;
1617 }
1618 break;
4f3ca2f1 1619
1da177e4 1620 default:
5772f813 1621 printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
0590d91c 1622 core->name);
1da177e4
LT		 1623 break;
1624 }
363c35fc 1625
2c9bcea1 1626 if ( (NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend) ) {
9507901e
MCC		 1627 printk(KERN_ERR
1628 "%s/2: frontend initialization failed\n",
0590d91c 1629 core->name);
60a5a927 1630 goto frontend_detach;
9507901e 1631 }
d7cba043 1632 /* define general-purpose callback pointer */
363c35fc 1633 fe0->dvb.frontend->callback = cx88_tuner_callback;
9507901e 1634
6c5be74c 1635 /* Ensure all frontends negotiate bus access */
363c35fc
ST		 1636 fe0->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1637 if (fe1)
1638 fe1->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
1da177e4 1639
93352f5c 1640 /* Put the analog decoder in standby to keep it quiet */
622b828a 1641 call_all(core, core, s_power, 0);
93352f5c 1642
1da177e4 1643 /* register everything */
0b6b6302 1644 res = vb2_dvb_register_bus(&dev->frontends, THIS_MODULE, dev,
2773b0e9
MCC		 1645 &dev->pci->dev, NULL, adapter_nr,
1646 mfe_shared);
7b0962d3
DF		 1647 if (res)
1648 goto frontend_detach;
1649 return res;
0590d91c
MCC		 1650
1651frontend_detach:
e32fadc4 1652 core->gate_ctrl = NULL;
0b6b6302 1653 vb2_dvb_dealloc_frontends(&dev->frontends);
7b0962d3 1654 return res;
1da177e4
LT		 1655}
1656
1657/* ----------------------------------------------------------- */
1658
6c5be74c
ST		 1659/* CX8802 MPEG -> mini driver - We have been given the hardware */
1660static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
1da177e4 1661{
6c5be74c
ST		 1662 struct cx88_core *core = drv->core;
1663 int err = 0;
32d83efc 1664 dprintk( 1, "%s\n", __func__);
6c5be74c 1665
6a59d64c 1666 switch (core->boardnr) {
6c5be74c
ST		 1667 case CX88_BOARD_HAUPPAUGE_HVR1300:
1668 /* We arrive here with either the cx23416 or the cx22702
1669 * on the bus. Take the bus from the cx23416 and enable the
1670 * cx22702 demod
1671 */
79392737
DB		 1672 /* Toggle reset on cx22702 leaving i2c active */
1673 cx_set(MO_GP0_IO, 0x00000080);
1674 udelay(1000);
1675 cx_clear(MO_GP0_IO, 0x00000080);
1676 udelay(50);
1677 cx_set(MO_GP0_IO, 0x00000080);
1678 udelay(1000);
1679 /* enable the cx22702 pins */
6c5be74c
ST		 1680 cx_clear(MO_GP0_IO, 0x00000004);
1681 udelay(1000);
1682 break;
363c35fc 1683
92abe9ee 1684 case CX88_BOARD_HAUPPAUGE_HVR3000:
363c35fc 1685 case CX88_BOARD_HAUPPAUGE_HVR4000:
79392737
DB		 1686 /* Toggle reset on cx22702 leaving i2c active */
1687 cx_set(MO_GP0_IO, 0x00000080);
1688 udelay(1000);
1689 cx_clear(MO_GP0_IO, 0x00000080);
1690 udelay(50);
1691 cx_set(MO_GP0_IO, 0x00000080);
1692 udelay(1000);
1693 switch (core->dvbdev->frontends.active_fe_id) {
1694 case 1: /* DVB-S/S2 Enabled */
1695 /* tri-state the cx22702 pins */
1696 cx_set(MO_GP0_IO, 0x00000004);
1697 /* Take the cx24116/cx24123 out of reset */
1698 cx_write(MO_SRST_IO, 1);
363c35fc 1699 core->dvbdev->ts_gen_cntrl = 0x02; /* Parallel IO */
79392737
DB		 1700 break;
1701 case 2: /* DVB-T Enabled */
363c35fc
ST		 1702 /* Put the cx24116/cx24123 into reset */
1703 cx_write(MO_SRST_IO, 0);
79392737 1704 /* enable the cx22702 pins */
363c35fc
ST		 1705 cx_clear(MO_GP0_IO, 0x00000004);
1706 core->dvbdev->ts_gen_cntrl = 0x0c; /* Serial IO */
79392737 1707 break;
363c35fc 1708 }
79392737 1709 udelay(1000);
363c35fc
ST		 1710 break;
1711
f271a3af 1712 case CX88_BOARD_WINFAST_DTV2000H_PLUS:
1713 /* set RF input to AIR for DVB-T (GPIO 16) */
1714 cx_write(MO_GP2_IO, 0x0101);
1715 break;
1716
6c5be74c
ST		 1717 default:
1718 err = -ENODEV;
1719 }
1720 return err;
1721}
1722
1723/* CX8802 MPEG -> mini driver - We no longer have the hardware */
1724static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
1725{
1726 struct cx88_core *core = drv->core;
1727 int err = 0;
32d83efc 1728 dprintk( 1, "%s\n", __func__);
6c5be74c 1729
6a59d64c 1730 switch (core->boardnr) {
6c5be74c
ST		 1731 case CX88_BOARD_HAUPPAUGE_HVR1300:
1732 /* Do Nothing, leave the cx22702 on the bus. */
1733 break;
363c35fc
ST		 1734 case CX88_BOARD_HAUPPAUGE_HVR3000:
1735 case CX88_BOARD_HAUPPAUGE_HVR4000:
1736 break;
6c5be74c
ST		 1737 default:
1738 err = -ENODEV;
1739 }
1740 return err;
1741}
1742
1743static int cx8802_dvb_probe(struct cx8802_driver *drv)
1744{
1745 struct cx88_core *core = drv->core;
1746 struct cx8802_dev *dev = drv->core->dvbdev;
cbd82441 1747 int err;
0b6b6302 1748 struct vb2_dvb_frontend *fe;
6e0e12f1 1749 int i;
1da177e4 1750
32d83efc 1751 dprintk( 1, "%s\n", __func__);
6c5be74c 1752 dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
6a59d64c 1753 core->boardnr,
6c5be74c
ST		 1754 core->name,
1755 core->pci_bus,
1756 core->pci_slot);
1da177e4
LT		 1757
1758 err = -ENODEV;
6a59d64c 1759 if (!(core->board.mpeg & CX88_MPEG_DVB))
1da177e4
LT		 1760 goto fail_core;
1761
ecf854df 1762 /* If vp3054 isn't enabled, a stub will just return 0 */
fc40b261
CP		 1763 err = vp3054_i2c_probe(dev);
1764 if (0 != err)
6e0e12f1 1765 goto fail_core;
fc40b261 1766
1da177e4 1767 /* dvb stuff */
5772f813 1768 printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
363c35fc
ST		 1769 dev->ts_gen_cntrl = 0x0c;
1770
6e0e12f1
AW		 1771 err = cx8802_alloc_frontends(dev);
1772 if (err)
1773 goto fail_core;
1774
cbd82441 1775 err = -ENODEV;
6e0e12f1 1776 for (i = 1; i <= core->board.num_frontends; i++) {
0b6b6302
HV		 1777 struct vb2_queue *q;
1778
1779 fe = vb2_dvb_get_frontend(&core->dvbdev->frontends, i);
6e0e12f1
AW		 1780 if (fe == NULL) {
1781 printk(KERN_ERR "%s() failed to get frontend(%d)\n",
cbd82441 1782 __func__, i);
6e0e12f1
AW		 1783 goto fail_probe;
1784 }
0b6b6302
HV		 1785 q = &fe->dvb.dvbq;
1786 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1787 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1788 q->gfp_flags = GFP_DMA32;
1789 q->min_buffers_needed = 2;
1790 q->drv_priv = dev;
1791 q->buf_struct_size = sizeof(struct cx88_buffer);
1792 q->ops = &dvb_qops;
1793 q->mem_ops = &vb2_dma_sg_memops;
1794 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1795 q->lock = &core->lock;
1796
1797 err = vb2_queue_init(q);
1798 if (err < 0)
1799 goto fail_probe;
1800
1801 /* init struct vb2_dvb */
6e0e12f1 1802 fe->dvb.name = dev->core->name;
363c35fc 1803 }
6e0e12f1 1804
1da177e4 1805 err = dvb_register(dev);
cbd82441
DB		 1806 if (err)
1807 /* frontends/adapter de-allocated in dvb_register */
5772f813
TP		 1808 printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
1809 core->name, err);
cbd82441
DB		 1810 return err;
1811fail_probe:
0b6b6302 1812 vb2_dvb_dealloc_frontends(&core->dvbdev->frontends);
92abe9ee 1813fail_core:
1da177e4
LT		 1814 return err;
1815}
1816
6c5be74c 1817static int cx8802_dvb_remove(struct cx8802_driver *drv)
1da177e4 1818{
0fcd488d 1819 struct cx88_core *core = drv->core;
6c5be74c 1820 struct cx8802_dev *dev = drv->core->dvbdev;
611900c1 1821
0fcd488d
DB		 1822 dprintk( 1, "%s\n", __func__);
1823
0b6b6302 1824 vb2_dvb_unregister_bus(&dev->frontends);
1da177e4 1825
fc40b261 1826 vp3054_i2c_remove(dev);
fc40b261 1827
e32fadc4
MCC		 1828 core->gate_ctrl = NULL;
1829
6c5be74c 1830 return 0;
1da177e4
LT		 1831}
1832
6c5be74c
ST		 1833static struct cx8802_driver cx8802_dvb_driver = {
1834 .type_id = CX88_MPEG_DVB,
1835 .hw_access = CX8802_DRVCTL_SHARED,
1836 .probe = cx8802_dvb_probe,
1837 .remove = cx8802_dvb_remove,
1838 .advise_acquire = cx8802_dvb_advise_acquire,
1839 .advise_release = cx8802_dvb_advise_release,
1da177e4
LT		 1840};
1841
31d0f845 1842static int __init dvb_init(void)
1da177e4 1843{
1990d50b
MCC		 1844 printk(KERN_INFO "cx88/2: cx2388x dvb driver version %s loaded\n",
1845 CX88_VERSION);
6c5be74c 1846 return cx8802_register_driver(&cx8802_dvb_driver);
1da177e4
LT		 1847}
1848
31d0f845 1849static void __exit dvb_fini(void)
1da177e4 1850{
6c5be74c 1851 cx8802_unregister_driver(&cx8802_dvb_driver);
1da177e4
LT		 1852}
1853
1854module_init(dvb_init);
1855module_exit(dvb_fini);
Linux kernel - Deliverables
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