Commit | Line | Data |
---|---|---|
89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/init.h> | |
a6b7a407 | 19 | #include <linux/interrupt.h> |
89e5785f HS |
20 | #include <linux/netdevice.h> |
21 | #include <linux/etherdevice.h> | |
89e5785f | 22 | #include <linux/dma-mapping.h> |
84e0cdb0 | 23 | #include <linux/platform_data/macb.h> |
89e5785f | 24 | #include <linux/platform_device.h> |
6c36a707 | 25 | #include <linux/phy.h> |
b17471f5 | 26 | #include <linux/of.h> |
fb97a846 JCPV |
27 | #include <linux/of_device.h> |
28 | #include <linux/of_net.h> | |
89e5785f | 29 | |
89e5785f HS |
30 | #include "macb.h" |
31 | ||
89e5785f | 32 | #define RX_BUFFER_SIZE 128 |
55054a16 HS |
33 | #define RX_RING_SIZE 512 /* must be power of 2 */ |
34 | #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE) | |
89e5785f | 35 | |
55054a16 HS |
36 | #define TX_RING_SIZE 128 /* must be power of 2 */ |
37 | #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE) | |
89e5785f HS |
38 | |
39 | /* minimum number of free TX descriptors before waking up TX process */ | |
40 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
41 | ||
42 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
43 | | MACB_BIT(ISR_ROVR)) | |
e86cd53a NF |
44 | #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ |
45 | | MACB_BIT(ISR_RLE) \ | |
46 | | MACB_BIT(TXERR)) | |
47 | #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) | |
48 | ||
49 | /* | |
50 | * Graceful stop timeouts in us. We should allow up to | |
51 | * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) | |
52 | */ | |
53 | #define MACB_HALT_TIMEOUT 1230 | |
89e5785f | 54 | |
55054a16 HS |
55 | /* Ring buffer accessors */ |
56 | static unsigned int macb_tx_ring_wrap(unsigned int index) | |
57 | { | |
58 | return index & (TX_RING_SIZE - 1); | |
59 | } | |
60 | ||
61 | static unsigned int macb_tx_ring_avail(struct macb *bp) | |
62 | { | |
63 | return (bp->tx_tail - bp->tx_head) & (TX_RING_SIZE - 1); | |
64 | } | |
65 | ||
66 | static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index) | |
67 | { | |
68 | return &bp->tx_ring[macb_tx_ring_wrap(index)]; | |
69 | } | |
70 | ||
71 | static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index) | |
72 | { | |
73 | return &bp->tx_skb[macb_tx_ring_wrap(index)]; | |
74 | } | |
75 | ||
76 | static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index) | |
77 | { | |
78 | dma_addr_t offset; | |
79 | ||
80 | offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc); | |
81 | ||
82 | return bp->tx_ring_dma + offset; | |
83 | } | |
84 | ||
85 | static unsigned int macb_rx_ring_wrap(unsigned int index) | |
86 | { | |
87 | return index & (RX_RING_SIZE - 1); | |
88 | } | |
89 | ||
90 | static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) | |
91 | { | |
92 | return &bp->rx_ring[macb_rx_ring_wrap(index)]; | |
93 | } | |
94 | ||
95 | static void *macb_rx_buffer(struct macb *bp, unsigned int index) | |
96 | { | |
97 | return bp->rx_buffers + RX_BUFFER_SIZE * macb_rx_ring_wrap(index); | |
98 | } | |
99 | ||
89e5785f HS |
100 | static void __macb_set_hwaddr(struct macb *bp) |
101 | { | |
102 | u32 bottom; | |
103 | u16 top; | |
104 | ||
105 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 106 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 107 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 108 | macb_or_gem_writel(bp, SA1T, top); |
89e5785f HS |
109 | } |
110 | ||
111 | static void __init macb_get_hwaddr(struct macb *bp) | |
112 | { | |
113 | u32 bottom; | |
114 | u16 top; | |
115 | u8 addr[6]; | |
116 | ||
f75ba50b JI |
117 | bottom = macb_or_gem_readl(bp, SA1B); |
118 | top = macb_or_gem_readl(bp, SA1T); | |
89e5785f HS |
119 | |
120 | addr[0] = bottom & 0xff; | |
121 | addr[1] = (bottom >> 8) & 0xff; | |
122 | addr[2] = (bottom >> 16) & 0xff; | |
123 | addr[3] = (bottom >> 24) & 0xff; | |
124 | addr[4] = top & 0xff; | |
125 | addr[5] = (top >> 8) & 0xff; | |
126 | ||
d1d5741d | 127 | if (is_valid_ether_addr(addr)) { |
89e5785f | 128 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); |
d1d5741d | 129 | } else { |
c220f8cd | 130 | netdev_info(bp->dev, "invalid hw address, using random\n"); |
f2cedb63 | 131 | eth_hw_addr_random(bp->dev); |
d1d5741d | 132 | } |
89e5785f HS |
133 | } |
134 | ||
6c36a707 | 135 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 136 | { |
6c36a707 | 137 | struct macb *bp = bus->priv; |
89e5785f HS |
138 | int value; |
139 | ||
89e5785f HS |
140 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
141 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
142 | | MACB_BF(PHYA, mii_id) |
143 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
144 | | MACB_BF(CODE, MACB_MAN_CODE))); |
145 | ||
6c36a707 R |
146 | /* wait for end of transfer */ |
147 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
148 | cpu_relax(); | |
89e5785f HS |
149 | |
150 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
151 | |
152 | return value; | |
153 | } | |
154 | ||
6c36a707 R |
155 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
156 | u16 value) | |
89e5785f | 157 | { |
6c36a707 | 158 | struct macb *bp = bus->priv; |
89e5785f HS |
159 | |
160 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
161 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
162 | | MACB_BF(PHYA, mii_id) |
163 | | MACB_BF(REGA, regnum) | |
89e5785f | 164 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 165 | | MACB_BF(DATA, value))); |
89e5785f | 166 | |
6c36a707 R |
167 | /* wait for end of transfer */ |
168 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
169 | cpu_relax(); | |
170 | ||
171 | return 0; | |
172 | } | |
89e5785f | 173 | |
6c36a707 R |
174 | static int macb_mdio_reset(struct mii_bus *bus) |
175 | { | |
176 | return 0; | |
89e5785f HS |
177 | } |
178 | ||
6c36a707 | 179 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 180 | { |
6c36a707 R |
181 | struct macb *bp = netdev_priv(dev); |
182 | struct phy_device *phydev = bp->phy_dev; | |
183 | unsigned long flags; | |
89e5785f | 184 | |
6c36a707 | 185 | int status_change = 0; |
89e5785f | 186 | |
6c36a707 R |
187 | spin_lock_irqsave(&bp->lock, flags); |
188 | ||
189 | if (phydev->link) { | |
190 | if ((bp->speed != phydev->speed) || | |
191 | (bp->duplex != phydev->duplex)) { | |
192 | u32 reg; | |
193 | ||
194 | reg = macb_readl(bp, NCFGR); | |
195 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
140b7552 PV |
196 | if (macb_is_gem(bp)) |
197 | reg &= ~GEM_BIT(GBE); | |
6c36a707 R |
198 | |
199 | if (phydev->duplex) | |
200 | reg |= MACB_BIT(FD); | |
179956f4 | 201 | if (phydev->speed == SPEED_100) |
6c36a707 | 202 | reg |= MACB_BIT(SPD); |
140b7552 PV |
203 | if (phydev->speed == SPEED_1000) |
204 | reg |= GEM_BIT(GBE); | |
6c36a707 | 205 | |
140b7552 | 206 | macb_or_gem_writel(bp, NCFGR, reg); |
6c36a707 R |
207 | |
208 | bp->speed = phydev->speed; | |
209 | bp->duplex = phydev->duplex; | |
210 | status_change = 1; | |
211 | } | |
89e5785f HS |
212 | } |
213 | ||
6c36a707 | 214 | if (phydev->link != bp->link) { |
c8f15686 | 215 | if (!phydev->link) { |
6c36a707 R |
216 | bp->speed = 0; |
217 | bp->duplex = -1; | |
218 | } | |
219 | bp->link = phydev->link; | |
89e5785f | 220 | |
6c36a707 R |
221 | status_change = 1; |
222 | } | |
89e5785f | 223 | |
6c36a707 R |
224 | spin_unlock_irqrestore(&bp->lock, flags); |
225 | ||
226 | if (status_change) { | |
03fc4721 NF |
227 | if (phydev->link) { |
228 | netif_carrier_on(dev); | |
c220f8cd JI |
229 | netdev_info(dev, "link up (%d/%s)\n", |
230 | phydev->speed, | |
231 | phydev->duplex == DUPLEX_FULL ? | |
232 | "Full" : "Half"); | |
03fc4721 NF |
233 | } else { |
234 | netif_carrier_off(dev); | |
c220f8cd | 235 | netdev_info(dev, "link down\n"); |
03fc4721 | 236 | } |
6c36a707 | 237 | } |
89e5785f HS |
238 | } |
239 | ||
6c36a707 R |
240 | /* based on au1000_eth. c*/ |
241 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 242 | { |
6c36a707 | 243 | struct macb *bp = netdev_priv(dev); |
7455a76f | 244 | struct phy_device *phydev; |
7455a76f | 245 | int ret; |
6c36a707 | 246 | |
7455a76f | 247 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 248 | if (!phydev) { |
c220f8cd | 249 | netdev_err(dev, "no PHY found\n"); |
6c36a707 R |
250 | return -1; |
251 | } | |
252 | ||
6c36a707 R |
253 | /* TODO : add pin_irq */ |
254 | ||
255 | /* attach the mac to the phy */ | |
7455a76f | 256 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, |
fb97a846 | 257 | bp->phy_interface); |
7455a76f | 258 | if (ret) { |
c220f8cd | 259 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 260 | return ret; |
6c36a707 R |
261 | } |
262 | ||
263 | /* mask with MAC supported features */ | |
140b7552 PV |
264 | if (macb_is_gem(bp)) |
265 | phydev->supported &= PHY_GBIT_FEATURES; | |
266 | else | |
267 | phydev->supported &= PHY_BASIC_FEATURES; | |
6c36a707 R |
268 | |
269 | phydev->advertising = phydev->supported; | |
270 | ||
271 | bp->link = 0; | |
272 | bp->speed = 0; | |
273 | bp->duplex = -1; | |
274 | bp->phy_dev = phydev; | |
275 | ||
276 | return 0; | |
89e5785f HS |
277 | } |
278 | ||
0005f541 | 279 | int macb_mii_init(struct macb *bp) |
89e5785f | 280 | { |
84e0cdb0 | 281 | struct macb_platform_data *pdata; |
6c36a707 | 282 | int err = -ENXIO, i; |
89e5785f | 283 | |
3dbda77e | 284 | /* Enable management port */ |
6c36a707 | 285 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 286 | |
298cf9be LB |
287 | bp->mii_bus = mdiobus_alloc(); |
288 | if (bp->mii_bus == NULL) { | |
289 | err = -ENOMEM; | |
290 | goto err_out; | |
291 | } | |
292 | ||
293 | bp->mii_bus->name = "MACB_mii_bus"; | |
294 | bp->mii_bus->read = &macb_mdio_read; | |
295 | bp->mii_bus->write = &macb_mdio_write; | |
296 | bp->mii_bus->reset = &macb_mdio_reset; | |
98d5e57e FF |
297 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
298 | bp->pdev->name, bp->pdev->id); | |
298cf9be LB |
299 | bp->mii_bus->priv = bp; |
300 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 301 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 302 | |
6c36a707 | 303 | if (pdata) |
298cf9be | 304 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 305 | |
298cf9be LB |
306 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
307 | if (!bp->mii_bus->irq) { | |
6c36a707 | 308 | err = -ENOMEM; |
298cf9be | 309 | goto err_out_free_mdiobus; |
89e5785f HS |
310 | } |
311 | ||
6c36a707 | 312 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 313 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 314 | |
91523947 | 315 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 316 | |
298cf9be | 317 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 318 | goto err_out_free_mdio_irq; |
89e5785f | 319 | |
6c36a707 R |
320 | if (macb_mii_probe(bp->dev) != 0) { |
321 | goto err_out_unregister_bus; | |
322 | } | |
89e5785f | 323 | |
6c36a707 | 324 | return 0; |
89e5785f | 325 | |
6c36a707 | 326 | err_out_unregister_bus: |
298cf9be | 327 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 328 | err_out_free_mdio_irq: |
298cf9be LB |
329 | kfree(bp->mii_bus->irq); |
330 | err_out_free_mdiobus: | |
331 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
332 | err_out: |
333 | return err; | |
89e5785f | 334 | } |
0005f541 | 335 | EXPORT_SYMBOL_GPL(macb_mii_init); |
89e5785f HS |
336 | |
337 | static void macb_update_stats(struct macb *bp) | |
338 | { | |
339 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
a494ed8e JI |
340 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
341 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
89e5785f HS |
342 | |
343 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
344 | ||
345 | for(; p < end; p++, reg++) | |
0f0d84e5 | 346 | *p += __raw_readl(reg); |
89e5785f HS |
347 | } |
348 | ||
e86cd53a | 349 | static int macb_halt_tx(struct macb *bp) |
89e5785f | 350 | { |
e86cd53a NF |
351 | unsigned long halt_time, timeout; |
352 | u32 status; | |
89e5785f | 353 | |
e86cd53a | 354 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT)); |
89e5785f | 355 | |
e86cd53a NF |
356 | timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT); |
357 | do { | |
358 | halt_time = jiffies; | |
359 | status = macb_readl(bp, TSR); | |
360 | if (!(status & MACB_BIT(TGO))) | |
361 | return 0; | |
89e5785f | 362 | |
e86cd53a NF |
363 | usleep_range(10, 250); |
364 | } while (time_before(halt_time, timeout)); | |
bdcba151 | 365 | |
e86cd53a NF |
366 | return -ETIMEDOUT; |
367 | } | |
39eddb4c | 368 | |
e86cd53a NF |
369 | static void macb_tx_error_task(struct work_struct *work) |
370 | { | |
371 | struct macb *bp = container_of(work, struct macb, tx_error_task); | |
372 | struct macb_tx_skb *tx_skb; | |
373 | struct sk_buff *skb; | |
374 | unsigned int tail; | |
bdcba151 | 375 | |
e86cd53a NF |
376 | netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n", |
377 | bp->tx_tail, bp->tx_head); | |
bdcba151 | 378 | |
e86cd53a NF |
379 | /* Make sure nobody is trying to queue up new packets */ |
380 | netif_stop_queue(bp->dev); | |
d3e61457 | 381 | |
e86cd53a NF |
382 | /* |
383 | * Stop transmission now | |
384 | * (in case we have just queued new packets) | |
385 | */ | |
386 | if (macb_halt_tx(bp)) | |
387 | /* Just complain for now, reinitializing TX path can be good */ | |
388 | netdev_err(bp->dev, "BUG: halt tx timed out\n"); | |
bdcba151 | 389 | |
e86cd53a | 390 | /* No need for the lock here as nobody will interrupt us anymore */ |
bdcba151 | 391 | |
e86cd53a NF |
392 | /* |
393 | * Treat frames in TX queue including the ones that caused the error. | |
394 | * Free transmit buffers in upper layer. | |
395 | */ | |
396 | for (tail = bp->tx_tail; tail != bp->tx_head; tail++) { | |
397 | struct macb_dma_desc *desc; | |
398 | u32 ctrl; | |
55054a16 | 399 | |
e86cd53a NF |
400 | desc = macb_tx_desc(bp, tail); |
401 | ctrl = desc->ctrl; | |
402 | tx_skb = macb_tx_skb(bp, tail); | |
403 | skb = tx_skb->skb; | |
bdcba151 | 404 | |
e86cd53a NF |
405 | if (ctrl & MACB_BIT(TX_USED)) { |
406 | netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", | |
407 | macb_tx_ring_wrap(tail), skb->data); | |
408 | bp->stats.tx_packets++; | |
409 | bp->stats.tx_bytes += skb->len; | |
410 | } else { | |
411 | /* | |
412 | * "Buffers exhausted mid-frame" errors may only happen | |
413 | * if the driver is buggy, so complain loudly about those. | |
414 | * Statistics are updated by hardware. | |
415 | */ | |
416 | if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED)) | |
417 | netdev_err(bp->dev, | |
418 | "BUG: TX buffers exhausted mid-frame\n"); | |
39eddb4c | 419 | |
e86cd53a NF |
420 | desc->ctrl = ctrl | MACB_BIT(TX_USED); |
421 | } | |
422 | ||
423 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, | |
424 | DMA_TO_DEVICE); | |
425 | tx_skb->skb = NULL; | |
426 | dev_kfree_skb(skb); | |
89e5785f HS |
427 | } |
428 | ||
e86cd53a NF |
429 | /* Make descriptor updates visible to hardware */ |
430 | wmb(); | |
431 | ||
432 | /* Reinitialize the TX desc queue */ | |
433 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
434 | /* Make TX ring reflect state of hardware */ | |
435 | bp->tx_head = bp->tx_tail = 0; | |
436 | ||
437 | /* Now we are ready to start transmission again */ | |
438 | netif_wake_queue(bp->dev); | |
439 | ||
440 | /* Housework before enabling TX IRQ */ | |
441 | macb_writel(bp, TSR, macb_readl(bp, TSR)); | |
442 | macb_writel(bp, IER, MACB_TX_INT_FLAGS); | |
443 | } | |
444 | ||
445 | static void macb_tx_interrupt(struct macb *bp) | |
446 | { | |
447 | unsigned int tail; | |
448 | unsigned int head; | |
449 | u32 status; | |
450 | ||
451 | status = macb_readl(bp, TSR); | |
452 | macb_writel(bp, TSR, status); | |
453 | ||
454 | netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n", | |
455 | (unsigned long)status); | |
89e5785f HS |
456 | |
457 | head = bp->tx_head; | |
55054a16 HS |
458 | for (tail = bp->tx_tail; tail != head; tail++) { |
459 | struct macb_tx_skb *tx_skb; | |
460 | struct sk_buff *skb; | |
461 | struct macb_dma_desc *desc; | |
462 | u32 ctrl; | |
89e5785f | 463 | |
55054a16 | 464 | desc = macb_tx_desc(bp, tail); |
89e5785f | 465 | |
03dbe05f | 466 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 467 | rmb(); |
03dbe05f | 468 | |
55054a16 | 469 | ctrl = desc->ctrl; |
89e5785f | 470 | |
55054a16 | 471 | if (!(ctrl & MACB_BIT(TX_USED))) |
89e5785f HS |
472 | break; |
473 | ||
55054a16 HS |
474 | tx_skb = macb_tx_skb(bp, tail); |
475 | skb = tx_skb->skb; | |
476 | ||
a268adb1 | 477 | netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", |
55054a16 HS |
478 | macb_tx_ring_wrap(tail), skb->data); |
479 | dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len, | |
89e5785f HS |
480 | DMA_TO_DEVICE); |
481 | bp->stats.tx_packets++; | |
482 | bp->stats.tx_bytes += skb->len; | |
55054a16 | 483 | tx_skb->skb = NULL; |
89e5785f HS |
484 | dev_kfree_skb_irq(skb); |
485 | } | |
486 | ||
487 | bp->tx_tail = tail; | |
55054a16 HS |
488 | if (netif_queue_stopped(bp->dev) |
489 | && macb_tx_ring_avail(bp) > MACB_TX_WAKEUP_THRESH) | |
89e5785f HS |
490 | netif_wake_queue(bp->dev); |
491 | } | |
492 | ||
493 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
494 | unsigned int last_frag) | |
495 | { | |
496 | unsigned int len; | |
497 | unsigned int frag; | |
29bc2e1e | 498 | unsigned int offset; |
89e5785f | 499 | struct sk_buff *skb; |
55054a16 | 500 | struct macb_dma_desc *desc; |
89e5785f | 501 | |
55054a16 HS |
502 | desc = macb_rx_desc(bp, last_frag); |
503 | len = MACB_BFEXT(RX_FRMLEN, desc->ctrl); | |
89e5785f | 504 | |
a268adb1 | 505 | netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
55054a16 HS |
506 | macb_rx_ring_wrap(first_frag), |
507 | macb_rx_ring_wrap(last_frag), len); | |
89e5785f | 508 | |
29bc2e1e HS |
509 | /* |
510 | * The ethernet header starts NET_IP_ALIGN bytes into the | |
511 | * first buffer. Since the header is 14 bytes, this makes the | |
512 | * payload word-aligned. | |
513 | * | |
514 | * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy | |
515 | * the two padding bytes into the skb so that we avoid hitting | |
516 | * the slowpath in memcpy(), and pull them off afterwards. | |
517 | */ | |
518 | skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); | |
89e5785f HS |
519 | if (!skb) { |
520 | bp->stats.rx_dropped++; | |
55054a16 HS |
521 | for (frag = first_frag; ; frag++) { |
522 | desc = macb_rx_desc(bp, frag); | |
523 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
524 | if (frag == last_frag) |
525 | break; | |
526 | } | |
03dbe05f HS |
527 | |
528 | /* Make descriptor updates visible to hardware */ | |
89e5785f | 529 | wmb(); |
03dbe05f | 530 | |
89e5785f HS |
531 | return 1; |
532 | } | |
533 | ||
29bc2e1e HS |
534 | offset = 0; |
535 | len += NET_IP_ALIGN; | |
bc8acf2c | 536 | skb_checksum_none_assert(skb); |
89e5785f HS |
537 | skb_put(skb, len); |
538 | ||
55054a16 | 539 | for (frag = first_frag; ; frag++) { |
89e5785f HS |
540 | unsigned int frag_len = RX_BUFFER_SIZE; |
541 | ||
542 | if (offset + frag_len > len) { | |
543 | BUG_ON(frag != last_frag); | |
544 | frag_len = len - offset; | |
545 | } | |
27d7ff46 | 546 | skb_copy_to_linear_data_offset(skb, offset, |
55054a16 | 547 | macb_rx_buffer(bp, frag), frag_len); |
89e5785f | 548 | offset += RX_BUFFER_SIZE; |
55054a16 HS |
549 | desc = macb_rx_desc(bp, frag); |
550 | desc->addr &= ~MACB_BIT(RX_USED); | |
89e5785f HS |
551 | |
552 | if (frag == last_frag) | |
553 | break; | |
554 | } | |
555 | ||
03dbe05f HS |
556 | /* Make descriptor updates visible to hardware */ |
557 | wmb(); | |
558 | ||
29bc2e1e | 559 | __skb_pull(skb, NET_IP_ALIGN); |
89e5785f HS |
560 | skb->protocol = eth_type_trans(skb, bp->dev); |
561 | ||
562 | bp->stats.rx_packets++; | |
29bc2e1e | 563 | bp->stats.rx_bytes += skb->len; |
a268adb1 | 564 | netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", |
c220f8cd | 565 | skb->len, skb->csum); |
89e5785f HS |
566 | netif_receive_skb(skb); |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
572 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
573 | unsigned int end) | |
574 | { | |
575 | unsigned int frag; | |
576 | ||
55054a16 HS |
577 | for (frag = begin; frag != end; frag++) { |
578 | struct macb_dma_desc *desc = macb_rx_desc(bp, frag); | |
579 | desc->addr &= ~MACB_BIT(RX_USED); | |
580 | } | |
03dbe05f HS |
581 | |
582 | /* Make descriptor updates visible to hardware */ | |
89e5785f HS |
583 | wmb(); |
584 | ||
585 | /* | |
586 | * When this happens, the hardware stats registers for | |
587 | * whatever caused this is updated, so we don't have to record | |
588 | * anything. | |
589 | */ | |
590 | } | |
591 | ||
592 | static int macb_rx(struct macb *bp, int budget) | |
593 | { | |
594 | int received = 0; | |
55054a16 | 595 | unsigned int tail; |
89e5785f HS |
596 | int first_frag = -1; |
597 | ||
55054a16 HS |
598 | for (tail = bp->rx_tail; budget > 0; tail++) { |
599 | struct macb_dma_desc *desc = macb_rx_desc(bp, tail); | |
89e5785f HS |
600 | u32 addr, ctrl; |
601 | ||
03dbe05f | 602 | /* Make hw descriptor updates visible to CPU */ |
89e5785f | 603 | rmb(); |
03dbe05f | 604 | |
55054a16 HS |
605 | addr = desc->addr; |
606 | ctrl = desc->ctrl; | |
89e5785f HS |
607 | |
608 | if (!(addr & MACB_BIT(RX_USED))) | |
609 | break; | |
610 | ||
611 | if (ctrl & MACB_BIT(RX_SOF)) { | |
612 | if (first_frag != -1) | |
613 | discard_partial_frame(bp, first_frag, tail); | |
614 | first_frag = tail; | |
615 | } | |
616 | ||
617 | if (ctrl & MACB_BIT(RX_EOF)) { | |
618 | int dropped; | |
619 | BUG_ON(first_frag == -1); | |
620 | ||
621 | dropped = macb_rx_frame(bp, first_frag, tail); | |
622 | first_frag = -1; | |
623 | if (!dropped) { | |
624 | received++; | |
625 | budget--; | |
626 | } | |
627 | } | |
628 | } | |
629 | ||
630 | if (first_frag != -1) | |
631 | bp->rx_tail = first_frag; | |
632 | else | |
633 | bp->rx_tail = tail; | |
634 | ||
635 | return received; | |
636 | } | |
637 | ||
bea3348e | 638 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 639 | { |
bea3348e | 640 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 641 | int work_done; |
89e5785f HS |
642 | u32 status; |
643 | ||
644 | status = macb_readl(bp, RSR); | |
645 | macb_writel(bp, RSR, status); | |
646 | ||
bea3348e | 647 | work_done = 0; |
89e5785f | 648 | |
a268adb1 | 649 | netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
c220f8cd | 650 | (unsigned long)status, budget); |
89e5785f | 651 | |
bea3348e | 652 | work_done = macb_rx(bp, budget); |
b336369c | 653 | if (work_done < budget) { |
288379f0 | 654 | napi_complete(napi); |
89e5785f | 655 | |
b336369c JH |
656 | /* |
657 | * We've done what we can to clean the buffers. Make sure we | |
658 | * get notified when new packets arrive. | |
659 | */ | |
660 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
661 | } | |
89e5785f HS |
662 | |
663 | /* TODO: Handle errors */ | |
664 | ||
bea3348e | 665 | return work_done; |
89e5785f HS |
666 | } |
667 | ||
668 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
669 | { | |
670 | struct net_device *dev = dev_id; | |
671 | struct macb *bp = netdev_priv(dev); | |
672 | u32 status; | |
673 | ||
674 | status = macb_readl(bp, ISR); | |
675 | ||
676 | if (unlikely(!status)) | |
677 | return IRQ_NONE; | |
678 | ||
679 | spin_lock(&bp->lock); | |
680 | ||
681 | while (status) { | |
89e5785f HS |
682 | /* close possible race with dev_close */ |
683 | if (unlikely(!netif_running(dev))) { | |
95ebcea6 | 684 | macb_writel(bp, IDR, -1); |
89e5785f HS |
685 | break; |
686 | } | |
687 | ||
a268adb1 HS |
688 | netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status); |
689 | ||
89e5785f | 690 | if (status & MACB_RX_INT_FLAGS) { |
b336369c JH |
691 | /* |
692 | * There's no point taking any more interrupts | |
693 | * until we have processed the buffers. The | |
694 | * scheduling call may fail if the poll routine | |
695 | * is already scheduled, so disable interrupts | |
696 | * now. | |
697 | */ | |
698 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
699 | ||
288379f0 | 700 | if (napi_schedule_prep(&bp->napi)) { |
a268adb1 | 701 | netdev_vdbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 702 | __napi_schedule(&bp->napi); |
89e5785f HS |
703 | } |
704 | } | |
705 | ||
e86cd53a NF |
706 | if (unlikely(status & (MACB_TX_ERR_FLAGS))) { |
707 | macb_writel(bp, IDR, MACB_TX_INT_FLAGS); | |
708 | schedule_work(&bp->tx_error_task); | |
709 | break; | |
710 | } | |
711 | ||
712 | if (status & MACB_BIT(TCOMP)) | |
713 | macb_tx_interrupt(bp); | |
89e5785f HS |
714 | |
715 | /* | |
716 | * Link change detection isn't possible with RMII, so we'll | |
717 | * add that if/when we get our hands on a full-blown MII PHY. | |
718 | */ | |
719 | ||
b19f7f71 AS |
720 | if (status & MACB_BIT(ISR_ROVR)) { |
721 | /* We missed at least one packet */ | |
f75ba50b JI |
722 | if (macb_is_gem(bp)) |
723 | bp->hw_stats.gem.rx_overruns++; | |
724 | else | |
725 | bp->hw_stats.macb.rx_overruns++; | |
b19f7f71 AS |
726 | } |
727 | ||
89e5785f HS |
728 | if (status & MACB_BIT(HRESP)) { |
729 | /* | |
c220f8cd JI |
730 | * TODO: Reset the hardware, and maybe move the |
731 | * netdev_err to a lower-priority context as well | |
732 | * (work queue?) | |
89e5785f | 733 | */ |
c220f8cd | 734 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
89e5785f HS |
735 | } |
736 | ||
737 | status = macb_readl(bp, ISR); | |
738 | } | |
739 | ||
740 | spin_unlock(&bp->lock); | |
741 | ||
742 | return IRQ_HANDLED; | |
743 | } | |
744 | ||
6e8cf5c0 TP |
745 | #ifdef CONFIG_NET_POLL_CONTROLLER |
746 | /* | |
747 | * Polling receive - used by netconsole and other diagnostic tools | |
748 | * to allow network i/o with interrupts disabled. | |
749 | */ | |
750 | static void macb_poll_controller(struct net_device *dev) | |
751 | { | |
752 | unsigned long flags; | |
753 | ||
754 | local_irq_save(flags); | |
755 | macb_interrupt(dev->irq, dev); | |
756 | local_irq_restore(flags); | |
757 | } | |
758 | #endif | |
759 | ||
89e5785f HS |
760 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
761 | { | |
762 | struct macb *bp = netdev_priv(dev); | |
763 | dma_addr_t mapping; | |
764 | unsigned int len, entry; | |
55054a16 HS |
765 | struct macb_dma_desc *desc; |
766 | struct macb_tx_skb *tx_skb; | |
89e5785f | 767 | u32 ctrl; |
4871953c | 768 | unsigned long flags; |
89e5785f | 769 | |
a268adb1 HS |
770 | #if defined(DEBUG) && defined(VERBOSE_DEBUG) |
771 | netdev_vdbg(bp->dev, | |
c220f8cd JI |
772 | "start_xmit: len %u head %p data %p tail %p end %p\n", |
773 | skb->len, skb->head, skb->data, | |
774 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
775 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
776 | skb->data, 16, true); | |
89e5785f HS |
777 | #endif |
778 | ||
779 | len = skb->len; | |
4871953c | 780 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
781 | |
782 | /* This is a hard error, log it. */ | |
55054a16 | 783 | if (macb_tx_ring_avail(bp) < 1) { |
89e5785f | 784 | netif_stop_queue(dev); |
4871953c | 785 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd JI |
786 | netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); |
787 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", | |
788 | bp->tx_head, bp->tx_tail); | |
5b548140 | 789 | return NETDEV_TX_BUSY; |
89e5785f HS |
790 | } |
791 | ||
55054a16 HS |
792 | entry = macb_tx_ring_wrap(bp->tx_head); |
793 | bp->tx_head++; | |
a268adb1 | 794 | netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry); |
89e5785f HS |
795 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
796 | len, DMA_TO_DEVICE); | |
55054a16 HS |
797 | |
798 | tx_skb = &bp->tx_skb[entry]; | |
799 | tx_skb->skb = skb; | |
800 | tx_skb->mapping = mapping; | |
a268adb1 | 801 | netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", |
c220f8cd | 802 | skb->data, (unsigned long)mapping); |
89e5785f HS |
803 | |
804 | ctrl = MACB_BF(TX_FRMLEN, len); | |
805 | ctrl |= MACB_BIT(TX_LAST); | |
806 | if (entry == (TX_RING_SIZE - 1)) | |
807 | ctrl |= MACB_BIT(TX_WRAP); | |
808 | ||
55054a16 HS |
809 | desc = &bp->tx_ring[entry]; |
810 | desc->addr = mapping; | |
811 | desc->ctrl = ctrl; | |
03dbe05f HS |
812 | |
813 | /* Make newly initialized descriptor visible to hardware */ | |
89e5785f HS |
814 | wmb(); |
815 | ||
e072092f RC |
816 | skb_tx_timestamp(skb); |
817 | ||
89e5785f HS |
818 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
819 | ||
55054a16 | 820 | if (macb_tx_ring_avail(bp) < 1) |
89e5785f HS |
821 | netif_stop_queue(dev); |
822 | ||
4871953c | 823 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 824 | |
6ed10654 | 825 | return NETDEV_TX_OK; |
89e5785f HS |
826 | } |
827 | ||
828 | static void macb_free_consistent(struct macb *bp) | |
829 | { | |
830 | if (bp->tx_skb) { | |
831 | kfree(bp->tx_skb); | |
832 | bp->tx_skb = NULL; | |
833 | } | |
834 | if (bp->rx_ring) { | |
835 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
836 | bp->rx_ring, bp->rx_ring_dma); | |
837 | bp->rx_ring = NULL; | |
838 | } | |
839 | if (bp->tx_ring) { | |
840 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
841 | bp->tx_ring, bp->tx_ring_dma); | |
842 | bp->tx_ring = NULL; | |
843 | } | |
844 | if (bp->rx_buffers) { | |
845 | dma_free_coherent(&bp->pdev->dev, | |
846 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
847 | bp->rx_buffers, bp->rx_buffers_dma); | |
848 | bp->rx_buffers = NULL; | |
849 | } | |
850 | } | |
851 | ||
852 | static int macb_alloc_consistent(struct macb *bp) | |
853 | { | |
854 | int size; | |
855 | ||
55054a16 | 856 | size = TX_RING_SIZE * sizeof(struct macb_tx_skb); |
89e5785f HS |
857 | bp->tx_skb = kmalloc(size, GFP_KERNEL); |
858 | if (!bp->tx_skb) | |
859 | goto out_err; | |
860 | ||
861 | size = RX_RING_BYTES; | |
862 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
863 | &bp->rx_ring_dma, GFP_KERNEL); | |
864 | if (!bp->rx_ring) | |
865 | goto out_err; | |
c220f8cd JI |
866 | netdev_dbg(bp->dev, |
867 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
868 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f HS |
869 | |
870 | size = TX_RING_BYTES; | |
871 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
872 | &bp->tx_ring_dma, GFP_KERNEL); | |
873 | if (!bp->tx_ring) | |
874 | goto out_err; | |
c220f8cd JI |
875 | netdev_dbg(bp->dev, |
876 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
877 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
89e5785f HS |
878 | |
879 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
880 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
881 | &bp->rx_buffers_dma, GFP_KERNEL); | |
882 | if (!bp->rx_buffers) | |
883 | goto out_err; | |
c220f8cd JI |
884 | netdev_dbg(bp->dev, |
885 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
886 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
89e5785f HS |
887 | |
888 | return 0; | |
889 | ||
890 | out_err: | |
891 | macb_free_consistent(bp); | |
892 | return -ENOMEM; | |
893 | } | |
894 | ||
895 | static void macb_init_rings(struct macb *bp) | |
896 | { | |
897 | int i; | |
898 | dma_addr_t addr; | |
899 | ||
900 | addr = bp->rx_buffers_dma; | |
901 | for (i = 0; i < RX_RING_SIZE; i++) { | |
902 | bp->rx_ring[i].addr = addr; | |
903 | bp->rx_ring[i].ctrl = 0; | |
904 | addr += RX_BUFFER_SIZE; | |
905 | } | |
906 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
907 | ||
908 | for (i = 0; i < TX_RING_SIZE; i++) { | |
909 | bp->tx_ring[i].addr = 0; | |
910 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
911 | } | |
912 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
913 | ||
914 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
915 | } | |
916 | ||
917 | static void macb_reset_hw(struct macb *bp) | |
918 | { | |
89e5785f HS |
919 | /* |
920 | * Disable RX and TX (XXX: Should we halt the transmission | |
921 | * more gracefully?) | |
922 | */ | |
923 | macb_writel(bp, NCR, 0); | |
924 | ||
925 | /* Clear the stats registers (XXX: Update stats first?) */ | |
926 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
927 | ||
928 | /* Clear all status flags */ | |
95ebcea6 JE |
929 | macb_writel(bp, TSR, -1); |
930 | macb_writel(bp, RSR, -1); | |
89e5785f HS |
931 | |
932 | /* Disable all interrupts */ | |
95ebcea6 | 933 | macb_writel(bp, IDR, -1); |
89e5785f HS |
934 | macb_readl(bp, ISR); |
935 | } | |
936 | ||
70c9f3d4 JI |
937 | static u32 gem_mdc_clk_div(struct macb *bp) |
938 | { | |
939 | u32 config; | |
940 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
941 | ||
942 | if (pclk_hz <= 20000000) | |
943 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
944 | else if (pclk_hz <= 40000000) | |
945 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
946 | else if (pclk_hz <= 80000000) | |
947 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
948 | else if (pclk_hz <= 120000000) | |
949 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
950 | else if (pclk_hz <= 160000000) | |
951 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
952 | else | |
953 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
954 | ||
955 | return config; | |
956 | } | |
957 | ||
958 | static u32 macb_mdc_clk_div(struct macb *bp) | |
959 | { | |
960 | u32 config; | |
961 | unsigned long pclk_hz; | |
962 | ||
963 | if (macb_is_gem(bp)) | |
964 | return gem_mdc_clk_div(bp); | |
965 | ||
966 | pclk_hz = clk_get_rate(bp->pclk); | |
967 | if (pclk_hz <= 20000000) | |
968 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
969 | else if (pclk_hz <= 40000000) | |
970 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
971 | else if (pclk_hz <= 80000000) | |
972 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
973 | else | |
974 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
975 | ||
976 | return config; | |
977 | } | |
978 | ||
757a03c6 JI |
979 | /* |
980 | * Get the DMA bus width field of the network configuration register that we | |
981 | * should program. We find the width from decoding the design configuration | |
982 | * register to find the maximum supported data bus width. | |
983 | */ | |
984 | static u32 macb_dbw(struct macb *bp) | |
985 | { | |
986 | if (!macb_is_gem(bp)) | |
987 | return 0; | |
988 | ||
989 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
990 | case 4: | |
991 | return GEM_BF(DBW, GEM_DBW128); | |
992 | case 2: | |
993 | return GEM_BF(DBW, GEM_DBW64); | |
994 | case 1: | |
995 | default: | |
996 | return GEM_BF(DBW, GEM_DBW32); | |
997 | } | |
998 | } | |
999 | ||
0116da4f JI |
1000 | /* |
1001 | * Configure the receive DMA engine to use the correct receive buffer size. | |
1002 | * This is a configurable parameter for GEM. | |
1003 | */ | |
1004 | static void macb_configure_dma(struct macb *bp) | |
1005 | { | |
1006 | u32 dmacfg; | |
1007 | ||
1008 | if (macb_is_gem(bp)) { | |
1009 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
1010 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); | |
1011 | gem_writel(bp, DMACFG, dmacfg); | |
1012 | } | |
1013 | } | |
1014 | ||
89e5785f HS |
1015 | static void macb_init_hw(struct macb *bp) |
1016 | { | |
1017 | u32 config; | |
1018 | ||
1019 | macb_reset_hw(bp); | |
1020 | __macb_set_hwaddr(bp); | |
1021 | ||
70c9f3d4 | 1022 | config = macb_mdc_clk_div(bp); |
29bc2e1e | 1023 | config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */ |
89e5785f HS |
1024 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
1025 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 1026 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
1027 | if (bp->dev->flags & IFF_PROMISC) |
1028 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
1029 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
1030 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 1031 | config |= macb_dbw(bp); |
89e5785f HS |
1032 | macb_writel(bp, NCFGR, config); |
1033 | ||
0116da4f JI |
1034 | macb_configure_dma(bp); |
1035 | ||
89e5785f HS |
1036 | /* Initialize TX and RX buffers */ |
1037 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
1038 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
1039 | ||
1040 | /* Enable TX and RX */ | |
6c36a707 | 1041 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
1042 | |
1043 | /* Enable interrupts */ | |
e86cd53a NF |
1044 | macb_writel(bp, IER, (MACB_RX_INT_FLAGS |
1045 | | MACB_TX_INT_FLAGS | |
89e5785f | 1046 | | MACB_BIT(HRESP))); |
89e5785f | 1047 | |
89e5785f HS |
1048 | } |
1049 | ||
446ebd01 PV |
1050 | /* |
1051 | * The hash address register is 64 bits long and takes up two | |
1052 | * locations in the memory map. The least significant bits are stored | |
1053 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
1054 | * | |
1055 | * The unicast hash enable and the multicast hash enable bits in the | |
1056 | * network configuration register enable the reception of hash matched | |
1057 | * frames. The destination address is reduced to a 6 bit index into | |
1058 | * the 64 bit hash register using the following hash function. The | |
1059 | * hash function is an exclusive or of every sixth bit of the | |
1060 | * destination address. | |
1061 | * | |
1062 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
1063 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
1064 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
1065 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
1066 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
1067 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
1068 | * | |
1069 | * da[0] represents the least significant bit of the first byte | |
1070 | * received, that is, the multicast/unicast indicator, and da[47] | |
1071 | * represents the most significant bit of the last byte received. If | |
1072 | * the hash index, hi[n], points to a bit that is set in the hash | |
1073 | * register then the frame will be matched according to whether the | |
1074 | * frame is multicast or unicast. A multicast match will be signalled | |
1075 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
1076 | * index points to a bit set in the hash register. A unicast match | |
1077 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
1078 | * and the hash index points to a bit set in the hash register. To | |
1079 | * receive all multicast frames, the hash register should be set with | |
1080 | * all ones and the multicast hash enable bit should be set in the | |
1081 | * network configuration register. | |
1082 | */ | |
1083 | ||
1084 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
1085 | { | |
1086 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
1087 | return 1; | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * Return the hash index value for the specified address. | |
1093 | */ | |
1094 | static int hash_get_index(__u8 *addr) | |
1095 | { | |
1096 | int i, j, bitval; | |
1097 | int hash_index = 0; | |
1098 | ||
1099 | for (j = 0; j < 6; j++) { | |
1100 | for (i = 0, bitval = 0; i < 8; i++) | |
1101 | bitval ^= hash_bit_value(i*6 + j, addr); | |
1102 | ||
1103 | hash_index |= (bitval << j); | |
1104 | } | |
1105 | ||
1106 | return hash_index; | |
1107 | } | |
1108 | ||
1109 | /* | |
1110 | * Add multicast addresses to the internal multicast-hash table. | |
1111 | */ | |
1112 | static void macb_sethashtable(struct net_device *dev) | |
1113 | { | |
22bedad3 | 1114 | struct netdev_hw_addr *ha; |
446ebd01 | 1115 | unsigned long mc_filter[2]; |
f9dcbcc9 | 1116 | unsigned int bitnr; |
446ebd01 PV |
1117 | struct macb *bp = netdev_priv(dev); |
1118 | ||
1119 | mc_filter[0] = mc_filter[1] = 0; | |
1120 | ||
22bedad3 JP |
1121 | netdev_for_each_mc_addr(ha, dev) { |
1122 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
1123 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
1124 | } | |
1125 | ||
f75ba50b JI |
1126 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
1127 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
1128 | } |
1129 | ||
1130 | /* | |
1131 | * Enable/Disable promiscuous and multicast modes. | |
1132 | */ | |
e0da1f14 | 1133 | void macb_set_rx_mode(struct net_device *dev) |
446ebd01 PV |
1134 | { |
1135 | unsigned long cfg; | |
1136 | struct macb *bp = netdev_priv(dev); | |
1137 | ||
1138 | cfg = macb_readl(bp, NCFGR); | |
1139 | ||
1140 | if (dev->flags & IFF_PROMISC) | |
1141 | /* Enable promiscuous mode */ | |
1142 | cfg |= MACB_BIT(CAF); | |
1143 | else if (dev->flags & (~IFF_PROMISC)) | |
1144 | /* Disable promiscuous mode */ | |
1145 | cfg &= ~MACB_BIT(CAF); | |
1146 | ||
1147 | if (dev->flags & IFF_ALLMULTI) { | |
1148 | /* Enable all multicast mode */ | |
f75ba50b JI |
1149 | macb_or_gem_writel(bp, HRB, -1); |
1150 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1151 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1152 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1153 | /* Enable specific multicasts */ |
1154 | macb_sethashtable(dev); | |
1155 | cfg |= MACB_BIT(NCFGR_MTI); | |
1156 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1157 | /* Disable all multicast mode */ | |
f75ba50b JI |
1158 | macb_or_gem_writel(bp, HRB, 0); |
1159 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1160 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1161 | } | |
1162 | ||
1163 | macb_writel(bp, NCFGR, cfg); | |
1164 | } | |
e0da1f14 | 1165 | EXPORT_SYMBOL_GPL(macb_set_rx_mode); |
446ebd01 | 1166 | |
89e5785f HS |
1167 | static int macb_open(struct net_device *dev) |
1168 | { | |
1169 | struct macb *bp = netdev_priv(dev); | |
1170 | int err; | |
1171 | ||
c220f8cd | 1172 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1173 | |
03fc4721 NF |
1174 | /* carrier starts down */ |
1175 | netif_carrier_off(dev); | |
1176 | ||
6c36a707 R |
1177 | /* if the phy is not yet register, retry later*/ |
1178 | if (!bp->phy_dev) | |
1179 | return -EAGAIN; | |
1180 | ||
89e5785f HS |
1181 | if (!is_valid_ether_addr(dev->dev_addr)) |
1182 | return -EADDRNOTAVAIL; | |
1183 | ||
1184 | err = macb_alloc_consistent(bp); | |
1185 | if (err) { | |
c220f8cd JI |
1186 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1187 | err); | |
89e5785f HS |
1188 | return err; |
1189 | } | |
1190 | ||
bea3348e SH |
1191 | napi_enable(&bp->napi); |
1192 | ||
89e5785f HS |
1193 | macb_init_rings(bp); |
1194 | macb_init_hw(bp); | |
89e5785f | 1195 | |
6c36a707 R |
1196 | /* schedule a link state check */ |
1197 | phy_start(bp->phy_dev); | |
89e5785f | 1198 | |
6c36a707 | 1199 | netif_start_queue(dev); |
89e5785f HS |
1200 | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static int macb_close(struct net_device *dev) | |
1205 | { | |
1206 | struct macb *bp = netdev_priv(dev); | |
1207 | unsigned long flags; | |
1208 | ||
89e5785f | 1209 | netif_stop_queue(dev); |
bea3348e | 1210 | napi_disable(&bp->napi); |
89e5785f | 1211 | |
6c36a707 R |
1212 | if (bp->phy_dev) |
1213 | phy_stop(bp->phy_dev); | |
1214 | ||
89e5785f HS |
1215 | spin_lock_irqsave(&bp->lock, flags); |
1216 | macb_reset_hw(bp); | |
1217 | netif_carrier_off(dev); | |
1218 | spin_unlock_irqrestore(&bp->lock, flags); | |
1219 | ||
1220 | macb_free_consistent(bp); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
a494ed8e JI |
1225 | static void gem_update_stats(struct macb *bp) |
1226 | { | |
1227 | u32 __iomem *reg = bp->regs + GEM_OTX; | |
1228 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; | |
1229 | u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; | |
1230 | ||
1231 | for (; p < end; p++, reg++) | |
1232 | *p += __raw_readl(reg); | |
1233 | } | |
1234 | ||
1235 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
1236 | { | |
1237 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
1238 | struct net_device_stats *nstat = &bp->stats; | |
1239 | ||
1240 | gem_update_stats(bp); | |
1241 | ||
1242 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
1243 | hwstat->rx_alignment_errors + | |
1244 | hwstat->rx_resource_errors + | |
1245 | hwstat->rx_overruns + | |
1246 | hwstat->rx_oversize_frames + | |
1247 | hwstat->rx_jabbers + | |
1248 | hwstat->rx_undersized_frames + | |
1249 | hwstat->rx_length_field_frame_errors); | |
1250 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
1251 | hwstat->tx_excessive_collisions + | |
1252 | hwstat->tx_underrun + | |
1253 | hwstat->tx_carrier_sense_errors); | |
1254 | nstat->multicast = hwstat->rx_multicast_frames; | |
1255 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
1256 | hwstat->tx_multiple_collision_frames + | |
1257 | hwstat->tx_excessive_collisions); | |
1258 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
1259 | hwstat->rx_jabbers + | |
1260 | hwstat->rx_undersized_frames + | |
1261 | hwstat->rx_length_field_frame_errors); | |
1262 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1263 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
1264 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
1265 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1266 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
1267 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
1268 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
1269 | ||
1270 | return nstat; | |
1271 | } | |
1272 | ||
89e5785f HS |
1273 | static struct net_device_stats *macb_get_stats(struct net_device *dev) |
1274 | { | |
1275 | struct macb *bp = netdev_priv(dev); | |
1276 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
1277 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
1278 | ||
1279 | if (macb_is_gem(bp)) | |
1280 | return gem_get_stats(bp); | |
89e5785f | 1281 | |
6c36a707 R |
1282 | /* read stats from hardware */ |
1283 | macb_update_stats(bp); | |
1284 | ||
89e5785f HS |
1285 | /* Convert HW stats into netdevice stats */ |
1286 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1287 | hwstat->rx_align_errors + | |
1288 | hwstat->rx_resource_errors + | |
1289 | hwstat->rx_overruns + | |
1290 | hwstat->rx_oversize_pkts + | |
1291 | hwstat->rx_jabbers + | |
1292 | hwstat->rx_undersize_pkts + | |
1293 | hwstat->sqe_test_errors + | |
1294 | hwstat->rx_length_mismatch); | |
1295 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1296 | hwstat->tx_excessive_cols + | |
1297 | hwstat->tx_underruns + | |
1298 | hwstat->tx_carrier_errors); | |
1299 | nstat->collisions = (hwstat->tx_single_cols + | |
1300 | hwstat->tx_multiple_cols + | |
1301 | hwstat->tx_excessive_cols); | |
1302 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1303 | hwstat->rx_jabbers + | |
1304 | hwstat->rx_undersize_pkts + | |
1305 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1306 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1307 | hwstat->rx_overruns; | |
89e5785f HS |
1308 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1309 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1310 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1311 | /* XXX: What does "missed" mean? */ | |
1312 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1313 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1314 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1315 | /* Don't know about heartbeat or window errors... */ | |
1316 | ||
1317 | return nstat; | |
1318 | } | |
1319 | ||
1320 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1321 | { | |
1322 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1323 | struct phy_device *phydev = bp->phy_dev; |
1324 | ||
1325 | if (!phydev) | |
1326 | return -ENODEV; | |
89e5785f | 1327 | |
6c36a707 | 1328 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1329 | } |
1330 | ||
1331 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1332 | { | |
1333 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1334 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1335 | |
6c36a707 R |
1336 | if (!phydev) |
1337 | return -ENODEV; | |
1338 | ||
1339 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1340 | } |
1341 | ||
d1d1b53d NF |
1342 | static int macb_get_regs_len(struct net_device *netdev) |
1343 | { | |
1344 | return MACB_GREGS_NBR * sizeof(u32); | |
1345 | } | |
1346 | ||
1347 | static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1348 | void *p) | |
1349 | { | |
1350 | struct macb *bp = netdev_priv(dev); | |
1351 | unsigned int tail, head; | |
1352 | u32 *regs_buff = p; | |
1353 | ||
1354 | regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) | |
1355 | | MACB_GREGS_VERSION; | |
1356 | ||
1357 | tail = macb_tx_ring_wrap(bp->tx_tail); | |
1358 | head = macb_tx_ring_wrap(bp->tx_head); | |
1359 | ||
1360 | regs_buff[0] = macb_readl(bp, NCR); | |
1361 | regs_buff[1] = macb_or_gem_readl(bp, NCFGR); | |
1362 | regs_buff[2] = macb_readl(bp, NSR); | |
1363 | regs_buff[3] = macb_readl(bp, TSR); | |
1364 | regs_buff[4] = macb_readl(bp, RBQP); | |
1365 | regs_buff[5] = macb_readl(bp, TBQP); | |
1366 | regs_buff[6] = macb_readl(bp, RSR); | |
1367 | regs_buff[7] = macb_readl(bp, IMR); | |
1368 | ||
1369 | regs_buff[8] = tail; | |
1370 | regs_buff[9] = head; | |
1371 | regs_buff[10] = macb_tx_dma(bp, tail); | |
1372 | regs_buff[11] = macb_tx_dma(bp, head); | |
1373 | ||
1374 | if (macb_is_gem(bp)) { | |
1375 | regs_buff[12] = gem_readl(bp, USRIO); | |
1376 | regs_buff[13] = gem_readl(bp, DMACFG); | |
1377 | } | |
1378 | } | |
1379 | ||
0005f541 | 1380 | const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
1381 | .get_settings = macb_get_settings, |
1382 | .set_settings = macb_set_settings, | |
d1d1b53d NF |
1383 | .get_regs_len = macb_get_regs_len, |
1384 | .get_regs = macb_get_regs, | |
89e5785f | 1385 | .get_link = ethtool_op_get_link, |
17f393e8 | 1386 | .get_ts_info = ethtool_op_get_ts_info, |
89e5785f | 1387 | }; |
0005f541 | 1388 | EXPORT_SYMBOL_GPL(macb_ethtool_ops); |
89e5785f | 1389 | |
0005f541 | 1390 | int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f HS |
1391 | { |
1392 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1393 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1394 | |
1395 | if (!netif_running(dev)) | |
1396 | return -EINVAL; | |
1397 | ||
6c36a707 R |
1398 | if (!phydev) |
1399 | return -ENODEV; | |
89e5785f | 1400 | |
28b04113 | 1401 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f | 1402 | } |
0005f541 | 1403 | EXPORT_SYMBOL_GPL(macb_ioctl); |
89e5785f | 1404 | |
5f1fa992 AB |
1405 | static const struct net_device_ops macb_netdev_ops = { |
1406 | .ndo_open = macb_open, | |
1407 | .ndo_stop = macb_close, | |
1408 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 1409 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
1410 | .ndo_get_stats = macb_get_stats, |
1411 | .ndo_do_ioctl = macb_ioctl, | |
1412 | .ndo_validate_addr = eth_validate_addr, | |
1413 | .ndo_change_mtu = eth_change_mtu, | |
1414 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
1415 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1416 | .ndo_poll_controller = macb_poll_controller, | |
1417 | #endif | |
5f1fa992 AB |
1418 | }; |
1419 | ||
fb97a846 JCPV |
1420 | #if defined(CONFIG_OF) |
1421 | static const struct of_device_id macb_dt_ids[] = { | |
1422 | { .compatible = "cdns,at32ap7000-macb" }, | |
1423 | { .compatible = "cdns,at91sam9260-macb" }, | |
1424 | { .compatible = "cdns,macb" }, | |
1425 | { .compatible = "cdns,pc302-gem" }, | |
1426 | { .compatible = "cdns,gem" }, | |
1427 | { /* sentinel */ } | |
1428 | }; | |
1429 | ||
1430 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
1431 | ||
1432 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1433 | { | |
1434 | struct device_node *np = pdev->dev.of_node; | |
1435 | ||
1436 | if (np) | |
1437 | return of_get_phy_mode(np); | |
1438 | ||
1439 | return -ENODEV; | |
1440 | } | |
1441 | ||
1442 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1443 | { | |
1444 | struct device_node *np = bp->pdev->dev.of_node; | |
1445 | if (np) { | |
1446 | const char *mac = of_get_mac_address(np); | |
1447 | if (mac) { | |
1448 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | |
1449 | return 0; | |
1450 | } | |
1451 | } | |
1452 | ||
1453 | return -ENODEV; | |
1454 | } | |
1455 | #else | |
1456 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1457 | { | |
1458 | return -ENODEV; | |
1459 | } | |
1460 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1461 | { | |
1462 | return -ENODEV; | |
1463 | } | |
1464 | #endif | |
1465 | ||
06c3fd6a | 1466 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f | 1467 | { |
84e0cdb0 | 1468 | struct macb_platform_data *pdata; |
89e5785f HS |
1469 | struct resource *regs; |
1470 | struct net_device *dev; | |
1471 | struct macb *bp; | |
6c36a707 | 1472 | struct phy_device *phydev; |
89e5785f HS |
1473 | u32 config; |
1474 | int err = -ENXIO; | |
1475 | ||
1476 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1477 | if (!regs) { | |
1478 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1479 | goto err_out; | |
1480 | } | |
1481 | ||
1482 | err = -ENOMEM; | |
1483 | dev = alloc_etherdev(sizeof(*bp)); | |
41de8d4c | 1484 | if (!dev) |
89e5785f | 1485 | goto err_out; |
89e5785f | 1486 | |
89e5785f HS |
1487 | SET_NETDEV_DEV(dev, &pdev->dev); |
1488 | ||
1489 | /* TODO: Actually, we have some interesting features... */ | |
1490 | dev->features |= 0; | |
1491 | ||
1492 | bp = netdev_priv(dev); | |
1493 | bp->pdev = pdev; | |
1494 | bp->dev = dev; | |
1495 | ||
1496 | spin_lock_init(&bp->lock); | |
e86cd53a | 1497 | INIT_WORK(&bp->tx_error_task, macb_tx_error_task); |
89e5785f | 1498 | |
461845db | 1499 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
0cc8674f AV |
1500 | if (IS_ERR(bp->pclk)) { |
1501 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1502 | goto err_out_free_dev; | |
1503 | } | |
1504 | clk_enable(bp->pclk); | |
461845db | 1505 | |
89e5785f HS |
1506 | bp->hclk = clk_get(&pdev->dev, "hclk"); |
1507 | if (IS_ERR(bp->hclk)) { | |
1508 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1509 | goto err_out_put_pclk; | |
1510 | } | |
89e5785f HS |
1511 | clk_enable(bp->hclk); |
1512 | ||
28f65c11 | 1513 | bp->regs = ioremap(regs->start, resource_size(regs)); |
89e5785f HS |
1514 | if (!bp->regs) { |
1515 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1516 | err = -ENOMEM; | |
1517 | goto err_out_disable_clocks; | |
1518 | } | |
1519 | ||
1520 | dev->irq = platform_get_irq(pdev, 0); | |
ab392d2d | 1521 | err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); |
89e5785f | 1522 | if (err) { |
c220f8cd JI |
1523 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", |
1524 | dev->irq, err); | |
89e5785f HS |
1525 | goto err_out_iounmap; |
1526 | } | |
1527 | ||
5f1fa992 | 1528 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 1529 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1530 | dev->ethtool_ops = &macb_ethtool_ops; |
1531 | ||
1532 | dev->base_addr = regs->start; | |
1533 | ||
89e5785f | 1534 | /* Set MII management clock divider */ |
70c9f3d4 | 1535 | config = macb_mdc_clk_div(bp); |
757a03c6 | 1536 | config |= macb_dbw(bp); |
89e5785f HS |
1537 | macb_writel(bp, NCFGR, config); |
1538 | ||
fb97a846 JCPV |
1539 | err = macb_get_hwaddr_dt(bp); |
1540 | if (err < 0) | |
1541 | macb_get_hwaddr(bp); | |
1542 | ||
1543 | err = macb_get_phy_mode_dt(pdev); | |
1544 | if (err < 0) { | |
1545 | pdata = pdev->dev.platform_data; | |
1546 | if (pdata && pdata->is_rmii) | |
1547 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
1548 | else | |
1549 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
1550 | } else { | |
1551 | bp->phy_interface = err; | |
1552 | } | |
6c36a707 | 1553 | |
140b7552 PV |
1554 | if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII) |
1555 | macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII)); | |
1556 | else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) | |
0cc8674f | 1557 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b JI |
1558 | macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | |
1559 | MACB_BIT(CLKEN))); | |
0cc8674f | 1560 | #else |
f75ba50b | 1561 | macb_or_gem_writel(bp, USRIO, 0); |
0cc8674f | 1562 | #endif |
89e5785f | 1563 | else |
0cc8674f | 1564 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b | 1565 | macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); |
0cc8674f | 1566 | #else |
f75ba50b | 1567 | macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1568 | #endif |
89e5785f | 1569 | |
89e5785f HS |
1570 | err = register_netdev(dev); |
1571 | if (err) { | |
1572 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1573 | goto err_out_free_irq; | |
1574 | } | |
1575 | ||
6c36a707 R |
1576 | if (macb_mii_init(bp) != 0) { |
1577 | goto err_out_unregister_netdev; | |
1578 | } | |
89e5785f | 1579 | |
6c36a707 | 1580 | platform_set_drvdata(pdev, dev); |
89e5785f | 1581 | |
03fc4721 NF |
1582 | netif_carrier_off(dev); |
1583 | ||
f75ba50b JI |
1584 | netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", |
1585 | macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, | |
1586 | dev->irq, dev->dev_addr); | |
89e5785f | 1587 | |
6c36a707 | 1588 | phydev = bp->phy_dev; |
c220f8cd JI |
1589 | netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1590 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 1591 | |
89e5785f HS |
1592 | return 0; |
1593 | ||
6c36a707 R |
1594 | err_out_unregister_netdev: |
1595 | unregister_netdev(dev); | |
89e5785f HS |
1596 | err_out_free_irq: |
1597 | free_irq(dev->irq, dev); | |
1598 | err_out_iounmap: | |
1599 | iounmap(bp->regs); | |
1600 | err_out_disable_clocks: | |
1601 | clk_disable(bp->hclk); | |
89e5785f | 1602 | clk_put(bp->hclk); |
0cc8674f | 1603 | clk_disable(bp->pclk); |
89e5785f HS |
1604 | err_out_put_pclk: |
1605 | clk_put(bp->pclk); | |
1606 | err_out_free_dev: | |
1607 | free_netdev(dev); | |
1608 | err_out: | |
1609 | platform_set_drvdata(pdev, NULL); | |
1610 | return err; | |
1611 | } | |
1612 | ||
06c3fd6a | 1613 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1614 | { |
1615 | struct net_device *dev; | |
1616 | struct macb *bp; | |
1617 | ||
1618 | dev = platform_get_drvdata(pdev); | |
1619 | ||
1620 | if (dev) { | |
1621 | bp = netdev_priv(dev); | |
84b7901f AN |
1622 | if (bp->phy_dev) |
1623 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1624 | mdiobus_unregister(bp->mii_bus); |
1625 | kfree(bp->mii_bus->irq); | |
1626 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1627 | unregister_netdev(dev); |
1628 | free_irq(dev->irq, dev); | |
1629 | iounmap(bp->regs); | |
1630 | clk_disable(bp->hclk); | |
89e5785f | 1631 | clk_put(bp->hclk); |
0cc8674f | 1632 | clk_disable(bp->pclk); |
89e5785f HS |
1633 | clk_put(bp->pclk); |
1634 | free_netdev(dev); | |
1635 | platform_set_drvdata(pdev, NULL); | |
1636 | } | |
1637 | ||
1638 | return 0; | |
1639 | } | |
1640 | ||
c1f598fd HS |
1641 | #ifdef CONFIG_PM |
1642 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1643 | { | |
1644 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1645 | struct macb *bp = netdev_priv(netdev); | |
1646 | ||
03fc4721 | 1647 | netif_carrier_off(netdev); |
c1f598fd HS |
1648 | netif_device_detach(netdev); |
1649 | ||
c1f598fd | 1650 | clk_disable(bp->hclk); |
c1f598fd HS |
1651 | clk_disable(bp->pclk); |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
1656 | static int macb_resume(struct platform_device *pdev) | |
1657 | { | |
1658 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1659 | struct macb *bp = netdev_priv(netdev); | |
1660 | ||
1661 | clk_enable(bp->pclk); | |
c1f598fd | 1662 | clk_enable(bp->hclk); |
c1f598fd HS |
1663 | |
1664 | netif_device_attach(netdev); | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | #else | |
1669 | #define macb_suspend NULL | |
1670 | #define macb_resume NULL | |
1671 | #endif | |
1672 | ||
89e5785f | 1673 | static struct platform_driver macb_driver = { |
06c3fd6a | 1674 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1675 | .suspend = macb_suspend, |
1676 | .resume = macb_resume, | |
89e5785f HS |
1677 | .driver = { |
1678 | .name = "macb", | |
72abb461 | 1679 | .owner = THIS_MODULE, |
fb97a846 | 1680 | .of_match_table = of_match_ptr(macb_dt_ids), |
89e5785f HS |
1681 | }, |
1682 | }; | |
1683 | ||
1684 | static int __init macb_init(void) | |
1685 | { | |
06c3fd6a | 1686 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1687 | } |
1688 | ||
1689 | static void __exit macb_exit(void) | |
1690 | { | |
1691 | platform_driver_unregister(&macb_driver); | |
1692 | } | |
1693 | ||
1694 | module_init(macb_init); | |
1695 | module_exit(macb_exit); | |
1696 | ||
1697 | MODULE_LICENSE("GPL"); | |
f75ba50b | 1698 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 1699 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 1700 | MODULE_ALIAS("platform:macb"); |