Commit | Line | Data |
---|---|---|
89e5785f | 1 | /* |
f75ba50b | 2 | * Cadence MACB/GEM Ethernet Controller driver |
89e5785f HS |
3 | * |
4 | * Copyright (C) 2004-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
c220f8cd | 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
89e5785f HS |
12 | #include <linux/clk.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/init.h> | |
a6b7a407 | 19 | #include <linux/interrupt.h> |
89e5785f HS |
20 | #include <linux/netdevice.h> |
21 | #include <linux/etherdevice.h> | |
89e5785f | 22 | #include <linux/dma-mapping.h> |
84e0cdb0 | 23 | #include <linux/platform_data/macb.h> |
89e5785f | 24 | #include <linux/platform_device.h> |
6c36a707 | 25 | #include <linux/phy.h> |
b17471f5 | 26 | #include <linux/of.h> |
fb97a846 JCPV |
27 | #include <linux/of_device.h> |
28 | #include <linux/of_net.h> | |
89e5785f | 29 | |
89e5785f HS |
30 | #include "macb.h" |
31 | ||
89e5785f HS |
32 | #define RX_BUFFER_SIZE 128 |
33 | #define RX_RING_SIZE 512 | |
34 | #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE) | |
35 | ||
36 | /* Make the IP header word-aligned (the ethernet header is 14 bytes) */ | |
37 | #define RX_OFFSET 2 | |
38 | ||
39 | #define TX_RING_SIZE 128 | |
40 | #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1) | |
41 | #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE) | |
42 | ||
43 | #define TX_RING_GAP(bp) \ | |
44 | (TX_RING_SIZE - (bp)->tx_pending) | |
45 | #define TX_BUFFS_AVAIL(bp) \ | |
46 | (((bp)->tx_tail <= (bp)->tx_head) ? \ | |
47 | (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \ | |
48 | (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp)) | |
49 | #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1)) | |
50 | ||
51 | #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1)) | |
52 | ||
53 | /* minimum number of free TX descriptors before waking up TX process */ | |
54 | #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4) | |
55 | ||
56 | #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | |
57 | | MACB_BIT(ISR_ROVR)) | |
58 | ||
59 | static void __macb_set_hwaddr(struct macb *bp) | |
60 | { | |
61 | u32 bottom; | |
62 | u16 top; | |
63 | ||
64 | bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); | |
f75ba50b | 65 | macb_or_gem_writel(bp, SA1B, bottom); |
89e5785f | 66 | top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); |
f75ba50b | 67 | macb_or_gem_writel(bp, SA1T, top); |
89e5785f HS |
68 | } |
69 | ||
70 | static void __init macb_get_hwaddr(struct macb *bp) | |
71 | { | |
72 | u32 bottom; | |
73 | u16 top; | |
74 | u8 addr[6]; | |
75 | ||
f75ba50b JI |
76 | bottom = macb_or_gem_readl(bp, SA1B); |
77 | top = macb_or_gem_readl(bp, SA1T); | |
89e5785f HS |
78 | |
79 | addr[0] = bottom & 0xff; | |
80 | addr[1] = (bottom >> 8) & 0xff; | |
81 | addr[2] = (bottom >> 16) & 0xff; | |
82 | addr[3] = (bottom >> 24) & 0xff; | |
83 | addr[4] = top & 0xff; | |
84 | addr[5] = (top >> 8) & 0xff; | |
85 | ||
d1d5741d | 86 | if (is_valid_ether_addr(addr)) { |
89e5785f | 87 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); |
d1d5741d | 88 | } else { |
c220f8cd | 89 | netdev_info(bp->dev, "invalid hw address, using random\n"); |
f2cedb63 | 90 | eth_hw_addr_random(bp->dev); |
d1d5741d | 91 | } |
89e5785f HS |
92 | } |
93 | ||
6c36a707 | 94 | static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
89e5785f | 95 | { |
6c36a707 | 96 | struct macb *bp = bus->priv; |
89e5785f HS |
97 | int value; |
98 | ||
89e5785f HS |
99 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) |
100 | | MACB_BF(RW, MACB_MAN_READ) | |
6c36a707 R |
101 | | MACB_BF(PHYA, mii_id) |
102 | | MACB_BF(REGA, regnum) | |
89e5785f HS |
103 | | MACB_BF(CODE, MACB_MAN_CODE))); |
104 | ||
6c36a707 R |
105 | /* wait for end of transfer */ |
106 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
107 | cpu_relax(); | |
89e5785f HS |
108 | |
109 | value = MACB_BFEXT(DATA, macb_readl(bp, MAN)); | |
89e5785f HS |
110 | |
111 | return value; | |
112 | } | |
113 | ||
6c36a707 R |
114 | static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
115 | u16 value) | |
89e5785f | 116 | { |
6c36a707 | 117 | struct macb *bp = bus->priv; |
89e5785f HS |
118 | |
119 | macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF) | |
120 | | MACB_BF(RW, MACB_MAN_WRITE) | |
6c36a707 R |
121 | | MACB_BF(PHYA, mii_id) |
122 | | MACB_BF(REGA, regnum) | |
89e5785f | 123 | | MACB_BF(CODE, MACB_MAN_CODE) |
6c36a707 | 124 | | MACB_BF(DATA, value))); |
89e5785f | 125 | |
6c36a707 R |
126 | /* wait for end of transfer */ |
127 | while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR))) | |
128 | cpu_relax(); | |
129 | ||
130 | return 0; | |
131 | } | |
89e5785f | 132 | |
6c36a707 R |
133 | static int macb_mdio_reset(struct mii_bus *bus) |
134 | { | |
135 | return 0; | |
89e5785f HS |
136 | } |
137 | ||
6c36a707 | 138 | static void macb_handle_link_change(struct net_device *dev) |
89e5785f | 139 | { |
6c36a707 R |
140 | struct macb *bp = netdev_priv(dev); |
141 | struct phy_device *phydev = bp->phy_dev; | |
142 | unsigned long flags; | |
89e5785f | 143 | |
6c36a707 | 144 | int status_change = 0; |
89e5785f | 145 | |
6c36a707 R |
146 | spin_lock_irqsave(&bp->lock, flags); |
147 | ||
148 | if (phydev->link) { | |
149 | if ((bp->speed != phydev->speed) || | |
150 | (bp->duplex != phydev->duplex)) { | |
151 | u32 reg; | |
152 | ||
153 | reg = macb_readl(bp, NCFGR); | |
154 | reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
155 | ||
156 | if (phydev->duplex) | |
157 | reg |= MACB_BIT(FD); | |
179956f4 | 158 | if (phydev->speed == SPEED_100) |
6c36a707 R |
159 | reg |= MACB_BIT(SPD); |
160 | ||
161 | macb_writel(bp, NCFGR, reg); | |
162 | ||
163 | bp->speed = phydev->speed; | |
164 | bp->duplex = phydev->duplex; | |
165 | status_change = 1; | |
166 | } | |
89e5785f HS |
167 | } |
168 | ||
6c36a707 | 169 | if (phydev->link != bp->link) { |
c8f15686 | 170 | if (!phydev->link) { |
6c36a707 R |
171 | bp->speed = 0; |
172 | bp->duplex = -1; | |
173 | } | |
174 | bp->link = phydev->link; | |
89e5785f | 175 | |
6c36a707 R |
176 | status_change = 1; |
177 | } | |
89e5785f | 178 | |
6c36a707 R |
179 | spin_unlock_irqrestore(&bp->lock, flags); |
180 | ||
181 | if (status_change) { | |
03fc4721 NF |
182 | if (phydev->link) { |
183 | netif_carrier_on(dev); | |
c220f8cd JI |
184 | netdev_info(dev, "link up (%d/%s)\n", |
185 | phydev->speed, | |
186 | phydev->duplex == DUPLEX_FULL ? | |
187 | "Full" : "Half"); | |
03fc4721 NF |
188 | } else { |
189 | netif_carrier_off(dev); | |
c220f8cd | 190 | netdev_info(dev, "link down\n"); |
03fc4721 | 191 | } |
6c36a707 | 192 | } |
89e5785f HS |
193 | } |
194 | ||
6c36a707 R |
195 | /* based on au1000_eth. c*/ |
196 | static int macb_mii_probe(struct net_device *dev) | |
89e5785f | 197 | { |
6c36a707 | 198 | struct macb *bp = netdev_priv(dev); |
7455a76f | 199 | struct phy_device *phydev; |
7455a76f | 200 | int ret; |
6c36a707 | 201 | |
7455a76f | 202 | phydev = phy_find_first(bp->mii_bus); |
6c36a707 | 203 | if (!phydev) { |
c220f8cd | 204 | netdev_err(dev, "no PHY found\n"); |
6c36a707 R |
205 | return -1; |
206 | } | |
207 | ||
6c36a707 R |
208 | /* TODO : add pin_irq */ |
209 | ||
210 | /* attach the mac to the phy */ | |
7455a76f | 211 | ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0, |
fb97a846 | 212 | bp->phy_interface); |
7455a76f | 213 | if (ret) { |
c220f8cd | 214 | netdev_err(dev, "Could not attach to PHY\n"); |
7455a76f | 215 | return ret; |
6c36a707 R |
216 | } |
217 | ||
218 | /* mask with MAC supported features */ | |
219 | phydev->supported &= PHY_BASIC_FEATURES; | |
220 | ||
221 | phydev->advertising = phydev->supported; | |
222 | ||
223 | bp->link = 0; | |
224 | bp->speed = 0; | |
225 | bp->duplex = -1; | |
226 | bp->phy_dev = phydev; | |
227 | ||
228 | return 0; | |
89e5785f HS |
229 | } |
230 | ||
0005f541 | 231 | int macb_mii_init(struct macb *bp) |
89e5785f | 232 | { |
84e0cdb0 | 233 | struct macb_platform_data *pdata; |
6c36a707 | 234 | int err = -ENXIO, i; |
89e5785f | 235 | |
3dbda77e | 236 | /* Enable management port */ |
6c36a707 | 237 | macb_writel(bp, NCR, MACB_BIT(MPE)); |
89e5785f | 238 | |
298cf9be LB |
239 | bp->mii_bus = mdiobus_alloc(); |
240 | if (bp->mii_bus == NULL) { | |
241 | err = -ENOMEM; | |
242 | goto err_out; | |
243 | } | |
244 | ||
245 | bp->mii_bus->name = "MACB_mii_bus"; | |
246 | bp->mii_bus->read = &macb_mdio_read; | |
247 | bp->mii_bus->write = &macb_mdio_write; | |
248 | bp->mii_bus->reset = &macb_mdio_reset; | |
98d5e57e FF |
249 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
250 | bp->pdev->name, bp->pdev->id); | |
298cf9be LB |
251 | bp->mii_bus->priv = bp; |
252 | bp->mii_bus->parent = &bp->dev->dev; | |
6c36a707 | 253 | pdata = bp->pdev->dev.platform_data; |
89e5785f | 254 | |
6c36a707 | 255 | if (pdata) |
298cf9be | 256 | bp->mii_bus->phy_mask = pdata->phy_mask; |
89e5785f | 257 | |
298cf9be LB |
258 | bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
259 | if (!bp->mii_bus->irq) { | |
6c36a707 | 260 | err = -ENOMEM; |
298cf9be | 261 | goto err_out_free_mdiobus; |
89e5785f HS |
262 | } |
263 | ||
6c36a707 | 264 | for (i = 0; i < PHY_MAX_ADDR; i++) |
298cf9be | 265 | bp->mii_bus->irq[i] = PHY_POLL; |
89e5785f | 266 | |
91523947 | 267 | dev_set_drvdata(&bp->dev->dev, bp->mii_bus); |
89e5785f | 268 | |
298cf9be | 269 | if (mdiobus_register(bp->mii_bus)) |
6c36a707 | 270 | goto err_out_free_mdio_irq; |
89e5785f | 271 | |
6c36a707 R |
272 | if (macb_mii_probe(bp->dev) != 0) { |
273 | goto err_out_unregister_bus; | |
274 | } | |
89e5785f | 275 | |
6c36a707 | 276 | return 0; |
89e5785f | 277 | |
6c36a707 | 278 | err_out_unregister_bus: |
298cf9be | 279 | mdiobus_unregister(bp->mii_bus); |
6c36a707 | 280 | err_out_free_mdio_irq: |
298cf9be LB |
281 | kfree(bp->mii_bus->irq); |
282 | err_out_free_mdiobus: | |
283 | mdiobus_free(bp->mii_bus); | |
6c36a707 R |
284 | err_out: |
285 | return err; | |
89e5785f | 286 | } |
0005f541 | 287 | EXPORT_SYMBOL_GPL(macb_mii_init); |
89e5785f HS |
288 | |
289 | static void macb_update_stats(struct macb *bp) | |
290 | { | |
291 | u32 __iomem *reg = bp->regs + MACB_PFR; | |
a494ed8e JI |
292 | u32 *p = &bp->hw_stats.macb.rx_pause_frames; |
293 | u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; | |
89e5785f HS |
294 | |
295 | WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); | |
296 | ||
297 | for(; p < end; p++, reg++) | |
0f0d84e5 | 298 | *p += __raw_readl(reg); |
89e5785f HS |
299 | } |
300 | ||
89e5785f HS |
301 | static void macb_tx(struct macb *bp) |
302 | { | |
303 | unsigned int tail; | |
304 | unsigned int head; | |
305 | u32 status; | |
306 | ||
307 | status = macb_readl(bp, TSR); | |
308 | macb_writel(bp, TSR, status); | |
309 | ||
c220f8cd | 310 | netdev_dbg(bp->dev, "macb_tx status = %02lx\n", (unsigned long)status); |
89e5785f | 311 | |
ee33c585 | 312 | if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) { |
bdcba151 | 313 | int i; |
c220f8cd JI |
314 | netdev_err(bp->dev, "TX %s, resetting buffers\n", |
315 | status & MACB_BIT(UND) ? | |
316 | "underrun" : "retry limit exceeded"); | |
bdcba151 | 317 | |
39eddb4c RR |
318 | /* Transfer ongoing, disable transmitter, to avoid confusion */ |
319 | if (status & MACB_BIT(TGO)) | |
320 | macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE)); | |
321 | ||
bdcba151 GC |
322 | head = bp->tx_head; |
323 | ||
324 | /*Mark all the buffer as used to avoid sending a lost buffer*/ | |
325 | for (i = 0; i < TX_RING_SIZE; i++) | |
326 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
327 | ||
d3e61457 TA |
328 | /* Add wrap bit */ |
329 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
330 | ||
bdcba151 GC |
331 | /* free transmit buffer in upper layer*/ |
332 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
333 | struct ring_info *rp = &bp->tx_skb[tail]; | |
334 | struct sk_buff *skb = rp->skb; | |
335 | ||
336 | BUG_ON(skb == NULL); | |
337 | ||
338 | rmb(); | |
339 | ||
340 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, | |
341 | DMA_TO_DEVICE); | |
342 | rp->skb = NULL; | |
343 | dev_kfree_skb_irq(skb); | |
344 | } | |
345 | ||
89e5785f | 346 | bp->tx_head = bp->tx_tail = 0; |
39eddb4c RR |
347 | |
348 | /* Enable the transmitter again */ | |
349 | if (status & MACB_BIT(TGO)) | |
350 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE)); | |
89e5785f HS |
351 | } |
352 | ||
353 | if (!(status & MACB_BIT(COMP))) | |
354 | /* | |
355 | * This may happen when a buffer becomes complete | |
356 | * between reading the ISR and scanning the | |
357 | * descriptors. Nothing to worry about. | |
358 | */ | |
359 | return; | |
360 | ||
361 | head = bp->tx_head; | |
362 | for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) { | |
363 | struct ring_info *rp = &bp->tx_skb[tail]; | |
364 | struct sk_buff *skb = rp->skb; | |
365 | u32 bufstat; | |
366 | ||
367 | BUG_ON(skb == NULL); | |
368 | ||
369 | rmb(); | |
370 | bufstat = bp->tx_ring[tail].ctrl; | |
371 | ||
372 | if (!(bufstat & MACB_BIT(TX_USED))) | |
373 | break; | |
374 | ||
c220f8cd JI |
375 | netdev_dbg(bp->dev, "skb %u (data %p) TX complete\n", |
376 | tail, skb->data); | |
89e5785f HS |
377 | dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len, |
378 | DMA_TO_DEVICE); | |
379 | bp->stats.tx_packets++; | |
380 | bp->stats.tx_bytes += skb->len; | |
381 | rp->skb = NULL; | |
382 | dev_kfree_skb_irq(skb); | |
383 | } | |
384 | ||
385 | bp->tx_tail = tail; | |
386 | if (netif_queue_stopped(bp->dev) && | |
387 | TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH) | |
388 | netif_wake_queue(bp->dev); | |
389 | } | |
390 | ||
391 | static int macb_rx_frame(struct macb *bp, unsigned int first_frag, | |
392 | unsigned int last_frag) | |
393 | { | |
394 | unsigned int len; | |
395 | unsigned int frag; | |
396 | unsigned int offset = 0; | |
397 | struct sk_buff *skb; | |
398 | ||
399 | len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl); | |
400 | ||
c220f8cd JI |
401 | netdev_dbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", |
402 | first_frag, last_frag, len); | |
89e5785f | 403 | |
21a4e469 | 404 | skb = netdev_alloc_skb(bp->dev, len + RX_OFFSET); |
89e5785f HS |
405 | if (!skb) { |
406 | bp->stats.rx_dropped++; | |
407 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
408 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
409 | if (frag == last_frag) | |
410 | break; | |
411 | } | |
412 | wmb(); | |
413 | return 1; | |
414 | } | |
415 | ||
416 | skb_reserve(skb, RX_OFFSET); | |
bc8acf2c | 417 | skb_checksum_none_assert(skb); |
89e5785f HS |
418 | skb_put(skb, len); |
419 | ||
420 | for (frag = first_frag; ; frag = NEXT_RX(frag)) { | |
421 | unsigned int frag_len = RX_BUFFER_SIZE; | |
422 | ||
423 | if (offset + frag_len > len) { | |
424 | BUG_ON(frag != last_frag); | |
425 | frag_len = len - offset; | |
426 | } | |
27d7ff46 ACM |
427 | skb_copy_to_linear_data_offset(skb, offset, |
428 | (bp->rx_buffers + | |
429 | (RX_BUFFER_SIZE * frag)), | |
430 | frag_len); | |
89e5785f HS |
431 | offset += RX_BUFFER_SIZE; |
432 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
433 | wmb(); | |
434 | ||
435 | if (frag == last_frag) | |
436 | break; | |
437 | } | |
438 | ||
439 | skb->protocol = eth_type_trans(skb, bp->dev); | |
440 | ||
441 | bp->stats.rx_packets++; | |
442 | bp->stats.rx_bytes += len; | |
c220f8cd JI |
443 | netdev_dbg(bp->dev, "received skb of length %u, csum: %08x\n", |
444 | skb->len, skb->csum); | |
89e5785f HS |
445 | netif_receive_skb(skb); |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | /* Mark DMA descriptors from begin up to and not including end as unused */ | |
451 | static void discard_partial_frame(struct macb *bp, unsigned int begin, | |
452 | unsigned int end) | |
453 | { | |
454 | unsigned int frag; | |
455 | ||
456 | for (frag = begin; frag != end; frag = NEXT_RX(frag)) | |
457 | bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED); | |
458 | wmb(); | |
459 | ||
460 | /* | |
461 | * When this happens, the hardware stats registers for | |
462 | * whatever caused this is updated, so we don't have to record | |
463 | * anything. | |
464 | */ | |
465 | } | |
466 | ||
467 | static int macb_rx(struct macb *bp, int budget) | |
468 | { | |
469 | int received = 0; | |
470 | unsigned int tail = bp->rx_tail; | |
471 | int first_frag = -1; | |
472 | ||
473 | for (; budget > 0; tail = NEXT_RX(tail)) { | |
474 | u32 addr, ctrl; | |
475 | ||
476 | rmb(); | |
477 | addr = bp->rx_ring[tail].addr; | |
478 | ctrl = bp->rx_ring[tail].ctrl; | |
479 | ||
480 | if (!(addr & MACB_BIT(RX_USED))) | |
481 | break; | |
482 | ||
483 | if (ctrl & MACB_BIT(RX_SOF)) { | |
484 | if (first_frag != -1) | |
485 | discard_partial_frame(bp, first_frag, tail); | |
486 | first_frag = tail; | |
487 | } | |
488 | ||
489 | if (ctrl & MACB_BIT(RX_EOF)) { | |
490 | int dropped; | |
491 | BUG_ON(first_frag == -1); | |
492 | ||
493 | dropped = macb_rx_frame(bp, first_frag, tail); | |
494 | first_frag = -1; | |
495 | if (!dropped) { | |
496 | received++; | |
497 | budget--; | |
498 | } | |
499 | } | |
500 | } | |
501 | ||
502 | if (first_frag != -1) | |
503 | bp->rx_tail = first_frag; | |
504 | else | |
505 | bp->rx_tail = tail; | |
506 | ||
507 | return received; | |
508 | } | |
509 | ||
bea3348e | 510 | static int macb_poll(struct napi_struct *napi, int budget) |
89e5785f | 511 | { |
bea3348e | 512 | struct macb *bp = container_of(napi, struct macb, napi); |
bea3348e | 513 | int work_done; |
89e5785f HS |
514 | u32 status; |
515 | ||
516 | status = macb_readl(bp, RSR); | |
517 | macb_writel(bp, RSR, status); | |
518 | ||
bea3348e | 519 | work_done = 0; |
89e5785f | 520 | |
c220f8cd JI |
521 | netdev_dbg(bp->dev, "poll: status = %08lx, budget = %d\n", |
522 | (unsigned long)status, budget); | |
89e5785f | 523 | |
bea3348e | 524 | work_done = macb_rx(bp, budget); |
b336369c | 525 | if (work_done < budget) { |
288379f0 | 526 | napi_complete(napi); |
89e5785f | 527 | |
b336369c JH |
528 | /* |
529 | * We've done what we can to clean the buffers. Make sure we | |
530 | * get notified when new packets arrive. | |
531 | */ | |
532 | macb_writel(bp, IER, MACB_RX_INT_FLAGS); | |
533 | } | |
89e5785f HS |
534 | |
535 | /* TODO: Handle errors */ | |
536 | ||
bea3348e | 537 | return work_done; |
89e5785f HS |
538 | } |
539 | ||
540 | static irqreturn_t macb_interrupt(int irq, void *dev_id) | |
541 | { | |
542 | struct net_device *dev = dev_id; | |
543 | struct macb *bp = netdev_priv(dev); | |
544 | u32 status; | |
545 | ||
546 | status = macb_readl(bp, ISR); | |
547 | ||
548 | if (unlikely(!status)) | |
549 | return IRQ_NONE; | |
550 | ||
551 | spin_lock(&bp->lock); | |
552 | ||
553 | while (status) { | |
89e5785f HS |
554 | /* close possible race with dev_close */ |
555 | if (unlikely(!netif_running(dev))) { | |
556 | macb_writel(bp, IDR, ~0UL); | |
557 | break; | |
558 | } | |
559 | ||
560 | if (status & MACB_RX_INT_FLAGS) { | |
b336369c JH |
561 | /* |
562 | * There's no point taking any more interrupts | |
563 | * until we have processed the buffers. The | |
564 | * scheduling call may fail if the poll routine | |
565 | * is already scheduled, so disable interrupts | |
566 | * now. | |
567 | */ | |
568 | macb_writel(bp, IDR, MACB_RX_INT_FLAGS); | |
569 | ||
288379f0 | 570 | if (napi_schedule_prep(&bp->napi)) { |
c220f8cd | 571 | netdev_dbg(bp->dev, "scheduling RX softirq\n"); |
288379f0 | 572 | __napi_schedule(&bp->napi); |
89e5785f HS |
573 | } |
574 | } | |
575 | ||
ee33c585 EW |
576 | if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | |
577 | MACB_BIT(ISR_RLE))) | |
89e5785f HS |
578 | macb_tx(bp); |
579 | ||
580 | /* | |
581 | * Link change detection isn't possible with RMII, so we'll | |
582 | * add that if/when we get our hands on a full-blown MII PHY. | |
583 | */ | |
584 | ||
b19f7f71 AS |
585 | if (status & MACB_BIT(ISR_ROVR)) { |
586 | /* We missed at least one packet */ | |
f75ba50b JI |
587 | if (macb_is_gem(bp)) |
588 | bp->hw_stats.gem.rx_overruns++; | |
589 | else | |
590 | bp->hw_stats.macb.rx_overruns++; | |
b19f7f71 AS |
591 | } |
592 | ||
89e5785f HS |
593 | if (status & MACB_BIT(HRESP)) { |
594 | /* | |
c220f8cd JI |
595 | * TODO: Reset the hardware, and maybe move the |
596 | * netdev_err to a lower-priority context as well | |
597 | * (work queue?) | |
89e5785f | 598 | */ |
c220f8cd | 599 | netdev_err(dev, "DMA bus error: HRESP not OK\n"); |
89e5785f HS |
600 | } |
601 | ||
602 | status = macb_readl(bp, ISR); | |
603 | } | |
604 | ||
605 | spin_unlock(&bp->lock); | |
606 | ||
607 | return IRQ_HANDLED; | |
608 | } | |
609 | ||
6e8cf5c0 TP |
610 | #ifdef CONFIG_NET_POLL_CONTROLLER |
611 | /* | |
612 | * Polling receive - used by netconsole and other diagnostic tools | |
613 | * to allow network i/o with interrupts disabled. | |
614 | */ | |
615 | static void macb_poll_controller(struct net_device *dev) | |
616 | { | |
617 | unsigned long flags; | |
618 | ||
619 | local_irq_save(flags); | |
620 | macb_interrupt(dev->irq, dev); | |
621 | local_irq_restore(flags); | |
622 | } | |
623 | #endif | |
624 | ||
89e5785f HS |
625 | static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev) |
626 | { | |
627 | struct macb *bp = netdev_priv(dev); | |
628 | dma_addr_t mapping; | |
629 | unsigned int len, entry; | |
630 | u32 ctrl; | |
4871953c | 631 | unsigned long flags; |
89e5785f HS |
632 | |
633 | #ifdef DEBUG | |
c220f8cd JI |
634 | netdev_dbg(bp->dev, |
635 | "start_xmit: len %u head %p data %p tail %p end %p\n", | |
636 | skb->len, skb->head, skb->data, | |
637 | skb_tail_pointer(skb), skb_end_pointer(skb)); | |
638 | print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, | |
639 | skb->data, 16, true); | |
89e5785f HS |
640 | #endif |
641 | ||
642 | len = skb->len; | |
4871953c | 643 | spin_lock_irqsave(&bp->lock, flags); |
89e5785f HS |
644 | |
645 | /* This is a hard error, log it. */ | |
646 | if (TX_BUFFS_AVAIL(bp) < 1) { | |
647 | netif_stop_queue(dev); | |
4871953c | 648 | spin_unlock_irqrestore(&bp->lock, flags); |
c220f8cd JI |
649 | netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n"); |
650 | netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", | |
651 | bp->tx_head, bp->tx_tail); | |
5b548140 | 652 | return NETDEV_TX_BUSY; |
89e5785f HS |
653 | } |
654 | ||
655 | entry = bp->tx_head; | |
c220f8cd | 656 | netdev_dbg(bp->dev, "Allocated ring entry %u\n", entry); |
89e5785f HS |
657 | mapping = dma_map_single(&bp->pdev->dev, skb->data, |
658 | len, DMA_TO_DEVICE); | |
659 | bp->tx_skb[entry].skb = skb; | |
660 | bp->tx_skb[entry].mapping = mapping; | |
c220f8cd JI |
661 | netdev_dbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n", |
662 | skb->data, (unsigned long)mapping); | |
89e5785f HS |
663 | |
664 | ctrl = MACB_BF(TX_FRMLEN, len); | |
665 | ctrl |= MACB_BIT(TX_LAST); | |
666 | if (entry == (TX_RING_SIZE - 1)) | |
667 | ctrl |= MACB_BIT(TX_WRAP); | |
668 | ||
669 | bp->tx_ring[entry].addr = mapping; | |
670 | bp->tx_ring[entry].ctrl = ctrl; | |
671 | wmb(); | |
672 | ||
673 | entry = NEXT_TX(entry); | |
674 | bp->tx_head = entry; | |
675 | ||
e072092f RC |
676 | skb_tx_timestamp(skb); |
677 | ||
89e5785f HS |
678 | macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); |
679 | ||
680 | if (TX_BUFFS_AVAIL(bp) < 1) | |
681 | netif_stop_queue(dev); | |
682 | ||
4871953c | 683 | spin_unlock_irqrestore(&bp->lock, flags); |
89e5785f | 684 | |
6ed10654 | 685 | return NETDEV_TX_OK; |
89e5785f HS |
686 | } |
687 | ||
688 | static void macb_free_consistent(struct macb *bp) | |
689 | { | |
690 | if (bp->tx_skb) { | |
691 | kfree(bp->tx_skb); | |
692 | bp->tx_skb = NULL; | |
693 | } | |
694 | if (bp->rx_ring) { | |
695 | dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES, | |
696 | bp->rx_ring, bp->rx_ring_dma); | |
697 | bp->rx_ring = NULL; | |
698 | } | |
699 | if (bp->tx_ring) { | |
700 | dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES, | |
701 | bp->tx_ring, bp->tx_ring_dma); | |
702 | bp->tx_ring = NULL; | |
703 | } | |
704 | if (bp->rx_buffers) { | |
705 | dma_free_coherent(&bp->pdev->dev, | |
706 | RX_RING_SIZE * RX_BUFFER_SIZE, | |
707 | bp->rx_buffers, bp->rx_buffers_dma); | |
708 | bp->rx_buffers = NULL; | |
709 | } | |
710 | } | |
711 | ||
712 | static int macb_alloc_consistent(struct macb *bp) | |
713 | { | |
714 | int size; | |
715 | ||
716 | size = TX_RING_SIZE * sizeof(struct ring_info); | |
717 | bp->tx_skb = kmalloc(size, GFP_KERNEL); | |
718 | if (!bp->tx_skb) | |
719 | goto out_err; | |
720 | ||
721 | size = RX_RING_BYTES; | |
722 | bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
723 | &bp->rx_ring_dma, GFP_KERNEL); | |
724 | if (!bp->rx_ring) | |
725 | goto out_err; | |
c220f8cd JI |
726 | netdev_dbg(bp->dev, |
727 | "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", | |
728 | size, (unsigned long)bp->rx_ring_dma, bp->rx_ring); | |
89e5785f HS |
729 | |
730 | size = TX_RING_BYTES; | |
731 | bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, | |
732 | &bp->tx_ring_dma, GFP_KERNEL); | |
733 | if (!bp->tx_ring) | |
734 | goto out_err; | |
c220f8cd JI |
735 | netdev_dbg(bp->dev, |
736 | "Allocated TX ring of %d bytes at %08lx (mapped %p)\n", | |
737 | size, (unsigned long)bp->tx_ring_dma, bp->tx_ring); | |
89e5785f HS |
738 | |
739 | size = RX_RING_SIZE * RX_BUFFER_SIZE; | |
740 | bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, | |
741 | &bp->rx_buffers_dma, GFP_KERNEL); | |
742 | if (!bp->rx_buffers) | |
743 | goto out_err; | |
c220f8cd JI |
744 | netdev_dbg(bp->dev, |
745 | "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n", | |
746 | size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers); | |
89e5785f HS |
747 | |
748 | return 0; | |
749 | ||
750 | out_err: | |
751 | macb_free_consistent(bp); | |
752 | return -ENOMEM; | |
753 | } | |
754 | ||
755 | static void macb_init_rings(struct macb *bp) | |
756 | { | |
757 | int i; | |
758 | dma_addr_t addr; | |
759 | ||
760 | addr = bp->rx_buffers_dma; | |
761 | for (i = 0; i < RX_RING_SIZE; i++) { | |
762 | bp->rx_ring[i].addr = addr; | |
763 | bp->rx_ring[i].ctrl = 0; | |
764 | addr += RX_BUFFER_SIZE; | |
765 | } | |
766 | bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP); | |
767 | ||
768 | for (i = 0; i < TX_RING_SIZE; i++) { | |
769 | bp->tx_ring[i].addr = 0; | |
770 | bp->tx_ring[i].ctrl = MACB_BIT(TX_USED); | |
771 | } | |
772 | bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP); | |
773 | ||
774 | bp->rx_tail = bp->tx_head = bp->tx_tail = 0; | |
775 | } | |
776 | ||
777 | static void macb_reset_hw(struct macb *bp) | |
778 | { | |
779 | /* Make sure we have the write buffer for ourselves */ | |
780 | wmb(); | |
781 | ||
782 | /* | |
783 | * Disable RX and TX (XXX: Should we halt the transmission | |
784 | * more gracefully?) | |
785 | */ | |
786 | macb_writel(bp, NCR, 0); | |
787 | ||
788 | /* Clear the stats registers (XXX: Update stats first?) */ | |
789 | macb_writel(bp, NCR, MACB_BIT(CLRSTAT)); | |
790 | ||
791 | /* Clear all status flags */ | |
792 | macb_writel(bp, TSR, ~0UL); | |
793 | macb_writel(bp, RSR, ~0UL); | |
794 | ||
795 | /* Disable all interrupts */ | |
796 | macb_writel(bp, IDR, ~0UL); | |
797 | macb_readl(bp, ISR); | |
798 | } | |
799 | ||
70c9f3d4 JI |
800 | static u32 gem_mdc_clk_div(struct macb *bp) |
801 | { | |
802 | u32 config; | |
803 | unsigned long pclk_hz = clk_get_rate(bp->pclk); | |
804 | ||
805 | if (pclk_hz <= 20000000) | |
806 | config = GEM_BF(CLK, GEM_CLK_DIV8); | |
807 | else if (pclk_hz <= 40000000) | |
808 | config = GEM_BF(CLK, GEM_CLK_DIV16); | |
809 | else if (pclk_hz <= 80000000) | |
810 | config = GEM_BF(CLK, GEM_CLK_DIV32); | |
811 | else if (pclk_hz <= 120000000) | |
812 | config = GEM_BF(CLK, GEM_CLK_DIV48); | |
813 | else if (pclk_hz <= 160000000) | |
814 | config = GEM_BF(CLK, GEM_CLK_DIV64); | |
815 | else | |
816 | config = GEM_BF(CLK, GEM_CLK_DIV96); | |
817 | ||
818 | return config; | |
819 | } | |
820 | ||
821 | static u32 macb_mdc_clk_div(struct macb *bp) | |
822 | { | |
823 | u32 config; | |
824 | unsigned long pclk_hz; | |
825 | ||
826 | if (macb_is_gem(bp)) | |
827 | return gem_mdc_clk_div(bp); | |
828 | ||
829 | pclk_hz = clk_get_rate(bp->pclk); | |
830 | if (pclk_hz <= 20000000) | |
831 | config = MACB_BF(CLK, MACB_CLK_DIV8); | |
832 | else if (pclk_hz <= 40000000) | |
833 | config = MACB_BF(CLK, MACB_CLK_DIV16); | |
834 | else if (pclk_hz <= 80000000) | |
835 | config = MACB_BF(CLK, MACB_CLK_DIV32); | |
836 | else | |
837 | config = MACB_BF(CLK, MACB_CLK_DIV64); | |
838 | ||
839 | return config; | |
840 | } | |
841 | ||
757a03c6 JI |
842 | /* |
843 | * Get the DMA bus width field of the network configuration register that we | |
844 | * should program. We find the width from decoding the design configuration | |
845 | * register to find the maximum supported data bus width. | |
846 | */ | |
847 | static u32 macb_dbw(struct macb *bp) | |
848 | { | |
849 | if (!macb_is_gem(bp)) | |
850 | return 0; | |
851 | ||
852 | switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) { | |
853 | case 4: | |
854 | return GEM_BF(DBW, GEM_DBW128); | |
855 | case 2: | |
856 | return GEM_BF(DBW, GEM_DBW64); | |
857 | case 1: | |
858 | default: | |
859 | return GEM_BF(DBW, GEM_DBW32); | |
860 | } | |
861 | } | |
862 | ||
0116da4f JI |
863 | /* |
864 | * Configure the receive DMA engine to use the correct receive buffer size. | |
865 | * This is a configurable parameter for GEM. | |
866 | */ | |
867 | static void macb_configure_dma(struct macb *bp) | |
868 | { | |
869 | u32 dmacfg; | |
870 | ||
871 | if (macb_is_gem(bp)) { | |
872 | dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); | |
873 | dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); | |
874 | gem_writel(bp, DMACFG, dmacfg); | |
875 | } | |
876 | } | |
877 | ||
89e5785f HS |
878 | static void macb_init_hw(struct macb *bp) |
879 | { | |
880 | u32 config; | |
881 | ||
882 | macb_reset_hw(bp); | |
883 | __macb_set_hwaddr(bp); | |
884 | ||
70c9f3d4 | 885 | config = macb_mdc_clk_div(bp); |
89e5785f HS |
886 | config |= MACB_BIT(PAE); /* PAuse Enable */ |
887 | config |= MACB_BIT(DRFCS); /* Discard Rx FCS */ | |
8dd4bd00 | 888 | config |= MACB_BIT(BIG); /* Receive oversized frames */ |
89e5785f HS |
889 | if (bp->dev->flags & IFF_PROMISC) |
890 | config |= MACB_BIT(CAF); /* Copy All Frames */ | |
891 | if (!(bp->dev->flags & IFF_BROADCAST)) | |
892 | config |= MACB_BIT(NBC); /* No BroadCast */ | |
757a03c6 | 893 | config |= macb_dbw(bp); |
89e5785f HS |
894 | macb_writel(bp, NCFGR, config); |
895 | ||
0116da4f JI |
896 | macb_configure_dma(bp); |
897 | ||
89e5785f HS |
898 | /* Initialize TX and RX buffers */ |
899 | macb_writel(bp, RBQP, bp->rx_ring_dma); | |
900 | macb_writel(bp, TBQP, bp->tx_ring_dma); | |
901 | ||
902 | /* Enable TX and RX */ | |
6c36a707 | 903 | macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE)); |
89e5785f HS |
904 | |
905 | /* Enable interrupts */ | |
906 | macb_writel(bp, IER, (MACB_BIT(RCOMP) | |
907 | | MACB_BIT(RXUBR) | |
908 | | MACB_BIT(ISR_TUND) | |
909 | | MACB_BIT(ISR_RLE) | |
910 | | MACB_BIT(TXERR) | |
911 | | MACB_BIT(TCOMP) | |
912 | | MACB_BIT(ISR_ROVR) | |
913 | | MACB_BIT(HRESP))); | |
89e5785f | 914 | |
89e5785f HS |
915 | } |
916 | ||
446ebd01 PV |
917 | /* |
918 | * The hash address register is 64 bits long and takes up two | |
919 | * locations in the memory map. The least significant bits are stored | |
920 | * in EMAC_HSL and the most significant bits in EMAC_HSH. | |
921 | * | |
922 | * The unicast hash enable and the multicast hash enable bits in the | |
923 | * network configuration register enable the reception of hash matched | |
924 | * frames. The destination address is reduced to a 6 bit index into | |
925 | * the 64 bit hash register using the following hash function. The | |
926 | * hash function is an exclusive or of every sixth bit of the | |
927 | * destination address. | |
928 | * | |
929 | * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
930 | * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
931 | * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
932 | * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
933 | * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
934 | * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
935 | * | |
936 | * da[0] represents the least significant bit of the first byte | |
937 | * received, that is, the multicast/unicast indicator, and da[47] | |
938 | * represents the most significant bit of the last byte received. If | |
939 | * the hash index, hi[n], points to a bit that is set in the hash | |
940 | * register then the frame will be matched according to whether the | |
941 | * frame is multicast or unicast. A multicast match will be signalled | |
942 | * if the multicast hash enable bit is set, da[0] is 1 and the hash | |
943 | * index points to a bit set in the hash register. A unicast match | |
944 | * will be signalled if the unicast hash enable bit is set, da[0] is 0 | |
945 | * and the hash index points to a bit set in the hash register. To | |
946 | * receive all multicast frames, the hash register should be set with | |
947 | * all ones and the multicast hash enable bit should be set in the | |
948 | * network configuration register. | |
949 | */ | |
950 | ||
951 | static inline int hash_bit_value(int bitnr, __u8 *addr) | |
952 | { | |
953 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
954 | return 1; | |
955 | return 0; | |
956 | } | |
957 | ||
958 | /* | |
959 | * Return the hash index value for the specified address. | |
960 | */ | |
961 | static int hash_get_index(__u8 *addr) | |
962 | { | |
963 | int i, j, bitval; | |
964 | int hash_index = 0; | |
965 | ||
966 | for (j = 0; j < 6; j++) { | |
967 | for (i = 0, bitval = 0; i < 8; i++) | |
968 | bitval ^= hash_bit_value(i*6 + j, addr); | |
969 | ||
970 | hash_index |= (bitval << j); | |
971 | } | |
972 | ||
973 | return hash_index; | |
974 | } | |
975 | ||
976 | /* | |
977 | * Add multicast addresses to the internal multicast-hash table. | |
978 | */ | |
979 | static void macb_sethashtable(struct net_device *dev) | |
980 | { | |
22bedad3 | 981 | struct netdev_hw_addr *ha; |
446ebd01 | 982 | unsigned long mc_filter[2]; |
f9dcbcc9 | 983 | unsigned int bitnr; |
446ebd01 PV |
984 | struct macb *bp = netdev_priv(dev); |
985 | ||
986 | mc_filter[0] = mc_filter[1] = 0; | |
987 | ||
22bedad3 JP |
988 | netdev_for_each_mc_addr(ha, dev) { |
989 | bitnr = hash_get_index(ha->addr); | |
446ebd01 PV |
990 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
991 | } | |
992 | ||
f75ba50b JI |
993 | macb_or_gem_writel(bp, HRB, mc_filter[0]); |
994 | macb_or_gem_writel(bp, HRT, mc_filter[1]); | |
446ebd01 PV |
995 | } |
996 | ||
997 | /* | |
998 | * Enable/Disable promiscuous and multicast modes. | |
999 | */ | |
1000 | static void macb_set_rx_mode(struct net_device *dev) | |
1001 | { | |
1002 | unsigned long cfg; | |
1003 | struct macb *bp = netdev_priv(dev); | |
1004 | ||
1005 | cfg = macb_readl(bp, NCFGR); | |
1006 | ||
1007 | if (dev->flags & IFF_PROMISC) | |
1008 | /* Enable promiscuous mode */ | |
1009 | cfg |= MACB_BIT(CAF); | |
1010 | else if (dev->flags & (~IFF_PROMISC)) | |
1011 | /* Disable promiscuous mode */ | |
1012 | cfg &= ~MACB_BIT(CAF); | |
1013 | ||
1014 | if (dev->flags & IFF_ALLMULTI) { | |
1015 | /* Enable all multicast mode */ | |
f75ba50b JI |
1016 | macb_or_gem_writel(bp, HRB, -1); |
1017 | macb_or_gem_writel(bp, HRT, -1); | |
446ebd01 | 1018 | cfg |= MACB_BIT(NCFGR_MTI); |
4cd24eaf | 1019 | } else if (!netdev_mc_empty(dev)) { |
446ebd01 PV |
1020 | /* Enable specific multicasts */ |
1021 | macb_sethashtable(dev); | |
1022 | cfg |= MACB_BIT(NCFGR_MTI); | |
1023 | } else if (dev->flags & (~IFF_ALLMULTI)) { | |
1024 | /* Disable all multicast mode */ | |
f75ba50b JI |
1025 | macb_or_gem_writel(bp, HRB, 0); |
1026 | macb_or_gem_writel(bp, HRT, 0); | |
446ebd01 PV |
1027 | cfg &= ~MACB_BIT(NCFGR_MTI); |
1028 | } | |
1029 | ||
1030 | macb_writel(bp, NCFGR, cfg); | |
1031 | } | |
1032 | ||
89e5785f HS |
1033 | static int macb_open(struct net_device *dev) |
1034 | { | |
1035 | struct macb *bp = netdev_priv(dev); | |
1036 | int err; | |
1037 | ||
c220f8cd | 1038 | netdev_dbg(bp->dev, "open\n"); |
89e5785f | 1039 | |
03fc4721 NF |
1040 | /* carrier starts down */ |
1041 | netif_carrier_off(dev); | |
1042 | ||
6c36a707 R |
1043 | /* if the phy is not yet register, retry later*/ |
1044 | if (!bp->phy_dev) | |
1045 | return -EAGAIN; | |
1046 | ||
89e5785f HS |
1047 | if (!is_valid_ether_addr(dev->dev_addr)) |
1048 | return -EADDRNOTAVAIL; | |
1049 | ||
1050 | err = macb_alloc_consistent(bp); | |
1051 | if (err) { | |
c220f8cd JI |
1052 | netdev_err(dev, "Unable to allocate DMA memory (error %d)\n", |
1053 | err); | |
89e5785f HS |
1054 | return err; |
1055 | } | |
1056 | ||
bea3348e SH |
1057 | napi_enable(&bp->napi); |
1058 | ||
89e5785f HS |
1059 | macb_init_rings(bp); |
1060 | macb_init_hw(bp); | |
89e5785f | 1061 | |
6c36a707 R |
1062 | /* schedule a link state check */ |
1063 | phy_start(bp->phy_dev); | |
89e5785f | 1064 | |
6c36a707 | 1065 | netif_start_queue(dev); |
89e5785f HS |
1066 | |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static int macb_close(struct net_device *dev) | |
1071 | { | |
1072 | struct macb *bp = netdev_priv(dev); | |
1073 | unsigned long flags; | |
1074 | ||
89e5785f | 1075 | netif_stop_queue(dev); |
bea3348e | 1076 | napi_disable(&bp->napi); |
89e5785f | 1077 | |
6c36a707 R |
1078 | if (bp->phy_dev) |
1079 | phy_stop(bp->phy_dev); | |
1080 | ||
89e5785f HS |
1081 | spin_lock_irqsave(&bp->lock, flags); |
1082 | macb_reset_hw(bp); | |
1083 | netif_carrier_off(dev); | |
1084 | spin_unlock_irqrestore(&bp->lock, flags); | |
1085 | ||
1086 | macb_free_consistent(bp); | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
a494ed8e JI |
1091 | static void gem_update_stats(struct macb *bp) |
1092 | { | |
1093 | u32 __iomem *reg = bp->regs + GEM_OTX; | |
1094 | u32 *p = &bp->hw_stats.gem.tx_octets_31_0; | |
1095 | u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1; | |
1096 | ||
1097 | for (; p < end; p++, reg++) | |
1098 | *p += __raw_readl(reg); | |
1099 | } | |
1100 | ||
1101 | static struct net_device_stats *gem_get_stats(struct macb *bp) | |
1102 | { | |
1103 | struct gem_stats *hwstat = &bp->hw_stats.gem; | |
1104 | struct net_device_stats *nstat = &bp->stats; | |
1105 | ||
1106 | gem_update_stats(bp); | |
1107 | ||
1108 | nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + | |
1109 | hwstat->rx_alignment_errors + | |
1110 | hwstat->rx_resource_errors + | |
1111 | hwstat->rx_overruns + | |
1112 | hwstat->rx_oversize_frames + | |
1113 | hwstat->rx_jabbers + | |
1114 | hwstat->rx_undersized_frames + | |
1115 | hwstat->rx_length_field_frame_errors); | |
1116 | nstat->tx_errors = (hwstat->tx_late_collisions + | |
1117 | hwstat->tx_excessive_collisions + | |
1118 | hwstat->tx_underrun + | |
1119 | hwstat->tx_carrier_sense_errors); | |
1120 | nstat->multicast = hwstat->rx_multicast_frames; | |
1121 | nstat->collisions = (hwstat->tx_single_collision_frames + | |
1122 | hwstat->tx_multiple_collision_frames + | |
1123 | hwstat->tx_excessive_collisions); | |
1124 | nstat->rx_length_errors = (hwstat->rx_oversize_frames + | |
1125 | hwstat->rx_jabbers + | |
1126 | hwstat->rx_undersized_frames + | |
1127 | hwstat->rx_length_field_frame_errors); | |
1128 | nstat->rx_over_errors = hwstat->rx_resource_errors; | |
1129 | nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; | |
1130 | nstat->rx_frame_errors = hwstat->rx_alignment_errors; | |
1131 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1132 | nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; | |
1133 | nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; | |
1134 | nstat->tx_fifo_errors = hwstat->tx_underrun; | |
1135 | ||
1136 | return nstat; | |
1137 | } | |
1138 | ||
89e5785f HS |
1139 | static struct net_device_stats *macb_get_stats(struct net_device *dev) |
1140 | { | |
1141 | struct macb *bp = netdev_priv(dev); | |
1142 | struct net_device_stats *nstat = &bp->stats; | |
a494ed8e JI |
1143 | struct macb_stats *hwstat = &bp->hw_stats.macb; |
1144 | ||
1145 | if (macb_is_gem(bp)) | |
1146 | return gem_get_stats(bp); | |
89e5785f | 1147 | |
6c36a707 R |
1148 | /* read stats from hardware */ |
1149 | macb_update_stats(bp); | |
1150 | ||
89e5785f HS |
1151 | /* Convert HW stats into netdevice stats */ |
1152 | nstat->rx_errors = (hwstat->rx_fcs_errors + | |
1153 | hwstat->rx_align_errors + | |
1154 | hwstat->rx_resource_errors + | |
1155 | hwstat->rx_overruns + | |
1156 | hwstat->rx_oversize_pkts + | |
1157 | hwstat->rx_jabbers + | |
1158 | hwstat->rx_undersize_pkts + | |
1159 | hwstat->sqe_test_errors + | |
1160 | hwstat->rx_length_mismatch); | |
1161 | nstat->tx_errors = (hwstat->tx_late_cols + | |
1162 | hwstat->tx_excessive_cols + | |
1163 | hwstat->tx_underruns + | |
1164 | hwstat->tx_carrier_errors); | |
1165 | nstat->collisions = (hwstat->tx_single_cols + | |
1166 | hwstat->tx_multiple_cols + | |
1167 | hwstat->tx_excessive_cols); | |
1168 | nstat->rx_length_errors = (hwstat->rx_oversize_pkts + | |
1169 | hwstat->rx_jabbers + | |
1170 | hwstat->rx_undersize_pkts + | |
1171 | hwstat->rx_length_mismatch); | |
b19f7f71 AS |
1172 | nstat->rx_over_errors = hwstat->rx_resource_errors + |
1173 | hwstat->rx_overruns; | |
89e5785f HS |
1174 | nstat->rx_crc_errors = hwstat->rx_fcs_errors; |
1175 | nstat->rx_frame_errors = hwstat->rx_align_errors; | |
1176 | nstat->rx_fifo_errors = hwstat->rx_overruns; | |
1177 | /* XXX: What does "missed" mean? */ | |
1178 | nstat->tx_aborted_errors = hwstat->tx_excessive_cols; | |
1179 | nstat->tx_carrier_errors = hwstat->tx_carrier_errors; | |
1180 | nstat->tx_fifo_errors = hwstat->tx_underruns; | |
1181 | /* Don't know about heartbeat or window errors... */ | |
1182 | ||
1183 | return nstat; | |
1184 | } | |
1185 | ||
1186 | static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1187 | { | |
1188 | struct macb *bp = netdev_priv(dev); | |
6c36a707 R |
1189 | struct phy_device *phydev = bp->phy_dev; |
1190 | ||
1191 | if (!phydev) | |
1192 | return -ENODEV; | |
89e5785f | 1193 | |
6c36a707 | 1194 | return phy_ethtool_gset(phydev, cmd); |
89e5785f HS |
1195 | } |
1196 | ||
1197 | static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1198 | { | |
1199 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1200 | struct phy_device *phydev = bp->phy_dev; |
89e5785f | 1201 | |
6c36a707 R |
1202 | if (!phydev) |
1203 | return -ENODEV; | |
1204 | ||
1205 | return phy_ethtool_sset(phydev, cmd); | |
89e5785f HS |
1206 | } |
1207 | ||
6c36a707 R |
1208 | static void macb_get_drvinfo(struct net_device *dev, |
1209 | struct ethtool_drvinfo *info) | |
89e5785f HS |
1210 | { |
1211 | struct macb *bp = netdev_priv(dev); | |
1212 | ||
1213 | strcpy(info->driver, bp->pdev->dev.driver->name); | |
1214 | strcpy(info->version, "$Revision: 1.14 $"); | |
db1d7bf7 | 1215 | strcpy(info->bus_info, dev_name(&bp->pdev->dev)); |
89e5785f HS |
1216 | } |
1217 | ||
0005f541 | 1218 | const struct ethtool_ops macb_ethtool_ops = { |
89e5785f HS |
1219 | .get_settings = macb_get_settings, |
1220 | .set_settings = macb_set_settings, | |
1221 | .get_drvinfo = macb_get_drvinfo, | |
89e5785f | 1222 | .get_link = ethtool_op_get_link, |
17f393e8 | 1223 | .get_ts_info = ethtool_op_get_ts_info, |
89e5785f | 1224 | }; |
0005f541 | 1225 | EXPORT_SYMBOL_GPL(macb_ethtool_ops); |
89e5785f | 1226 | |
0005f541 | 1227 | int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
89e5785f HS |
1228 | { |
1229 | struct macb *bp = netdev_priv(dev); | |
6c36a707 | 1230 | struct phy_device *phydev = bp->phy_dev; |
89e5785f HS |
1231 | |
1232 | if (!netif_running(dev)) | |
1233 | return -EINVAL; | |
1234 | ||
6c36a707 R |
1235 | if (!phydev) |
1236 | return -ENODEV; | |
89e5785f | 1237 | |
28b04113 | 1238 | return phy_mii_ioctl(phydev, rq, cmd); |
89e5785f | 1239 | } |
0005f541 | 1240 | EXPORT_SYMBOL_GPL(macb_ioctl); |
89e5785f | 1241 | |
5f1fa992 AB |
1242 | static const struct net_device_ops macb_netdev_ops = { |
1243 | .ndo_open = macb_open, | |
1244 | .ndo_stop = macb_close, | |
1245 | .ndo_start_xmit = macb_start_xmit, | |
afc4b13d | 1246 | .ndo_set_rx_mode = macb_set_rx_mode, |
5f1fa992 AB |
1247 | .ndo_get_stats = macb_get_stats, |
1248 | .ndo_do_ioctl = macb_ioctl, | |
1249 | .ndo_validate_addr = eth_validate_addr, | |
1250 | .ndo_change_mtu = eth_change_mtu, | |
1251 | .ndo_set_mac_address = eth_mac_addr, | |
6e8cf5c0 TP |
1252 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1253 | .ndo_poll_controller = macb_poll_controller, | |
1254 | #endif | |
5f1fa992 AB |
1255 | }; |
1256 | ||
fb97a846 JCPV |
1257 | #if defined(CONFIG_OF) |
1258 | static const struct of_device_id macb_dt_ids[] = { | |
1259 | { .compatible = "cdns,at32ap7000-macb" }, | |
1260 | { .compatible = "cdns,at91sam9260-macb" }, | |
1261 | { .compatible = "cdns,macb" }, | |
1262 | { .compatible = "cdns,pc302-gem" }, | |
1263 | { .compatible = "cdns,gem" }, | |
1264 | { /* sentinel */ } | |
1265 | }; | |
1266 | ||
1267 | MODULE_DEVICE_TABLE(of, macb_dt_ids); | |
1268 | ||
1269 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1270 | { | |
1271 | struct device_node *np = pdev->dev.of_node; | |
1272 | ||
1273 | if (np) | |
1274 | return of_get_phy_mode(np); | |
1275 | ||
1276 | return -ENODEV; | |
1277 | } | |
1278 | ||
1279 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1280 | { | |
1281 | struct device_node *np = bp->pdev->dev.of_node; | |
1282 | if (np) { | |
1283 | const char *mac = of_get_mac_address(np); | |
1284 | if (mac) { | |
1285 | memcpy(bp->dev->dev_addr, mac, ETH_ALEN); | |
1286 | return 0; | |
1287 | } | |
1288 | } | |
1289 | ||
1290 | return -ENODEV; | |
1291 | } | |
1292 | #else | |
1293 | static int __devinit macb_get_phy_mode_dt(struct platform_device *pdev) | |
1294 | { | |
1295 | return -ENODEV; | |
1296 | } | |
1297 | static int __devinit macb_get_hwaddr_dt(struct macb *bp) | |
1298 | { | |
1299 | return -ENODEV; | |
1300 | } | |
1301 | #endif | |
1302 | ||
06c3fd6a | 1303 | static int __init macb_probe(struct platform_device *pdev) |
89e5785f | 1304 | { |
84e0cdb0 | 1305 | struct macb_platform_data *pdata; |
89e5785f HS |
1306 | struct resource *regs; |
1307 | struct net_device *dev; | |
1308 | struct macb *bp; | |
6c36a707 | 1309 | struct phy_device *phydev; |
89e5785f HS |
1310 | u32 config; |
1311 | int err = -ENXIO; | |
1312 | ||
1313 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1314 | if (!regs) { | |
1315 | dev_err(&pdev->dev, "no mmio resource defined\n"); | |
1316 | goto err_out; | |
1317 | } | |
1318 | ||
1319 | err = -ENOMEM; | |
1320 | dev = alloc_etherdev(sizeof(*bp)); | |
41de8d4c | 1321 | if (!dev) |
89e5785f | 1322 | goto err_out; |
89e5785f | 1323 | |
89e5785f HS |
1324 | SET_NETDEV_DEV(dev, &pdev->dev); |
1325 | ||
1326 | /* TODO: Actually, we have some interesting features... */ | |
1327 | dev->features |= 0; | |
1328 | ||
1329 | bp = netdev_priv(dev); | |
1330 | bp->pdev = pdev; | |
1331 | bp->dev = dev; | |
1332 | ||
1333 | spin_lock_init(&bp->lock); | |
1334 | ||
461845db | 1335 | bp->pclk = clk_get(&pdev->dev, "pclk"); |
0cc8674f AV |
1336 | if (IS_ERR(bp->pclk)) { |
1337 | dev_err(&pdev->dev, "failed to get macb_clk\n"); | |
1338 | goto err_out_free_dev; | |
1339 | } | |
1340 | clk_enable(bp->pclk); | |
461845db | 1341 | |
89e5785f HS |
1342 | bp->hclk = clk_get(&pdev->dev, "hclk"); |
1343 | if (IS_ERR(bp->hclk)) { | |
1344 | dev_err(&pdev->dev, "failed to get hclk\n"); | |
1345 | goto err_out_put_pclk; | |
1346 | } | |
89e5785f HS |
1347 | clk_enable(bp->hclk); |
1348 | ||
28f65c11 | 1349 | bp->regs = ioremap(regs->start, resource_size(regs)); |
89e5785f HS |
1350 | if (!bp->regs) { |
1351 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | |
1352 | err = -ENOMEM; | |
1353 | goto err_out_disable_clocks; | |
1354 | } | |
1355 | ||
1356 | dev->irq = platform_get_irq(pdev, 0); | |
ab392d2d | 1357 | err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev); |
89e5785f | 1358 | if (err) { |
c220f8cd JI |
1359 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", |
1360 | dev->irq, err); | |
89e5785f HS |
1361 | goto err_out_iounmap; |
1362 | } | |
1363 | ||
5f1fa992 | 1364 | dev->netdev_ops = &macb_netdev_ops; |
bea3348e | 1365 | netif_napi_add(dev, &bp->napi, macb_poll, 64); |
89e5785f HS |
1366 | dev->ethtool_ops = &macb_ethtool_ops; |
1367 | ||
1368 | dev->base_addr = regs->start; | |
1369 | ||
89e5785f | 1370 | /* Set MII management clock divider */ |
70c9f3d4 | 1371 | config = macb_mdc_clk_div(bp); |
757a03c6 | 1372 | config |= macb_dbw(bp); |
89e5785f HS |
1373 | macb_writel(bp, NCFGR, config); |
1374 | ||
fb97a846 JCPV |
1375 | err = macb_get_hwaddr_dt(bp); |
1376 | if (err < 0) | |
1377 | macb_get_hwaddr(bp); | |
1378 | ||
1379 | err = macb_get_phy_mode_dt(pdev); | |
1380 | if (err < 0) { | |
1381 | pdata = pdev->dev.platform_data; | |
1382 | if (pdata && pdata->is_rmii) | |
1383 | bp->phy_interface = PHY_INTERFACE_MODE_RMII; | |
1384 | else | |
1385 | bp->phy_interface = PHY_INTERFACE_MODE_MII; | |
1386 | } else { | |
1387 | bp->phy_interface = err; | |
1388 | } | |
6c36a707 | 1389 | |
fb97a846 | 1390 | if (bp->phy_interface == PHY_INTERFACE_MODE_RMII) |
0cc8674f | 1391 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b JI |
1392 | macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) | |
1393 | MACB_BIT(CLKEN))); | |
0cc8674f | 1394 | #else |
f75ba50b | 1395 | macb_or_gem_writel(bp, USRIO, 0); |
0cc8674f | 1396 | #endif |
89e5785f | 1397 | else |
0cc8674f | 1398 | #if defined(CONFIG_ARCH_AT91) |
f75ba50b | 1399 | macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN)); |
0cc8674f | 1400 | #else |
f75ba50b | 1401 | macb_or_gem_writel(bp, USRIO, MACB_BIT(MII)); |
0cc8674f | 1402 | #endif |
89e5785f HS |
1403 | |
1404 | bp->tx_pending = DEF_TX_RING_PENDING; | |
1405 | ||
1406 | err = register_netdev(dev); | |
1407 | if (err) { | |
1408 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | |
1409 | goto err_out_free_irq; | |
1410 | } | |
1411 | ||
6c36a707 R |
1412 | if (macb_mii_init(bp) != 0) { |
1413 | goto err_out_unregister_netdev; | |
1414 | } | |
89e5785f | 1415 | |
6c36a707 | 1416 | platform_set_drvdata(pdev, dev); |
89e5785f | 1417 | |
03fc4721 NF |
1418 | netif_carrier_off(dev); |
1419 | ||
f75ba50b JI |
1420 | netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n", |
1421 | macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr, | |
1422 | dev->irq, dev->dev_addr); | |
89e5785f | 1423 | |
6c36a707 | 1424 | phydev = bp->phy_dev; |
c220f8cd JI |
1425 | netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1426 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
6c36a707 | 1427 | |
89e5785f HS |
1428 | return 0; |
1429 | ||
6c36a707 R |
1430 | err_out_unregister_netdev: |
1431 | unregister_netdev(dev); | |
89e5785f HS |
1432 | err_out_free_irq: |
1433 | free_irq(dev->irq, dev); | |
1434 | err_out_iounmap: | |
1435 | iounmap(bp->regs); | |
1436 | err_out_disable_clocks: | |
1437 | clk_disable(bp->hclk); | |
89e5785f | 1438 | clk_put(bp->hclk); |
0cc8674f | 1439 | clk_disable(bp->pclk); |
89e5785f HS |
1440 | err_out_put_pclk: |
1441 | clk_put(bp->pclk); | |
1442 | err_out_free_dev: | |
1443 | free_netdev(dev); | |
1444 | err_out: | |
1445 | platform_set_drvdata(pdev, NULL); | |
1446 | return err; | |
1447 | } | |
1448 | ||
06c3fd6a | 1449 | static int __exit macb_remove(struct platform_device *pdev) |
89e5785f HS |
1450 | { |
1451 | struct net_device *dev; | |
1452 | struct macb *bp; | |
1453 | ||
1454 | dev = platform_get_drvdata(pdev); | |
1455 | ||
1456 | if (dev) { | |
1457 | bp = netdev_priv(dev); | |
84b7901f AN |
1458 | if (bp->phy_dev) |
1459 | phy_disconnect(bp->phy_dev); | |
298cf9be LB |
1460 | mdiobus_unregister(bp->mii_bus); |
1461 | kfree(bp->mii_bus->irq); | |
1462 | mdiobus_free(bp->mii_bus); | |
89e5785f HS |
1463 | unregister_netdev(dev); |
1464 | free_irq(dev->irq, dev); | |
1465 | iounmap(bp->regs); | |
1466 | clk_disable(bp->hclk); | |
89e5785f | 1467 | clk_put(bp->hclk); |
0cc8674f | 1468 | clk_disable(bp->pclk); |
89e5785f HS |
1469 | clk_put(bp->pclk); |
1470 | free_netdev(dev); | |
1471 | platform_set_drvdata(pdev, NULL); | |
1472 | } | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
c1f598fd HS |
1477 | #ifdef CONFIG_PM |
1478 | static int macb_suspend(struct platform_device *pdev, pm_message_t state) | |
1479 | { | |
1480 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1481 | struct macb *bp = netdev_priv(netdev); | |
1482 | ||
03fc4721 | 1483 | netif_carrier_off(netdev); |
c1f598fd HS |
1484 | netif_device_detach(netdev); |
1485 | ||
c1f598fd | 1486 | clk_disable(bp->hclk); |
c1f598fd HS |
1487 | clk_disable(bp->pclk); |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | static int macb_resume(struct platform_device *pdev) | |
1493 | { | |
1494 | struct net_device *netdev = platform_get_drvdata(pdev); | |
1495 | struct macb *bp = netdev_priv(netdev); | |
1496 | ||
1497 | clk_enable(bp->pclk); | |
c1f598fd | 1498 | clk_enable(bp->hclk); |
c1f598fd HS |
1499 | |
1500 | netif_device_attach(netdev); | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | #else | |
1505 | #define macb_suspend NULL | |
1506 | #define macb_resume NULL | |
1507 | #endif | |
1508 | ||
89e5785f | 1509 | static struct platform_driver macb_driver = { |
06c3fd6a | 1510 | .remove = __exit_p(macb_remove), |
c1f598fd HS |
1511 | .suspend = macb_suspend, |
1512 | .resume = macb_resume, | |
89e5785f HS |
1513 | .driver = { |
1514 | .name = "macb", | |
72abb461 | 1515 | .owner = THIS_MODULE, |
fb97a846 | 1516 | .of_match_table = of_match_ptr(macb_dt_ids), |
89e5785f HS |
1517 | }, |
1518 | }; | |
1519 | ||
1520 | static int __init macb_init(void) | |
1521 | { | |
06c3fd6a | 1522 | return platform_driver_probe(&macb_driver, macb_probe); |
89e5785f HS |
1523 | } |
1524 | ||
1525 | static void __exit macb_exit(void) | |
1526 | { | |
1527 | platform_driver_unregister(&macb_driver); | |
1528 | } | |
1529 | ||
1530 | module_init(macb_init); | |
1531 | module_exit(macb_exit); | |
1532 | ||
1533 | MODULE_LICENSE("GPL"); | |
f75ba50b | 1534 | MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver"); |
e05503ef | 1535 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
72abb461 | 1536 | MODULE_ALIAS("platform:macb"); |