projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* config/tc-mips.c (HAVE_IN_PLACE_ADDENDS): New macro.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0f10071e 3 2000, 2001, 2002, 2003, 2004
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132
RH		 35#include "opcode/i386.h"
36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
29b0f896
AM		 65static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
66static INLINE int fits_in_signed_byte PARAMS ((offsetT));
67static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
69static INLINE int fits_in_signed_word PARAMS ((offsetT));
70static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
71static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 72static int smallest_imm_type PARAMS ((offsetT));
73static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 74static int add_prefix PARAMS ((unsigned int));
3e73aa7c 75static void set_code_flag PARAMS ((int));
47926f60 76static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 77static void set_intel_syntax PARAMS ((int));
e413e4e9 78static void set_cpu_arch PARAMS ((int));
6482c264
NC		 79#ifdef TE_PE
80static void pe_directive_secrel PARAMS ((int));
81#endif
29b0f896
AM		 82static char *output_invalid PARAMS ((int c));
83static int i386_operand PARAMS ((char *operand_string));
84static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
85static const reg_entry *parse_register PARAMS ((char *reg_string,
86 char **end_op));
87static char *parse_insn PARAMS ((char *, char *));
88static char *parse_operands PARAMS ((char *, const char *));
89static void swap_operands PARAMS ((void));
90static void optimize_imm PARAMS ((void));
91static void optimize_disp PARAMS ((void));
92static int match_template PARAMS ((void));
93static int check_string PARAMS ((void));
94static int process_suffix PARAMS ((void));
95static int check_byte_reg PARAMS ((void));
96static int check_long_reg PARAMS ((void));
97static int check_qword_reg PARAMS ((void));
98static int check_word_reg PARAMS ((void));
99static int finalize_imm PARAMS ((void));
100static int process_operands PARAMS ((void));
101static const seg_entry *build_modrm_byte PARAMS ((void));
102static void output_insn PARAMS ((void));
103static void output_branch PARAMS ((void));
104static void output_jump PARAMS ((void));
105static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 106static void output_imm PARAMS ((fragS *insn_start_frag,
107 offsetT insn_start_off));
108static void output_disp PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
29b0f896
AM		 110#ifndef I386COFF
111static void s_bss PARAMS ((int));
252b5132
RH		 112#endif
113
a847613f 114static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 115
252b5132 116/* 'md_assemble ()' gathers together information and puts it into a
47926f60 117 i386_insn. */
252b5132 118
520dc8e8
AM		 119union i386_op
120 {
121 expressionS *disps;
122 expressionS *imms;
123 const reg_entry *regs;
124 };
125
252b5132
RH		 126struct _i386_insn
127 {
47926f60 128 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 129 template tm;
130
131 /* SUFFIX holds the instruction mnemonic suffix if given.
132 (e.g. 'l' for 'movl') */
133 char suffix;
134
47926f60 135 /* OPERANDS gives the number of given operands. */
252b5132
RH		 136 unsigned int operands;
137
138 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
139 of given register, displacement, memory operands and immediate
47926f60 140 operands. */
252b5132
RH		 141 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
142
143 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 144 use OP[i] for the corresponding operand. */
252b5132
RH		 145 unsigned int types[MAX_OPERANDS];
146
520dc8e8
AM		 147 /* Displacement expression, immediate expression, or register for each
148 operand. */
149 union i386_op op[MAX_OPERANDS];
252b5132 150
3e73aa7c
JH		 151 /* Flags for operands. */
152 unsigned int flags[MAX_OPERANDS];
153#define Operand_PCrel 1
154
252b5132 155 /* Relocation type for operand */
f86103b7 156 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 157
252b5132
RH		 158 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
159 the base index byte below. */
160 const reg_entry *base_reg;
161 const reg_entry *index_reg;
162 unsigned int log2_scale_factor;
163
164 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 165 explicit segment overrides are given. */
ce8a8b2f 166 const seg_entry *seg[2];
252b5132
RH		 167
168 /* PREFIX holds all the given prefix opcodes (usually null).
169 PREFIXES is the number of prefix opcodes. */
170 unsigned int prefixes;
171 unsigned char prefix[MAX_PREFIXES];
172
173 /* RM and SIB are the modrm byte and the sib byte where the
174 addressing modes of this insn are encoded. */
175
176 modrm_byte rm;
3e73aa7c 177 rex_byte rex;
252b5132
RH		 178 sib_byte sib;
179 };
180
181typedef struct _i386_insn i386_insn;
182
183/* List of chars besides those in app.c:symbol_chars that can start an
184 operand. Used to prevent the scrubber eating vital white-space. */
32137342 185const char extra_symbol_chars[] = "*%-(["
252b5132 186#ifdef LEX_AT
32137342
NC		 187 "@"
188#endif
189#ifdef LEX_QM
190 "?"
252b5132 191#endif
32137342 192 ;
252b5132 193
29b0f896
AM		 194#if (defined (TE_I386AIX) \
195 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
196 && !defined (TE_LINUX) \
32137342 197 && !defined (TE_NETWARE) \
29b0f896
AM		 198 && !defined (TE_FreeBSD) \
199 && !defined (TE_NetBSD)))
252b5132 200/* This array holds the chars that always start a comment. If the
ce8a8b2f 201 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 202const char comment_chars[] = "#/";
203#define PREFIX_SEPARATOR '\\'
252b5132
RH		 204
205/* This array holds the chars that only start a comment at the beginning of
206 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 207 .line and .file directives will appear in the pre-processed output.
208 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 209 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 210 #NO_APP at the beginning of its output.
211 Also note that comments started like this one will always work if
252b5132 212 '/' isn't otherwise defined. */
0d9f6d04 213const char line_comment_chars[] = "#";
29b0f896 214
252b5132 215#else
29b0f896
AM		 216/* Putting '/' here makes it impossible to use the divide operator.
217 However, we need it for compatibility with SVR4 systems. */
218const char comment_chars[] = "#";
219#define PREFIX_SEPARATOR '/'
220
0d9f6d04 221const char line_comment_chars[] = "/#";
252b5132
RH		 222#endif
223
63a0b638 224const char line_separator_chars[] = ";";
252b5132 225
ce8a8b2f
AM		 226/* Chars that can be used to separate mant from exp in floating point
227 nums. */
252b5132
RH		 228const char EXP_CHARS[] = "eE";
229
ce8a8b2f
AM		 230/* Chars that mean this number is a floating point constant
231 As in 0f12.456
232 or 0d1.2345e12. */
252b5132
RH		 233const char FLT_CHARS[] = "fFdDxX";
234
ce8a8b2f 235/* Tables for lexical analysis. */
252b5132
RH		 236static char mnemonic_chars[256];
237static char register_chars[256];
238static char operand_chars[256];
239static char identifier_chars[256];
240static char digit_chars[256];
241
ce8a8b2f 242/* Lexical macros. */
252b5132
RH		 243#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
244#define is_operand_char(x) (operand_chars[(unsigned char) x])
245#define is_register_char(x) (register_chars[(unsigned char) x])
246#define is_space_char(x) ((x) == ' ')
247#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
248#define is_digit_char(x) (digit_chars[(unsigned char) x])
249
0234cb7c 250/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 251static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
252
253/* md_assemble() always leaves the strings it's passed unaltered. To
254 effect this we maintain a stack of saved characters that we've smashed
255 with '\0's (indicating end of strings for various sub-fields of the
47926f60 256 assembler instruction). */
252b5132 257static char save_stack[32];
ce8a8b2f 258static char *save_stack_p;
252b5132
RH		 259#define END_STRING_AND_SAVE(s) \
260 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
261#define RESTORE_END_STRING(s) \
262 do { *(s) = *--save_stack_p; } while (0)
263
47926f60 264/* The instruction we're assembling. */
252b5132
RH		 265static i386_insn i;
266
267/* Possible templates for current insn. */
268static const templates *current_templates;
269
47926f60 270/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 271static expressionS disp_expressions[2], im_expressions[2];
272
47926f60
KH		 273/* Current operand we are working on. */
274static int this_operand;
252b5132 275
3e73aa7c
JH		 276/* We support four different modes. FLAG_CODE variable is used to distinguish
277 these. */
278
279enum flag_code {
280 CODE_32BIT,
281 CODE_16BIT,
282 CODE_64BIT };
f3c180ae 283#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 284
285static enum flag_code flag_code;
286static int use_rela_relocations = 0;
287
288/* The names used to print error messages. */
b77a7acd 289static const char *flag_code_names[] =
3e73aa7c
JH		 290 {
291 "32",
292 "16",
293 "64"
294 };
252b5132 295
47926f60
KH		 296/* 1 for intel syntax,
297 0 if att syntax. */
298static int intel_syntax = 0;
252b5132 299
47926f60
KH		 300/* 1 if register prefix % not required. */
301static int allow_naked_reg = 0;
252b5132 302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
a38cf1db 316
47926f60 317/* CPU feature flags. */
29b0f896 318static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 319
fddf5b5b
AM		 320/* If set, conditional jumps are not automatically promoted to handle
321 larger than a byte offset. */
322static unsigned int no_cond_jump_promotion = 0;
323
29b0f896
AM		 324/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
325symbolS *GOT_symbol;
326
a4447b93
RH		 327/* The dwarf2 return column, adjusted for 32 or 64 bit. */
328unsigned int x86_dwarf2_return_column;
329
330/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
331int x86_cie_data_alignment;
332
252b5132 333/* Interface to relax_segment.
fddf5b5b
AM		 334 There are 3 major relax states for 386 jump insns because the
335 different types of jumps add different sizes to frags when we're
336 figuring out what sort of jump to choose to reach a given label. */
252b5132 337
47926f60 338/* Types. */
93c2a809
AM		 339#define UNCOND_JUMP 0
340#define COND_JUMP 1
341#define COND_JUMP86 2
fddf5b5b 342
47926f60 343/* Sizes. */
252b5132
RH		 344#define CODE16 1
345#define SMALL 0
29b0f896 346#define SMALL16 (SMALL | CODE16)
252b5132 347#define BIG 2
29b0f896 348#define BIG16 (BIG | CODE16)
252b5132
RH		 349
350#ifndef INLINE
351#ifdef __GNUC__
352#define INLINE __inline__
353#else
354#define INLINE
355#endif
356#endif
357
fddf5b5b
AM		 358#define ENCODE_RELAX_STATE(type, size) \
359 ((relax_substateT) (((type) << 2) | (size)))
360#define TYPE_FROM_RELAX_STATE(s) \
361 ((s) >> 2)
362#define DISP_SIZE_FROM_RELAX_STATE(s) \
363 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 364
365/* This table is used by relax_frag to promote short jumps to long
366 ones where necessary. SMALL (short) jumps may be promoted to BIG
367 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
368 don't allow a short jump in a 32 bit code segment to be promoted to
369 a 16 bit offset jump because it's slower (requires data size
370 prefix), and doesn't work, unless the destination is in the bottom
371 64k of the code segment (The top 16 bits of eip are zeroed). */
372
373const relax_typeS md_relax_table[] =
374{
24eab124
AM		 375 /* The fields are:
376 1) most positive reach of this state,
377 2) most negative reach of this state,
93c2a809 378 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 379 4) which index into the table to try if we can't fit into this one. */
252b5132 380
fddf5b5b 381 /* UNCOND_JUMP states. */
93c2a809
AM		 382 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
383 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
384 /* dword jmp adds 4 bytes to frag:
385 0 extra opcode bytes, 4 displacement bytes. */
252b5132 386 {0, 0, 4, 0},
93c2a809
AM		 387 /* word jmp adds 2 byte2 to frag:
388 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 389 {0, 0, 2, 0},
390
93c2a809
AM		 391 /* COND_JUMP states. */
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
394 /* dword conditionals adds 5 bytes to frag:
395 1 extra opcode byte, 4 displacement bytes. */
396 {0, 0, 5, 0},
fddf5b5b 397 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 398 1 extra opcode byte, 2 displacement bytes. */
399 {0, 0, 3, 0},
400
401 /* COND_JUMP86 states. */
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
404 /* dword conditionals adds 5 bytes to frag:
405 1 extra opcode byte, 4 displacement bytes. */
406 {0, 0, 5, 0},
407 /* word conditionals add 4 bytes to frag:
408 1 displacement byte and a 3 byte long branch insn. */
409 {0, 0, 4, 0}
252b5132
RH		 410};
411
e413e4e9
AM		 412static const arch_entry cpu_arch[] = {
413 {"i8086", Cpu086 },
414 {"i186", Cpu086|Cpu186 },
415 {"i286", Cpu086|Cpu186|Cpu286 },
416 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
417 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
418 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
419 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
420 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
421 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 422 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 423 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
424 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 425 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 426 {NULL, 0 }
427};
428
29b0f896
AM		 429const pseudo_typeS md_pseudo_table[] =
430{
431#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
432 {"align", s_align_bytes, 0},
433#else
434 {"align", s_align_ptwo, 0},
435#endif
436 {"arch", set_cpu_arch, 0},
437#ifndef I386COFF
438 {"bss", s_bss, 0},
439#endif
440 {"ffloat", float_cons, 'f'},
441 {"dfloat", float_cons, 'd'},
442 {"tfloat", float_cons, 'x'},
443 {"value", cons, 2},
444 {"noopt", s_ignore, 0},
445 {"optim", s_ignore, 0},
446 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
447 {"code16", set_code_flag, CODE_16BIT},
448 {"code32", set_code_flag, CODE_32BIT},
449 {"code64", set_code_flag, CODE_64BIT},
450 {"intel_syntax", set_intel_syntax, 1},
451 {"att_syntax", set_intel_syntax, 0},
c6682705 452 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 453 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 454#ifdef TE_PE
455 {"secrel32", pe_directive_secrel, 0},
456#endif
29b0f896
AM		 457 {0, 0, 0}
458};
459
460/* For interface with expression (). */
461extern char *input_line_pointer;
462
463/* Hash table for instruction mnemonic lookup. */
464static struct hash_control *op_hash;
465
466/* Hash table for register lookup. */
467static struct hash_control *reg_hash;
468\f
252b5132
RH		 469void
470i386_align_code (fragP, count)
471 fragS *fragP;
472 int count;
473{
ce8a8b2f
AM		 474 /* Various efficient no-op patterns for aligning code labels.
475 Note: Don't try to assemble the instructions in the comments.
476 0L and 0w are not legal. */
252b5132
RH		 477 static const char f32_1[] =
478 {0x90}; /* nop */
479 static const char f32_2[] =
480 {0x89,0xf6}; /* movl %esi,%esi */
481 static const char f32_3[] =
482 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
483 static const char f32_4[] =
484 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
485 static const char f32_5[] =
486 {0x90, /* nop */
487 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
488 static const char f32_6[] =
489 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
490 static const char f32_7[] =
491 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
492 static const char f32_8[] =
493 {0x90, /* nop */
494 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
495 static const char f32_9[] =
496 {0x89,0xf6, /* movl %esi,%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_10[] =
499 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
500 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
501 static const char f32_11[] =
502 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
503 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
504 static const char f32_12[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
506 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
507 static const char f32_13[] =
508 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_14[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_15[] =
514 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
515 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 516 static const char f16_3[] =
517 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 518 static const char f16_4[] =
519 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
520 static const char f16_5[] =
521 {0x90, /* nop */
522 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
523 static const char f16_6[] =
524 {0x89,0xf6, /* mov %si,%si */
525 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
526 static const char f16_7[] =
527 {0x8d,0x74,0x00, /* lea 0(%si),%si */
528 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
529 static const char f16_8[] =
530 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
531 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
532 static const char *const f32_patt[] = {
533 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
534 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
535 };
536 static const char *const f16_patt[] = {
c3332e24 537 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 538 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
539 };
540
33fef721
JH		 541 if (count <= 0 || count > 15)
542 return;
3e73aa7c 543
33fef721
JH		 544 /* The recommended way to pad 64bit code is to use NOPs preceded by
545 maximally four 0x66 prefixes. Balance the size of nops. */
546 if (flag_code == CODE_64BIT)
252b5132 547 {
33fef721
JH		 548 int i;
549 int nnops = (count + 3) / 4;
550 int len = count / nnops;
551 int remains = count - nnops * len;
552 int pos = 0;
553
554 for (i = 0; i < remains; i++)
252b5132 555 {
33fef721
JH		 556 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
557 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
558 pos += len + 1;
559 }
560 for (; i < nnops; i++)
561 {
562 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
563 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
564 pos += len;
252b5132 565 }
252b5132 566 }
33fef721
JH		 567 else
568 if (flag_code == CODE_16BIT)
569 {
570 memcpy (fragP->fr_literal + fragP->fr_fix,
571 f16_patt[count - 1], count);
572 if (count > 8)
573 /* Adjust jump offset. */
574 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
575 }
576 else
577 memcpy (fragP->fr_literal + fragP->fr_fix,
578 f32_patt[count - 1], count);
579 fragP->fr_var = count;
252b5132
RH		 580}
581
252b5132
RH		 582static INLINE unsigned int
583mode_from_disp_size (t)
584 unsigned int t;
585{
3e73aa7c 586 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 587}
588
589static INLINE int
590fits_in_signed_byte (num)
847f7ad4 591 offsetT num;
252b5132
RH		 592{
593 return (num >= -128) && (num <= 127);
47926f60 594}
252b5132
RH		 595
596static INLINE int
597fits_in_unsigned_byte (num)
847f7ad4 598 offsetT num;
252b5132
RH		 599{
600 return (num & 0xff) == num;
47926f60 601}
252b5132
RH		 602
603static INLINE int
604fits_in_unsigned_word (num)
847f7ad4 605 offsetT num;
252b5132
RH		 606{
607 return (num & 0xffff) == num;
47926f60 608}
252b5132
RH		 609
610static INLINE int
611fits_in_signed_word (num)
847f7ad4 612 offsetT num;
252b5132
RH		 613{
614 return (-32768 <= num) && (num <= 32767);
47926f60 615}
3e73aa7c
JH		 616static INLINE int
617fits_in_signed_long (num)
618 offsetT num ATTRIBUTE_UNUSED;
619{
620#ifndef BFD64
621 return 1;
622#else
623 return (!(((offsetT) -1 << 31) & num)
624 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
625#endif
626} /* fits_in_signed_long() */
627static INLINE int
628fits_in_unsigned_long (num)
629 offsetT num ATTRIBUTE_UNUSED;
630{
631#ifndef BFD64
632 return 1;
633#else
634 return (num & (((offsetT) 2 << 31) - 1)) == num;
635#endif
636} /* fits_in_unsigned_long() */
252b5132
RH		 637
638static int
639smallest_imm_type (num)
847f7ad4 640 offsetT num;
252b5132 641{
a847613f 642 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 643 {
644 /* This code is disabled on the 486 because all the Imm1 forms
645 in the opcode table are slower on the i486. They're the
646 versions with the implicitly specified single-position
647 displacement, which has another syntax if you really want to
648 use that form. */
649 if (num == 1)
3e73aa7c 650 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 651 }
252b5132 652 return (fits_in_signed_byte (num)
3e73aa7c 653 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 654 : fits_in_unsigned_byte (num)
3e73aa7c 655 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 656 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 657 ? (Imm16 | Imm32 | Imm32S | Imm64)
658 : fits_in_signed_long (num)
659 ? (Imm32 | Imm32S | Imm64)
660 : fits_in_unsigned_long (num)
661 ? (Imm32 | Imm64)
662 : Imm64);
47926f60 663}
252b5132 664
847f7ad4
AM		 665static offsetT
666offset_in_range (val, size)
667 offsetT val;
668 int size;
669{
508866be 670 addressT mask;
ba2adb93 671
847f7ad4
AM		 672 switch (size)
673 {
508866be
L		 674 case 1: mask = ((addressT) 1 << 8) - 1; break;
675 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 676 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 677#ifdef BFD64
678 case 8: mask = ((addressT) 2 << 63) - 1; break;
679#endif
47926f60 680 default: abort ();
847f7ad4
AM		 681 }
682
ba2adb93 683 /* If BFD64, sign extend val. */
3e73aa7c
JH		 684 if (!use_rela_relocations)
685 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
686 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 687
47926f60 688 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 689 {
690 char buf1[40], buf2[40];
691
692 sprint_value (buf1, val);
693 sprint_value (buf2, val & mask);
694 as_warn (_("%s shortened to %s"), buf1, buf2);
695 }
696 return val & mask;
697}
698
252b5132
RH		 699/* Returns 0 if attempting to add a prefix where one from the same
700 class already exists, 1 if non rep/repne added, 2 if rep/repne
701 added. */
702static int
703add_prefix (prefix)
704 unsigned int prefix;
705{
706 int ret = 1;
707 int q;
708
29b0f896
AM		 709 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
710 && flag_code == CODE_64BIT)
3e73aa7c
JH		 711 q = REX_PREFIX;
712 else
713 switch (prefix)
714 {
715 default:
716 abort ();
717
718 case CS_PREFIX_OPCODE:
719 case DS_PREFIX_OPCODE:
720 case ES_PREFIX_OPCODE:
721 case FS_PREFIX_OPCODE:
722 case GS_PREFIX_OPCODE:
723 case SS_PREFIX_OPCODE:
724 q = SEG_PREFIX;
725 break;
252b5132 726
3e73aa7c
JH		 727 case REPNE_PREFIX_OPCODE:
728 case REPE_PREFIX_OPCODE:
729 ret = 2;
730 /* fall thru */
731 case LOCK_PREFIX_OPCODE:
732 q = LOCKREP_PREFIX;
733 break;
252b5132 734
3e73aa7c
JH		 735 case FWAIT_OPCODE:
736 q = WAIT_PREFIX;
737 break;
252b5132 738
3e73aa7c
JH		 739 case ADDR_PREFIX_OPCODE:
740 q = ADDR_PREFIX;
741 break;
252b5132 742
3e73aa7c
JH		 743 case DATA_PREFIX_OPCODE:
744 q = DATA_PREFIX;
745 break;
746 }
252b5132 747
29b0f896 748 if (i.prefix[q] != 0)
252b5132
RH		 749 {
750 as_bad (_("same type of prefix used twice"));
751 return 0;
752 }
753
754 i.prefixes += 1;
755 i.prefix[q] = prefix;
756 return ret;
757}
758
759static void
3e73aa7c 760set_code_flag (value)
e5cb08ac 761 int value;
eecb386c 762{
3e73aa7c
JH		 763 flag_code = value;
764 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
765 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
766 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
767 {
768 as_bad (_("64bit mode not supported on this CPU."));
769 }
770 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
771 {
772 as_bad (_("32bit mode not supported on this CPU."));
773 }
eecb386c
AM		 774 stackop_size = '\0';
775}
776
777static void
3e73aa7c
JH		 778set_16bit_gcc_code_flag (new_code_flag)
779 int new_code_flag;
252b5132 780{
3e73aa7c
JH		 781 flag_code = new_code_flag;
782 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
783 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
784 stackop_size = 'l';
252b5132
RH		 785}
786
787static void
788set_intel_syntax (syntax_flag)
eecb386c 789 int syntax_flag;
252b5132
RH		 790{
791 /* Find out if register prefixing is specified. */
792 int ask_naked_reg = 0;
793
794 SKIP_WHITESPACE ();
29b0f896 795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 796 {
797 char *string = input_line_pointer;
798 int e = get_symbol_end ();
799
47926f60 800 if (strcmp (string, "prefix") == 0)
252b5132 801 ask_naked_reg = 1;
47926f60 802 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 803 ask_naked_reg = -1;
804 else
d0b47220 805 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 806 *input_line_pointer = e;
807 }
808 demand_empty_rest_of_line ();
c3332e24 809
252b5132
RH		 810 intel_syntax = syntax_flag;
811
812 if (ask_naked_reg == 0)
f86103b7
AM		 813 allow_naked_reg = (intel_syntax
814 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 815 else
816 allow_naked_reg = (ask_naked_reg < 0);
817}
818
e413e4e9
AM		 819static void
820set_cpu_arch (dummy)
47926f60 821 int dummy ATTRIBUTE_UNUSED;
e413e4e9 822{
47926f60 823 SKIP_WHITESPACE ();
e413e4e9 824
29b0f896 825 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 826 {
827 char *string = input_line_pointer;
828 int e = get_symbol_end ();
829 int i;
830
831 for (i = 0; cpu_arch[i].name; i++)
832 {
833 if (strcmp (string, cpu_arch[i].name) == 0)
834 {
835 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 836 cpu_arch_flags = (cpu_arch[i].flags
837 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 838 break;
839 }
840 }
841 if (!cpu_arch[i].name)
842 as_bad (_("no such architecture: `%s'"), string);
843
844 *input_line_pointer = e;
845 }
846 else
847 as_bad (_("missing cpu architecture"));
848
fddf5b5b
AM		 849 no_cond_jump_promotion = 0;
850 if (*input_line_pointer == ','
29b0f896 851 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 852 {
853 char *string = ++input_line_pointer;
854 int e = get_symbol_end ();
855
856 if (strcmp (string, "nojumps") == 0)
857 no_cond_jump_promotion = 1;
858 else if (strcmp (string, "jumps") == 0)
859 ;
860 else
861 as_bad (_("no such architecture modifier: `%s'"), string);
862
863 *input_line_pointer = e;
864 }
865
e413e4e9
AM		 866 demand_empty_rest_of_line ();
867}
868
b9d79e03
JH		 869unsigned long
870i386_mach ()
871{
872 if (!strcmp (default_arch, "x86_64"))
873 return bfd_mach_x86_64;
874 else if (!strcmp (default_arch, "i386"))
875 return bfd_mach_i386_i386;
876 else
877 as_fatal (_("Unknown architecture"));
878}
b9d79e03 879\f
252b5132
RH		 880void
881md_begin ()
882{
883 const char *hash_err;
884
47926f60 885 /* Initialize op_hash hash table. */
252b5132
RH		 886 op_hash = hash_new ();
887
888 {
29b0f896
AM		 889 const template *optab;
890 templates *core_optab;
252b5132 891
47926f60
KH		 892 /* Setup for loop. */
893 optab = i386_optab;
252b5132
RH		 894 core_optab = (templates *) xmalloc (sizeof (templates));
895 core_optab->start = optab;
896
897 while (1)
898 {
899 ++optab;
900 if (optab->name == NULL
901 || strcmp (optab->name, (optab - 1)->name) != 0)
902 {
903 /* different name --> ship out current template list;
47926f60 904 add to hash table; & begin anew. */
252b5132
RH		 905 core_optab->end = optab;
906 hash_err = hash_insert (op_hash,
907 (optab - 1)->name,
908 (PTR) core_optab);
909 if (hash_err)
910 {
252b5132
RH		 911 as_fatal (_("Internal Error: Can't hash %s: %s"),
912 (optab - 1)->name,
913 hash_err);
914 }
915 if (optab->name == NULL)
916 break;
917 core_optab = (templates *) xmalloc (sizeof (templates));
918 core_optab->start = optab;
919 }
920 }
921 }
922
47926f60 923 /* Initialize reg_hash hash table. */
252b5132
RH		 924 reg_hash = hash_new ();
925 {
29b0f896 926 const reg_entry *regtab;
252b5132
RH		 927
928 for (regtab = i386_regtab;
929 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
930 regtab++)
931 {
932 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
933 if (hash_err)
3e73aa7c
JH		 934 as_fatal (_("Internal Error: Can't hash %s: %s"),
935 regtab->reg_name,
936 hash_err);
252b5132
RH		 937 }
938 }
939
47926f60 940 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 941 {
29b0f896
AM		 942 int c;
943 char *p;
252b5132
RH		 944
945 for (c = 0; c < 256; c++)
946 {
3882b010 947 if (ISDIGIT (c))
252b5132
RH		 948 {
949 digit_chars[c] = c;
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISLOWER (c))
252b5132
RH		 955 {
956 mnemonic_chars[c] = c;
957 register_chars[c] = c;
958 operand_chars[c] = c;
959 }
3882b010 960 else if (ISUPPER (c))
252b5132 961 {
3882b010 962 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 963 register_chars[c] = mnemonic_chars[c];
964 operand_chars[c] = c;
965 }
966
3882b010 967 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 968 identifier_chars[c] = c;
969 else if (c >= 128)
970 {
971 identifier_chars[c] = c;
972 operand_chars[c] = c;
973 }
974 }
975
976#ifdef LEX_AT
977 identifier_chars['@'] = '@';
32137342
NC		 978#endif
979#ifdef LEX_QM
980 identifier_chars['?'] = '?';
981 operand_chars['?'] = '?';
252b5132 982#endif
252b5132
RH		 983 digit_chars['-'] = '-';
984 identifier_chars['_'] = '_';
985 identifier_chars['.'] = '.';
986
987 for (p = operand_special_chars; *p != '\0'; p++)
988 operand_chars[(unsigned char) *p] = *p;
989 }
990
991#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
992 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
993 {
994 record_alignment (text_section, 2);
995 record_alignment (data_section, 2);
996 record_alignment (bss_section, 2);
997 }
998#endif
a4447b93
RH		 999
1000 if (flag_code == CODE_64BIT)
1001 {
1002 x86_dwarf2_return_column = 16;
1003 x86_cie_data_alignment = -8;
1004 }
1005 else
1006 {
1007 x86_dwarf2_return_column = 8;
1008 x86_cie_data_alignment = -4;
1009 }
252b5132
RH		 1010}
1011
1012void
1013i386_print_statistics (file)
1014 FILE *file;
1015{
1016 hash_print_statistics (file, "i386 opcode", op_hash);
1017 hash_print_statistics (file, "i386 register", reg_hash);
1018}
1019\f
252b5132
RH		 1020#ifdef DEBUG386
1021
ce8a8b2f 1022/* Debugging routines for md_assemble. */
252b5132
RH		 1023static void pi PARAMS ((char *, i386_insn *));
1024static void pte PARAMS ((template *));
1025static void pt PARAMS ((unsigned int));
1026static void pe PARAMS ((expressionS *));
1027static void ps PARAMS ((symbolS *));
1028
1029static void
1030pi (line, x)
1031 char *line;
1032 i386_insn *x;
1033{
09f131f2 1034 unsigned int i;
252b5132
RH		 1035
1036 fprintf (stdout, "%s: template ", line);
1037 pte (&x->tm);
09f131f2
JH		 1038 fprintf (stdout, " address: base %s index %s scale %x\n",
1039 x->base_reg ? x->base_reg->reg_name : "none",
1040 x->index_reg ? x->index_reg->reg_name : "none",
1041 x->log2_scale_factor);
1042 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1043 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1044 fprintf (stdout, " sib: base %x index %x scale %x\n",
1045 x->sib.base, x->sib.index, x->sib.scale);
1046 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1047 (x->rex & REX_MODE64) != 0,
1048 (x->rex & REX_EXTX) != 0,
1049 (x->rex & REX_EXTY) != 0,
1050 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1051 for (i = 0; i < x->operands; i++)
1052 {
1053 fprintf (stdout, " #%d: ", i + 1);
1054 pt (x->types[i]);
1055 fprintf (stdout, "\n");
1056 if (x->types[i]
3f4438ab 1057 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1058 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1059 if (x->types[i] & Imm)
520dc8e8 1060 pe (x->op[i].imms);
252b5132 1061 if (x->types[i] & Disp)
520dc8e8 1062 pe (x->op[i].disps);
252b5132
RH		 1063 }
1064}
1065
1066static void
1067pte (t)
1068 template *t;
1069{
09f131f2 1070 unsigned int i;
252b5132 1071 fprintf (stdout, " %d operands ", t->operands);
47926f60 1072 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1073 if (t->extension_opcode != None)
1074 fprintf (stdout, "ext %x ", t->extension_opcode);
1075 if (t->opcode_modifier & D)
1076 fprintf (stdout, "D");
1077 if (t->opcode_modifier & W)
1078 fprintf (stdout, "W");
1079 fprintf (stdout, "\n");
1080 for (i = 0; i < t->operands; i++)
1081 {
1082 fprintf (stdout, " #%d type ", i + 1);
1083 pt (t->operand_types[i]);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089pe (e)
1090 expressionS *e;
1091{
24eab124 1092 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1093 fprintf (stdout, " add_number %ld (%lx)\n",
1094 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1095 if (e->X_add_symbol)
1096 {
1097 fprintf (stdout, " add_symbol ");
1098 ps (e->X_add_symbol);
1099 fprintf (stdout, "\n");
1100 }
1101 if (e->X_op_symbol)
1102 {
1103 fprintf (stdout, " op_symbol ");
1104 ps (e->X_op_symbol);
1105 fprintf (stdout, "\n");
1106 }
1107}
1108
1109static void
1110ps (s)
1111 symbolS *s;
1112{
1113 fprintf (stdout, "%s type %s%s",
1114 S_GET_NAME (s),
1115 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1116 segment_name (S_GET_SEGMENT (s)));
1117}
1118
1119struct type_name
1120 {
1121 unsigned int mask;
1122 char *tname;
1123 }
1124
29b0f896 1125static const type_names[] =
252b5132
RH		 1126{
1127 { Reg8, "r8" },
1128 { Reg16, "r16" },
1129 { Reg32, "r32" },
09f131f2 1130 { Reg64, "r64" },
252b5132
RH		 1131 { Imm8, "i8" },
1132 { Imm8S, "i8s" },
1133 { Imm16, "i16" },
1134 { Imm32, "i32" },
09f131f2
JH		 1135 { Imm32S, "i32s" },
1136 { Imm64, "i64" },
252b5132
RH		 1137 { Imm1, "i1" },
1138 { BaseIndex, "BaseIndex" },
1139 { Disp8, "d8" },
1140 { Disp16, "d16" },
1141 { Disp32, "d32" },
09f131f2
JH		 1142 { Disp32S, "d32s" },
1143 { Disp64, "d64" },
252b5132
RH		 1144 { InOutPortReg, "InOutPortReg" },
1145 { ShiftCount, "ShiftCount" },
1146 { Control, "control reg" },
1147 { Test, "test reg" },
1148 { Debug, "debug reg" },
1149 { FloatReg, "FReg" },
1150 { FloatAcc, "FAcc" },
1151 { SReg2, "SReg2" },
1152 { SReg3, "SReg3" },
1153 { Acc, "Acc" },
1154 { JumpAbsolute, "Jump Absolute" },
1155 { RegMMX, "rMMX" },
3f4438ab 1156 { RegXMM, "rXMM" },
252b5132
RH		 1157 { EsSeg, "es" },
1158 { 0, "" }
1159};
1160
1161static void
1162pt (t)
1163 unsigned int t;
1164{
29b0f896 1165 const struct type_name *ty;
252b5132 1166
09f131f2
JH		 1167 for (ty = type_names; ty->mask; ty++)
1168 if (t & ty->mask)
1169 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1170 fflush (stdout);
1171}
1172
1173#endif /* DEBUG386 */
1174\f
29b0f896
AM		 1175static bfd_reloc_code_real_type reloc
1176 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1177
1178static bfd_reloc_code_real_type
3e73aa7c 1179reloc (size, pcrel, sign, other)
252b5132
RH		 1180 int size;
1181 int pcrel;
3e73aa7c 1182 int sign;
252b5132
RH		 1183 bfd_reloc_code_real_type other;
1184{
47926f60
KH		 1185 if (other != NO_RELOC)
1186 return other;
252b5132
RH		 1187
1188 if (pcrel)
1189 {
3e73aa7c 1190 if (!sign)
e5cb08ac 1191 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1192 switch (size)
1193 {
1194 case 1: return BFD_RELOC_8_PCREL;
1195 case 2: return BFD_RELOC_16_PCREL;
1196 case 4: return BFD_RELOC_32_PCREL;
1197 }
d0b47220 1198 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1199 }
1200 else
1201 {
3e73aa7c 1202 if (sign)
e5cb08ac 1203 switch (size)
3e73aa7c
JH		 1204 {
1205 case 4: return BFD_RELOC_X86_64_32S;
1206 }
1207 else
1208 switch (size)
1209 {
1210 case 1: return BFD_RELOC_8;
1211 case 2: return BFD_RELOC_16;
1212 case 4: return BFD_RELOC_32;
1213 case 8: return BFD_RELOC_64;
1214 }
1215 as_bad (_("can not do %s %d byte relocation"),
1216 sign ? "signed" : "unsigned", size);
252b5132
RH		 1217 }
1218
bfb32b52 1219 abort ();
252b5132
RH		 1220 return BFD_RELOC_NONE;
1221}
1222
47926f60
KH		 1223/* Here we decide which fixups can be adjusted to make them relative to
1224 the beginning of the section instead of the symbol. Basically we need
1225 to make sure that the dynamic relocations are done correctly, so in
1226 some cases we force the original symbol to be used. */
1227
252b5132 1228int
c0c949c7 1229tc_i386_fix_adjustable (fixP)
31312f95 1230 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1231{
6d249963 1232#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1233 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1234 return 1;
1235
a161fe53
AM		 1236 /* Don't adjust pc-relative references to merge sections in 64-bit
1237 mode. */
1238 if (use_rela_relocations
1239 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1240 && fixP->fx_pcrel)
252b5132 1241 return 0;
31312f95 1242
8d01d9a9
AJ		 1243 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1244 and changed later by validate_fix. */
1245 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1246 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1247 return 0;
1248
ce8a8b2f 1249 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1250 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1251 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1252 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1253 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1254 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1255 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1256 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1257 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1258 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1259 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1260 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1261 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1262 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1263 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1264 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1265 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1266 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1267 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1268 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1269 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1270 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1271 return 0;
31312f95 1272#endif
252b5132
RH		 1273 return 1;
1274}
252b5132 1275
29b0f896 1276static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1277
1278static int
252b5132 1279intel_float_operand (mnemonic)
29b0f896 1280 const char *mnemonic;
252b5132 1281{
47926f60 1282 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1283 return 2;
252b5132
RH		 1284
1285 if (mnemonic[0] == 'f')
1286 return 1;
1287
1288 return 0;
1289}
1290
1291/* This is the guts of the machine-dependent assembler. LINE points to a
1292 machine dependent instruction. This function is supposed to emit
1293 the frags/bytes it assembles to. */
1294
1295void
1296md_assemble (line)
1297 char *line;
1298{
252b5132 1299 int j;
252b5132
RH		 1300 char mnemonic[MAX_MNEM_SIZE];
1301
47926f60 1302 /* Initialize globals. */
252b5132
RH		 1303 memset (&i, '\0', sizeof (i));
1304 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1305 i.reloc[j] = NO_RELOC;
252b5132
RH		 1306 memset (disp_expressions, '\0', sizeof (disp_expressions));
1307 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1308 save_stack_p = save_stack;
252b5132
RH		 1309
1310 /* First parse an instruction mnemonic & call i386_operand for the operands.
1311 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1312 start of a (possibly prefixed) mnemonic. */
252b5132 1313
29b0f896
AM		 1314 line = parse_insn (line, mnemonic);
1315 if (line == NULL)
1316 return;
252b5132 1317
29b0f896
AM		 1318 line = parse_operands (line, mnemonic);
1319 if (line == NULL)
1320 return;
252b5132 1321
29b0f896
AM		 1322 /* Now we've parsed the mnemonic into a set of templates, and have the
1323 operands at hand. */
1324
1325 /* All intel opcodes have reversed operands except for "bound" and
1326 "enter". We also don't reverse intersegment "jmp" and "call"
1327 instructions with 2 immediate operands so that the immediate segment
1328 precedes the offset, as it does when in AT&T mode. "enter" and the
1329 intersegment "jmp" and "call" instructions are the only ones that
1330 have two immediate operands. */
1331 if (intel_syntax && i.operands > 1
1332 && (strcmp (mnemonic, "bound") != 0)
1333 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1334 swap_operands ();
1335
1336 if (i.imm_operands)
1337 optimize_imm ();
1338
1339 if (i.disp_operands)
1340 optimize_disp ();
1341
1342 /* Next, we find a template that matches the given insn,
1343 making sure the overlap of the given operands types is consistent
1344 with the template operand types. */
252b5132 1345
29b0f896
AM		 1346 if (!match_template ())
1347 return;
252b5132 1348
cd61ebfe
AM		 1349 if (intel_syntax)
1350 {
1351 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1352 if (SYSV386_COMPAT
1353 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1354 i.tm.base_opcode ^= FloatR;
1355
1356 /* Zap movzx and movsx suffix. The suffix may have been set from
1357 "word ptr" or "byte ptr" on the source operand, but we'll use
1358 the suffix later to choose the destination register. */
1359 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1360 i.suffix = 0;
1361 }
24eab124 1362
29b0f896
AM		 1363 if (i.tm.opcode_modifier & FWait)
1364 if (!add_prefix (FWAIT_OPCODE))
1365 return;
252b5132 1366
29b0f896
AM		 1367 /* Check string instruction segment overrides. */
1368 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1369 {
1370 if (!check_string ())
5dd0794d 1371 return;
29b0f896 1372 }
5dd0794d 1373
29b0f896
AM		 1374 if (!process_suffix ())
1375 return;
e413e4e9 1376
29b0f896
AM		 1377 /* Make still unresolved immediate matches conform to size of immediate
1378 given in i.suffix. */
1379 if (!finalize_imm ())
1380 return;
252b5132 1381
29b0f896
AM		 1382 if (i.types[0] & Imm1)
1383 i.imm_operands = 0; /* kludge for shift insns. */
1384 if (i.types[0] & ImplicitRegister)
1385 i.reg_operands--;
1386 if (i.types[1] & ImplicitRegister)
1387 i.reg_operands--;
1388 if (i.types[2] & ImplicitRegister)
1389 i.reg_operands--;
252b5132 1390
29b0f896
AM		 1391 if (i.tm.opcode_modifier & ImmExt)
1392 {
02fc3089
L		 1393 expressionS *exp;
1394
ca164297
L		 1395 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1396 {
67c1ffbe 1397 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1398 operands with an opcode suffix which is coded in the same
1399 place as an 8-bit immediate field would be. Here we check
1400 those operands and remove them afterwards. */
1401 unsigned int x;
1402
a4622f40 1403 for (x = 0; x < i.operands; x++)
ca164297
L		 1404 if (i.op[x].regs->reg_num != x)
1405 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1406 i.op[x].regs->reg_name, x + 1, i.tm.name);
1407 i.operands = 0;
1408 }
1409
29b0f896
AM		 1410 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1411 opcode suffix which is coded in the same place as an 8-bit
1412 immediate field would be. Here we fake an 8-bit immediate
1413 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1414
29b0f896 1415 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1416
29b0f896
AM		 1417 exp = &im_expressions[i.imm_operands++];
1418 i.op[i.operands].imms = exp;
1419 i.types[i.operands++] = Imm8;
1420 exp->X_op = O_constant;
1421 exp->X_add_number = i.tm.extension_opcode;
1422 i.tm.extension_opcode = None;
1423 }
252b5132 1424
29b0f896
AM		 1425 /* For insns with operands there are more diddles to do to the opcode. */
1426 if (i.operands)
1427 {
1428 if (!process_operands ())
1429 return;
1430 }
1431 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1432 {
1433 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1434 as_warn (_("translating to `%sp'"), i.tm.name);
1435 }
252b5132 1436
29b0f896
AM		 1437 /* Handle conversion of 'int $3' --> special int3 insn. */
1438 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1439 {
1440 i.tm.base_opcode = INT3_OPCODE;
1441 i.imm_operands = 0;
1442 }
252b5132 1443
29b0f896
AM		 1444 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1445 && i.op[0].disps->X_op == O_constant)
1446 {
1447 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1448 the absolute address given by the constant. Since ix86 jumps and
1449 calls are pc relative, we need to generate a reloc. */
1450 i.op[0].disps->X_add_symbol = &abs_symbol;
1451 i.op[0].disps->X_op = O_symbol;
1452 }
252b5132 1453
29b0f896
AM		 1454 if ((i.tm.opcode_modifier & Rex64) != 0)
1455 i.rex |= REX_MODE64;
252b5132 1456
29b0f896
AM		 1457 /* For 8 bit registers we need an empty rex prefix. Also if the
1458 instruction already has a prefix, we need to convert old
1459 registers to new ones. */
773f551c 1460
29b0f896
AM		 1461 if (((i.types[0] & Reg8) != 0
1462 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1463 || ((i.types[1] & Reg8) != 0
1464 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1465 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1466 && i.rex != 0))
1467 {
1468 int x;
726c5dcd 1469
29b0f896
AM		 1470 i.rex |= REX_OPCODE;
1471 for (x = 0; x < 2; x++)
1472 {
1473 /* Look for 8 bit operand that uses old registers. */
1474 if ((i.types[x] & Reg8) != 0
1475 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1476 {
29b0f896
AM		 1477 /* In case it is "hi" register, give up. */
1478 if (i.op[x].regs->reg_num > 3)
1479 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1480 i.op[x].regs->reg_name);
773f551c 1481
29b0f896
AM		 1482 /* Otherwise it is equivalent to the extended register.
1483 Since the encoding doesn't change this is merely
1484 cosmetic cleanup for debug output. */
1485
1486 i.op[x].regs = i.op[x].regs + 8;
773f551c 1487 }
29b0f896
AM		 1488 }
1489 }
773f551c 1490
29b0f896
AM		 1491 if (i.rex != 0)
1492 add_prefix (REX_OPCODE | i.rex);
1493
1494 /* We are ready to output the insn. */
1495 output_insn ();
1496}
1497
1498static char *
1499parse_insn (line, mnemonic)
1500 char *line;
1501 char *mnemonic;
1502{
1503 char *l = line;
1504 char *token_start = l;
1505 char *mnem_p;
1506
1507 /* Non-zero if we found a prefix only acceptable with string insns. */
1508 const char *expecting_string_instruction = NULL;
45288df1 1509
29b0f896
AM		 1510 while (1)
1511 {
1512 mnem_p = mnemonic;
1513 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1514 {
1515 mnem_p++;
1516 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1517 {
29b0f896
AM		 1518 as_bad (_("no such instruction: `%s'"), token_start);
1519 return NULL;
1520 }
1521 l++;
1522 }
1523 if (!is_space_char (*l)
1524 && *l != END_OF_INSN
1525 && *l != PREFIX_SEPARATOR
1526 && *l != ',')
1527 {
1528 as_bad (_("invalid character %s in mnemonic"),
1529 output_invalid (*l));
1530 return NULL;
1531 }
1532 if (token_start == l)
1533 {
1534 if (*l == PREFIX_SEPARATOR)
1535 as_bad (_("expecting prefix; got nothing"));
1536 else
1537 as_bad (_("expecting mnemonic; got nothing"));
1538 return NULL;
1539 }
45288df1 1540
29b0f896
AM		 1541 /* Look up instruction (or prefix) via hash table. */
1542 current_templates = hash_find (op_hash, mnemonic);
47926f60 1543
29b0f896
AM		 1544 if (*l != END_OF_INSN
1545 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1546 && current_templates
1547 && (current_templates->start->opcode_modifier & IsPrefix))
1548 {
1549 /* If we are in 16-bit mode, do not allow addr16 or data16.
1550 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1551 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1552 && flag_code != CODE_64BIT
1553 && (((current_templates->start->opcode_modifier & Size32) != 0)
1554 ^ (flag_code == CODE_16BIT)))
1555 {
1556 as_bad (_("redundant %s prefix"),
1557 current_templates->start->name);
1558 return NULL;
45288df1 1559 }
29b0f896
AM		 1560 /* Add prefix, checking for repeated prefixes. */
1561 switch (add_prefix (current_templates->start->base_opcode))
1562 {
1563 case 0:
1564 return NULL;
1565 case 2:
1566 expecting_string_instruction = current_templates->start->name;
1567 break;
1568 }
1569 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1570 token_start = ++l;
1571 }
1572 else
1573 break;
1574 }
45288df1 1575
29b0f896
AM		 1576 if (!current_templates)
1577 {
1578 /* See if we can get a match by trimming off a suffix. */
1579 switch (mnem_p[-1])
1580 {
1581 case WORD_MNEM_SUFFIX:
1582 case BYTE_MNEM_SUFFIX:
1583 case QWORD_MNEM_SUFFIX:
1584 i.suffix = mnem_p[-1];
1585 mnem_p[-1] = '\0';
1586 current_templates = hash_find (op_hash, mnemonic);
1587 break;
1588 case SHORT_MNEM_SUFFIX:
1589 case LONG_MNEM_SUFFIX:
1590 if (!intel_syntax)
1591 {
1592 i.suffix = mnem_p[-1];
1593 mnem_p[-1] = '\0';
1594 current_templates = hash_find (op_hash, mnemonic);
1595 }
1596 break;
252b5132 1597
29b0f896
AM		 1598 /* Intel Syntax. */
1599 case 'd':
1600 if (intel_syntax)
1601 {
1602 if (intel_float_operand (mnemonic))
1603 i.suffix = SHORT_MNEM_SUFFIX;
1604 else
1605 i.suffix = LONG_MNEM_SUFFIX;
1606 mnem_p[-1] = '\0';
1607 current_templates = hash_find (op_hash, mnemonic);
1608 }
1609 break;
1610 }
1611 if (!current_templates)
1612 {
1613 as_bad (_("no such instruction: `%s'"), token_start);
1614 return NULL;
1615 }
1616 }
252b5132 1617
29b0f896
AM		 1618 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1619 {
1620 /* Check for a branch hint. We allow ",pt" and ",pn" for
1621 predict taken and predict not taken respectively.
1622 I'm not sure that branch hints actually do anything on loop
1623 and jcxz insns (JumpByte) for current Pentium4 chips. They
1624 may work in the future and it doesn't hurt to accept them
1625 now. */
1626 if (l[0] == ',' && l[1] == 'p')
1627 {
1628 if (l[2] == 't')
1629 {
1630 if (!add_prefix (DS_PREFIX_OPCODE))
1631 return NULL;
1632 l += 3;
1633 }
1634 else if (l[2] == 'n')
1635 {
1636 if (!add_prefix (CS_PREFIX_OPCODE))
1637 return NULL;
1638 l += 3;
1639 }
1640 }
1641 }
1642 /* Any other comma loses. */
1643 if (*l == ',')
1644 {
1645 as_bad (_("invalid character %s in mnemonic"),
1646 output_invalid (*l));
1647 return NULL;
1648 }
252b5132 1649
29b0f896
AM		 1650 /* Check if instruction is supported on specified architecture. */
1651 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1652 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1653 {
1654 as_warn (_("`%s' is not supported on `%s'"),
1655 current_templates->start->name, cpu_arch_name);
1656 }
1657 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1658 {
1659 as_warn (_("use .code16 to ensure correct addressing mode"));
1660 }
252b5132 1661
29b0f896
AM		 1662 /* Check for rep/repne without a string instruction. */
1663 if (expecting_string_instruction
1664 && !(current_templates->start->opcode_modifier & IsString))
1665 {
1666 as_bad (_("expecting string instruction after `%s'"),
1667 expecting_string_instruction);
1668 return NULL;
1669 }
252b5132 1670
29b0f896
AM		 1671 return l;
1672}
252b5132 1673
29b0f896
AM		 1674static char *
1675parse_operands (l, mnemonic)
1676 char *l;
1677 const char *mnemonic;
1678{
1679 char *token_start;
3138f287 1680
29b0f896
AM		 1681 /* 1 if operand is pending after ','. */
1682 unsigned int expecting_operand = 0;
252b5132 1683
29b0f896
AM		 1684 /* Non-zero if operand parens not balanced. */
1685 unsigned int paren_not_balanced;
1686
1687 while (*l != END_OF_INSN)
1688 {
1689 /* Skip optional white space before operand. */
1690 if (is_space_char (*l))
1691 ++l;
1692 if (!is_operand_char (*l) && *l != END_OF_INSN)
1693 {
1694 as_bad (_("invalid character %s before operand %d"),
1695 output_invalid (*l),
1696 i.operands + 1);
1697 return NULL;
1698 }
1699 token_start = l; /* after white space */
1700 paren_not_balanced = 0;
1701 while (paren_not_balanced || *l != ',')
1702 {
1703 if (*l == END_OF_INSN)
1704 {
1705 if (paren_not_balanced)
1706 {
1707 if (!intel_syntax)
1708 as_bad (_("unbalanced parenthesis in operand %d."),
1709 i.operands + 1);
1710 else
1711 as_bad (_("unbalanced brackets in operand %d."),
1712 i.operands + 1);
1713 return NULL;
1714 }
1715 else
1716 break; /* we are done */
1717 }
1718 else if (!is_operand_char (*l) && !is_space_char (*l))
1719 {
1720 as_bad (_("invalid character %s in operand %d"),
1721 output_invalid (*l),
1722 i.operands + 1);
1723 return NULL;
1724 }
1725 if (!intel_syntax)
1726 {
1727 if (*l == '(')
1728 ++paren_not_balanced;
1729 if (*l == ')')
1730 --paren_not_balanced;
1731 }
1732 else
1733 {
1734 if (*l == '[')
1735 ++paren_not_balanced;
1736 if (*l == ']')
1737 --paren_not_balanced;
1738 }
1739 l++;
1740 }
1741 if (l != token_start)
1742 { /* Yes, we've read in another operand. */
1743 unsigned int operand_ok;
1744 this_operand = i.operands++;
1745 if (i.operands > MAX_OPERANDS)
1746 {
1747 as_bad (_("spurious operands; (%d operands/instruction max)"),
1748 MAX_OPERANDS);
1749 return NULL;
1750 }
1751 /* Now parse operand adding info to 'i' as we go along. */
1752 END_STRING_AND_SAVE (l);
1753
1754 if (intel_syntax)
1755 operand_ok =
1756 i386_intel_operand (token_start,
1757 intel_float_operand (mnemonic));
1758 else
1759 operand_ok = i386_operand (token_start);
1760
1761 RESTORE_END_STRING (l);
1762 if (!operand_ok)
1763 return NULL;
1764 }
1765 else
1766 {
1767 if (expecting_operand)
1768 {
1769 expecting_operand_after_comma:
1770 as_bad (_("expecting operand after ','; got nothing"));
1771 return NULL;
1772 }
1773 if (*l == ',')
1774 {
1775 as_bad (_("expecting operand before ','; got nothing"));
1776 return NULL;
1777 }
1778 }
7f3f1ea2 1779
29b0f896
AM		 1780 /* Now *l must be either ',' or END_OF_INSN. */
1781 if (*l == ',')
1782 {
1783 if (*++l == END_OF_INSN)
1784 {
1785 /* Just skip it, if it's \n complain. */
1786 goto expecting_operand_after_comma;
1787 }
1788 expecting_operand = 1;
1789 }
1790 }
1791 return l;
1792}
7f3f1ea2 1793
29b0f896
AM		 1794static void
1795swap_operands ()
1796{
1797 union i386_op temp_op;
1798 unsigned int temp_type;
f86103b7 1799 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1800 int xchg1 = 0;
1801 int xchg2 = 0;
252b5132 1802
29b0f896
AM		 1803 if (i.operands == 2)
1804 {
1805 xchg1 = 0;
1806 xchg2 = 1;
1807 }
1808 else if (i.operands == 3)
1809 {
1810 xchg1 = 0;
1811 xchg2 = 2;
1812 }
1813 temp_type = i.types[xchg2];
1814 i.types[xchg2] = i.types[xchg1];
1815 i.types[xchg1] = temp_type;
1816 temp_op = i.op[xchg2];
1817 i.op[xchg2] = i.op[xchg1];
1818 i.op[xchg1] = temp_op;
1819 temp_reloc = i.reloc[xchg2];
1820 i.reloc[xchg2] = i.reloc[xchg1];
1821 i.reloc[xchg1] = temp_reloc;
1822
1823 if (i.mem_operands == 2)
1824 {
1825 const seg_entry *temp_seg;
1826 temp_seg = i.seg[0];
1827 i.seg[0] = i.seg[1];
1828 i.seg[1] = temp_seg;
1829 }
1830}
252b5132 1831
29b0f896
AM		 1832/* Try to ensure constant immediates are represented in the smallest
1833 opcode possible. */
1834static void
1835optimize_imm ()
1836{
1837 char guess_suffix = 0;
1838 int op;
252b5132 1839
29b0f896
AM		 1840 if (i.suffix)
1841 guess_suffix = i.suffix;
1842 else if (i.reg_operands)
1843 {
1844 /* Figure out a suffix from the last register operand specified.
1845 We can't do this properly yet, ie. excluding InOutPortReg,
1846 but the following works for instructions with immediates.
1847 In any case, we can't set i.suffix yet. */
1848 for (op = i.operands; --op >= 0;)
1849 if (i.types[op] & Reg)
252b5132 1850 {
29b0f896
AM		 1851 if (i.types[op] & Reg8)
1852 guess_suffix = BYTE_MNEM_SUFFIX;
1853 else if (i.types[op] & Reg16)
1854 guess_suffix = WORD_MNEM_SUFFIX;
1855 else if (i.types[op] & Reg32)
1856 guess_suffix = LONG_MNEM_SUFFIX;
1857 else if (i.types[op] & Reg64)
1858 guess_suffix = QWORD_MNEM_SUFFIX;
1859 break;
252b5132 1860 }
29b0f896
AM		 1861 }
1862 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1863 guess_suffix = WORD_MNEM_SUFFIX;
1864
1865 for (op = i.operands; --op >= 0;)
1866 if (i.types[op] & Imm)
1867 {
1868 switch (i.op[op].imms->X_op)
252b5132 1869 {
29b0f896
AM		 1870 case O_constant:
1871 /* If a suffix is given, this operand may be shortened. */
1872 switch (guess_suffix)
252b5132 1873 {
29b0f896
AM		 1874 case LONG_MNEM_SUFFIX:
1875 i.types[op] |= Imm32 | Imm64;
1876 break;
1877 case WORD_MNEM_SUFFIX:
1878 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1879 break;
1880 case BYTE_MNEM_SUFFIX:
1881 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1882 break;
252b5132 1883 }
252b5132 1884
29b0f896
AM		 1885 /* If this operand is at most 16 bits, convert it
1886 to a signed 16 bit number before trying to see
1887 whether it will fit in an even smaller size.
1888 This allows a 16-bit operand such as $0xffe0 to
1889 be recognised as within Imm8S range. */
1890 if ((i.types[op] & Imm16)
1891 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1892 {
29b0f896
AM		 1893 i.op[op].imms->X_add_number =
1894 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1895 }
1896 if ((i.types[op] & Imm32)
1897 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1898 == 0))
1899 {
1900 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1901 ^ ((offsetT) 1 << 31))
1902 - ((offsetT) 1 << 31));
1903 }
1904 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1905
29b0f896
AM		 1906 /* We must avoid matching of Imm32 templates when 64bit
1907 only immediate is available. */
1908 if (guess_suffix == QWORD_MNEM_SUFFIX)
1909 i.types[op] &= ~Imm32;
1910 break;
252b5132 1911
29b0f896
AM		 1912 case O_absent:
1913 case O_register:
1914 abort ();
1915
1916 /* Symbols and expressions. */
1917 default:
1918 /* Convert symbolic operand to proper sizes for matching. */
1919 switch (guess_suffix)
1920 {
1921 case QWORD_MNEM_SUFFIX:
1922 i.types[op] = Imm64 | Imm32S;
1923 break;
1924 case LONG_MNEM_SUFFIX:
1925 i.types[op] = Imm32 | Imm64;
1926 break;
1927 case WORD_MNEM_SUFFIX:
1928 i.types[op] = Imm16 | Imm32 | Imm64;
1929 break;
1930 break;
1931 case BYTE_MNEM_SUFFIX:
1932 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1933 break;
1934 break;
252b5132 1935 }
29b0f896 1936 break;
252b5132 1937 }
29b0f896
AM		 1938 }
1939}
47926f60 1940
29b0f896
AM		 1941/* Try to use the smallest displacement type too. */
1942static void
1943optimize_disp ()
1944{
1945 int op;
3e73aa7c 1946
29b0f896
AM		 1947 for (op = i.operands; --op >= 0;)
1948 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1949 {
29b0f896
AM		 1950 offsetT disp = i.op[op].disps->X_add_number;
1951
1952 if (i.types[op] & Disp16)
252b5132 1953 {
29b0f896
AM		 1954 /* We know this operand is at most 16 bits, so
1955 convert to a signed 16 bit number before trying
1956 to see whether it will fit in an even smaller
1957 size. */
1958
1959 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1960 }
29b0f896 1961 else if (i.types[op] & Disp32)
252b5132 1962 {
29b0f896
AM		 1963 /* We know this operand is at most 32 bits, so convert to a
1964 signed 32 bit number before trying to see whether it will
1965 fit in an even smaller size. */
1966 disp &= (((offsetT) 2 << 31) - 1);
1967 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1968 }
29b0f896 1969 if (flag_code == CODE_64BIT)
252b5132 1970 {
29b0f896
AM		 1971 if (fits_in_signed_long (disp))
1972 i.types[op] |= Disp32S;
1973 if (fits_in_unsigned_long (disp))
1974 i.types[op] |= Disp32;
252b5132 1975 }
29b0f896
AM		 1976 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1977 && fits_in_signed_byte (disp))
1978 i.types[op] |= Disp8;
252b5132 1979 }
29b0f896
AM		 1980}
1981
1982static int
1983match_template ()
1984{
1985 /* Points to template once we've found it. */
1986 const template *t;
1987 unsigned int overlap0, overlap1, overlap2;
1988 unsigned int found_reverse_match;
1989 int suffix_check;
1990
1991#define MATCH(overlap, given, template) \
1992 ((overlap & ~JumpAbsolute) \
1993 && (((given) & (BaseIndex | JumpAbsolute)) \
1994 == ((overlap) & (BaseIndex | JumpAbsolute))))
1995
1996 /* If given types r0 and r1 are registers they must be of the same type
1997 unless the expected operand type register overlap is null.
1998 Note that Acc in a template matches every size of reg. */
1999#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2000 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2001 || ((g0) & Reg) == ((g1) & Reg) \
2002 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2003
2004 overlap0 = 0;
2005 overlap1 = 0;
2006 overlap2 = 0;
2007 found_reverse_match = 0;
2008 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2009 ? No_bSuf
2010 : (i.suffix == WORD_MNEM_SUFFIX
2011 ? No_wSuf
2012 : (i.suffix == SHORT_MNEM_SUFFIX
2013 ? No_sSuf
2014 : (i.suffix == LONG_MNEM_SUFFIX
2015 ? No_lSuf
2016 : (i.suffix == QWORD_MNEM_SUFFIX
2017 ? No_qSuf
2018 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2019 ? No_xSuf : 0))))));
2020
2021 for (t = current_templates->start;
2022 t < current_templates->end;
2023 t++)
2024 {
2025 /* Must have right number of operands. */
2026 if (i.operands != t->operands)
2027 continue;
2028
2029 /* Check the suffix, except for some instructions in intel mode. */
2030 if ((t->opcode_modifier & suffix_check)
2031 && !(intel_syntax
2032 && (t->opcode_modifier & IgnoreSize))
2033 && !(intel_syntax
2034 && t->base_opcode == 0xd9
2035 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2036 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2037 continue;
2038
2039 /* Do not verify operands when there are none. */
2040 else if (!t->operands)
2041 {
2042 if (t->cpu_flags & ~cpu_arch_flags)
2043 continue;
2044 /* We've found a match; break out of loop. */
2045 break;
2046 }
252b5132 2047
29b0f896
AM		 2048 overlap0 = i.types[0] & t->operand_types[0];
2049 switch (t->operands)
2050 {
2051 case 1:
2052 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2053 continue;
2054 break;
2055 case 2:
2056 case 3:
2057 overlap1 = i.types[1] & t->operand_types[1];
2058 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2059 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2060 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2061 t->operand_types[0],
2062 overlap1, i.types[1],
2063 t->operand_types[1]))
2064 {
2065 /* Check if other direction is valid ... */
2066 if ((t->opcode_modifier & (D | FloatD)) == 0)
2067 continue;
2068
2069 /* Try reversing direction of operands. */
2070 overlap0 = i.types[0] & t->operand_types[1];
2071 overlap1 = i.types[1] & t->operand_types[0];
2072 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2073 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2074 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2075 t->operand_types[1],
2076 overlap1, i.types[1],
2077 t->operand_types[0]))
2078 {
2079 /* Does not match either direction. */
2080 continue;
2081 }
2082 /* found_reverse_match holds which of D or FloatDR
2083 we've found. */
2084 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2085 }
2086 /* Found a forward 2 operand match here. */
2087 else if (t->operands == 3)
2088 {
2089 /* Here we make use of the fact that there are no
2090 reverse match 3 operand instructions, and all 3
2091 operand instructions only need to be checked for
2092 register consistency between operands 2 and 3. */
2093 overlap2 = i.types[2] & t->operand_types[2];
2094 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2095 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2096 t->operand_types[1],
2097 overlap2, i.types[2],
2098 t->operand_types[2]))
2099
2100 continue;
2101 }
2102 /* Found either forward/reverse 2 or 3 operand match here:
2103 slip through to break. */
2104 }
2105 if (t->cpu_flags & ~cpu_arch_flags)
2106 {
2107 found_reverse_match = 0;
2108 continue;
2109 }
2110 /* We've found a match; break out of loop. */
2111 break;
2112 }
2113
2114 if (t == current_templates->end)
2115 {
2116 /* We found no match. */
2117 as_bad (_("suffix or operands invalid for `%s'"),
2118 current_templates->start->name);
2119 return 0;
2120 }
252b5132 2121
29b0f896
AM		 2122 if (!quiet_warnings)
2123 {
2124 if (!intel_syntax
2125 && ((i.types[0] & JumpAbsolute)
2126 != (t->operand_types[0] & JumpAbsolute)))
2127 {
2128 as_warn (_("indirect %s without `*'"), t->name);
2129 }
2130
2131 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2132 == (IsPrefix | IgnoreSize))
2133 {
2134 /* Warn them that a data or address size prefix doesn't
2135 affect assembly of the next line of code. */
2136 as_warn (_("stand-alone `%s' prefix"), t->name);
2137 }
2138 }
2139
2140 /* Copy the template we found. */
2141 i.tm = *t;
2142 if (found_reverse_match)
2143 {
2144 /* If we found a reverse match we must alter the opcode
2145 direction bit. found_reverse_match holds bits to change
2146 (different for int & float insns). */
2147
2148 i.tm.base_opcode ^= found_reverse_match;
2149
2150 i.tm.operand_types[0] = t->operand_types[1];
2151 i.tm.operand_types[1] = t->operand_types[0];
2152 }
2153
2154 return 1;
2155}
2156
2157static int
2158check_string ()
2159{
2160 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2161 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2162 {
2163 if (i.seg[0] != NULL && i.seg[0] != &es)
2164 {
2165 as_bad (_("`%s' operand %d must use `%%es' segment"),
2166 i.tm.name,
2167 mem_op + 1);
2168 return 0;
2169 }
2170 /* There's only ever one segment override allowed per instruction.
2171 This instruction possibly has a legal segment override on the
2172 second operand, so copy the segment to where non-string
2173 instructions store it, allowing common code. */
2174 i.seg[0] = i.seg[1];
2175 }
2176 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2177 {
2178 if (i.seg[1] != NULL && i.seg[1] != &es)
2179 {
2180 as_bad (_("`%s' operand %d must use `%%es' segment"),
2181 i.tm.name,
2182 mem_op + 2);
2183 return 0;
2184 }
2185 }
2186 return 1;
2187}
2188
2189static int
2190process_suffix ()
2191{
2192 /* If matched instruction specifies an explicit instruction mnemonic
2193 suffix, use it. */
2194 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2195 {
2196 if (i.tm.opcode_modifier & Size16)
2197 i.suffix = WORD_MNEM_SUFFIX;
2198 else if (i.tm.opcode_modifier & Size64)
2199 i.suffix = QWORD_MNEM_SUFFIX;
2200 else
2201 i.suffix = LONG_MNEM_SUFFIX;
2202 }
2203 else if (i.reg_operands)
2204 {
2205 /* If there's no instruction mnemonic suffix we try to invent one
2206 based on register operands. */
2207 if (!i.suffix)
2208 {
2209 /* We take i.suffix from the last register operand specified,
2210 Destination register type is more significant than source
2211 register type. */
2212 int op;
2213 for (op = i.operands; --op >= 0;)
2214 if ((i.types[op] & Reg)
2215 && !(i.tm.operand_types[op] & InOutPortReg))
2216 {
2217 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2218 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2219 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2220 LONG_MNEM_SUFFIX);
2221 break;
2222 }
2223 }
2224 else if (i.suffix == BYTE_MNEM_SUFFIX)
2225 {
2226 if (!check_byte_reg ())
2227 return 0;
2228 }
2229 else if (i.suffix == LONG_MNEM_SUFFIX)
2230 {
2231 if (!check_long_reg ())
2232 return 0;
2233 }
2234 else if (i.suffix == QWORD_MNEM_SUFFIX)
2235 {
2236 if (!check_qword_reg ())
2237 return 0;
2238 }
2239 else if (i.suffix == WORD_MNEM_SUFFIX)
2240 {
2241 if (!check_word_reg ())
2242 return 0;
2243 }
2244 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2245 /* Do nothing if the instruction is going to ignore the prefix. */
2246 ;
2247 else
2248 abort ();
2249 }
2250 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2251 {
2252 i.suffix = stackop_size;
2253 }
252b5132 2254
29b0f896
AM		 2255 /* Change the opcode based on the operand size given by i.suffix;
2256 We need not change things for byte insns. */
252b5132 2257
29b0f896
AM		 2258 if (!i.suffix && (i.tm.opcode_modifier & W))
2259 {
2260 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2261 return 0;
2262 }
252b5132 2263
29b0f896
AM		 2264 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2265 {
2266 /* It's not a byte, select word/dword operation. */
2267 if (i.tm.opcode_modifier & W)
2268 {
2269 if (i.tm.opcode_modifier & ShortForm)
2270 i.tm.base_opcode |= 8;
2271 else
2272 i.tm.base_opcode |= 1;
2273 }
0f3f3d8b 2274
29b0f896
AM		 2275 /* Now select between word & dword operations via the operand
2276 size prefix, except for instructions that will ignore this
2277 prefix anyway. */
2278 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2279 && !(i.tm.opcode_modifier & IgnoreSize)
2280 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2281 || (flag_code == CODE_64BIT
2282 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2283 {
2284 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2285 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2286 prefix = ADDR_PREFIX_OPCODE;
252b5132 2287
29b0f896
AM		 2288 if (!add_prefix (prefix))
2289 return 0;
24eab124 2290 }
252b5132 2291
29b0f896
AM		 2292 /* Set mode64 for an operand. */
2293 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2294 && flag_code == CODE_64BIT
29b0f896 2295 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2296 i.rex |= REX_MODE64;
3e73aa7c 2297
29b0f896
AM		 2298 /* Size floating point instruction. */
2299 if (i.suffix == LONG_MNEM_SUFFIX)
2300 {
2301 if (i.tm.opcode_modifier & FloatMF)
2302 i.tm.base_opcode ^= 4;
2303 }
2304 }
7ecd2f8b 2305
29b0f896
AM		 2306 return 1;
2307}
3e73aa7c 2308
29b0f896
AM		 2309static int
2310check_byte_reg ()
2311{
2312 int op;
2313 for (op = i.operands; --op >= 0;)
2314 {
2315 /* If this is an eight bit register, it's OK. If it's the 16 or
2316 32 bit version of an eight bit register, we will just use the
2317 low portion, and that's OK too. */
2318 if (i.types[op] & Reg8)
2319 continue;
2320
2321 /* movzx and movsx should not generate this warning. */
2322 if (intel_syntax
2323 && (i.tm.base_opcode == 0xfb7
2324 || i.tm.base_opcode == 0xfb6
2325 || i.tm.base_opcode == 0x63
2326 || i.tm.base_opcode == 0xfbe
2327 || i.tm.base_opcode == 0xfbf))
2328 continue;
2329
2330 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2331#if 0
2332 /* Check that the template allows eight bit regs. This
2333 kills insns such as `orb $1,%edx', which maybe should be
2334 allowed. */
2335 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2336#endif
2337 )
2338 {
2339 /* Prohibit these changes in the 64bit mode, since the
2340 lowering is more complicated. */
2341 if (flag_code == CODE_64BIT
2342 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2343 {
0f3f3d8b 2344 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2345 i.op[op].regs->reg_name,
2346 i.suffix);
2347 return 0;
2348 }
2349#if REGISTER_WARNINGS
2350 if (!quiet_warnings
2351 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2352 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2353 (i.op[op].regs + (i.types[op] & Reg16
2354 ? REGNAM_AL - REGNAM_AX
2355 : REGNAM_AL - REGNAM_EAX))->reg_name,
2356 i.op[op].regs->reg_name,
2357 i.suffix);
2358#endif
2359 continue;
2360 }
2361 /* Any other register is bad. */
2362 if (i.types[op] & (Reg | RegMMX | RegXMM
2363 | SReg2 | SReg3
2364 | Control | Debug | Test
2365 | FloatReg | FloatAcc))
2366 {
2367 as_bad (_("`%%%s' not allowed with `%s%c'"),
2368 i.op[op].regs->reg_name,
2369 i.tm.name,
2370 i.suffix);
2371 return 0;
2372 }
2373 }
2374 return 1;
2375}
2376
2377static int
2378check_long_reg ()
2379{
2380 int op;
2381
2382 for (op = i.operands; --op >= 0;)
2383 /* Reject eight bit registers, except where the template requires
2384 them. (eg. movzb) */
2385 if ((i.types[op] & Reg8) != 0
2386 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2387 {
2388 as_bad (_("`%%%s' not allowed with `%s%c'"),
2389 i.op[op].regs->reg_name,
2390 i.tm.name,
2391 i.suffix);
2392 return 0;
2393 }
2394 /* Warn if the e prefix on a general reg is missing. */
2395 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2396 && (i.types[op] & Reg16) != 0
2397 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2398 {
2399 /* Prohibit these changes in the 64bit mode, since the
2400 lowering is more complicated. */
2401 if (flag_code == CODE_64BIT)
252b5132 2402 {
0f3f3d8b 2403 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2404 i.op[op].regs->reg_name,
2405 i.suffix);
2406 return 0;
252b5132 2407 }
29b0f896
AM		 2408#if REGISTER_WARNINGS
2409 else
2410 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2411 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2412 i.op[op].regs->reg_name,
2413 i.suffix);
2414#endif
252b5132 2415 }
29b0f896
AM		 2416 /* Warn if the r prefix on a general reg is missing. */
2417 else if ((i.types[op] & Reg64) != 0
2418 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2419 {
0f3f3d8b 2420 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2421 i.op[op].regs->reg_name,
2422 i.suffix);
2423 return 0;
2424 }
2425 return 1;
2426}
252b5132 2427
29b0f896
AM		 2428static int
2429check_qword_reg ()
2430{
2431 int op;
252b5132 2432
29b0f896
AM		 2433 for (op = i.operands; --op >= 0; )
2434 /* Reject eight bit registers, except where the template requires
2435 them. (eg. movzb) */
2436 if ((i.types[op] & Reg8) != 0
2437 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2438 {
2439 as_bad (_("`%%%s' not allowed with `%s%c'"),
2440 i.op[op].regs->reg_name,
2441 i.tm.name,
2442 i.suffix);
2443 return 0;
2444 }
2445 /* Warn if the e prefix on a general reg is missing. */
2446 else if (((i.types[op] & Reg16) != 0
2447 || (i.types[op] & Reg32) != 0)
2448 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2449 {
2450 /* Prohibit these changes in the 64bit mode, since the
2451 lowering is more complicated. */
0f3f3d8b 2452 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2453 i.op[op].regs->reg_name,
2454 i.suffix);
2455 return 0;
252b5132 2456 }
29b0f896
AM		 2457 return 1;
2458}
252b5132 2459
29b0f896
AM		 2460static int
2461check_word_reg ()
2462{
2463 int op;
2464 for (op = i.operands; --op >= 0;)
2465 /* Reject eight bit registers, except where the template requires
2466 them. (eg. movzb) */
2467 if ((i.types[op] & Reg8) != 0
2468 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2469 {
2470 as_bad (_("`%%%s' not allowed with `%s%c'"),
2471 i.op[op].regs->reg_name,
2472 i.tm.name,
2473 i.suffix);
2474 return 0;
2475 }
2476 /* Warn if the e prefix on a general reg is present. */
2477 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2478 && (i.types[op] & Reg32) != 0
2479 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2480 {
29b0f896
AM		 2481 /* Prohibit these changes in the 64bit mode, since the
2482 lowering is more complicated. */
2483 if (flag_code == CODE_64BIT)
252b5132 2484 {
0f3f3d8b 2485 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2486 i.op[op].regs->reg_name,
2487 i.suffix);
2488 return 0;
252b5132 2489 }
29b0f896
AM		 2490 else
2491#if REGISTER_WARNINGS
2492 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2493 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2494 i.op[op].regs->reg_name,
2495 i.suffix);
2496#endif
2497 }
2498 return 1;
2499}
252b5132 2500
29b0f896
AM		 2501static int
2502finalize_imm ()
2503{
2504 unsigned int overlap0, overlap1, overlap2;
2505
2506 overlap0 = i.types[0] & i.tm.operand_types[0];
2507 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2508 && overlap0 != Imm8 && overlap0 != Imm8S
2509 && overlap0 != Imm16 && overlap0 != Imm32S
2510 && overlap0 != Imm32 && overlap0 != Imm64)
2511 {
2512 if (i.suffix)
2513 {
2514 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2515 ? Imm8 | Imm8S
2516 : (i.suffix == WORD_MNEM_SUFFIX
2517 ? Imm16
2518 : (i.suffix == QWORD_MNEM_SUFFIX
2519 ? Imm64 | Imm32S
2520 : Imm32)));
2521 }
2522 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2523 || overlap0 == (Imm16 | Imm32)
2524 || overlap0 == (Imm16 | Imm32S))
2525 {
2526 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2527 ? Imm16 : Imm32S);
2528 }
2529 if (overlap0 != Imm8 && overlap0 != Imm8S
2530 && overlap0 != Imm16 && overlap0 != Imm32S
2531 && overlap0 != Imm32 && overlap0 != Imm64)
2532 {
2533 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2534 return 0;
2535 }
2536 }
2537 i.types[0] = overlap0;
2538
2539 overlap1 = i.types[1] & i.tm.operand_types[1];
2540 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2541 && overlap1 != Imm8 && overlap1 != Imm8S
2542 && overlap1 != Imm16 && overlap1 != Imm32S
2543 && overlap1 != Imm32 && overlap1 != Imm64)
2544 {
2545 if (i.suffix)
2546 {
2547 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2548 ? Imm8 | Imm8S
2549 : (i.suffix == WORD_MNEM_SUFFIX
2550 ? Imm16
2551 : (i.suffix == QWORD_MNEM_SUFFIX
2552 ? Imm64 | Imm32S
2553 : Imm32)));
2554 }
2555 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2556 || overlap1 == (Imm16 | Imm32)
2557 || overlap1 == (Imm16 | Imm32S))
2558 {
2559 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2560 ? Imm16 : Imm32S);
2561 }
2562 if (overlap1 != Imm8 && overlap1 != Imm8S
2563 && overlap1 != Imm16 && overlap1 != Imm32S
2564 && overlap1 != Imm32 && overlap1 != Imm64)
2565 {
2566 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2567 return 0;
2568 }
2569 }
2570 i.types[1] = overlap1;
2571
2572 overlap2 = i.types[2] & i.tm.operand_types[2];
2573 assert ((overlap2 & Imm) == 0);
2574 i.types[2] = overlap2;
2575
2576 return 1;
2577}
2578
2579static int
2580process_operands ()
2581{
2582 /* Default segment register this instruction will use for memory
2583 accesses. 0 means unknown. This is only for optimizing out
2584 unnecessary segment overrides. */
2585 const seg_entry *default_seg = 0;
2586
2587 /* The imul $imm, %reg instruction is converted into
2588 imul $imm, %reg, %reg, and the clr %reg instruction
2589 is converted into xor %reg, %reg. */
2590 if (i.tm.opcode_modifier & regKludge)
2591 {
2592 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2593 /* Pretend we saw the extra register operand. */
2594 assert (i.op[first_reg_op + 1].regs == 0);
2595 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2596 i.types[first_reg_op + 1] = i.types[first_reg_op];
2597 i.reg_operands = 2;
2598 }
2599
2600 if (i.tm.opcode_modifier & ShortForm)
2601 {
2602 /* The register or float register operand is in operand 0 or 1. */
2603 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2604 /* Register goes in low 3 bits of opcode. */
2605 i.tm.base_opcode |= i.op[op].regs->reg_num;
2606 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2607 i.rex |= REX_EXTZ;
2608 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2609 {
2610 /* Warn about some common errors, but press on regardless.
2611 The first case can be generated by gcc (<= 2.8.1). */
2612 if (i.operands == 2)
2613 {
2614 /* Reversed arguments on faddp, fsubp, etc. */
2615 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2616 i.op[1].regs->reg_name,
2617 i.op[0].regs->reg_name);
2618 }
2619 else
2620 {
2621 /* Extraneous `l' suffix on fp insn. */
2622 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2623 i.op[0].regs->reg_name);
2624 }
2625 }
2626 }
2627 else if (i.tm.opcode_modifier & Modrm)
2628 {
2629 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2630 must be put into the modrm byte). Now, we make the modrm and
2631 index base bytes based on all the info we've collected. */
29b0f896
AM		 2632
2633 default_seg = build_modrm_byte ();
2634 }
2635 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2636 {
2637 if (i.tm.base_opcode == POP_SEG_SHORT
2638 && i.op[0].regs->reg_num == 1)
2639 {
2640 as_bad (_("you can't `pop %%cs'"));
2641 return 0;
2642 }
2643 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2644 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2645 i.rex |= REX_EXTZ;
2646 }
2647 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2648 {
2649 default_seg = &ds;
2650 }
2651 else if ((i.tm.opcode_modifier & IsString) != 0)
2652 {
2653 /* For the string instructions that allow a segment override
2654 on one of their operands, the default segment is ds. */
2655 default_seg = &ds;
2656 }
2657
52271982
AM		 2658 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2659 as_warn (_("segment override on `lea' is ineffectual"));
2660
2661 /* If a segment was explicitly specified, and the specified segment
2662 is not the default, use an opcode prefix to select it. If we
2663 never figured out what the default segment is, then default_seg
2664 will be zero at this point, and the specified segment prefix will
2665 always be used. */
29b0f896
AM		 2666 if ((i.seg[0]) && (i.seg[0] != default_seg))
2667 {
2668 if (!add_prefix (i.seg[0]->seg_prefix))
2669 return 0;
2670 }
2671 return 1;
2672}
2673
2674static const seg_entry *
2675build_modrm_byte ()
2676{
2677 const seg_entry *default_seg = 0;
2678
2679 /* i.reg_operands MUST be the number of real register operands;
2680 implicit registers do not count. */
2681 if (i.reg_operands == 2)
2682 {
2683 unsigned int source, dest;
2684 source = ((i.types[0]
2685 & (Reg | RegMMX | RegXMM
2686 | SReg2 | SReg3
2687 | Control | Debug | Test))
2688 ? 0 : 1);
2689 dest = source + 1;
2690
2691 i.rm.mode = 3;
2692 /* One of the register operands will be encoded in the i.tm.reg
2693 field, the other in the combined i.tm.mode and i.tm.regmem
2694 fields. If no form of this instruction supports a memory
2695 destination operand, then we assume the source operand may
2696 sometimes be a memory operand and so we need to store the
2697 destination in the i.rm.reg field. */
2698 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2699 {
2700 i.rm.reg = i.op[dest].regs->reg_num;
2701 i.rm.regmem = i.op[source].regs->reg_num;
2702 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2703 i.rex |= REX_EXTX;
2704 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2705 i.rex |= REX_EXTZ;
2706 }
2707 else
2708 {
2709 i.rm.reg = i.op[source].regs->reg_num;
2710 i.rm.regmem = i.op[dest].regs->reg_num;
2711 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2712 i.rex |= REX_EXTZ;
2713 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2714 i.rex |= REX_EXTX;
2715 }
2716 }
2717 else
2718 { /* If it's not 2 reg operands... */
2719 if (i.mem_operands)
2720 {
2721 unsigned int fake_zero_displacement = 0;
2722 unsigned int op = ((i.types[0] & AnyMem)
2723 ? 0
2724 : (i.types[1] & AnyMem) ? 1 : 2);
2725
2726 default_seg = &ds;
2727
2728 if (i.base_reg == 0)
2729 {
2730 i.rm.mode = 0;
2731 if (!i.disp_operands)
2732 fake_zero_displacement = 1;
2733 if (i.index_reg == 0)
2734 {
2735 /* Operand is just <disp> */
2736 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2737 && (flag_code != CODE_64BIT))
2738 {
2739 i.rm.regmem = NO_BASE_REGISTER_16;
2740 i.types[op] &= ~Disp;
2741 i.types[op] |= Disp16;
2742 }
2743 else if (flag_code != CODE_64BIT
2744 || (i.prefix[ADDR_PREFIX] != 0))
2745 {
2746 i.rm.regmem = NO_BASE_REGISTER;
2747 i.types[op] &= ~Disp;
2748 i.types[op] |= Disp32;
2749 }
2750 else
2751 {
2752 /* 64bit mode overwrites the 32bit absolute
2753 addressing by RIP relative addressing and
2754 absolute addressing is encoded by one of the
2755 redundant SIB forms. */
2756 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2757 i.sib.base = NO_BASE_REGISTER;
2758 i.sib.index = NO_INDEX_REGISTER;
2759 i.types[op] &= ~Disp;
2760 i.types[op] |= Disp32S;
2761 }
2762 }
2763 else /* !i.base_reg && i.index_reg */
2764 {
2765 i.sib.index = i.index_reg->reg_num;
2766 i.sib.base = NO_BASE_REGISTER;
2767 i.sib.scale = i.log2_scale_factor;
2768 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2769 i.types[op] &= ~Disp;
2770 if (flag_code != CODE_64BIT)
2771 i.types[op] |= Disp32; /* Must be 32 bit */
2772 else
2773 i.types[op] |= Disp32S;
2774 if ((i.index_reg->reg_flags & RegRex) != 0)
2775 i.rex |= REX_EXTY;
2776 }
2777 }
2778 /* RIP addressing for 64bit mode. */
2779 else if (i.base_reg->reg_type == BaseIndex)
2780 {
2781 i.rm.regmem = NO_BASE_REGISTER;
2782 i.types[op] &= ~Disp;
2783 i.types[op] |= Disp32S;
2784 i.flags[op] = Operand_PCrel;
2785 }
2786 else if (i.base_reg->reg_type & Reg16)
2787 {
2788 switch (i.base_reg->reg_num)
2789 {
2790 case 3: /* (%bx) */
2791 if (i.index_reg == 0)
2792 i.rm.regmem = 7;
2793 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2794 i.rm.regmem = i.index_reg->reg_num - 6;
2795 break;
2796 case 5: /* (%bp) */
2797 default_seg = &ss;
2798 if (i.index_reg == 0)
2799 {
2800 i.rm.regmem = 6;
2801 if ((i.types[op] & Disp) == 0)
2802 {
2803 /* fake (%bp) into 0(%bp) */
2804 i.types[op] |= Disp8;
252b5132 2805 fake_zero_displacement = 1;
29b0f896
AM		 2806 }
2807 }
2808 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2809 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2810 break;
2811 default: /* (%si) -> 4 or (%di) -> 5 */
2812 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2813 }
2814 i.rm.mode = mode_from_disp_size (i.types[op]);
2815 }
2816 else /* i.base_reg and 32/64 bit mode */
2817 {
2818 if (flag_code == CODE_64BIT
2819 && (i.types[op] & Disp))
2820 {
2821 if (i.types[op] & Disp8)
2822 i.types[op] = Disp8 | Disp32S;
2823 else
2824 i.types[op] = Disp32S;
2825 }
2826 i.rm.regmem = i.base_reg->reg_num;
2827 if ((i.base_reg->reg_flags & RegRex) != 0)
2828 i.rex |= REX_EXTZ;
2829 i.sib.base = i.base_reg->reg_num;
2830 /* x86-64 ignores REX prefix bit here to avoid decoder
2831 complications. */
2832 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2833 {
2834 default_seg = &ss;
2835 if (i.disp_operands == 0)
2836 {
2837 fake_zero_displacement = 1;
2838 i.types[op] |= Disp8;
2839 }
2840 }
2841 else if (i.base_reg->reg_num == ESP_REG_NUM)
2842 {
2843 default_seg = &ss;
2844 }
2845 i.sib.scale = i.log2_scale_factor;
2846 if (i.index_reg == 0)
2847 {
2848 /* <disp>(%esp) becomes two byte modrm with no index
2849 register. We've already stored the code for esp
2850 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2851 Any base register besides %esp will not use the
2852 extra modrm byte. */
2853 i.sib.index = NO_INDEX_REGISTER;
2854#if !SCALE1_WHEN_NO_INDEX
2855 /* Another case where we force the second modrm byte. */
2856 if (i.log2_scale_factor)
2857 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2858#endif
29b0f896
AM		 2859 }
2860 else
2861 {
2862 i.sib.index = i.index_reg->reg_num;
2863 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2864 if ((i.index_reg->reg_flags & RegRex) != 0)
2865 i.rex |= REX_EXTY;
2866 }
2867 i.rm.mode = mode_from_disp_size (i.types[op]);
2868 }
252b5132 2869
29b0f896
AM		 2870 if (fake_zero_displacement)
2871 {
2872 /* Fakes a zero displacement assuming that i.types[op]
2873 holds the correct displacement size. */
2874 expressionS *exp;
2875
2876 assert (i.op[op].disps == 0);
2877 exp = &disp_expressions[i.disp_operands++];
2878 i.op[op].disps = exp;
2879 exp->X_op = O_constant;
2880 exp->X_add_number = 0;
2881 exp->X_add_symbol = (symbolS *) 0;
2882 exp->X_op_symbol = (symbolS *) 0;
2883 }
2884 }
252b5132 2885
29b0f896
AM		 2886 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2887 (if any) based on i.tm.extension_opcode. Again, we must be
2888 careful to make sure that segment/control/debug/test/MMX
2889 registers are coded into the i.rm.reg field. */
2890 if (i.reg_operands)
2891 {
2892 unsigned int op =
2893 ((i.types[0]
2894 & (Reg | RegMMX | RegXMM
2895 | SReg2 | SReg3
2896 | Control | Debug | Test))
2897 ? 0
2898 : ((i.types[1]
2899 & (Reg | RegMMX | RegXMM
2900 | SReg2 | SReg3
2901 | Control | Debug | Test))
2902 ? 1
2903 : 2));
2904 /* If there is an extension opcode to put here, the register
2905 number must be put into the regmem field. */
2906 if (i.tm.extension_opcode != None)
2907 {
2908 i.rm.regmem = i.op[op].regs->reg_num;
2909 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2910 i.rex |= REX_EXTZ;
2911 }
2912 else
2913 {
2914 i.rm.reg = i.op[op].regs->reg_num;
2915 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2916 i.rex |= REX_EXTX;
2917 }
252b5132 2918
29b0f896
AM		 2919 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2920 must set it to 3 to indicate this is a register operand
2921 in the regmem field. */
2922 if (!i.mem_operands)
2923 i.rm.mode = 3;
2924 }
252b5132 2925
29b0f896
AM		 2926 /* Fill in i.rm.reg field with extension opcode (if any). */
2927 if (i.tm.extension_opcode != None)
2928 i.rm.reg = i.tm.extension_opcode;
2929 }
2930 return default_seg;
2931}
252b5132 2932
29b0f896
AM		 2933static void
2934output_branch ()
2935{
2936 char *p;
2937 int code16;
2938 int prefix;
2939 relax_substateT subtype;
2940 symbolS *sym;
2941 offsetT off;
2942
2943 code16 = 0;
2944 if (flag_code == CODE_16BIT)
2945 code16 = CODE16;
2946
2947 prefix = 0;
2948 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2949 {
29b0f896
AM		 2950 prefix = 1;
2951 i.prefixes -= 1;
2952 code16 ^= CODE16;
252b5132 2953 }
29b0f896
AM		 2954 /* Pentium4 branch hints. */
2955 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2956 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2957 {
29b0f896
AM		 2958 prefix++;
2959 i.prefixes--;
2960 }
2961 if (i.prefix[REX_PREFIX] != 0)
2962 {
2963 prefix++;
2964 i.prefixes--;
2f66722d
AM		 2965 }
2966
29b0f896
AM		 2967 if (i.prefixes != 0 && !intel_syntax)
2968 as_warn (_("skipping prefixes on this instruction"));
2969
2970 /* It's always a symbol; End frag & setup for relax.
2971 Make sure there is enough room in this frag for the largest
2972 instruction we may generate in md_convert_frag. This is 2
2973 bytes for the opcode and room for the prefix and largest
2974 displacement. */
2975 frag_grow (prefix + 2 + 4);
2976 /* Prefix and 1 opcode byte go in fr_fix. */
2977 p = frag_more (prefix + 1);
2978 if (i.prefix[DATA_PREFIX] != 0)
2979 *p++ = DATA_PREFIX_OPCODE;
2980 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2981 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2982 *p++ = i.prefix[SEG_PREFIX];
2983 if (i.prefix[REX_PREFIX] != 0)
2984 *p++ = i.prefix[REX_PREFIX];
2985 *p = i.tm.base_opcode;
2986
2987 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2988 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2989 else if ((cpu_arch_flags & Cpu386) != 0)
2990 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2991 else
2992 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2993 subtype |= code16;
3e73aa7c 2994
29b0f896
AM		 2995 sym = i.op[0].disps->X_add_symbol;
2996 off = i.op[0].disps->X_add_number;
3e73aa7c 2997
29b0f896
AM		 2998 if (i.op[0].disps->X_op != O_constant
2999 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3000 {
29b0f896
AM		 3001 /* Handle complex expressions. */
3002 sym = make_expr_symbol (i.op[0].disps);
3003 off = 0;
3004 }
3e73aa7c 3005
29b0f896
AM		 3006 /* 1 possible extra opcode + 4 byte displacement go in var part.
3007 Pass reloc in fr_var. */
3008 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3009}
3e73aa7c 3010
29b0f896
AM		 3011static void
3012output_jump ()
3013{
3014 char *p;
3015 int size;
3e02c1cc 3016 fixS *fixP;
29b0f896
AM		 3017
3018 if (i.tm.opcode_modifier & JumpByte)
3019 {
3020 /* This is a loop or jecxz type instruction. */
3021 size = 1;
3022 if (i.prefix[ADDR_PREFIX] != 0)
3023 {
3024 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3025 i.prefixes -= 1;
3026 }
3027 /* Pentium4 branch hints. */
3028 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3029 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3030 {
3031 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3032 i.prefixes--;
3e73aa7c
JH		 3033 }
3034 }
29b0f896
AM		 3035 else
3036 {
3037 int code16;
3e73aa7c 3038
29b0f896
AM		 3039 code16 = 0;
3040 if (flag_code == CODE_16BIT)
3041 code16 = CODE16;
3e73aa7c 3042
29b0f896
AM		 3043 if (i.prefix[DATA_PREFIX] != 0)
3044 {
3045 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3046 i.prefixes -= 1;
3047 code16 ^= CODE16;
3048 }
252b5132 3049
29b0f896
AM		 3050 size = 4;
3051 if (code16)
3052 size = 2;
3053 }
9fcc94b6 3054
29b0f896
AM		 3055 if (i.prefix[REX_PREFIX] != 0)
3056 {
3057 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3058 i.prefixes -= 1;
3059 }
252b5132 3060
29b0f896
AM		 3061 if (i.prefixes != 0 && !intel_syntax)
3062 as_warn (_("skipping prefixes on this instruction"));
e0890092 3063
29b0f896
AM		 3064 p = frag_more (1 + size);
3065 *p++ = i.tm.base_opcode;
e0890092 3066
3e02c1cc
AM		 3067 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3068 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3069
3070 /* All jumps handled here are signed, but don't use a signed limit
3071 check for 32 and 16 bit jumps as we want to allow wrap around at
3072 4G and 64k respectively. */
3073 if (size == 1)
3074 fixP->fx_signed = 1;
29b0f896 3075}
e0890092 3076
29b0f896
AM		 3077static void
3078output_interseg_jump ()
3079{
3080 char *p;
3081 int size;
3082 int prefix;
3083 int code16;
252b5132 3084
29b0f896
AM		 3085 code16 = 0;
3086 if (flag_code == CODE_16BIT)
3087 code16 = CODE16;
a217f122 3088
29b0f896
AM		 3089 prefix = 0;
3090 if (i.prefix[DATA_PREFIX] != 0)
3091 {
3092 prefix = 1;
3093 i.prefixes -= 1;
3094 code16 ^= CODE16;
3095 }
3096 if (i.prefix[REX_PREFIX] != 0)
3097 {
3098 prefix++;
3099 i.prefixes -= 1;
3100 }
252b5132 3101
29b0f896
AM		 3102 size = 4;
3103 if (code16)
3104 size = 2;
252b5132 3105
29b0f896
AM		 3106 if (i.prefixes != 0 && !intel_syntax)
3107 as_warn (_("skipping prefixes on this instruction"));
252b5132 3108
29b0f896
AM		 3109 /* 1 opcode; 2 segment; offset */
3110 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3111
29b0f896
AM		 3112 if (i.prefix[DATA_PREFIX] != 0)
3113 *p++ = DATA_PREFIX_OPCODE;
252b5132 3114
29b0f896
AM		 3115 if (i.prefix[REX_PREFIX] != 0)
3116 *p++ = i.prefix[REX_PREFIX];
252b5132 3117
29b0f896
AM		 3118 *p++ = i.tm.base_opcode;
3119 if (i.op[1].imms->X_op == O_constant)
3120 {
3121 offsetT n = i.op[1].imms->X_add_number;
252b5132 3122
29b0f896
AM		 3123 if (size == 2
3124 && !fits_in_unsigned_word (n)
3125 && !fits_in_signed_word (n))
3126 {
3127 as_bad (_("16-bit jump out of range"));
3128 return;
3129 }
3130 md_number_to_chars (p, n, size);
3131 }
3132 else
3133 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3134 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3135 if (i.op[0].imms->X_op != O_constant)
3136 as_bad (_("can't handle non absolute segment in `%s'"),
3137 i.tm.name);
3138 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3139}
a217f122 3140
29b0f896
AM		 3141static void
3142output_insn ()
3143{
2bbd9c25
JJ		 3144 fragS *insn_start_frag;
3145 offsetT insn_start_off;
3146
29b0f896
AM		 3147 /* Tie dwarf2 debug info to the address at the start of the insn.
3148 We can't do this after the insn has been output as the current
3149 frag may have been closed off. eg. by frag_var. */
3150 dwarf2_emit_insn (0);
3151
2bbd9c25
JJ		 3152 insn_start_frag = frag_now;
3153 insn_start_off = frag_now_fix ();
3154
29b0f896
AM		 3155 /* Output jumps. */
3156 if (i.tm.opcode_modifier & Jump)
3157 output_branch ();
3158 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3159 output_jump ();
3160 else if (i.tm.opcode_modifier & JumpInterSegment)
3161 output_interseg_jump ();
3162 else
3163 {
3164 /* Output normal instructions here. */
3165 char *p;
3166 unsigned char *q;
252b5132 3167
0f10071e
ML		 3168 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3169 have 3 bytes. We may use one more higher byte to specify a prefix
3170 the instruction requires. */
3171 if ((i.tm.cpu_flags & CpuPadLock) != 0
3172 && (i.tm.base_opcode & 0xff000000) != 0)
3173 {
3174 unsigned int prefix;
3175 prefix = (i.tm.base_opcode >> 24) & 0xff;
3176
3177 if (prefix != REPE_PREFIX_OPCODE
3178 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3179 add_prefix (prefix);
3180 }
3181 else
3182 if ((i.tm.cpu_flags & CpuPadLock) == 0
3183 && (i.tm.base_opcode & 0xff0000) != 0)
3184 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3185
29b0f896
AM		 3186 /* The prefix bytes. */
3187 for (q = i.prefix;
3188 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3189 q++)
3190 {
3191 if (*q)
3192 {
3193 p = frag_more (1);
3194 md_number_to_chars (p, (valueT) *q, 1);
3195 }
3196 }
252b5132 3197
29b0f896
AM		 3198 /* Now the opcode; be careful about word order here! */
3199 if (fits_in_unsigned_byte (i.tm.base_opcode))
3200 {
3201 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3202 }
3203 else
3204 {
0f10071e
ML		 3205 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3206 {
3207 p = frag_more (3);
3208 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3209 }
3210 else
3211 p = frag_more (2);
3212
29b0f896
AM		 3213 /* Put out high byte first: can't use md_number_to_chars! */
3214 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3215 *p = i.tm.base_opcode & 0xff;
3216 }
3e73aa7c 3217
29b0f896
AM		 3218 /* Now the modrm byte and sib byte (if present). */
3219 if (i.tm.opcode_modifier & Modrm)
3220 {
3221 p = frag_more (1);
3222 md_number_to_chars (p,
3223 (valueT) (i.rm.regmem << 0
3224 | i.rm.reg << 3
3225 | i.rm.mode << 6),
3226 1);
3227 /* If i.rm.regmem == ESP (4)
3228 && i.rm.mode != (Register mode)
3229 && not 16 bit
3230 ==> need second modrm byte. */
3231 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3232 && i.rm.mode != 3
3233 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3234 {
3235 p = frag_more (1);
3236 md_number_to_chars (p,
3237 (valueT) (i.sib.base << 0
3238 | i.sib.index << 3
3239 | i.sib.scale << 6),
3240 1);
3241 }
3242 }
3e73aa7c 3243
29b0f896 3244 if (i.disp_operands)
2bbd9c25 3245 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3246
29b0f896 3247 if (i.imm_operands)
2bbd9c25 3248 output_imm (insn_start_frag, insn_start_off);
29b0f896 3249 }
252b5132 3250
29b0f896
AM		 3251#ifdef DEBUG386
3252 if (flag_debug)
3253 {
3254 pi (line, &i);
3255 }
3256#endif /* DEBUG386 */
3257}
252b5132 3258
29b0f896 3259static void
2bbd9c25
JJ		 3260output_disp (insn_start_frag, insn_start_off)
3261 fragS *insn_start_frag;
3262 offsetT insn_start_off;
29b0f896
AM		 3263{
3264 char *p;
3265 unsigned int n;
252b5132 3266
29b0f896
AM		 3267 for (n = 0; n < i.operands; n++)
3268 {
3269 if (i.types[n] & Disp)
3270 {
3271 if (i.op[n].disps->X_op == O_constant)
3272 {
3273 int size;
3274 offsetT val;
252b5132 3275
29b0f896
AM		 3276 size = 4;
3277 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3278 {
3279 size = 2;
3280 if (i.types[n] & Disp8)
3281 size = 1;
3282 if (i.types[n] & Disp64)
3283 size = 8;
3284 }
3285 val = offset_in_range (i.op[n].disps->X_add_number,
3286 size);
3287 p = frag_more (size);
3288 md_number_to_chars (p, val, size);
3289 }
3290 else
3291 {
f86103b7 3292 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3293 int size = 4;
3294 int sign = 0;
3295 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3296
3297 /* The PC relative address is computed relative
3298 to the instruction boundary, so in case immediate
3299 fields follows, we need to adjust the value. */
3300 if (pcrel && i.imm_operands)
3301 {
3302 int imm_size = 4;
3303 unsigned int n1;
252b5132 3304
29b0f896
AM		 3305 for (n1 = 0; n1 < i.operands; n1++)
3306 if (i.types[n1] & Imm)
252b5132 3307 {
29b0f896 3308 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3309 {
29b0f896
AM		 3310 imm_size = 2;
3311 if (i.types[n1] & (Imm8 | Imm8S))
3312 imm_size = 1;
3313 if (i.types[n1] & Imm64)
3314 imm_size = 8;
252b5132 3315 }
29b0f896 3316 break;
252b5132 3317 }
29b0f896
AM		 3318 /* We should find the immediate. */
3319 if (n1 == i.operands)
3320 abort ();
3321 i.op[n].disps->X_add_number -= imm_size;
3322 }
520dc8e8 3323
29b0f896
AM		 3324 if (i.types[n] & Disp32S)
3325 sign = 1;
3e73aa7c 3326
29b0f896
AM		 3327 if (i.types[n] & (Disp16 | Disp64))
3328 {
3329 size = 2;
3330 if (i.types[n] & Disp64)
3331 size = 8;
3332 }
520dc8e8 3333
29b0f896 3334 p = frag_more (size);
2bbd9c25 3335 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
2bbd9c25
JJ		 3336 if (reloc_type == BFD_RELOC_32
3337 && GOT_symbol
3338 && GOT_symbol == i.op[n].disps->X_add_symbol
3339 && (i.op[n].disps->X_op == O_symbol
3340 || (i.op[n].disps->X_op == O_add
3341 && ((symbol_get_value_expression
3342 (i.op[n].disps->X_op_symbol)->X_op)
3343 == O_subtract))))
3344 {
3345 offsetT add;
3346
3347 if (insn_start_frag == frag_now)
3348 add = (p - frag_now->fr_literal) - insn_start_off;
3349 else
3350 {
3351 fragS *fr;
3352
3353 add = insn_start_frag->fr_fix - insn_start_off;
3354 for (fr = insn_start_frag->fr_next;
3355 fr && fr != frag_now; fr = fr->fr_next)
3356 add += fr->fr_fix;
3357 add += p - frag_now->fr_literal;
3358 }
3359
3360 /* We don't support dynamic linking on x86-64 yet. */
3361 if (flag_code == CODE_64BIT)
3362 abort ();
3363 reloc_type = BFD_RELOC_386_GOTPC;
3364 i.op[n].disps->X_add_number += add;
3365 }
062cd5e7 3366 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3367 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3368 }
3369 }
3370 }
3371}
252b5132 3372
29b0f896 3373static void
2bbd9c25
JJ		 3374output_imm (insn_start_frag, insn_start_off)
3375 fragS *insn_start_frag;
3376 offsetT insn_start_off;
29b0f896
AM		 3377{
3378 char *p;
3379 unsigned int n;
252b5132 3380
29b0f896
AM		 3381 for (n = 0; n < i.operands; n++)
3382 {
3383 if (i.types[n] & Imm)
3384 {
3385 if (i.op[n].imms->X_op == O_constant)
3386 {
3387 int size;
3388 offsetT val;
b4cac588 3389
29b0f896
AM		 3390 size = 4;
3391 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3392 {
3393 size = 2;
3394 if (i.types[n] & (Imm8 | Imm8S))
3395 size = 1;
3396 else if (i.types[n] & Imm64)
3397 size = 8;
3398 }
3399 val = offset_in_range (i.op[n].imms->X_add_number,
3400 size);
3401 p = frag_more (size);
3402 md_number_to_chars (p, val, size);
3403 }
3404 else
3405 {
3406 /* Not absolute_section.
3407 Need a 32-bit fixup (don't support 8bit
3408 non-absolute imms). Try to support other
3409 sizes ... */
f86103b7 3410 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3411 int size = 4;
3412 int sign = 0;
3413
3414 if ((i.types[n] & (Imm32S))
3415 && i.suffix == QWORD_MNEM_SUFFIX)
3416 sign = 1;
3417 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3418 {
3419 size = 2;
3420 if (i.types[n] & (Imm8 | Imm8S))
3421 size = 1;
3422 if (i.types[n] & Imm64)
3423 size = 8;
3424 }
520dc8e8 3425
29b0f896
AM		 3426 p = frag_more (size);
3427 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3428
2bbd9c25
JJ		 3429 /* This is tough to explain. We end up with this one if we
3430 * have operands that look like
3431 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3432 * obtain the absolute address of the GOT, and it is strongly
3433 * preferable from a performance point of view to avoid using
3434 * a runtime relocation for this. The actual sequence of
3435 * instructions often look something like:
3436 *
3437 * call .L66
3438 * .L66:
3439 * popl %ebx
3440 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3441 *
3442 * The call and pop essentially return the absolute address
3443 * of the label .L66 and store it in %ebx. The linker itself
3444 * will ultimately change the first operand of the addl so
3445 * that %ebx points to the GOT, but to keep things simple, the
3446 * .o file must have this operand set so that it generates not
3447 * the absolute address of .L66, but the absolute address of
3448 * itself. This allows the linker itself simply treat a GOTPC
3449 * relocation as asking for a pcrel offset to the GOT to be
3450 * added in, and the addend of the relocation is stored in the
3451 * operand field for the instruction itself.
3452 *
3453 * Our job here is to fix the operand so that it would add
3454 * the correct offset so that %ebx would point to itself. The
3455 * thing that is tricky is that .-.L66 will point to the
3456 * beginning of the instruction, so we need to further modify
3457 * the operand so that it will point to itself. There are
3458 * other cases where you have something like:
3459 *
3460 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3461 *
3462 * and here no correction would be required. Internally in
3463 * the assembler we treat operands of this form as not being
3464 * pcrel since the '.' is explicitly mentioned, and I wonder
3465 * whether it would simplify matters to do it this way. Who
3466 * knows. In earlier versions of the PIC patches, the
3467 * pcrel_adjust field was used to store the correction, but
3468 * since the expression is not pcrel, I felt it would be
3469 * confusing to do it this way. */
3470
29b0f896
AM		 3471 if (reloc_type == BFD_RELOC_32
3472 && GOT_symbol
3473 && GOT_symbol == i.op[n].imms->X_add_symbol
3474 && (i.op[n].imms->X_op == O_symbol
3475 || (i.op[n].imms->X_op == O_add
3476 && ((symbol_get_value_expression
3477 (i.op[n].imms->X_op_symbol)->X_op)
3478 == O_subtract))))
3479 {
2bbd9c25
JJ		 3480 offsetT add;
3481
3482 if (insn_start_frag == frag_now)
3483 add = (p - frag_now->fr_literal) - insn_start_off;
3484 else
3485 {
3486 fragS *fr;
3487
3488 add = insn_start_frag->fr_fix - insn_start_off;
3489 for (fr = insn_start_frag->fr_next;
3490 fr && fr != frag_now; fr = fr->fr_next)
3491 add += fr->fr_fix;
3492 add += p - frag_now->fr_literal;
3493 }
3494
29b0f896
AM		 3495 /* We don't support dynamic linking on x86-64 yet. */
3496 if (flag_code == CODE_64BIT)
3497 abort ();
3498 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3499 i.op[n].imms->X_add_number += add;
29b0f896 3500 }
29b0f896
AM		 3501 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3502 i.op[n].imms, 0, reloc_type);
3503 }
3504 }
3505 }
252b5132
RH		 3506}
3507\f
f3c180ae 3508#ifndef LEX_AT
f86103b7 3509static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
f3c180ae
AM		 3510
3511/* Parse operands of the form
3512 <symbol>@GOTOFF+<nnn>
3513 and similar .plt or .got references.
3514
3515 If we find one, set up the correct relocation in RELOC and copy the
3516 input string, minus the `@GOTOFF' into a malloc'd buffer for
3517 parsing by the calling routine. Return this buffer, and if ADJUST
3518 is non-null set it to the length of the string we removed from the
3519 input line. Otherwise return NULL. */
3520static char *
3521lex_got (reloc, adjust)
f86103b7 3522 enum bfd_reloc_code_real *reloc;
f3c180ae
AM		 3523 int *adjust;
3524{
3525 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3526 static const struct {
3527 const char *str;
f86103b7 3528 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
f3c180ae 3529 } gotrel[] = {
13ae64f3
JJ		 3530 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3531 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3532 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3533 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3534 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3535 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3536 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3537 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3538 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3539 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3540 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3541 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3542 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3543 };
3544 char *cp;
3545 unsigned int j;
3546
3547 for (cp = input_line_pointer; *cp != '@'; cp++)
3548 if (is_end_of_line[(unsigned char) *cp])
3549 return NULL;
3550
3551 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3552 {
3553 int len;
3554
3555 len = strlen (gotrel[j].str);
28f81592 3556 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3557 {
3558 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3559 {
28f81592
AM		 3560 int first, second;
3561 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3562
3563 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3564 if (adjust)
3565 *adjust = len;
f3c180ae
AM		 3566
3567 if (GOT_symbol == NULL)
3568 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3569
3570 /* Replace the relocation token with ' ', so that
3571 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3572
3573 /* The length of the first part of our input line. */
f3c180ae 3574 first = cp - input_line_pointer;
28f81592
AM		 3575
3576 /* The second part goes from after the reloc token until
3577 (and including) an end_of_line char. Don't use strlen
3578 here as the end_of_line char may not be a NUL. */
3579 past_reloc = cp + 1 + len;
3580 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3581 ;
3582 second = cp - past_reloc;
3583
3584 /* Allocate and copy string. The trailing NUL shouldn't
3585 be necessary, but be safe. */
3586 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3587 memcpy (tmpbuf, input_line_pointer, first);
3588 tmpbuf[first] = ' ';
28f81592
AM		 3589 memcpy (tmpbuf + first + 1, past_reloc, second);
3590 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3591 return tmpbuf;
3592 }
3593
3594 as_bad (_("@%s reloc is not supported in %s bit mode"),
3595 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3596 return NULL;
3597 }
3598 }
3599
3600 /* Might be a symbol version string. Don't as_bad here. */
3601 return NULL;
3602}
3603
3604/* x86_cons_fix_new is called via the expression parsing code when a
3605 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3606static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3607
3608void
3609x86_cons_fix_new (frag, off, len, exp)
3610 fragS *frag;
3611 unsigned int off;
3612 unsigned int len;
3613 expressionS *exp;
3614{
f86103b7 3615 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
f3c180ae
AM		 3616 got_reloc = NO_RELOC;
3617 fix_new_exp (frag, off, len, exp, 0, r);
3618}
3619
3620void
3621x86_cons (exp, size)
3622 expressionS *exp;
3623 int size;
3624{
3625 if (size == 4)
3626 {
3627 /* Handle @GOTOFF and the like in an expression. */
3628 char *save;
3629 char *gotfree_input_line;
3630 int adjust;
3631
3632 save = input_line_pointer;
3633 gotfree_input_line = lex_got (&got_reloc, &adjust);
3634 if (gotfree_input_line)
3635 input_line_pointer = gotfree_input_line;
3636
3637 expression (exp);
3638
3639 if (gotfree_input_line)
3640 {
3641 /* expression () has merrily parsed up to the end of line,
3642 or a comma - in the wrong buffer. Transfer how far
3643 input_line_pointer has moved to the right buffer. */
3644 input_line_pointer = (save
3645 + (input_line_pointer - gotfree_input_line)
3646 + adjust);
3647 free (gotfree_input_line);
3648 }
3649 }
3650 else
3651 expression (exp);
3652}
3653#endif
3654
6482c264
NC		 3655#ifdef TE_PE
3656
3657#define O_secrel (O_max + 1)
3658
3659void
3660x86_pe_cons_fix_new (frag, off, len, exp)
3661 fragS *frag;
3662 unsigned int off;
3663 unsigned int len;
3664 expressionS *exp;
3665{
3666 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3667
3668 if (exp->X_op == O_secrel)
3669 {
3670 exp->X_op = O_symbol;
3671 r = BFD_RELOC_32_SECREL;
3672 }
3673
3674 fix_new_exp (frag, off, len, exp, 0, r);
3675}
3676
3677static void
3678pe_directive_secrel (dummy)
3679 int dummy ATTRIBUTE_UNUSED;
3680{
3681 expressionS exp;
3682
3683 do
3684 {
3685 expression (&exp);
3686 if (exp.X_op == O_symbol)
3687 exp.X_op = O_secrel;
3688
3689 emit_expr (&exp, 4);
3690 }
3691 while (*input_line_pointer++ == ',');
3692
3693 input_line_pointer--;
3694 demand_empty_rest_of_line ();
3695}
3696
3697#endif
3698
252b5132
RH		 3699static int i386_immediate PARAMS ((char *));
3700
3701static int
3702i386_immediate (imm_start)
3703 char *imm_start;
3704{
3705 char *save_input_line_pointer;
f3c180ae
AM		 3706#ifndef LEX_AT
3707 char *gotfree_input_line;
3708#endif
252b5132 3709 segT exp_seg = 0;
47926f60 3710 expressionS *exp;
252b5132
RH		 3711
3712 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3713 {
d0b47220 3714 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3715 return 0;
3716 }
3717
3718 exp = &im_expressions[i.imm_operands++];
520dc8e8 3719 i.op[this_operand].imms = exp;
252b5132
RH		 3720
3721 if (is_space_char (*imm_start))
3722 ++imm_start;
3723
3724 save_input_line_pointer = input_line_pointer;
3725 input_line_pointer = imm_start;
3726
3727#ifndef LEX_AT
f3c180ae
AM		 3728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3729 if (gotfree_input_line)
3730 input_line_pointer = gotfree_input_line;
252b5132
RH		 3731#endif
3732
3733 exp_seg = expression (exp);
3734
83183c0c 3735 SKIP_WHITESPACE ();
252b5132 3736 if (*input_line_pointer)
f3c180ae 3737 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3738
3739 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3740#ifndef LEX_AT
3741 if (gotfree_input_line)
3742 free (gotfree_input_line);
3743#endif
252b5132 3744
2daf4fd8 3745 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3746 {
47926f60 3747 /* Missing or bad expr becomes absolute 0. */
d0b47220 3748 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3749 imm_start);
252b5132
RH		 3750 exp->X_op = O_constant;
3751 exp->X_add_number = 0;
3752 exp->X_add_symbol = (symbolS *) 0;
3753 exp->X_op_symbol = (symbolS *) 0;
252b5132 3754 }
3e73aa7c 3755 else if (exp->X_op == O_constant)
252b5132 3756 {
47926f60 3757 /* Size it properly later. */
3e73aa7c
JH		 3758 i.types[this_operand] |= Imm64;
3759 /* If BFD64, sign extend val. */
3760 if (!use_rela_relocations)
3761 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3762 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3763 }
4c63da97 3764#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 3765 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3766 && exp_seg != absolute_section
47926f60 3767 && exp_seg != text_section
24eab124
AM		 3768 && exp_seg != data_section
3769 && exp_seg != bss_section
3770 && exp_seg != undefined_section
f86103b7 3771 && !bfd_is_com_section (exp_seg))
252b5132 3772 {
d0b47220 3773 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 3774 return 0;
3775 }
3776#endif
3777 else
3778 {
3779 /* This is an address. The size of the address will be
24eab124 3780 determined later, depending on destination register,
3e73aa7c
JH		 3781 suffix, or the default for the section. */
3782 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3783 }
3784
3785 return 1;
3786}
3787
551c1ca1 3788static char *i386_scale PARAMS ((char *));
252b5132 3789
551c1ca1 3790static char *
252b5132
RH		 3791i386_scale (scale)
3792 char *scale;
3793{
551c1ca1
AM		 3794 offsetT val;
3795 char *save = input_line_pointer;
252b5132 3796
551c1ca1
AM		 3797 input_line_pointer = scale;
3798 val = get_absolute_expression ();
3799
3800 switch (val)
252b5132 3801 {
551c1ca1
AM		 3802 case 0:
3803 case 1:
252b5132
RH		 3804 i.log2_scale_factor = 0;
3805 break;
551c1ca1 3806 case 2:
252b5132
RH		 3807 i.log2_scale_factor = 1;
3808 break;
551c1ca1 3809 case 4:
252b5132
RH		 3810 i.log2_scale_factor = 2;
3811 break;
551c1ca1 3812 case 8:
252b5132
RH		 3813 i.log2_scale_factor = 3;
3814 break;
3815 default:
252b5132 3816 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3817 scale);
551c1ca1
AM		 3818 input_line_pointer = save;
3819 return NULL;
252b5132 3820 }
29b0f896 3821 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3822 {
3823 as_warn (_("scale factor of %d without an index register"),
24eab124 3824 1 << i.log2_scale_factor);
252b5132
RH		 3825#if SCALE1_WHEN_NO_INDEX
3826 i.log2_scale_factor = 0;
3827#endif
3828 }
551c1ca1
AM		 3829 scale = input_line_pointer;
3830 input_line_pointer = save;
3831 return scale;
252b5132
RH		 3832}
3833
3834static int i386_displacement PARAMS ((char *, char *));
3835
3836static int
3837i386_displacement (disp_start, disp_end)
3838 char *disp_start;
3839 char *disp_end;
3840{
29b0f896 3841 expressionS *exp;
252b5132
RH		 3842 segT exp_seg = 0;
3843 char *save_input_line_pointer;
f3c180ae
AM		 3844#ifndef LEX_AT
3845 char *gotfree_input_line;
3846#endif
252b5132
RH		 3847 int bigdisp = Disp32;
3848
3e73aa7c 3849 if (flag_code == CODE_64BIT)
7ecd2f8b 3850 {
29b0f896
AM		 3851 if (i.prefix[ADDR_PREFIX] == 0)
3852 bigdisp = Disp64;
7ecd2f8b
JH		 3853 }
3854 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3855 bigdisp = Disp16;
252b5132
RH		 3856 i.types[this_operand] |= bigdisp;
3857
3858 exp = &disp_expressions[i.disp_operands];
520dc8e8 3859 i.op[this_operand].disps = exp;
252b5132
RH		 3860 i.disp_operands++;
3861 save_input_line_pointer = input_line_pointer;
3862 input_line_pointer = disp_start;
3863 END_STRING_AND_SAVE (disp_end);
3864
3865#ifndef GCC_ASM_O_HACK
3866#define GCC_ASM_O_HACK 0
3867#endif
3868#if GCC_ASM_O_HACK
3869 END_STRING_AND_SAVE (disp_end + 1);
3870 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3871 && displacement_string_end[-1] == '+')
252b5132
RH		 3872 {
3873 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3874 constraint within gcc asm statements.
3875 For instance:
3876
3877 #define _set_tssldt_desc(n,addr,limit,type) \
3878 __asm__ __volatile__ ( \
3879 "movw %w2,%0\n\t" \
3880 "movw %w1,2+%0\n\t" \
3881 "rorl $16,%1\n\t" \
3882 "movb %b1,4+%0\n\t" \
3883 "movb %4,5+%0\n\t" \
3884 "movb $0,6+%0\n\t" \
3885 "movb %h1,7+%0\n\t" \
3886 "rorl $16,%1" \
3887 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3888
3889 This works great except that the output assembler ends
3890 up looking a bit weird if it turns out that there is
3891 no offset. You end up producing code that looks like:
3892
3893 #APP
3894 movw $235,(%eax)
3895 movw %dx,2+(%eax)
3896 rorl $16,%edx
3897 movb %dl,4+(%eax)
3898 movb $137,5+(%eax)
3899 movb $0,6+(%eax)
3900 movb %dh,7+(%eax)
3901 rorl $16,%edx
3902 #NO_APP
3903
47926f60 3904 So here we provide the missing zero. */
24eab124
AM		 3905
3906 *displacement_string_end = '0';
252b5132
RH		 3907 }
3908#endif
3909#ifndef LEX_AT
f3c180ae
AM		 3910 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3911 if (gotfree_input_line)
3912 input_line_pointer = gotfree_input_line;
252b5132
RH		 3913#endif
3914
24eab124 3915 exp_seg = expression (exp);
252b5132 3916
636c26b0
AM		 3917 SKIP_WHITESPACE ();
3918 if (*input_line_pointer)
3919 as_bad (_("junk `%s' after expression"), input_line_pointer);
3920#if GCC_ASM_O_HACK
3921 RESTORE_END_STRING (disp_end + 1);
3922#endif
3923 RESTORE_END_STRING (disp_end);
3924 input_line_pointer = save_input_line_pointer;
3925#ifndef LEX_AT
3926 if (gotfree_input_line)
3927 free (gotfree_input_line);
3928#endif
3929
24eab124
AM		 3930 /* We do this to make sure that the section symbol is in
3931 the symbol table. We will ultimately change the relocation
47926f60 3932 to be relative to the beginning of the section. */
1ae12ab7
AM		 3933 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3934 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3935 {
636c26b0
AM		 3936 if (exp->X_op != O_symbol)
3937 {
3938 as_bad (_("bad expression used with @%s"),
3939 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3940 ? "GOTPCREL"
3941 : "GOTOFF"));
3942 return 0;
3943 }
3944
e5cb08ac 3945 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3946 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3947 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3948 exp->X_op = O_subtract;
3949 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3950 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3951 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3952 else
29b0f896 3953 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3954 }
252b5132 3955
2daf4fd8
AM		 3956 if (exp->X_op == O_absent || exp->X_op == O_big)
3957 {
47926f60 3958 /* Missing or bad expr becomes absolute 0. */
d0b47220 3959 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3960 disp_start);
3961 exp->X_op = O_constant;
3962 exp->X_add_number = 0;
3963 exp->X_add_symbol = (symbolS *) 0;
3964 exp->X_op_symbol = (symbolS *) 0;
3965 }
3966
4c63da97 3967#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3968 if (exp->X_op != O_constant
45288df1 3969 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3970 && exp_seg != absolute_section
45288df1
AM		 3971 && exp_seg != text_section
3972 && exp_seg != data_section
3973 && exp_seg != bss_section
31312f95 3974 && exp_seg != undefined_section
f86103b7 3975 && !bfd_is_com_section (exp_seg))
24eab124 3976 {
d0b47220 3977 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 3978 return 0;
3979 }
252b5132 3980#endif
3e73aa7c
JH		 3981 else if (flag_code == CODE_64BIT)
3982 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3983 return 1;
3984}
3985
e5cb08ac 3986static int i386_index_check PARAMS ((const char *));
252b5132 3987
eecb386c 3988/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3989 Return 1 on success, 0 on a failure. */
3990
252b5132 3991static int
eecb386c
AM		 3992i386_index_check (operand_string)
3993 const char *operand_string;
252b5132 3994{
3e73aa7c 3995 int ok;
24eab124 3996#if INFER_ADDR_PREFIX
eecb386c
AM		 3997 int fudged = 0;
3998
24eab124
AM		 3999 tryprefix:
4000#endif
3e73aa7c
JH		 4001 ok = 1;
4002 if (flag_code == CODE_64BIT)
4003 {
7ecd2f8b
JH		 4004 if (i.prefix[ADDR_PREFIX] == 0)
4005 {
4006 /* 64bit checks. */
4007 if ((i.base_reg
4008 && ((i.base_reg->reg_type & Reg64) == 0)
4009 && (i.base_reg->reg_type != BaseIndex
4010 || i.index_reg))
4011 || (i.index_reg
29b0f896
AM		 4012 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
4013 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 4014 ok = 0;
4015 }
4016 else
4017 {
4018 /* 32bit checks. */
4019 if ((i.base_reg
4020 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4021 || (i.index_reg
29b0f896
AM		 4022 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4023 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 4024 ok = 0;
4025 }
3e73aa7c
JH		 4026 }
4027 else
4028 {
4029 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4030 {
4031 /* 16bit checks. */
4032 if ((i.base_reg
29b0f896
AM		 4033 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4034 != (Reg16 | BaseIndex)))
3e73aa7c 4035 || (i.index_reg
29b0f896
AM		 4036 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4037 != (Reg16 | BaseIndex))
4038 || !(i.base_reg
4039 && i.base_reg->reg_num < 6
4040 && i.index_reg->reg_num >= 6
4041 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4042 ok = 0;
4043 }
4044 else
e5cb08ac 4045 {
3e73aa7c
JH		 4046 /* 32bit checks. */
4047 if ((i.base_reg
4048 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4049 || (i.index_reg
29b0f896
AM		 4050 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4051 != (Reg32 | BaseIndex))))
e5cb08ac 4052 ok = 0;
3e73aa7c
JH		 4053 }
4054 }
4055 if (!ok)
24eab124
AM		 4056 {
4057#if INFER_ADDR_PREFIX
3e73aa7c
JH		 4058 if (flag_code != CODE_64BIT
4059 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 4060 {
4061 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4062 i.prefixes += 1;
b23bac36
AM		 4063 /* Change the size of any displacement too. At most one of
4064 Disp16 or Disp32 is set.
4065 FIXME. There doesn't seem to be any real need for separate
4066 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4067 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 4068 if (i.types[this_operand] & (Disp16 | Disp32))
4069 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4070 fudged = 1;
24eab124
AM		 4071 goto tryprefix;
4072 }
eecb386c
AM		 4073 if (fudged)
4074 as_bad (_("`%s' is not a valid base/index expression"),
4075 operand_string);
4076 else
c388dee8 4077#endif
eecb386c
AM		 4078 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4079 operand_string,
3e73aa7c 4080 flag_code_names[flag_code]);
eecb386c 4081 return 0;
24eab124
AM		 4082 }
4083 return 1;
4084}
252b5132 4085
252b5132 4086/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4087 on error. */
252b5132 4088
252b5132
RH		 4089static int
4090i386_operand (operand_string)
4091 char *operand_string;
4092{
af6bdddf
AM		 4093 const reg_entry *r;
4094 char *end_op;
24eab124 4095 char *op_string = operand_string;
252b5132 4096
24eab124 4097 if (is_space_char (*op_string))
252b5132
RH		 4098 ++op_string;
4099
24eab124 4100 /* We check for an absolute prefix (differentiating,
47926f60 4101 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4102 if (*op_string == ABSOLUTE_PREFIX)
4103 {
4104 ++op_string;
4105 if (is_space_char (*op_string))
4106 ++op_string;
4107 i.types[this_operand] |= JumpAbsolute;
4108 }
252b5132 4109
47926f60 4110 /* Check if operand is a register. */
af6bdddf
AM		 4111 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4112 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4113 {
24eab124
AM		 4114 /* Check for a segment override by searching for ':' after a
4115 segment register. */
4116 op_string = end_op;
4117 if (is_space_char (*op_string))
4118 ++op_string;
4119 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4120 {
4121 switch (r->reg_num)
4122 {
4123 case 0:
4124 i.seg[i.mem_operands] = &es;
4125 break;
4126 case 1:
4127 i.seg[i.mem_operands] = &cs;
4128 break;
4129 case 2:
4130 i.seg[i.mem_operands] = &ss;
4131 break;
4132 case 3:
4133 i.seg[i.mem_operands] = &ds;
4134 break;
4135 case 4:
4136 i.seg[i.mem_operands] = &fs;
4137 break;
4138 case 5:
4139 i.seg[i.mem_operands] = &gs;
4140 break;
4141 }
252b5132 4142
24eab124 4143 /* Skip the ':' and whitespace. */
252b5132
RH		 4144 ++op_string;
4145 if (is_space_char (*op_string))
24eab124 4146 ++op_string;
252b5132 4147
24eab124
AM		 4148 if (!is_digit_char (*op_string)
4149 && !is_identifier_char (*op_string)
4150 && *op_string != '('
4151 && *op_string != ABSOLUTE_PREFIX)
4152 {
4153 as_bad (_("bad memory operand `%s'"), op_string);
4154 return 0;
4155 }
47926f60 4156 /* Handle case of %es:*foo. */
24eab124
AM		 4157 if (*op_string == ABSOLUTE_PREFIX)
4158 {
4159 ++op_string;
4160 if (is_space_char (*op_string))
4161 ++op_string;
4162 i.types[this_operand] |= JumpAbsolute;
4163 }
4164 goto do_memory_reference;
4165 }
4166 if (*op_string)
4167 {
d0b47220 4168 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4169 return 0;
4170 }
4171 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4172 i.op[this_operand].regs = r;
24eab124
AM		 4173 i.reg_operands++;
4174 }
af6bdddf
AM		 4175 else if (*op_string == REGISTER_PREFIX)
4176 {
4177 as_bad (_("bad register name `%s'"), op_string);
4178 return 0;
4179 }
24eab124 4180 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4181 {
24eab124
AM		 4182 ++op_string;
4183 if (i.types[this_operand] & JumpAbsolute)
4184 {
d0b47220 4185 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4186 return 0;
4187 }
4188 if (!i386_immediate (op_string))
4189 return 0;
4190 }
4191 else if (is_digit_char (*op_string)
4192 || is_identifier_char (*op_string)
e5cb08ac 4193 || *op_string == '(')
24eab124 4194 {
47926f60 4195 /* This is a memory reference of some sort. */
af6bdddf 4196 char *base_string;
252b5132 4197
47926f60 4198 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4199 char *displacement_string_start;
4200 char *displacement_string_end;
252b5132 4201
24eab124 4202 do_memory_reference:
24eab124
AM		 4203 if ((i.mem_operands == 1
4204 && (current_templates->start->opcode_modifier & IsString) == 0)
4205 || i.mem_operands == 2)
4206 {
4207 as_bad (_("too many memory references for `%s'"),
4208 current_templates->start->name);
4209 return 0;
4210 }
252b5132 4211
24eab124
AM		 4212 /* Check for base index form. We detect the base index form by
4213 looking for an ')' at the end of the operand, searching
4214 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4215 after the '('. */
af6bdddf 4216 base_string = op_string + strlen (op_string);
c3332e24 4217
af6bdddf
AM		 4218 --base_string;
4219 if (is_space_char (*base_string))
4220 --base_string;
252b5132 4221
47926f60 4222 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4223 displacement_string_start = op_string;
4224 displacement_string_end = base_string + 1;
252b5132 4225
24eab124
AM		 4226 if (*base_string == ')')
4227 {
af6bdddf 4228 char *temp_string;
24eab124
AM		 4229 unsigned int parens_balanced = 1;
4230 /* We've already checked that the number of left & right ()'s are
47926f60 4231 equal, so this loop will not be infinite. */
24eab124
AM		 4232 do
4233 {
4234 base_string--;
4235 if (*base_string == ')')
4236 parens_balanced++;
4237 if (*base_string == '(')
4238 parens_balanced--;
4239 }
4240 while (parens_balanced);
c3332e24 4241
af6bdddf 4242 temp_string = base_string;
c3332e24 4243
24eab124 4244 /* Skip past '(' and whitespace. */
252b5132
RH		 4245 ++base_string;
4246 if (is_space_char (*base_string))
24eab124 4247 ++base_string;
252b5132 4248
af6bdddf
AM		 4249 if (*base_string == ','
4250 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4251 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4252 {
af6bdddf 4253 displacement_string_end = temp_string;
252b5132 4254
af6bdddf 4255 i.types[this_operand] |= BaseIndex;
252b5132 4256
af6bdddf 4257 if (i.base_reg)
24eab124 4258 {
24eab124
AM		 4259 base_string = end_op;
4260 if (is_space_char (*base_string))
4261 ++base_string;
af6bdddf
AM		 4262 }
4263
4264 /* There may be an index reg or scale factor here. */
4265 if (*base_string == ',')
4266 {
4267 ++base_string;
4268 if (is_space_char (*base_string))
4269 ++base_string;
4270
4271 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4272 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4273 {
af6bdddf 4274 base_string = end_op;
24eab124
AM		 4275 if (is_space_char (*base_string))
4276 ++base_string;
af6bdddf
AM		 4277 if (*base_string == ',')
4278 {
4279 ++base_string;
4280 if (is_space_char (*base_string))
4281 ++base_string;
4282 }
e5cb08ac 4283 else if (*base_string != ')')
af6bdddf
AM		 4284 {
4285 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4286 operand_string);
4287 return 0;
4288 }
24eab124 4289 }
af6bdddf 4290 else if (*base_string == REGISTER_PREFIX)
24eab124 4291 {
af6bdddf 4292 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4293 return 0;
4294 }
252b5132 4295
47926f60 4296 /* Check for scale factor. */
551c1ca1 4297 if (*base_string != ')')
af6bdddf 4298 {
551c1ca1
AM		 4299 char *end_scale = i386_scale (base_string);
4300
4301 if (!end_scale)
af6bdddf 4302 return 0;
24eab124 4303
551c1ca1 4304 base_string = end_scale;
af6bdddf
AM		 4305 if (is_space_char (*base_string))
4306 ++base_string;
4307 if (*base_string != ')')
4308 {
4309 as_bad (_("expecting `)' after scale factor in `%s'"),
4310 operand_string);
4311 return 0;
4312 }
4313 }
4314 else if (!i.index_reg)
24eab124 4315 {
af6bdddf
AM		 4316 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4317 *base_string);
24eab124
AM		 4318 return 0;
4319 }
4320 }
af6bdddf 4321 else if (*base_string != ')')
24eab124 4322 {
af6bdddf
AM		 4323 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4324 operand_string);
24eab124
AM		 4325 return 0;
4326 }
c3332e24 4327 }
af6bdddf 4328 else if (*base_string == REGISTER_PREFIX)
c3332e24 4329 {
af6bdddf 4330 as_bad (_("bad register name `%s'"), base_string);
24eab124 4331 return 0;
c3332e24 4332 }
24eab124
AM		 4333 }
4334
4335 /* If there's an expression beginning the operand, parse it,
4336 assuming displacement_string_start and
4337 displacement_string_end are meaningful. */
4338 if (displacement_string_start != displacement_string_end)
4339 {
4340 if (!i386_displacement (displacement_string_start,
4341 displacement_string_end))
4342 return 0;
4343 }
4344
4345 /* Special case for (%dx) while doing input/output op. */
4346 if (i.base_reg
4347 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4348 && i.index_reg == 0
4349 && i.log2_scale_factor == 0
4350 && i.seg[i.mem_operands] == 0
4351 && (i.types[this_operand] & Disp) == 0)
4352 {
4353 i.types[this_operand] = InOutPortReg;
4354 return 1;
4355 }
4356
eecb386c
AM		 4357 if (i386_index_check (operand_string) == 0)
4358 return 0;
24eab124
AM		 4359 i.mem_operands++;
4360 }
4361 else
ce8a8b2f
AM		 4362 {
4363 /* It's not a memory operand; argh! */
24eab124
AM		 4364 as_bad (_("invalid char %s beginning operand %d `%s'"),
4365 output_invalid (*op_string),
4366 this_operand + 1,
4367 op_string);
4368 return 0;
4369 }
47926f60 4370 return 1; /* Normal return. */
252b5132
RH		 4371}
4372\f
ee7fcc42
AM		 4373/* md_estimate_size_before_relax()
4374
4375 Called just before relax() for rs_machine_dependent frags. The x86
4376 assembler uses these frags to handle variable size jump
4377 instructions.
4378
4379 Any symbol that is now undefined will not become defined.
4380 Return the correct fr_subtype in the frag.
4381 Return the initial "guess for variable size of frag" to caller.
4382 The guess is actually the growth beyond the fixed part. Whatever
4383 we do to grow the fixed or variable part contributes to our
4384 returned value. */
4385
252b5132
RH		 4386int
4387md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4388 fragS *fragP;
4389 segT segment;
252b5132 4390{
252b5132 4391 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4392 check for un-relaxable symbols. On an ELF system, we can't relax
4393 an externally visible symbol, because it may be overridden by a
4394 shared library. */
4395 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4396#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4397 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4398 && (S_IS_EXTERNAL (fragP->fr_symbol)
4399 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4400#endif
4401 )
252b5132 4402 {
b98ef147
AM		 4403 /* Symbol is undefined in this segment, or we need to keep a
4404 reloc so that weak symbols can be overridden. */
4405 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4406 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4407 unsigned char *opcode;
4408 int old_fr_fix;
f6af82bd 4409
ee7fcc42
AM		 4410 if (fragP->fr_var != NO_RELOC)
4411 reloc_type = fragP->fr_var;
b98ef147 4412 else if (size == 2)
f6af82bd
AM		 4413 reloc_type = BFD_RELOC_16_PCREL;
4414 else
4415 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4416
ee7fcc42
AM		 4417 old_fr_fix = fragP->fr_fix;
4418 opcode = (unsigned char *) fragP->fr_opcode;
4419
fddf5b5b 4420 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4421 {
fddf5b5b
AM		 4422 case UNCOND_JUMP:
4423 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4424 opcode[0] = 0xe9;
252b5132 4425 fragP->fr_fix += size;
062cd5e7
AS		 4426 fix_new (fragP, old_fr_fix, size,
4427 fragP->fr_symbol,
4428 fragP->fr_offset, 1,
4429 reloc_type);
252b5132
RH		 4430 break;
4431
fddf5b5b 4432 case COND_JUMP86:
412167cb
AM		 4433 if (size == 2
4434 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4435 {
4436 /* Negate the condition, and branch past an
4437 unconditional jump. */
4438 opcode[0] ^= 1;
4439 opcode[1] = 3;
4440 /* Insert an unconditional jump. */
4441 opcode[2] = 0xe9;
4442 /* We added two extra opcode bytes, and have a two byte
4443 offset. */
4444 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4445 fix_new (fragP, old_fr_fix + 2, 2,
4446 fragP->fr_symbol,
4447 fragP->fr_offset, 1,
4448 reloc_type);
fddf5b5b
AM		 4449 break;
4450 }
4451 /* Fall through. */
4452
4453 case COND_JUMP:
412167cb
AM		 4454 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4455 {
3e02c1cc
AM		 4456 fixS *fixP;
4457
412167cb 4458 fragP->fr_fix += 1;
3e02c1cc
AM		 4459 fixP = fix_new (fragP, old_fr_fix, 1,
4460 fragP->fr_symbol,
4461 fragP->fr_offset, 1,
4462 BFD_RELOC_8_PCREL);
4463 fixP->fx_signed = 1;
412167cb
AM		 4464 break;
4465 }
93c2a809 4466
24eab124 4467 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4468 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4469 opcode[1] = opcode[0] + 0x10;
f6af82bd 4470 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4471 /* We've added an opcode byte. */
4472 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4473 fix_new (fragP, old_fr_fix + 1, size,
4474 fragP->fr_symbol,
4475 fragP->fr_offset, 1,
4476 reloc_type);
252b5132 4477 break;
fddf5b5b
AM		 4478
4479 default:
4480 BAD_CASE (fragP->fr_subtype);
4481 break;
252b5132
RH		 4482 }
4483 frag_wane (fragP);
ee7fcc42 4484 return fragP->fr_fix - old_fr_fix;
252b5132 4485 }
93c2a809 4486
93c2a809
AM		 4487 /* Guess size depending on current relax state. Initially the relax
4488 state will correspond to a short jump and we return 1, because
4489 the variable part of the frag (the branch offset) is one byte
4490 long. However, we can relax a section more than once and in that
4491 case we must either set fr_subtype back to the unrelaxed state,
4492 or return the value for the appropriate branch. */
4493 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4494}
4495
47926f60
KH		 4496/* Called after relax() is finished.
4497
4498 In: Address of frag.
4499 fr_type == rs_machine_dependent.
4500 fr_subtype is what the address relaxed to.
4501
4502 Out: Any fixSs and constants are set up.
4503 Caller will turn frag into a ".space 0". */
4504
252b5132
RH		 4505void
4506md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4507 bfd *abfd ATTRIBUTE_UNUSED;
4508 segT sec ATTRIBUTE_UNUSED;
29b0f896 4509 fragS *fragP;
252b5132 4510{
29b0f896 4511 unsigned char *opcode;
252b5132 4512 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4513 offsetT target_address;
4514 offsetT opcode_address;
252b5132 4515 unsigned int extension = 0;
847f7ad4 4516 offsetT displacement_from_opcode_start;
252b5132
RH		 4517
4518 opcode = (unsigned char *) fragP->fr_opcode;
4519
47926f60 4520 /* Address we want to reach in file space. */
252b5132 4521 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4522
47926f60 4523 /* Address opcode resides at in file space. */
252b5132
RH		 4524 opcode_address = fragP->fr_address + fragP->fr_fix;
4525
47926f60 4526 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4527 displacement_from_opcode_start = target_address - opcode_address;
4528
fddf5b5b 4529 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4530 {
47926f60
KH		 4531 /* Don't have to change opcode. */
4532 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4533 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4534 }
4535 else
4536 {
4537 if (no_cond_jump_promotion
4538 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4539 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4540
fddf5b5b
AM		 4541 switch (fragP->fr_subtype)
4542 {
4543 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4544 extension = 4; /* 1 opcode + 4 displacement */
4545 opcode[0] = 0xe9;
4546 where_to_put_displacement = &opcode[1];
4547 break;
252b5132 4548
fddf5b5b
AM		 4549 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4550 extension = 2; /* 1 opcode + 2 displacement */
4551 opcode[0] = 0xe9;
4552 where_to_put_displacement = &opcode[1];
4553 break;
252b5132 4554
fddf5b5b
AM		 4555 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4556 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4557 extension = 5; /* 2 opcode + 4 displacement */
4558 opcode[1] = opcode[0] + 0x10;
4559 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4560 where_to_put_displacement = &opcode[2];
4561 break;
252b5132 4562
fddf5b5b
AM		 4563 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4564 extension = 3; /* 2 opcode + 2 displacement */
4565 opcode[1] = opcode[0] + 0x10;
4566 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4567 where_to_put_displacement = &opcode[2];
4568 break;
252b5132 4569
fddf5b5b
AM		 4570 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4571 extension = 4;
4572 opcode[0] ^= 1;
4573 opcode[1] = 3;
4574 opcode[2] = 0xe9;
4575 where_to_put_displacement = &opcode[3];
4576 break;
4577
4578 default:
4579 BAD_CASE (fragP->fr_subtype);
4580 break;
4581 }
252b5132 4582 }
fddf5b5b 4583
47926f60 4584 /* Now put displacement after opcode. */
252b5132
RH		 4585 md_number_to_chars ((char *) where_to_put_displacement,
4586 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4587 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4588 fragP->fr_fix += extension;
4589}
4590\f
47926f60
KH		 4591/* Size of byte displacement jmp. */
4592int md_short_jump_size = 2;
4593
4594/* Size of dword displacement jmp. */
4595int md_long_jump_size = 5;
252b5132 4596
47926f60
KH		 4597/* Size of relocation record. */
4598const int md_reloc_size = 8;
252b5132
RH		 4599
4600void
4601md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4602 char *ptr;
4603 addressT from_addr, to_addr;
ab9da554
ILT		 4604 fragS *frag ATTRIBUTE_UNUSED;
4605 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4606{
847f7ad4 4607 offsetT offset;
252b5132
RH		 4608
4609 offset = to_addr - (from_addr + 2);
47926f60
KH		 4610 /* Opcode for byte-disp jump. */
4611 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4612 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4613}
4614
4615void
4616md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4617 char *ptr;
4618 addressT from_addr, to_addr;
a38cf1db
AM		 4619 fragS *frag ATTRIBUTE_UNUSED;
4620 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4621{
847f7ad4 4622 offsetT offset;
252b5132 4623
a38cf1db
AM		 4624 offset = to_addr - (from_addr + 5);
4625 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4626 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4627}
4628\f
4629/* Apply a fixup (fixS) to segment data, once it has been determined
4630 by our caller that we have all the info we need to fix it up.
4631
4632 On the 386, immediates, displacements, and data pointers are all in
4633 the same (little-endian) format, so we don't need to care about which
4634 we are handling. */
4635
94f592af
NC		 4636void
4637md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4638 /* The fix we're to put in. */
4639 fixS *fixP;
47926f60 4640 /* Pointer to the value of the bits. */
c6682705 4641 valueT *valP;
47926f60
KH		 4642 /* Segment fix is from. */
4643 segT seg ATTRIBUTE_UNUSED;
252b5132 4644{
94f592af 4645 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4646 valueT value = *valP;
252b5132 4647
f86103b7 4648#if !defined (TE_Mach)
93382f6d
AM		 4649 if (fixP->fx_pcrel)
4650 {
4651 switch (fixP->fx_r_type)
4652 {
5865bb77
ILT		 4653 default:
4654 break;
4655
93382f6d
AM		 4656 case BFD_RELOC_32:
4657 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4658 break;
4659 case BFD_RELOC_16:
4660 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4661 break;
4662 case BFD_RELOC_8:
4663 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4664 break;
4665 }
4666 }
252b5132 4667
a161fe53 4668 if (fixP->fx_addsy != NULL
31312f95
AM		 4669 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4670 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4671 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4672 && !use_rela_relocations)
252b5132 4673 {
31312f95
AM		 4674 /* This is a hack. There should be a better way to handle this.
4675 This covers for the fact that bfd_install_relocation will
4676 subtract the current location (for partial_inplace, PC relative
4677 relocations); see more below. */
252b5132
RH		 4678#ifndef OBJ_AOUT
4679 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4680#ifdef TE_PE
4681 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4682#endif
4683 )
4684 value += fixP->fx_where + fixP->fx_frag->fr_address;
4685#endif
4686#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4687 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4688 {
6539b54b 4689 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4690
6539b54b 4691 if ((sym_seg == seg
2f66722d 4692 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4693 && sym_seg != absolute_section))
ae6063d4 4694 && !generic_force_reloc (fixP))
2f66722d
AM		 4695 {
4696 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4697 bfd_install_relocation subtracts them out again. I think
4698 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4699 it. FIXME. */
4700 value += fixP->fx_where + fixP->fx_frag->fr_address;
4701 }
252b5132
RH		 4702 }
4703#endif
4704#if defined (OBJ_COFF) && defined (TE_PE)
4705 /* For some reason, the PE format does not store a section
24eab124 4706 address offset for a PC relative symbol. */
252b5132
RH		 4707 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4708 value += md_pcrel_from (fixP);
4709#endif
4710 }
4711
4712 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4713 and we must not disappoint it. */
252b5132
RH		 4714#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4715 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4716 && fixP->fx_addsy)
47926f60
KH		 4717 switch (fixP->fx_r_type)
4718 {
4719 case BFD_RELOC_386_PLT32:
3e73aa7c 4720 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4721 /* Make the jump instruction point to the address of the operand. At
4722 runtime we merely add the offset to the actual PLT entry. */
4723 value = -4;
4724 break;
31312f95 4725
13ae64f3
JJ		 4726 case BFD_RELOC_386_TLS_GD:
4727 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4728 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4729 case BFD_RELOC_386_TLS_IE:
4730 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4731 case BFD_RELOC_X86_64_TLSGD:
4732 case BFD_RELOC_X86_64_TLSLD:
4733 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4734 value = 0; /* Fully resolved at runtime. No addend. */
4735 /* Fallthrough */
4736 case BFD_RELOC_386_TLS_LE:
4737 case BFD_RELOC_386_TLS_LDO_32:
4738 case BFD_RELOC_386_TLS_LE_32:
4739 case BFD_RELOC_X86_64_DTPOFF32:
4740 case BFD_RELOC_X86_64_TPOFF32:
4741 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4742 break;
4743
4744 case BFD_RELOC_386_GOT32:
4745 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4746 value = 0; /* Fully resolved at runtime. No addend. */
4747 break;
47926f60
KH		 4748
4749 case BFD_RELOC_VTABLE_INHERIT:
4750 case BFD_RELOC_VTABLE_ENTRY:
4751 fixP->fx_done = 0;
94f592af 4752 return;
47926f60
KH		 4753
4754 default:
4755 break;
4756 }
4757#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4758 *valP = value;
f86103b7 4759#endif /* !defined (TE_Mach) */
3e73aa7c 4760
3e73aa7c 4761 /* Are we finished with this relocation now? */
c6682705 4762 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 4763 fixP->fx_done = 1;
4764 else if (use_rela_relocations)
4765 {
4766 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4767 /* Remember value for tc_gen_reloc. */
4768 fixP->fx_addnumber = value;
3e73aa7c
JH		 4769 value = 0;
4770 }
f86103b7 4771
94f592af 4772 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4773}
252b5132 4774\f
252b5132
RH		 4775#define MAX_LITTLENUMS 6
4776
47926f60
KH		 4777/* Turn the string pointed to by litP into a floating point constant
4778 of type TYPE, and emit the appropriate bytes. The number of
4779 LITTLENUMS emitted is stored in *SIZEP. An error message is
4780 returned, or NULL on OK. */
4781
252b5132
RH		 4782char *
4783md_atof (type, litP, sizeP)
2ab9b79e 4784 int type;
252b5132
RH		 4785 char *litP;
4786 int *sizeP;
4787{
4788 int prec;
4789 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4790 LITTLENUM_TYPE *wordP;
4791 char *t;
4792
4793 switch (type)
4794 {
4795 case 'f':
4796 case 'F':
4797 prec = 2;
4798 break;
4799
4800 case 'd':
4801 case 'D':
4802 prec = 4;
4803 break;
4804
4805 case 'x':
4806 case 'X':
4807 prec = 5;
4808 break;
4809
4810 default:
4811 *sizeP = 0;
4812 return _("Bad call to md_atof ()");
4813 }
4814 t = atof_ieee (input_line_pointer, type, words);
4815 if (t)
4816 input_line_pointer = t;
4817
4818 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4819 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4820 the bigendian 386. */
4821 for (wordP = words + prec - 1; prec--;)
4822 {
4823 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4824 litP += sizeof (LITTLENUM_TYPE);
4825 }
4826 return 0;
4827}
4828\f
4829char output_invalid_buf[8];
4830
252b5132
RH		 4831static char *
4832output_invalid (c)
4833 int c;
4834{
3882b010 4835 if (ISPRINT (c))
252b5132
RH		 4836 sprintf (output_invalid_buf, "'%c'", c);
4837 else
4838 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4839 return output_invalid_buf;
4840}
4841
af6bdddf 4842/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4843
4844static const reg_entry *
4845parse_register (reg_string, end_op)
4846 char *reg_string;
4847 char **end_op;
4848{
af6bdddf
AM		 4849 char *s = reg_string;
4850 char *p;
252b5132
RH		 4851 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4852 const reg_entry *r;
4853
4854 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4855 if (*s == REGISTER_PREFIX)
4856 ++s;
4857
4858 if (is_space_char (*s))
4859 ++s;
4860
4861 p = reg_name_given;
af6bdddf 4862 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4863 {
4864 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4865 return (const reg_entry *) NULL;
4866 s++;
252b5132
RH		 4867 }
4868
6588847e
DN		 4869 /* For naked regs, make sure that we are not dealing with an identifier.
4870 This prevents confusing an identifier like `eax_var' with register
4871 `eax'. */
4872 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4873 return (const reg_entry *) NULL;
4874
af6bdddf 4875 *end_op = s;
252b5132
RH		 4876
4877 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4878
5f47d35b 4879 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4880 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4881 {
5f47d35b
AM		 4882 if (is_space_char (*s))
4883 ++s;
4884 if (*s == '(')
4885 {
af6bdddf 4886 ++s;
5f47d35b
AM		 4887 if (is_space_char (*s))
4888 ++s;
4889 if (*s >= '0' && *s <= '7')
4890 {
4891 r = &i386_float_regtab[*s - '0'];
af6bdddf 4892 ++s;
5f47d35b
AM		 4893 if (is_space_char (*s))
4894 ++s;
4895 if (*s == ')')
4896 {
4897 *end_op = s + 1;
4898 return r;
4899 }
5f47d35b 4900 }
47926f60 4901 /* We have "%st(" then garbage. */
5f47d35b
AM		 4902 return (const reg_entry *) NULL;
4903 }
4904 }
4905
1ae00879 4906 if (r != NULL
29b0f896 4907 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4908 && flag_code != CODE_64BIT)
4909 {
4910 return (const reg_entry *) NULL;
4911 }
4912
252b5132
RH		 4913 return r;
4914}
4915\f
4cc782b5 4916#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 4917const char *md_shortopts = "kVQ:sqn";
252b5132 4918#else
12b55ccc 4919const char *md_shortopts = "qn";
252b5132 4920#endif
6e0b89ee 4921
252b5132 4922struct option md_longopts[] = {
3e73aa7c
JH		 4923#define OPTION_32 (OPTION_MD_BASE + 0)
4924 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4925#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4926#define OPTION_64 (OPTION_MD_BASE + 1)
4927 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4928#endif
252b5132
RH		 4929 {NULL, no_argument, NULL, 0}
4930};
4931size_t md_longopts_size = sizeof (md_longopts);
4932
4933int
4934md_parse_option (c, arg)
4935 int c;
ab9da554 4936 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4937{
4938 switch (c)
4939 {
12b55ccc
L		 4940 case 'n':
4941 optimize_align_code = 0;
4942 break;
4943
a38cf1db
AM		 4944 case 'q':
4945 quiet_warnings = 1;
252b5132
RH		 4946 break;
4947
4948#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4949 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4950 should be emitted or not. FIXME: Not implemented. */
4951 case 'Q':
252b5132
RH		 4952 break;
4953
4954 /* -V: SVR4 argument to print version ID. */
4955 case 'V':
4956 print_version_id ();
4957 break;
4958
a38cf1db
AM		 4959 /* -k: Ignore for FreeBSD compatibility. */
4960 case 'k':
252b5132 4961 break;
4cc782b5
ILT		 4962
4963 case 's':
4964 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4965 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4966 break;
6e0b89ee 4967
3e73aa7c
JH		 4968 case OPTION_64:
4969 {
4970 const char **list, **l;
4971
3e73aa7c
JH		 4972 list = bfd_target_list ();
4973 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4974 if (strcmp (*l, "elf64-x86-64") == 0)
4975 {
4976 default_arch = "x86_64";
4977 break;
4978 }
3e73aa7c 4979 if (*l == NULL)
6e0b89ee 4980 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4981 free (list);
4982 }
4983 break;
4984#endif
252b5132 4985
6e0b89ee
AM		 4986 case OPTION_32:
4987 default_arch = "i386";
4988 break;
4989
252b5132
RH		 4990 default:
4991 return 0;
4992 }
4993 return 1;
4994}
4995
4996void
4997md_show_usage (stream)
4998 FILE *stream;
4999{
4cc782b5
ILT		 5000#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5001 fprintf (stream, _("\
a38cf1db
AM		 5002 -Q ignored\n\
5003 -V print assembler version number\n\
5004 -k ignored\n\
12b55ccc 5005 -n Do not optimize code alignment\n\
a38cf1db
AM		 5006 -q quieten some warnings\n\
5007 -s ignored\n"));
5008#else
5009 fprintf (stream, _("\
12b55ccc 5010 -n Do not optimize code alignment\n\
a38cf1db 5011 -q quieten some warnings\n"));
4cc782b5 5012#endif
252b5132
RH		 5013}
5014
3e73aa7c
JH		 5015#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5016 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5017
5018/* Pick the target format to use. */
5019
47926f60 5020const char *
252b5132
RH		 5021i386_target_format ()
5022{
3e73aa7c
JH		 5023 if (!strcmp (default_arch, "x86_64"))
5024 set_code_flag (CODE_64BIT);
5025 else if (!strcmp (default_arch, "i386"))
5026 set_code_flag (CODE_32BIT);
5027 else
5028 as_fatal (_("Unknown architecture"));
252b5132
RH		 5029 switch (OUTPUT_FLAVOR)
5030 {
4c63da97
AM		 5031#ifdef OBJ_MAYBE_AOUT
5032 case bfd_target_aout_flavour:
47926f60 5033 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5034#endif
5035#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5036 case bfd_target_coff_flavour:
5037 return "coff-i386";
4c63da97 5038#endif
3e73aa7c 5039#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5040 case bfd_target_elf_flavour:
3e73aa7c 5041 {
e5cb08ac
KH		 5042 if (flag_code == CODE_64BIT)
5043 use_rela_relocations = 1;
4ada7262 5044 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5045 }
4c63da97 5046#endif
252b5132
RH		 5047 default:
5048 abort ();
5049 return NULL;
5050 }
5051}
5052
47926f60 5053#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5054
5055#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5056void i386_elf_emit_arch_note ()
5057{
5058 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5059 && cpu_arch_name != NULL)
5060 {
5061 char *p;
5062 asection *seg = now_seg;
5063 subsegT subseg = now_subseg;
5064 Elf_Internal_Note i_note;
5065 Elf_External_Note e_note;
5066 asection *note_secp;
5067 int len;
5068
5069 /* Create the .note section. */
5070 note_secp = subseg_new (".note", 0);
5071 bfd_set_section_flags (stdoutput,
5072 note_secp,
5073 SEC_HAS_CONTENTS | SEC_READONLY);
5074
5075 /* Process the arch string. */
5076 len = strlen (cpu_arch_name);
5077
5078 i_note.namesz = len + 1;
5079 i_note.descsz = 0;
5080 i_note.type = NT_ARCH;
5081 p = frag_more (sizeof (e_note.namesz));
5082 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5083 p = frag_more (sizeof (e_note.descsz));
5084 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5085 p = frag_more (sizeof (e_note.type));
5086 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5087 p = frag_more (len + 1);
5088 strcpy (p, cpu_arch_name);
5089
5090 frag_align (2, 0, 0);
5091
5092 subseg_set (seg, subseg);
5093 }
5094}
5095#endif
252b5132 5096\f
252b5132
RH		 5097symbolS *
5098md_undefined_symbol (name)
5099 char *name;
5100{
18dc2407
ILT		 5101 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5102 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5103 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5104 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5105 {
5106 if (!GOT_symbol)
5107 {
5108 if (symbol_find (name))
5109 as_bad (_("GOT already in symbol table"));
5110 GOT_symbol = symbol_new (name, undefined_section,
5111 (valueT) 0, &zero_address_frag);
5112 };
5113 return GOT_symbol;
5114 }
252b5132
RH		 5115 return 0;
5116}
5117
5118/* Round up a section size to the appropriate boundary. */
47926f60 5119
252b5132
RH		 5120valueT
5121md_section_align (segment, size)
ab9da554 5122 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5123 valueT size;
5124{
4c63da97
AM		 5125#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5126 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5127 {
5128 /* For a.out, force the section size to be aligned. If we don't do
5129 this, BFD will align it for us, but it will not write out the
5130 final bytes of the section. This may be a bug in BFD, but it is
5131 easier to fix it here since that is how the other a.out targets
5132 work. */
5133 int align;
5134
5135 align = bfd_get_section_alignment (stdoutput, segment);
5136 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5137 }
252b5132
RH		 5138#endif
5139
5140 return size;
5141}
5142
5143/* On the i386, PC-relative offsets are relative to the start of the
5144 next instruction. That is, the address of the offset, plus its
5145 size, since the offset is always the last part of the insn. */
5146
5147long
5148md_pcrel_from (fixP)
5149 fixS *fixP;
5150{
5151 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5152}
5153
5154#ifndef I386COFF
5155
5156static void
5157s_bss (ignore)
ab9da554 5158 int ignore ATTRIBUTE_UNUSED;
252b5132 5159{
29b0f896 5160 int temp;
252b5132
RH		 5161
5162 temp = get_absolute_expression ();
5163 subseg_set (bss_section, (subsegT) temp);
5164 demand_empty_rest_of_line ();
5165}
5166
5167#endif
5168
252b5132
RH		 5169void
5170i386_validate_fix (fixp)
5171 fixS *fixp;
5172{
5173 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5174 {
3e73aa7c 5175 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5176 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5177 {
5178 if (flag_code != CODE_64BIT)
5179 abort ();
5180 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5181 }
5182 else
5183 {
5184 if (flag_code == CODE_64BIT)
5185 abort ();
5186 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5187 }
252b5132
RH		 5188 fixp->fx_subsy = 0;
5189 }
5190}
5191
252b5132
RH		 5192arelent *
5193tc_gen_reloc (section, fixp)
ab9da554 5194 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5195 fixS *fixp;
5196{
5197 arelent *rel;
5198 bfd_reloc_code_real_type code;
5199
5200 switch (fixp->fx_r_type)
5201 {
3e73aa7c
JH		 5202 case BFD_RELOC_X86_64_PLT32:
5203 case BFD_RELOC_X86_64_GOT32:
5204 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5205 case BFD_RELOC_386_PLT32:
5206 case BFD_RELOC_386_GOT32:
5207 case BFD_RELOC_386_GOTOFF:
5208 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5209 case BFD_RELOC_386_TLS_GD:
5210 case BFD_RELOC_386_TLS_LDM:
5211 case BFD_RELOC_386_TLS_LDO_32:
5212 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5213 case BFD_RELOC_386_TLS_IE:
5214 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5215 case BFD_RELOC_386_TLS_LE_32:
5216 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5217 case BFD_RELOC_X86_64_32S:
bffbf940
JJ		 5218 case BFD_RELOC_X86_64_TLSGD:
5219 case BFD_RELOC_X86_64_TLSLD:
5220 case BFD_RELOC_X86_64_DTPOFF32:
5221 case BFD_RELOC_X86_64_GOTTPOFF:
5222 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5223 case BFD_RELOC_RVA:
5224 case BFD_RELOC_VTABLE_ENTRY:
5225 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5226#ifdef TE_PE
5227 case BFD_RELOC_32_SECREL:
5228#endif
252b5132
RH		 5229 code = fixp->fx_r_type;
5230 break;
5231 default:
93382f6d 5232 if (fixp->fx_pcrel)
252b5132 5233 {
93382f6d
AM		 5234 switch (fixp->fx_size)
5235 {
5236 default:
b091f402
AM		 5237 as_bad_where (fixp->fx_file, fixp->fx_line,
5238 _("can not do %d byte pc-relative relocation"),
5239 fixp->fx_size);
93382f6d
AM		 5240 code = BFD_RELOC_32_PCREL;
5241 break;
5242 case 1: code = BFD_RELOC_8_PCREL; break;
5243 case 2: code = BFD_RELOC_16_PCREL; break;
5244 case 4: code = BFD_RELOC_32_PCREL; break;
5245 }
5246 }
5247 else
5248 {
5249 switch (fixp->fx_size)
5250 {
5251 default:
b091f402
AM		 5252 as_bad_where (fixp->fx_file, fixp->fx_line,
5253 _("can not do %d byte relocation"),
5254 fixp->fx_size);
93382f6d
AM		 5255 code = BFD_RELOC_32;
5256 break;
5257 case 1: code = BFD_RELOC_8; break;
5258 case 2: code = BFD_RELOC_16; break;
5259 case 4: code = BFD_RELOC_32; break;
937149dd 5260#ifdef BFD64
3e73aa7c 5261 case 8: code = BFD_RELOC_64; break;
937149dd 5262#endif
93382f6d 5263 }
252b5132
RH		 5264 }
5265 break;
5266 }
252b5132
RH		 5267
5268 if (code == BFD_RELOC_32
5269 && GOT_symbol
5270 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5271 {
5272 /* We don't support GOTPC on 64bit targets. */
5273 if (flag_code == CODE_64BIT)
bfb32b52 5274 abort ();
3e73aa7c
JH		 5275 code = BFD_RELOC_386_GOTPC;
5276 }
252b5132
RH		 5277
5278 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5279 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5280 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5281
5282 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5283 if (!use_rela_relocations)
5284 {
5285 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5286 vtable entry to be used in the relocation's section offset. */
5287 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5288 rel->address = fixp->fx_offset;
252b5132 5289
c6682705 5290 rel->addend = 0;
3e73aa7c
JH		 5291 }
5292 /* Use the rela in 64bit mode. */
252b5132 5293 else
3e73aa7c 5294 {
062cd5e7
AS		 5295 if (!fixp->fx_pcrel)
5296 rel->addend = fixp->fx_offset;
5297 else
5298 switch (code)
5299 {
5300 case BFD_RELOC_X86_64_PLT32:
5301 case BFD_RELOC_X86_64_GOT32:
5302 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5303 case BFD_RELOC_X86_64_TLSGD:
5304 case BFD_RELOC_X86_64_TLSLD:
5305 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5306 rel->addend = fixp->fx_offset - fixp->fx_size;
5307 break;
5308 default:
5309 rel->addend = (section->vma
5310 - fixp->fx_size
5311 + fixp->fx_addnumber
5312 + md_pcrel_from (fixp));
5313 break;
5314 }
3e73aa7c
JH		 5315 }
5316
252b5132
RH		 5317 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5318 if (rel->howto == NULL)
5319 {
5320 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5321 _("cannot represent relocation type %s"),
252b5132
RH		 5322 bfd_get_reloc_code_name (code));
5323 /* Set howto to a garbage value so that we can keep going. */
5324 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5325 assert (rel->howto != NULL);
5326 }
5327
5328 return rel;
5329}
5330
64a0c779
DN		 5331\f
5332/* Parse operands using Intel syntax. This implements a recursive descent
5333 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5334 Programmer's Guide.
5335
5336 FIXME: We do not recognize the full operand grammar defined in the MASM
5337 documentation. In particular, all the structure/union and
5338 high-level macro operands are missing.
5339
5340 Uppercase words are terminals, lower case words are non-terminals.
5341 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5342 bars '|' denote choices. Most grammar productions are implemented in
5343 functions called 'intel_<production>'.
5344
5345 Initial production is 'expr'.
5346
64a0c779
DN		 5347 addOp + | -
5348
5349 alpha [a-zA-Z]
5350
5351 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5352
5353 constant digits [[ radixOverride ]]
5354
5355 dataType BYTE | WORD | DWORD | QWORD | XWORD
5356
5357 digits decdigit
b77a7acd
AJ		 5358 | digits decdigit
5359 | digits hexdigit
64a0c779
DN		 5360
5361 decdigit [0-9]
5362
5363 e05 e05 addOp e06
b77a7acd 5364 | e06
64a0c779
DN		 5365
5366 e06 e06 mulOp e09
b77a7acd 5367 | e09
64a0c779
DN		 5368
5369 e09 OFFSET e10
5370 | e09 PTR e10
5371 | e09 : e10
5372 | e10
5373
5374 e10 e10 [ expr ]
b77a7acd 5375 | e11
64a0c779
DN		 5376
5377 e11 ( expr )
b77a7acd 5378 | [ expr ]
64a0c779
DN		 5379 | constant
5380 | dataType
5381 | id
5382 | $
5383 | register
5384
5385 => expr SHORT e05
b77a7acd 5386 | e05
64a0c779
DN		 5387
5388 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5389 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5390
5391 hexdigit a | b | c | d | e | f
b77a7acd 5392 | A | B | C | D | E | F
64a0c779
DN		 5393
5394 id alpha
b77a7acd 5395 | id alpha
64a0c779
DN		 5396 | id decdigit
5397
5398 mulOp * | / | MOD
5399
5400 quote " | '
5401
5402 register specialRegister
b77a7acd 5403 | gpRegister
64a0c779
DN		 5404 | byteRegister
5405
5406 segmentRegister CS | DS | ES | FS | GS | SS
5407
5408 specialRegister CR0 | CR2 | CR3
b77a7acd 5409 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5410 | TR3 | TR4 | TR5 | TR6 | TR7
5411
64a0c779
DN		 5412 We simplify the grammar in obvious places (e.g., register parsing is
5413 done by calling parse_register) and eliminate immediate left recursion
5414 to implement a recursive-descent parser.
5415
5416 expr SHORT e05
b77a7acd 5417 | e05
64a0c779
DN		 5418
5419 e05 e06 e05'
5420
5421 e05' addOp e06 e05'
b77a7acd 5422 | Empty
64a0c779
DN		 5423
5424 e06 e09 e06'
5425
5426 e06' mulOp e09 e06'
b77a7acd 5427 | Empty
64a0c779
DN		 5428
5429 e09 OFFSET e10 e09'
b77a7acd 5430 | e10 e09'
64a0c779
DN		 5431
5432 e09' PTR e10 e09'
b77a7acd 5433 | : e10 e09'
64a0c779
DN		 5434 | Empty
5435
5436 e10 e11 e10'
5437
5438 e10' [ expr ] e10'
b77a7acd 5439 | Empty
64a0c779
DN		 5440
5441 e11 ( expr )
b77a7acd 5442 | [ expr ]
64a0c779
DN		 5443 | BYTE
5444 | WORD
5445 | DWORD
5446 | QWORD
5447 | XWORD
5448 | .
5449 | $
5450 | register
5451 | id
5452 | constant */
5453
5454/* Parsing structure for the intel syntax parser. Used to implement the
5455 semantic actions for the operand grammar. */
5456struct intel_parser_s
5457 {
5458 char *op_string; /* The string being parsed. */
5459 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5460 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5461 int is_mem; /* 1 if operand is memory reference. */
5462 const reg_entry *reg; /* Last register reference found. */
5463 char *disp; /* Displacement string being built. */
5464 };
5465
5466static struct intel_parser_s intel_parser;
5467
5468/* Token structure for parsing intel syntax. */
5469struct intel_token
5470 {
5471 int code; /* Token code. */
5472 const reg_entry *reg; /* Register entry for register tokens. */
5473 char *str; /* String representation. */
5474 };
5475
5476static struct intel_token cur_token, prev_token;
5477
50705ef4
AM		 5478/* Token codes for the intel parser. Since T_SHORT is already used
5479 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5480#define T_NIL -1
5481#define T_CONST 1
5482#define T_REG 2
5483#define T_BYTE 3
5484#define T_WORD 4
5485#define T_DWORD 5
5486#define T_QWORD 6
5487#define T_XWORD 7
50705ef4 5488#undef T_SHORT
64a0c779
DN		 5489#define T_SHORT 8
5490#define T_OFFSET 9
5491#define T_PTR 10
5492#define T_ID 11
5493
5494/* Prototypes for intel parser functions. */
5495static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5496static void intel_get_token PARAMS ((void));
5497static void intel_putback_token PARAMS ((void));
5498static int intel_expr PARAMS ((void));
5499static int intel_e05 PARAMS ((void));
5500static int intel_e05_1 PARAMS ((void));
5501static int intel_e06 PARAMS ((void));
5502static int intel_e06_1 PARAMS ((void));
5503static int intel_e09 PARAMS ((void));
5504static int intel_e09_1 PARAMS ((void));
5505static int intel_e10 PARAMS ((void));
5506static int intel_e10_1 PARAMS ((void));
5507static int intel_e11 PARAMS ((void));
64a0c779 5508
64a0c779
DN		 5509static int
5510i386_intel_operand (operand_string, got_a_float)
5511 char *operand_string;
5512 int got_a_float;
5513{
5514 int ret;
5515 char *p;
5516
5517 /* Initialize token holders. */
5518 cur_token.code = prev_token.code = T_NIL;
5519 cur_token.reg = prev_token.reg = NULL;
5520 cur_token.str = prev_token.str = NULL;
5521
5522 /* Initialize parser structure. */
e5cb08ac 5523 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5524 if (p == NULL)
5525 abort ();
5526 strcpy (intel_parser.op_string, operand_string);
5527 intel_parser.got_a_float = got_a_float;
5528 intel_parser.op_modifier = -1;
5529 intel_parser.is_mem = 0;
5530 intel_parser.reg = NULL;
e5cb08ac 5531 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5532 if (intel_parser.disp == NULL)
5533 abort ();
5534 intel_parser.disp[0] = '\0';
5535
5536 /* Read the first token and start the parser. */
5537 intel_get_token ();
5538 ret = intel_expr ();
5539
5540 if (ret)
5541 {
5542 /* If we found a memory reference, hand it over to i386_displacement
5543 to fill in the rest of the operand fields. */
5544 if (intel_parser.is_mem)
5545 {
5546 if ((i.mem_operands == 1
5547 && (current_templates->start->opcode_modifier & IsString) == 0)
5548 || i.mem_operands == 2)
5549 {
5550 as_bad (_("too many memory references for '%s'"),
5551 current_templates->start->name);
5552 ret = 0;
5553 }
5554 else
5555 {
5556 char *s = intel_parser.disp;
5557 i.mem_operands++;
5558
5559 /* Add the displacement expression. */
5560 if (*s != '\0')
a4622f40
AM		 5561 ret = i386_displacement (s, s + strlen (s));
5562 if (ret)
5563 ret = i386_index_check (operand_string);
64a0c779
DN		 5564 }
5565 }
5566
5567 /* Constant and OFFSET expressions are handled by i386_immediate. */
5568 else if (intel_parser.op_modifier == OFFSET_FLAT
5569 || intel_parser.reg == NULL)
5570 ret = i386_immediate (intel_parser.disp);
5571 }
5572
5573 free (p);
5574 free (intel_parser.disp);
5575
5576 return ret;
5577}
5578
64a0c779 5579/* expr SHORT e05
b77a7acd 5580 | e05 */
64a0c779
DN		 5581static int
5582intel_expr ()
5583{
5584 /* expr SHORT e05 */
5585 if (cur_token.code == T_SHORT)
5586 {
5587 intel_parser.op_modifier = SHORT;
5588 intel_match_token (T_SHORT);
5589
5590 return (intel_e05 ());
5591 }
5592
5593 /* expr e05 */
5594 else
5595 return intel_e05 ();
5596}
5597
64a0c779
DN		 5598/* e05 e06 e05'
5599
4a1805b1 5600 e05' addOp e06 e05'
64a0c779
DN		 5601 | Empty */
5602static int
5603intel_e05 ()
5604{
5605 return (intel_e06 () && intel_e05_1 ());
5606}
5607
5608static int
5609intel_e05_1 ()
5610{
5611 /* e05' addOp e06 e05' */
5612 if (cur_token.code == '+' || cur_token.code == '-')
5613 {
5614 strcat (intel_parser.disp, cur_token.str);
5615 intel_match_token (cur_token.code);
5616
5617 return (intel_e06 () && intel_e05_1 ());
5618 }
5619
5620 /* e05' Empty */
5621 else
5622 return 1;
4a1805b1 5623}
64a0c779
DN		 5624
5625/* e06 e09 e06'
5626
5627 e06' mulOp e09 e06'
b77a7acd 5628 | Empty */
64a0c779
DN		 5629static int
5630intel_e06 ()
5631{
5632 return (intel_e09 () && intel_e06_1 ());
5633}
5634
5635static int
5636intel_e06_1 ()
5637{
5638 /* e06' mulOp e09 e06' */
5639 if (cur_token.code == '*' || cur_token.code == '/')
5640 {
5641 strcat (intel_parser.disp, cur_token.str);
5642 intel_match_token (cur_token.code);
5643
5644 return (intel_e09 () && intel_e06_1 ());
5645 }
4a1805b1 5646
64a0c779 5647 /* e06' Empty */
4a1805b1 5648 else
64a0c779
DN		 5649 return 1;
5650}
5651
64a0c779 5652/* e09 OFFSET e10 e09'
b77a7acd 5653 | e10 e09'
64a0c779
DN		 5654
5655 e09' PTR e10 e09'
b77a7acd 5656 | : e10 e09'
64a0c779
DN		 5657 | Empty */
5658static int
5659intel_e09 ()
5660{
5661 /* e09 OFFSET e10 e09' */
5662 if (cur_token.code == T_OFFSET)
5663 {
5664 intel_parser.is_mem = 0;
5665 intel_parser.op_modifier = OFFSET_FLAT;
5666 intel_match_token (T_OFFSET);
5667
5668 return (intel_e10 () && intel_e09_1 ());
5669 }
5670
5671 /* e09 e10 e09' */
5672 else
5673 return (intel_e10 () && intel_e09_1 ());
5674}
5675
5676static int
5677intel_e09_1 ()
5678{
5679 /* e09' PTR e10 e09' */
5680 if (cur_token.code == T_PTR)
5681 {
5682 if (prev_token.code == T_BYTE)
5683 i.suffix = BYTE_MNEM_SUFFIX;
5684
5685 else if (prev_token.code == T_WORD)
5686 {
5687 if (intel_parser.got_a_float == 2) /* "fi..." */
5688 i.suffix = SHORT_MNEM_SUFFIX;
5689 else
5690 i.suffix = WORD_MNEM_SUFFIX;
5691 }
5692
5693 else if (prev_token.code == T_DWORD)
5694 {
5695 if (intel_parser.got_a_float == 1) /* "f..." */
5696 i.suffix = SHORT_MNEM_SUFFIX;
5697 else
5698 i.suffix = LONG_MNEM_SUFFIX;
5699 }
5700
5701 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5702 {
5703 if (intel_parser.got_a_float == 1) /* "f..." */
5704 i.suffix = LONG_MNEM_SUFFIX;
5705 else
3e73aa7c 5706 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5707 }
64a0c779
DN		 5708
5709 else if (prev_token.code == T_XWORD)
5710 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5711
5712 else
5713 {
5714 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5715 return 0;
5716 }
5717
5718 intel_match_token (T_PTR);
5719
5720 return (intel_e10 () && intel_e09_1 ());
5721 }
5722
5723 /* e09 : e10 e09' */
5724 else if (cur_token.code == ':')
5725 {
21d6c4af
DN		 5726 /* Mark as a memory operand only if it's not already known to be an
5727 offset expression. */
5728 if (intel_parser.op_modifier != OFFSET_FLAT)
5729 intel_parser.is_mem = 1;
64a0c779
DN		 5730
5731 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5732 }
5733
5734 /* e09' Empty */
5735 else
5736 return 1;
5737}
5738
5739/* e10 e11 e10'
5740
5741 e10' [ expr ] e10'
b77a7acd 5742 | Empty */
64a0c779
DN		 5743static int
5744intel_e10 ()
5745{
5746 return (intel_e11 () && intel_e10_1 ());
5747}
5748
5749static int
5750intel_e10_1 ()
5751{
5752 /* e10' [ expr ] e10' */
5753 if (cur_token.code == '[')
5754 {
5755 intel_match_token ('[');
21d6c4af
DN		 5756
5757 /* Mark as a memory operand only if it's not already known to be an
5758 offset expression. If it's an offset expression, we need to keep
5759 the brace in. */
5760 if (intel_parser.op_modifier != OFFSET_FLAT)
5761 intel_parser.is_mem = 1;
5762 else
5763 strcat (intel_parser.disp, "[");
4a1805b1 5764
64a0c779 5765 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5766 if (*intel_parser.disp != '\0'
5767 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5768 strcat (intel_parser.disp, "+");
5769
21d6c4af
DN		 5770 if (intel_expr () && intel_match_token (']'))
5771 {
5772 /* Preserve brackets when the operand is an offset expression. */
5773 if (intel_parser.op_modifier == OFFSET_FLAT)
5774 strcat (intel_parser.disp, "]");
5775
5776 return intel_e10_1 ();
5777 }
5778 else
5779 return 0;
64a0c779
DN		 5780 }
5781
5782 /* e10' Empty */
5783 else
5784 return 1;
5785}
5786
64a0c779 5787/* e11 ( expr )
b77a7acd 5788 | [ expr ]
64a0c779
DN		 5789 | BYTE
5790 | WORD
5791 | DWORD
5792 | QWORD
5793 | XWORD
4a1805b1 5794 | $
64a0c779
DN		 5795 | .
5796 | register
5797 | id
5798 | constant */
5799static int
5800intel_e11 ()
5801{
5802 /* e11 ( expr ) */
5803 if (cur_token.code == '(')
5804 {
5805 intel_match_token ('(');
5806 strcat (intel_parser.disp, "(");
5807
5808 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5809 {
5810 strcat (intel_parser.disp, ")");
5811 return 1;
5812 }
64a0c779
DN		 5813 else
5814 return 0;
5815 }
5816
5817 /* e11 [ expr ] */
5818 else if (cur_token.code == '[')
5819 {
5820 intel_match_token ('[');
21d6c4af
DN		 5821
5822 /* Mark as a memory operand only if it's not already known to be an
5823 offset expression. If it's an offset expression, we need to keep
5824 the brace in. */
5825 if (intel_parser.op_modifier != OFFSET_FLAT)
5826 intel_parser.is_mem = 1;
5827 else
5828 strcat (intel_parser.disp, "[");
4a1805b1 5829
64a0c779
DN		 5830 /* Operands for jump/call inside brackets denote absolute addresses. */
5831 if (current_templates->start->opcode_modifier & Jump
5832 || current_templates->start->opcode_modifier & JumpDword
5833 || current_templates->start->opcode_modifier & JumpByte
5834 || current_templates->start->opcode_modifier & JumpInterSegment)
5835 i.types[this_operand] |= JumpAbsolute;
5836
5837 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5838 if (*intel_parser.disp != '\0'
5839 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5840 strcat (intel_parser.disp, "+");
5841
21d6c4af
DN		 5842 if (intel_expr () && intel_match_token (']'))
5843 {
5844 /* Preserve brackets when the operand is an offset expression. */
5845 if (intel_parser.op_modifier == OFFSET_FLAT)
5846 strcat (intel_parser.disp, "]");
5847
5848 return 1;
5849 }
5850 else
5851 return 0;
64a0c779
DN		 5852 }
5853
4a1805b1 5854 /* e11 BYTE
64a0c779
DN		 5855 | WORD
5856 | DWORD
5857 | QWORD
5858 | XWORD */
5859 else if (cur_token.code == T_BYTE
5860 || cur_token.code == T_WORD
5861 || cur_token.code == T_DWORD
5862 || cur_token.code == T_QWORD
5863 || cur_token.code == T_XWORD)
5864 {
5865 intel_match_token (cur_token.code);
5866
5867 return 1;
5868 }
5869
5870 /* e11 $
5871 | . */
5872 else if (cur_token.code == '$' || cur_token.code == '.')
5873 {
5874 strcat (intel_parser.disp, cur_token.str);
5875 intel_match_token (cur_token.code);
21d6c4af
DN		 5876
5877 /* Mark as a memory operand only if it's not already known to be an
5878 offset expression. */
5879 if (intel_parser.op_modifier != OFFSET_FLAT)
5880 intel_parser.is_mem = 1;
64a0c779
DN		 5881
5882 return 1;
5883 }
5884
5885 /* e11 register */
5886 else if (cur_token.code == T_REG)
5887 {
5888 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5889
5890 intel_match_token (T_REG);
5891
5892 /* Check for segment change. */
5893 if (cur_token.code == ':')
5894 {
5895 if (reg->reg_type & (SReg2 | SReg3))
5896 {
5897 switch (reg->reg_num)
5898 {
5899 case 0:
5900 i.seg[i.mem_operands] = &es;
5901 break;
5902 case 1:
5903 i.seg[i.mem_operands] = &cs;
5904 break;
5905 case 2:
5906 i.seg[i.mem_operands] = &ss;
5907 break;
5908 case 3:
5909 i.seg[i.mem_operands] = &ds;
5910 break;
5911 case 4:
5912 i.seg[i.mem_operands] = &fs;
5913 break;
5914 case 5:
5915 i.seg[i.mem_operands] = &gs;
5916 break;
5917 }
5918 }
5919 else
5920 {
5921 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5922 return 0;
5923 }
5924 }
5925
5926 /* Not a segment register. Check for register scaling. */
5927 else if (cur_token.code == '*')
5928 {
5929 if (!intel_parser.is_mem)
5930 {
5931 as_bad (_("Register scaling only allowed in memory operands."));
5932 return 0;
5933 }
5934
4a1805b1 5935 /* What follows must be a valid scale. */
64a0c779
DN		 5936 if (intel_match_token ('*')
5937 && strchr ("01248", *cur_token.str))
5938 {
5939 i.index_reg = reg;
5940 i.types[this_operand] |= BaseIndex;
5941
5942 /* Set the scale after setting the register (otherwise,
5943 i386_scale will complain) */
5944 i386_scale (cur_token.str);
5945 intel_match_token (T_CONST);
5946 }
5947 else
5948 {
5949 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5950 cur_token.str);
5951 return 0;
5952 }
5953 }
5954
5955 /* No scaling. If this is a memory operand, the register is either a
5956 base register (first occurrence) or an index register (second
5957 occurrence). */
5958 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5959 {
5960 if (i.base_reg && i.index_reg)
5961 {
5962 as_bad (_("Too many register references in memory operand.\n"));
5963 return 0;
5964 }
5965
5966 if (i.base_reg == NULL)
5967 i.base_reg = reg;
5968 else
5969 i.index_reg = reg;
5970
5971 i.types[this_operand] |= BaseIndex;
5972 }
5973
5974 /* Offset modifier. Add the register to the displacement string to be
5975 parsed as an immediate expression after we're done. */
5976 else if (intel_parser.op_modifier == OFFSET_FLAT)
5977 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5978
64a0c779
DN		 5979 /* It's neither base nor index nor offset. */
5980 else
5981 {
5982 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5983 i.op[this_operand].regs = reg;
5984 i.reg_operands++;
5985 }
5986
5987 /* Since registers are not part of the displacement string (except
5988 when we're parsing offset operands), we may need to remove any
5989 preceding '+' from the displacement string. */
5990 if (*intel_parser.disp != '\0'
5991 && intel_parser.op_modifier != OFFSET_FLAT)
5992 {
5993 char *s = intel_parser.disp;
5994 s += strlen (s) - 1;
5995 if (*s == '+')
5996 *s = '\0';
5997 }
5998
5999 return 1;
6000 }
4a1805b1 6001
64a0c779
DN		 6002 /* e11 id */
6003 else if (cur_token.code == T_ID)
6004 {
6005 /* Add the identifier to the displacement string. */
6006 strcat (intel_parser.disp, cur_token.str);
6007 intel_match_token (T_ID);
6008
6009 /* The identifier represents a memory reference only if it's not
6010 preceded by an offset modifier. */
21d6c4af 6011 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6012 intel_parser.is_mem = 1;
6013
6014 return 1;
6015 }
6016
6017 /* e11 constant */
6018 else if (cur_token.code == T_CONST
e5cb08ac 6019 || cur_token.code == '-'
64a0c779
DN		 6020 || cur_token.code == '+')
6021 {
6022 char *save_str;
6023
6024 /* Allow constants that start with `+' or `-'. */
6025 if (cur_token.code == '-' || cur_token.code == '+')
6026 {
6027 strcat (intel_parser.disp, cur_token.str);
6028 intel_match_token (cur_token.code);
6029 if (cur_token.code != T_CONST)
6030 {
6031 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6032 cur_token.str);
6033 return 0;
6034 }
6035 }
6036
e5cb08ac 6037 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6038 if (save_str == NULL)
bc805888 6039 abort ();
64a0c779
DN		 6040 strcpy (save_str, cur_token.str);
6041
6042 /* Get the next token to check for register scaling. */
6043 intel_match_token (cur_token.code);
6044
6045 /* Check if this constant is a scaling factor for an index register. */
6046 if (cur_token.code == '*')
6047 {
6048 if (intel_match_token ('*') && cur_token.code == T_REG)
6049 {
6050 if (!intel_parser.is_mem)
6051 {
6052 as_bad (_("Register scaling only allowed in memory operands."));
6053 return 0;
6054 }
6055
4a1805b1 6056 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6057 a valid scale. */
6058 if (strchr ("01248", *save_str))
6059 {
6060 i.index_reg = cur_token.reg;
6061 i.types[this_operand] |= BaseIndex;
6062
6063 /* Set the scale after setting the register (otherwise,
6064 i386_scale will complain) */
6065 i386_scale (save_str);
6066 intel_match_token (T_REG);
6067
6068 /* Since registers are not part of the displacement
6069 string, we may need to remove any preceding '+' from
6070 the displacement string. */
6071 if (*intel_parser.disp != '\0')
6072 {
6073 char *s = intel_parser.disp;
6074 s += strlen (s) - 1;
6075 if (*s == '+')
6076 *s = '\0';
6077 }
6078
6079 free (save_str);
6080
6081 return 1;
6082 }
6083 else
6084 return 0;
6085 }
6086
6087 /* The constant was not used for register scaling. Since we have
6088 already consumed the token following `*' we now need to put it
6089 back in the stream. */
6090 else
6091 intel_putback_token ();
6092 }
6093
6094 /* Add the constant to the displacement string. */
6095 strcat (intel_parser.disp, save_str);
6096 free (save_str);
6097
6098 return 1;
6099 }
6100
64a0c779
DN		 6101 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6102 return 0;
6103}
6104
64a0c779
DN		 6105/* Match the given token against cur_token. If they match, read the next
6106 token from the operand string. */
6107static int
6108intel_match_token (code)
e5cb08ac 6109 int code;
64a0c779
DN		 6110{
6111 if (cur_token.code == code)
6112 {
6113 intel_get_token ();
6114 return 1;
6115 }
6116 else
6117 {
6118 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6119 return 0;
6120 }
6121}
6122
64a0c779
DN		 6123/* Read a new token from intel_parser.op_string and store it in cur_token. */
6124static void
6125intel_get_token ()
6126{
6127 char *end_op;
6128 const reg_entry *reg;
6129 struct intel_token new_token;
6130
6131 new_token.code = T_NIL;
6132 new_token.reg = NULL;
6133 new_token.str = NULL;
6134
4a1805b1 6135 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6136 cur_token to prev_token. */
6137 if (prev_token.str)
6138 free (prev_token.str);
6139
6140 prev_token = cur_token;
6141
6142 /* Skip whitespace. */
6143 while (is_space_char (*intel_parser.op_string))
6144 intel_parser.op_string++;
6145
6146 /* Return an empty token if we find nothing else on the line. */
6147 if (*intel_parser.op_string == '\0')
6148 {
6149 cur_token = new_token;
6150 return;
6151 }
6152
6153 /* The new token cannot be larger than the remainder of the operand
6154 string. */
e5cb08ac 6155 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6156 if (new_token.str == NULL)
bc805888 6157 abort ();
64a0c779
DN		 6158 new_token.str[0] = '\0';
6159
6160 if (strchr ("0123456789", *intel_parser.op_string))
6161 {
6162 char *p = new_token.str;
6163 char *q = intel_parser.op_string;
6164 new_token.code = T_CONST;
6165
6166 /* Allow any kind of identifier char to encompass floating point and
6167 hexadecimal numbers. */
6168 while (is_identifier_char (*q))
6169 *p++ = *q++;
6170 *p = '\0';
6171
6172 /* Recognize special symbol names [0-9][bf]. */
6173 if (strlen (intel_parser.op_string) == 2
4a1805b1 6174 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6175 || intel_parser.op_string[1] == 'f'))
6176 new_token.code = T_ID;
6177 }
6178
6179 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6180 {
6181 new_token.code = *intel_parser.op_string;
6182 new_token.str[0] = *intel_parser.op_string;
6183 new_token.str[1] = '\0';
6184 }
6185
6186 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6187 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6188 {
6189 new_token.code = T_REG;
6190 new_token.reg = reg;
6191
6192 if (*intel_parser.op_string == REGISTER_PREFIX)
6193 {
6194 new_token.str[0] = REGISTER_PREFIX;
6195 new_token.str[1] = '\0';
6196 }
6197
6198 strcat (new_token.str, reg->reg_name);
6199 }
6200
6201 else if (is_identifier_char (*intel_parser.op_string))
6202 {
6203 char *p = new_token.str;
6204 char *q = intel_parser.op_string;
6205
6206 /* A '.' or '$' followed by an identifier char is an identifier.
6207 Otherwise, it's operator '.' followed by an expression. */
6208 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6209 {
6210 new_token.code = *q;
6211 new_token.str[0] = *q;
6212 new_token.str[1] = '\0';
6213 }
6214 else
6215 {
6216 while (is_identifier_char (*q) || *q == '@')
6217 *p++ = *q++;
6218 *p = '\0';
6219
6220 if (strcasecmp (new_token.str, "BYTE") == 0)
6221 new_token.code = T_BYTE;
6222
6223 else if (strcasecmp (new_token.str, "WORD") == 0)
6224 new_token.code = T_WORD;
6225
6226 else if (strcasecmp (new_token.str, "DWORD") == 0)
6227 new_token.code = T_DWORD;
6228
6229 else if (strcasecmp (new_token.str, "QWORD") == 0)
6230 new_token.code = T_QWORD;
6231
6232 else if (strcasecmp (new_token.str, "XWORD") == 0)
6233 new_token.code = T_XWORD;
6234
6235 else if (strcasecmp (new_token.str, "PTR") == 0)
6236 new_token.code = T_PTR;
6237
6238 else if (strcasecmp (new_token.str, "SHORT") == 0)
6239 new_token.code = T_SHORT;
6240
6241 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6242 {
6243 new_token.code = T_OFFSET;
6244
6245 /* ??? This is not mentioned in the MASM grammar but gcc
6246 makes use of it with -mintel-syntax. OFFSET may be
6247 followed by FLAT: */
6248 if (strncasecmp (q, " FLAT:", 6) == 0)
6249 strcat (new_token.str, " FLAT:");
6250 }
6251
6252 /* ??? This is not mentioned in the MASM grammar. */
6253 else if (strcasecmp (new_token.str, "FLAT") == 0)
6254 new_token.code = T_OFFSET;
6255
6256 else
6257 new_token.code = T_ID;
6258 }
6259 }
6260
6261 else
6262 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6263
6264 intel_parser.op_string += strlen (new_token.str);
6265 cur_token = new_token;
6266}
6267
64a0c779
DN		 6268/* Put cur_token back into the token stream and make cur_token point to
6269 prev_token. */
6270static void
6271intel_putback_token ()
6272{
6273 intel_parser.op_string -= strlen (cur_token.str);
6274 free (cur_token.str);
6275 cur_token = prev_token;
4a1805b1 6276
64a0c779
DN		 6277 /* Forget prev_token. */
6278 prev_token.code = T_NIL;
6279 prev_token.reg = NULL;
6280 prev_token.str = NULL;
6281}
54cfded0 6282
a4447b93 6283int
54cfded0
AM		 6284tc_x86_regname_to_dw2regnum (const char *regname)
6285{
6286 unsigned int regnum;
6287 unsigned int regnames_count;
6288 char *regnames_32[] =
6289 {
a4447b93
RH		 6290 "eax", "ecx", "edx", "ebx",
6291 "esp", "ebp", "esi", "edi",
54cfded0
AM		 6292 "eip"
6293 };
6294 char *regnames_64[] =
6295 {
6296 "rax", "rbx", "rcx", "rdx",
6297 "rdi", "rsi", "rbp", "rsp",
6298 "r8", "r9", "r10", "r11",
6299 "r12", "r13", "r14", "r15",
6300 "rip"
6301 };
6302 char **regnames;
6303
6304 if (flag_code == CODE_64BIT)
6305 {
6306 regnames = regnames_64;
0cea6190 6307 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6308 }
6309 else
6310 {
6311 regnames = regnames_32;
0cea6190 6312 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6313 }
6314
6315 for (regnum = 0; regnum < regnames_count; regnum++)
6316 if (strcmp (regname, regnames[regnum]) == 0)
6317 return regnum;
6318
54cfded0
AM		 6319 return -1;
6320}
6321
6322void
6323tc_x86_frame_initial_instructions (void)
6324{
a4447b93
RH		 6325 static unsigned int sp_regno;
6326
6327 if (!sp_regno)
6328 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6329 ? "rsp" : "esp");
6330
6331 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6332 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6333}
GDB Binutils - Deliverables
This page took 0.587987 seconds and 4 git commands to generate.