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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f3c180ae 157 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186#ifdef LEX_AT
200dbde8 187const char extra_symbol_chars[] = "*%-(@[";
252b5132 188#else
200dbde8 189const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 190#endif
191
29b0f896
AM		 192#if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
252b5132 197/* This array holds the chars that always start a comment. If the
ce8a8b2f 198 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 199const char comment_chars[] = "#/";
200#define PREFIX_SEPARATOR '\\'
252b5132
RH		 201
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
252b5132 210const char line_comment_chars[] = "";
29b0f896 211
252b5132 212#else
29b0f896
AM		 213/* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215const char comment_chars[] = "#";
216#define PREFIX_SEPARATOR '/'
217
252b5132
RH		 218const char line_comment_chars[] = "/";
219#endif
220
63a0b638 221const char line_separator_chars[] = ";";
252b5132 222
ce8a8b2f
AM		 223/* Chars that can be used to separate mant from exp in floating point
224 nums. */
252b5132
RH		 225const char EXP_CHARS[] = "eE";
226
ce8a8b2f
AM		 227/* Chars that mean this number is a floating point constant
228 As in 0f12.456
229 or 0d1.2345e12. */
252b5132
RH		 230const char FLT_CHARS[] = "fFdDxX";
231
ce8a8b2f 232/* Tables for lexical analysis. */
252b5132
RH		 233static char mnemonic_chars[256];
234static char register_chars[256];
235static char operand_chars[256];
236static char identifier_chars[256];
237static char digit_chars[256];
238
ce8a8b2f 239/* Lexical macros. */
252b5132
RH		 240#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241#define is_operand_char(x) (operand_chars[(unsigned char) x])
242#define is_register_char(x) (register_chars[(unsigned char) x])
243#define is_space_char(x) ((x) == ' ')
244#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245#define is_digit_char(x) (digit_chars[(unsigned char) x])
246
ce8a8b2f 247/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 248static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
249
250/* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
47926f60 253 assembler instruction). */
252b5132 254static char save_stack[32];
ce8a8b2f 255static char *save_stack_p;
252b5132
RH		 256#define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258#define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
260
47926f60 261/* The instruction we're assembling. */
252b5132
RH		 262static i386_insn i;
263
264/* Possible templates for current insn. */
265static const templates *current_templates;
266
47926f60 267/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 268static expressionS disp_expressions[2], im_expressions[2];
269
47926f60
KH		 270/* Current operand we are working on. */
271static int this_operand;
252b5132 272
3e73aa7c
JH		 273/* We support four different modes. FLAG_CODE variable is used to distinguish
274 these. */
275
276enum flag_code {
277 CODE_32BIT,
278 CODE_16BIT,
279 CODE_64BIT };
f3c180ae 280#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 281
282static enum flag_code flag_code;
283static int use_rela_relocations = 0;
284
285/* The names used to print error messages. */
b77a7acd 286static const char *flag_code_names[] =
3e73aa7c
JH		 287 {
288 "32",
289 "16",
290 "64"
291 };
252b5132 292
47926f60
KH		 293/* 1 for intel syntax,
294 0 if att syntax. */
295static int intel_syntax = 0;
252b5132 296
47926f60
KH		 297/* 1 if register prefix % not required. */
298static int allow_naked_reg = 0;
252b5132 299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
fddf5b5b
AM		 314/* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316static unsigned int no_cond_jump_promotion = 0;
317
29b0f896
AM		 318/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319symbolS *GOT_symbol;
320
252b5132 321/* Interface to relax_segment.
fddf5b5b
AM		 322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
252b5132 325
47926f60 326/* Types. */
93c2a809
AM		 327#define UNCOND_JUMP 0
328#define COND_JUMP 1
329#define COND_JUMP86 2
fddf5b5b 330
47926f60 331/* Sizes. */
252b5132
RH		 332#define CODE16 1
333#define SMALL 0
29b0f896 334#define SMALL16 (SMALL | CODE16)
252b5132 335#define BIG 2
29b0f896 336#define BIG16 (BIG | CODE16)
252b5132
RH		 337
338#ifndef INLINE
339#ifdef __GNUC__
340#define INLINE __inline__
341#else
342#define INLINE
343#endif
344#endif
345
fddf5b5b
AM		 346#define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348#define TYPE_FROM_RELAX_STATE(s) \
349 ((s) >> 2)
350#define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 352
353/* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
360
361const relax_typeS md_relax_table[] =
362{
24eab124
AM		 363 /* The fields are:
364 1) most positive reach of this state,
365 2) most negative reach of this state,
93c2a809 366 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 367 4) which index into the table to try if we can't fit into this one. */
252b5132 368
fddf5b5b 369 /* UNCOND_JUMP states. */
93c2a809
AM		 370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
252b5132 374 {0, 0, 4, 0},
93c2a809
AM		 375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 377 {0, 0, 2, 0},
378
93c2a809
AM		 379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
384 {0, 0, 5, 0},
fddf5b5b 385 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 386 1 extra opcode byte, 2 displacement bytes. */
387 {0, 0, 3, 0},
388
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
394 {0, 0, 5, 0},
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
397 {0, 0, 4, 0}
252b5132
RH		 398};
399
e413e4e9
AM		 400static const arch_entry cpu_arch[] = {
401 {"i8086", Cpu086 },
402 {"i186", Cpu086|Cpu186 },
403 {"i286", Cpu086|Cpu186|Cpu286 },
404 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
405 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
406 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 410 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 411 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
412 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 413 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 414 {NULL, 0 }
415};
416
29b0f896
AM		 417const pseudo_typeS md_pseudo_table[] =
418{
419#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes, 0},
421#else
422 {"align", s_align_ptwo, 0},
423#endif
424 {"arch", set_cpu_arch, 0},
425#ifndef I386COFF
426 {"bss", s_bss, 0},
427#endif
428 {"ffloat", float_cons, 'f'},
429 {"dfloat", float_cons, 'd'},
430 {"tfloat", float_cons, 'x'},
431 {"value", cons, 2},
432 {"noopt", s_ignore, 0},
433 {"optim", s_ignore, 0},
434 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
435 {"code16", set_code_flag, CODE_16BIT},
436 {"code32", set_code_flag, CODE_32BIT},
437 {"code64", set_code_flag, CODE_64BIT},
438 {"intel_syntax", set_intel_syntax, 1},
439 {"att_syntax", set_intel_syntax, 0},
c6682705 440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 441 {"loc", dwarf2_directive_loc, 0},
442 {0, 0, 0}
443};
444
445/* For interface with expression (). */
446extern char *input_line_pointer;
447
448/* Hash table for instruction mnemonic lookup. */
449static struct hash_control *op_hash;
450
451/* Hash table for register lookup. */
452static struct hash_control *reg_hash;
453\f
252b5132
RH		 454void
455i386_align_code (fragP, count)
456 fragS *fragP;
457 int count;
458{
ce8a8b2f
AM		 459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
252b5132
RH		 462 static const char f32_1[] =
463 {0x90}; /* nop */
464 static const char f32_2[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5[] =
471 {0x90, /* nop */
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8[] =
478 {0x90, /* nop */
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 501 static const char f16_3[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 503 static const char f16_4[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5[] =
506 {0x90, /* nop */
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt[] = {
518 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
519 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
520 };
521 static const char *const f16_patt[] = {
c3332e24 522 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 523 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 };
525
33fef721
JH		 526 if (count <= 0 || count > 15)
527 return;
3e73aa7c 528
33fef721
JH		 529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code == CODE_64BIT)
252b5132 532 {
33fef721
JH		 533 int i;
534 int nnops = (count + 3) / 4;
535 int len = count / nnops;
536 int remains = count - nnops * len;
537 int pos = 0;
538
539 for (i = 0; i < remains; i++)
252b5132 540 {
33fef721
JH		 541 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
542 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
543 pos += len + 1;
544 }
545 for (; i < nnops; i++)
546 {
547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
548 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
549 pos += len;
252b5132 550 }
252b5132 551 }
33fef721
JH		 552 else
553 if (flag_code == CODE_16BIT)
554 {
555 memcpy (fragP->fr_literal + fragP->fr_fix,
556 f16_patt[count - 1], count);
557 if (count > 8)
558 /* Adjust jump offset. */
559 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
560 }
561 else
562 memcpy (fragP->fr_literal + fragP->fr_fix,
563 f32_patt[count - 1], count);
564 fragP->fr_var = count;
252b5132
RH		 565}
566
252b5132
RH		 567static INLINE unsigned int
568mode_from_disp_size (t)
569 unsigned int t;
570{
3e73aa7c 571 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 572}
573
574static INLINE int
575fits_in_signed_byte (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (num >= -128) && (num <= 127);
47926f60 579}
252b5132
RH		 580
581static INLINE int
582fits_in_unsigned_byte (num)
847f7ad4 583 offsetT num;
252b5132
RH		 584{
585 return (num & 0xff) == num;
47926f60 586}
252b5132
RH		 587
588static INLINE int
589fits_in_unsigned_word (num)
847f7ad4 590 offsetT num;
252b5132
RH		 591{
592 return (num & 0xffff) == num;
47926f60 593}
252b5132
RH		 594
595static INLINE int
596fits_in_signed_word (num)
847f7ad4 597 offsetT num;
252b5132
RH		 598{
599 return (-32768 <= num) && (num <= 32767);
47926f60 600}
3e73aa7c
JH		 601static INLINE int
602fits_in_signed_long (num)
603 offsetT num ATTRIBUTE_UNUSED;
604{
605#ifndef BFD64
606 return 1;
607#else
608 return (!(((offsetT) -1 << 31) & num)
609 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
610#endif
611} /* fits_in_signed_long() */
612static INLINE int
613fits_in_unsigned_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (num & (((offsetT) 2 << 31) - 1)) == num;
620#endif
621} /* fits_in_unsigned_long() */
252b5132
RH		 622
623static int
624smallest_imm_type (num)
847f7ad4 625 offsetT num;
252b5132 626{
a847613f 627 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 628 {
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
633 use that form. */
634 if (num == 1)
3e73aa7c 635 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 636 }
252b5132 637 return (fits_in_signed_byte (num)
3e73aa7c 638 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : fits_in_unsigned_byte (num)
3e73aa7c 640 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 641 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 642 ? (Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_signed_long (num)
644 ? (Imm32 | Imm32S | Imm64)
645 : fits_in_unsigned_long (num)
646 ? (Imm32 | Imm64)
647 : Imm64);
47926f60 648}
252b5132 649
847f7ad4
AM		 650static offsetT
651offset_in_range (val, size)
652 offsetT val;
653 int size;
654{
508866be 655 addressT mask;
ba2adb93 656
847f7ad4
AM		 657 switch (size)
658 {
508866be
L		 659 case 1: mask = ((addressT) 1 << 8) - 1; break;
660 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 661 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 662#ifdef BFD64
663 case 8: mask = ((addressT) 2 << 63) - 1; break;
664#endif
47926f60 665 default: abort ();
847f7ad4
AM		 666 }
667
ba2adb93 668 /* If BFD64, sign extend val. */
3e73aa7c
JH		 669 if (!use_rela_relocations)
670 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
671 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 672
47926f60 673 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 674 {
675 char buf1[40], buf2[40];
676
677 sprint_value (buf1, val);
678 sprint_value (buf2, val & mask);
679 as_warn (_("%s shortened to %s"), buf1, buf2);
680 }
681 return val & mask;
682}
683
252b5132
RH		 684/* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
686 added. */
687static int
688add_prefix (prefix)
689 unsigned int prefix;
690{
691 int ret = 1;
692 int q;
693
29b0f896
AM		 694 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
695 && flag_code == CODE_64BIT)
3e73aa7c
JH		 696 q = REX_PREFIX;
697 else
698 switch (prefix)
699 {
700 default:
701 abort ();
702
703 case CS_PREFIX_OPCODE:
704 case DS_PREFIX_OPCODE:
705 case ES_PREFIX_OPCODE:
706 case FS_PREFIX_OPCODE:
707 case GS_PREFIX_OPCODE:
708 case SS_PREFIX_OPCODE:
709 q = SEG_PREFIX;
710 break;
252b5132 711
3e73aa7c
JH		 712 case REPNE_PREFIX_OPCODE:
713 case REPE_PREFIX_OPCODE:
714 ret = 2;
715 /* fall thru */
716 case LOCK_PREFIX_OPCODE:
717 q = LOCKREP_PREFIX;
718 break;
252b5132 719
3e73aa7c
JH		 720 case FWAIT_OPCODE:
721 q = WAIT_PREFIX;
722 break;
252b5132 723
3e73aa7c
JH		 724 case ADDR_PREFIX_OPCODE:
725 q = ADDR_PREFIX;
726 break;
252b5132 727
3e73aa7c
JH		 728 case DATA_PREFIX_OPCODE:
729 q = DATA_PREFIX;
730 break;
731 }
252b5132 732
29b0f896 733 if (i.prefix[q] != 0)
252b5132
RH		 734 {
735 as_bad (_("same type of prefix used twice"));
736 return 0;
737 }
738
739 i.prefixes += 1;
740 i.prefix[q] = prefix;
741 return ret;
742}
743
744static void
3e73aa7c 745set_code_flag (value)
e5cb08ac 746 int value;
eecb386c 747{
3e73aa7c
JH		 748 flag_code = value;
749 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
750 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
751 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
752 {
753 as_bad (_("64bit mode not supported on this CPU."));
754 }
755 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
756 {
757 as_bad (_("32bit mode not supported on this CPU."));
758 }
eecb386c
AM		 759 stackop_size = '\0';
760}
761
762static void
3e73aa7c
JH		 763set_16bit_gcc_code_flag (new_code_flag)
764 int new_code_flag;
252b5132 765{
3e73aa7c
JH		 766 flag_code = new_code_flag;
767 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
768 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
769 stackop_size = 'l';
252b5132
RH		 770}
771
772static void
773set_intel_syntax (syntax_flag)
eecb386c 774 int syntax_flag;
252b5132
RH		 775{
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg = 0;
778
779 SKIP_WHITESPACE ();
29b0f896 780 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 781 {
782 char *string = input_line_pointer;
783 int e = get_symbol_end ();
784
47926f60 785 if (strcmp (string, "prefix") == 0)
252b5132 786 ask_naked_reg = 1;
47926f60 787 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 788 ask_naked_reg = -1;
789 else
d0b47220 790 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 791 *input_line_pointer = e;
792 }
793 demand_empty_rest_of_line ();
c3332e24 794
252b5132
RH		 795 intel_syntax = syntax_flag;
796
797 if (ask_naked_reg == 0)
798 {
799#ifdef BFD_ASSEMBLER
800 allow_naked_reg = (intel_syntax
24eab124 801 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 802#else
47926f60
KH		 803 /* Conservative default. */
804 allow_naked_reg = 0;
252b5132
RH		 805#endif
806 }
807 else
808 allow_naked_reg = (ask_naked_reg < 0);
809}
810
e413e4e9
AM		 811static void
812set_cpu_arch (dummy)
47926f60 813 int dummy ATTRIBUTE_UNUSED;
e413e4e9 814{
47926f60 815 SKIP_WHITESPACE ();
e413e4e9 816
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821 int i;
822
823 for (i = 0; cpu_arch[i].name; i++)
824 {
825 if (strcmp (string, cpu_arch[i].name) == 0)
826 {
827 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 828 cpu_arch_flags = (cpu_arch[i].flags
829 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 830 break;
831 }
832 }
833 if (!cpu_arch[i].name)
834 as_bad (_("no such architecture: `%s'"), string);
835
836 *input_line_pointer = e;
837 }
838 else
839 as_bad (_("missing cpu architecture"));
840
fddf5b5b
AM		 841 no_cond_jump_promotion = 0;
842 if (*input_line_pointer == ','
29b0f896 843 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 844 {
845 char *string = ++input_line_pointer;
846 int e = get_symbol_end ();
847
848 if (strcmp (string, "nojumps") == 0)
849 no_cond_jump_promotion = 1;
850 else if (strcmp (string, "jumps") == 0)
851 ;
852 else
853 as_bad (_("no such architecture modifier: `%s'"), string);
854
855 *input_line_pointer = e;
856 }
857
e413e4e9
AM		 858 demand_empty_rest_of_line ();
859}
860
b9d79e03
JH		 861#ifdef BFD_ASSEMBLER
862unsigned long
863i386_mach ()
864{
865 if (!strcmp (default_arch, "x86_64"))
866 return bfd_mach_x86_64;
867 else if (!strcmp (default_arch, "i386"))
868 return bfd_mach_i386_i386;
869 else
870 as_fatal (_("Unknown architecture"));
871}
872#endif
873\f
252b5132
RH		 874void
875md_begin ()
876{
877 const char *hash_err;
878
47926f60 879 /* Initialize op_hash hash table. */
252b5132
RH		 880 op_hash = hash_new ();
881
882 {
29b0f896
AM		 883 const template *optab;
884 templates *core_optab;
252b5132 885
47926f60
KH		 886 /* Setup for loop. */
887 optab = i386_optab;
252b5132
RH		 888 core_optab = (templates *) xmalloc (sizeof (templates));
889 core_optab->start = optab;
890
891 while (1)
892 {
893 ++optab;
894 if (optab->name == NULL
895 || strcmp (optab->name, (optab - 1)->name) != 0)
896 {
897 /* different name --> ship out current template list;
47926f60 898 add to hash table; & begin anew. */
252b5132
RH		 899 core_optab->end = optab;
900 hash_err = hash_insert (op_hash,
901 (optab - 1)->name,
902 (PTR) core_optab);
903 if (hash_err)
904 {
252b5132
RH		 905 as_fatal (_("Internal Error: Can't hash %s: %s"),
906 (optab - 1)->name,
907 hash_err);
908 }
909 if (optab->name == NULL)
910 break;
911 core_optab = (templates *) xmalloc (sizeof (templates));
912 core_optab->start = optab;
913 }
914 }
915 }
916
47926f60 917 /* Initialize reg_hash hash table. */
252b5132
RH		 918 reg_hash = hash_new ();
919 {
29b0f896 920 const reg_entry *regtab;
252b5132
RH		 921
922 for (regtab = i386_regtab;
923 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
924 regtab++)
925 {
926 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
927 if (hash_err)
3e73aa7c
JH		 928 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 regtab->reg_name,
930 hash_err);
252b5132
RH		 931 }
932 }
933
47926f60 934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 935 {
29b0f896
AM		 936 int c;
937 char *p;
252b5132
RH		 938
939 for (c = 0; c < 256; c++)
940 {
3882b010 941 if (ISDIGIT (c))
252b5132
RH		 942 {
943 digit_chars[c] = c;
944 mnemonic_chars[c] = c;
945 register_chars[c] = c;
946 operand_chars[c] = c;
947 }
3882b010 948 else if (ISLOWER (c))
252b5132
RH		 949 {
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISUPPER (c))
252b5132 955 {
3882b010 956 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 957 register_chars[c] = mnemonic_chars[c];
958 operand_chars[c] = c;
959 }
960
3882b010 961 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 962 identifier_chars[c] = c;
963 else if (c >= 128)
964 {
965 identifier_chars[c] = c;
966 operand_chars[c] = c;
967 }
968 }
969
970#ifdef LEX_AT
971 identifier_chars['@'] = '@';
972#endif
252b5132
RH		 973 digit_chars['-'] = '-';
974 identifier_chars['_'] = '_';
975 identifier_chars['.'] = '.';
976
977 for (p = operand_special_chars; *p != '\0'; p++)
978 operand_chars[(unsigned char) *p] = *p;
979 }
980
981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
983 {
984 record_alignment (text_section, 2);
985 record_alignment (data_section, 2);
986 record_alignment (bss_section, 2);
987 }
988#endif
989}
990
991void
992i386_print_statistics (file)
993 FILE *file;
994{
995 hash_print_statistics (file, "i386 opcode", op_hash);
996 hash_print_statistics (file, "i386 register", reg_hash);
997}
998\f
252b5132
RH		 999#ifdef DEBUG386
1000
ce8a8b2f 1001/* Debugging routines for md_assemble. */
252b5132
RH		 1002static void pi PARAMS ((char *, i386_insn *));
1003static void pte PARAMS ((template *));
1004static void pt PARAMS ((unsigned int));
1005static void pe PARAMS ((expressionS *));
1006static void ps PARAMS ((symbolS *));
1007
1008static void
1009pi (line, x)
1010 char *line;
1011 i386_insn *x;
1012{
09f131f2 1013 unsigned int i;
252b5132
RH		 1014
1015 fprintf (stdout, "%s: template ", line);
1016 pte (&x->tm);
09f131f2
JH		 1017 fprintf (stdout, " address: base %s index %s scale %x\n",
1018 x->base_reg ? x->base_reg->reg_name : "none",
1019 x->index_reg ? x->index_reg->reg_name : "none",
1020 x->log2_scale_factor);
1021 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1022 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1023 fprintf (stdout, " sib: base %x index %x scale %x\n",
1024 x->sib.base, x->sib.index, x->sib.scale);
1025 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1026 (x->rex & REX_MODE64) != 0,
1027 (x->rex & REX_EXTX) != 0,
1028 (x->rex & REX_EXTY) != 0,
1029 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1030 for (i = 0; i < x->operands; i++)
1031 {
1032 fprintf (stdout, " #%d: ", i + 1);
1033 pt (x->types[i]);
1034 fprintf (stdout, "\n");
1035 if (x->types[i]
3f4438ab 1036 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1037 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1038 if (x->types[i] & Imm)
520dc8e8 1039 pe (x->op[i].imms);
252b5132 1040 if (x->types[i] & Disp)
520dc8e8 1041 pe (x->op[i].disps);
252b5132
RH		 1042 }
1043}
1044
1045static void
1046pte (t)
1047 template *t;
1048{
09f131f2 1049 unsigned int i;
252b5132 1050 fprintf (stdout, " %d operands ", t->operands);
47926f60 1051 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1052 if (t->extension_opcode != None)
1053 fprintf (stdout, "ext %x ", t->extension_opcode);
1054 if (t->opcode_modifier & D)
1055 fprintf (stdout, "D");
1056 if (t->opcode_modifier & W)
1057 fprintf (stdout, "W");
1058 fprintf (stdout, "\n");
1059 for (i = 0; i < t->operands; i++)
1060 {
1061 fprintf (stdout, " #%d type ", i + 1);
1062 pt (t->operand_types[i]);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068pe (e)
1069 expressionS *e;
1070{
24eab124 1071 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1072 fprintf (stdout, " add_number %ld (%lx)\n",
1073 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1074 if (e->X_add_symbol)
1075 {
1076 fprintf (stdout, " add_symbol ");
1077 ps (e->X_add_symbol);
1078 fprintf (stdout, "\n");
1079 }
1080 if (e->X_op_symbol)
1081 {
1082 fprintf (stdout, " op_symbol ");
1083 ps (e->X_op_symbol);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089ps (s)
1090 symbolS *s;
1091{
1092 fprintf (stdout, "%s type %s%s",
1093 S_GET_NAME (s),
1094 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s)));
1096}
1097
1098struct type_name
1099 {
1100 unsigned int mask;
1101 char *tname;
1102 }
1103
29b0f896 1104static const type_names[] =
252b5132
RH		 1105{
1106 { Reg8, "r8" },
1107 { Reg16, "r16" },
1108 { Reg32, "r32" },
09f131f2 1109 { Reg64, "r64" },
252b5132
RH		 1110 { Imm8, "i8" },
1111 { Imm8S, "i8s" },
1112 { Imm16, "i16" },
1113 { Imm32, "i32" },
09f131f2
JH		 1114 { Imm32S, "i32s" },
1115 { Imm64, "i64" },
252b5132
RH		 1116 { Imm1, "i1" },
1117 { BaseIndex, "BaseIndex" },
1118 { Disp8, "d8" },
1119 { Disp16, "d16" },
1120 { Disp32, "d32" },
09f131f2
JH		 1121 { Disp32S, "d32s" },
1122 { Disp64, "d64" },
252b5132
RH		 1123 { InOutPortReg, "InOutPortReg" },
1124 { ShiftCount, "ShiftCount" },
1125 { Control, "control reg" },
1126 { Test, "test reg" },
1127 { Debug, "debug reg" },
1128 { FloatReg, "FReg" },
1129 { FloatAcc, "FAcc" },
1130 { SReg2, "SReg2" },
1131 { SReg3, "SReg3" },
1132 { Acc, "Acc" },
1133 { JumpAbsolute, "Jump Absolute" },
1134 { RegMMX, "rMMX" },
3f4438ab 1135 { RegXMM, "rXMM" },
252b5132
RH		 1136 { EsSeg, "es" },
1137 { 0, "" }
1138};
1139
1140static void
1141pt (t)
1142 unsigned int t;
1143{
29b0f896 1144 const struct type_name *ty;
252b5132 1145
09f131f2
JH		 1146 for (ty = type_names; ty->mask; ty++)
1147 if (t & ty->mask)
1148 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1149 fflush (stdout);
1150}
1151
1152#endif /* DEBUG386 */
1153\f
252b5132 1154#ifdef BFD_ASSEMBLER
29b0f896
AM		 1155static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1157
1158static bfd_reloc_code_real_type
3e73aa7c 1159reloc (size, pcrel, sign, other)
252b5132
RH		 1160 int size;
1161 int pcrel;
3e73aa7c 1162 int sign;
252b5132
RH		 1163 bfd_reloc_code_real_type other;
1164{
47926f60
KH		 1165 if (other != NO_RELOC)
1166 return other;
252b5132
RH		 1167
1168 if (pcrel)
1169 {
3e73aa7c 1170 if (!sign)
e5cb08ac 1171 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1172 switch (size)
1173 {
1174 case 1: return BFD_RELOC_8_PCREL;
1175 case 2: return BFD_RELOC_16_PCREL;
1176 case 4: return BFD_RELOC_32_PCREL;
1177 }
d0b47220 1178 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1179 }
1180 else
1181 {
3e73aa7c 1182 if (sign)
e5cb08ac 1183 switch (size)
3e73aa7c
JH		 1184 {
1185 case 4: return BFD_RELOC_X86_64_32S;
1186 }
1187 else
1188 switch (size)
1189 {
1190 case 1: return BFD_RELOC_8;
1191 case 2: return BFD_RELOC_16;
1192 case 4: return BFD_RELOC_32;
1193 case 8: return BFD_RELOC_64;
1194 }
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign ? "signed" : "unsigned", size);
252b5132
RH		 1197 }
1198
bfb32b52 1199 abort ();
252b5132
RH		 1200 return BFD_RELOC_NONE;
1201}
1202
47926f60
KH		 1203/* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1207
252b5132 1208int
c0c949c7 1209tc_i386_fix_adjustable (fixP)
31312f95 1210 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1211{
6d249963 1212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1214 return 1;
1215
a161fe53
AM		 1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 mode. */
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1220 && fixP->fx_pcrel)
252b5132 1221 return 0;
31312f95 1222
ce8a8b2f 1223 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1243 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1244 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1245 return 0;
31312f95 1246#endif
252b5132
RH		 1247 return 1;
1248}
1249#else
ec56dfb4 1250#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1251#define BFD_RELOC_8 0
ec56dfb4
L		 1252#define BFD_RELOC_16 0
1253#define BFD_RELOC_32 0
c6682705 1254#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1255#define BFD_RELOC_16_PCREL 0
1256#define BFD_RELOC_32_PCREL 0
1257#define BFD_RELOC_386_PLT32 0
1258#define BFD_RELOC_386_GOT32 0
1259#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1260#define BFD_RELOC_386_TLS_GD 0
1261#define BFD_RELOC_386_TLS_LDM 0
1262#define BFD_RELOC_386_TLS_LDO_32 0
1263#define BFD_RELOC_386_TLS_IE_32 0
37e55690
JJ		 1264#define BFD_RELOC_386_TLS_IE 0
1265#define BFD_RELOC_386_TLS_GOTIE 0
13ae64f3
JJ		 1266#define BFD_RELOC_386_TLS_LE_32 0
1267#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1268#define BFD_RELOC_X86_64_PLT32 0
1269#define BFD_RELOC_X86_64_GOT32 0
1270#define BFD_RELOC_X86_64_GOTPCREL 0
bffbf940
JJ		 1271#define BFD_RELOC_X86_64_TLSGD 0
1272#define BFD_RELOC_X86_64_TLSLD 0
1273#define BFD_RELOC_X86_64_DTPOFF32 0
1274#define BFD_RELOC_X86_64_GOTTPOFF 0
1275#define BFD_RELOC_X86_64_TPOFF32 0
252b5132
RH		 1276#endif
1277
29b0f896 1278static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1279
1280static int
252b5132 1281intel_float_operand (mnemonic)
29b0f896 1282 const char *mnemonic;
252b5132 1283{
47926f60 1284 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1285 return 2;
252b5132
RH		 1286
1287 if (mnemonic[0] == 'f')
1288 return 1;
1289
1290 return 0;
1291}
1292
1293/* This is the guts of the machine-dependent assembler. LINE points to a
1294 machine dependent instruction. This function is supposed to emit
1295 the frags/bytes it assembles to. */
1296
1297void
1298md_assemble (line)
1299 char *line;
1300{
252b5132 1301 int j;
252b5132
RH		 1302 char mnemonic[MAX_MNEM_SIZE];
1303
47926f60 1304 /* Initialize globals. */
252b5132
RH		 1305 memset (&i, '\0', sizeof (i));
1306 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1307 i.reloc[j] = NO_RELOC;
252b5132
RH		 1308 memset (disp_expressions, '\0', sizeof (disp_expressions));
1309 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1310 save_stack_p = save_stack;
252b5132
RH		 1311
1312 /* First parse an instruction mnemonic & call i386_operand for the operands.
1313 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1314 start of a (possibly prefixed) mnemonic. */
252b5132 1315
29b0f896
AM		 1316 line = parse_insn (line, mnemonic);
1317 if (line == NULL)
1318 return;
252b5132 1319
29b0f896
AM		 1320 line = parse_operands (line, mnemonic);
1321 if (line == NULL)
1322 return;
252b5132 1323
29b0f896
AM		 1324 /* Now we've parsed the mnemonic into a set of templates, and have the
1325 operands at hand. */
1326
1327 /* All intel opcodes have reversed operands except for "bound" and
1328 "enter". We also don't reverse intersegment "jmp" and "call"
1329 instructions with 2 immediate operands so that the immediate segment
1330 precedes the offset, as it does when in AT&T mode. "enter" and the
1331 intersegment "jmp" and "call" instructions are the only ones that
1332 have two immediate operands. */
1333 if (intel_syntax && i.operands > 1
1334 && (strcmp (mnemonic, "bound") != 0)
1335 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1336 swap_operands ();
1337
1338 if (i.imm_operands)
1339 optimize_imm ();
1340
1341 if (i.disp_operands)
1342 optimize_disp ();
1343
1344 /* Next, we find a template that matches the given insn,
1345 making sure the overlap of the given operands types is consistent
1346 with the template operand types. */
252b5132 1347
29b0f896
AM		 1348 if (!match_template ())
1349 return;
252b5132 1350
cd61ebfe
AM		 1351 if (intel_syntax)
1352 {
1353 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1354 if (SYSV386_COMPAT
1355 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1356 i.tm.base_opcode ^= FloatR;
1357
1358 /* Zap movzx and movsx suffix. The suffix may have been set from
1359 "word ptr" or "byte ptr" on the source operand, but we'll use
1360 the suffix later to choose the destination register. */
1361 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1362 i.suffix = 0;
1363 }
24eab124 1364
29b0f896
AM		 1365 if (i.tm.opcode_modifier & FWait)
1366 if (!add_prefix (FWAIT_OPCODE))
1367 return;
252b5132 1368
29b0f896
AM		 1369 /* Check string instruction segment overrides. */
1370 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1371 {
1372 if (!check_string ())
5dd0794d 1373 return;
29b0f896 1374 }
5dd0794d 1375
29b0f896
AM		 1376 if (!process_suffix ())
1377 return;
e413e4e9 1378
29b0f896
AM		 1379 /* Make still unresolved immediate matches conform to size of immediate
1380 given in i.suffix. */
1381 if (!finalize_imm ())
1382 return;
252b5132 1383
29b0f896
AM		 1384 if (i.types[0] & Imm1)
1385 i.imm_operands = 0; /* kludge for shift insns. */
1386 if (i.types[0] & ImplicitRegister)
1387 i.reg_operands--;
1388 if (i.types[1] & ImplicitRegister)
1389 i.reg_operands--;
1390 if (i.types[2] & ImplicitRegister)
1391 i.reg_operands--;
252b5132 1392
29b0f896
AM		 1393 if (i.tm.opcode_modifier & ImmExt)
1394 {
1395 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1396 opcode suffix which is coded in the same place as an 8-bit
1397 immediate field would be. Here we fake an 8-bit immediate
1398 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1399
29b0f896 1400 expressionS *exp;
252b5132 1401
29b0f896 1402 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1403
29b0f896
AM		 1404 exp = &im_expressions[i.imm_operands++];
1405 i.op[i.operands].imms = exp;
1406 i.types[i.operands++] = Imm8;
1407 exp->X_op = O_constant;
1408 exp->X_add_number = i.tm.extension_opcode;
1409 i.tm.extension_opcode = None;
1410 }
252b5132 1411
29b0f896
AM		 1412 /* For insns with operands there are more diddles to do to the opcode. */
1413 if (i.operands)
1414 {
1415 if (!process_operands ())
1416 return;
1417 }
1418 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1419 {
1420 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1421 as_warn (_("translating to `%sp'"), i.tm.name);
1422 }
252b5132 1423
29b0f896
AM		 1424 /* Handle conversion of 'int $3' --> special int3 insn. */
1425 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1426 {
1427 i.tm.base_opcode = INT3_OPCODE;
1428 i.imm_operands = 0;
1429 }
252b5132 1430
29b0f896
AM		 1431 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1432 && i.op[0].disps->X_op == O_constant)
1433 {
1434 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1435 the absolute address given by the constant. Since ix86 jumps and
1436 calls are pc relative, we need to generate a reloc. */
1437 i.op[0].disps->X_add_symbol = &abs_symbol;
1438 i.op[0].disps->X_op = O_symbol;
1439 }
252b5132 1440
29b0f896
AM		 1441 if ((i.tm.opcode_modifier & Rex64) != 0)
1442 i.rex |= REX_MODE64;
252b5132 1443
29b0f896
AM		 1444 /* For 8 bit registers we need an empty rex prefix. Also if the
1445 instruction already has a prefix, we need to convert old
1446 registers to new ones. */
773f551c 1447
29b0f896
AM		 1448 if (((i.types[0] & Reg8) != 0
1449 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1450 || ((i.types[1] & Reg8) != 0
1451 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1452 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1453 && i.rex != 0))
1454 {
1455 int x;
726c5dcd 1456
29b0f896
AM		 1457 i.rex |= REX_OPCODE;
1458 for (x = 0; x < 2; x++)
1459 {
1460 /* Look for 8 bit operand that uses old registers. */
1461 if ((i.types[x] & Reg8) != 0
1462 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1463 {
29b0f896
AM		 1464 /* In case it is "hi" register, give up. */
1465 if (i.op[x].regs->reg_num > 3)
1466 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1467 i.op[x].regs->reg_name);
773f551c 1468
29b0f896
AM		 1469 /* Otherwise it is equivalent to the extended register.
1470 Since the encoding doesn't change this is merely
1471 cosmetic cleanup for debug output. */
1472
1473 i.op[x].regs = i.op[x].regs + 8;
773f551c 1474 }
29b0f896
AM		 1475 }
1476 }
773f551c 1477
29b0f896
AM		 1478 if (i.rex != 0)
1479 add_prefix (REX_OPCODE | i.rex);
1480
1481 /* We are ready to output the insn. */
1482 output_insn ();
1483}
1484
1485static char *
1486parse_insn (line, mnemonic)
1487 char *line;
1488 char *mnemonic;
1489{
1490 char *l = line;
1491 char *token_start = l;
1492 char *mnem_p;
1493
1494 /* Non-zero if we found a prefix only acceptable with string insns. */
1495 const char *expecting_string_instruction = NULL;
45288df1 1496
29b0f896
AM		 1497 while (1)
1498 {
1499 mnem_p = mnemonic;
1500 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1501 {
1502 mnem_p++;
1503 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1504 {
29b0f896
AM		 1505 as_bad (_("no such instruction: `%s'"), token_start);
1506 return NULL;
1507 }
1508 l++;
1509 }
1510 if (!is_space_char (*l)
1511 && *l != END_OF_INSN
1512 && *l != PREFIX_SEPARATOR
1513 && *l != ',')
1514 {
1515 as_bad (_("invalid character %s in mnemonic"),
1516 output_invalid (*l));
1517 return NULL;
1518 }
1519 if (token_start == l)
1520 {
1521 if (*l == PREFIX_SEPARATOR)
1522 as_bad (_("expecting prefix; got nothing"));
1523 else
1524 as_bad (_("expecting mnemonic; got nothing"));
1525 return NULL;
1526 }
45288df1 1527
29b0f896
AM		 1528 /* Look up instruction (or prefix) via hash table. */
1529 current_templates = hash_find (op_hash, mnemonic);
47926f60 1530
29b0f896
AM		 1531 if (*l != END_OF_INSN
1532 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1533 && current_templates
1534 && (current_templates->start->opcode_modifier & IsPrefix))
1535 {
1536 /* If we are in 16-bit mode, do not allow addr16 or data16.
1537 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1538 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1539 && flag_code != CODE_64BIT
1540 && (((current_templates->start->opcode_modifier & Size32) != 0)
1541 ^ (flag_code == CODE_16BIT)))
1542 {
1543 as_bad (_("redundant %s prefix"),
1544 current_templates->start->name);
1545 return NULL;
45288df1 1546 }
29b0f896
AM		 1547 /* Add prefix, checking for repeated prefixes. */
1548 switch (add_prefix (current_templates->start->base_opcode))
1549 {
1550 case 0:
1551 return NULL;
1552 case 2:
1553 expecting_string_instruction = current_templates->start->name;
1554 break;
1555 }
1556 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1557 token_start = ++l;
1558 }
1559 else
1560 break;
1561 }
45288df1 1562
29b0f896
AM		 1563 if (!current_templates)
1564 {
1565 /* See if we can get a match by trimming off a suffix. */
1566 switch (mnem_p[-1])
1567 {
1568 case WORD_MNEM_SUFFIX:
1569 case BYTE_MNEM_SUFFIX:
1570 case QWORD_MNEM_SUFFIX:
1571 i.suffix = mnem_p[-1];
1572 mnem_p[-1] = '\0';
1573 current_templates = hash_find (op_hash, mnemonic);
1574 break;
1575 case SHORT_MNEM_SUFFIX:
1576 case LONG_MNEM_SUFFIX:
1577 if (!intel_syntax)
1578 {
1579 i.suffix = mnem_p[-1];
1580 mnem_p[-1] = '\0';
1581 current_templates = hash_find (op_hash, mnemonic);
1582 }
1583 break;
252b5132 1584
29b0f896
AM		 1585 /* Intel Syntax. */
1586 case 'd':
1587 if (intel_syntax)
1588 {
1589 if (intel_float_operand (mnemonic))
1590 i.suffix = SHORT_MNEM_SUFFIX;
1591 else
1592 i.suffix = LONG_MNEM_SUFFIX;
1593 mnem_p[-1] = '\0';
1594 current_templates = hash_find (op_hash, mnemonic);
1595 }
1596 break;
1597 }
1598 if (!current_templates)
1599 {
1600 as_bad (_("no such instruction: `%s'"), token_start);
1601 return NULL;
1602 }
1603 }
252b5132 1604
29b0f896
AM		 1605 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1606 {
1607 /* Check for a branch hint. We allow ",pt" and ",pn" for
1608 predict taken and predict not taken respectively.
1609 I'm not sure that branch hints actually do anything on loop
1610 and jcxz insns (JumpByte) for current Pentium4 chips. They
1611 may work in the future and it doesn't hurt to accept them
1612 now. */
1613 if (l[0] == ',' && l[1] == 'p')
1614 {
1615 if (l[2] == 't')
1616 {
1617 if (!add_prefix (DS_PREFIX_OPCODE))
1618 return NULL;
1619 l += 3;
1620 }
1621 else if (l[2] == 'n')
1622 {
1623 if (!add_prefix (CS_PREFIX_OPCODE))
1624 return NULL;
1625 l += 3;
1626 }
1627 }
1628 }
1629 /* Any other comma loses. */
1630 if (*l == ',')
1631 {
1632 as_bad (_("invalid character %s in mnemonic"),
1633 output_invalid (*l));
1634 return NULL;
1635 }
252b5132 1636
29b0f896
AM		 1637 /* Check if instruction is supported on specified architecture. */
1638 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1639 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1640 {
1641 as_warn (_("`%s' is not supported on `%s'"),
1642 current_templates->start->name, cpu_arch_name);
1643 }
1644 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1645 {
1646 as_warn (_("use .code16 to ensure correct addressing mode"));
1647 }
252b5132 1648
29b0f896
AM		 1649 /* Check for rep/repne without a string instruction. */
1650 if (expecting_string_instruction
1651 && !(current_templates->start->opcode_modifier & IsString))
1652 {
1653 as_bad (_("expecting string instruction after `%s'"),
1654 expecting_string_instruction);
1655 return NULL;
1656 }
252b5132 1657
29b0f896
AM		 1658 return l;
1659}
252b5132 1660
29b0f896
AM		 1661static char *
1662parse_operands (l, mnemonic)
1663 char *l;
1664 const char *mnemonic;
1665{
1666 char *token_start;
3138f287 1667
29b0f896
AM		 1668 /* 1 if operand is pending after ','. */
1669 unsigned int expecting_operand = 0;
252b5132 1670
29b0f896
AM		 1671 /* Non-zero if operand parens not balanced. */
1672 unsigned int paren_not_balanced;
1673
1674 while (*l != END_OF_INSN)
1675 {
1676 /* Skip optional white space before operand. */
1677 if (is_space_char (*l))
1678 ++l;
1679 if (!is_operand_char (*l) && *l != END_OF_INSN)
1680 {
1681 as_bad (_("invalid character %s before operand %d"),
1682 output_invalid (*l),
1683 i.operands + 1);
1684 return NULL;
1685 }
1686 token_start = l; /* after white space */
1687 paren_not_balanced = 0;
1688 while (paren_not_balanced || *l != ',')
1689 {
1690 if (*l == END_OF_INSN)
1691 {
1692 if (paren_not_balanced)
1693 {
1694 if (!intel_syntax)
1695 as_bad (_("unbalanced parenthesis in operand %d."),
1696 i.operands + 1);
1697 else
1698 as_bad (_("unbalanced brackets in operand %d."),
1699 i.operands + 1);
1700 return NULL;
1701 }
1702 else
1703 break; /* we are done */
1704 }
1705 else if (!is_operand_char (*l) && !is_space_char (*l))
1706 {
1707 as_bad (_("invalid character %s in operand %d"),
1708 output_invalid (*l),
1709 i.operands + 1);
1710 return NULL;
1711 }
1712 if (!intel_syntax)
1713 {
1714 if (*l == '(')
1715 ++paren_not_balanced;
1716 if (*l == ')')
1717 --paren_not_balanced;
1718 }
1719 else
1720 {
1721 if (*l == '[')
1722 ++paren_not_balanced;
1723 if (*l == ']')
1724 --paren_not_balanced;
1725 }
1726 l++;
1727 }
1728 if (l != token_start)
1729 { /* Yes, we've read in another operand. */
1730 unsigned int operand_ok;
1731 this_operand = i.operands++;
1732 if (i.operands > MAX_OPERANDS)
1733 {
1734 as_bad (_("spurious operands; (%d operands/instruction max)"),
1735 MAX_OPERANDS);
1736 return NULL;
1737 }
1738 /* Now parse operand adding info to 'i' as we go along. */
1739 END_STRING_AND_SAVE (l);
1740
1741 if (intel_syntax)
1742 operand_ok =
1743 i386_intel_operand (token_start,
1744 intel_float_operand (mnemonic));
1745 else
1746 operand_ok = i386_operand (token_start);
1747
1748 RESTORE_END_STRING (l);
1749 if (!operand_ok)
1750 return NULL;
1751 }
1752 else
1753 {
1754 if (expecting_operand)
1755 {
1756 expecting_operand_after_comma:
1757 as_bad (_("expecting operand after ','; got nothing"));
1758 return NULL;
1759 }
1760 if (*l == ',')
1761 {
1762 as_bad (_("expecting operand before ','; got nothing"));
1763 return NULL;
1764 }
1765 }
7f3f1ea2 1766
29b0f896
AM		 1767 /* Now *l must be either ',' or END_OF_INSN. */
1768 if (*l == ',')
1769 {
1770 if (*++l == END_OF_INSN)
1771 {
1772 /* Just skip it, if it's \n complain. */
1773 goto expecting_operand_after_comma;
1774 }
1775 expecting_operand = 1;
1776 }
1777 }
1778 return l;
1779}
7f3f1ea2 1780
29b0f896
AM		 1781static void
1782swap_operands ()
1783{
1784 union i386_op temp_op;
1785 unsigned int temp_type;
1786 RELOC_ENUM temp_reloc;
1787 int xchg1 = 0;
1788 int xchg2 = 0;
252b5132 1789
29b0f896
AM		 1790 if (i.operands == 2)
1791 {
1792 xchg1 = 0;
1793 xchg2 = 1;
1794 }
1795 else if (i.operands == 3)
1796 {
1797 xchg1 = 0;
1798 xchg2 = 2;
1799 }
1800 temp_type = i.types[xchg2];
1801 i.types[xchg2] = i.types[xchg1];
1802 i.types[xchg1] = temp_type;
1803 temp_op = i.op[xchg2];
1804 i.op[xchg2] = i.op[xchg1];
1805 i.op[xchg1] = temp_op;
1806 temp_reloc = i.reloc[xchg2];
1807 i.reloc[xchg2] = i.reloc[xchg1];
1808 i.reloc[xchg1] = temp_reloc;
1809
1810 if (i.mem_operands == 2)
1811 {
1812 const seg_entry *temp_seg;
1813 temp_seg = i.seg[0];
1814 i.seg[0] = i.seg[1];
1815 i.seg[1] = temp_seg;
1816 }
1817}
252b5132 1818
29b0f896
AM		 1819/* Try to ensure constant immediates are represented in the smallest
1820 opcode possible. */
1821static void
1822optimize_imm ()
1823{
1824 char guess_suffix = 0;
1825 int op;
252b5132 1826
29b0f896
AM		 1827 if (i.suffix)
1828 guess_suffix = i.suffix;
1829 else if (i.reg_operands)
1830 {
1831 /* Figure out a suffix from the last register operand specified.
1832 We can't do this properly yet, ie. excluding InOutPortReg,
1833 but the following works for instructions with immediates.
1834 In any case, we can't set i.suffix yet. */
1835 for (op = i.operands; --op >= 0;)
1836 if (i.types[op] & Reg)
252b5132 1837 {
29b0f896
AM		 1838 if (i.types[op] & Reg8)
1839 guess_suffix = BYTE_MNEM_SUFFIX;
1840 else if (i.types[op] & Reg16)
1841 guess_suffix = WORD_MNEM_SUFFIX;
1842 else if (i.types[op] & Reg32)
1843 guess_suffix = LONG_MNEM_SUFFIX;
1844 else if (i.types[op] & Reg64)
1845 guess_suffix = QWORD_MNEM_SUFFIX;
1846 break;
252b5132 1847 }
29b0f896
AM		 1848 }
1849 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1850 guess_suffix = WORD_MNEM_SUFFIX;
1851
1852 for (op = i.operands; --op >= 0;)
1853 if (i.types[op] & Imm)
1854 {
1855 switch (i.op[op].imms->X_op)
252b5132 1856 {
29b0f896
AM		 1857 case O_constant:
1858 /* If a suffix is given, this operand may be shortened. */
1859 switch (guess_suffix)
252b5132 1860 {
29b0f896
AM		 1861 case LONG_MNEM_SUFFIX:
1862 i.types[op] |= Imm32 | Imm64;
1863 break;
1864 case WORD_MNEM_SUFFIX:
1865 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1866 break;
1867 case BYTE_MNEM_SUFFIX:
1868 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1869 break;
252b5132 1870 }
252b5132 1871
29b0f896
AM		 1872 /* If this operand is at most 16 bits, convert it
1873 to a signed 16 bit number before trying to see
1874 whether it will fit in an even smaller size.
1875 This allows a 16-bit operand such as $0xffe0 to
1876 be recognised as within Imm8S range. */
1877 if ((i.types[op] & Imm16)
1878 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1879 {
29b0f896
AM		 1880 i.op[op].imms->X_add_number =
1881 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1882 }
1883 if ((i.types[op] & Imm32)
1884 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1885 == 0))
1886 {
1887 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1888 ^ ((offsetT) 1 << 31))
1889 - ((offsetT) 1 << 31));
1890 }
1891 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1892
29b0f896
AM		 1893 /* We must avoid matching of Imm32 templates when 64bit
1894 only immediate is available. */
1895 if (guess_suffix == QWORD_MNEM_SUFFIX)
1896 i.types[op] &= ~Imm32;
1897 break;
252b5132 1898
29b0f896
AM		 1899 case O_absent:
1900 case O_register:
1901 abort ();
1902
1903 /* Symbols and expressions. */
1904 default:
1905 /* Convert symbolic operand to proper sizes for matching. */
1906 switch (guess_suffix)
1907 {
1908 case QWORD_MNEM_SUFFIX:
1909 i.types[op] = Imm64 | Imm32S;
1910 break;
1911 case LONG_MNEM_SUFFIX:
1912 i.types[op] = Imm32 | Imm64;
1913 break;
1914 case WORD_MNEM_SUFFIX:
1915 i.types[op] = Imm16 | Imm32 | Imm64;
1916 break;
1917 break;
1918 case BYTE_MNEM_SUFFIX:
1919 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1920 break;
1921 break;
252b5132 1922 }
29b0f896 1923 break;
252b5132 1924 }
29b0f896
AM		 1925 }
1926}
47926f60 1927
29b0f896
AM		 1928/* Try to use the smallest displacement type too. */
1929static void
1930optimize_disp ()
1931{
1932 int op;
3e73aa7c 1933
29b0f896
AM		 1934 for (op = i.operands; --op >= 0;)
1935 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1936 {
29b0f896
AM		 1937 offsetT disp = i.op[op].disps->X_add_number;
1938
1939 if (i.types[op] & Disp16)
252b5132 1940 {
29b0f896
AM		 1941 /* We know this operand is at most 16 bits, so
1942 convert to a signed 16 bit number before trying
1943 to see whether it will fit in an even smaller
1944 size. */
1945
1946 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1947 }
29b0f896 1948 else if (i.types[op] & Disp32)
252b5132 1949 {
29b0f896
AM		 1950 /* We know this operand is at most 32 bits, so convert to a
1951 signed 32 bit number before trying to see whether it will
1952 fit in an even smaller size. */
1953 disp &= (((offsetT) 2 << 31) - 1);
1954 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1955 }
29b0f896 1956 if (flag_code == CODE_64BIT)
252b5132 1957 {
29b0f896
AM		 1958 if (fits_in_signed_long (disp))
1959 i.types[op] |= Disp32S;
1960 if (fits_in_unsigned_long (disp))
1961 i.types[op] |= Disp32;
252b5132 1962 }
29b0f896
AM		 1963 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1964 && fits_in_signed_byte (disp))
1965 i.types[op] |= Disp8;
252b5132 1966 }
29b0f896
AM		 1967}
1968
1969static int
1970match_template ()
1971{
1972 /* Points to template once we've found it. */
1973 const template *t;
1974 unsigned int overlap0, overlap1, overlap2;
1975 unsigned int found_reverse_match;
1976 int suffix_check;
1977
1978#define MATCH(overlap, given, template) \
1979 ((overlap & ~JumpAbsolute) \
1980 && (((given) & (BaseIndex | JumpAbsolute)) \
1981 == ((overlap) & (BaseIndex | JumpAbsolute))))
1982
1983 /* If given types r0 and r1 are registers they must be of the same type
1984 unless the expected operand type register overlap is null.
1985 Note that Acc in a template matches every size of reg. */
1986#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1987 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1988 || ((g0) & Reg) == ((g1) & Reg) \
1989 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1990
1991 overlap0 = 0;
1992 overlap1 = 0;
1993 overlap2 = 0;
1994 found_reverse_match = 0;
1995 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1996 ? No_bSuf
1997 : (i.suffix == WORD_MNEM_SUFFIX
1998 ? No_wSuf
1999 : (i.suffix == SHORT_MNEM_SUFFIX
2000 ? No_sSuf
2001 : (i.suffix == LONG_MNEM_SUFFIX
2002 ? No_lSuf
2003 : (i.suffix == QWORD_MNEM_SUFFIX
2004 ? No_qSuf
2005 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2006 ? No_xSuf : 0))))));
2007
2008 for (t = current_templates->start;
2009 t < current_templates->end;
2010 t++)
2011 {
2012 /* Must have right number of operands. */
2013 if (i.operands != t->operands)
2014 continue;
2015
2016 /* Check the suffix, except for some instructions in intel mode. */
2017 if ((t->opcode_modifier & suffix_check)
2018 && !(intel_syntax
2019 && (t->opcode_modifier & IgnoreSize))
2020 && !(intel_syntax
2021 && t->base_opcode == 0xd9
2022 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2023 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2024 continue;
2025
2026 /* Do not verify operands when there are none. */
2027 else if (!t->operands)
2028 {
2029 if (t->cpu_flags & ~cpu_arch_flags)
2030 continue;
2031 /* We've found a match; break out of loop. */
2032 break;
2033 }
252b5132 2034
29b0f896
AM		 2035 overlap0 = i.types[0] & t->operand_types[0];
2036 switch (t->operands)
2037 {
2038 case 1:
2039 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2040 continue;
2041 break;
2042 case 2:
2043 case 3:
2044 overlap1 = i.types[1] & t->operand_types[1];
2045 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2046 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2047 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2048 t->operand_types[0],
2049 overlap1, i.types[1],
2050 t->operand_types[1]))
2051 {
2052 /* Check if other direction is valid ... */
2053 if ((t->opcode_modifier & (D | FloatD)) == 0)
2054 continue;
2055
2056 /* Try reversing direction of operands. */
2057 overlap0 = i.types[0] & t->operand_types[1];
2058 overlap1 = i.types[1] & t->operand_types[0];
2059 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2060 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2061 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2062 t->operand_types[1],
2063 overlap1, i.types[1],
2064 t->operand_types[0]))
2065 {
2066 /* Does not match either direction. */
2067 continue;
2068 }
2069 /* found_reverse_match holds which of D or FloatDR
2070 we've found. */
2071 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2072 }
2073 /* Found a forward 2 operand match here. */
2074 else if (t->operands == 3)
2075 {
2076 /* Here we make use of the fact that there are no
2077 reverse match 3 operand instructions, and all 3
2078 operand instructions only need to be checked for
2079 register consistency between operands 2 and 3. */
2080 overlap2 = i.types[2] & t->operand_types[2];
2081 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2082 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2083 t->operand_types[1],
2084 overlap2, i.types[2],
2085 t->operand_types[2]))
2086
2087 continue;
2088 }
2089 /* Found either forward/reverse 2 or 3 operand match here:
2090 slip through to break. */
2091 }
2092 if (t->cpu_flags & ~cpu_arch_flags)
2093 {
2094 found_reverse_match = 0;
2095 continue;
2096 }
2097 /* We've found a match; break out of loop. */
2098 break;
2099 }
2100
2101 if (t == current_templates->end)
2102 {
2103 /* We found no match. */
2104 as_bad (_("suffix or operands invalid for `%s'"),
2105 current_templates->start->name);
2106 return 0;
2107 }
252b5132 2108
29b0f896
AM		 2109 if (!quiet_warnings)
2110 {
2111 if (!intel_syntax
2112 && ((i.types[0] & JumpAbsolute)
2113 != (t->operand_types[0] & JumpAbsolute)))
2114 {
2115 as_warn (_("indirect %s without `*'"), t->name);
2116 }
2117
2118 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2119 == (IsPrefix | IgnoreSize))
2120 {
2121 /* Warn them that a data or address size prefix doesn't
2122 affect assembly of the next line of code. */
2123 as_warn (_("stand-alone `%s' prefix"), t->name);
2124 }
2125 }
2126
2127 /* Copy the template we found. */
2128 i.tm = *t;
2129 if (found_reverse_match)
2130 {
2131 /* If we found a reverse match we must alter the opcode
2132 direction bit. found_reverse_match holds bits to change
2133 (different for int & float insns). */
2134
2135 i.tm.base_opcode ^= found_reverse_match;
2136
2137 i.tm.operand_types[0] = t->operand_types[1];
2138 i.tm.operand_types[1] = t->operand_types[0];
2139 }
2140
2141 return 1;
2142}
2143
2144static int
2145check_string ()
2146{
2147 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2148 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2149 {
2150 if (i.seg[0] != NULL && i.seg[0] != &es)
2151 {
2152 as_bad (_("`%s' operand %d must use `%%es' segment"),
2153 i.tm.name,
2154 mem_op + 1);
2155 return 0;
2156 }
2157 /* There's only ever one segment override allowed per instruction.
2158 This instruction possibly has a legal segment override on the
2159 second operand, so copy the segment to where non-string
2160 instructions store it, allowing common code. */
2161 i.seg[0] = i.seg[1];
2162 }
2163 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2164 {
2165 if (i.seg[1] != NULL && i.seg[1] != &es)
2166 {
2167 as_bad (_("`%s' operand %d must use `%%es' segment"),
2168 i.tm.name,
2169 mem_op + 2);
2170 return 0;
2171 }
2172 }
2173 return 1;
2174}
2175
2176static int
2177process_suffix ()
2178{
2179 /* If matched instruction specifies an explicit instruction mnemonic
2180 suffix, use it. */
2181 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2182 {
2183 if (i.tm.opcode_modifier & Size16)
2184 i.suffix = WORD_MNEM_SUFFIX;
2185 else if (i.tm.opcode_modifier & Size64)
2186 i.suffix = QWORD_MNEM_SUFFIX;
2187 else
2188 i.suffix = LONG_MNEM_SUFFIX;
2189 }
2190 else if (i.reg_operands)
2191 {
2192 /* If there's no instruction mnemonic suffix we try to invent one
2193 based on register operands. */
2194 if (!i.suffix)
2195 {
2196 /* We take i.suffix from the last register operand specified,
2197 Destination register type is more significant than source
2198 register type. */
2199 int op;
2200 for (op = i.operands; --op >= 0;)
2201 if ((i.types[op] & Reg)
2202 && !(i.tm.operand_types[op] & InOutPortReg))
2203 {
2204 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2205 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2206 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2207 LONG_MNEM_SUFFIX);
2208 break;
2209 }
2210 }
2211 else if (i.suffix == BYTE_MNEM_SUFFIX)
2212 {
2213 if (!check_byte_reg ())
2214 return 0;
2215 }
2216 else if (i.suffix == LONG_MNEM_SUFFIX)
2217 {
2218 if (!check_long_reg ())
2219 return 0;
2220 }
2221 else if (i.suffix == QWORD_MNEM_SUFFIX)
2222 {
2223 if (!check_qword_reg ())
2224 return 0;
2225 }
2226 else if (i.suffix == WORD_MNEM_SUFFIX)
2227 {
2228 if (!check_word_reg ())
2229 return 0;
2230 }
2231 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2232 /* Do nothing if the instruction is going to ignore the prefix. */
2233 ;
2234 else
2235 abort ();
2236 }
2237 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2238 {
2239 i.suffix = stackop_size;
2240 }
252b5132 2241
29b0f896
AM		 2242 /* Change the opcode based on the operand size given by i.suffix;
2243 We need not change things for byte insns. */
252b5132 2244
29b0f896
AM		 2245 if (!i.suffix && (i.tm.opcode_modifier & W))
2246 {
2247 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2248 return 0;
2249 }
252b5132 2250
29b0f896
AM		 2251 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2252 {
2253 /* It's not a byte, select word/dword operation. */
2254 if (i.tm.opcode_modifier & W)
2255 {
2256 if (i.tm.opcode_modifier & ShortForm)
2257 i.tm.base_opcode |= 8;
2258 else
2259 i.tm.base_opcode |= 1;
2260 }
0f3f3d8b 2261
29b0f896
AM		 2262 /* Now select between word & dword operations via the operand
2263 size prefix, except for instructions that will ignore this
2264 prefix anyway. */
2265 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2266 && !(i.tm.opcode_modifier & IgnoreSize)
2267 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2268 || (flag_code == CODE_64BIT
2269 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2270 {
2271 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2272 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2273 prefix = ADDR_PREFIX_OPCODE;
252b5132 2274
29b0f896
AM		 2275 if (!add_prefix (prefix))
2276 return 0;
24eab124 2277 }
252b5132 2278
29b0f896
AM		 2279 /* Set mode64 for an operand. */
2280 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2281 && flag_code == CODE_64BIT
29b0f896 2282 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2283 i.rex |= REX_MODE64;
3e73aa7c 2284
29b0f896
AM		 2285 /* Size floating point instruction. */
2286 if (i.suffix == LONG_MNEM_SUFFIX)
2287 {
2288 if (i.tm.opcode_modifier & FloatMF)
2289 i.tm.base_opcode ^= 4;
2290 }
2291 }
7ecd2f8b 2292
29b0f896
AM		 2293 return 1;
2294}
3e73aa7c 2295
29b0f896
AM		 2296static int
2297check_byte_reg ()
2298{
2299 int op;
2300 for (op = i.operands; --op >= 0;)
2301 {
2302 /* If this is an eight bit register, it's OK. If it's the 16 or
2303 32 bit version of an eight bit register, we will just use the
2304 low portion, and that's OK too. */
2305 if (i.types[op] & Reg8)
2306 continue;
2307
2308 /* movzx and movsx should not generate this warning. */
2309 if (intel_syntax
2310 && (i.tm.base_opcode == 0xfb7
2311 || i.tm.base_opcode == 0xfb6
2312 || i.tm.base_opcode == 0x63
2313 || i.tm.base_opcode == 0xfbe
2314 || i.tm.base_opcode == 0xfbf))
2315 continue;
2316
2317 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2318#if 0
2319 /* Check that the template allows eight bit regs. This
2320 kills insns such as `orb $1,%edx', which maybe should be
2321 allowed. */
2322 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2323#endif
2324 )
2325 {
2326 /* Prohibit these changes in the 64bit mode, since the
2327 lowering is more complicated. */
2328 if (flag_code == CODE_64BIT
2329 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2330 {
0f3f3d8b 2331 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2332 i.op[op].regs->reg_name,
2333 i.suffix);
2334 return 0;
2335 }
2336#if REGISTER_WARNINGS
2337 if (!quiet_warnings
2338 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2339 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2340 (i.op[op].regs + (i.types[op] & Reg16
2341 ? REGNAM_AL - REGNAM_AX
2342 : REGNAM_AL - REGNAM_EAX))->reg_name,
2343 i.op[op].regs->reg_name,
2344 i.suffix);
2345#endif
2346 continue;
2347 }
2348 /* Any other register is bad. */
2349 if (i.types[op] & (Reg | RegMMX | RegXMM
2350 | SReg2 | SReg3
2351 | Control | Debug | Test
2352 | FloatReg | FloatAcc))
2353 {
2354 as_bad (_("`%%%s' not allowed with `%s%c'"),
2355 i.op[op].regs->reg_name,
2356 i.tm.name,
2357 i.suffix);
2358 return 0;
2359 }
2360 }
2361 return 1;
2362}
2363
2364static int
2365check_long_reg ()
2366{
2367 int op;
2368
2369 for (op = i.operands; --op >= 0;)
2370 /* Reject eight bit registers, except where the template requires
2371 them. (eg. movzb) */
2372 if ((i.types[op] & Reg8) != 0
2373 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2374 {
2375 as_bad (_("`%%%s' not allowed with `%s%c'"),
2376 i.op[op].regs->reg_name,
2377 i.tm.name,
2378 i.suffix);
2379 return 0;
2380 }
2381 /* Warn if the e prefix on a general reg is missing. */
2382 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2383 && (i.types[op] & Reg16) != 0
2384 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2385 {
2386 /* Prohibit these changes in the 64bit mode, since the
2387 lowering is more complicated. */
2388 if (flag_code == CODE_64BIT)
252b5132 2389 {
0f3f3d8b 2390 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2391 i.op[op].regs->reg_name,
2392 i.suffix);
2393 return 0;
252b5132 2394 }
29b0f896
AM		 2395#if REGISTER_WARNINGS
2396 else
2397 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2398 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2399 i.op[op].regs->reg_name,
2400 i.suffix);
2401#endif
252b5132 2402 }
29b0f896
AM		 2403 /* Warn if the r prefix on a general reg is missing. */
2404 else if ((i.types[op] & Reg64) != 0
2405 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2406 {
0f3f3d8b 2407 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2408 i.op[op].regs->reg_name,
2409 i.suffix);
2410 return 0;
2411 }
2412 return 1;
2413}
252b5132 2414
29b0f896
AM		 2415static int
2416check_qword_reg ()
2417{
2418 int op;
252b5132 2419
29b0f896
AM		 2420 for (op = i.operands; --op >= 0; )
2421 /* Reject eight bit registers, except where the template requires
2422 them. (eg. movzb) */
2423 if ((i.types[op] & Reg8) != 0
2424 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2425 {
2426 as_bad (_("`%%%s' not allowed with `%s%c'"),
2427 i.op[op].regs->reg_name,
2428 i.tm.name,
2429 i.suffix);
2430 return 0;
2431 }
2432 /* Warn if the e prefix on a general reg is missing. */
2433 else if (((i.types[op] & Reg16) != 0
2434 || (i.types[op] & Reg32) != 0)
2435 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2436 {
2437 /* Prohibit these changes in the 64bit mode, since the
2438 lowering is more complicated. */
0f3f3d8b 2439 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2440 i.op[op].regs->reg_name,
2441 i.suffix);
2442 return 0;
252b5132 2443 }
29b0f896
AM		 2444 return 1;
2445}
252b5132 2446
29b0f896
AM		 2447static int
2448check_word_reg ()
2449{
2450 int op;
2451 for (op = i.operands; --op >= 0;)
2452 /* Reject eight bit registers, except where the template requires
2453 them. (eg. movzb) */
2454 if ((i.types[op] & Reg8) != 0
2455 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2456 {
2457 as_bad (_("`%%%s' not allowed with `%s%c'"),
2458 i.op[op].regs->reg_name,
2459 i.tm.name,
2460 i.suffix);
2461 return 0;
2462 }
2463 /* Warn if the e prefix on a general reg is present. */
2464 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2465 && (i.types[op] & Reg32) != 0
2466 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2467 {
29b0f896
AM		 2468 /* Prohibit these changes in the 64bit mode, since the
2469 lowering is more complicated. */
2470 if (flag_code == CODE_64BIT)
252b5132 2471 {
0f3f3d8b 2472 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2473 i.op[op].regs->reg_name,
2474 i.suffix);
2475 return 0;
252b5132 2476 }
29b0f896
AM		 2477 else
2478#if REGISTER_WARNINGS
2479 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2480 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2481 i.op[op].regs->reg_name,
2482 i.suffix);
2483#endif
2484 }
2485 return 1;
2486}
252b5132 2487
29b0f896
AM		 2488static int
2489finalize_imm ()
2490{
2491 unsigned int overlap0, overlap1, overlap2;
2492
2493 overlap0 = i.types[0] & i.tm.operand_types[0];
2494 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2495 && overlap0 != Imm8 && overlap0 != Imm8S
2496 && overlap0 != Imm16 && overlap0 != Imm32S
2497 && overlap0 != Imm32 && overlap0 != Imm64)
2498 {
2499 if (i.suffix)
2500 {
2501 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2502 ? Imm8 | Imm8S
2503 : (i.suffix == WORD_MNEM_SUFFIX
2504 ? Imm16
2505 : (i.suffix == QWORD_MNEM_SUFFIX
2506 ? Imm64 | Imm32S
2507 : Imm32)));
2508 }
2509 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2510 || overlap0 == (Imm16 | Imm32)
2511 || overlap0 == (Imm16 | Imm32S))
2512 {
2513 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2514 ? Imm16 : Imm32S);
2515 }
2516 if (overlap0 != Imm8 && overlap0 != Imm8S
2517 && overlap0 != Imm16 && overlap0 != Imm32S
2518 && overlap0 != Imm32 && overlap0 != Imm64)
2519 {
2520 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2521 return 0;
2522 }
2523 }
2524 i.types[0] = overlap0;
2525
2526 overlap1 = i.types[1] & i.tm.operand_types[1];
2527 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2528 && overlap1 != Imm8 && overlap1 != Imm8S
2529 && overlap1 != Imm16 && overlap1 != Imm32S
2530 && overlap1 != Imm32 && overlap1 != Imm64)
2531 {
2532 if (i.suffix)
2533 {
2534 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2535 ? Imm8 | Imm8S
2536 : (i.suffix == WORD_MNEM_SUFFIX
2537 ? Imm16
2538 : (i.suffix == QWORD_MNEM_SUFFIX
2539 ? Imm64 | Imm32S
2540 : Imm32)));
2541 }
2542 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2543 || overlap1 == (Imm16 | Imm32)
2544 || overlap1 == (Imm16 | Imm32S))
2545 {
2546 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2547 ? Imm16 : Imm32S);
2548 }
2549 if (overlap1 != Imm8 && overlap1 != Imm8S
2550 && overlap1 != Imm16 && overlap1 != Imm32S
2551 && overlap1 != Imm32 && overlap1 != Imm64)
2552 {
2553 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2554 return 0;
2555 }
2556 }
2557 i.types[1] = overlap1;
2558
2559 overlap2 = i.types[2] & i.tm.operand_types[2];
2560 assert ((overlap2 & Imm) == 0);
2561 i.types[2] = overlap2;
2562
2563 return 1;
2564}
2565
2566static int
2567process_operands ()
2568{
2569 /* Default segment register this instruction will use for memory
2570 accesses. 0 means unknown. This is only for optimizing out
2571 unnecessary segment overrides. */
2572 const seg_entry *default_seg = 0;
2573
2574 /* The imul $imm, %reg instruction is converted into
2575 imul $imm, %reg, %reg, and the clr %reg instruction
2576 is converted into xor %reg, %reg. */
2577 if (i.tm.opcode_modifier & regKludge)
2578 {
2579 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2580 /* Pretend we saw the extra register operand. */
2581 assert (i.op[first_reg_op + 1].regs == 0);
2582 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2583 i.types[first_reg_op + 1] = i.types[first_reg_op];
2584 i.reg_operands = 2;
2585 }
2586
2587 if (i.tm.opcode_modifier & ShortForm)
2588 {
2589 /* The register or float register operand is in operand 0 or 1. */
2590 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2591 /* Register goes in low 3 bits of opcode. */
2592 i.tm.base_opcode |= i.op[op].regs->reg_num;
2593 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2594 i.rex |= REX_EXTZ;
2595 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2596 {
2597 /* Warn about some common errors, but press on regardless.
2598 The first case can be generated by gcc (<= 2.8.1). */
2599 if (i.operands == 2)
2600 {
2601 /* Reversed arguments on faddp, fsubp, etc. */
2602 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2603 i.op[1].regs->reg_name,
2604 i.op[0].regs->reg_name);
2605 }
2606 else
2607 {
2608 /* Extraneous `l' suffix on fp insn. */
2609 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2610 i.op[0].regs->reg_name);
2611 }
2612 }
2613 }
2614 else if (i.tm.opcode_modifier & Modrm)
2615 {
2616 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2617 must be put into the modrm byte). Now, we make the modrm and
2618 index base bytes based on all the info we've collected. */
29b0f896
AM		 2619
2620 default_seg = build_modrm_byte ();
2621 }
2622 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2623 {
2624 if (i.tm.base_opcode == POP_SEG_SHORT
2625 && i.op[0].regs->reg_num == 1)
2626 {
2627 as_bad (_("you can't `pop %%cs'"));
2628 return 0;
2629 }
2630 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2631 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2632 i.rex |= REX_EXTZ;
2633 }
2634 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2635 {
2636 default_seg = &ds;
2637 }
2638 else if ((i.tm.opcode_modifier & IsString) != 0)
2639 {
2640 /* For the string instructions that allow a segment override
2641 on one of their operands, the default segment is ds. */
2642 default_seg = &ds;
2643 }
2644
52271982
AM		 2645 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2646 as_warn (_("segment override on `lea' is ineffectual"));
2647
2648 /* If a segment was explicitly specified, and the specified segment
2649 is not the default, use an opcode prefix to select it. If we
2650 never figured out what the default segment is, then default_seg
2651 will be zero at this point, and the specified segment prefix will
2652 always be used. */
29b0f896
AM		 2653 if ((i.seg[0]) && (i.seg[0] != default_seg))
2654 {
2655 if (!add_prefix (i.seg[0]->seg_prefix))
2656 return 0;
2657 }
2658 return 1;
2659}
2660
2661static const seg_entry *
2662build_modrm_byte ()
2663{
2664 const seg_entry *default_seg = 0;
2665
2666 /* i.reg_operands MUST be the number of real register operands;
2667 implicit registers do not count. */
2668 if (i.reg_operands == 2)
2669 {
2670 unsigned int source, dest;
2671 source = ((i.types[0]
2672 & (Reg | RegMMX | RegXMM
2673 | SReg2 | SReg3
2674 | Control | Debug | Test))
2675 ? 0 : 1);
2676 dest = source + 1;
2677
2678 i.rm.mode = 3;
2679 /* One of the register operands will be encoded in the i.tm.reg
2680 field, the other in the combined i.tm.mode and i.tm.regmem
2681 fields. If no form of this instruction supports a memory
2682 destination operand, then we assume the source operand may
2683 sometimes be a memory operand and so we need to store the
2684 destination in the i.rm.reg field. */
2685 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2686 {
2687 i.rm.reg = i.op[dest].regs->reg_num;
2688 i.rm.regmem = i.op[source].regs->reg_num;
2689 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2690 i.rex |= REX_EXTX;
2691 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2692 i.rex |= REX_EXTZ;
2693 }
2694 else
2695 {
2696 i.rm.reg = i.op[source].regs->reg_num;
2697 i.rm.regmem = i.op[dest].regs->reg_num;
2698 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2699 i.rex |= REX_EXTZ;
2700 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2701 i.rex |= REX_EXTX;
2702 }
2703 }
2704 else
2705 { /* If it's not 2 reg operands... */
2706 if (i.mem_operands)
2707 {
2708 unsigned int fake_zero_displacement = 0;
2709 unsigned int op = ((i.types[0] & AnyMem)
2710 ? 0
2711 : (i.types[1] & AnyMem) ? 1 : 2);
2712
2713 default_seg = &ds;
2714
2715 if (i.base_reg == 0)
2716 {
2717 i.rm.mode = 0;
2718 if (!i.disp_operands)
2719 fake_zero_displacement = 1;
2720 if (i.index_reg == 0)
2721 {
2722 /* Operand is just <disp> */
2723 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2724 && (flag_code != CODE_64BIT))
2725 {
2726 i.rm.regmem = NO_BASE_REGISTER_16;
2727 i.types[op] &= ~Disp;
2728 i.types[op] |= Disp16;
2729 }
2730 else if (flag_code != CODE_64BIT
2731 || (i.prefix[ADDR_PREFIX] != 0))
2732 {
2733 i.rm.regmem = NO_BASE_REGISTER;
2734 i.types[op] &= ~Disp;
2735 i.types[op] |= Disp32;
2736 }
2737 else
2738 {
2739 /* 64bit mode overwrites the 32bit absolute
2740 addressing by RIP relative addressing and
2741 absolute addressing is encoded by one of the
2742 redundant SIB forms. */
2743 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2744 i.sib.base = NO_BASE_REGISTER;
2745 i.sib.index = NO_INDEX_REGISTER;
2746 i.types[op] &= ~Disp;
2747 i.types[op] |= Disp32S;
2748 }
2749 }
2750 else /* !i.base_reg && i.index_reg */
2751 {
2752 i.sib.index = i.index_reg->reg_num;
2753 i.sib.base = NO_BASE_REGISTER;
2754 i.sib.scale = i.log2_scale_factor;
2755 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2756 i.types[op] &= ~Disp;
2757 if (flag_code != CODE_64BIT)
2758 i.types[op] |= Disp32; /* Must be 32 bit */
2759 else
2760 i.types[op] |= Disp32S;
2761 if ((i.index_reg->reg_flags & RegRex) != 0)
2762 i.rex |= REX_EXTY;
2763 }
2764 }
2765 /* RIP addressing for 64bit mode. */
2766 else if (i.base_reg->reg_type == BaseIndex)
2767 {
2768 i.rm.regmem = NO_BASE_REGISTER;
2769 i.types[op] &= ~Disp;
2770 i.types[op] |= Disp32S;
2771 i.flags[op] = Operand_PCrel;
2772 }
2773 else if (i.base_reg->reg_type & Reg16)
2774 {
2775 switch (i.base_reg->reg_num)
2776 {
2777 case 3: /* (%bx) */
2778 if (i.index_reg == 0)
2779 i.rm.regmem = 7;
2780 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2781 i.rm.regmem = i.index_reg->reg_num - 6;
2782 break;
2783 case 5: /* (%bp) */
2784 default_seg = &ss;
2785 if (i.index_reg == 0)
2786 {
2787 i.rm.regmem = 6;
2788 if ((i.types[op] & Disp) == 0)
2789 {
2790 /* fake (%bp) into 0(%bp) */
2791 i.types[op] |= Disp8;
252b5132 2792 fake_zero_displacement = 1;
29b0f896
AM		 2793 }
2794 }
2795 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2796 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2797 break;
2798 default: /* (%si) -> 4 or (%di) -> 5 */
2799 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2800 }
2801 i.rm.mode = mode_from_disp_size (i.types[op]);
2802 }
2803 else /* i.base_reg and 32/64 bit mode */
2804 {
2805 if (flag_code == CODE_64BIT
2806 && (i.types[op] & Disp))
2807 {
2808 if (i.types[op] & Disp8)
2809 i.types[op] = Disp8 | Disp32S;
2810 else
2811 i.types[op] = Disp32S;
2812 }
2813 i.rm.regmem = i.base_reg->reg_num;
2814 if ((i.base_reg->reg_flags & RegRex) != 0)
2815 i.rex |= REX_EXTZ;
2816 i.sib.base = i.base_reg->reg_num;
2817 /* x86-64 ignores REX prefix bit here to avoid decoder
2818 complications. */
2819 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2820 {
2821 default_seg = &ss;
2822 if (i.disp_operands == 0)
2823 {
2824 fake_zero_displacement = 1;
2825 i.types[op] |= Disp8;
2826 }
2827 }
2828 else if (i.base_reg->reg_num == ESP_REG_NUM)
2829 {
2830 default_seg = &ss;
2831 }
2832 i.sib.scale = i.log2_scale_factor;
2833 if (i.index_reg == 0)
2834 {
2835 /* <disp>(%esp) becomes two byte modrm with no index
2836 register. We've already stored the code for esp
2837 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2838 Any base register besides %esp will not use the
2839 extra modrm byte. */
2840 i.sib.index = NO_INDEX_REGISTER;
2841#if !SCALE1_WHEN_NO_INDEX
2842 /* Another case where we force the second modrm byte. */
2843 if (i.log2_scale_factor)
2844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2845#endif
29b0f896
AM		 2846 }
2847 else
2848 {
2849 i.sib.index = i.index_reg->reg_num;
2850 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2851 if ((i.index_reg->reg_flags & RegRex) != 0)
2852 i.rex |= REX_EXTY;
2853 }
2854 i.rm.mode = mode_from_disp_size (i.types[op]);
2855 }
252b5132 2856
29b0f896
AM		 2857 if (fake_zero_displacement)
2858 {
2859 /* Fakes a zero displacement assuming that i.types[op]
2860 holds the correct displacement size. */
2861 expressionS *exp;
2862
2863 assert (i.op[op].disps == 0);
2864 exp = &disp_expressions[i.disp_operands++];
2865 i.op[op].disps = exp;
2866 exp->X_op = O_constant;
2867 exp->X_add_number = 0;
2868 exp->X_add_symbol = (symbolS *) 0;
2869 exp->X_op_symbol = (symbolS *) 0;
2870 }
2871 }
252b5132 2872
29b0f896
AM		 2873 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2874 (if any) based on i.tm.extension_opcode. Again, we must be
2875 careful to make sure that segment/control/debug/test/MMX
2876 registers are coded into the i.rm.reg field. */
2877 if (i.reg_operands)
2878 {
2879 unsigned int op =
2880 ((i.types[0]
2881 & (Reg | RegMMX | RegXMM
2882 | SReg2 | SReg3
2883 | Control | Debug | Test))
2884 ? 0
2885 : ((i.types[1]
2886 & (Reg | RegMMX | RegXMM
2887 | SReg2 | SReg3
2888 | Control | Debug | Test))
2889 ? 1
2890 : 2));
2891 /* If there is an extension opcode to put here, the register
2892 number must be put into the regmem field. */
2893 if (i.tm.extension_opcode != None)
2894 {
2895 i.rm.regmem = i.op[op].regs->reg_num;
2896 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2897 i.rex |= REX_EXTZ;
2898 }
2899 else
2900 {
2901 i.rm.reg = i.op[op].regs->reg_num;
2902 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2903 i.rex |= REX_EXTX;
2904 }
252b5132 2905
29b0f896
AM		 2906 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2907 must set it to 3 to indicate this is a register operand
2908 in the regmem field. */
2909 if (!i.mem_operands)
2910 i.rm.mode = 3;
2911 }
252b5132 2912
29b0f896
AM		 2913 /* Fill in i.rm.reg field with extension opcode (if any). */
2914 if (i.tm.extension_opcode != None)
2915 i.rm.reg = i.tm.extension_opcode;
2916 }
2917 return default_seg;
2918}
252b5132 2919
29b0f896
AM		 2920static void
2921output_branch ()
2922{
2923 char *p;
2924 int code16;
2925 int prefix;
2926 relax_substateT subtype;
2927 symbolS *sym;
2928 offsetT off;
2929
2930 code16 = 0;
2931 if (flag_code == CODE_16BIT)
2932 code16 = CODE16;
2933
2934 prefix = 0;
2935 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2936 {
29b0f896
AM		 2937 prefix = 1;
2938 i.prefixes -= 1;
2939 code16 ^= CODE16;
252b5132 2940 }
29b0f896
AM		 2941 /* Pentium4 branch hints. */
2942 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2943 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2944 {
29b0f896
AM		 2945 prefix++;
2946 i.prefixes--;
2947 }
2948 if (i.prefix[REX_PREFIX] != 0)
2949 {
2950 prefix++;
2951 i.prefixes--;
2f66722d
AM		 2952 }
2953
29b0f896
AM		 2954 if (i.prefixes != 0 && !intel_syntax)
2955 as_warn (_("skipping prefixes on this instruction"));
2956
2957 /* It's always a symbol; End frag & setup for relax.
2958 Make sure there is enough room in this frag for the largest
2959 instruction we may generate in md_convert_frag. This is 2
2960 bytes for the opcode and room for the prefix and largest
2961 displacement. */
2962 frag_grow (prefix + 2 + 4);
2963 /* Prefix and 1 opcode byte go in fr_fix. */
2964 p = frag_more (prefix + 1);
2965 if (i.prefix[DATA_PREFIX] != 0)
2966 *p++ = DATA_PREFIX_OPCODE;
2967 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2968 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2969 *p++ = i.prefix[SEG_PREFIX];
2970 if (i.prefix[REX_PREFIX] != 0)
2971 *p++ = i.prefix[REX_PREFIX];
2972 *p = i.tm.base_opcode;
2973
2974 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2975 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2976 else if ((cpu_arch_flags & Cpu386) != 0)
2977 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2978 else
2979 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2980 subtype |= code16;
3e73aa7c 2981
29b0f896
AM		 2982 sym = i.op[0].disps->X_add_symbol;
2983 off = i.op[0].disps->X_add_number;
3e73aa7c 2984
29b0f896
AM		 2985 if (i.op[0].disps->X_op != O_constant
2986 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2987 {
29b0f896
AM		 2988 /* Handle complex expressions. */
2989 sym = make_expr_symbol (i.op[0].disps);
2990 off = 0;
2991 }
3e73aa7c 2992
29b0f896
AM		 2993 /* 1 possible extra opcode + 4 byte displacement go in var part.
2994 Pass reloc in fr_var. */
2995 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2996}
3e73aa7c 2997
29b0f896
AM		 2998static void
2999output_jump ()
3000{
3001 char *p;
3002 int size;
3003
3004 if (i.tm.opcode_modifier & JumpByte)
3005 {
3006 /* This is a loop or jecxz type instruction. */
3007 size = 1;
3008 if (i.prefix[ADDR_PREFIX] != 0)
3009 {
3010 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3011 i.prefixes -= 1;
3012 }
3013 /* Pentium4 branch hints. */
3014 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3015 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3016 {
3017 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3018 i.prefixes--;
3e73aa7c
JH		 3019 }
3020 }
29b0f896
AM		 3021 else
3022 {
3023 int code16;
3e73aa7c 3024
29b0f896
AM		 3025 code16 = 0;
3026 if (flag_code == CODE_16BIT)
3027 code16 = CODE16;
3e73aa7c 3028
29b0f896
AM		 3029 if (i.prefix[DATA_PREFIX] != 0)
3030 {
3031 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3032 i.prefixes -= 1;
3033 code16 ^= CODE16;
3034 }
252b5132 3035
29b0f896
AM		 3036 size = 4;
3037 if (code16)
3038 size = 2;
3039 }
9fcc94b6 3040
29b0f896
AM		 3041 if (i.prefix[REX_PREFIX] != 0)
3042 {
3043 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3044 i.prefixes -= 1;
3045 }
252b5132 3046
29b0f896
AM		 3047 if (i.prefixes != 0 && !intel_syntax)
3048 as_warn (_("skipping prefixes on this instruction"));
e0890092 3049
29b0f896
AM		 3050 p = frag_more (1 + size);
3051 *p++ = i.tm.base_opcode;
e0890092 3052
062cd5e7
AS		 3053 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3054 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3055}
e0890092 3056
29b0f896
AM		 3057static void
3058output_interseg_jump ()
3059{
3060 char *p;
3061 int size;
3062 int prefix;
3063 int code16;
252b5132 3064
29b0f896
AM		 3065 code16 = 0;
3066 if (flag_code == CODE_16BIT)
3067 code16 = CODE16;
a217f122 3068
29b0f896
AM		 3069 prefix = 0;
3070 if (i.prefix[DATA_PREFIX] != 0)
3071 {
3072 prefix = 1;
3073 i.prefixes -= 1;
3074 code16 ^= CODE16;
3075 }
3076 if (i.prefix[REX_PREFIX] != 0)
3077 {
3078 prefix++;
3079 i.prefixes -= 1;
3080 }
252b5132 3081
29b0f896
AM		 3082 size = 4;
3083 if (code16)
3084 size = 2;
252b5132 3085
29b0f896
AM		 3086 if (i.prefixes != 0 && !intel_syntax)
3087 as_warn (_("skipping prefixes on this instruction"));
252b5132 3088
29b0f896
AM		 3089 /* 1 opcode; 2 segment; offset */
3090 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3091
29b0f896
AM		 3092 if (i.prefix[DATA_PREFIX] != 0)
3093 *p++ = DATA_PREFIX_OPCODE;
252b5132 3094
29b0f896
AM		 3095 if (i.prefix[REX_PREFIX] != 0)
3096 *p++ = i.prefix[REX_PREFIX];
252b5132 3097
29b0f896
AM		 3098 *p++ = i.tm.base_opcode;
3099 if (i.op[1].imms->X_op == O_constant)
3100 {
3101 offsetT n = i.op[1].imms->X_add_number;
252b5132 3102
29b0f896
AM		 3103 if (size == 2
3104 && !fits_in_unsigned_word (n)
3105 && !fits_in_signed_word (n))
3106 {
3107 as_bad (_("16-bit jump out of range"));
3108 return;
3109 }
3110 md_number_to_chars (p, n, size);
3111 }
3112 else
3113 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3114 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3115 if (i.op[0].imms->X_op != O_constant)
3116 as_bad (_("can't handle non absolute segment in `%s'"),
3117 i.tm.name);
3118 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3119}
a217f122 3120
2bbd9c25 3121
29b0f896
AM		 3122static void
3123output_insn ()
3124{
2bbd9c25
JJ		 3125 fragS *insn_start_frag;
3126 offsetT insn_start_off;
3127
29b0f896
AM		 3128 /* Tie dwarf2 debug info to the address at the start of the insn.
3129 We can't do this after the insn has been output as the current
3130 frag may have been closed off. eg. by frag_var. */
3131 dwarf2_emit_insn (0);
3132
2bbd9c25
JJ		 3133 insn_start_frag = frag_now;
3134 insn_start_off = frag_now_fix ();
3135
29b0f896
AM		 3136 /* Output jumps. */
3137 if (i.tm.opcode_modifier & Jump)
3138 output_branch ();
3139 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3140 output_jump ();
3141 else if (i.tm.opcode_modifier & JumpInterSegment)
3142 output_interseg_jump ();
3143 else
3144 {
3145 /* Output normal instructions here. */
3146 char *p;
3147 unsigned char *q;
252b5132 3148
29b0f896
AM		 3149 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3150 byte for the SSE instructions to specify a prefix they require. */
3151 if (i.tm.base_opcode & 0xff0000)
3152 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3153
29b0f896
AM		 3154 /* The prefix bytes. */
3155 for (q = i.prefix;
3156 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3157 q++)
3158 {
3159 if (*q)
3160 {
3161 p = frag_more (1);
3162 md_number_to_chars (p, (valueT) *q, 1);
3163 }
3164 }
252b5132 3165
29b0f896
AM		 3166 /* Now the opcode; be careful about word order here! */
3167 if (fits_in_unsigned_byte (i.tm.base_opcode))
3168 {
3169 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3170 }
3171 else
3172 {
3173 p = frag_more (2);
3174 /* Put out high byte first: can't use md_number_to_chars! */
3175 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3176 *p = i.tm.base_opcode & 0xff;
3177 }
3e73aa7c 3178
29b0f896
AM		 3179 /* Now the modrm byte and sib byte (if present). */
3180 if (i.tm.opcode_modifier & Modrm)
3181 {
3182 p = frag_more (1);
3183 md_number_to_chars (p,
3184 (valueT) (i.rm.regmem << 0
3185 | i.rm.reg << 3
3186 | i.rm.mode << 6),
3187 1);
3188 /* If i.rm.regmem == ESP (4)
3189 && i.rm.mode != (Register mode)
3190 && not 16 bit
3191 ==> need second modrm byte. */
3192 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3193 && i.rm.mode != 3
3194 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3195 {
3196 p = frag_more (1);
3197 md_number_to_chars (p,
3198 (valueT) (i.sib.base << 0
3199 | i.sib.index << 3
3200 | i.sib.scale << 6),
3201 1);
3202 }
3203 }
3e73aa7c 3204
29b0f896 3205 if (i.disp_operands)
2bbd9c25 3206 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3207
29b0f896 3208 if (i.imm_operands)
2bbd9c25 3209 output_imm (insn_start_frag, insn_start_off);
29b0f896 3210 }
252b5132 3211
29b0f896
AM		 3212#ifdef DEBUG386
3213 if (flag_debug)
3214 {
3215 pi (line, &i);
3216 }
3217#endif /* DEBUG386 */
3218}
252b5132 3219
29b0f896 3220static void
2bbd9c25
JJ		 3221output_disp (insn_start_frag, insn_start_off)
3222 fragS *insn_start_frag;
3223 offsetT insn_start_off;
29b0f896
AM		 3224{
3225 char *p;
3226 unsigned int n;
252b5132 3227
29b0f896
AM		 3228 for (n = 0; n < i.operands; n++)
3229 {
3230 if (i.types[n] & Disp)
3231 {
3232 if (i.op[n].disps->X_op == O_constant)
3233 {
3234 int size;
3235 offsetT val;
252b5132 3236
29b0f896
AM		 3237 size = 4;
3238 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3239 {
3240 size = 2;
3241 if (i.types[n] & Disp8)
3242 size = 1;
3243 if (i.types[n] & Disp64)
3244 size = 8;
3245 }
3246 val = offset_in_range (i.op[n].disps->X_add_number,
3247 size);
3248 p = frag_more (size);
3249 md_number_to_chars (p, val, size);
3250 }
3251 else
3252 {
2bbd9c25 3253 RELOC_ENUM reloc_type;
29b0f896
AM		 3254 int size = 4;
3255 int sign = 0;
3256 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3257
3258 /* The PC relative address is computed relative
3259 to the instruction boundary, so in case immediate
3260 fields follows, we need to adjust the value. */
3261 if (pcrel && i.imm_operands)
3262 {
3263 int imm_size = 4;
3264 unsigned int n1;
252b5132 3265
29b0f896
AM		 3266 for (n1 = 0; n1 < i.operands; n1++)
3267 if (i.types[n1] & Imm)
252b5132 3268 {
29b0f896 3269 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3270 {
29b0f896
AM		 3271 imm_size = 2;
3272 if (i.types[n1] & (Imm8 | Imm8S))
3273 imm_size = 1;
3274 if (i.types[n1] & Imm64)
3275 imm_size = 8;
252b5132 3276 }
29b0f896 3277 break;
252b5132 3278 }
29b0f896
AM		 3279 /* We should find the immediate. */
3280 if (n1 == i.operands)
3281 abort ();
3282 i.op[n].disps->X_add_number -= imm_size;
3283 }
520dc8e8 3284
29b0f896
AM		 3285 if (i.types[n] & Disp32S)
3286 sign = 1;
3e73aa7c 3287
29b0f896
AM		 3288 if (i.types[n] & (Disp16 | Disp64))
3289 {
3290 size = 2;
3291 if (i.types[n] & Disp64)
3292 size = 8;
3293 }
520dc8e8 3294
29b0f896 3295 p = frag_more (size);
2bbd9c25
JJ		 3296 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3297#ifdef BFD_ASSEMBLER
3298 if (reloc_type == BFD_RELOC_32
3299 && GOT_symbol
3300 && GOT_symbol == i.op[n].disps->X_add_symbol
3301 && (i.op[n].disps->X_op == O_symbol
3302 || (i.op[n].disps->X_op == O_add
3303 && ((symbol_get_value_expression
3304 (i.op[n].disps->X_op_symbol)->X_op)
3305 == O_subtract))))
3306 {
3307 offsetT add;
3308
3309 if (insn_start_frag == frag_now)
3310 add = (p - frag_now->fr_literal) - insn_start_off;
3311 else
3312 {
3313 fragS *fr;
3314
3315 add = insn_start_frag->fr_fix - insn_start_off;
3316 for (fr = insn_start_frag->fr_next;
3317 fr && fr != frag_now; fr = fr->fr_next)
3318 add += fr->fr_fix;
3319 add += p - frag_now->fr_literal;
3320 }
3321
3322 /* We don't support dynamic linking on x86-64 yet. */
3323 if (flag_code == CODE_64BIT)
3324 abort ();
3325 reloc_type = BFD_RELOC_386_GOTPC;
3326 i.op[n].disps->X_add_number += add;
3327 }
3328#endif
062cd5e7 3329 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3330 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3331 }
3332 }
3333 }
3334}
252b5132 3335
29b0f896 3336static void
2bbd9c25
JJ		 3337output_imm (insn_start_frag, insn_start_off)
3338 fragS *insn_start_frag;
3339 offsetT insn_start_off;
29b0f896
AM		 3340{
3341 char *p;
3342 unsigned int n;
252b5132 3343
29b0f896
AM		 3344 for (n = 0; n < i.operands; n++)
3345 {
3346 if (i.types[n] & Imm)
3347 {
3348 if (i.op[n].imms->X_op == O_constant)
3349 {
3350 int size;
3351 offsetT val;
b4cac588 3352
29b0f896
AM		 3353 size = 4;
3354 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3355 {
3356 size = 2;
3357 if (i.types[n] & (Imm8 | Imm8S))
3358 size = 1;
3359 else if (i.types[n] & Imm64)
3360 size = 8;
3361 }
3362 val = offset_in_range (i.op[n].imms->X_add_number,
3363 size);
3364 p = frag_more (size);
3365 md_number_to_chars (p, val, size);
3366 }
3367 else
3368 {
3369 /* Not absolute_section.
3370 Need a 32-bit fixup (don't support 8bit
3371 non-absolute imms). Try to support other
3372 sizes ... */
3373 RELOC_ENUM reloc_type;
3374 int size = 4;
3375 int sign = 0;
3376
3377 if ((i.types[n] & (Imm32S))
3378 && i.suffix == QWORD_MNEM_SUFFIX)
3379 sign = 1;
3380 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3381 {
3382 size = 2;
3383 if (i.types[n] & (Imm8 | Imm8S))
3384 size = 1;
3385 if (i.types[n] & Imm64)
3386 size = 8;
3387 }
520dc8e8 3388
29b0f896
AM		 3389 p = frag_more (size);
3390 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3391#ifdef BFD_ASSEMBLER
2bbd9c25
JJ		 3392 /* This is tough to explain. We end up with this one if we
3393 * have operands that look like
3394 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3395 * obtain the absolute address of the GOT, and it is strongly
3396 * preferable from a performance point of view to avoid using
3397 * a runtime relocation for this. The actual sequence of
3398 * instructions often look something like:
3399 *
3400 * call .L66
3401 * .L66:
3402 * popl %ebx
3403 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3404 *
3405 * The call and pop essentially return the absolute address
3406 * of the label .L66 and store it in %ebx. The linker itself
3407 * will ultimately change the first operand of the addl so
3408 * that %ebx points to the GOT, but to keep things simple, the
3409 * .o file must have this operand set so that it generates not
3410 * the absolute address of .L66, but the absolute address of
3411 * itself. This allows the linker itself simply treat a GOTPC
3412 * relocation as asking for a pcrel offset to the GOT to be
3413 * added in, and the addend of the relocation is stored in the
3414 * operand field for the instruction itself.
3415 *
3416 * Our job here is to fix the operand so that it would add
3417 * the correct offset so that %ebx would point to itself. The
3418 * thing that is tricky is that .-.L66 will point to the
3419 * beginning of the instruction, so we need to further modify
3420 * the operand so that it will point to itself. There are
3421 * other cases where you have something like:
3422 *
3423 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3424 *
3425 * and here no correction would be required. Internally in
3426 * the assembler we treat operands of this form as not being
3427 * pcrel since the '.' is explicitly mentioned, and I wonder
3428 * whether it would simplify matters to do it this way. Who
3429 * knows. In earlier versions of the PIC patches, the
3430 * pcrel_adjust field was used to store the correction, but
3431 * since the expression is not pcrel, I felt it would be
3432 * confusing to do it this way. */
3433
29b0f896
AM		 3434 if (reloc_type == BFD_RELOC_32
3435 && GOT_symbol
3436 && GOT_symbol == i.op[n].imms->X_add_symbol
3437 && (i.op[n].imms->X_op == O_symbol
3438 || (i.op[n].imms->X_op == O_add
3439 && ((symbol_get_value_expression
3440 (i.op[n].imms->X_op_symbol)->X_op)
3441 == O_subtract))))
3442 {
2bbd9c25
JJ		 3443 offsetT add;
3444
3445 if (insn_start_frag == frag_now)
3446 add = (p - frag_now->fr_literal) - insn_start_off;
3447 else
3448 {
3449 fragS *fr;
3450
3451 add = insn_start_frag->fr_fix - insn_start_off;
3452 for (fr = insn_start_frag->fr_next;
3453 fr && fr != frag_now; fr = fr->fr_next)
3454 add += fr->fr_fix;
3455 add += p - frag_now->fr_literal;
3456 }
3457
29b0f896
AM		 3458 /* We don't support dynamic linking on x86-64 yet. */
3459 if (flag_code == CODE_64BIT)
3460 abort ();
3461 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3462 i.op[n].imms->X_add_number += add;
29b0f896 3463 }
252b5132 3464#endif
29b0f896
AM		 3465 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3466 i.op[n].imms, 0, reloc_type);
3467 }
3468 }
3469 }
252b5132
RH		 3470}
3471\f
f3c180ae
AM		 3472#ifndef LEX_AT
3473static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3474
3475/* Parse operands of the form
3476 <symbol>@GOTOFF+<nnn>
3477 and similar .plt or .got references.
3478
3479 If we find one, set up the correct relocation in RELOC and copy the
3480 input string, minus the `@GOTOFF' into a malloc'd buffer for
3481 parsing by the calling routine. Return this buffer, and if ADJUST
3482 is non-null set it to the length of the string we removed from the
3483 input line. Otherwise return NULL. */
3484static char *
3485lex_got (reloc, adjust)
3486 RELOC_ENUM *reloc;
3487 int *adjust;
3488{
3489 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3490 static const struct {
3491 const char *str;
3492 const RELOC_ENUM rel[NUM_FLAG_CODE];
3493 } gotrel[] = {
13ae64f3
JJ		 3494 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3495 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3496 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3497 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3498 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3499 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3500 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3501 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3502 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3503 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3504 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3505 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3506 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3507 };
3508 char *cp;
3509 unsigned int j;
3510
3511 for (cp = input_line_pointer; *cp != '@'; cp++)
3512 if (is_end_of_line[(unsigned char) *cp])
3513 return NULL;
3514
3515 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3516 {
3517 int len;
3518
3519 len = strlen (gotrel[j].str);
28f81592 3520 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3521 {
3522 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3523 {
28f81592
AM		 3524 int first, second;
3525 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3526
3527 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3528 if (adjust)
3529 *adjust = len;
f3c180ae
AM		 3530
3531 if (GOT_symbol == NULL)
3532 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3533
3534 /* Replace the relocation token with ' ', so that
3535 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3536
3537 /* The length of the first part of our input line. */
f3c180ae 3538 first = cp - input_line_pointer;
28f81592
AM		 3539
3540 /* The second part goes from after the reloc token until
3541 (and including) an end_of_line char. Don't use strlen
3542 here as the end_of_line char may not be a NUL. */
3543 past_reloc = cp + 1 + len;
3544 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3545 ;
3546 second = cp - past_reloc;
3547
3548 /* Allocate and copy string. The trailing NUL shouldn't
3549 be necessary, but be safe. */
3550 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3551 memcpy (tmpbuf, input_line_pointer, first);
3552 tmpbuf[first] = ' ';
28f81592
AM		 3553 memcpy (tmpbuf + first + 1, past_reloc, second);
3554 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3555 return tmpbuf;
3556 }
3557
3558 as_bad (_("@%s reloc is not supported in %s bit mode"),
3559 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3560 return NULL;
3561 }
3562 }
3563
3564 /* Might be a symbol version string. Don't as_bad here. */
3565 return NULL;
3566}
3567
3568/* x86_cons_fix_new is called via the expression parsing code when a
3569 reloc is needed. We use this hook to get the correct .got reloc. */
3570static RELOC_ENUM got_reloc = NO_RELOC;
3571
3572void
3573x86_cons_fix_new (frag, off, len, exp)
3574 fragS *frag;
3575 unsigned int off;
3576 unsigned int len;
3577 expressionS *exp;
3578{
3579 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3580 got_reloc = NO_RELOC;
3581 fix_new_exp (frag, off, len, exp, 0, r);
3582}
3583
3584void
3585x86_cons (exp, size)
3586 expressionS *exp;
3587 int size;
3588{
3589 if (size == 4)
3590 {
3591 /* Handle @GOTOFF and the like in an expression. */
3592 char *save;
3593 char *gotfree_input_line;
3594 int adjust;
3595
3596 save = input_line_pointer;
3597 gotfree_input_line = lex_got (&got_reloc, &adjust);
3598 if (gotfree_input_line)
3599 input_line_pointer = gotfree_input_line;
3600
3601 expression (exp);
3602
3603 if (gotfree_input_line)
3604 {
3605 /* expression () has merrily parsed up to the end of line,
3606 or a comma - in the wrong buffer. Transfer how far
3607 input_line_pointer has moved to the right buffer. */
3608 input_line_pointer = (save
3609 + (input_line_pointer - gotfree_input_line)
3610 + adjust);
3611 free (gotfree_input_line);
3612 }
3613 }
3614 else
3615 expression (exp);
3616}
3617#endif
3618
252b5132
RH		 3619static int i386_immediate PARAMS ((char *));
3620
3621static int
3622i386_immediate (imm_start)
3623 char *imm_start;
3624{
3625 char *save_input_line_pointer;
f3c180ae
AM		 3626#ifndef LEX_AT
3627 char *gotfree_input_line;
3628#endif
252b5132 3629 segT exp_seg = 0;
47926f60 3630 expressionS *exp;
252b5132
RH		 3631
3632 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3633 {
d0b47220 3634 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3635 return 0;
3636 }
3637
3638 exp = &im_expressions[i.imm_operands++];
520dc8e8 3639 i.op[this_operand].imms = exp;
252b5132
RH		 3640
3641 if (is_space_char (*imm_start))
3642 ++imm_start;
3643
3644 save_input_line_pointer = input_line_pointer;
3645 input_line_pointer = imm_start;
3646
3647#ifndef LEX_AT
f3c180ae
AM		 3648 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3649 if (gotfree_input_line)
3650 input_line_pointer = gotfree_input_line;
252b5132
RH		 3651#endif
3652
3653 exp_seg = expression (exp);
3654
83183c0c 3655 SKIP_WHITESPACE ();
252b5132 3656 if (*input_line_pointer)
f3c180ae 3657 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3658
3659 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3660#ifndef LEX_AT
3661 if (gotfree_input_line)
3662 free (gotfree_input_line);
3663#endif
252b5132 3664
2daf4fd8 3665 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3666 {
47926f60 3667 /* Missing or bad expr becomes absolute 0. */
d0b47220 3668 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3669 imm_start);
252b5132
RH		 3670 exp->X_op = O_constant;
3671 exp->X_add_number = 0;
3672 exp->X_add_symbol = (symbolS *) 0;
3673 exp->X_op_symbol = (symbolS *) 0;
252b5132 3674 }
3e73aa7c 3675 else if (exp->X_op == O_constant)
252b5132 3676 {
47926f60 3677 /* Size it properly later. */
3e73aa7c
JH		 3678 i.types[this_operand] |= Imm64;
3679 /* If BFD64, sign extend val. */
3680 if (!use_rela_relocations)
3681 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3682 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3683 }
4c63da97 3684#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3685 else if (1
4c63da97 3686#ifdef BFD_ASSEMBLER
47926f60 3687 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3688#endif
31312f95 3689 && exp_seg != absolute_section
47926f60 3690 && exp_seg != text_section
24eab124
AM		 3691 && exp_seg != data_section
3692 && exp_seg != bss_section
3693 && exp_seg != undefined_section
252b5132 3694#ifdef BFD_ASSEMBLER
24eab124 3695 && !bfd_is_com_section (exp_seg)
252b5132 3696#endif
24eab124 3697 )
252b5132 3698 {
4c63da97 3699#ifdef BFD_ASSEMBLER
d0b47220 3700 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3701#else
d0b47220 3702 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3703#endif
252b5132
RH		 3704 return 0;
3705 }
3706#endif
3707 else
3708 {
3709 /* This is an address. The size of the address will be
24eab124 3710 determined later, depending on destination register,
3e73aa7c
JH		 3711 suffix, or the default for the section. */
3712 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3713 }
3714
3715 return 1;
3716}
3717
551c1ca1 3718static char *i386_scale PARAMS ((char *));
252b5132 3719
551c1ca1 3720static char *
252b5132
RH		 3721i386_scale (scale)
3722 char *scale;
3723{
551c1ca1
AM		 3724 offsetT val;
3725 char *save = input_line_pointer;
252b5132 3726
551c1ca1
AM		 3727 input_line_pointer = scale;
3728 val = get_absolute_expression ();
3729
3730 switch (val)
252b5132 3731 {
551c1ca1
AM		 3732 case 0:
3733 case 1:
252b5132
RH		 3734 i.log2_scale_factor = 0;
3735 break;
551c1ca1 3736 case 2:
252b5132
RH		 3737 i.log2_scale_factor = 1;
3738 break;
551c1ca1 3739 case 4:
252b5132
RH		 3740 i.log2_scale_factor = 2;
3741 break;
551c1ca1 3742 case 8:
252b5132
RH		 3743 i.log2_scale_factor = 3;
3744 break;
3745 default:
252b5132 3746 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3747 scale);
551c1ca1
AM		 3748 input_line_pointer = save;
3749 return NULL;
252b5132 3750 }
29b0f896 3751 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3752 {
3753 as_warn (_("scale factor of %d without an index register"),
24eab124 3754 1 << i.log2_scale_factor);
252b5132
RH		 3755#if SCALE1_WHEN_NO_INDEX
3756 i.log2_scale_factor = 0;
3757#endif
3758 }
551c1ca1
AM		 3759 scale = input_line_pointer;
3760 input_line_pointer = save;
3761 return scale;
252b5132
RH		 3762}
3763
3764static int i386_displacement PARAMS ((char *, char *));
3765
3766static int
3767i386_displacement (disp_start, disp_end)
3768 char *disp_start;
3769 char *disp_end;
3770{
29b0f896 3771 expressionS *exp;
252b5132
RH		 3772 segT exp_seg = 0;
3773 char *save_input_line_pointer;
f3c180ae
AM		 3774#ifndef LEX_AT
3775 char *gotfree_input_line;
3776#endif
252b5132
RH		 3777 int bigdisp = Disp32;
3778
3e73aa7c 3779 if (flag_code == CODE_64BIT)
7ecd2f8b 3780 {
29b0f896
AM		 3781 if (i.prefix[ADDR_PREFIX] == 0)
3782 bigdisp = Disp64;
7ecd2f8b
JH		 3783 }
3784 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3785 bigdisp = Disp16;
252b5132
RH		 3786 i.types[this_operand] |= bigdisp;
3787
3788 exp = &disp_expressions[i.disp_operands];
520dc8e8 3789 i.op[this_operand].disps = exp;
252b5132
RH		 3790 i.disp_operands++;
3791 save_input_line_pointer = input_line_pointer;
3792 input_line_pointer = disp_start;
3793 END_STRING_AND_SAVE (disp_end);
3794
3795#ifndef GCC_ASM_O_HACK
3796#define GCC_ASM_O_HACK 0
3797#endif
3798#if GCC_ASM_O_HACK
3799 END_STRING_AND_SAVE (disp_end + 1);
3800 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3801 && displacement_string_end[-1] == '+')
252b5132
RH		 3802 {
3803 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3804 constraint within gcc asm statements.
3805 For instance:
3806
3807 #define _set_tssldt_desc(n,addr,limit,type) \
3808 __asm__ __volatile__ ( \
3809 "movw %w2,%0\n\t" \
3810 "movw %w1,2+%0\n\t" \
3811 "rorl $16,%1\n\t" \
3812 "movb %b1,4+%0\n\t" \
3813 "movb %4,5+%0\n\t" \
3814 "movb $0,6+%0\n\t" \
3815 "movb %h1,7+%0\n\t" \
3816 "rorl $16,%1" \
3817 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3818
3819 This works great except that the output assembler ends
3820 up looking a bit weird if it turns out that there is
3821 no offset. You end up producing code that looks like:
3822
3823 #APP
3824 movw $235,(%eax)
3825 movw %dx,2+(%eax)
3826 rorl $16,%edx
3827 movb %dl,4+(%eax)
3828 movb $137,5+(%eax)
3829 movb $0,6+(%eax)
3830 movb %dh,7+(%eax)
3831 rorl $16,%edx
3832 #NO_APP
3833
47926f60 3834 So here we provide the missing zero. */
24eab124
AM		 3835
3836 *displacement_string_end = '0';
252b5132
RH		 3837 }
3838#endif
3839#ifndef LEX_AT
f3c180ae
AM		 3840 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3841 if (gotfree_input_line)
3842 input_line_pointer = gotfree_input_line;
252b5132
RH		 3843#endif
3844
24eab124 3845 exp_seg = expression (exp);
252b5132 3846
636c26b0
AM		 3847 SKIP_WHITESPACE ();
3848 if (*input_line_pointer)
3849 as_bad (_("junk `%s' after expression"), input_line_pointer);
3850#if GCC_ASM_O_HACK
3851 RESTORE_END_STRING (disp_end + 1);
3852#endif
3853 RESTORE_END_STRING (disp_end);
3854 input_line_pointer = save_input_line_pointer;
3855#ifndef LEX_AT
3856 if (gotfree_input_line)
3857 free (gotfree_input_line);
3858#endif
3859
252b5132 3860#ifdef BFD_ASSEMBLER
24eab124
AM		 3861 /* We do this to make sure that the section symbol is in
3862 the symbol table. We will ultimately change the relocation
47926f60 3863 to be relative to the beginning of the section. */
1ae12ab7
AM		 3864 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3865 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3866 {
636c26b0
AM		 3867 if (exp->X_op != O_symbol)
3868 {
3869 as_bad (_("bad expression used with @%s"),
3870 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3871 ? "GOTPCREL"
3872 : "GOTOFF"));
3873 return 0;
3874 }
3875
e5cb08ac 3876 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3877 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3878 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3879 exp->X_op = O_subtract;
3880 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3881 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3882 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3883 else
29b0f896 3884 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3885 }
252b5132
RH		 3886#endif
3887
2daf4fd8
AM		 3888 if (exp->X_op == O_absent || exp->X_op == O_big)
3889 {
47926f60 3890 /* Missing or bad expr becomes absolute 0. */
d0b47220 3891 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3892 disp_start);
3893 exp->X_op = O_constant;
3894 exp->X_add_number = 0;
3895 exp->X_add_symbol = (symbolS *) 0;
3896 exp->X_op_symbol = (symbolS *) 0;
3897 }
3898
4c63da97 3899#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3900 if (exp->X_op != O_constant
4c63da97 3901#ifdef BFD_ASSEMBLER
45288df1 3902 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3903#endif
31312f95 3904 && exp_seg != absolute_section
45288df1
AM		 3905 && exp_seg != text_section
3906 && exp_seg != data_section
3907 && exp_seg != bss_section
31312f95
AM		 3908 && exp_seg != undefined_section
3909#ifdef BFD_ASSEMBLER
3910 && !bfd_is_com_section (exp_seg)
3911#endif
3912 )
24eab124 3913 {
4c63da97 3914#ifdef BFD_ASSEMBLER
d0b47220 3915 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3916#else
d0b47220 3917 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3918#endif
24eab124
AM		 3919 return 0;
3920 }
252b5132 3921#endif
3e73aa7c
JH		 3922 else if (flag_code == CODE_64BIT)
3923 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3924 return 1;
3925}
3926
e5cb08ac 3927static int i386_index_check PARAMS ((const char *));
252b5132 3928
eecb386c 3929/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3930 Return 1 on success, 0 on a failure. */
3931
252b5132 3932static int
eecb386c
AM		 3933i386_index_check (operand_string)
3934 const char *operand_string;
252b5132 3935{
3e73aa7c 3936 int ok;
24eab124 3937#if INFER_ADDR_PREFIX
eecb386c
AM		 3938 int fudged = 0;
3939
24eab124
AM		 3940 tryprefix:
3941#endif
3e73aa7c
JH		 3942 ok = 1;
3943 if (flag_code == CODE_64BIT)
3944 {
7ecd2f8b
JH		 3945 if (i.prefix[ADDR_PREFIX] == 0)
3946 {
3947 /* 64bit checks. */
3948 if ((i.base_reg
3949 && ((i.base_reg->reg_type & Reg64) == 0)
3950 && (i.base_reg->reg_type != BaseIndex
3951 || i.index_reg))
3952 || (i.index_reg
29b0f896
AM		 3953 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3954 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3955 ok = 0;
3956 }
3957 else
3958 {
3959 /* 32bit checks. */
3960 if ((i.base_reg
3961 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3962 || (i.index_reg
29b0f896
AM		 3963 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3964 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3965 ok = 0;
3966 }
3e73aa7c
JH		 3967 }
3968 else
3969 {
3970 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3971 {
3972 /* 16bit checks. */
3973 if ((i.base_reg
29b0f896
AM		 3974 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3975 != (Reg16 | BaseIndex)))
3e73aa7c 3976 || (i.index_reg
29b0f896
AM		 3977 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3978 != (Reg16 | BaseIndex))
3979 || !(i.base_reg
3980 && i.base_reg->reg_num < 6
3981 && i.index_reg->reg_num >= 6
3982 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3983 ok = 0;
3984 }
3985 else
e5cb08ac 3986 {
3e73aa7c
JH		 3987 /* 32bit checks. */
3988 if ((i.base_reg
3989 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3990 || (i.index_reg
29b0f896
AM		 3991 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3992 != (Reg32 | BaseIndex))))
e5cb08ac 3993 ok = 0;
3e73aa7c
JH		 3994 }
3995 }
3996 if (!ok)
24eab124
AM		 3997 {
3998#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3999 if (flag_code != CODE_64BIT
4000 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 4001 {
4002 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4003 i.prefixes += 1;
b23bac36
AM		 4004 /* Change the size of any displacement too. At most one of
4005 Disp16 or Disp32 is set.
4006 FIXME. There doesn't seem to be any real need for separate
4007 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4008 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 4009 if (i.types[this_operand] & (Disp16 | Disp32))
4010 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4011 fudged = 1;
24eab124
AM		 4012 goto tryprefix;
4013 }
eecb386c
AM		 4014 if (fudged)
4015 as_bad (_("`%s' is not a valid base/index expression"),
4016 operand_string);
4017 else
c388dee8 4018#endif
eecb386c
AM		 4019 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4020 operand_string,
3e73aa7c 4021 flag_code_names[flag_code]);
eecb386c 4022 return 0;
24eab124
AM		 4023 }
4024 return 1;
4025}
252b5132 4026
252b5132 4027/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4028 on error. */
252b5132 4029
252b5132
RH		 4030static int
4031i386_operand (operand_string)
4032 char *operand_string;
4033{
af6bdddf
AM		 4034 const reg_entry *r;
4035 char *end_op;
24eab124 4036 char *op_string = operand_string;
252b5132 4037
24eab124 4038 if (is_space_char (*op_string))
252b5132
RH		 4039 ++op_string;
4040
24eab124 4041 /* We check for an absolute prefix (differentiating,
47926f60 4042 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4043 if (*op_string == ABSOLUTE_PREFIX)
4044 {
4045 ++op_string;
4046 if (is_space_char (*op_string))
4047 ++op_string;
4048 i.types[this_operand] |= JumpAbsolute;
4049 }
252b5132 4050
47926f60 4051 /* Check if operand is a register. */
af6bdddf
AM		 4052 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4053 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4054 {
24eab124
AM		 4055 /* Check for a segment override by searching for ':' after a
4056 segment register. */
4057 op_string = end_op;
4058 if (is_space_char (*op_string))
4059 ++op_string;
4060 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4061 {
4062 switch (r->reg_num)
4063 {
4064 case 0:
4065 i.seg[i.mem_operands] = &es;
4066 break;
4067 case 1:
4068 i.seg[i.mem_operands] = &cs;
4069 break;
4070 case 2:
4071 i.seg[i.mem_operands] = &ss;
4072 break;
4073 case 3:
4074 i.seg[i.mem_operands] = &ds;
4075 break;
4076 case 4:
4077 i.seg[i.mem_operands] = &fs;
4078 break;
4079 case 5:
4080 i.seg[i.mem_operands] = &gs;
4081 break;
4082 }
252b5132 4083
24eab124 4084 /* Skip the ':' and whitespace. */
252b5132
RH		 4085 ++op_string;
4086 if (is_space_char (*op_string))
24eab124 4087 ++op_string;
252b5132 4088
24eab124
AM		 4089 if (!is_digit_char (*op_string)
4090 && !is_identifier_char (*op_string)
4091 && *op_string != '('
4092 && *op_string != ABSOLUTE_PREFIX)
4093 {
4094 as_bad (_("bad memory operand `%s'"), op_string);
4095 return 0;
4096 }
47926f60 4097 /* Handle case of %es:*foo. */
24eab124
AM		 4098 if (*op_string == ABSOLUTE_PREFIX)
4099 {
4100 ++op_string;
4101 if (is_space_char (*op_string))
4102 ++op_string;
4103 i.types[this_operand] |= JumpAbsolute;
4104 }
4105 goto do_memory_reference;
4106 }
4107 if (*op_string)
4108 {
d0b47220 4109 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4110 return 0;
4111 }
4112 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4113 i.op[this_operand].regs = r;
24eab124
AM		 4114 i.reg_operands++;
4115 }
af6bdddf
AM		 4116 else if (*op_string == REGISTER_PREFIX)
4117 {
4118 as_bad (_("bad register name `%s'"), op_string);
4119 return 0;
4120 }
24eab124 4121 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4122 {
24eab124
AM		 4123 ++op_string;
4124 if (i.types[this_operand] & JumpAbsolute)
4125 {
d0b47220 4126 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4127 return 0;
4128 }
4129 if (!i386_immediate (op_string))
4130 return 0;
4131 }
4132 else if (is_digit_char (*op_string)
4133 || is_identifier_char (*op_string)
e5cb08ac 4134 || *op_string == '(')
24eab124 4135 {
47926f60 4136 /* This is a memory reference of some sort. */
af6bdddf 4137 char *base_string;
252b5132 4138
47926f60 4139 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4140 char *displacement_string_start;
4141 char *displacement_string_end;
252b5132 4142
24eab124 4143 do_memory_reference:
24eab124
AM		 4144 if ((i.mem_operands == 1
4145 && (current_templates->start->opcode_modifier & IsString) == 0)
4146 || i.mem_operands == 2)
4147 {
4148 as_bad (_("too many memory references for `%s'"),
4149 current_templates->start->name);
4150 return 0;
4151 }
252b5132 4152
24eab124
AM		 4153 /* Check for base index form. We detect the base index form by
4154 looking for an ')' at the end of the operand, searching
4155 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4156 after the '('. */
af6bdddf 4157 base_string = op_string + strlen (op_string);
c3332e24 4158
af6bdddf
AM		 4159 --base_string;
4160 if (is_space_char (*base_string))
4161 --base_string;
252b5132 4162
47926f60 4163 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4164 displacement_string_start = op_string;
4165 displacement_string_end = base_string + 1;
252b5132 4166
24eab124
AM		 4167 if (*base_string == ')')
4168 {
af6bdddf 4169 char *temp_string;
24eab124
AM		 4170 unsigned int parens_balanced = 1;
4171 /* We've already checked that the number of left & right ()'s are
47926f60 4172 equal, so this loop will not be infinite. */
24eab124
AM		 4173 do
4174 {
4175 base_string--;
4176 if (*base_string == ')')
4177 parens_balanced++;
4178 if (*base_string == '(')
4179 parens_balanced--;
4180 }
4181 while (parens_balanced);
c3332e24 4182
af6bdddf 4183 temp_string = base_string;
c3332e24 4184
24eab124 4185 /* Skip past '(' and whitespace. */
252b5132
RH		 4186 ++base_string;
4187 if (is_space_char (*base_string))
24eab124 4188 ++base_string;
252b5132 4189
af6bdddf
AM		 4190 if (*base_string == ','
4191 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4192 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4193 {
af6bdddf 4194 displacement_string_end = temp_string;
252b5132 4195
af6bdddf 4196 i.types[this_operand] |= BaseIndex;
252b5132 4197
af6bdddf 4198 if (i.base_reg)
24eab124 4199 {
24eab124
AM		 4200 base_string = end_op;
4201 if (is_space_char (*base_string))
4202 ++base_string;
af6bdddf
AM		 4203 }
4204
4205 /* There may be an index reg or scale factor here. */
4206 if (*base_string == ',')
4207 {
4208 ++base_string;
4209 if (is_space_char (*base_string))
4210 ++base_string;
4211
4212 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4213 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4214 {
af6bdddf 4215 base_string = end_op;
24eab124
AM		 4216 if (is_space_char (*base_string))
4217 ++base_string;
af6bdddf
AM		 4218 if (*base_string == ',')
4219 {
4220 ++base_string;
4221 if (is_space_char (*base_string))
4222 ++base_string;
4223 }
e5cb08ac 4224 else if (*base_string != ')')
af6bdddf
AM		 4225 {
4226 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4227 operand_string);
4228 return 0;
4229 }
24eab124 4230 }
af6bdddf 4231 else if (*base_string == REGISTER_PREFIX)
24eab124 4232 {
af6bdddf 4233 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4234 return 0;
4235 }
252b5132 4236
47926f60 4237 /* Check for scale factor. */
551c1ca1 4238 if (*base_string != ')')
af6bdddf 4239 {
551c1ca1
AM		 4240 char *end_scale = i386_scale (base_string);
4241
4242 if (!end_scale)
af6bdddf 4243 return 0;
24eab124 4244
551c1ca1 4245 base_string = end_scale;
af6bdddf
AM		 4246 if (is_space_char (*base_string))
4247 ++base_string;
4248 if (*base_string != ')')
4249 {
4250 as_bad (_("expecting `)' after scale factor in `%s'"),
4251 operand_string);
4252 return 0;
4253 }
4254 }
4255 else if (!i.index_reg)
24eab124 4256 {
af6bdddf
AM		 4257 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4258 *base_string);
24eab124
AM		 4259 return 0;
4260 }
4261 }
af6bdddf 4262 else if (*base_string != ')')
24eab124 4263 {
af6bdddf
AM		 4264 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4265 operand_string);
24eab124
AM		 4266 return 0;
4267 }
c3332e24 4268 }
af6bdddf 4269 else if (*base_string == REGISTER_PREFIX)
c3332e24 4270 {
af6bdddf 4271 as_bad (_("bad register name `%s'"), base_string);
24eab124 4272 return 0;
c3332e24 4273 }
24eab124
AM		 4274 }
4275
4276 /* If there's an expression beginning the operand, parse it,
4277 assuming displacement_string_start and
4278 displacement_string_end are meaningful. */
4279 if (displacement_string_start != displacement_string_end)
4280 {
4281 if (!i386_displacement (displacement_string_start,
4282 displacement_string_end))
4283 return 0;
4284 }
4285
4286 /* Special case for (%dx) while doing input/output op. */
4287 if (i.base_reg
4288 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4289 && i.index_reg == 0
4290 && i.log2_scale_factor == 0
4291 && i.seg[i.mem_operands] == 0
4292 && (i.types[this_operand] & Disp) == 0)
4293 {
4294 i.types[this_operand] = InOutPortReg;
4295 return 1;
4296 }
4297
eecb386c
AM		 4298 if (i386_index_check (operand_string) == 0)
4299 return 0;
24eab124
AM		 4300 i.mem_operands++;
4301 }
4302 else
ce8a8b2f
AM		 4303 {
4304 /* It's not a memory operand; argh! */
24eab124
AM		 4305 as_bad (_("invalid char %s beginning operand %d `%s'"),
4306 output_invalid (*op_string),
4307 this_operand + 1,
4308 op_string);
4309 return 0;
4310 }
47926f60 4311 return 1; /* Normal return. */
252b5132
RH		 4312}
4313\f
ee7fcc42
AM		 4314/* md_estimate_size_before_relax()
4315
4316 Called just before relax() for rs_machine_dependent frags. The x86
4317 assembler uses these frags to handle variable size jump
4318 instructions.
4319
4320 Any symbol that is now undefined will not become defined.
4321 Return the correct fr_subtype in the frag.
4322 Return the initial "guess for variable size of frag" to caller.
4323 The guess is actually the growth beyond the fixed part. Whatever
4324 we do to grow the fixed or variable part contributes to our
4325 returned value. */
4326
252b5132
RH		 4327int
4328md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4329 fragS *fragP;
4330 segT segment;
252b5132 4331{
252b5132 4332 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4333 check for un-relaxable symbols. On an ELF system, we can't relax
4334 an externally visible symbol, because it may be overridden by a
4335 shared library. */
4336 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4338 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4339 && (S_IS_EXTERNAL (fragP->fr_symbol)
4340 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4341#endif
4342 )
252b5132 4343 {
b98ef147
AM		 4344 /* Symbol is undefined in this segment, or we need to keep a
4345 reloc so that weak symbols can be overridden. */
4346 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4347 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4348 unsigned char *opcode;
4349 int old_fr_fix;
f6af82bd 4350
ee7fcc42
AM		 4351 if (fragP->fr_var != NO_RELOC)
4352 reloc_type = fragP->fr_var;
b98ef147 4353 else if (size == 2)
f6af82bd
AM		 4354 reloc_type = BFD_RELOC_16_PCREL;
4355 else
4356 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4357
ee7fcc42
AM		 4358 old_fr_fix = fragP->fr_fix;
4359 opcode = (unsigned char *) fragP->fr_opcode;
4360
fddf5b5b 4361 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4362 {
fddf5b5b
AM		 4363 case UNCOND_JUMP:
4364 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4365 opcode[0] = 0xe9;
252b5132 4366 fragP->fr_fix += size;
062cd5e7
AS		 4367 fix_new (fragP, old_fr_fix, size,
4368 fragP->fr_symbol,
4369 fragP->fr_offset, 1,
4370 reloc_type);
252b5132
RH		 4371 break;
4372
fddf5b5b 4373 case COND_JUMP86:
412167cb
AM		 4374 if (size == 2
4375 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4376 {
4377 /* Negate the condition, and branch past an
4378 unconditional jump. */
4379 opcode[0] ^= 1;
4380 opcode[1] = 3;
4381 /* Insert an unconditional jump. */
4382 opcode[2] = 0xe9;
4383 /* We added two extra opcode bytes, and have a two byte
4384 offset. */
4385 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4386 fix_new (fragP, old_fr_fix + 2, 2,
4387 fragP->fr_symbol,
4388 fragP->fr_offset, 1,
4389 reloc_type);
fddf5b5b
AM		 4390 break;
4391 }
4392 /* Fall through. */
4393
4394 case COND_JUMP:
412167cb
AM		 4395 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4396 {
4397 fragP->fr_fix += 1;
4398 fix_new (fragP, old_fr_fix, 1,
4399 fragP->fr_symbol,
4400 fragP->fr_offset, 1,
4401 BFD_RELOC_8_PCREL);
4402 break;
4403 }
93c2a809 4404
24eab124 4405 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4406 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4407 opcode[1] = opcode[0] + 0x10;
f6af82bd 4408 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4409 /* We've added an opcode byte. */
4410 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4411 fix_new (fragP, old_fr_fix + 1, size,
4412 fragP->fr_symbol,
4413 fragP->fr_offset, 1,
4414 reloc_type);
252b5132 4415 break;
fddf5b5b
AM		 4416
4417 default:
4418 BAD_CASE (fragP->fr_subtype);
4419 break;
252b5132
RH		 4420 }
4421 frag_wane (fragP);
ee7fcc42 4422 return fragP->fr_fix - old_fr_fix;
252b5132 4423 }
93c2a809 4424
93c2a809
AM		 4425 /* Guess size depending on current relax state. Initially the relax
4426 state will correspond to a short jump and we return 1, because
4427 the variable part of the frag (the branch offset) is one byte
4428 long. However, we can relax a section more than once and in that
4429 case we must either set fr_subtype back to the unrelaxed state,
4430 or return the value for the appropriate branch. */
4431 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4432}
4433
47926f60
KH		 4434/* Called after relax() is finished.
4435
4436 In: Address of frag.
4437 fr_type == rs_machine_dependent.
4438 fr_subtype is what the address relaxed to.
4439
4440 Out: Any fixSs and constants are set up.
4441 Caller will turn frag into a ".space 0". */
4442
252b5132
RH		 4443#ifndef BFD_ASSEMBLER
4444void
4445md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4446 object_headers *headers ATTRIBUTE_UNUSED;
4447 segT sec ATTRIBUTE_UNUSED;
29b0f896 4448 fragS *fragP;
252b5132
RH		 4449#else
4450void
4451md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4452 bfd *abfd ATTRIBUTE_UNUSED;
4453 segT sec ATTRIBUTE_UNUSED;
29b0f896 4454 fragS *fragP;
252b5132
RH		 4455#endif
4456{
29b0f896 4457 unsigned char *opcode;
252b5132 4458 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4459 offsetT target_address;
4460 offsetT opcode_address;
252b5132 4461 unsigned int extension = 0;
847f7ad4 4462 offsetT displacement_from_opcode_start;
252b5132
RH		 4463
4464 opcode = (unsigned char *) fragP->fr_opcode;
4465
47926f60 4466 /* Address we want to reach in file space. */
252b5132 4467 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4468
47926f60 4469 /* Address opcode resides at in file space. */
252b5132
RH		 4470 opcode_address = fragP->fr_address + fragP->fr_fix;
4471
47926f60 4472 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4473 displacement_from_opcode_start = target_address - opcode_address;
4474
fddf5b5b 4475 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4476 {
47926f60
KH		 4477 /* Don't have to change opcode. */
4478 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4479 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4480 }
4481 else
4482 {
4483 if (no_cond_jump_promotion
4484 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4485 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4486
fddf5b5b
AM		 4487 switch (fragP->fr_subtype)
4488 {
4489 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4490 extension = 4; /* 1 opcode + 4 displacement */
4491 opcode[0] = 0xe9;
4492 where_to_put_displacement = &opcode[1];
4493 break;
252b5132 4494
fddf5b5b
AM		 4495 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4496 extension = 2; /* 1 opcode + 2 displacement */
4497 opcode[0] = 0xe9;
4498 where_to_put_displacement = &opcode[1];
4499 break;
252b5132 4500
fddf5b5b
AM		 4501 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4502 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4503 extension = 5; /* 2 opcode + 4 displacement */
4504 opcode[1] = opcode[0] + 0x10;
4505 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4506 where_to_put_displacement = &opcode[2];
4507 break;
252b5132 4508
fddf5b5b
AM		 4509 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4510 extension = 3; /* 2 opcode + 2 displacement */
4511 opcode[1] = opcode[0] + 0x10;
4512 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4513 where_to_put_displacement = &opcode[2];
4514 break;
252b5132 4515
fddf5b5b
AM		 4516 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4517 extension = 4;
4518 opcode[0] ^= 1;
4519 opcode[1] = 3;
4520 opcode[2] = 0xe9;
4521 where_to_put_displacement = &opcode[3];
4522 break;
4523
4524 default:
4525 BAD_CASE (fragP->fr_subtype);
4526 break;
4527 }
252b5132 4528 }
fddf5b5b 4529
47926f60 4530 /* Now put displacement after opcode. */
252b5132
RH		 4531 md_number_to_chars ((char *) where_to_put_displacement,
4532 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4533 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4534 fragP->fr_fix += extension;
4535}
4536\f
47926f60
KH		 4537/* Size of byte displacement jmp. */
4538int md_short_jump_size = 2;
4539
4540/* Size of dword displacement jmp. */
4541int md_long_jump_size = 5;
252b5132 4542
47926f60
KH		 4543/* Size of relocation record. */
4544const int md_reloc_size = 8;
252b5132
RH		 4545
4546void
4547md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4548 char *ptr;
4549 addressT from_addr, to_addr;
ab9da554
ILT		 4550 fragS *frag ATTRIBUTE_UNUSED;
4551 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4552{
847f7ad4 4553 offsetT offset;
252b5132
RH		 4554
4555 offset = to_addr - (from_addr + 2);
47926f60
KH		 4556 /* Opcode for byte-disp jump. */
4557 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4558 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4559}
4560
4561void
4562md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4563 char *ptr;
4564 addressT from_addr, to_addr;
a38cf1db
AM		 4565 fragS *frag ATTRIBUTE_UNUSED;
4566 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4567{
847f7ad4 4568 offsetT offset;
252b5132 4569
a38cf1db
AM		 4570 offset = to_addr - (from_addr + 5);
4571 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4572 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4573}
4574\f
4575/* Apply a fixup (fixS) to segment data, once it has been determined
4576 by our caller that we have all the info we need to fix it up.
4577
4578 On the 386, immediates, displacements, and data pointers are all in
4579 the same (little-endian) format, so we don't need to care about which
4580 we are handling. */
4581
94f592af
NC		 4582void
4583md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4584 /* The fix we're to put in. */
4585 fixS *fixP;
47926f60 4586 /* Pointer to the value of the bits. */
c6682705 4587 valueT *valP;
47926f60
KH		 4588 /* Segment fix is from. */
4589 segT seg ATTRIBUTE_UNUSED;
252b5132 4590{
94f592af 4591 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4592 valueT value = *valP;
252b5132 4593
e1b283bb 4594#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4595 if (fixP->fx_pcrel)
4596 {
4597 switch (fixP->fx_r_type)
4598 {
5865bb77
ILT		 4599 default:
4600 break;
4601
93382f6d
AM		 4602 case BFD_RELOC_32:
4603 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4604 break;
4605 case BFD_RELOC_16:
4606 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4607 break;
4608 case BFD_RELOC_8:
4609 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4610 break;
4611 }
4612 }
252b5132 4613
a161fe53 4614 if (fixP->fx_addsy != NULL
31312f95
AM		 4615 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4616 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4617 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4618 && !use_rela_relocations)
252b5132 4619 {
31312f95
AM		 4620 /* This is a hack. There should be a better way to handle this.
4621 This covers for the fact that bfd_install_relocation will
4622 subtract the current location (for partial_inplace, PC relative
4623 relocations); see more below. */
252b5132
RH		 4624#ifndef OBJ_AOUT
4625 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4626#ifdef TE_PE
4627 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4628#endif
4629 )
4630 value += fixP->fx_where + fixP->fx_frag->fr_address;
4631#endif
4632#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4633 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4634 {
6539b54b 4635 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4636
6539b54b 4637 if ((sym_seg == seg
2f66722d 4638 || (symbol_section_p (fixP->fx_addsy)
6539b54b
AM		 4639 && sym_seg != absolute_section))
4640 && !S_FORCE_RELOC (fixP->fx_addsy))
2f66722d
AM		 4641 {
4642 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4643 bfd_install_relocation subtracts them out again. I think
4644 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4645 it. FIXME. */
4646 value += fixP->fx_where + fixP->fx_frag->fr_address;
4647 }
252b5132
RH		 4648 }
4649#endif
4650#if defined (OBJ_COFF) && defined (TE_PE)
4651 /* For some reason, the PE format does not store a section
24eab124 4652 address offset for a PC relative symbol. */
252b5132
RH		 4653 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4654 value += md_pcrel_from (fixP);
4655#endif
4656 }
4657
4658 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4659 and we must not dissappoint it. */
252b5132
RH		 4660#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4661 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4662 && fixP->fx_addsy)
47926f60
KH		 4663 switch (fixP->fx_r_type)
4664 {
4665 case BFD_RELOC_386_PLT32:
3e73aa7c 4666 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4667 /* Make the jump instruction point to the address of the operand. At
4668 runtime we merely add the offset to the actual PLT entry. */
4669 value = -4;
4670 break;
31312f95 4671
47926f60 4672 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4673 case BFD_RELOC_386_TLS_GD:
4674 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4675 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4676 case BFD_RELOC_386_TLS_IE:
4677 case BFD_RELOC_386_TLS_GOTIE:
3e73aa7c 4678 case BFD_RELOC_X86_64_GOT32:
bffbf940
JJ		 4679 case BFD_RELOC_X86_64_TLSGD:
4680 case BFD_RELOC_X86_64_TLSLD:
4681 case BFD_RELOC_X86_64_GOTTPOFF:
47926f60
KH		 4682 value = 0; /* Fully resolved at runtime. No addend. */
4683 break;
47926f60
KH		 4684
4685 case BFD_RELOC_VTABLE_INHERIT:
4686 case BFD_RELOC_VTABLE_ENTRY:
4687 fixP->fx_done = 0;
94f592af 4688 return;
47926f60
KH		 4689
4690 default:
4691 break;
4692 }
4693#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4694 *valP = value;
47926f60 4695#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4696
3e73aa7c 4697 /* Are we finished with this relocation now? */
c6682705 4698 if (fixP->fx_addsy == NULL)
3e73aa7c 4699 fixP->fx_done = 1;
94f592af 4700#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4701 else if (use_rela_relocations)
4702 {
4703 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4704 /* Remember value for tc_gen_reloc. */
4705 fixP->fx_addnumber = value;
3e73aa7c
JH		 4706 value = 0;
4707 }
3e73aa7c 4708#endif
94f592af 4709 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4710}
252b5132 4711\f
252b5132
RH		 4712#define MAX_LITTLENUMS 6
4713
47926f60
KH		 4714/* Turn the string pointed to by litP into a floating point constant
4715 of type TYPE, and emit the appropriate bytes. The number of
4716 LITTLENUMS emitted is stored in *SIZEP. An error message is
4717 returned, or NULL on OK. */
4718
252b5132
RH		 4719char *
4720md_atof (type, litP, sizeP)
2ab9b79e 4721 int type;
252b5132
RH		 4722 char *litP;
4723 int *sizeP;
4724{
4725 int prec;
4726 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4727 LITTLENUM_TYPE *wordP;
4728 char *t;
4729
4730 switch (type)
4731 {
4732 case 'f':
4733 case 'F':
4734 prec = 2;
4735 break;
4736
4737 case 'd':
4738 case 'D':
4739 prec = 4;
4740 break;
4741
4742 case 'x':
4743 case 'X':
4744 prec = 5;
4745 break;
4746
4747 default:
4748 *sizeP = 0;
4749 return _("Bad call to md_atof ()");
4750 }
4751 t = atof_ieee (input_line_pointer, type, words);
4752 if (t)
4753 input_line_pointer = t;
4754
4755 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4756 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4757 the bigendian 386. */
4758 for (wordP = words + prec - 1; prec--;)
4759 {
4760 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4761 litP += sizeof (LITTLENUM_TYPE);
4762 }
4763 return 0;
4764}
4765\f
4766char output_invalid_buf[8];
4767
252b5132
RH		 4768static char *
4769output_invalid (c)
4770 int c;
4771{
3882b010 4772 if (ISPRINT (c))
252b5132
RH		 4773 sprintf (output_invalid_buf, "'%c'", c);
4774 else
4775 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4776 return output_invalid_buf;
4777}
4778
af6bdddf 4779/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4780
4781static const reg_entry *
4782parse_register (reg_string, end_op)
4783 char *reg_string;
4784 char **end_op;
4785{
af6bdddf
AM		 4786 char *s = reg_string;
4787 char *p;
252b5132
RH		 4788 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4789 const reg_entry *r;
4790
4791 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4792 if (*s == REGISTER_PREFIX)
4793 ++s;
4794
4795 if (is_space_char (*s))
4796 ++s;
4797
4798 p = reg_name_given;
af6bdddf 4799 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4800 {
4801 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4802 return (const reg_entry *) NULL;
4803 s++;
252b5132
RH		 4804 }
4805
6588847e
DN		 4806 /* For naked regs, make sure that we are not dealing with an identifier.
4807 This prevents confusing an identifier like `eax_var' with register
4808 `eax'. */
4809 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4810 return (const reg_entry *) NULL;
4811
af6bdddf 4812 *end_op = s;
252b5132
RH		 4813
4814 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4815
5f47d35b 4816 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4817 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4818 {
5f47d35b
AM		 4819 if (is_space_char (*s))
4820 ++s;
4821 if (*s == '(')
4822 {
af6bdddf 4823 ++s;
5f47d35b
AM		 4824 if (is_space_char (*s))
4825 ++s;
4826 if (*s >= '0' && *s <= '7')
4827 {
4828 r = &i386_float_regtab[*s - '0'];
af6bdddf 4829 ++s;
5f47d35b
AM		 4830 if (is_space_char (*s))
4831 ++s;
4832 if (*s == ')')
4833 {
4834 *end_op = s + 1;
4835 return r;
4836 }
5f47d35b 4837 }
47926f60 4838 /* We have "%st(" then garbage. */
5f47d35b
AM		 4839 return (const reg_entry *) NULL;
4840 }
4841 }
4842
1ae00879 4843 if (r != NULL
29b0f896 4844 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4845 && flag_code != CODE_64BIT)
4846 {
4847 return (const reg_entry *) NULL;
4848 }
4849
252b5132
RH		 4850 return r;
4851}
4852\f
4cc782b5 4853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4854const char *md_shortopts = "kVQ:sq";
252b5132 4855#else
65172ab8 4856const char *md_shortopts = "q";
252b5132 4857#endif
6e0b89ee 4858
252b5132 4859struct option md_longopts[] = {
3e73aa7c
JH		 4860#define OPTION_32 (OPTION_MD_BASE + 0)
4861 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4862#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4863#define OPTION_64 (OPTION_MD_BASE + 1)
4864 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4865#endif
252b5132
RH		 4866 {NULL, no_argument, NULL, 0}
4867};
4868size_t md_longopts_size = sizeof (md_longopts);
4869
4870int
4871md_parse_option (c, arg)
4872 int c;
ab9da554 4873 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4874{
4875 switch (c)
4876 {
a38cf1db
AM		 4877 case 'q':
4878 quiet_warnings = 1;
252b5132
RH		 4879 break;
4880
4881#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4882 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4883 should be emitted or not. FIXME: Not implemented. */
4884 case 'Q':
252b5132
RH		 4885 break;
4886
4887 /* -V: SVR4 argument to print version ID. */
4888 case 'V':
4889 print_version_id ();
4890 break;
4891
a38cf1db
AM		 4892 /* -k: Ignore for FreeBSD compatibility. */
4893 case 'k':
252b5132 4894 break;
4cc782b5
ILT		 4895
4896 case 's':
4897 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4898 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4899 break;
6e0b89ee 4900
3e73aa7c
JH		 4901 case OPTION_64:
4902 {
4903 const char **list, **l;
4904
3e73aa7c
JH		 4905 list = bfd_target_list ();
4906 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4907 if (strcmp (*l, "elf64-x86-64") == 0)
4908 {
4909 default_arch = "x86_64";
4910 break;
4911 }
3e73aa7c 4912 if (*l == NULL)
6e0b89ee 4913 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4914 free (list);
4915 }
4916 break;
4917#endif
252b5132 4918
6e0b89ee
AM		 4919 case OPTION_32:
4920 default_arch = "i386";
4921 break;
4922
252b5132
RH		 4923 default:
4924 return 0;
4925 }
4926 return 1;
4927}
4928
4929void
4930md_show_usage (stream)
4931 FILE *stream;
4932{
4cc782b5
ILT		 4933#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4934 fprintf (stream, _("\
a38cf1db
AM		 4935 -Q ignored\n\
4936 -V print assembler version number\n\
4937 -k ignored\n\
4938 -q quieten some warnings\n\
4939 -s ignored\n"));
4940#else
4941 fprintf (stream, _("\
4942 -q quieten some warnings\n"));
4cc782b5 4943#endif
252b5132
RH		 4944}
4945
4946#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4947#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4948 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4949
4950/* Pick the target format to use. */
4951
47926f60 4952const char *
252b5132
RH		 4953i386_target_format ()
4954{
3e73aa7c
JH		 4955 if (!strcmp (default_arch, "x86_64"))
4956 set_code_flag (CODE_64BIT);
4957 else if (!strcmp (default_arch, "i386"))
4958 set_code_flag (CODE_32BIT);
4959 else
4960 as_fatal (_("Unknown architecture"));
252b5132
RH		 4961 switch (OUTPUT_FLAVOR)
4962 {
4c63da97
AM		 4963#ifdef OBJ_MAYBE_AOUT
4964 case bfd_target_aout_flavour:
47926f60 4965 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4966#endif
4967#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4968 case bfd_target_coff_flavour:
4969 return "coff-i386";
4c63da97 4970#endif
3e73aa7c 4971#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4972 case bfd_target_elf_flavour:
3e73aa7c 4973 {
e5cb08ac
KH		 4974 if (flag_code == CODE_64BIT)
4975 use_rela_relocations = 1;
4ada7262 4976 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 4977 }
4c63da97 4978#endif
252b5132
RH		 4979 default:
4980 abort ();
4981 return NULL;
4982 }
4983}
4984
47926f60 4985#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4986
4987#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4988void i386_elf_emit_arch_note ()
4989{
4990 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4991 && cpu_arch_name != NULL)
4992 {
4993 char *p;
4994 asection *seg = now_seg;
4995 subsegT subseg = now_subseg;
4996 Elf_Internal_Note i_note;
4997 Elf_External_Note e_note;
4998 asection *note_secp;
4999 int len;
5000
5001 /* Create the .note section. */
5002 note_secp = subseg_new (".note", 0);
5003 bfd_set_section_flags (stdoutput,
5004 note_secp,
5005 SEC_HAS_CONTENTS | SEC_READONLY);
5006
5007 /* Process the arch string. */
5008 len = strlen (cpu_arch_name);
5009
5010 i_note.namesz = len + 1;
5011 i_note.descsz = 0;
5012 i_note.type = NT_ARCH;
5013 p = frag_more (sizeof (e_note.namesz));
5014 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5015 p = frag_more (sizeof (e_note.descsz));
5016 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5017 p = frag_more (sizeof (e_note.type));
5018 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5019 p = frag_more (len + 1);
5020 strcpy (p, cpu_arch_name);
5021
5022 frag_align (2, 0, 0);
5023
5024 subseg_set (seg, subseg);
5025 }
5026}
5027#endif
47926f60 5028#endif /* BFD_ASSEMBLER */
252b5132 5029\f
252b5132
RH		 5030symbolS *
5031md_undefined_symbol (name)
5032 char *name;
5033{
18dc2407
ILT		 5034 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5035 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5036 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5037 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5038 {
5039 if (!GOT_symbol)
5040 {
5041 if (symbol_find (name))
5042 as_bad (_("GOT already in symbol table"));
5043 GOT_symbol = symbol_new (name, undefined_section,
5044 (valueT) 0, &zero_address_frag);
5045 };
5046 return GOT_symbol;
5047 }
252b5132
RH		 5048 return 0;
5049}
5050
5051/* Round up a section size to the appropriate boundary. */
47926f60 5052
252b5132
RH		 5053valueT
5054md_section_align (segment, size)
ab9da554 5055 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5056 valueT size;
5057{
252b5132 5058#ifdef BFD_ASSEMBLER
4c63da97
AM		 5059#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5060 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5061 {
5062 /* For a.out, force the section size to be aligned. If we don't do
5063 this, BFD will align it for us, but it will not write out the
5064 final bytes of the section. This may be a bug in BFD, but it is
5065 easier to fix it here since that is how the other a.out targets
5066 work. */
5067 int align;
5068
5069 align = bfd_get_section_alignment (stdoutput, segment);
5070 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5071 }
252b5132
RH		 5072#endif
5073#endif
5074
5075 return size;
5076}
5077
5078/* On the i386, PC-relative offsets are relative to the start of the
5079 next instruction. That is, the address of the offset, plus its
5080 size, since the offset is always the last part of the insn. */
5081
5082long
5083md_pcrel_from (fixP)
5084 fixS *fixP;
5085{
5086 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5087}
5088
5089#ifndef I386COFF
5090
5091static void
5092s_bss (ignore)
ab9da554 5093 int ignore ATTRIBUTE_UNUSED;
252b5132 5094{
29b0f896 5095 int temp;
252b5132
RH		 5096
5097 temp = get_absolute_expression ();
5098 subseg_set (bss_section, (subsegT) temp);
5099 demand_empty_rest_of_line ();
5100}
5101
5102#endif
5103
252b5132
RH		 5104#ifdef BFD_ASSEMBLER
5105
5106void
5107i386_validate_fix (fixp)
5108 fixS *fixp;
5109{
5110 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5111 {
3e73aa7c 5112 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5113 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5114 {
5115 if (flag_code != CODE_64BIT)
5116 abort ();
5117 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5118 }
5119 else
5120 {
5121 if (flag_code == CODE_64BIT)
5122 abort ();
5123 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5124 }
252b5132
RH		 5125 fixp->fx_subsy = 0;
5126 }
5127}
5128
a161fe53
AM		 5129boolean
5130i386_force_relocation (fixp)
5131 fixS *fixp;
5132{
5133 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5134 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5135 return 1;
5136
5137 return S_FORCE_RELOC (fixp->fx_addsy);
5138}
5139
252b5132
RH		 5140arelent *
5141tc_gen_reloc (section, fixp)
ab9da554 5142 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5143 fixS *fixp;
5144{
5145 arelent *rel;
5146 bfd_reloc_code_real_type code;
5147
5148 switch (fixp->fx_r_type)
5149 {
3e73aa7c
JH		 5150 case BFD_RELOC_X86_64_PLT32:
5151 case BFD_RELOC_X86_64_GOT32:
5152 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5153 case BFD_RELOC_386_PLT32:
5154 case BFD_RELOC_386_GOT32:
5155 case BFD_RELOC_386_GOTOFF:
5156 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5157 case BFD_RELOC_386_TLS_GD:
5158 case BFD_RELOC_386_TLS_LDM:
5159 case BFD_RELOC_386_TLS_LDO_32:
5160 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5161 case BFD_RELOC_386_TLS_IE:
5162 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5163 case BFD_RELOC_386_TLS_LE_32:
5164 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5165 case BFD_RELOC_X86_64_32S:
bffbf940
JJ		 5166 case BFD_RELOC_X86_64_TLSGD:
5167 case BFD_RELOC_X86_64_TLSLD:
5168 case BFD_RELOC_X86_64_DTPOFF32:
5169 case BFD_RELOC_X86_64_GOTTPOFF:
5170 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5171 case BFD_RELOC_RVA:
5172 case BFD_RELOC_VTABLE_ENTRY:
5173 case BFD_RELOC_VTABLE_INHERIT:
5174 code = fixp->fx_r_type;
5175 break;
5176 default:
93382f6d 5177 if (fixp->fx_pcrel)
252b5132 5178 {
93382f6d
AM		 5179 switch (fixp->fx_size)
5180 {
5181 default:
b091f402
AM		 5182 as_bad_where (fixp->fx_file, fixp->fx_line,
5183 _("can not do %d byte pc-relative relocation"),
5184 fixp->fx_size);
93382f6d
AM		 5185 code = BFD_RELOC_32_PCREL;
5186 break;
5187 case 1: code = BFD_RELOC_8_PCREL; break;
5188 case 2: code = BFD_RELOC_16_PCREL; break;
5189 case 4: code = BFD_RELOC_32_PCREL; break;
5190 }
5191 }
5192 else
5193 {
5194 switch (fixp->fx_size)
5195 {
5196 default:
b091f402
AM		 5197 as_bad_where (fixp->fx_file, fixp->fx_line,
5198 _("can not do %d byte relocation"),
5199 fixp->fx_size);
93382f6d
AM		 5200 code = BFD_RELOC_32;
5201 break;
5202 case 1: code = BFD_RELOC_8; break;
5203 case 2: code = BFD_RELOC_16; break;
5204 case 4: code = BFD_RELOC_32; break;
937149dd 5205#ifdef BFD64
3e73aa7c 5206 case 8: code = BFD_RELOC_64; break;
937149dd 5207#endif
93382f6d 5208 }
252b5132
RH		 5209 }
5210 break;
5211 }
252b5132
RH		 5212
5213 if (code == BFD_RELOC_32
5214 && GOT_symbol
5215 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5216 {
5217 /* We don't support GOTPC on 64bit targets. */
5218 if (flag_code == CODE_64BIT)
bfb32b52 5219 abort ();
3e73aa7c
JH		 5220 code = BFD_RELOC_386_GOTPC;
5221 }
252b5132
RH		 5222
5223 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5224 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5225 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5226
5227 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5228 if (!use_rela_relocations)
5229 {
5230 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5231 vtable entry to be used in the relocation's section offset. */
5232 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5233 rel->address = fixp->fx_offset;
252b5132 5234
c6682705 5235 rel->addend = 0;
3e73aa7c
JH		 5236 }
5237 /* Use the rela in 64bit mode. */
252b5132 5238 else
3e73aa7c 5239 {
062cd5e7
AS		 5240 if (!fixp->fx_pcrel)
5241 rel->addend = fixp->fx_offset;
5242 else
5243 switch (code)
5244 {
5245 case BFD_RELOC_X86_64_PLT32:
5246 case BFD_RELOC_X86_64_GOT32:
5247 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5248 case BFD_RELOC_X86_64_TLSGD:
5249 case BFD_RELOC_X86_64_TLSLD:
5250 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5251 rel->addend = fixp->fx_offset - fixp->fx_size;
5252 break;
5253 default:
5254 rel->addend = (section->vma
5255 - fixp->fx_size
5256 + fixp->fx_addnumber
5257 + md_pcrel_from (fixp));
5258 break;
5259 }
3e73aa7c
JH		 5260 }
5261
252b5132
RH		 5262 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5263 if (rel->howto == NULL)
5264 {
5265 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5266 _("cannot represent relocation type %s"),
252b5132
RH		 5267 bfd_get_reloc_code_name (code));
5268 /* Set howto to a garbage value so that we can keep going. */
5269 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5270 assert (rel->howto != NULL);
5271 }
5272
5273 return rel;
5274}
5275
29b0f896 5276#else /* !BFD_ASSEMBLER */
252b5132
RH		 5277
5278#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5279void
5280tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5281 char *where;
5282 fixS *fixP;
5283 relax_addressT segment_address_in_file;
5284{
47926f60
KH		 5285 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5286 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5287
47926f60 5288 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5289 long r_symbolnum;
5290
5291 know (fixP->fx_addsy != NULL);
5292
5293 md_number_to_chars (where,
5294 (valueT) (fixP->fx_frag->fr_address
5295 + fixP->fx_where - segment_address_in_file),
5296 4);
5297
5298 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5299 ? S_GET_TYPE (fixP->fx_addsy)
5300 : fixP->fx_addsy->sy_number);
5301
5302 where[6] = (r_symbolnum >> 16) & 0x0ff;
5303 where[5] = (r_symbolnum >> 8) & 0x0ff;
5304 where[4] = r_symbolnum & 0x0ff;
5305 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5306 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5307 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5308}
5309
47926f60 5310#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5311
5312#if defined (I386COFF)
5313
5314short
5315tc_coff_fix2rtype (fixP)
5316 fixS *fixP;
5317{
5318 if (fixP->fx_r_type == R_IMAGEBASE)
5319 return R_IMAGEBASE;
5320
5321 return (fixP->fx_pcrel ?
5322 (fixP->fx_size == 1 ? R_PCRBYTE :
5323 fixP->fx_size == 2 ? R_PCRWORD :
5324 R_PCRLONG) :
5325 (fixP->fx_size == 1 ? R_RELBYTE :
5326 fixP->fx_size == 2 ? R_RELWORD :
5327 R_DIR32));
5328}
5329
5330int
5331tc_coff_sizemachdep (frag)
5332 fragS *frag;
5333{
5334 if (frag->fr_next)
5335 return (frag->fr_next->fr_address - frag->fr_address);
5336 else
5337 return 0;
5338}
5339
47926f60 5340#endif /* I386COFF */
252b5132 5341
29b0f896 5342#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5343\f
5344/* Parse operands using Intel syntax. This implements a recursive descent
5345 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5346 Programmer's Guide.
5347
5348 FIXME: We do not recognize the full operand grammar defined in the MASM
5349 documentation. In particular, all the structure/union and
5350 high-level macro operands are missing.
5351
5352 Uppercase words are terminals, lower case words are non-terminals.
5353 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5354 bars '|' denote choices. Most grammar productions are implemented in
5355 functions called 'intel_<production>'.
5356
5357 Initial production is 'expr'.
5358
64a0c779
DN		 5359 addOp + | -
5360
5361 alpha [a-zA-Z]
5362
5363 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5364
5365 constant digits [[ radixOverride ]]
5366
5367 dataType BYTE | WORD | DWORD | QWORD | XWORD
5368
5369 digits decdigit
b77a7acd
AJ		 5370 | digits decdigit
5371 | digits hexdigit
64a0c779
DN		 5372
5373 decdigit [0-9]
5374
5375 e05 e05 addOp e06
b77a7acd 5376 | e06
64a0c779
DN		 5377
5378 e06 e06 mulOp e09
b77a7acd 5379 | e09
64a0c779
DN		 5380
5381 e09 OFFSET e10
5382 | e09 PTR e10
5383 | e09 : e10
5384 | e10
5385
5386 e10 e10 [ expr ]
b77a7acd 5387 | e11
64a0c779
DN		 5388
5389 e11 ( expr )
b77a7acd 5390 | [ expr ]
64a0c779
DN		 5391 | constant
5392 | dataType
5393 | id
5394 | $
5395 | register
5396
5397 => expr SHORT e05
b77a7acd 5398 | e05
64a0c779
DN		 5399
5400 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5401 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5402
5403 hexdigit a | b | c | d | e | f
b77a7acd 5404 | A | B | C | D | E | F
64a0c779
DN		 5405
5406 id alpha
b77a7acd 5407 | id alpha
64a0c779
DN		 5408 | id decdigit
5409
5410 mulOp * | / | MOD
5411
5412 quote " | '
5413
5414 register specialRegister
b77a7acd 5415 | gpRegister
64a0c779
DN		 5416 | byteRegister
5417
5418 segmentRegister CS | DS | ES | FS | GS | SS
5419
5420 specialRegister CR0 | CR2 | CR3
b77a7acd 5421 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5422 | TR3 | TR4 | TR5 | TR6 | TR7
5423
64a0c779
DN		 5424 We simplify the grammar in obvious places (e.g., register parsing is
5425 done by calling parse_register) and eliminate immediate left recursion
5426 to implement a recursive-descent parser.
5427
5428 expr SHORT e05
b77a7acd 5429 | e05
64a0c779
DN		 5430
5431 e05 e06 e05'
5432
5433 e05' addOp e06 e05'
b77a7acd 5434 | Empty
64a0c779
DN		 5435
5436 e06 e09 e06'
5437
5438 e06' mulOp e09 e06'
b77a7acd 5439 | Empty
64a0c779
DN		 5440
5441 e09 OFFSET e10 e09'
b77a7acd 5442 | e10 e09'
64a0c779
DN		 5443
5444 e09' PTR e10 e09'
b77a7acd 5445 | : e10 e09'
64a0c779
DN		 5446 | Empty
5447
5448 e10 e11 e10'
5449
5450 e10' [ expr ] e10'
b77a7acd 5451 | Empty
64a0c779
DN		 5452
5453 e11 ( expr )
b77a7acd 5454 | [ expr ]
64a0c779
DN		 5455 | BYTE
5456 | WORD
5457 | DWORD
5458 | QWORD
5459 | XWORD
5460 | .
5461 | $
5462 | register
5463 | id
5464 | constant */
5465
5466/* Parsing structure for the intel syntax parser. Used to implement the
5467 semantic actions for the operand grammar. */
5468struct intel_parser_s
5469 {
5470 char *op_string; /* The string being parsed. */
5471 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5472 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5473 int is_mem; /* 1 if operand is memory reference. */
5474 const reg_entry *reg; /* Last register reference found. */
5475 char *disp; /* Displacement string being built. */
5476 };
5477
5478static struct intel_parser_s intel_parser;
5479
5480/* Token structure for parsing intel syntax. */
5481struct intel_token
5482 {
5483 int code; /* Token code. */
5484 const reg_entry *reg; /* Register entry for register tokens. */
5485 char *str; /* String representation. */
5486 };
5487
5488static struct intel_token cur_token, prev_token;
5489
50705ef4
AM		 5490/* Token codes for the intel parser. Since T_SHORT is already used
5491 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5492#define T_NIL -1
5493#define T_CONST 1
5494#define T_REG 2
5495#define T_BYTE 3
5496#define T_WORD 4
5497#define T_DWORD 5
5498#define T_QWORD 6
5499#define T_XWORD 7
50705ef4 5500#undef T_SHORT
64a0c779
DN		 5501#define T_SHORT 8
5502#define T_OFFSET 9
5503#define T_PTR 10
5504#define T_ID 11
5505
5506/* Prototypes for intel parser functions. */
5507static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5508static void intel_get_token PARAMS ((void));
5509static void intel_putback_token PARAMS ((void));
5510static int intel_expr PARAMS ((void));
5511static int intel_e05 PARAMS ((void));
5512static int intel_e05_1 PARAMS ((void));
5513static int intel_e06 PARAMS ((void));
5514static int intel_e06_1 PARAMS ((void));
5515static int intel_e09 PARAMS ((void));
5516static int intel_e09_1 PARAMS ((void));
5517static int intel_e10 PARAMS ((void));
5518static int intel_e10_1 PARAMS ((void));
5519static int intel_e11 PARAMS ((void));
64a0c779 5520
64a0c779
DN		 5521static int
5522i386_intel_operand (operand_string, got_a_float)
5523 char *operand_string;
5524 int got_a_float;
5525{
5526 int ret;
5527 char *p;
5528
5529 /* Initialize token holders. */
5530 cur_token.code = prev_token.code = T_NIL;
5531 cur_token.reg = prev_token.reg = NULL;
5532 cur_token.str = prev_token.str = NULL;
5533
5534 /* Initialize parser structure. */
e5cb08ac 5535 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5536 if (p == NULL)
5537 abort ();
5538 strcpy (intel_parser.op_string, operand_string);
5539 intel_parser.got_a_float = got_a_float;
5540 intel_parser.op_modifier = -1;
5541 intel_parser.is_mem = 0;
5542 intel_parser.reg = NULL;
e5cb08ac 5543 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5544 if (intel_parser.disp == NULL)
5545 abort ();
5546 intel_parser.disp[0] = '\0';
5547
5548 /* Read the first token and start the parser. */
5549 intel_get_token ();
5550 ret = intel_expr ();
5551
5552 if (ret)
5553 {
5554 /* If we found a memory reference, hand it over to i386_displacement
5555 to fill in the rest of the operand fields. */
5556 if (intel_parser.is_mem)
5557 {
5558 if ((i.mem_operands == 1
5559 && (current_templates->start->opcode_modifier & IsString) == 0)
5560 || i.mem_operands == 2)
5561 {
5562 as_bad (_("too many memory references for '%s'"),
5563 current_templates->start->name);
5564 ret = 0;
5565 }
5566 else
5567 {
5568 char *s = intel_parser.disp;
5569 i.mem_operands++;
5570
5571 /* Add the displacement expression. */
5572 if (*s != '\0')
5573 ret = i386_displacement (s, s + strlen (s))
5574 && i386_index_check (s);
5575 }
5576 }
5577
5578 /* Constant and OFFSET expressions are handled by i386_immediate. */
5579 else if (intel_parser.op_modifier == OFFSET_FLAT
5580 || intel_parser.reg == NULL)
5581 ret = i386_immediate (intel_parser.disp);
5582 }
5583
5584 free (p);
5585 free (intel_parser.disp);
5586
5587 return ret;
5588}
5589
64a0c779 5590/* expr SHORT e05
b77a7acd 5591 | e05 */
64a0c779
DN		 5592static int
5593intel_expr ()
5594{
5595 /* expr SHORT e05 */
5596 if (cur_token.code == T_SHORT)
5597 {
5598 intel_parser.op_modifier = SHORT;
5599 intel_match_token (T_SHORT);
5600
5601 return (intel_e05 ());
5602 }
5603
5604 /* expr e05 */
5605 else
5606 return intel_e05 ();
5607}
5608
64a0c779
DN		 5609/* e05 e06 e05'
5610
4a1805b1 5611 e05' addOp e06 e05'
64a0c779
DN		 5612 | Empty */
5613static int
5614intel_e05 ()
5615{
5616 return (intel_e06 () && intel_e05_1 ());
5617}
5618
5619static int
5620intel_e05_1 ()
5621{
5622 /* e05' addOp e06 e05' */
5623 if (cur_token.code == '+' || cur_token.code == '-')
5624 {
5625 strcat (intel_parser.disp, cur_token.str);
5626 intel_match_token (cur_token.code);
5627
5628 return (intel_e06 () && intel_e05_1 ());
5629 }
5630
5631 /* e05' Empty */
5632 else
5633 return 1;
4a1805b1 5634}
64a0c779
DN		 5635
5636/* e06 e09 e06'
5637
5638 e06' mulOp e09 e06'
b77a7acd 5639 | Empty */
64a0c779
DN		 5640static int
5641intel_e06 ()
5642{
5643 return (intel_e09 () && intel_e06_1 ());
5644}
5645
5646static int
5647intel_e06_1 ()
5648{
5649 /* e06' mulOp e09 e06' */
5650 if (cur_token.code == '*' || cur_token.code == '/')
5651 {
5652 strcat (intel_parser.disp, cur_token.str);
5653 intel_match_token (cur_token.code);
5654
5655 return (intel_e09 () && intel_e06_1 ());
5656 }
4a1805b1 5657
64a0c779 5658 /* e06' Empty */
4a1805b1 5659 else
64a0c779
DN		 5660 return 1;
5661}
5662
64a0c779 5663/* e09 OFFSET e10 e09'
b77a7acd 5664 | e10 e09'
64a0c779
DN		 5665
5666 e09' PTR e10 e09'
b77a7acd 5667 | : e10 e09'
64a0c779
DN		 5668 | Empty */
5669static int
5670intel_e09 ()
5671{
5672 /* e09 OFFSET e10 e09' */
5673 if (cur_token.code == T_OFFSET)
5674 {
5675 intel_parser.is_mem = 0;
5676 intel_parser.op_modifier = OFFSET_FLAT;
5677 intel_match_token (T_OFFSET);
5678
5679 return (intel_e10 () && intel_e09_1 ());
5680 }
5681
5682 /* e09 e10 e09' */
5683 else
5684 return (intel_e10 () && intel_e09_1 ());
5685}
5686
5687static int
5688intel_e09_1 ()
5689{
5690 /* e09' PTR e10 e09' */
5691 if (cur_token.code == T_PTR)
5692 {
5693 if (prev_token.code == T_BYTE)
5694 i.suffix = BYTE_MNEM_SUFFIX;
5695
5696 else if (prev_token.code == T_WORD)
5697 {
5698 if (intel_parser.got_a_float == 2) /* "fi..." */
5699 i.suffix = SHORT_MNEM_SUFFIX;
5700 else
5701 i.suffix = WORD_MNEM_SUFFIX;
5702 }
5703
5704 else if (prev_token.code == T_DWORD)
5705 {
5706 if (intel_parser.got_a_float == 1) /* "f..." */
5707 i.suffix = SHORT_MNEM_SUFFIX;
5708 else
5709 i.suffix = LONG_MNEM_SUFFIX;
5710 }
5711
5712 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5713 {
5714 if (intel_parser.got_a_float == 1) /* "f..." */
5715 i.suffix = LONG_MNEM_SUFFIX;
5716 else
3e73aa7c 5717 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5718 }
64a0c779
DN		 5719
5720 else if (prev_token.code == T_XWORD)
5721 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5722
5723 else
5724 {
5725 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5726 return 0;
5727 }
5728
5729 intel_match_token (T_PTR);
5730
5731 return (intel_e10 () && intel_e09_1 ());
5732 }
5733
5734 /* e09 : e10 e09' */
5735 else if (cur_token.code == ':')
5736 {
21d6c4af
DN		 5737 /* Mark as a memory operand only if it's not already known to be an
5738 offset expression. */
5739 if (intel_parser.op_modifier != OFFSET_FLAT)
5740 intel_parser.is_mem = 1;
64a0c779
DN		 5741
5742 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5743 }
5744
5745 /* e09' Empty */
5746 else
5747 return 1;
5748}
5749
5750/* e10 e11 e10'
5751
5752 e10' [ expr ] e10'
b77a7acd 5753 | Empty */
64a0c779
DN		 5754static int
5755intel_e10 ()
5756{
5757 return (intel_e11 () && intel_e10_1 ());
5758}
5759
5760static int
5761intel_e10_1 ()
5762{
5763 /* e10' [ expr ] e10' */
5764 if (cur_token.code == '[')
5765 {
5766 intel_match_token ('[');
21d6c4af
DN		 5767
5768 /* Mark as a memory operand only if it's not already known to be an
5769 offset expression. If it's an offset expression, we need to keep
5770 the brace in. */
5771 if (intel_parser.op_modifier != OFFSET_FLAT)
5772 intel_parser.is_mem = 1;
5773 else
5774 strcat (intel_parser.disp, "[");
4a1805b1 5775
64a0c779 5776 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5777 if (*intel_parser.disp != '\0'
5778 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5779 strcat (intel_parser.disp, "+");
5780
21d6c4af
DN		 5781 if (intel_expr () && intel_match_token (']'))
5782 {
5783 /* Preserve brackets when the operand is an offset expression. */
5784 if (intel_parser.op_modifier == OFFSET_FLAT)
5785 strcat (intel_parser.disp, "]");
5786
5787 return intel_e10_1 ();
5788 }
5789 else
5790 return 0;
64a0c779
DN		 5791 }
5792
5793 /* e10' Empty */
5794 else
5795 return 1;
5796}
5797
64a0c779 5798/* e11 ( expr )
b77a7acd 5799 | [ expr ]
64a0c779
DN		 5800 | BYTE
5801 | WORD
5802 | DWORD
5803 | QWORD
5804 | XWORD
4a1805b1 5805 | $
64a0c779
DN		 5806 | .
5807 | register
5808 | id
5809 | constant */
5810static int
5811intel_e11 ()
5812{
5813 /* e11 ( expr ) */
5814 if (cur_token.code == '(')
5815 {
5816 intel_match_token ('(');
5817 strcat (intel_parser.disp, "(");
5818
5819 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5820 {
5821 strcat (intel_parser.disp, ")");
5822 return 1;
5823 }
64a0c779
DN		 5824 else
5825 return 0;
5826 }
5827
5828 /* e11 [ expr ] */
5829 else if (cur_token.code == '[')
5830 {
5831 intel_match_token ('[');
21d6c4af
DN		 5832
5833 /* Mark as a memory operand only if it's not already known to be an
5834 offset expression. If it's an offset expression, we need to keep
5835 the brace in. */
5836 if (intel_parser.op_modifier != OFFSET_FLAT)
5837 intel_parser.is_mem = 1;
5838 else
5839 strcat (intel_parser.disp, "[");
4a1805b1 5840
64a0c779
DN		 5841 /* Operands for jump/call inside brackets denote absolute addresses. */
5842 if (current_templates->start->opcode_modifier & Jump
5843 || current_templates->start->opcode_modifier & JumpDword
5844 || current_templates->start->opcode_modifier & JumpByte
5845 || current_templates->start->opcode_modifier & JumpInterSegment)
5846 i.types[this_operand] |= JumpAbsolute;
5847
5848 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5849 if (*intel_parser.disp != '\0'
5850 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5851 strcat (intel_parser.disp, "+");
5852
21d6c4af
DN		 5853 if (intel_expr () && intel_match_token (']'))
5854 {
5855 /* Preserve brackets when the operand is an offset expression. */
5856 if (intel_parser.op_modifier == OFFSET_FLAT)
5857 strcat (intel_parser.disp, "]");
5858
5859 return 1;
5860 }
5861 else
5862 return 0;
64a0c779
DN		 5863 }
5864
4a1805b1 5865 /* e11 BYTE
64a0c779
DN		 5866 | WORD
5867 | DWORD
5868 | QWORD
5869 | XWORD */
5870 else if (cur_token.code == T_BYTE
5871 || cur_token.code == T_WORD
5872 || cur_token.code == T_DWORD
5873 || cur_token.code == T_QWORD
5874 || cur_token.code == T_XWORD)
5875 {
5876 intel_match_token (cur_token.code);
5877
5878 return 1;
5879 }
5880
5881 /* e11 $
5882 | . */
5883 else if (cur_token.code == '$' || cur_token.code == '.')
5884 {
5885 strcat (intel_parser.disp, cur_token.str);
5886 intel_match_token (cur_token.code);
21d6c4af
DN		 5887
5888 /* Mark as a memory operand only if it's not already known to be an
5889 offset expression. */
5890 if (intel_parser.op_modifier != OFFSET_FLAT)
5891 intel_parser.is_mem = 1;
64a0c779
DN		 5892
5893 return 1;
5894 }
5895
5896 /* e11 register */
5897 else if (cur_token.code == T_REG)
5898 {
5899 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5900
5901 intel_match_token (T_REG);
5902
5903 /* Check for segment change. */
5904 if (cur_token.code == ':')
5905 {
5906 if (reg->reg_type & (SReg2 | SReg3))
5907 {
5908 switch (reg->reg_num)
5909 {
5910 case 0:
5911 i.seg[i.mem_operands] = &es;
5912 break;
5913 case 1:
5914 i.seg[i.mem_operands] = &cs;
5915 break;
5916 case 2:
5917 i.seg[i.mem_operands] = &ss;
5918 break;
5919 case 3:
5920 i.seg[i.mem_operands] = &ds;
5921 break;
5922 case 4:
5923 i.seg[i.mem_operands] = &fs;
5924 break;
5925 case 5:
5926 i.seg[i.mem_operands] = &gs;
5927 break;
5928 }
5929 }
5930 else
5931 {
5932 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5933 return 0;
5934 }
5935 }
5936
5937 /* Not a segment register. Check for register scaling. */
5938 else if (cur_token.code == '*')
5939 {
5940 if (!intel_parser.is_mem)
5941 {
5942 as_bad (_("Register scaling only allowed in memory operands."));
5943 return 0;
5944 }
5945
4a1805b1 5946 /* What follows must be a valid scale. */
64a0c779
DN		 5947 if (intel_match_token ('*')
5948 && strchr ("01248", *cur_token.str))
5949 {
5950 i.index_reg = reg;
5951 i.types[this_operand] |= BaseIndex;
5952
5953 /* Set the scale after setting the register (otherwise,
5954 i386_scale will complain) */
5955 i386_scale (cur_token.str);
5956 intel_match_token (T_CONST);
5957 }
5958 else
5959 {
5960 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5961 cur_token.str);
5962 return 0;
5963 }
5964 }
5965
5966 /* No scaling. If this is a memory operand, the register is either a
5967 base register (first occurrence) or an index register (second
5968 occurrence). */
5969 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5970 {
5971 if (i.base_reg && i.index_reg)
5972 {
5973 as_bad (_("Too many register references in memory operand.\n"));
5974 return 0;
5975 }
5976
5977 if (i.base_reg == NULL)
5978 i.base_reg = reg;
5979 else
5980 i.index_reg = reg;
5981
5982 i.types[this_operand] |= BaseIndex;
5983 }
5984
5985 /* Offset modifier. Add the register to the displacement string to be
5986 parsed as an immediate expression after we're done. */
5987 else if (intel_parser.op_modifier == OFFSET_FLAT)
5988 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5989
64a0c779
DN		 5990 /* It's neither base nor index nor offset. */
5991 else
5992 {
5993 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5994 i.op[this_operand].regs = reg;
5995 i.reg_operands++;
5996 }
5997
5998 /* Since registers are not part of the displacement string (except
5999 when we're parsing offset operands), we may need to remove any
6000 preceding '+' from the displacement string. */
6001 if (*intel_parser.disp != '\0'
6002 && intel_parser.op_modifier != OFFSET_FLAT)
6003 {
6004 char *s = intel_parser.disp;
6005 s += strlen (s) - 1;
6006 if (*s == '+')
6007 *s = '\0';
6008 }
6009
6010 return 1;
6011 }
4a1805b1 6012
64a0c779
DN		 6013 /* e11 id */
6014 else if (cur_token.code == T_ID)
6015 {
6016 /* Add the identifier to the displacement string. */
6017 strcat (intel_parser.disp, cur_token.str);
6018 intel_match_token (T_ID);
6019
6020 /* The identifier represents a memory reference only if it's not
6021 preceded by an offset modifier. */
21d6c4af 6022 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6023 intel_parser.is_mem = 1;
6024
6025 return 1;
6026 }
6027
6028 /* e11 constant */
6029 else if (cur_token.code == T_CONST
e5cb08ac 6030 || cur_token.code == '-'
64a0c779
DN		 6031 || cur_token.code == '+')
6032 {
6033 char *save_str;
6034
6035 /* Allow constants that start with `+' or `-'. */
6036 if (cur_token.code == '-' || cur_token.code == '+')
6037 {
6038 strcat (intel_parser.disp, cur_token.str);
6039 intel_match_token (cur_token.code);
6040 if (cur_token.code != T_CONST)
6041 {
6042 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6043 cur_token.str);
6044 return 0;
6045 }
6046 }
6047
e5cb08ac 6048 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6049 if (save_str == NULL)
bc805888 6050 abort ();
64a0c779
DN		 6051 strcpy (save_str, cur_token.str);
6052
6053 /* Get the next token to check for register scaling. */
6054 intel_match_token (cur_token.code);
6055
6056 /* Check if this constant is a scaling factor for an index register. */
6057 if (cur_token.code == '*')
6058 {
6059 if (intel_match_token ('*') && cur_token.code == T_REG)
6060 {
6061 if (!intel_parser.is_mem)
6062 {
6063 as_bad (_("Register scaling only allowed in memory operands."));
6064 return 0;
6065 }
6066
4a1805b1 6067 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6068 a valid scale. */
6069 if (strchr ("01248", *save_str))
6070 {
6071 i.index_reg = cur_token.reg;
6072 i.types[this_operand] |= BaseIndex;
6073
6074 /* Set the scale after setting the register (otherwise,
6075 i386_scale will complain) */
6076 i386_scale (save_str);
6077 intel_match_token (T_REG);
6078
6079 /* Since registers are not part of the displacement
6080 string, we may need to remove any preceding '+' from
6081 the displacement string. */
6082 if (*intel_parser.disp != '\0')
6083 {
6084 char *s = intel_parser.disp;
6085 s += strlen (s) - 1;
6086 if (*s == '+')
6087 *s = '\0';
6088 }
6089
6090 free (save_str);
6091
6092 return 1;
6093 }
6094 else
6095 return 0;
6096 }
6097
6098 /* The constant was not used for register scaling. Since we have
6099 already consumed the token following `*' we now need to put it
6100 back in the stream. */
6101 else
6102 intel_putback_token ();
6103 }
6104
6105 /* Add the constant to the displacement string. */
6106 strcat (intel_parser.disp, save_str);
6107 free (save_str);
6108
6109 return 1;
6110 }
6111
64a0c779
DN		 6112 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6113 return 0;
6114}
6115
64a0c779
DN		 6116/* Match the given token against cur_token. If they match, read the next
6117 token from the operand string. */
6118static int
6119intel_match_token (code)
e5cb08ac 6120 int code;
64a0c779
DN		 6121{
6122 if (cur_token.code == code)
6123 {
6124 intel_get_token ();
6125 return 1;
6126 }
6127 else
6128 {
6129 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6130 return 0;
6131 }
6132}
6133
64a0c779
DN		 6134/* Read a new token from intel_parser.op_string and store it in cur_token. */
6135static void
6136intel_get_token ()
6137{
6138 char *end_op;
6139 const reg_entry *reg;
6140 struct intel_token new_token;
6141
6142 new_token.code = T_NIL;
6143 new_token.reg = NULL;
6144 new_token.str = NULL;
6145
4a1805b1 6146 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6147 cur_token to prev_token. */
6148 if (prev_token.str)
6149 free (prev_token.str);
6150
6151 prev_token = cur_token;
6152
6153 /* Skip whitespace. */
6154 while (is_space_char (*intel_parser.op_string))
6155 intel_parser.op_string++;
6156
6157 /* Return an empty token if we find nothing else on the line. */
6158 if (*intel_parser.op_string == '\0')
6159 {
6160 cur_token = new_token;
6161 return;
6162 }
6163
6164 /* The new token cannot be larger than the remainder of the operand
6165 string. */
e5cb08ac 6166 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6167 if (new_token.str == NULL)
bc805888 6168 abort ();
64a0c779
DN		 6169 new_token.str[0] = '\0';
6170
6171 if (strchr ("0123456789", *intel_parser.op_string))
6172 {
6173 char *p = new_token.str;
6174 char *q = intel_parser.op_string;
6175 new_token.code = T_CONST;
6176
6177 /* Allow any kind of identifier char to encompass floating point and
6178 hexadecimal numbers. */
6179 while (is_identifier_char (*q))
6180 *p++ = *q++;
6181 *p = '\0';
6182
6183 /* Recognize special symbol names [0-9][bf]. */
6184 if (strlen (intel_parser.op_string) == 2
4a1805b1 6185 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6186 || intel_parser.op_string[1] == 'f'))
6187 new_token.code = T_ID;
6188 }
6189
6190 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6191 {
6192 new_token.code = *intel_parser.op_string;
6193 new_token.str[0] = *intel_parser.op_string;
6194 new_token.str[1] = '\0';
6195 }
6196
6197 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6198 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6199 {
6200 new_token.code = T_REG;
6201 new_token.reg = reg;
6202
6203 if (*intel_parser.op_string == REGISTER_PREFIX)
6204 {
6205 new_token.str[0] = REGISTER_PREFIX;
6206 new_token.str[1] = '\0';
6207 }
6208
6209 strcat (new_token.str, reg->reg_name);
6210 }
6211
6212 else if (is_identifier_char (*intel_parser.op_string))
6213 {
6214 char *p = new_token.str;
6215 char *q = intel_parser.op_string;
6216
6217 /* A '.' or '$' followed by an identifier char is an identifier.
6218 Otherwise, it's operator '.' followed by an expression. */
6219 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6220 {
6221 new_token.code = *q;
6222 new_token.str[0] = *q;
6223 new_token.str[1] = '\0';
6224 }
6225 else
6226 {
6227 while (is_identifier_char (*q) || *q == '@')
6228 *p++ = *q++;
6229 *p = '\0';
6230
6231 if (strcasecmp (new_token.str, "BYTE") == 0)
6232 new_token.code = T_BYTE;
6233
6234 else if (strcasecmp (new_token.str, "WORD") == 0)
6235 new_token.code = T_WORD;
6236
6237 else if (strcasecmp (new_token.str, "DWORD") == 0)
6238 new_token.code = T_DWORD;
6239
6240 else if (strcasecmp (new_token.str, "QWORD") == 0)
6241 new_token.code = T_QWORD;
6242
6243 else if (strcasecmp (new_token.str, "XWORD") == 0)
6244 new_token.code = T_XWORD;
6245
6246 else if (strcasecmp (new_token.str, "PTR") == 0)
6247 new_token.code = T_PTR;
6248
6249 else if (strcasecmp (new_token.str, "SHORT") == 0)
6250 new_token.code = T_SHORT;
6251
6252 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6253 {
6254 new_token.code = T_OFFSET;
6255
6256 /* ??? This is not mentioned in the MASM grammar but gcc
6257 makes use of it with -mintel-syntax. OFFSET may be
6258 followed by FLAT: */
6259 if (strncasecmp (q, " FLAT:", 6) == 0)
6260 strcat (new_token.str, " FLAT:");
6261 }
6262
6263 /* ??? This is not mentioned in the MASM grammar. */
6264 else if (strcasecmp (new_token.str, "FLAT") == 0)
6265 new_token.code = T_OFFSET;
6266
6267 else
6268 new_token.code = T_ID;
6269 }
6270 }
6271
6272 else
6273 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6274
6275 intel_parser.op_string += strlen (new_token.str);
6276 cur_token = new_token;
6277}
6278
64a0c779
DN		 6279/* Put cur_token back into the token stream and make cur_token point to
6280 prev_token. */
6281static void
6282intel_putback_token ()
6283{
6284 intel_parser.op_string -= strlen (cur_token.str);
6285 free (cur_token.str);
6286 cur_token = prev_token;
4a1805b1 6287
64a0c779
DN		 6288 /* Forget prev_token. */
6289 prev_token.code = T_NIL;
6290 prev_token.reg = NULL;
6291 prev_token.str = NULL;
6292}
GDB Binutils - Deliverables
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