projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* elf.c: Formatting.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
107static void output_imm PARAMS ((void));
108static void output_disp PARAMS ((void));
109#ifndef I386COFF
110static void s_bss PARAMS ((int));
252b5132
RH		 111#endif
112
a847613f 113static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 114
252b5132 115/* 'md_assemble ()' gathers together information and puts it into a
47926f60 116 i386_insn. */
252b5132 117
520dc8e8
AM		 118union i386_op
119 {
120 expressionS *disps;
121 expressionS *imms;
122 const reg_entry *regs;
123 };
124
252b5132
RH		 125struct _i386_insn
126 {
47926f60 127 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 128 template tm;
129
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
132 char suffix;
133
47926f60 134 /* OPERANDS gives the number of given operands. */
252b5132
RH		 135 unsigned int operands;
136
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
47926f60 139 operands. */
252b5132
RH		 140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
141
142 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 143 use OP[i] for the corresponding operand. */
252b5132
RH		 144 unsigned int types[MAX_OPERANDS];
145
520dc8e8
AM		 146 /* Displacement expression, immediate expression, or register for each
147 operand. */
148 union i386_op op[MAX_OPERANDS];
252b5132 149
3e73aa7c
JH		 150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152#define Operand_PCrel 1
153
252b5132 154 /* Relocation type for operand */
f3c180ae 155 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 156
252b5132
RH		 157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
162
163 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 164 explicit segment overrides are given. */
ce8a8b2f 165 const seg_entry *seg[2];
252b5132
RH		 166
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
171
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
174
175 modrm_byte rm;
3e73aa7c 176 rex_byte rex;
252b5132
RH		 177 sib_byte sib;
178 };
179
180typedef struct _i386_insn i386_insn;
181
182/* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
184#ifdef LEX_AT
200dbde8 185const char extra_symbol_chars[] = "*%-(@[";
252b5132 186#else
200dbde8 187const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 188#endif
189
29b0f896
AM		 190#if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
252b5132 195/* This array holds the chars that always start a comment. If the
ce8a8b2f 196 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 197const char comment_chars[] = "#/";
198#define PREFIX_SEPARATOR '\\'
252b5132
RH		 199
200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
252b5132 208const char line_comment_chars[] = "";
29b0f896 209
252b5132 210#else
29b0f896
AM		 211/* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213const char comment_chars[] = "#";
214#define PREFIX_SEPARATOR '/'
215
252b5132
RH		 216const char line_comment_chars[] = "/";
217#endif
218
63a0b638 219const char line_separator_chars[] = ";";
252b5132 220
ce8a8b2f
AM		 221/* Chars that can be used to separate mant from exp in floating point
222 nums. */
252b5132
RH		 223const char EXP_CHARS[] = "eE";
224
ce8a8b2f
AM		 225/* Chars that mean this number is a floating point constant
226 As in 0f12.456
227 or 0d1.2345e12. */
252b5132
RH		 228const char FLT_CHARS[] = "fFdDxX";
229
ce8a8b2f 230/* Tables for lexical analysis. */
252b5132
RH		 231static char mnemonic_chars[256];
232static char register_chars[256];
233static char operand_chars[256];
234static char identifier_chars[256];
235static char digit_chars[256];
236
ce8a8b2f 237/* Lexical macros. */
252b5132
RH		 238#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239#define is_operand_char(x) (operand_chars[(unsigned char) x])
240#define is_register_char(x) (register_chars[(unsigned char) x])
241#define is_space_char(x) ((x) == ' ')
242#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243#define is_digit_char(x) (digit_chars[(unsigned char) x])
244
ce8a8b2f 245/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 246static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
247
248/* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
47926f60 251 assembler instruction). */
252b5132 252static char save_stack[32];
ce8a8b2f 253static char *save_stack_p;
252b5132
RH		 254#define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256#define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
258
47926f60 259/* The instruction we're assembling. */
252b5132
RH		 260static i386_insn i;
261
262/* Possible templates for current insn. */
263static const templates *current_templates;
264
47926f60 265/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 266static expressionS disp_expressions[2], im_expressions[2];
267
47926f60
KH		 268/* Current operand we are working on. */
269static int this_operand;
252b5132 270
3e73aa7c
JH		 271/* We support four different modes. FLAG_CODE variable is used to distinguish
272 these. */
273
274enum flag_code {
275 CODE_32BIT,
276 CODE_16BIT,
277 CODE_64BIT };
f3c180ae 278#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 279
280static enum flag_code flag_code;
281static int use_rela_relocations = 0;
282
283/* The names used to print error messages. */
b77a7acd 284static const char *flag_code_names[] =
3e73aa7c
JH		 285 {
286 "32",
287 "16",
288 "64"
289 };
252b5132 290
47926f60
KH		 291/* 1 for intel syntax,
292 0 if att syntax. */
293static int intel_syntax = 0;
252b5132 294
47926f60
KH		 295/* 1 if register prefix % not required. */
296static int allow_naked_reg = 0;
252b5132 297
47926f60
KH		 298/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301static char stackop_size = '\0';
eecb386c 302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
fddf5b5b
AM		 312/* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314static unsigned int no_cond_jump_promotion = 0;
315
29b0f896
AM		 316/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
317symbolS *GOT_symbol;
318
252b5132 319/* Interface to relax_segment.
fddf5b5b
AM		 320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
252b5132 323
47926f60 324/* Types. */
93c2a809
AM		 325#define UNCOND_JUMP 0
326#define COND_JUMP 1
327#define COND_JUMP86 2
fddf5b5b 328
47926f60 329/* Sizes. */
252b5132
RH		 330#define CODE16 1
331#define SMALL 0
29b0f896 332#define SMALL16 (SMALL | CODE16)
252b5132 333#define BIG 2
29b0f896 334#define BIG16 (BIG | CODE16)
252b5132
RH		 335
336#ifndef INLINE
337#ifdef __GNUC__
338#define INLINE __inline__
339#else
340#define INLINE
341#endif
342#endif
343
fddf5b5b
AM		 344#define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346#define TYPE_FROM_RELAX_STATE(s) \
347 ((s) >> 2)
348#define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 350
351/* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
358
359const relax_typeS md_relax_table[] =
360{
24eab124
AM		 361 /* The fields are:
362 1) most positive reach of this state,
363 2) most negative reach of this state,
93c2a809 364 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 365 4) which index into the table to try if we can't fit into this one. */
252b5132 366
fddf5b5b 367 /* UNCOND_JUMP states. */
93c2a809
AM		 368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
252b5132 372 {0, 0, 4, 0},
93c2a809
AM		 373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 375 {0, 0, 2, 0},
376
93c2a809
AM		 377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
382 {0, 0, 5, 0},
fddf5b5b 383 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 384 1 extra opcode byte, 2 displacement bytes. */
385 {0, 0, 3, 0},
386
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
395 {0, 0, 4, 0}
252b5132
RH		 396};
397
e413e4e9
AM		 398static const arch_entry cpu_arch[] = {
399 {"i8086", Cpu086 },
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 412 {NULL, 0 }
413};
414
29b0f896
AM		 415const pseudo_typeS md_pseudo_table[] =
416{
417#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
419#else
420 {"align", s_align_ptwo, 0},
421#endif
422 {"arch", set_cpu_arch, 0},
423#ifndef I386COFF
424 {"bss", s_bss, 0},
425#endif
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
429 {"value", cons, 2},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
438 {"file", dwarf2_directive_file, 0},
439 {"loc", dwarf2_directive_loc, 0},
440 {0, 0, 0}
441};
442
443/* For interface with expression (). */
444extern char *input_line_pointer;
445
446/* Hash table for instruction mnemonic lookup. */
447static struct hash_control *op_hash;
448
449/* Hash table for register lookup. */
450static struct hash_control *reg_hash;
451\f
252b5132
RH		 452void
453i386_align_code (fragP, count)
454 fragS *fragP;
455 int count;
456{
ce8a8b2f
AM		 457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
252b5132
RH		 460 static const char f32_1[] =
461 {0x90}; /* nop */
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
469 {0x90, /* nop */
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
476 {0x90, /* nop */
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
504 {0x90, /* nop */
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
518 };
519 static const char *const f16_patt[] = {
c3332e24 520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
522 };
523
3e73aa7c
JH		 524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code == CODE_64BIT)
527 count = 1;
528
252b5132
RH		 529 if (count > 0 && count <= 15)
530 {
3e73aa7c 531 if (flag_code == CODE_16BIT)
252b5132 532 {
47926f60
KH		 533 memcpy (fragP->fr_literal + fragP->fr_fix,
534 f16_patt[count - 1], count);
535 if (count > 8)
536 /* Adjust jump offset. */
252b5132
RH		 537 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
538 }
539 else
47926f60
KH		 540 memcpy (fragP->fr_literal + fragP->fr_fix,
541 f32_patt[count - 1], count);
252b5132
RH		 542 fragP->fr_var = count;
543 }
544}
545
252b5132
RH		 546static INLINE unsigned int
547mode_from_disp_size (t)
548 unsigned int t;
549{
3e73aa7c 550 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 551}
552
553static INLINE int
554fits_in_signed_byte (num)
847f7ad4 555 offsetT num;
252b5132
RH		 556{
557 return (num >= -128) && (num <= 127);
47926f60 558}
252b5132
RH		 559
560static INLINE int
561fits_in_unsigned_byte (num)
847f7ad4 562 offsetT num;
252b5132
RH		 563{
564 return (num & 0xff) == num;
47926f60 565}
252b5132
RH		 566
567static INLINE int
568fits_in_unsigned_word (num)
847f7ad4 569 offsetT num;
252b5132
RH		 570{
571 return (num & 0xffff) == num;
47926f60 572}
252b5132
RH		 573
574static INLINE int
575fits_in_signed_word (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (-32768 <= num) && (num <= 32767);
47926f60 579}
3e73aa7c
JH		 580static INLINE int
581fits_in_signed_long (num)
582 offsetT num ATTRIBUTE_UNUSED;
583{
584#ifndef BFD64
585 return 1;
586#else
587 return (!(((offsetT) -1 << 31) & num)
588 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
589#endif
590} /* fits_in_signed_long() */
591static INLINE int
592fits_in_unsigned_long (num)
593 offsetT num ATTRIBUTE_UNUSED;
594{
595#ifndef BFD64
596 return 1;
597#else
598 return (num & (((offsetT) 2 << 31) - 1)) == num;
599#endif
600} /* fits_in_unsigned_long() */
252b5132
RH		 601
602static int
603smallest_imm_type (num)
847f7ad4 604 offsetT num;
252b5132 605{
a847613f 606 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 607 {
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
612 use that form. */
613 if (num == 1)
3e73aa7c 614 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 615 }
252b5132 616 return (fits_in_signed_byte (num)
3e73aa7c 617 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 618 : fits_in_unsigned_byte (num)
3e73aa7c 619 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 620 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 621 ? (Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_signed_long (num)
623 ? (Imm32 | Imm32S | Imm64)
624 : fits_in_unsigned_long (num)
625 ? (Imm32 | Imm64)
626 : Imm64);
47926f60 627}
252b5132 628
847f7ad4
AM		 629static offsetT
630offset_in_range (val, size)
631 offsetT val;
632 int size;
633{
508866be 634 addressT mask;
ba2adb93 635
847f7ad4
AM		 636 switch (size)
637 {
508866be
L		 638 case 1: mask = ((addressT) 1 << 8) - 1; break;
639 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 640 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 641#ifdef BFD64
642 case 8: mask = ((addressT) 2 << 63) - 1; break;
643#endif
47926f60 644 default: abort ();
847f7ad4
AM		 645 }
646
ba2adb93 647 /* If BFD64, sign extend val. */
3e73aa7c
JH		 648 if (!use_rela_relocations)
649 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
650 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 651
47926f60 652 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 653 {
654 char buf1[40], buf2[40];
655
656 sprint_value (buf1, val);
657 sprint_value (buf2, val & mask);
658 as_warn (_("%s shortened to %s"), buf1, buf2);
659 }
660 return val & mask;
661}
662
252b5132
RH		 663/* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
665 added. */
666static int
667add_prefix (prefix)
668 unsigned int prefix;
669{
670 int ret = 1;
671 int q;
672
29b0f896
AM		 673 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
674 && flag_code == CODE_64BIT)
3e73aa7c
JH		 675 q = REX_PREFIX;
676 else
677 switch (prefix)
678 {
679 default:
680 abort ();
681
682 case CS_PREFIX_OPCODE:
683 case DS_PREFIX_OPCODE:
684 case ES_PREFIX_OPCODE:
685 case FS_PREFIX_OPCODE:
686 case GS_PREFIX_OPCODE:
687 case SS_PREFIX_OPCODE:
688 q = SEG_PREFIX;
689 break;
252b5132 690
3e73aa7c
JH		 691 case REPNE_PREFIX_OPCODE:
692 case REPE_PREFIX_OPCODE:
693 ret = 2;
694 /* fall thru */
695 case LOCK_PREFIX_OPCODE:
696 q = LOCKREP_PREFIX;
697 break;
252b5132 698
3e73aa7c
JH		 699 case FWAIT_OPCODE:
700 q = WAIT_PREFIX;
701 break;
252b5132 702
3e73aa7c
JH		 703 case ADDR_PREFIX_OPCODE:
704 q = ADDR_PREFIX;
705 break;
252b5132 706
3e73aa7c
JH		 707 case DATA_PREFIX_OPCODE:
708 q = DATA_PREFIX;
709 break;
710 }
252b5132 711
29b0f896 712 if (i.prefix[q] != 0)
252b5132
RH		 713 {
714 as_bad (_("same type of prefix used twice"));
715 return 0;
716 }
717
718 i.prefixes += 1;
719 i.prefix[q] = prefix;
720 return ret;
721}
722
723static void
3e73aa7c 724set_code_flag (value)
e5cb08ac 725 int value;
eecb386c 726{
3e73aa7c
JH		 727 flag_code = value;
728 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
729 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
731 {
732 as_bad (_("64bit mode not supported on this CPU."));
733 }
734 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
735 {
736 as_bad (_("32bit mode not supported on this CPU."));
737 }
eecb386c
AM		 738 stackop_size = '\0';
739}
740
741static void
3e73aa7c
JH		 742set_16bit_gcc_code_flag (new_code_flag)
743 int new_code_flag;
252b5132 744{
3e73aa7c
JH		 745 flag_code = new_code_flag;
746 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
747 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
748 stackop_size = 'l';
252b5132
RH		 749}
750
751static void
752set_intel_syntax (syntax_flag)
eecb386c 753 int syntax_flag;
252b5132
RH		 754{
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg = 0;
757
758 SKIP_WHITESPACE ();
29b0f896 759 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 760 {
761 char *string = input_line_pointer;
762 int e = get_symbol_end ();
763
47926f60 764 if (strcmp (string, "prefix") == 0)
252b5132 765 ask_naked_reg = 1;
47926f60 766 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 767 ask_naked_reg = -1;
768 else
d0b47220 769 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 770 *input_line_pointer = e;
771 }
772 demand_empty_rest_of_line ();
c3332e24 773
252b5132
RH		 774 intel_syntax = syntax_flag;
775
776 if (ask_naked_reg == 0)
777 {
778#ifdef BFD_ASSEMBLER
779 allow_naked_reg = (intel_syntax
24eab124 780 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 781#else
47926f60
KH		 782 /* Conservative default. */
783 allow_naked_reg = 0;
252b5132
RH		 784#endif
785 }
786 else
787 allow_naked_reg = (ask_naked_reg < 0);
788}
789
e413e4e9
AM		 790static void
791set_cpu_arch (dummy)
47926f60 792 int dummy ATTRIBUTE_UNUSED;
e413e4e9 793{
47926f60 794 SKIP_WHITESPACE ();
e413e4e9 795
29b0f896 796 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 797 {
798 char *string = input_line_pointer;
799 int e = get_symbol_end ();
800 int i;
801
802 for (i = 0; cpu_arch[i].name; i++)
803 {
804 if (strcmp (string, cpu_arch[i].name) == 0)
805 {
806 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 807 cpu_arch_flags = (cpu_arch[i].flags
808 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 809 break;
810 }
811 }
812 if (!cpu_arch[i].name)
813 as_bad (_("no such architecture: `%s'"), string);
814
815 *input_line_pointer = e;
816 }
817 else
818 as_bad (_("missing cpu architecture"));
819
fddf5b5b
AM		 820 no_cond_jump_promotion = 0;
821 if (*input_line_pointer == ','
29b0f896 822 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 823 {
824 char *string = ++input_line_pointer;
825 int e = get_symbol_end ();
826
827 if (strcmp (string, "nojumps") == 0)
828 no_cond_jump_promotion = 1;
829 else if (strcmp (string, "jumps") == 0)
830 ;
831 else
832 as_bad (_("no such architecture modifier: `%s'"), string);
833
834 *input_line_pointer = e;
835 }
836
e413e4e9
AM		 837 demand_empty_rest_of_line ();
838}
839
b9d79e03
JH		 840#ifdef BFD_ASSEMBLER
841unsigned long
842i386_mach ()
843{
844 if (!strcmp (default_arch, "x86_64"))
845 return bfd_mach_x86_64;
846 else if (!strcmp (default_arch, "i386"))
847 return bfd_mach_i386_i386;
848 else
849 as_fatal (_("Unknown architecture"));
850}
851#endif
852\f
252b5132
RH		 853void
854md_begin ()
855{
856 const char *hash_err;
857
47926f60 858 /* Initialize op_hash hash table. */
252b5132
RH		 859 op_hash = hash_new ();
860
861 {
29b0f896
AM		 862 const template *optab;
863 templates *core_optab;
252b5132 864
47926f60
KH		 865 /* Setup for loop. */
866 optab = i386_optab;
252b5132
RH		 867 core_optab = (templates *) xmalloc (sizeof (templates));
868 core_optab->start = optab;
869
870 while (1)
871 {
872 ++optab;
873 if (optab->name == NULL
874 || strcmp (optab->name, (optab - 1)->name) != 0)
875 {
876 /* different name --> ship out current template list;
47926f60 877 add to hash table; & begin anew. */
252b5132
RH		 878 core_optab->end = optab;
879 hash_err = hash_insert (op_hash,
880 (optab - 1)->name,
881 (PTR) core_optab);
882 if (hash_err)
883 {
252b5132
RH		 884 as_fatal (_("Internal Error: Can't hash %s: %s"),
885 (optab - 1)->name,
886 hash_err);
887 }
888 if (optab->name == NULL)
889 break;
890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
892 }
893 }
894 }
895
47926f60 896 /* Initialize reg_hash hash table. */
252b5132
RH		 897 reg_hash = hash_new ();
898 {
29b0f896 899 const reg_entry *regtab;
252b5132
RH		 900
901 for (regtab = i386_regtab;
902 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
903 regtab++)
904 {
905 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
906 if (hash_err)
3e73aa7c
JH		 907 as_fatal (_("Internal Error: Can't hash %s: %s"),
908 regtab->reg_name,
909 hash_err);
252b5132
RH		 910 }
911 }
912
47926f60 913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 914 {
29b0f896
AM		 915 int c;
916 char *p;
252b5132
RH		 917
918 for (c = 0; c < 256; c++)
919 {
3882b010 920 if (ISDIGIT (c))
252b5132
RH		 921 {
922 digit_chars[c] = c;
923 mnemonic_chars[c] = c;
924 register_chars[c] = c;
925 operand_chars[c] = c;
926 }
3882b010 927 else if (ISLOWER (c))
252b5132
RH		 928 {
929 mnemonic_chars[c] = c;
930 register_chars[c] = c;
931 operand_chars[c] = c;
932 }
3882b010 933 else if (ISUPPER (c))
252b5132 934 {
3882b010 935 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 936 register_chars[c] = mnemonic_chars[c];
937 operand_chars[c] = c;
938 }
939
3882b010 940 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 941 identifier_chars[c] = c;
942 else if (c >= 128)
943 {
944 identifier_chars[c] = c;
945 operand_chars[c] = c;
946 }
947 }
948
949#ifdef LEX_AT
950 identifier_chars['@'] = '@';
951#endif
252b5132
RH		 952 digit_chars['-'] = '-';
953 identifier_chars['_'] = '_';
954 identifier_chars['.'] = '.';
955
956 for (p = operand_special_chars; *p != '\0'; p++)
957 operand_chars[(unsigned char) *p] = *p;
958 }
959
960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
962 {
963 record_alignment (text_section, 2);
964 record_alignment (data_section, 2);
965 record_alignment (bss_section, 2);
966 }
967#endif
968}
969
970void
971i386_print_statistics (file)
972 FILE *file;
973{
974 hash_print_statistics (file, "i386 opcode", op_hash);
975 hash_print_statistics (file, "i386 register", reg_hash);
976}
977\f
252b5132
RH		 978#ifdef DEBUG386
979
ce8a8b2f 980/* Debugging routines for md_assemble. */
252b5132
RH		 981static void pi PARAMS ((char *, i386_insn *));
982static void pte PARAMS ((template *));
983static void pt PARAMS ((unsigned int));
984static void pe PARAMS ((expressionS *));
985static void ps PARAMS ((symbolS *));
986
987static void
988pi (line, x)
989 char *line;
990 i386_insn *x;
991{
09f131f2 992 unsigned int i;
252b5132
RH		 993
994 fprintf (stdout, "%s: template ", line);
995 pte (&x->tm);
09f131f2
JH		 996 fprintf (stdout, " address: base %s index %s scale %x\n",
997 x->base_reg ? x->base_reg->reg_name : "none",
998 x->index_reg ? x->index_reg->reg_name : "none",
999 x->log2_scale_factor);
1000 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1001 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1002 fprintf (stdout, " sib: base %x index %x scale %x\n",
1003 x->sib.base, x->sib.index, x->sib.scale);
1004 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1005 (x->rex & REX_MODE64) != 0,
1006 (x->rex & REX_EXTX) != 0,
1007 (x->rex & REX_EXTY) != 0,
1008 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1009 for (i = 0; i < x->operands; i++)
1010 {
1011 fprintf (stdout, " #%d: ", i + 1);
1012 pt (x->types[i]);
1013 fprintf (stdout, "\n");
1014 if (x->types[i]
3f4438ab 1015 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1016 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1017 if (x->types[i] & Imm)
520dc8e8 1018 pe (x->op[i].imms);
252b5132 1019 if (x->types[i] & Disp)
520dc8e8 1020 pe (x->op[i].disps);
252b5132
RH		 1021 }
1022}
1023
1024static void
1025pte (t)
1026 template *t;
1027{
09f131f2 1028 unsigned int i;
252b5132 1029 fprintf (stdout, " %d operands ", t->operands);
47926f60 1030 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1031 if (t->extension_opcode != None)
1032 fprintf (stdout, "ext %x ", t->extension_opcode);
1033 if (t->opcode_modifier & D)
1034 fprintf (stdout, "D");
1035 if (t->opcode_modifier & W)
1036 fprintf (stdout, "W");
1037 fprintf (stdout, "\n");
1038 for (i = 0; i < t->operands; i++)
1039 {
1040 fprintf (stdout, " #%d type ", i + 1);
1041 pt (t->operand_types[i]);
1042 fprintf (stdout, "\n");
1043 }
1044}
1045
1046static void
1047pe (e)
1048 expressionS *e;
1049{
24eab124 1050 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1051 fprintf (stdout, " add_number %ld (%lx)\n",
1052 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1053 if (e->X_add_symbol)
1054 {
1055 fprintf (stdout, " add_symbol ");
1056 ps (e->X_add_symbol);
1057 fprintf (stdout, "\n");
1058 }
1059 if (e->X_op_symbol)
1060 {
1061 fprintf (stdout, " op_symbol ");
1062 ps (e->X_op_symbol);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068ps (s)
1069 symbolS *s;
1070{
1071 fprintf (stdout, "%s type %s%s",
1072 S_GET_NAME (s),
1073 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s)));
1075}
1076
1077struct type_name
1078 {
1079 unsigned int mask;
1080 char *tname;
1081 }
1082
29b0f896 1083static const type_names[] =
252b5132
RH		 1084{
1085 { Reg8, "r8" },
1086 { Reg16, "r16" },
1087 { Reg32, "r32" },
09f131f2 1088 { Reg64, "r64" },
252b5132
RH		 1089 { Imm8, "i8" },
1090 { Imm8S, "i8s" },
1091 { Imm16, "i16" },
1092 { Imm32, "i32" },
09f131f2
JH		 1093 { Imm32S, "i32s" },
1094 { Imm64, "i64" },
252b5132
RH		 1095 { Imm1, "i1" },
1096 { BaseIndex, "BaseIndex" },
1097 { Disp8, "d8" },
1098 { Disp16, "d16" },
1099 { Disp32, "d32" },
09f131f2
JH		 1100 { Disp32S, "d32s" },
1101 { Disp64, "d64" },
252b5132
RH		 1102 { InOutPortReg, "InOutPortReg" },
1103 { ShiftCount, "ShiftCount" },
1104 { Control, "control reg" },
1105 { Test, "test reg" },
1106 { Debug, "debug reg" },
1107 { FloatReg, "FReg" },
1108 { FloatAcc, "FAcc" },
1109 { SReg2, "SReg2" },
1110 { SReg3, "SReg3" },
1111 { Acc, "Acc" },
1112 { JumpAbsolute, "Jump Absolute" },
1113 { RegMMX, "rMMX" },
3f4438ab 1114 { RegXMM, "rXMM" },
252b5132
RH		 1115 { EsSeg, "es" },
1116 { 0, "" }
1117};
1118
1119static void
1120pt (t)
1121 unsigned int t;
1122{
29b0f896 1123 const struct type_name *ty;
252b5132 1124
09f131f2
JH		 1125 for (ty = type_names; ty->mask; ty++)
1126 if (t & ty->mask)
1127 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1128 fflush (stdout);
1129}
1130
1131#endif /* DEBUG386 */
1132\f
1133int
1134tc_i386_force_relocation (fixp)
1135 struct fix *fixp;
1136{
1137#ifdef BFD_ASSEMBLER
1138 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1139 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1140 return 1;
1141 return 0;
1142#else
ce8a8b2f 1143 /* For COFF. */
f6af82bd 1144 return fixp->fx_r_type == 7;
252b5132
RH		 1145#endif
1146}
1147
1148#ifdef BFD_ASSEMBLER
29b0f896
AM		 1149static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1151
1152static bfd_reloc_code_real_type
3e73aa7c 1153reloc (size, pcrel, sign, other)
252b5132
RH		 1154 int size;
1155 int pcrel;
3e73aa7c 1156 int sign;
252b5132
RH		 1157 bfd_reloc_code_real_type other;
1158{
47926f60
KH		 1159 if (other != NO_RELOC)
1160 return other;
252b5132
RH		 1161
1162 if (pcrel)
1163 {
3e73aa7c 1164 if (!sign)
e5cb08ac 1165 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1166 switch (size)
1167 {
1168 case 1: return BFD_RELOC_8_PCREL;
1169 case 2: return BFD_RELOC_16_PCREL;
1170 case 4: return BFD_RELOC_32_PCREL;
1171 }
d0b47220 1172 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1173 }
1174 else
1175 {
3e73aa7c 1176 if (sign)
e5cb08ac 1177 switch (size)
3e73aa7c
JH		 1178 {
1179 case 4: return BFD_RELOC_X86_64_32S;
1180 }
1181 else
1182 switch (size)
1183 {
1184 case 1: return BFD_RELOC_8;
1185 case 2: return BFD_RELOC_16;
1186 case 4: return BFD_RELOC_32;
1187 case 8: return BFD_RELOC_64;
1188 }
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign ? "signed" : "unsigned", size);
252b5132
RH		 1191 }
1192
bfb32b52 1193 abort ();
252b5132
RH		 1194 return BFD_RELOC_NONE;
1195}
1196
47926f60
KH		 1197/* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1201
252b5132 1202int
c0c949c7 1203tc_i386_fix_adjustable (fixP)
47926f60 1204 fixS *fixP;
252b5132 1205{
6d249963 1206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
b98ef147 1209 if (S_IS_EXTERNAL (fixP->fx_addsy)
3bf057fa
AS		 1210 || S_IS_WEAK (fixP->fx_addsy)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1212 mode. */
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1215 && fixP->fx_pcrel))
252b5132
RH		 1216 return 0;
1217#endif
ce8a8b2f 1218 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1219 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1220 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1221 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1228 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1230 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1231 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1232 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1233 return 0;
1234 return 1;
1235}
1236#else
ec56dfb4
L		 1237#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1238#define BFD_RELOC_16 0
1239#define BFD_RELOC_32 0
1240#define BFD_RELOC_16_PCREL 0
1241#define BFD_RELOC_32_PCREL 0
1242#define BFD_RELOC_386_PLT32 0
1243#define BFD_RELOC_386_GOT32 0
1244#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1245#define BFD_RELOC_386_TLS_GD 0
1246#define BFD_RELOC_386_TLS_LDM 0
1247#define BFD_RELOC_386_TLS_LDO_32 0
1248#define BFD_RELOC_386_TLS_IE_32 0
1249#define BFD_RELOC_386_TLS_LE_32 0
1250#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1251#define BFD_RELOC_X86_64_PLT32 0
1252#define BFD_RELOC_X86_64_GOT32 0
1253#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1254#endif
1255
29b0f896 1256static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1257
1258static int
252b5132 1259intel_float_operand (mnemonic)
29b0f896 1260 const char *mnemonic;
252b5132 1261{
47926f60 1262 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1263 return 2;
252b5132
RH		 1264
1265 if (mnemonic[0] == 'f')
1266 return 1;
1267
1268 return 0;
1269}
1270
1271/* This is the guts of the machine-dependent assembler. LINE points to a
1272 machine dependent instruction. This function is supposed to emit
1273 the frags/bytes it assembles to. */
1274
1275void
1276md_assemble (line)
1277 char *line;
1278{
252b5132 1279 int j;
252b5132
RH		 1280 char mnemonic[MAX_MNEM_SIZE];
1281
47926f60 1282 /* Initialize globals. */
252b5132
RH		 1283 memset (&i, '\0', sizeof (i));
1284 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1285 i.reloc[j] = NO_RELOC;
252b5132
RH		 1286 memset (disp_expressions, '\0', sizeof (disp_expressions));
1287 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1288 save_stack_p = save_stack;
252b5132
RH		 1289
1290 /* First parse an instruction mnemonic & call i386_operand for the operands.
1291 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1292 start of a (possibly prefixed) mnemonic. */
252b5132 1293
29b0f896
AM		 1294 line = parse_insn (line, mnemonic);
1295 if (line == NULL)
1296 return;
252b5132 1297
29b0f896
AM		 1298 line = parse_operands (line, mnemonic);
1299 if (line == NULL)
1300 return;
252b5132 1301
29b0f896
AM		 1302 /* Now we've parsed the mnemonic into a set of templates, and have the
1303 operands at hand. */
1304
1305 /* All intel opcodes have reversed operands except for "bound" and
1306 "enter". We also don't reverse intersegment "jmp" and "call"
1307 instructions with 2 immediate operands so that the immediate segment
1308 precedes the offset, as it does when in AT&T mode. "enter" and the
1309 intersegment "jmp" and "call" instructions are the only ones that
1310 have two immediate operands. */
1311 if (intel_syntax && i.operands > 1
1312 && (strcmp (mnemonic, "bound") != 0)
1313 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1314 swap_operands ();
1315
1316 if (i.imm_operands)
1317 optimize_imm ();
1318
1319 if (i.disp_operands)
1320 optimize_disp ();
1321
1322 /* Next, we find a template that matches the given insn,
1323 making sure the overlap of the given operands types is consistent
1324 with the template operand types. */
252b5132 1325
29b0f896
AM		 1326 if (!match_template ())
1327 return;
252b5132 1328
29b0f896
AM		 1329 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1330 if (SYSV386_COMPAT
1331 && intel_syntax
1332 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1333 i.tm.base_opcode ^= FloatR;
24eab124 1334
29b0f896
AM		 1335 if (i.tm.opcode_modifier & FWait)
1336 if (!add_prefix (FWAIT_OPCODE))
1337 return;
252b5132 1338
29b0f896
AM		 1339 /* Check string instruction segment overrides. */
1340 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1341 {
1342 if (!check_string ())
5dd0794d 1343 return;
29b0f896 1344 }
5dd0794d 1345
29b0f896
AM		 1346 if (!process_suffix ())
1347 return;
e413e4e9 1348
29b0f896
AM		 1349 /* Make still unresolved immediate matches conform to size of immediate
1350 given in i.suffix. */
1351 if (!finalize_imm ())
1352 return;
252b5132 1353
29b0f896
AM		 1354 if (i.types[0] & Imm1)
1355 i.imm_operands = 0; /* kludge for shift insns. */
1356 if (i.types[0] & ImplicitRegister)
1357 i.reg_operands--;
1358 if (i.types[1] & ImplicitRegister)
1359 i.reg_operands--;
1360 if (i.types[2] & ImplicitRegister)
1361 i.reg_operands--;
252b5132 1362
29b0f896
AM		 1363 if (i.tm.opcode_modifier & ImmExt)
1364 {
1365 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1366 opcode suffix which is coded in the same place as an 8-bit
1367 immediate field would be. Here we fake an 8-bit immediate
1368 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1369
29b0f896 1370 expressionS *exp;
252b5132 1371
29b0f896 1372 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1373
29b0f896
AM		 1374 exp = &im_expressions[i.imm_operands++];
1375 i.op[i.operands].imms = exp;
1376 i.types[i.operands++] = Imm8;
1377 exp->X_op = O_constant;
1378 exp->X_add_number = i.tm.extension_opcode;
1379 i.tm.extension_opcode = None;
1380 }
252b5132 1381
29b0f896
AM		 1382 /* For insns with operands there are more diddles to do to the opcode. */
1383 if (i.operands)
1384 {
1385 if (!process_operands ())
1386 return;
1387 }
1388 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1389 {
1390 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1391 as_warn (_("translating to `%sp'"), i.tm.name);
1392 }
252b5132 1393
29b0f896
AM		 1394 /* Handle conversion of 'int $3' --> special int3 insn. */
1395 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1396 {
1397 i.tm.base_opcode = INT3_OPCODE;
1398 i.imm_operands = 0;
1399 }
252b5132 1400
29b0f896
AM		 1401 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1402 && i.op[0].disps->X_op == O_constant)
1403 {
1404 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1405 the absolute address given by the constant. Since ix86 jumps and
1406 calls are pc relative, we need to generate a reloc. */
1407 i.op[0].disps->X_add_symbol = &abs_symbol;
1408 i.op[0].disps->X_op = O_symbol;
1409 }
252b5132 1410
29b0f896
AM		 1411 if ((i.tm.opcode_modifier & Rex64) != 0)
1412 i.rex |= REX_MODE64;
252b5132 1413
29b0f896
AM		 1414 /* For 8 bit registers we need an empty rex prefix. Also if the
1415 instruction already has a prefix, we need to convert old
1416 registers to new ones. */
773f551c 1417
29b0f896
AM		 1418 if (((i.types[0] & Reg8) != 0
1419 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1420 || ((i.types[1] & Reg8) != 0
1421 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1422 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1423 && i.rex != 0))
1424 {
1425 int x;
726c5dcd 1426
29b0f896
AM		 1427 i.rex |= REX_OPCODE;
1428 for (x = 0; x < 2; x++)
1429 {
1430 /* Look for 8 bit operand that uses old registers. */
1431 if ((i.types[x] & Reg8) != 0
1432 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1433 {
29b0f896
AM		 1434 /* In case it is "hi" register, give up. */
1435 if (i.op[x].regs->reg_num > 3)
1436 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1437 i.op[x].regs->reg_name);
773f551c 1438
29b0f896
AM		 1439 /* Otherwise it is equivalent to the extended register.
1440 Since the encoding doesn't change this is merely
1441 cosmetic cleanup for debug output. */
1442
1443 i.op[x].regs = i.op[x].regs + 8;
773f551c 1444 }
29b0f896
AM		 1445 }
1446 }
773f551c 1447
29b0f896
AM		 1448 if (i.rex != 0)
1449 add_prefix (REX_OPCODE | i.rex);
1450
1451 /* We are ready to output the insn. */
1452 output_insn ();
1453}
1454
1455static char *
1456parse_insn (line, mnemonic)
1457 char *line;
1458 char *mnemonic;
1459{
1460 char *l = line;
1461 char *token_start = l;
1462 char *mnem_p;
1463
1464 /* Non-zero if we found a prefix only acceptable with string insns. */
1465 const char *expecting_string_instruction = NULL;
45288df1 1466
29b0f896
AM		 1467 while (1)
1468 {
1469 mnem_p = mnemonic;
1470 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1471 {
1472 mnem_p++;
1473 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1474 {
29b0f896
AM		 1475 as_bad (_("no such instruction: `%s'"), token_start);
1476 return NULL;
1477 }
1478 l++;
1479 }
1480 if (!is_space_char (*l)
1481 && *l != END_OF_INSN
1482 && *l != PREFIX_SEPARATOR
1483 && *l != ',')
1484 {
1485 as_bad (_("invalid character %s in mnemonic"),
1486 output_invalid (*l));
1487 return NULL;
1488 }
1489 if (token_start == l)
1490 {
1491 if (*l == PREFIX_SEPARATOR)
1492 as_bad (_("expecting prefix; got nothing"));
1493 else
1494 as_bad (_("expecting mnemonic; got nothing"));
1495 return NULL;
1496 }
45288df1 1497
29b0f896
AM		 1498 /* Look up instruction (or prefix) via hash table. */
1499 current_templates = hash_find (op_hash, mnemonic);
47926f60 1500
29b0f896
AM		 1501 if (*l != END_OF_INSN
1502 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1503 && current_templates
1504 && (current_templates->start->opcode_modifier & IsPrefix))
1505 {
1506 /* If we are in 16-bit mode, do not allow addr16 or data16.
1507 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1508 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1509 && flag_code != CODE_64BIT
1510 && (((current_templates->start->opcode_modifier & Size32) != 0)
1511 ^ (flag_code == CODE_16BIT)))
1512 {
1513 as_bad (_("redundant %s prefix"),
1514 current_templates->start->name);
1515 return NULL;
45288df1 1516 }
29b0f896
AM		 1517 /* Add prefix, checking for repeated prefixes. */
1518 switch (add_prefix (current_templates->start->base_opcode))
1519 {
1520 case 0:
1521 return NULL;
1522 case 2:
1523 expecting_string_instruction = current_templates->start->name;
1524 break;
1525 }
1526 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1527 token_start = ++l;
1528 }
1529 else
1530 break;
1531 }
45288df1 1532
29b0f896
AM		 1533 if (!current_templates)
1534 {
1535 /* See if we can get a match by trimming off a suffix. */
1536 switch (mnem_p[-1])
1537 {
1538 case WORD_MNEM_SUFFIX:
1539 case BYTE_MNEM_SUFFIX:
1540 case QWORD_MNEM_SUFFIX:
1541 i.suffix = mnem_p[-1];
1542 mnem_p[-1] = '\0';
1543 current_templates = hash_find (op_hash, mnemonic);
1544 break;
1545 case SHORT_MNEM_SUFFIX:
1546 case LONG_MNEM_SUFFIX:
1547 if (!intel_syntax)
1548 {
1549 i.suffix = mnem_p[-1];
1550 mnem_p[-1] = '\0';
1551 current_templates = hash_find (op_hash, mnemonic);
1552 }
1553 break;
252b5132 1554
29b0f896
AM		 1555 /* Intel Syntax. */
1556 case 'd':
1557 if (intel_syntax)
1558 {
1559 if (intel_float_operand (mnemonic))
1560 i.suffix = SHORT_MNEM_SUFFIX;
1561 else
1562 i.suffix = LONG_MNEM_SUFFIX;
1563 mnem_p[-1] = '\0';
1564 current_templates = hash_find (op_hash, mnemonic);
1565 }
1566 break;
1567 }
1568 if (!current_templates)
1569 {
1570 as_bad (_("no such instruction: `%s'"), token_start);
1571 return NULL;
1572 }
1573 }
252b5132 1574
29b0f896
AM		 1575 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1576 {
1577 /* Check for a branch hint. We allow ",pt" and ",pn" for
1578 predict taken and predict not taken respectively.
1579 I'm not sure that branch hints actually do anything on loop
1580 and jcxz insns (JumpByte) for current Pentium4 chips. They
1581 may work in the future and it doesn't hurt to accept them
1582 now. */
1583 if (l[0] == ',' && l[1] == 'p')
1584 {
1585 if (l[2] == 't')
1586 {
1587 if (!add_prefix (DS_PREFIX_OPCODE))
1588 return NULL;
1589 l += 3;
1590 }
1591 else if (l[2] == 'n')
1592 {
1593 if (!add_prefix (CS_PREFIX_OPCODE))
1594 return NULL;
1595 l += 3;
1596 }
1597 }
1598 }
1599 /* Any other comma loses. */
1600 if (*l == ',')
1601 {
1602 as_bad (_("invalid character %s in mnemonic"),
1603 output_invalid (*l));
1604 return NULL;
1605 }
252b5132 1606
29b0f896
AM		 1607 /* Check if instruction is supported on specified architecture. */
1608 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1609 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1610 {
1611 as_warn (_("`%s' is not supported on `%s'"),
1612 current_templates->start->name, cpu_arch_name);
1613 }
1614 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1615 {
1616 as_warn (_("use .code16 to ensure correct addressing mode"));
1617 }
252b5132 1618
29b0f896
AM		 1619 /* Check for rep/repne without a string instruction. */
1620 if (expecting_string_instruction
1621 && !(current_templates->start->opcode_modifier & IsString))
1622 {
1623 as_bad (_("expecting string instruction after `%s'"),
1624 expecting_string_instruction);
1625 return NULL;
1626 }
252b5132 1627
29b0f896
AM		 1628 return l;
1629}
252b5132 1630
29b0f896
AM		 1631static char *
1632parse_operands (l, mnemonic)
1633 char *l;
1634 const char *mnemonic;
1635{
1636 char *token_start;
3138f287 1637
29b0f896
AM		 1638 /* 1 if operand is pending after ','. */
1639 unsigned int expecting_operand = 0;
252b5132 1640
29b0f896
AM		 1641 /* Non-zero if operand parens not balanced. */
1642 unsigned int paren_not_balanced;
1643
1644 while (*l != END_OF_INSN)
1645 {
1646 /* Skip optional white space before operand. */
1647 if (is_space_char (*l))
1648 ++l;
1649 if (!is_operand_char (*l) && *l != END_OF_INSN)
1650 {
1651 as_bad (_("invalid character %s before operand %d"),
1652 output_invalid (*l),
1653 i.operands + 1);
1654 return NULL;
1655 }
1656 token_start = l; /* after white space */
1657 paren_not_balanced = 0;
1658 while (paren_not_balanced || *l != ',')
1659 {
1660 if (*l == END_OF_INSN)
1661 {
1662 if (paren_not_balanced)
1663 {
1664 if (!intel_syntax)
1665 as_bad (_("unbalanced parenthesis in operand %d."),
1666 i.operands + 1);
1667 else
1668 as_bad (_("unbalanced brackets in operand %d."),
1669 i.operands + 1);
1670 return NULL;
1671 }
1672 else
1673 break; /* we are done */
1674 }
1675 else if (!is_operand_char (*l) && !is_space_char (*l))
1676 {
1677 as_bad (_("invalid character %s in operand %d"),
1678 output_invalid (*l),
1679 i.operands + 1);
1680 return NULL;
1681 }
1682 if (!intel_syntax)
1683 {
1684 if (*l == '(')
1685 ++paren_not_balanced;
1686 if (*l == ')')
1687 --paren_not_balanced;
1688 }
1689 else
1690 {
1691 if (*l == '[')
1692 ++paren_not_balanced;
1693 if (*l == ']')
1694 --paren_not_balanced;
1695 }
1696 l++;
1697 }
1698 if (l != token_start)
1699 { /* Yes, we've read in another operand. */
1700 unsigned int operand_ok;
1701 this_operand = i.operands++;
1702 if (i.operands > MAX_OPERANDS)
1703 {
1704 as_bad (_("spurious operands; (%d operands/instruction max)"),
1705 MAX_OPERANDS);
1706 return NULL;
1707 }
1708 /* Now parse operand adding info to 'i' as we go along. */
1709 END_STRING_AND_SAVE (l);
1710
1711 if (intel_syntax)
1712 operand_ok =
1713 i386_intel_operand (token_start,
1714 intel_float_operand (mnemonic));
1715 else
1716 operand_ok = i386_operand (token_start);
1717
1718 RESTORE_END_STRING (l);
1719 if (!operand_ok)
1720 return NULL;
1721 }
1722 else
1723 {
1724 if (expecting_operand)
1725 {
1726 expecting_operand_after_comma:
1727 as_bad (_("expecting operand after ','; got nothing"));
1728 return NULL;
1729 }
1730 if (*l == ',')
1731 {
1732 as_bad (_("expecting operand before ','; got nothing"));
1733 return NULL;
1734 }
1735 }
7f3f1ea2 1736
29b0f896
AM		 1737 /* Now *l must be either ',' or END_OF_INSN. */
1738 if (*l == ',')
1739 {
1740 if (*++l == END_OF_INSN)
1741 {
1742 /* Just skip it, if it's \n complain. */
1743 goto expecting_operand_after_comma;
1744 }
1745 expecting_operand = 1;
1746 }
1747 }
1748 return l;
1749}
7f3f1ea2 1750
29b0f896
AM		 1751static void
1752swap_operands ()
1753{
1754 union i386_op temp_op;
1755 unsigned int temp_type;
1756 RELOC_ENUM temp_reloc;
1757 int xchg1 = 0;
1758 int xchg2 = 0;
252b5132 1759
29b0f896
AM		 1760 if (i.operands == 2)
1761 {
1762 xchg1 = 0;
1763 xchg2 = 1;
1764 }
1765 else if (i.operands == 3)
1766 {
1767 xchg1 = 0;
1768 xchg2 = 2;
1769 }
1770 temp_type = i.types[xchg2];
1771 i.types[xchg2] = i.types[xchg1];
1772 i.types[xchg1] = temp_type;
1773 temp_op = i.op[xchg2];
1774 i.op[xchg2] = i.op[xchg1];
1775 i.op[xchg1] = temp_op;
1776 temp_reloc = i.reloc[xchg2];
1777 i.reloc[xchg2] = i.reloc[xchg1];
1778 i.reloc[xchg1] = temp_reloc;
1779
1780 if (i.mem_operands == 2)
1781 {
1782 const seg_entry *temp_seg;
1783 temp_seg = i.seg[0];
1784 i.seg[0] = i.seg[1];
1785 i.seg[1] = temp_seg;
1786 }
1787}
252b5132 1788
29b0f896
AM		 1789/* Try to ensure constant immediates are represented in the smallest
1790 opcode possible. */
1791static void
1792optimize_imm ()
1793{
1794 char guess_suffix = 0;
1795 int op;
252b5132 1796
29b0f896
AM		 1797 if (i.suffix)
1798 guess_suffix = i.suffix;
1799 else if (i.reg_operands)
1800 {
1801 /* Figure out a suffix from the last register operand specified.
1802 We can't do this properly yet, ie. excluding InOutPortReg,
1803 but the following works for instructions with immediates.
1804 In any case, we can't set i.suffix yet. */
1805 for (op = i.operands; --op >= 0;)
1806 if (i.types[op] & Reg)
252b5132 1807 {
29b0f896
AM		 1808 if (i.types[op] & Reg8)
1809 guess_suffix = BYTE_MNEM_SUFFIX;
1810 else if (i.types[op] & Reg16)
1811 guess_suffix = WORD_MNEM_SUFFIX;
1812 else if (i.types[op] & Reg32)
1813 guess_suffix = LONG_MNEM_SUFFIX;
1814 else if (i.types[op] & Reg64)
1815 guess_suffix = QWORD_MNEM_SUFFIX;
1816 break;
252b5132 1817 }
29b0f896
AM		 1818 }
1819 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1820 guess_suffix = WORD_MNEM_SUFFIX;
1821
1822 for (op = i.operands; --op >= 0;)
1823 if (i.types[op] & Imm)
1824 {
1825 switch (i.op[op].imms->X_op)
252b5132 1826 {
29b0f896
AM		 1827 case O_constant:
1828 /* If a suffix is given, this operand may be shortened. */
1829 switch (guess_suffix)
252b5132 1830 {
29b0f896
AM		 1831 case LONG_MNEM_SUFFIX:
1832 i.types[op] |= Imm32 | Imm64;
1833 break;
1834 case WORD_MNEM_SUFFIX:
1835 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1836 break;
1837 case BYTE_MNEM_SUFFIX:
1838 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1839 break;
252b5132 1840 }
252b5132 1841
29b0f896
AM		 1842 /* If this operand is at most 16 bits, convert it
1843 to a signed 16 bit number before trying to see
1844 whether it will fit in an even smaller size.
1845 This allows a 16-bit operand such as $0xffe0 to
1846 be recognised as within Imm8S range. */
1847 if ((i.types[op] & Imm16)
1848 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1849 {
29b0f896
AM		 1850 i.op[op].imms->X_add_number =
1851 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1852 }
1853 if ((i.types[op] & Imm32)
1854 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1855 == 0))
1856 {
1857 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1858 ^ ((offsetT) 1 << 31))
1859 - ((offsetT) 1 << 31));
1860 }
1861 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1862
29b0f896
AM		 1863 /* We must avoid matching of Imm32 templates when 64bit
1864 only immediate is available. */
1865 if (guess_suffix == QWORD_MNEM_SUFFIX)
1866 i.types[op] &= ~Imm32;
1867 break;
252b5132 1868
29b0f896
AM		 1869 case O_absent:
1870 case O_register:
1871 abort ();
1872
1873 /* Symbols and expressions. */
1874 default:
1875 /* Convert symbolic operand to proper sizes for matching. */
1876 switch (guess_suffix)
1877 {
1878 case QWORD_MNEM_SUFFIX:
1879 i.types[op] = Imm64 | Imm32S;
1880 break;
1881 case LONG_MNEM_SUFFIX:
1882 i.types[op] = Imm32 | Imm64;
1883 break;
1884 case WORD_MNEM_SUFFIX:
1885 i.types[op] = Imm16 | Imm32 | Imm64;
1886 break;
1887 break;
1888 case BYTE_MNEM_SUFFIX:
1889 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1890 break;
1891 break;
252b5132 1892 }
29b0f896 1893 break;
252b5132 1894 }
29b0f896
AM		 1895 }
1896}
47926f60 1897
29b0f896
AM		 1898/* Try to use the smallest displacement type too. */
1899static void
1900optimize_disp ()
1901{
1902 int op;
3e73aa7c 1903
29b0f896
AM		 1904 for (op = i.operands; --op >= 0;)
1905 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1906 {
29b0f896
AM		 1907 offsetT disp = i.op[op].disps->X_add_number;
1908
1909 if (i.types[op] & Disp16)
252b5132 1910 {
29b0f896
AM		 1911 /* We know this operand is at most 16 bits, so
1912 convert to a signed 16 bit number before trying
1913 to see whether it will fit in an even smaller
1914 size. */
1915
1916 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1917 }
29b0f896 1918 else if (i.types[op] & Disp32)
252b5132 1919 {
29b0f896
AM		 1920 /* We know this operand is at most 32 bits, so convert to a
1921 signed 32 bit number before trying to see whether it will
1922 fit in an even smaller size. */
1923 disp &= (((offsetT) 2 << 31) - 1);
1924 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1925 }
29b0f896 1926 if (flag_code == CODE_64BIT)
252b5132 1927 {
29b0f896
AM		 1928 if (fits_in_signed_long (disp))
1929 i.types[op] |= Disp32S;
1930 if (fits_in_unsigned_long (disp))
1931 i.types[op] |= Disp32;
252b5132 1932 }
29b0f896
AM		 1933 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1934 && fits_in_signed_byte (disp))
1935 i.types[op] |= Disp8;
252b5132 1936 }
29b0f896
AM		 1937}
1938
1939static int
1940match_template ()
1941{
1942 /* Points to template once we've found it. */
1943 const template *t;
1944 unsigned int overlap0, overlap1, overlap2;
1945 unsigned int found_reverse_match;
1946 int suffix_check;
1947
1948#define MATCH(overlap, given, template) \
1949 ((overlap & ~JumpAbsolute) \
1950 && (((given) & (BaseIndex | JumpAbsolute)) \
1951 == ((overlap) & (BaseIndex | JumpAbsolute))))
1952
1953 /* If given types r0 and r1 are registers they must be of the same type
1954 unless the expected operand type register overlap is null.
1955 Note that Acc in a template matches every size of reg. */
1956#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1957 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1958 || ((g0) & Reg) == ((g1) & Reg) \
1959 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1960
1961 overlap0 = 0;
1962 overlap1 = 0;
1963 overlap2 = 0;
1964 found_reverse_match = 0;
1965 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1966 ? No_bSuf
1967 : (i.suffix == WORD_MNEM_SUFFIX
1968 ? No_wSuf
1969 : (i.suffix == SHORT_MNEM_SUFFIX
1970 ? No_sSuf
1971 : (i.suffix == LONG_MNEM_SUFFIX
1972 ? No_lSuf
1973 : (i.suffix == QWORD_MNEM_SUFFIX
1974 ? No_qSuf
1975 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1976 ? No_xSuf : 0))))));
1977
1978 for (t = current_templates->start;
1979 t < current_templates->end;
1980 t++)
1981 {
1982 /* Must have right number of operands. */
1983 if (i.operands != t->operands)
1984 continue;
1985
1986 /* Check the suffix, except for some instructions in intel mode. */
1987 if ((t->opcode_modifier & suffix_check)
1988 && !(intel_syntax
1989 && (t->opcode_modifier & IgnoreSize))
1990 && !(intel_syntax
1991 && t->base_opcode == 0xd9
1992 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1993 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1994 continue;
1995
1996 /* Do not verify operands when there are none. */
1997 else if (!t->operands)
1998 {
1999 if (t->cpu_flags & ~cpu_arch_flags)
2000 continue;
2001 /* We've found a match; break out of loop. */
2002 break;
2003 }
252b5132 2004
29b0f896
AM		 2005 overlap0 = i.types[0] & t->operand_types[0];
2006 switch (t->operands)
2007 {
2008 case 1:
2009 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2010 continue;
2011 break;
2012 case 2:
2013 case 3:
2014 overlap1 = i.types[1] & t->operand_types[1];
2015 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2016 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2017 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2018 t->operand_types[0],
2019 overlap1, i.types[1],
2020 t->operand_types[1]))
2021 {
2022 /* Check if other direction is valid ... */
2023 if ((t->opcode_modifier & (D | FloatD)) == 0)
2024 continue;
2025
2026 /* Try reversing direction of operands. */
2027 overlap0 = i.types[0] & t->operand_types[1];
2028 overlap1 = i.types[1] & t->operand_types[0];
2029 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2030 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2031 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2032 t->operand_types[1],
2033 overlap1, i.types[1],
2034 t->operand_types[0]))
2035 {
2036 /* Does not match either direction. */
2037 continue;
2038 }
2039 /* found_reverse_match holds which of D or FloatDR
2040 we've found. */
2041 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2042 }
2043 /* Found a forward 2 operand match here. */
2044 else if (t->operands == 3)
2045 {
2046 /* Here we make use of the fact that there are no
2047 reverse match 3 operand instructions, and all 3
2048 operand instructions only need to be checked for
2049 register consistency between operands 2 and 3. */
2050 overlap2 = i.types[2] & t->operand_types[2];
2051 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2052 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2053 t->operand_types[1],
2054 overlap2, i.types[2],
2055 t->operand_types[2]))
2056
2057 continue;
2058 }
2059 /* Found either forward/reverse 2 or 3 operand match here:
2060 slip through to break. */
2061 }
2062 if (t->cpu_flags & ~cpu_arch_flags)
2063 {
2064 found_reverse_match = 0;
2065 continue;
2066 }
2067 /* We've found a match; break out of loop. */
2068 break;
2069 }
2070
2071 if (t == current_templates->end)
2072 {
2073 /* We found no match. */
2074 as_bad (_("suffix or operands invalid for `%s'"),
2075 current_templates->start->name);
2076 return 0;
2077 }
252b5132 2078
29b0f896
AM		 2079 if (!quiet_warnings)
2080 {
2081 if (!intel_syntax
2082 && ((i.types[0] & JumpAbsolute)
2083 != (t->operand_types[0] & JumpAbsolute)))
2084 {
2085 as_warn (_("indirect %s without `*'"), t->name);
2086 }
2087
2088 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2089 == (IsPrefix | IgnoreSize))
2090 {
2091 /* Warn them that a data or address size prefix doesn't
2092 affect assembly of the next line of code. */
2093 as_warn (_("stand-alone `%s' prefix"), t->name);
2094 }
2095 }
2096
2097 /* Copy the template we found. */
2098 i.tm = *t;
2099 if (found_reverse_match)
2100 {
2101 /* If we found a reverse match we must alter the opcode
2102 direction bit. found_reverse_match holds bits to change
2103 (different for int & float insns). */
2104
2105 i.tm.base_opcode ^= found_reverse_match;
2106
2107 i.tm.operand_types[0] = t->operand_types[1];
2108 i.tm.operand_types[1] = t->operand_types[0];
2109 }
2110
2111 return 1;
2112}
2113
2114static int
2115check_string ()
2116{
2117 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2118 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2119 {
2120 if (i.seg[0] != NULL && i.seg[0] != &es)
2121 {
2122 as_bad (_("`%s' operand %d must use `%%es' segment"),
2123 i.tm.name,
2124 mem_op + 1);
2125 return 0;
2126 }
2127 /* There's only ever one segment override allowed per instruction.
2128 This instruction possibly has a legal segment override on the
2129 second operand, so copy the segment to where non-string
2130 instructions store it, allowing common code. */
2131 i.seg[0] = i.seg[1];
2132 }
2133 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2134 {
2135 if (i.seg[1] != NULL && i.seg[1] != &es)
2136 {
2137 as_bad (_("`%s' operand %d must use `%%es' segment"),
2138 i.tm.name,
2139 mem_op + 2);
2140 return 0;
2141 }
2142 }
2143 return 1;
2144}
2145
2146static int
2147process_suffix ()
2148{
2149 /* If matched instruction specifies an explicit instruction mnemonic
2150 suffix, use it. */
2151 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2152 {
2153 if (i.tm.opcode_modifier & Size16)
2154 i.suffix = WORD_MNEM_SUFFIX;
2155 else if (i.tm.opcode_modifier & Size64)
2156 i.suffix = QWORD_MNEM_SUFFIX;
2157 else
2158 i.suffix = LONG_MNEM_SUFFIX;
2159 }
2160 else if (i.reg_operands)
2161 {
2162 /* If there's no instruction mnemonic suffix we try to invent one
2163 based on register operands. */
2164 if (!i.suffix)
2165 {
2166 /* We take i.suffix from the last register operand specified,
2167 Destination register type is more significant than source
2168 register type. */
2169 int op;
2170 for (op = i.operands; --op >= 0;)
2171 if ((i.types[op] & Reg)
2172 && !(i.tm.operand_types[op] & InOutPortReg))
2173 {
2174 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2175 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2176 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2177 LONG_MNEM_SUFFIX);
2178 break;
2179 }
2180 }
2181 else if (i.suffix == BYTE_MNEM_SUFFIX)
2182 {
2183 if (!check_byte_reg ())
2184 return 0;
2185 }
2186 else if (i.suffix == LONG_MNEM_SUFFIX)
2187 {
2188 if (!check_long_reg ())
2189 return 0;
2190 }
2191 else if (i.suffix == QWORD_MNEM_SUFFIX)
2192 {
2193 if (!check_qword_reg ())
2194 return 0;
2195 }
2196 else if (i.suffix == WORD_MNEM_SUFFIX)
2197 {
2198 if (!check_word_reg ())
2199 return 0;
2200 }
2201 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2202 /* Do nothing if the instruction is going to ignore the prefix. */
2203 ;
2204 else
2205 abort ();
2206 }
2207 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2208 {
2209 i.suffix = stackop_size;
2210 }
252b5132 2211
29b0f896
AM		 2212 /* Change the opcode based on the operand size given by i.suffix;
2213 We need not change things for byte insns. */
252b5132 2214
29b0f896
AM		 2215 if (!i.suffix && (i.tm.opcode_modifier & W))
2216 {
2217 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2218 return 0;
2219 }
252b5132 2220
29b0f896
AM		 2221 /* For movzx and movsx, need to check the register type. */
2222 if (intel_syntax
0f3f3d8b
AM		 2223 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
2224 && i.suffix == BYTE_MNEM_SUFFIX)
2225 {
2226 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896 2227
0f3f3d8b
AM		 2228 if ((i.op[1].regs->reg_type & Reg16) != 0)
2229 if (!add_prefix (prefix))
2230 return 0;
2231 }
252b5132 2232
29b0f896
AM		 2233 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2234 {
2235 /* It's not a byte, select word/dword operation. */
2236 if (i.tm.opcode_modifier & W)
2237 {
2238 if (i.tm.opcode_modifier & ShortForm)
2239 i.tm.base_opcode |= 8;
2240 else
2241 i.tm.base_opcode |= 1;
2242 }
0f3f3d8b 2243
29b0f896
AM		 2244 /* Now select between word & dword operations via the operand
2245 size prefix, except for instructions that will ignore this
2246 prefix anyway. */
2247 if (i.suffix != QWORD_MNEM_SUFFIX
2248 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2249 && !(i.tm.opcode_modifier & IgnoreSize))
24eab124
AM		 2250 {
2251 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2252 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2253 prefix = ADDR_PREFIX_OPCODE;
252b5132 2254
29b0f896
AM		 2255 if (!add_prefix (prefix))
2256 return 0;
24eab124 2257 }
252b5132 2258
29b0f896
AM		 2259 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2260 && !(i.tm.opcode_modifier & IgnoreSize)
2261 && (i.tm.opcode_modifier & JumpByte))
2262 {
2263 if (!add_prefix (ADDR_PREFIX_OPCODE))
2264 return 0;
2265 }
252b5132 2266
29b0f896
AM		 2267 /* Set mode64 for an operand. */
2268 if (i.suffix == QWORD_MNEM_SUFFIX
2269 && (i.tm.opcode_modifier & NoRex64) == 0)
2270 {
2271 i.rex |= REX_MODE64;
2272 if (flag_code < CODE_64BIT)
2273 {
2274 as_bad (_("64bit operations available only in 64bit modes."));
2275 return 0;
2276 }
2277 }
3e73aa7c 2278
29b0f896
AM		 2279 /* Size floating point instruction. */
2280 if (i.suffix == LONG_MNEM_SUFFIX)
2281 {
2282 if (i.tm.opcode_modifier & FloatMF)
2283 i.tm.base_opcode ^= 4;
2284 }
2285 }
7ecd2f8b 2286
29b0f896
AM		 2287 return 1;
2288}
3e73aa7c 2289
29b0f896
AM		 2290static int
2291check_byte_reg ()
2292{
2293 int op;
2294 for (op = i.operands; --op >= 0;)
2295 {
2296 /* If this is an eight bit register, it's OK. If it's the 16 or
2297 32 bit version of an eight bit register, we will just use the
2298 low portion, and that's OK too. */
2299 if (i.types[op] & Reg8)
2300 continue;
2301
2302 /* movzx and movsx should not generate this warning. */
2303 if (intel_syntax
2304 && (i.tm.base_opcode == 0xfb7
2305 || i.tm.base_opcode == 0xfb6
2306 || i.tm.base_opcode == 0x63
2307 || i.tm.base_opcode == 0xfbe
2308 || i.tm.base_opcode == 0xfbf))
2309 continue;
2310
2311 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2312#if 0
2313 /* Check that the template allows eight bit regs. This
2314 kills insns such as `orb $1,%edx', which maybe should be
2315 allowed. */
2316 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2317#endif
2318 )
2319 {
2320 /* Prohibit these changes in the 64bit mode, since the
2321 lowering is more complicated. */
2322 if (flag_code == CODE_64BIT
2323 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2324 {
0f3f3d8b 2325 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2326 i.op[op].regs->reg_name,
2327 i.suffix);
2328 return 0;
2329 }
2330#if REGISTER_WARNINGS
2331 if (!quiet_warnings
2332 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2333 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2334 (i.op[op].regs + (i.types[op] & Reg16
2335 ? REGNAM_AL - REGNAM_AX
2336 : REGNAM_AL - REGNAM_EAX))->reg_name,
2337 i.op[op].regs->reg_name,
2338 i.suffix);
2339#endif
2340 continue;
2341 }
2342 /* Any other register is bad. */
2343 if (i.types[op] & (Reg | RegMMX | RegXMM
2344 | SReg2 | SReg3
2345 | Control | Debug | Test
2346 | FloatReg | FloatAcc))
2347 {
2348 as_bad (_("`%%%s' not allowed with `%s%c'"),
2349 i.op[op].regs->reg_name,
2350 i.tm.name,
2351 i.suffix);
2352 return 0;
2353 }
2354 }
2355 return 1;
2356}
2357
2358static int
2359check_long_reg ()
2360{
2361 int op;
2362
2363 for (op = i.operands; --op >= 0;)
2364 /* Reject eight bit registers, except where the template requires
2365 them. (eg. movzb) */
2366 if ((i.types[op] & Reg8) != 0
2367 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2368 {
2369 as_bad (_("`%%%s' not allowed with `%s%c'"),
2370 i.op[op].regs->reg_name,
2371 i.tm.name,
2372 i.suffix);
2373 return 0;
2374 }
2375 /* Warn if the e prefix on a general reg is missing. */
2376 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2377 && (i.types[op] & Reg16) != 0
2378 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2379 {
2380 /* Prohibit these changes in the 64bit mode, since the
2381 lowering is more complicated. */
2382 if (flag_code == CODE_64BIT)
252b5132 2383 {
0f3f3d8b 2384 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2385 i.op[op].regs->reg_name,
2386 i.suffix);
2387 return 0;
252b5132 2388 }
29b0f896
AM		 2389#if REGISTER_WARNINGS
2390 else
2391 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2392 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2393 i.op[op].regs->reg_name,
2394 i.suffix);
2395#endif
252b5132 2396 }
29b0f896
AM		 2397 /* Warn if the r prefix on a general reg is missing. */
2398 else if ((i.types[op] & Reg64) != 0
2399 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2400 {
0f3f3d8b 2401 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2402 i.op[op].regs->reg_name,
2403 i.suffix);
2404 return 0;
2405 }
2406 return 1;
2407}
252b5132 2408
29b0f896
AM		 2409static int
2410check_qword_reg ()
2411{
2412 int op;
252b5132 2413
29b0f896
AM		 2414 for (op = i.operands; --op >= 0; )
2415 /* Reject eight bit registers, except where the template requires
2416 them. (eg. movzb) */
2417 if ((i.types[op] & Reg8) != 0
2418 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2419 {
2420 as_bad (_("`%%%s' not allowed with `%s%c'"),
2421 i.op[op].regs->reg_name,
2422 i.tm.name,
2423 i.suffix);
2424 return 0;
2425 }
2426 /* Warn if the e prefix on a general reg is missing. */
2427 else if (((i.types[op] & Reg16) != 0
2428 || (i.types[op] & Reg32) != 0)
2429 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2430 {
2431 /* Prohibit these changes in the 64bit mode, since the
2432 lowering is more complicated. */
0f3f3d8b 2433 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2434 i.op[op].regs->reg_name,
2435 i.suffix);
2436 return 0;
252b5132 2437 }
29b0f896
AM		 2438 return 1;
2439}
252b5132 2440
29b0f896
AM		 2441static int
2442check_word_reg ()
2443{
2444 int op;
2445 for (op = i.operands; --op >= 0;)
2446 /* Reject eight bit registers, except where the template requires
2447 them. (eg. movzb) */
2448 if ((i.types[op] & Reg8) != 0
2449 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2450 {
2451 as_bad (_("`%%%s' not allowed with `%s%c'"),
2452 i.op[op].regs->reg_name,
2453 i.tm.name,
2454 i.suffix);
2455 return 0;
2456 }
2457 /* Warn if the e prefix on a general reg is present. */
2458 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2459 && (i.types[op] & Reg32) != 0
2460 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2461 {
29b0f896
AM		 2462 /* Prohibit these changes in the 64bit mode, since the
2463 lowering is more complicated. */
2464 if (flag_code == CODE_64BIT)
252b5132 2465 {
0f3f3d8b 2466 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2467 i.op[op].regs->reg_name,
2468 i.suffix);
2469 return 0;
252b5132 2470 }
29b0f896
AM		 2471 else
2472#if REGISTER_WARNINGS
2473 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2474 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2475 i.op[op].regs->reg_name,
2476 i.suffix);
2477#endif
2478 }
2479 return 1;
2480}
252b5132 2481
29b0f896
AM		 2482static int
2483finalize_imm ()
2484{
2485 unsigned int overlap0, overlap1, overlap2;
2486
2487 overlap0 = i.types[0] & i.tm.operand_types[0];
2488 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2489 && overlap0 != Imm8 && overlap0 != Imm8S
2490 && overlap0 != Imm16 && overlap0 != Imm32S
2491 && overlap0 != Imm32 && overlap0 != Imm64)
2492 {
2493 if (i.suffix)
2494 {
2495 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2496 ? Imm8 | Imm8S
2497 : (i.suffix == WORD_MNEM_SUFFIX
2498 ? Imm16
2499 : (i.suffix == QWORD_MNEM_SUFFIX
2500 ? Imm64 | Imm32S
2501 : Imm32)));
2502 }
2503 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2504 || overlap0 == (Imm16 | Imm32)
2505 || overlap0 == (Imm16 | Imm32S))
2506 {
2507 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2508 ? Imm16 : Imm32S);
2509 }
2510 if (overlap0 != Imm8 && overlap0 != Imm8S
2511 && overlap0 != Imm16 && overlap0 != Imm32S
2512 && overlap0 != Imm32 && overlap0 != Imm64)
2513 {
2514 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2515 return 0;
2516 }
2517 }
2518 i.types[0] = overlap0;
2519
2520 overlap1 = i.types[1] & i.tm.operand_types[1];
2521 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2522 && overlap1 != Imm8 && overlap1 != Imm8S
2523 && overlap1 != Imm16 && overlap1 != Imm32S
2524 && overlap1 != Imm32 && overlap1 != Imm64)
2525 {
2526 if (i.suffix)
2527 {
2528 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2529 ? Imm8 | Imm8S
2530 : (i.suffix == WORD_MNEM_SUFFIX
2531 ? Imm16
2532 : (i.suffix == QWORD_MNEM_SUFFIX
2533 ? Imm64 | Imm32S
2534 : Imm32)));
2535 }
2536 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2537 || overlap1 == (Imm16 | Imm32)
2538 || overlap1 == (Imm16 | Imm32S))
2539 {
2540 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2541 ? Imm16 : Imm32S);
2542 }
2543 if (overlap1 != Imm8 && overlap1 != Imm8S
2544 && overlap1 != Imm16 && overlap1 != Imm32S
2545 && overlap1 != Imm32 && overlap1 != Imm64)
2546 {
2547 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2548 return 0;
2549 }
2550 }
2551 i.types[1] = overlap1;
2552
2553 overlap2 = i.types[2] & i.tm.operand_types[2];
2554 assert ((overlap2 & Imm) == 0);
2555 i.types[2] = overlap2;
2556
2557 return 1;
2558}
2559
2560static int
2561process_operands ()
2562{
2563 /* Default segment register this instruction will use for memory
2564 accesses. 0 means unknown. This is only for optimizing out
2565 unnecessary segment overrides. */
2566 const seg_entry *default_seg = 0;
2567
2568 /* The imul $imm, %reg instruction is converted into
2569 imul $imm, %reg, %reg, and the clr %reg instruction
2570 is converted into xor %reg, %reg. */
2571 if (i.tm.opcode_modifier & regKludge)
2572 {
2573 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2574 /* Pretend we saw the extra register operand. */
2575 assert (i.op[first_reg_op + 1].regs == 0);
2576 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2577 i.types[first_reg_op + 1] = i.types[first_reg_op];
2578 i.reg_operands = 2;
2579 }
2580
2581 if (i.tm.opcode_modifier & ShortForm)
2582 {
2583 /* The register or float register operand is in operand 0 or 1. */
2584 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2585 /* Register goes in low 3 bits of opcode. */
2586 i.tm.base_opcode |= i.op[op].regs->reg_num;
2587 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2588 i.rex |= REX_EXTZ;
2589 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2590 {
2591 /* Warn about some common errors, but press on regardless.
2592 The first case can be generated by gcc (<= 2.8.1). */
2593 if (i.operands == 2)
2594 {
2595 /* Reversed arguments on faddp, fsubp, etc. */
2596 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2597 i.op[1].regs->reg_name,
2598 i.op[0].regs->reg_name);
2599 }
2600 else
2601 {
2602 /* Extraneous `l' suffix on fp insn. */
2603 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2604 i.op[0].regs->reg_name);
2605 }
2606 }
2607 }
2608 else if (i.tm.opcode_modifier & Modrm)
2609 {
2610 /* The opcode is completed (modulo i.tm.extension_opcode which
2611 must be put into the modrm byte).
2612 Now, we make the modrm & index base bytes based on all the
2613 info we've collected. */
2614
2615 default_seg = build_modrm_byte ();
2616 }
2617 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2618 {
2619 if (i.tm.base_opcode == POP_SEG_SHORT
2620 && i.op[0].regs->reg_num == 1)
2621 {
2622 as_bad (_("you can't `pop %%cs'"));
2623 return 0;
2624 }
2625 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2626 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2627 i.rex |= REX_EXTZ;
2628 }
2629 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2630 {
2631 default_seg = &ds;
2632 }
2633 else if ((i.tm.opcode_modifier & IsString) != 0)
2634 {
2635 /* For the string instructions that allow a segment override
2636 on one of their operands, the default segment is ds. */
2637 default_seg = &ds;
2638 }
2639
2640 /* If a segment was explicitly specified,
2641 and the specified segment is not the default,
2642 use an opcode prefix to select it.
2643 If we never figured out what the default segment is,
2644 then default_seg will be zero at this point,
2645 and the specified segment prefix will always be used. */
2646 if ((i.seg[0]) && (i.seg[0] != default_seg))
2647 {
2648 if (!add_prefix (i.seg[0]->seg_prefix))
2649 return 0;
2650 }
2651 return 1;
2652}
2653
2654static const seg_entry *
2655build_modrm_byte ()
2656{
2657 const seg_entry *default_seg = 0;
2658
2659 /* i.reg_operands MUST be the number of real register operands;
2660 implicit registers do not count. */
2661 if (i.reg_operands == 2)
2662 {
2663 unsigned int source, dest;
2664 source = ((i.types[0]
2665 & (Reg | RegMMX | RegXMM
2666 | SReg2 | SReg3
2667 | Control | Debug | Test))
2668 ? 0 : 1);
2669 dest = source + 1;
2670
2671 i.rm.mode = 3;
2672 /* One of the register operands will be encoded in the i.tm.reg
2673 field, the other in the combined i.tm.mode and i.tm.regmem
2674 fields. If no form of this instruction supports a memory
2675 destination operand, then we assume the source operand may
2676 sometimes be a memory operand and so we need to store the
2677 destination in the i.rm.reg field. */
2678 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2679 {
2680 i.rm.reg = i.op[dest].regs->reg_num;
2681 i.rm.regmem = i.op[source].regs->reg_num;
2682 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2683 i.rex |= REX_EXTX;
2684 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2685 i.rex |= REX_EXTZ;
2686 }
2687 else
2688 {
2689 i.rm.reg = i.op[source].regs->reg_num;
2690 i.rm.regmem = i.op[dest].regs->reg_num;
2691 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2692 i.rex |= REX_EXTZ;
2693 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2694 i.rex |= REX_EXTX;
2695 }
2696 }
2697 else
2698 { /* If it's not 2 reg operands... */
2699 if (i.mem_operands)
2700 {
2701 unsigned int fake_zero_displacement = 0;
2702 unsigned int op = ((i.types[0] & AnyMem)
2703 ? 0
2704 : (i.types[1] & AnyMem) ? 1 : 2);
2705
2706 default_seg = &ds;
2707
2708 if (i.base_reg == 0)
2709 {
2710 i.rm.mode = 0;
2711 if (!i.disp_operands)
2712 fake_zero_displacement = 1;
2713 if (i.index_reg == 0)
2714 {
2715 /* Operand is just <disp> */
2716 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2717 && (flag_code != CODE_64BIT))
2718 {
2719 i.rm.regmem = NO_BASE_REGISTER_16;
2720 i.types[op] &= ~Disp;
2721 i.types[op] |= Disp16;
2722 }
2723 else if (flag_code != CODE_64BIT
2724 || (i.prefix[ADDR_PREFIX] != 0))
2725 {
2726 i.rm.regmem = NO_BASE_REGISTER;
2727 i.types[op] &= ~Disp;
2728 i.types[op] |= Disp32;
2729 }
2730 else
2731 {
2732 /* 64bit mode overwrites the 32bit absolute
2733 addressing by RIP relative addressing and
2734 absolute addressing is encoded by one of the
2735 redundant SIB forms. */
2736 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2737 i.sib.base = NO_BASE_REGISTER;
2738 i.sib.index = NO_INDEX_REGISTER;
2739 i.types[op] &= ~Disp;
2740 i.types[op] |= Disp32S;
2741 }
2742 }
2743 else /* !i.base_reg && i.index_reg */
2744 {
2745 i.sib.index = i.index_reg->reg_num;
2746 i.sib.base = NO_BASE_REGISTER;
2747 i.sib.scale = i.log2_scale_factor;
2748 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2749 i.types[op] &= ~Disp;
2750 if (flag_code != CODE_64BIT)
2751 i.types[op] |= Disp32; /* Must be 32 bit */
2752 else
2753 i.types[op] |= Disp32S;
2754 if ((i.index_reg->reg_flags & RegRex) != 0)
2755 i.rex |= REX_EXTY;
2756 }
2757 }
2758 /* RIP addressing for 64bit mode. */
2759 else if (i.base_reg->reg_type == BaseIndex)
2760 {
2761 i.rm.regmem = NO_BASE_REGISTER;
2762 i.types[op] &= ~Disp;
2763 i.types[op] |= Disp32S;
2764 i.flags[op] = Operand_PCrel;
2765 }
2766 else if (i.base_reg->reg_type & Reg16)
2767 {
2768 switch (i.base_reg->reg_num)
2769 {
2770 case 3: /* (%bx) */
2771 if (i.index_reg == 0)
2772 i.rm.regmem = 7;
2773 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2774 i.rm.regmem = i.index_reg->reg_num - 6;
2775 break;
2776 case 5: /* (%bp) */
2777 default_seg = &ss;
2778 if (i.index_reg == 0)
2779 {
2780 i.rm.regmem = 6;
2781 if ((i.types[op] & Disp) == 0)
2782 {
2783 /* fake (%bp) into 0(%bp) */
2784 i.types[op] |= Disp8;
252b5132 2785 fake_zero_displacement = 1;
29b0f896
AM		 2786 }
2787 }
2788 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2789 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2790 break;
2791 default: /* (%si) -> 4 or (%di) -> 5 */
2792 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2793 }
2794 i.rm.mode = mode_from_disp_size (i.types[op]);
2795 }
2796 else /* i.base_reg and 32/64 bit mode */
2797 {
2798 if (flag_code == CODE_64BIT
2799 && (i.types[op] & Disp))
2800 {
2801 if (i.types[op] & Disp8)
2802 i.types[op] = Disp8 | Disp32S;
2803 else
2804 i.types[op] = Disp32S;
2805 }
2806 i.rm.regmem = i.base_reg->reg_num;
2807 if ((i.base_reg->reg_flags & RegRex) != 0)
2808 i.rex |= REX_EXTZ;
2809 i.sib.base = i.base_reg->reg_num;
2810 /* x86-64 ignores REX prefix bit here to avoid decoder
2811 complications. */
2812 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2813 {
2814 default_seg = &ss;
2815 if (i.disp_operands == 0)
2816 {
2817 fake_zero_displacement = 1;
2818 i.types[op] |= Disp8;
2819 }
2820 }
2821 else if (i.base_reg->reg_num == ESP_REG_NUM)
2822 {
2823 default_seg = &ss;
2824 }
2825 i.sib.scale = i.log2_scale_factor;
2826 if (i.index_reg == 0)
2827 {
2828 /* <disp>(%esp) becomes two byte modrm with no index
2829 register. We've already stored the code for esp
2830 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2831 Any base register besides %esp will not use the
2832 extra modrm byte. */
2833 i.sib.index = NO_INDEX_REGISTER;
2834#if !SCALE1_WHEN_NO_INDEX
2835 /* Another case where we force the second modrm byte. */
2836 if (i.log2_scale_factor)
2837 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2838#endif
29b0f896
AM		 2839 }
2840 else
2841 {
2842 i.sib.index = i.index_reg->reg_num;
2843 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2844 if ((i.index_reg->reg_flags & RegRex) != 0)
2845 i.rex |= REX_EXTY;
2846 }
2847 i.rm.mode = mode_from_disp_size (i.types[op]);
2848 }
252b5132 2849
29b0f896
AM		 2850 if (fake_zero_displacement)
2851 {
2852 /* Fakes a zero displacement assuming that i.types[op]
2853 holds the correct displacement size. */
2854 expressionS *exp;
2855
2856 assert (i.op[op].disps == 0);
2857 exp = &disp_expressions[i.disp_operands++];
2858 i.op[op].disps = exp;
2859 exp->X_op = O_constant;
2860 exp->X_add_number = 0;
2861 exp->X_add_symbol = (symbolS *) 0;
2862 exp->X_op_symbol = (symbolS *) 0;
2863 }
2864 }
252b5132 2865
29b0f896
AM		 2866 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2867 (if any) based on i.tm.extension_opcode. Again, we must be
2868 careful to make sure that segment/control/debug/test/MMX
2869 registers are coded into the i.rm.reg field. */
2870 if (i.reg_operands)
2871 {
2872 unsigned int op =
2873 ((i.types[0]
2874 & (Reg | RegMMX | RegXMM
2875 | SReg2 | SReg3
2876 | Control | Debug | Test))
2877 ? 0
2878 : ((i.types[1]
2879 & (Reg | RegMMX | RegXMM
2880 | SReg2 | SReg3
2881 | Control | Debug | Test))
2882 ? 1
2883 : 2));
2884 /* If there is an extension opcode to put here, the register
2885 number must be put into the regmem field. */
2886 if (i.tm.extension_opcode != None)
2887 {
2888 i.rm.regmem = i.op[op].regs->reg_num;
2889 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2890 i.rex |= REX_EXTZ;
2891 }
2892 else
2893 {
2894 i.rm.reg = i.op[op].regs->reg_num;
2895 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2896 i.rex |= REX_EXTX;
2897 }
252b5132 2898
29b0f896
AM		 2899 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2900 must set it to 3 to indicate this is a register operand
2901 in the regmem field. */
2902 if (!i.mem_operands)
2903 i.rm.mode = 3;
2904 }
252b5132 2905
29b0f896
AM		 2906 /* Fill in i.rm.reg field with extension opcode (if any). */
2907 if (i.tm.extension_opcode != None)
2908 i.rm.reg = i.tm.extension_opcode;
2909 }
2910 return default_seg;
2911}
252b5132 2912
29b0f896
AM		 2913static void
2914output_branch ()
2915{
2916 char *p;
2917 int code16;
2918 int prefix;
2919 relax_substateT subtype;
2920 symbolS *sym;
2921 offsetT off;
2922
2923 code16 = 0;
2924 if (flag_code == CODE_16BIT)
2925 code16 = CODE16;
2926
2927 prefix = 0;
2928 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2929 {
29b0f896
AM		 2930 prefix = 1;
2931 i.prefixes -= 1;
2932 code16 ^= CODE16;
252b5132 2933 }
29b0f896
AM		 2934 /* Pentium4 branch hints. */
2935 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2936 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2937 {
29b0f896
AM		 2938 prefix++;
2939 i.prefixes--;
2940 }
2941 if (i.prefix[REX_PREFIX] != 0)
2942 {
2943 prefix++;
2944 i.prefixes--;
2f66722d
AM		 2945 }
2946
29b0f896
AM		 2947 if (i.prefixes != 0 && !intel_syntax)
2948 as_warn (_("skipping prefixes on this instruction"));
2949
2950 /* It's always a symbol; End frag & setup for relax.
2951 Make sure there is enough room in this frag for the largest
2952 instruction we may generate in md_convert_frag. This is 2
2953 bytes for the opcode and room for the prefix and largest
2954 displacement. */
2955 frag_grow (prefix + 2 + 4);
2956 /* Prefix and 1 opcode byte go in fr_fix. */
2957 p = frag_more (prefix + 1);
2958 if (i.prefix[DATA_PREFIX] != 0)
2959 *p++ = DATA_PREFIX_OPCODE;
2960 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2961 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2962 *p++ = i.prefix[SEG_PREFIX];
2963 if (i.prefix[REX_PREFIX] != 0)
2964 *p++ = i.prefix[REX_PREFIX];
2965 *p = i.tm.base_opcode;
2966
2967 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2968 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2969 else if ((cpu_arch_flags & Cpu386) != 0)
2970 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2971 else
2972 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2973 subtype |= code16;
3e73aa7c 2974
29b0f896
AM		 2975 sym = i.op[0].disps->X_add_symbol;
2976 off = i.op[0].disps->X_add_number;
3e73aa7c 2977
29b0f896
AM		 2978 if (i.op[0].disps->X_op != O_constant
2979 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2980 {
29b0f896
AM		 2981 /* Handle complex expressions. */
2982 sym = make_expr_symbol (i.op[0].disps);
2983 off = 0;
2984 }
3e73aa7c 2985
29b0f896
AM		 2986 /* 1 possible extra opcode + 4 byte displacement go in var part.
2987 Pass reloc in fr_var. */
2988 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2989}
3e73aa7c 2990
29b0f896
AM		 2991static void
2992output_jump ()
2993{
2994 char *p;
2995 int size;
2996
2997 if (i.tm.opcode_modifier & JumpByte)
2998 {
2999 /* This is a loop or jecxz type instruction. */
3000 size = 1;
3001 if (i.prefix[ADDR_PREFIX] != 0)
3002 {
3003 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3004 i.prefixes -= 1;
3005 }
3006 /* Pentium4 branch hints. */
3007 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3008 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3009 {
3010 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3011 i.prefixes--;
3e73aa7c
JH		 3012 }
3013 }
29b0f896
AM		 3014 else
3015 {
3016 int code16;
3e73aa7c 3017
29b0f896
AM		 3018 code16 = 0;
3019 if (flag_code == CODE_16BIT)
3020 code16 = CODE16;
3e73aa7c 3021
29b0f896
AM		 3022 if (i.prefix[DATA_PREFIX] != 0)
3023 {
3024 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3025 i.prefixes -= 1;
3026 code16 ^= CODE16;
3027 }
252b5132 3028
29b0f896
AM		 3029 size = 4;
3030 if (code16)
3031 size = 2;
3032 }
9fcc94b6 3033
29b0f896
AM		 3034 if (i.prefix[REX_PREFIX] != 0)
3035 {
3036 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3037 i.prefixes -= 1;
3038 }
252b5132 3039
29b0f896
AM		 3040 if (i.prefixes != 0 && !intel_syntax)
3041 as_warn (_("skipping prefixes on this instruction"));
e0890092 3042
29b0f896
AM		 3043 p = frag_more (1 + size);
3044 *p++ = i.tm.base_opcode;
e0890092 3045
062cd5e7
AS		 3046 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3047 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3048}
e0890092 3049
29b0f896
AM		 3050static void
3051output_interseg_jump ()
3052{
3053 char *p;
3054 int size;
3055 int prefix;
3056 int code16;
252b5132 3057
29b0f896
AM		 3058 code16 = 0;
3059 if (flag_code == CODE_16BIT)
3060 code16 = CODE16;
a217f122 3061
29b0f896
AM		 3062 prefix = 0;
3063 if (i.prefix[DATA_PREFIX] != 0)
3064 {
3065 prefix = 1;
3066 i.prefixes -= 1;
3067 code16 ^= CODE16;
3068 }
3069 if (i.prefix[REX_PREFIX] != 0)
3070 {
3071 prefix++;
3072 i.prefixes -= 1;
3073 }
252b5132 3074
29b0f896
AM		 3075 size = 4;
3076 if (code16)
3077 size = 2;
252b5132 3078
29b0f896
AM		 3079 if (i.prefixes != 0 && !intel_syntax)
3080 as_warn (_("skipping prefixes on this instruction"));
252b5132 3081
29b0f896
AM		 3082 /* 1 opcode; 2 segment; offset */
3083 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3084
29b0f896
AM		 3085 if (i.prefix[DATA_PREFIX] != 0)
3086 *p++ = DATA_PREFIX_OPCODE;
252b5132 3087
29b0f896
AM		 3088 if (i.prefix[REX_PREFIX] != 0)
3089 *p++ = i.prefix[REX_PREFIX];
252b5132 3090
29b0f896
AM		 3091 *p++ = i.tm.base_opcode;
3092 if (i.op[1].imms->X_op == O_constant)
3093 {
3094 offsetT n = i.op[1].imms->X_add_number;
252b5132 3095
29b0f896
AM		 3096 if (size == 2
3097 && !fits_in_unsigned_word (n)
3098 && !fits_in_signed_word (n))
3099 {
3100 as_bad (_("16-bit jump out of range"));
3101 return;
3102 }
3103 md_number_to_chars (p, n, size);
3104 }
3105 else
3106 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3107 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3108 if (i.op[0].imms->X_op != O_constant)
3109 as_bad (_("can't handle non absolute segment in `%s'"),
3110 i.tm.name);
3111 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3112}
a217f122 3113
29b0f896
AM		 3114static void
3115output_insn ()
3116{
3117 /* Tie dwarf2 debug info to the address at the start of the insn.
3118 We can't do this after the insn has been output as the current
3119 frag may have been closed off. eg. by frag_var. */
3120 dwarf2_emit_insn (0);
3121
3122 /* Output jumps. */
3123 if (i.tm.opcode_modifier & Jump)
3124 output_branch ();
3125 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3126 output_jump ();
3127 else if (i.tm.opcode_modifier & JumpInterSegment)
3128 output_interseg_jump ();
3129 else
3130 {
3131 /* Output normal instructions here. */
3132 char *p;
3133 unsigned char *q;
252b5132 3134
29b0f896
AM		 3135 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3136 byte for the SSE instructions to specify a prefix they require. */
3137 if (i.tm.base_opcode & 0xff0000)
3138 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3139
29b0f896
AM		 3140 /* The prefix bytes. */
3141 for (q = i.prefix;
3142 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3143 q++)
3144 {
3145 if (*q)
3146 {
3147 p = frag_more (1);
3148 md_number_to_chars (p, (valueT) *q, 1);
3149 }
3150 }
252b5132 3151
29b0f896
AM		 3152 /* Now the opcode; be careful about word order here! */
3153 if (fits_in_unsigned_byte (i.tm.base_opcode))
3154 {
3155 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3156 }
3157 else
3158 {
3159 p = frag_more (2);
3160 /* Put out high byte first: can't use md_number_to_chars! */
3161 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3162 *p = i.tm.base_opcode & 0xff;
3163 }
3e73aa7c 3164
29b0f896
AM		 3165 /* Now the modrm byte and sib byte (if present). */
3166 if (i.tm.opcode_modifier & Modrm)
3167 {
3168 p = frag_more (1);
3169 md_number_to_chars (p,
3170 (valueT) (i.rm.regmem << 0
3171 | i.rm.reg << 3
3172 | i.rm.mode << 6),
3173 1);
3174 /* If i.rm.regmem == ESP (4)
3175 && i.rm.mode != (Register mode)
3176 && not 16 bit
3177 ==> need second modrm byte. */
3178 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3179 && i.rm.mode != 3
3180 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3181 {
3182 p = frag_more (1);
3183 md_number_to_chars (p,
3184 (valueT) (i.sib.base << 0
3185 | i.sib.index << 3
3186 | i.sib.scale << 6),
3187 1);
3188 }
3189 }
3e73aa7c 3190
29b0f896
AM		 3191 if (i.disp_operands)
3192 output_disp ();
3e73aa7c 3193
29b0f896
AM		 3194 if (i.imm_operands)
3195 output_imm ();
3196 }
252b5132 3197
29b0f896
AM		 3198#ifdef DEBUG386
3199 if (flag_debug)
3200 {
3201 pi (line, &i);
3202 }
3203#endif /* DEBUG386 */
3204}
252b5132 3205
29b0f896
AM		 3206static void
3207output_disp ()
3208{
3209 char *p;
3210 unsigned int n;
252b5132 3211
29b0f896
AM		 3212 for (n = 0; n < i.operands; n++)
3213 {
3214 if (i.types[n] & Disp)
3215 {
3216 if (i.op[n].disps->X_op == O_constant)
3217 {
3218 int size;
3219 offsetT val;
252b5132 3220
29b0f896
AM		 3221 size = 4;
3222 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3223 {
3224 size = 2;
3225 if (i.types[n] & Disp8)
3226 size = 1;
3227 if (i.types[n] & Disp64)
3228 size = 8;
3229 }
3230 val = offset_in_range (i.op[n].disps->X_add_number,
3231 size);
3232 p = frag_more (size);
3233 md_number_to_chars (p, val, size);
3234 }
3235 else
3236 {
3237 int size = 4;
3238 int sign = 0;
3239 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3240
3241 /* The PC relative address is computed relative
3242 to the instruction boundary, so in case immediate
3243 fields follows, we need to adjust the value. */
3244 if (pcrel && i.imm_operands)
3245 {
3246 int imm_size = 4;
3247 unsigned int n1;
252b5132 3248
29b0f896
AM		 3249 for (n1 = 0; n1 < i.operands; n1++)
3250 if (i.types[n1] & Imm)
252b5132 3251 {
29b0f896 3252 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3253 {
29b0f896
AM		 3254 imm_size = 2;
3255 if (i.types[n1] & (Imm8 | Imm8S))
3256 imm_size = 1;
3257 if (i.types[n1] & Imm64)
3258 imm_size = 8;
252b5132 3259 }
29b0f896 3260 break;
252b5132 3261 }
29b0f896
AM		 3262 /* We should find the immediate. */
3263 if (n1 == i.operands)
3264 abort ();
3265 i.op[n].disps->X_add_number -= imm_size;
3266 }
520dc8e8 3267
29b0f896
AM		 3268 if (i.types[n] & Disp32S)
3269 sign = 1;
3e73aa7c 3270
29b0f896
AM		 3271 if (i.types[n] & (Disp16 | Disp64))
3272 {
3273 size = 2;
3274 if (i.types[n] & Disp64)
3275 size = 8;
3276 }
520dc8e8 3277
29b0f896 3278 p = frag_more (size);
062cd5e7
AS		 3279 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3280 i.op[n].disps, pcrel,
3281 reloc (size, pcrel, sign, i.reloc[n]));
29b0f896
AM		 3282 }
3283 }
3284 }
3285}
252b5132 3286
29b0f896
AM		 3287static void
3288output_imm ()
3289{
3290 char *p;
3291 unsigned int n;
252b5132 3292
29b0f896
AM		 3293 for (n = 0; n < i.operands; n++)
3294 {
3295 if (i.types[n] & Imm)
3296 {
3297 if (i.op[n].imms->X_op == O_constant)
3298 {
3299 int size;
3300 offsetT val;
b4cac588 3301
29b0f896
AM		 3302 size = 4;
3303 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3304 {
3305 size = 2;
3306 if (i.types[n] & (Imm8 | Imm8S))
3307 size = 1;
3308 else if (i.types[n] & Imm64)
3309 size = 8;
3310 }
3311 val = offset_in_range (i.op[n].imms->X_add_number,
3312 size);
3313 p = frag_more (size);
3314 md_number_to_chars (p, val, size);
3315 }
3316 else
3317 {
3318 /* Not absolute_section.
3319 Need a 32-bit fixup (don't support 8bit
3320 non-absolute imms). Try to support other
3321 sizes ... */
3322 RELOC_ENUM reloc_type;
3323 int size = 4;
3324 int sign = 0;
3325
3326 if ((i.types[n] & (Imm32S))
3327 && i.suffix == QWORD_MNEM_SUFFIX)
3328 sign = 1;
3329 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3330 {
3331 size = 2;
3332 if (i.types[n] & (Imm8 | Imm8S))
3333 size = 1;
3334 if (i.types[n] & Imm64)
3335 size = 8;
3336 }
520dc8e8 3337
29b0f896
AM		 3338 p = frag_more (size);
3339 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3340#ifdef BFD_ASSEMBLER
29b0f896
AM		 3341 if (reloc_type == BFD_RELOC_32
3342 && GOT_symbol
3343 && GOT_symbol == i.op[n].imms->X_add_symbol
3344 && (i.op[n].imms->X_op == O_symbol
3345 || (i.op[n].imms->X_op == O_add
3346 && ((symbol_get_value_expression
3347 (i.op[n].imms->X_op_symbol)->X_op)
3348 == O_subtract))))
3349 {
3350 /* We don't support dynamic linking on x86-64 yet. */
3351 if (flag_code == CODE_64BIT)
3352 abort ();
3353 reloc_type = BFD_RELOC_386_GOTPC;
3354 i.op[n].imms->X_add_number += 3;
3355 }
252b5132 3356#endif
29b0f896
AM		 3357 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3358 i.op[n].imms, 0, reloc_type);
3359 }
3360 }
3361 }
252b5132
RH		 3362}
3363\f
f3c180ae
AM		 3364#ifndef LEX_AT
3365static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3366
3367/* Parse operands of the form
3368 <symbol>@GOTOFF+<nnn>
3369 and similar .plt or .got references.
3370
3371 If we find one, set up the correct relocation in RELOC and copy the
3372 input string, minus the `@GOTOFF' into a malloc'd buffer for
3373 parsing by the calling routine. Return this buffer, and if ADJUST
3374 is non-null set it to the length of the string we removed from the
3375 input line. Otherwise return NULL. */
3376static char *
3377lex_got (reloc, adjust)
3378 RELOC_ENUM *reloc;
3379 int *adjust;
3380{
3381 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3382 static const struct {
3383 const char *str;
3384 const RELOC_ENUM rel[NUM_FLAG_CODE];
3385 } gotrel[] = {
13ae64f3
JJ		 3386 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3387 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3388 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3389 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3390 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3391 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3392 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3393 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3394 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3395 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3396 };
3397 char *cp;
3398 unsigned int j;
3399
3400 for (cp = input_line_pointer; *cp != '@'; cp++)
3401 if (is_end_of_line[(unsigned char) *cp])
3402 return NULL;
3403
3404 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3405 {
3406 int len;
3407
3408 len = strlen (gotrel[j].str);
28f81592 3409 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3410 {
3411 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3412 {
28f81592
AM		 3413 int first, second;
3414 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3415
3416 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3417 if (adjust)
3418 *adjust = len;
f3c180ae
AM		 3419
3420 if (GOT_symbol == NULL)
3421 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3422
3423 /* Replace the relocation token with ' ', so that
3424 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3425
3426 /* The length of the first part of our input line. */
f3c180ae 3427 first = cp - input_line_pointer;
28f81592
AM		 3428
3429 /* The second part goes from after the reloc token until
3430 (and including) an end_of_line char. Don't use strlen
3431 here as the end_of_line char may not be a NUL. */
3432 past_reloc = cp + 1 + len;
3433 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3434 ;
3435 second = cp - past_reloc;
3436
3437 /* Allocate and copy string. The trailing NUL shouldn't
3438 be necessary, but be safe. */
3439 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3440 memcpy (tmpbuf, input_line_pointer, first);
3441 tmpbuf[first] = ' ';
28f81592
AM		 3442 memcpy (tmpbuf + first + 1, past_reloc, second);
3443 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3444 return tmpbuf;
3445 }
3446
3447 as_bad (_("@%s reloc is not supported in %s bit mode"),
3448 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3449 return NULL;
3450 }
3451 }
3452
3453 /* Might be a symbol version string. Don't as_bad here. */
3454 return NULL;
3455}
3456
3457/* x86_cons_fix_new is called via the expression parsing code when a
3458 reloc is needed. We use this hook to get the correct .got reloc. */
3459static RELOC_ENUM got_reloc = NO_RELOC;
3460
3461void
3462x86_cons_fix_new (frag, off, len, exp)
3463 fragS *frag;
3464 unsigned int off;
3465 unsigned int len;
3466 expressionS *exp;
3467{
3468 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3469 got_reloc = NO_RELOC;
3470 fix_new_exp (frag, off, len, exp, 0, r);
3471}
3472
3473void
3474x86_cons (exp, size)
3475 expressionS *exp;
3476 int size;
3477{
3478 if (size == 4)
3479 {
3480 /* Handle @GOTOFF and the like in an expression. */
3481 char *save;
3482 char *gotfree_input_line;
3483 int adjust;
3484
3485 save = input_line_pointer;
3486 gotfree_input_line = lex_got (&got_reloc, &adjust);
3487 if (gotfree_input_line)
3488 input_line_pointer = gotfree_input_line;
3489
3490 expression (exp);
3491
3492 if (gotfree_input_line)
3493 {
3494 /* expression () has merrily parsed up to the end of line,
3495 or a comma - in the wrong buffer. Transfer how far
3496 input_line_pointer has moved to the right buffer. */
3497 input_line_pointer = (save
3498 + (input_line_pointer - gotfree_input_line)
3499 + adjust);
3500 free (gotfree_input_line);
3501 }
3502 }
3503 else
3504 expression (exp);
3505}
3506#endif
3507
252b5132
RH		 3508static int i386_immediate PARAMS ((char *));
3509
3510static int
3511i386_immediate (imm_start)
3512 char *imm_start;
3513{
3514 char *save_input_line_pointer;
f3c180ae
AM		 3515#ifndef LEX_AT
3516 char *gotfree_input_line;
3517#endif
252b5132 3518 segT exp_seg = 0;
47926f60 3519 expressionS *exp;
252b5132
RH		 3520
3521 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3522 {
d0b47220 3523 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3524 return 0;
3525 }
3526
3527 exp = &im_expressions[i.imm_operands++];
520dc8e8 3528 i.op[this_operand].imms = exp;
252b5132
RH		 3529
3530 if (is_space_char (*imm_start))
3531 ++imm_start;
3532
3533 save_input_line_pointer = input_line_pointer;
3534 input_line_pointer = imm_start;
3535
3536#ifndef LEX_AT
f3c180ae
AM		 3537 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3538 if (gotfree_input_line)
3539 input_line_pointer = gotfree_input_line;
252b5132
RH		 3540#endif
3541
3542 exp_seg = expression (exp);
3543
83183c0c 3544 SKIP_WHITESPACE ();
252b5132 3545 if (*input_line_pointer)
f3c180ae 3546 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3547
3548 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3549#ifndef LEX_AT
3550 if (gotfree_input_line)
3551 free (gotfree_input_line);
3552#endif
252b5132 3553
2daf4fd8 3554 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3555 {
47926f60 3556 /* Missing or bad expr becomes absolute 0. */
d0b47220 3557 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3558 imm_start);
252b5132
RH		 3559 exp->X_op = O_constant;
3560 exp->X_add_number = 0;
3561 exp->X_add_symbol = (symbolS *) 0;
3562 exp->X_op_symbol = (symbolS *) 0;
252b5132 3563 }
3e73aa7c 3564 else if (exp->X_op == O_constant)
252b5132 3565 {
47926f60 3566 /* Size it properly later. */
3e73aa7c
JH		 3567 i.types[this_operand] |= Imm64;
3568 /* If BFD64, sign extend val. */
3569 if (!use_rela_relocations)
3570 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3571 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3572 }
4c63da97 3573#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3574 else if (1
4c63da97 3575#ifdef BFD_ASSEMBLER
47926f60 3576 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3577#endif
47926f60 3578 && exp_seg != text_section
24eab124
AM		 3579 && exp_seg != data_section
3580 && exp_seg != bss_section
3581 && exp_seg != undefined_section
252b5132 3582#ifdef BFD_ASSEMBLER
24eab124 3583 && !bfd_is_com_section (exp_seg)
252b5132 3584#endif
24eab124 3585 )
252b5132 3586 {
4c63da97 3587#ifdef BFD_ASSEMBLER
d0b47220 3588 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3589#else
d0b47220 3590 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3591#endif
252b5132
RH		 3592 return 0;
3593 }
3594#endif
3595 else
3596 {
3597 /* This is an address. The size of the address will be
24eab124 3598 determined later, depending on destination register,
3e73aa7c
JH		 3599 suffix, or the default for the section. */
3600 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3601 }
3602
3603 return 1;
3604}
3605
551c1ca1 3606static char *i386_scale PARAMS ((char *));
252b5132 3607
551c1ca1 3608static char *
252b5132
RH		 3609i386_scale (scale)
3610 char *scale;
3611{
551c1ca1
AM		 3612 offsetT val;
3613 char *save = input_line_pointer;
252b5132 3614
551c1ca1
AM		 3615 input_line_pointer = scale;
3616 val = get_absolute_expression ();
3617
3618 switch (val)
252b5132 3619 {
551c1ca1
AM		 3620 case 0:
3621 case 1:
252b5132
RH		 3622 i.log2_scale_factor = 0;
3623 break;
551c1ca1 3624 case 2:
252b5132
RH		 3625 i.log2_scale_factor = 1;
3626 break;
551c1ca1 3627 case 4:
252b5132
RH		 3628 i.log2_scale_factor = 2;
3629 break;
551c1ca1 3630 case 8:
252b5132
RH		 3631 i.log2_scale_factor = 3;
3632 break;
3633 default:
252b5132 3634 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3635 scale);
551c1ca1
AM		 3636 input_line_pointer = save;
3637 return NULL;
252b5132 3638 }
29b0f896 3639 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3640 {
3641 as_warn (_("scale factor of %d without an index register"),
24eab124 3642 1 << i.log2_scale_factor);
252b5132
RH		 3643#if SCALE1_WHEN_NO_INDEX
3644 i.log2_scale_factor = 0;
3645#endif
3646 }
551c1ca1
AM		 3647 scale = input_line_pointer;
3648 input_line_pointer = save;
3649 return scale;
252b5132
RH		 3650}
3651
3652static int i386_displacement PARAMS ((char *, char *));
3653
3654static int
3655i386_displacement (disp_start, disp_end)
3656 char *disp_start;
3657 char *disp_end;
3658{
29b0f896 3659 expressionS *exp;
252b5132
RH		 3660 segT exp_seg = 0;
3661 char *save_input_line_pointer;
f3c180ae
AM		 3662#ifndef LEX_AT
3663 char *gotfree_input_line;
3664#endif
252b5132
RH		 3665 int bigdisp = Disp32;
3666
3e73aa7c 3667 if (flag_code == CODE_64BIT)
7ecd2f8b 3668 {
29b0f896
AM		 3669 if (i.prefix[ADDR_PREFIX] == 0)
3670 bigdisp = Disp64;
7ecd2f8b
JH		 3671 }
3672 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3673 bigdisp = Disp16;
252b5132
RH		 3674 i.types[this_operand] |= bigdisp;
3675
3676 exp = &disp_expressions[i.disp_operands];
520dc8e8 3677 i.op[this_operand].disps = exp;
252b5132
RH		 3678 i.disp_operands++;
3679 save_input_line_pointer = input_line_pointer;
3680 input_line_pointer = disp_start;
3681 END_STRING_AND_SAVE (disp_end);
3682
3683#ifndef GCC_ASM_O_HACK
3684#define GCC_ASM_O_HACK 0
3685#endif
3686#if GCC_ASM_O_HACK
3687 END_STRING_AND_SAVE (disp_end + 1);
3688 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3689 && displacement_string_end[-1] == '+')
252b5132
RH		 3690 {
3691 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3692 constraint within gcc asm statements.
3693 For instance:
3694
3695 #define _set_tssldt_desc(n,addr,limit,type) \
3696 __asm__ __volatile__ ( \
3697 "movw %w2,%0\n\t" \
3698 "movw %w1,2+%0\n\t" \
3699 "rorl $16,%1\n\t" \
3700 "movb %b1,4+%0\n\t" \
3701 "movb %4,5+%0\n\t" \
3702 "movb $0,6+%0\n\t" \
3703 "movb %h1,7+%0\n\t" \
3704 "rorl $16,%1" \
3705 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3706
3707 This works great except that the output assembler ends
3708 up looking a bit weird if it turns out that there is
3709 no offset. You end up producing code that looks like:
3710
3711 #APP
3712 movw $235,(%eax)
3713 movw %dx,2+(%eax)
3714 rorl $16,%edx
3715 movb %dl,4+(%eax)
3716 movb $137,5+(%eax)
3717 movb $0,6+(%eax)
3718 movb %dh,7+(%eax)
3719 rorl $16,%edx
3720 #NO_APP
3721
47926f60 3722 So here we provide the missing zero. */
24eab124
AM		 3723
3724 *displacement_string_end = '0';
252b5132
RH		 3725 }
3726#endif
3727#ifndef LEX_AT
f3c180ae
AM		 3728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3729 if (gotfree_input_line)
3730 input_line_pointer = gotfree_input_line;
252b5132
RH		 3731#endif
3732
24eab124 3733 exp_seg = expression (exp);
252b5132 3734
636c26b0
AM		 3735 SKIP_WHITESPACE ();
3736 if (*input_line_pointer)
3737 as_bad (_("junk `%s' after expression"), input_line_pointer);
3738#if GCC_ASM_O_HACK
3739 RESTORE_END_STRING (disp_end + 1);
3740#endif
3741 RESTORE_END_STRING (disp_end);
3742 input_line_pointer = save_input_line_pointer;
3743#ifndef LEX_AT
3744 if (gotfree_input_line)
3745 free (gotfree_input_line);
3746#endif
3747
252b5132 3748#ifdef BFD_ASSEMBLER
24eab124
AM		 3749 /* We do this to make sure that the section symbol is in
3750 the symbol table. We will ultimately change the relocation
47926f60 3751 to be relative to the beginning of the section. */
1ae12ab7
AM		 3752 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3753 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3754 {
636c26b0
AM		 3755 if (exp->X_op != O_symbol)
3756 {
3757 as_bad (_("bad expression used with @%s"),
3758 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3759 ? "GOTPCREL"
3760 : "GOTOFF"));
3761 return 0;
3762 }
3763
e5cb08ac 3764 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3765 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3766 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3767 exp->X_op = O_subtract;
3768 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3769 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3770 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3771 else
29b0f896 3772 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3773 }
252b5132
RH		 3774#endif
3775
2daf4fd8
AM		 3776 if (exp->X_op == O_absent || exp->X_op == O_big)
3777 {
47926f60 3778 /* Missing or bad expr becomes absolute 0. */
d0b47220 3779 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3780 disp_start);
3781 exp->X_op = O_constant;
3782 exp->X_add_number = 0;
3783 exp->X_add_symbol = (symbolS *) 0;
3784 exp->X_op_symbol = (symbolS *) 0;
3785 }
3786
4c63da97 3787#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3788 if (exp->X_op != O_constant
4c63da97 3789#ifdef BFD_ASSEMBLER
45288df1 3790 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3791#endif
45288df1
AM		 3792 && exp_seg != text_section
3793 && exp_seg != data_section
3794 && exp_seg != bss_section
3795 && exp_seg != undefined_section)
24eab124 3796 {
4c63da97 3797#ifdef BFD_ASSEMBLER
d0b47220 3798 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3799#else
d0b47220 3800 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3801#endif
24eab124
AM		 3802 return 0;
3803 }
252b5132 3804#endif
3e73aa7c
JH		 3805 else if (flag_code == CODE_64BIT)
3806 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3807 return 1;
3808}
3809
e5cb08ac 3810static int i386_index_check PARAMS ((const char *));
252b5132 3811
eecb386c 3812/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3813 Return 1 on success, 0 on a failure. */
3814
252b5132 3815static int
eecb386c
AM		 3816i386_index_check (operand_string)
3817 const char *operand_string;
252b5132 3818{
3e73aa7c 3819 int ok;
24eab124 3820#if INFER_ADDR_PREFIX
eecb386c
AM		 3821 int fudged = 0;
3822
24eab124
AM		 3823 tryprefix:
3824#endif
3e73aa7c
JH		 3825 ok = 1;
3826 if (flag_code == CODE_64BIT)
3827 {
7ecd2f8b
JH		 3828 if (i.prefix[ADDR_PREFIX] == 0)
3829 {
3830 /* 64bit checks. */
3831 if ((i.base_reg
3832 && ((i.base_reg->reg_type & Reg64) == 0)
3833 && (i.base_reg->reg_type != BaseIndex
3834 || i.index_reg))
3835 || (i.index_reg
29b0f896
AM		 3836 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3837 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3838 ok = 0;
3839 }
3840 else
3841 {
3842 /* 32bit checks. */
3843 if ((i.base_reg
3844 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3845 || (i.index_reg
29b0f896
AM		 3846 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3847 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3848 ok = 0;
3849 }
3e73aa7c
JH		 3850 }
3851 else
3852 {
3853 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3854 {
3855 /* 16bit checks. */
3856 if ((i.base_reg
29b0f896
AM		 3857 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3858 != (Reg16 | BaseIndex)))
3e73aa7c 3859 || (i.index_reg
29b0f896
AM		 3860 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3861 != (Reg16 | BaseIndex))
3862 || !(i.base_reg
3863 && i.base_reg->reg_num < 6
3864 && i.index_reg->reg_num >= 6
3865 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3866 ok = 0;
3867 }
3868 else
e5cb08ac 3869 {
3e73aa7c
JH		 3870 /* 32bit checks. */
3871 if ((i.base_reg
3872 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3873 || (i.index_reg
29b0f896
AM		 3874 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3875 != (Reg32 | BaseIndex))))
e5cb08ac 3876 ok = 0;
3e73aa7c
JH		 3877 }
3878 }
3879 if (!ok)
24eab124
AM		 3880 {
3881#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3882 if (flag_code != CODE_64BIT
3883 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3884 {
3885 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3886 i.prefixes += 1;
b23bac36
AM		 3887 /* Change the size of any displacement too. At most one of
3888 Disp16 or Disp32 is set.
3889 FIXME. There doesn't seem to be any real need for separate
3890 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3891 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3892 if (i.types[this_operand] & (Disp16 | Disp32))
3893 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3894 fudged = 1;
24eab124
AM		 3895 goto tryprefix;
3896 }
eecb386c
AM		 3897 if (fudged)
3898 as_bad (_("`%s' is not a valid base/index expression"),
3899 operand_string);
3900 else
c388dee8 3901#endif
eecb386c
AM		 3902 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3903 operand_string,
3e73aa7c 3904 flag_code_names[flag_code]);
eecb386c 3905 return 0;
24eab124
AM		 3906 }
3907 return 1;
3908}
252b5132 3909
252b5132 3910/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3911 on error. */
252b5132 3912
252b5132
RH		 3913static int
3914i386_operand (operand_string)
3915 char *operand_string;
3916{
af6bdddf
AM		 3917 const reg_entry *r;
3918 char *end_op;
24eab124 3919 char *op_string = operand_string;
252b5132 3920
24eab124 3921 if (is_space_char (*op_string))
252b5132
RH		 3922 ++op_string;
3923
24eab124 3924 /* We check for an absolute prefix (differentiating,
47926f60 3925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3926 if (*op_string == ABSOLUTE_PREFIX)
3927 {
3928 ++op_string;
3929 if (is_space_char (*op_string))
3930 ++op_string;
3931 i.types[this_operand] |= JumpAbsolute;
3932 }
252b5132 3933
47926f60 3934 /* Check if operand is a register. */
af6bdddf
AM		 3935 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3936 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3937 {
24eab124
AM		 3938 /* Check for a segment override by searching for ':' after a
3939 segment register. */
3940 op_string = end_op;
3941 if (is_space_char (*op_string))
3942 ++op_string;
3943 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3944 {
3945 switch (r->reg_num)
3946 {
3947 case 0:
3948 i.seg[i.mem_operands] = &es;
3949 break;
3950 case 1:
3951 i.seg[i.mem_operands] = &cs;
3952 break;
3953 case 2:
3954 i.seg[i.mem_operands] = &ss;
3955 break;
3956 case 3:
3957 i.seg[i.mem_operands] = &ds;
3958 break;
3959 case 4:
3960 i.seg[i.mem_operands] = &fs;
3961 break;
3962 case 5:
3963 i.seg[i.mem_operands] = &gs;
3964 break;
3965 }
252b5132 3966
24eab124 3967 /* Skip the ':' and whitespace. */
252b5132
RH		 3968 ++op_string;
3969 if (is_space_char (*op_string))
24eab124 3970 ++op_string;
252b5132 3971
24eab124
AM		 3972 if (!is_digit_char (*op_string)
3973 && !is_identifier_char (*op_string)
3974 && *op_string != '('
3975 && *op_string != ABSOLUTE_PREFIX)
3976 {
3977 as_bad (_("bad memory operand `%s'"), op_string);
3978 return 0;
3979 }
47926f60 3980 /* Handle case of %es:*foo. */
24eab124
AM		 3981 if (*op_string == ABSOLUTE_PREFIX)
3982 {
3983 ++op_string;
3984 if (is_space_char (*op_string))
3985 ++op_string;
3986 i.types[this_operand] |= JumpAbsolute;
3987 }
3988 goto do_memory_reference;
3989 }
3990 if (*op_string)
3991 {
d0b47220 3992 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3993 return 0;
3994 }
3995 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3996 i.op[this_operand].regs = r;
24eab124
AM		 3997 i.reg_operands++;
3998 }
af6bdddf
AM		 3999 else if (*op_string == REGISTER_PREFIX)
4000 {
4001 as_bad (_("bad register name `%s'"), op_string);
4002 return 0;
4003 }
24eab124 4004 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4005 {
24eab124
AM		 4006 ++op_string;
4007 if (i.types[this_operand] & JumpAbsolute)
4008 {
d0b47220 4009 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4010 return 0;
4011 }
4012 if (!i386_immediate (op_string))
4013 return 0;
4014 }
4015 else if (is_digit_char (*op_string)
4016 || is_identifier_char (*op_string)
e5cb08ac 4017 || *op_string == '(')
24eab124 4018 {
47926f60 4019 /* This is a memory reference of some sort. */
af6bdddf 4020 char *base_string;
252b5132 4021
47926f60 4022 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4023 char *displacement_string_start;
4024 char *displacement_string_end;
252b5132 4025
24eab124 4026 do_memory_reference:
24eab124
AM		 4027 if ((i.mem_operands == 1
4028 && (current_templates->start->opcode_modifier & IsString) == 0)
4029 || i.mem_operands == 2)
4030 {
4031 as_bad (_("too many memory references for `%s'"),
4032 current_templates->start->name);
4033 return 0;
4034 }
252b5132 4035
24eab124
AM		 4036 /* Check for base index form. We detect the base index form by
4037 looking for an ')' at the end of the operand, searching
4038 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4039 after the '('. */
af6bdddf 4040 base_string = op_string + strlen (op_string);
c3332e24 4041
af6bdddf
AM		 4042 --base_string;
4043 if (is_space_char (*base_string))
4044 --base_string;
252b5132 4045
47926f60 4046 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4047 displacement_string_start = op_string;
4048 displacement_string_end = base_string + 1;
252b5132 4049
24eab124
AM		 4050 if (*base_string == ')')
4051 {
af6bdddf 4052 char *temp_string;
24eab124
AM		 4053 unsigned int parens_balanced = 1;
4054 /* We've already checked that the number of left & right ()'s are
47926f60 4055 equal, so this loop will not be infinite. */
24eab124
AM		 4056 do
4057 {
4058 base_string--;
4059 if (*base_string == ')')
4060 parens_balanced++;
4061 if (*base_string == '(')
4062 parens_balanced--;
4063 }
4064 while (parens_balanced);
c3332e24 4065
af6bdddf 4066 temp_string = base_string;
c3332e24 4067
24eab124 4068 /* Skip past '(' and whitespace. */
252b5132
RH		 4069 ++base_string;
4070 if (is_space_char (*base_string))
24eab124 4071 ++base_string;
252b5132 4072
af6bdddf
AM		 4073 if (*base_string == ','
4074 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4075 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4076 {
af6bdddf 4077 displacement_string_end = temp_string;
252b5132 4078
af6bdddf 4079 i.types[this_operand] |= BaseIndex;
252b5132 4080
af6bdddf 4081 if (i.base_reg)
24eab124 4082 {
24eab124
AM		 4083 base_string = end_op;
4084 if (is_space_char (*base_string))
4085 ++base_string;
af6bdddf
AM		 4086 }
4087
4088 /* There may be an index reg or scale factor here. */
4089 if (*base_string == ',')
4090 {
4091 ++base_string;
4092 if (is_space_char (*base_string))
4093 ++base_string;
4094
4095 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4096 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4097 {
af6bdddf 4098 base_string = end_op;
24eab124
AM		 4099 if (is_space_char (*base_string))
4100 ++base_string;
af6bdddf
AM		 4101 if (*base_string == ',')
4102 {
4103 ++base_string;
4104 if (is_space_char (*base_string))
4105 ++base_string;
4106 }
e5cb08ac 4107 else if (*base_string != ')')
af6bdddf
AM		 4108 {
4109 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4110 operand_string);
4111 return 0;
4112 }
24eab124 4113 }
af6bdddf 4114 else if (*base_string == REGISTER_PREFIX)
24eab124 4115 {
af6bdddf 4116 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4117 return 0;
4118 }
252b5132 4119
47926f60 4120 /* Check for scale factor. */
551c1ca1 4121 if (*base_string != ')')
af6bdddf 4122 {
551c1ca1
AM		 4123 char *end_scale = i386_scale (base_string);
4124
4125 if (!end_scale)
af6bdddf 4126 return 0;
24eab124 4127
551c1ca1 4128 base_string = end_scale;
af6bdddf
AM		 4129 if (is_space_char (*base_string))
4130 ++base_string;
4131 if (*base_string != ')')
4132 {
4133 as_bad (_("expecting `)' after scale factor in `%s'"),
4134 operand_string);
4135 return 0;
4136 }
4137 }
4138 else if (!i.index_reg)
24eab124 4139 {
af6bdddf
AM		 4140 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4141 *base_string);
24eab124
AM		 4142 return 0;
4143 }
4144 }
af6bdddf 4145 else if (*base_string != ')')
24eab124 4146 {
af6bdddf
AM		 4147 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4148 operand_string);
24eab124
AM		 4149 return 0;
4150 }
c3332e24 4151 }
af6bdddf 4152 else if (*base_string == REGISTER_PREFIX)
c3332e24 4153 {
af6bdddf 4154 as_bad (_("bad register name `%s'"), base_string);
24eab124 4155 return 0;
c3332e24 4156 }
24eab124
AM		 4157 }
4158
4159 /* If there's an expression beginning the operand, parse it,
4160 assuming displacement_string_start and
4161 displacement_string_end are meaningful. */
4162 if (displacement_string_start != displacement_string_end)
4163 {
4164 if (!i386_displacement (displacement_string_start,
4165 displacement_string_end))
4166 return 0;
4167 }
4168
4169 /* Special case for (%dx) while doing input/output op. */
4170 if (i.base_reg
4171 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4172 && i.index_reg == 0
4173 && i.log2_scale_factor == 0
4174 && i.seg[i.mem_operands] == 0
4175 && (i.types[this_operand] & Disp) == 0)
4176 {
4177 i.types[this_operand] = InOutPortReg;
4178 return 1;
4179 }
4180
eecb386c
AM		 4181 if (i386_index_check (operand_string) == 0)
4182 return 0;
24eab124
AM		 4183 i.mem_operands++;
4184 }
4185 else
ce8a8b2f
AM		 4186 {
4187 /* It's not a memory operand; argh! */
24eab124
AM		 4188 as_bad (_("invalid char %s beginning operand %d `%s'"),
4189 output_invalid (*op_string),
4190 this_operand + 1,
4191 op_string);
4192 return 0;
4193 }
47926f60 4194 return 1; /* Normal return. */
252b5132
RH		 4195}
4196\f
ee7fcc42
AM		 4197/* md_estimate_size_before_relax()
4198
4199 Called just before relax() for rs_machine_dependent frags. The x86
4200 assembler uses these frags to handle variable size jump
4201 instructions.
4202
4203 Any symbol that is now undefined will not become defined.
4204 Return the correct fr_subtype in the frag.
4205 Return the initial "guess for variable size of frag" to caller.
4206 The guess is actually the growth beyond the fixed part. Whatever
4207 we do to grow the fixed or variable part contributes to our
4208 returned value. */
4209
252b5132
RH		 4210int
4211md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4212 fragS *fragP;
4213 segT segment;
252b5132 4214{
252b5132 4215 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4216 check for un-relaxable symbols. On an ELF system, we can't relax
4217 an externally visible symbol, because it may be overridden by a
4218 shared library. */
4219 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4220#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 4221 || S_IS_EXTERNAL (fragP->fr_symbol)
4222 || S_IS_WEAK (fragP->fr_symbol)
4223#endif
4224 )
252b5132 4225 {
b98ef147
AM		 4226 /* Symbol is undefined in this segment, or we need to keep a
4227 reloc so that weak symbols can be overridden. */
4228 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4229 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4230 unsigned char *opcode;
4231 int old_fr_fix;
f6af82bd 4232
ee7fcc42
AM		 4233 if (fragP->fr_var != NO_RELOC)
4234 reloc_type = fragP->fr_var;
b98ef147 4235 else if (size == 2)
f6af82bd
AM		 4236 reloc_type = BFD_RELOC_16_PCREL;
4237 else
4238 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4239
ee7fcc42
AM		 4240 old_fr_fix = fragP->fr_fix;
4241 opcode = (unsigned char *) fragP->fr_opcode;
4242
fddf5b5b 4243 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4244 {
fddf5b5b
AM		 4245 case UNCOND_JUMP:
4246 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4247 opcode[0] = 0xe9;
252b5132 4248 fragP->fr_fix += size;
062cd5e7
AS		 4249 fix_new (fragP, old_fr_fix, size,
4250 fragP->fr_symbol,
4251 fragP->fr_offset, 1,
4252 reloc_type);
252b5132
RH		 4253 break;
4254
fddf5b5b 4255 case COND_JUMP86:
412167cb
AM		 4256 if (size == 2
4257 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4258 {
4259 /* Negate the condition, and branch past an
4260 unconditional jump. */
4261 opcode[0] ^= 1;
4262 opcode[1] = 3;
4263 /* Insert an unconditional jump. */
4264 opcode[2] = 0xe9;
4265 /* We added two extra opcode bytes, and have a two byte
4266 offset. */
4267 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4268 fix_new (fragP, old_fr_fix + 2, 2,
4269 fragP->fr_symbol,
4270 fragP->fr_offset, 1,
4271 reloc_type);
fddf5b5b
AM		 4272 break;
4273 }
4274 /* Fall through. */
4275
4276 case COND_JUMP:
412167cb
AM		 4277 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4278 {
4279 fragP->fr_fix += 1;
4280 fix_new (fragP, old_fr_fix, 1,
4281 fragP->fr_symbol,
4282 fragP->fr_offset, 1,
4283 BFD_RELOC_8_PCREL);
4284 break;
4285 }
93c2a809 4286
24eab124 4287 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4288 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4289 opcode[1] = opcode[0] + 0x10;
f6af82bd 4290 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4291 /* We've added an opcode byte. */
4292 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4293 fix_new (fragP, old_fr_fix + 1, size,
4294 fragP->fr_symbol,
4295 fragP->fr_offset, 1,
4296 reloc_type);
252b5132 4297 break;
fddf5b5b
AM		 4298
4299 default:
4300 BAD_CASE (fragP->fr_subtype);
4301 break;
252b5132
RH		 4302 }
4303 frag_wane (fragP);
ee7fcc42 4304 return fragP->fr_fix - old_fr_fix;
252b5132 4305 }
93c2a809 4306
93c2a809
AM		 4307 /* Guess size depending on current relax state. Initially the relax
4308 state will correspond to a short jump and we return 1, because
4309 the variable part of the frag (the branch offset) is one byte
4310 long. However, we can relax a section more than once and in that
4311 case we must either set fr_subtype back to the unrelaxed state,
4312 or return the value for the appropriate branch. */
4313 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4314}
4315
47926f60
KH		 4316/* Called after relax() is finished.
4317
4318 In: Address of frag.
4319 fr_type == rs_machine_dependent.
4320 fr_subtype is what the address relaxed to.
4321
4322 Out: Any fixSs and constants are set up.
4323 Caller will turn frag into a ".space 0". */
4324
252b5132
RH		 4325#ifndef BFD_ASSEMBLER
4326void
4327md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4328 object_headers *headers ATTRIBUTE_UNUSED;
4329 segT sec ATTRIBUTE_UNUSED;
29b0f896 4330 fragS *fragP;
252b5132
RH		 4331#else
4332void
4333md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4334 bfd *abfd ATTRIBUTE_UNUSED;
4335 segT sec ATTRIBUTE_UNUSED;
29b0f896 4336 fragS *fragP;
252b5132
RH		 4337#endif
4338{
29b0f896 4339 unsigned char *opcode;
252b5132 4340 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4341 offsetT target_address;
4342 offsetT opcode_address;
252b5132 4343 unsigned int extension = 0;
847f7ad4 4344 offsetT displacement_from_opcode_start;
252b5132
RH		 4345
4346 opcode = (unsigned char *) fragP->fr_opcode;
4347
47926f60 4348 /* Address we want to reach in file space. */
252b5132 4349 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4350
47926f60 4351 /* Address opcode resides at in file space. */
252b5132
RH		 4352 opcode_address = fragP->fr_address + fragP->fr_fix;
4353
47926f60 4354 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4355 displacement_from_opcode_start = target_address - opcode_address;
4356
fddf5b5b 4357 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4358 {
47926f60
KH		 4359 /* Don't have to change opcode. */
4360 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4361 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4362 }
4363 else
4364 {
4365 if (no_cond_jump_promotion
4366 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4367 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4368
fddf5b5b
AM		 4369 switch (fragP->fr_subtype)
4370 {
4371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4372 extension = 4; /* 1 opcode + 4 displacement */
4373 opcode[0] = 0xe9;
4374 where_to_put_displacement = &opcode[1];
4375 break;
252b5132 4376
fddf5b5b
AM		 4377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4378 extension = 2; /* 1 opcode + 2 displacement */
4379 opcode[0] = 0xe9;
4380 where_to_put_displacement = &opcode[1];
4381 break;
252b5132 4382
fddf5b5b
AM		 4383 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4385 extension = 5; /* 2 opcode + 4 displacement */
4386 opcode[1] = opcode[0] + 0x10;
4387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4388 where_to_put_displacement = &opcode[2];
4389 break;
252b5132 4390
fddf5b5b
AM		 4391 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4392 extension = 3; /* 2 opcode + 2 displacement */
4393 opcode[1] = opcode[0] + 0x10;
4394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4395 where_to_put_displacement = &opcode[2];
4396 break;
252b5132 4397
fddf5b5b
AM		 4398 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4399 extension = 4;
4400 opcode[0] ^= 1;
4401 opcode[1] = 3;
4402 opcode[2] = 0xe9;
4403 where_to_put_displacement = &opcode[3];
4404 break;
4405
4406 default:
4407 BAD_CASE (fragP->fr_subtype);
4408 break;
4409 }
252b5132 4410 }
fddf5b5b 4411
47926f60 4412 /* Now put displacement after opcode. */
252b5132
RH		 4413 md_number_to_chars ((char *) where_to_put_displacement,
4414 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4415 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4416 fragP->fr_fix += extension;
4417}
4418\f
47926f60
KH		 4419/* Size of byte displacement jmp. */
4420int md_short_jump_size = 2;
4421
4422/* Size of dword displacement jmp. */
4423int md_long_jump_size = 5;
252b5132 4424
47926f60
KH		 4425/* Size of relocation record. */
4426const int md_reloc_size = 8;
252b5132
RH		 4427
4428void
4429md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4430 char *ptr;
4431 addressT from_addr, to_addr;
ab9da554
ILT		 4432 fragS *frag ATTRIBUTE_UNUSED;
4433 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4434{
847f7ad4 4435 offsetT offset;
252b5132
RH		 4436
4437 offset = to_addr - (from_addr + 2);
47926f60
KH		 4438 /* Opcode for byte-disp jump. */
4439 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4440 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4441}
4442
4443void
4444md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4445 char *ptr;
4446 addressT from_addr, to_addr;
a38cf1db
AM		 4447 fragS *frag ATTRIBUTE_UNUSED;
4448 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4449{
847f7ad4 4450 offsetT offset;
252b5132 4451
a38cf1db
AM		 4452 offset = to_addr - (from_addr + 5);
4453 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4454 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4455}
4456\f
4457/* Apply a fixup (fixS) to segment data, once it has been determined
4458 by our caller that we have all the info we need to fix it up.
4459
4460 On the 386, immediates, displacements, and data pointers are all in
4461 the same (little-endian) format, so we don't need to care about which
4462 we are handling. */
4463
94f592af
NC		 4464void
4465md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4466 /* The fix we're to put in. */
4467 fixS *fixP;
47926f60 4468 /* Pointer to the value of the bits. */
94f592af 4469 valueT * valP;
47926f60
KH		 4470 /* Segment fix is from. */
4471 segT seg ATTRIBUTE_UNUSED;
252b5132 4472{
94f592af
NC		 4473 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4474 valueT value = * valP;
252b5132 4475
e1b283bb 4476#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4477 if (fixP->fx_pcrel)
4478 {
4479 switch (fixP->fx_r_type)
4480 {
5865bb77
ILT		 4481 default:
4482 break;
4483
93382f6d
AM		 4484 case BFD_RELOC_32:
4485 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4486 break;
4487 case BFD_RELOC_16:
4488 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4489 break;
4490 case BFD_RELOC_8:
4491 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4492 break;
4493 }
4494 }
252b5132 4495
0723899b
ILT		 4496 /* This is a hack. There should be a better way to handle this.
4497 This covers for the fact that bfd_install_relocation will
4498 subtract the current location (for partial_inplace, PC relative
4499 relocations); see more below. */
93382f6d
AM		 4500 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4501 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4502 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4503 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4504 {
4505#ifndef OBJ_AOUT
4506 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4507#ifdef TE_PE
4508 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4509#endif
4510 )
4511 value += fixP->fx_where + fixP->fx_frag->fr_address;
4512#endif
4513#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4514 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4515 {
2f66722d
AM		 4516 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4517
4518 if ((fseg == seg
4519 || (symbol_section_p (fixP->fx_addsy)
4520 && fseg != absolute_section))
29b0f896
AM		 4521 && !S_IS_EXTERNAL (fixP->fx_addsy)
4522 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4523 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4524 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4525 {
4526 /* Yes, we add the values in twice. This is because
4527 bfd_perform_relocation subtracts them out again. I think
4528 bfd_perform_relocation is broken, but I don't dare change
4529 it. FIXME. */
4530 value += fixP->fx_where + fixP->fx_frag->fr_address;
4531 }
252b5132
RH		 4532 }
4533#endif
4534#if defined (OBJ_COFF) && defined (TE_PE)
4535 /* For some reason, the PE format does not store a section
24eab124 4536 address offset for a PC relative symbol. */
252b5132
RH		 4537 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4538 value += md_pcrel_from (fixP);
4539#endif
4540 }
4541
4542 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4543 and we must not dissappoint it. */
252b5132
RH		 4544#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4545 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4546 && fixP->fx_addsy)
47926f60
KH		 4547 switch (fixP->fx_r_type)
4548 {
4549 case BFD_RELOC_386_PLT32:
3e73aa7c 4550 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4551 /* Make the jump instruction point to the address of the operand. At
4552 runtime we merely add the offset to the actual PLT entry. */
4553 value = -4;
4554 break;
4555 case BFD_RELOC_386_GOTPC:
4556
4557/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4558 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4559 * here is to obtain the absolute address of the GOT, and it is strongly
4560 * preferable from a performance point of view to avoid using a runtime
c3332e24 4561 * relocation for this. The actual sequence of instructions often look
252b5132 4562 * something like:
c3332e24 4563 *
24eab124 4564 * call .L66
252b5132 4565 * .L66:
24eab124
AM		 4566 * popl %ebx
4567 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4568 *
24eab124 4569 * The call and pop essentially return the absolute address of
252b5132
RH		 4570 * the label .L66 and store it in %ebx. The linker itself will
4571 * ultimately change the first operand of the addl so that %ebx points to
4572 * the GOT, but to keep things simple, the .o file must have this operand
4573 * set so that it generates not the absolute address of .L66, but the
4574 * absolute address of itself. This allows the linker itself simply
4575 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4576 * added in, and the addend of the relocation is stored in the operand
4577 * field for the instruction itself.
c3332e24 4578 *
24eab124 4579 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4580 * offset so that %ebx would point to itself. The thing that is tricky is
4581 * that .-.L66 will point to the beginning of the instruction, so we need
4582 * to further modify the operand so that it will point to itself.
4583 * There are other cases where you have something like:
c3332e24 4584 *
24eab124 4585 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4586 *
252b5132 4587 * and here no correction would be required. Internally in the assembler
c3332e24 4588 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4589 * explicitly mentioned, and I wonder whether it would simplify matters
4590 * to do it this way. Who knows. In earlier versions of the PIC patches,
4591 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4592 * expression is not pcrel, I felt it would be confusing to do it this
4593 * way. */
4594
4595 value -= 1;
4596 break;
4597 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4598 case BFD_RELOC_386_TLS_GD:
4599 case BFD_RELOC_386_TLS_LDM:
4600 case BFD_RELOC_386_TLS_LDO_32:
4601 case BFD_RELOC_386_TLS_IE_32:
4602 case BFD_RELOC_386_TLS_LE_32:
4603 case BFD_RELOC_386_TLS_LE:
3e73aa7c 4604 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4605 value = 0; /* Fully resolved at runtime. No addend. */
4606 break;
4607 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4608 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4609 break;
4610
4611 case BFD_RELOC_VTABLE_INHERIT:
4612 case BFD_RELOC_VTABLE_ENTRY:
4613 fixP->fx_done = 0;
94f592af 4614 return;
47926f60
KH		 4615
4616 default:
4617 break;
4618 }
4619#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
94f592af 4620 * valP = value;
47926f60 4621#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4622
3e73aa7c 4623 /* Are we finished with this relocation now? */
94f592af 4624 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3e73aa7c 4625 fixP->fx_done = 1;
94f592af 4626#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4627 else if (use_rela_relocations)
4628 {
4629 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4630 /* Remember value for tc_gen_reloc. */
4631 fixP->fx_addnumber = value;
3e73aa7c
JH		 4632 value = 0;
4633 }
3e73aa7c 4634#endif
94f592af 4635 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4636}
252b5132 4637\f
252b5132
RH		 4638#define MAX_LITTLENUMS 6
4639
47926f60
KH		 4640/* Turn the string pointed to by litP into a floating point constant
4641 of type TYPE, and emit the appropriate bytes. The number of
4642 LITTLENUMS emitted is stored in *SIZEP. An error message is
4643 returned, or NULL on OK. */
4644
252b5132
RH		 4645char *
4646md_atof (type, litP, sizeP)
2ab9b79e 4647 int type;
252b5132
RH		 4648 char *litP;
4649 int *sizeP;
4650{
4651 int prec;
4652 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4653 LITTLENUM_TYPE *wordP;
4654 char *t;
4655
4656 switch (type)
4657 {
4658 case 'f':
4659 case 'F':
4660 prec = 2;
4661 break;
4662
4663 case 'd':
4664 case 'D':
4665 prec = 4;
4666 break;
4667
4668 case 'x':
4669 case 'X':
4670 prec = 5;
4671 break;
4672
4673 default:
4674 *sizeP = 0;
4675 return _("Bad call to md_atof ()");
4676 }
4677 t = atof_ieee (input_line_pointer, type, words);
4678 if (t)
4679 input_line_pointer = t;
4680
4681 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4682 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4683 the bigendian 386. */
4684 for (wordP = words + prec - 1; prec--;)
4685 {
4686 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4687 litP += sizeof (LITTLENUM_TYPE);
4688 }
4689 return 0;
4690}
4691\f
4692char output_invalid_buf[8];
4693
252b5132
RH		 4694static char *
4695output_invalid (c)
4696 int c;
4697{
3882b010 4698 if (ISPRINT (c))
252b5132
RH		 4699 sprintf (output_invalid_buf, "'%c'", c);
4700 else
4701 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4702 return output_invalid_buf;
4703}
4704
af6bdddf 4705/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4706
4707static const reg_entry *
4708parse_register (reg_string, end_op)
4709 char *reg_string;
4710 char **end_op;
4711{
af6bdddf
AM		 4712 char *s = reg_string;
4713 char *p;
252b5132
RH		 4714 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4715 const reg_entry *r;
4716
4717 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4718 if (*s == REGISTER_PREFIX)
4719 ++s;
4720
4721 if (is_space_char (*s))
4722 ++s;
4723
4724 p = reg_name_given;
af6bdddf 4725 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4726 {
4727 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4728 return (const reg_entry *) NULL;
4729 s++;
252b5132
RH		 4730 }
4731
6588847e
DN		 4732 /* For naked regs, make sure that we are not dealing with an identifier.
4733 This prevents confusing an identifier like `eax_var' with register
4734 `eax'. */
4735 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4736 return (const reg_entry *) NULL;
4737
af6bdddf 4738 *end_op = s;
252b5132
RH		 4739
4740 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4741
5f47d35b 4742 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4743 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4744 {
5f47d35b
AM		 4745 if (is_space_char (*s))
4746 ++s;
4747 if (*s == '(')
4748 {
af6bdddf 4749 ++s;
5f47d35b
AM		 4750 if (is_space_char (*s))
4751 ++s;
4752 if (*s >= '0' && *s <= '7')
4753 {
4754 r = &i386_float_regtab[*s - '0'];
af6bdddf 4755 ++s;
5f47d35b
AM		 4756 if (is_space_char (*s))
4757 ++s;
4758 if (*s == ')')
4759 {
4760 *end_op = s + 1;
4761 return r;
4762 }
5f47d35b 4763 }
47926f60 4764 /* We have "%st(" then garbage. */
5f47d35b
AM		 4765 return (const reg_entry *) NULL;
4766 }
4767 }
4768
1ae00879 4769 if (r != NULL
29b0f896 4770 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4771 && flag_code != CODE_64BIT)
4772 {
4773 return (const reg_entry *) NULL;
4774 }
4775
252b5132
RH		 4776 return r;
4777}
4778\f
4cc782b5 4779#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4780const char *md_shortopts = "kVQ:sq";
252b5132 4781#else
65172ab8 4782const char *md_shortopts = "q";
252b5132 4783#endif
6e0b89ee 4784
252b5132 4785struct option md_longopts[] = {
3e73aa7c
JH		 4786#define OPTION_32 (OPTION_MD_BASE + 0)
4787 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4788#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4789#define OPTION_64 (OPTION_MD_BASE + 1)
4790 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4791#endif
252b5132
RH		 4792 {NULL, no_argument, NULL, 0}
4793};
4794size_t md_longopts_size = sizeof (md_longopts);
4795
4796int
4797md_parse_option (c, arg)
4798 int c;
ab9da554 4799 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4800{
4801 switch (c)
4802 {
a38cf1db
AM		 4803 case 'q':
4804 quiet_warnings = 1;
252b5132
RH		 4805 break;
4806
4807#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4808 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4809 should be emitted or not. FIXME: Not implemented. */
4810 case 'Q':
252b5132
RH		 4811 break;
4812
4813 /* -V: SVR4 argument to print version ID. */
4814 case 'V':
4815 print_version_id ();
4816 break;
4817
a38cf1db
AM		 4818 /* -k: Ignore for FreeBSD compatibility. */
4819 case 'k':
252b5132 4820 break;
4cc782b5
ILT		 4821
4822 case 's':
4823 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4824 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4825 break;
6e0b89ee 4826
3e73aa7c
JH		 4827 case OPTION_64:
4828 {
4829 const char **list, **l;
4830
3e73aa7c
JH		 4831 list = bfd_target_list ();
4832 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4833 if (strcmp (*l, "elf64-x86-64") == 0)
4834 {
4835 default_arch = "x86_64";
4836 break;
4837 }
3e73aa7c 4838 if (*l == NULL)
6e0b89ee 4839 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4840 free (list);
4841 }
4842 break;
4843#endif
252b5132 4844
6e0b89ee
AM		 4845 case OPTION_32:
4846 default_arch = "i386";
4847 break;
4848
252b5132
RH		 4849 default:
4850 return 0;
4851 }
4852 return 1;
4853}
4854
4855void
4856md_show_usage (stream)
4857 FILE *stream;
4858{
4cc782b5
ILT		 4859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4860 fprintf (stream, _("\
a38cf1db
AM		 4861 -Q ignored\n\
4862 -V print assembler version number\n\
4863 -k ignored\n\
4864 -q quieten some warnings\n\
4865 -s ignored\n"));
4866#else
4867 fprintf (stream, _("\
4868 -q quieten some warnings\n"));
4cc782b5 4869#endif
252b5132
RH		 4870}
4871
4872#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4873#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4874 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4875
4876/* Pick the target format to use. */
4877
47926f60 4878const char *
252b5132
RH		 4879i386_target_format ()
4880{
3e73aa7c
JH		 4881 if (!strcmp (default_arch, "x86_64"))
4882 set_code_flag (CODE_64BIT);
4883 else if (!strcmp (default_arch, "i386"))
4884 set_code_flag (CODE_32BIT);
4885 else
4886 as_fatal (_("Unknown architecture"));
252b5132
RH		 4887 switch (OUTPUT_FLAVOR)
4888 {
4c63da97
AM		 4889#ifdef OBJ_MAYBE_AOUT
4890 case bfd_target_aout_flavour:
47926f60 4891 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4892#endif
4893#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4894 case bfd_target_coff_flavour:
4895 return "coff-i386";
4c63da97 4896#endif
3e73aa7c 4897#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4898 case bfd_target_elf_flavour:
3e73aa7c 4899 {
e5cb08ac
KH		 4900 if (flag_code == CODE_64BIT)
4901 use_rela_relocations = 1;
4902 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4903 }
4c63da97 4904#endif
252b5132
RH		 4905 default:
4906 abort ();
4907 return NULL;
4908 }
4909}
4910
47926f60 4911#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4912
4913#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4914void i386_elf_emit_arch_note ()
4915{
4916 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4917 && cpu_arch_name != NULL)
4918 {
4919 char *p;
4920 asection *seg = now_seg;
4921 subsegT subseg = now_subseg;
4922 Elf_Internal_Note i_note;
4923 Elf_External_Note e_note;
4924 asection *note_secp;
4925 int len;
4926
4927 /* Create the .note section. */
4928 note_secp = subseg_new (".note", 0);
4929 bfd_set_section_flags (stdoutput,
4930 note_secp,
4931 SEC_HAS_CONTENTS | SEC_READONLY);
4932
4933 /* Process the arch string. */
4934 len = strlen (cpu_arch_name);
4935
4936 i_note.namesz = len + 1;
4937 i_note.descsz = 0;
4938 i_note.type = NT_ARCH;
4939 p = frag_more (sizeof (e_note.namesz));
4940 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4941 p = frag_more (sizeof (e_note.descsz));
4942 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4943 p = frag_more (sizeof (e_note.type));
4944 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4945 p = frag_more (len + 1);
4946 strcpy (p, cpu_arch_name);
4947
4948 frag_align (2, 0, 0);
4949
4950 subseg_set (seg, subseg);
4951 }
4952}
4953#endif
47926f60 4954#endif /* BFD_ASSEMBLER */
252b5132 4955\f
252b5132
RH		 4956symbolS *
4957md_undefined_symbol (name)
4958 char *name;
4959{
18dc2407
ILT		 4960 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4961 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4962 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4963 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4964 {
4965 if (!GOT_symbol)
4966 {
4967 if (symbol_find (name))
4968 as_bad (_("GOT already in symbol table"));
4969 GOT_symbol = symbol_new (name, undefined_section,
4970 (valueT) 0, &zero_address_frag);
4971 };
4972 return GOT_symbol;
4973 }
252b5132
RH		 4974 return 0;
4975}
4976
4977/* Round up a section size to the appropriate boundary. */
47926f60 4978
252b5132
RH		 4979valueT
4980md_section_align (segment, size)
ab9da554 4981 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4982 valueT size;
4983{
252b5132 4984#ifdef BFD_ASSEMBLER
4c63da97
AM		 4985#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4986 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4987 {
4988 /* For a.out, force the section size to be aligned. If we don't do
4989 this, BFD will align it for us, but it will not write out the
4990 final bytes of the section. This may be a bug in BFD, but it is
4991 easier to fix it here since that is how the other a.out targets
4992 work. */
4993 int align;
4994
4995 align = bfd_get_section_alignment (stdoutput, segment);
4996 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4997 }
252b5132
RH		 4998#endif
4999#endif
5000
5001 return size;
5002}
5003
5004/* On the i386, PC-relative offsets are relative to the start of the
5005 next instruction. That is, the address of the offset, plus its
5006 size, since the offset is always the last part of the insn. */
5007
5008long
5009md_pcrel_from (fixP)
5010 fixS *fixP;
5011{
5012 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5013}
5014
5015#ifndef I386COFF
5016
5017static void
5018s_bss (ignore)
ab9da554 5019 int ignore ATTRIBUTE_UNUSED;
252b5132 5020{
29b0f896 5021 int temp;
252b5132
RH		 5022
5023 temp = get_absolute_expression ();
5024 subseg_set (bss_section, (subsegT) temp);
5025 demand_empty_rest_of_line ();
5026}
5027
5028#endif
5029
252b5132
RH		 5030#ifdef BFD_ASSEMBLER
5031
5032void
5033i386_validate_fix (fixp)
5034 fixS *fixp;
5035{
5036 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5037 {
3e73aa7c 5038 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5039 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5040 {
5041 if (flag_code != CODE_64BIT)
5042 abort ();
5043 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5044 }
5045 else
5046 {
5047 if (flag_code == CODE_64BIT)
5048 abort ();
5049 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5050 }
252b5132
RH		 5051 fixp->fx_subsy = 0;
5052 }
5053}
5054
252b5132
RH		 5055arelent *
5056tc_gen_reloc (section, fixp)
ab9da554 5057 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5058 fixS *fixp;
5059{
5060 arelent *rel;
5061 bfd_reloc_code_real_type code;
5062
5063 switch (fixp->fx_r_type)
5064 {
3e73aa7c
JH		 5065 case BFD_RELOC_X86_64_PLT32:
5066 case BFD_RELOC_X86_64_GOT32:
5067 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5068 case BFD_RELOC_386_PLT32:
5069 case BFD_RELOC_386_GOT32:
5070 case BFD_RELOC_386_GOTOFF:
5071 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5072 case BFD_RELOC_386_TLS_GD:
5073 case BFD_RELOC_386_TLS_LDM:
5074 case BFD_RELOC_386_TLS_LDO_32:
5075 case BFD_RELOC_386_TLS_IE_32:
5076 case BFD_RELOC_386_TLS_LE_32:
5077 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5078 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5079 case BFD_RELOC_RVA:
5080 case BFD_RELOC_VTABLE_ENTRY:
5081 case BFD_RELOC_VTABLE_INHERIT:
5082 code = fixp->fx_r_type;
5083 break;
5084 default:
93382f6d 5085 if (fixp->fx_pcrel)
252b5132 5086 {
93382f6d
AM		 5087 switch (fixp->fx_size)
5088 {
5089 default:
b091f402
AM		 5090 as_bad_where (fixp->fx_file, fixp->fx_line,
5091 _("can not do %d byte pc-relative relocation"),
5092 fixp->fx_size);
93382f6d
AM		 5093 code = BFD_RELOC_32_PCREL;
5094 break;
5095 case 1: code = BFD_RELOC_8_PCREL; break;
5096 case 2: code = BFD_RELOC_16_PCREL; break;
5097 case 4: code = BFD_RELOC_32_PCREL; break;
5098 }
5099 }
5100 else
5101 {
5102 switch (fixp->fx_size)
5103 {
5104 default:
b091f402
AM		 5105 as_bad_where (fixp->fx_file, fixp->fx_line,
5106 _("can not do %d byte relocation"),
5107 fixp->fx_size);
93382f6d
AM		 5108 code = BFD_RELOC_32;
5109 break;
5110 case 1: code = BFD_RELOC_8; break;
5111 case 2: code = BFD_RELOC_16; break;
5112 case 4: code = BFD_RELOC_32; break;
937149dd 5113#ifdef BFD64
3e73aa7c 5114 case 8: code = BFD_RELOC_64; break;
937149dd 5115#endif
93382f6d 5116 }
252b5132
RH		 5117 }
5118 break;
5119 }
252b5132
RH		 5120
5121 if (code == BFD_RELOC_32
5122 && GOT_symbol
5123 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5124 {
5125 /* We don't support GOTPC on 64bit targets. */
5126 if (flag_code == CODE_64BIT)
bfb32b52 5127 abort ();
3e73aa7c
JH		 5128 code = BFD_RELOC_386_GOTPC;
5129 }
252b5132
RH		 5130
5131 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5132 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5133 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5134
5135 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5136 if (!use_rela_relocations)
5137 {
5138 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5139 vtable entry to be used in the relocation's section offset. */
5140 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5141 rel->address = fixp->fx_offset;
252b5132 5142
3e73aa7c
JH		 5143 if (fixp->fx_pcrel)
5144 rel->addend = fixp->fx_addnumber;
5145 else
5146 rel->addend = 0;
5147 }
5148 /* Use the rela in 64bit mode. */
252b5132 5149 else
3e73aa7c 5150 {
062cd5e7
AS		 5151 if (!fixp->fx_pcrel)
5152 rel->addend = fixp->fx_offset;
5153 else
5154 switch (code)
5155 {
5156 case BFD_RELOC_X86_64_PLT32:
5157 case BFD_RELOC_X86_64_GOT32:
5158 case BFD_RELOC_X86_64_GOTPCREL:
5159 rel->addend = fixp->fx_offset - fixp->fx_size;
5160 break;
5161 default:
5162 rel->addend = (section->vma
5163 - fixp->fx_size
5164 + fixp->fx_addnumber
5165 + md_pcrel_from (fixp));
5166 break;
5167 }
3e73aa7c
JH		 5168 }
5169
252b5132
RH		 5170 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5171 if (rel->howto == NULL)
5172 {
5173 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5174 _("cannot represent relocation type %s"),
252b5132
RH		 5175 bfd_get_reloc_code_name (code));
5176 /* Set howto to a garbage value so that we can keep going. */
5177 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5178 assert (rel->howto != NULL);
5179 }
5180
5181 return rel;
5182}
5183
29b0f896 5184#else /* !BFD_ASSEMBLER */
252b5132
RH		 5185
5186#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5187void
5188tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5189 char *where;
5190 fixS *fixP;
5191 relax_addressT segment_address_in_file;
5192{
47926f60
KH		 5193 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5194 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5195
47926f60 5196 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5197 long r_symbolnum;
5198
5199 know (fixP->fx_addsy != NULL);
5200
5201 md_number_to_chars (where,
5202 (valueT) (fixP->fx_frag->fr_address
5203 + fixP->fx_where - segment_address_in_file),
5204 4);
5205
5206 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5207 ? S_GET_TYPE (fixP->fx_addsy)
5208 : fixP->fx_addsy->sy_number);
5209
5210 where[6] = (r_symbolnum >> 16) & 0x0ff;
5211 where[5] = (r_symbolnum >> 8) & 0x0ff;
5212 where[4] = r_symbolnum & 0x0ff;
5213 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5214 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5215 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5216}
5217
47926f60 5218#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5219
5220#if defined (I386COFF)
5221
5222short
5223tc_coff_fix2rtype (fixP)
5224 fixS *fixP;
5225{
5226 if (fixP->fx_r_type == R_IMAGEBASE)
5227 return R_IMAGEBASE;
5228
5229 return (fixP->fx_pcrel ?
5230 (fixP->fx_size == 1 ? R_PCRBYTE :
5231 fixP->fx_size == 2 ? R_PCRWORD :
5232 R_PCRLONG) :
5233 (fixP->fx_size == 1 ? R_RELBYTE :
5234 fixP->fx_size == 2 ? R_RELWORD :
5235 R_DIR32));
5236}
5237
5238int
5239tc_coff_sizemachdep (frag)
5240 fragS *frag;
5241{
5242 if (frag->fr_next)
5243 return (frag->fr_next->fr_address - frag->fr_address);
5244 else
5245 return 0;
5246}
5247
47926f60 5248#endif /* I386COFF */
252b5132 5249
29b0f896 5250#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5251\f
5252/* Parse operands using Intel syntax. This implements a recursive descent
5253 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5254 Programmer's Guide.
5255
5256 FIXME: We do not recognize the full operand grammar defined in the MASM
5257 documentation. In particular, all the structure/union and
5258 high-level macro operands are missing.
5259
5260 Uppercase words are terminals, lower case words are non-terminals.
5261 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5262 bars '|' denote choices. Most grammar productions are implemented in
5263 functions called 'intel_<production>'.
5264
5265 Initial production is 'expr'.
5266
64a0c779
DN		 5267 addOp + | -
5268
5269 alpha [a-zA-Z]
5270
5271 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5272
5273 constant digits [[ radixOverride ]]
5274
5275 dataType BYTE | WORD | DWORD | QWORD | XWORD
5276
5277 digits decdigit
b77a7acd
AJ		 5278 | digits decdigit
5279 | digits hexdigit
64a0c779
DN		 5280
5281 decdigit [0-9]
5282
5283 e05 e05 addOp e06
b77a7acd 5284 | e06
64a0c779
DN		 5285
5286 e06 e06 mulOp e09
b77a7acd 5287 | e09
64a0c779
DN		 5288
5289 e09 OFFSET e10
5290 | e09 PTR e10
5291 | e09 : e10
5292 | e10
5293
5294 e10 e10 [ expr ]
b77a7acd 5295 | e11
64a0c779
DN		 5296
5297 e11 ( expr )
b77a7acd 5298 | [ expr ]
64a0c779
DN		 5299 | constant
5300 | dataType
5301 | id
5302 | $
5303 | register
5304
5305 => expr SHORT e05
b77a7acd 5306 | e05
64a0c779
DN		 5307
5308 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5309 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5310
5311 hexdigit a | b | c | d | e | f
b77a7acd 5312 | A | B | C | D | E | F
64a0c779
DN		 5313
5314 id alpha
b77a7acd 5315 | id alpha
64a0c779
DN		 5316 | id decdigit
5317
5318 mulOp * | / | MOD
5319
5320 quote " | '
5321
5322 register specialRegister
b77a7acd 5323 | gpRegister
64a0c779
DN		 5324 | byteRegister
5325
5326 segmentRegister CS | DS | ES | FS | GS | SS
5327
5328 specialRegister CR0 | CR2 | CR3
b77a7acd 5329 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5330 | TR3 | TR4 | TR5 | TR6 | TR7
5331
64a0c779
DN		 5332 We simplify the grammar in obvious places (e.g., register parsing is
5333 done by calling parse_register) and eliminate immediate left recursion
5334 to implement a recursive-descent parser.
5335
5336 expr SHORT e05
b77a7acd 5337 | e05
64a0c779
DN		 5338
5339 e05 e06 e05'
5340
5341 e05' addOp e06 e05'
b77a7acd 5342 | Empty
64a0c779
DN		 5343
5344 e06 e09 e06'
5345
5346 e06' mulOp e09 e06'
b77a7acd 5347 | Empty
64a0c779
DN		 5348
5349 e09 OFFSET e10 e09'
b77a7acd 5350 | e10 e09'
64a0c779
DN		 5351
5352 e09' PTR e10 e09'
b77a7acd 5353 | : e10 e09'
64a0c779
DN		 5354 | Empty
5355
5356 e10 e11 e10'
5357
5358 e10' [ expr ] e10'
b77a7acd 5359 | Empty
64a0c779
DN		 5360
5361 e11 ( expr )
b77a7acd 5362 | [ expr ]
64a0c779
DN		 5363 | BYTE
5364 | WORD
5365 | DWORD
5366 | QWORD
5367 | XWORD
5368 | .
5369 | $
5370 | register
5371 | id
5372 | constant */
5373
5374/* Parsing structure for the intel syntax parser. Used to implement the
5375 semantic actions for the operand grammar. */
5376struct intel_parser_s
5377 {
5378 char *op_string; /* The string being parsed. */
5379 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5380 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5381 int is_mem; /* 1 if operand is memory reference. */
5382 const reg_entry *reg; /* Last register reference found. */
5383 char *disp; /* Displacement string being built. */
5384 };
5385
5386static struct intel_parser_s intel_parser;
5387
5388/* Token structure for parsing intel syntax. */
5389struct intel_token
5390 {
5391 int code; /* Token code. */
5392 const reg_entry *reg; /* Register entry for register tokens. */
5393 char *str; /* String representation. */
5394 };
5395
5396static struct intel_token cur_token, prev_token;
5397
50705ef4
AM		 5398/* Token codes for the intel parser. Since T_SHORT is already used
5399 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5400#define T_NIL -1
5401#define T_CONST 1
5402#define T_REG 2
5403#define T_BYTE 3
5404#define T_WORD 4
5405#define T_DWORD 5
5406#define T_QWORD 6
5407#define T_XWORD 7
50705ef4 5408#undef T_SHORT
64a0c779
DN		 5409#define T_SHORT 8
5410#define T_OFFSET 9
5411#define T_PTR 10
5412#define T_ID 11
5413
5414/* Prototypes for intel parser functions. */
5415static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5416static void intel_get_token PARAMS ((void));
5417static void intel_putback_token PARAMS ((void));
5418static int intel_expr PARAMS ((void));
5419static int intel_e05 PARAMS ((void));
5420static int intel_e05_1 PARAMS ((void));
5421static int intel_e06 PARAMS ((void));
5422static int intel_e06_1 PARAMS ((void));
5423static int intel_e09 PARAMS ((void));
5424static int intel_e09_1 PARAMS ((void));
5425static int intel_e10 PARAMS ((void));
5426static int intel_e10_1 PARAMS ((void));
5427static int intel_e11 PARAMS ((void));
64a0c779 5428
64a0c779
DN		 5429static int
5430i386_intel_operand (operand_string, got_a_float)
5431 char *operand_string;
5432 int got_a_float;
5433{
5434 int ret;
5435 char *p;
5436
5437 /* Initialize token holders. */
5438 cur_token.code = prev_token.code = T_NIL;
5439 cur_token.reg = prev_token.reg = NULL;
5440 cur_token.str = prev_token.str = NULL;
5441
5442 /* Initialize parser structure. */
e5cb08ac 5443 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5444 if (p == NULL)
5445 abort ();
5446 strcpy (intel_parser.op_string, operand_string);
5447 intel_parser.got_a_float = got_a_float;
5448 intel_parser.op_modifier = -1;
5449 intel_parser.is_mem = 0;
5450 intel_parser.reg = NULL;
e5cb08ac 5451 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5452 if (intel_parser.disp == NULL)
5453 abort ();
5454 intel_parser.disp[0] = '\0';
5455
5456 /* Read the first token and start the parser. */
5457 intel_get_token ();
5458 ret = intel_expr ();
5459
5460 if (ret)
5461 {
5462 /* If we found a memory reference, hand it over to i386_displacement
5463 to fill in the rest of the operand fields. */
5464 if (intel_parser.is_mem)
5465 {
5466 if ((i.mem_operands == 1
5467 && (current_templates->start->opcode_modifier & IsString) == 0)
5468 || i.mem_operands == 2)
5469 {
5470 as_bad (_("too many memory references for '%s'"),
5471 current_templates->start->name);
5472 ret = 0;
5473 }
5474 else
5475 {
5476 char *s = intel_parser.disp;
5477 i.mem_operands++;
5478
5479 /* Add the displacement expression. */
5480 if (*s != '\0')
5481 ret = i386_displacement (s, s + strlen (s))
5482 && i386_index_check (s);
5483 }
5484 }
5485
5486 /* Constant and OFFSET expressions are handled by i386_immediate. */
5487 else if (intel_parser.op_modifier == OFFSET_FLAT
5488 || intel_parser.reg == NULL)
5489 ret = i386_immediate (intel_parser.disp);
5490 }
5491
5492 free (p);
5493 free (intel_parser.disp);
5494
5495 return ret;
5496}
5497
64a0c779 5498/* expr SHORT e05
b77a7acd 5499 | e05 */
64a0c779
DN		 5500static int
5501intel_expr ()
5502{
5503 /* expr SHORT e05 */
5504 if (cur_token.code == T_SHORT)
5505 {
5506 intel_parser.op_modifier = SHORT;
5507 intel_match_token (T_SHORT);
5508
5509 return (intel_e05 ());
5510 }
5511
5512 /* expr e05 */
5513 else
5514 return intel_e05 ();
5515}
5516
64a0c779
DN		 5517/* e05 e06 e05'
5518
4a1805b1 5519 e05' addOp e06 e05'
64a0c779
DN		 5520 | Empty */
5521static int
5522intel_e05 ()
5523{
5524 return (intel_e06 () && intel_e05_1 ());
5525}
5526
5527static int
5528intel_e05_1 ()
5529{
5530 /* e05' addOp e06 e05' */
5531 if (cur_token.code == '+' || cur_token.code == '-')
5532 {
5533 strcat (intel_parser.disp, cur_token.str);
5534 intel_match_token (cur_token.code);
5535
5536 return (intel_e06 () && intel_e05_1 ());
5537 }
5538
5539 /* e05' Empty */
5540 else
5541 return 1;
4a1805b1 5542}
64a0c779
DN		 5543
5544/* e06 e09 e06'
5545
5546 e06' mulOp e09 e06'
b77a7acd 5547 | Empty */
64a0c779
DN		 5548static int
5549intel_e06 ()
5550{
5551 return (intel_e09 () && intel_e06_1 ());
5552}
5553
5554static int
5555intel_e06_1 ()
5556{
5557 /* e06' mulOp e09 e06' */
5558 if (cur_token.code == '*' || cur_token.code == '/')
5559 {
5560 strcat (intel_parser.disp, cur_token.str);
5561 intel_match_token (cur_token.code);
5562
5563 return (intel_e09 () && intel_e06_1 ());
5564 }
4a1805b1 5565
64a0c779 5566 /* e06' Empty */
4a1805b1 5567 else
64a0c779
DN		 5568 return 1;
5569}
5570
64a0c779 5571/* e09 OFFSET e10 e09'
b77a7acd 5572 | e10 e09'
64a0c779
DN		 5573
5574 e09' PTR e10 e09'
b77a7acd 5575 | : e10 e09'
64a0c779
DN		 5576 | Empty */
5577static int
5578intel_e09 ()
5579{
5580 /* e09 OFFSET e10 e09' */
5581 if (cur_token.code == T_OFFSET)
5582 {
5583 intel_parser.is_mem = 0;
5584 intel_parser.op_modifier = OFFSET_FLAT;
5585 intel_match_token (T_OFFSET);
5586
5587 return (intel_e10 () && intel_e09_1 ());
5588 }
5589
5590 /* e09 e10 e09' */
5591 else
5592 return (intel_e10 () && intel_e09_1 ());
5593}
5594
5595static int
5596intel_e09_1 ()
5597{
5598 /* e09' PTR e10 e09' */
5599 if (cur_token.code == T_PTR)
5600 {
5601 if (prev_token.code == T_BYTE)
5602 i.suffix = BYTE_MNEM_SUFFIX;
5603
5604 else if (prev_token.code == T_WORD)
5605 {
5606 if (intel_parser.got_a_float == 2) /* "fi..." */
5607 i.suffix = SHORT_MNEM_SUFFIX;
5608 else
5609 i.suffix = WORD_MNEM_SUFFIX;
5610 }
5611
5612 else if (prev_token.code == T_DWORD)
5613 {
5614 if (intel_parser.got_a_float == 1) /* "f..." */
5615 i.suffix = SHORT_MNEM_SUFFIX;
5616 else
5617 i.suffix = LONG_MNEM_SUFFIX;
5618 }
5619
5620 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5621 {
5622 if (intel_parser.got_a_float == 1) /* "f..." */
5623 i.suffix = LONG_MNEM_SUFFIX;
5624 else
3e73aa7c 5625 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5626 }
64a0c779
DN		 5627
5628 else if (prev_token.code == T_XWORD)
5629 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5630
5631 else
5632 {
5633 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5634 return 0;
5635 }
5636
5637 intel_match_token (T_PTR);
5638
5639 return (intel_e10 () && intel_e09_1 ());
5640 }
5641
5642 /* e09 : e10 e09' */
5643 else if (cur_token.code == ':')
5644 {
21d6c4af
DN		 5645 /* Mark as a memory operand only if it's not already known to be an
5646 offset expression. */
5647 if (intel_parser.op_modifier != OFFSET_FLAT)
5648 intel_parser.is_mem = 1;
64a0c779
DN		 5649
5650 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5651 }
5652
5653 /* e09' Empty */
5654 else
5655 return 1;
5656}
5657
5658/* e10 e11 e10'
5659
5660 e10' [ expr ] e10'
b77a7acd 5661 | Empty */
64a0c779
DN		 5662static int
5663intel_e10 ()
5664{
5665 return (intel_e11 () && intel_e10_1 ());
5666}
5667
5668static int
5669intel_e10_1 ()
5670{
5671 /* e10' [ expr ] e10' */
5672 if (cur_token.code == '[')
5673 {
5674 intel_match_token ('[');
21d6c4af
DN		 5675
5676 /* Mark as a memory operand only if it's not already known to be an
5677 offset expression. If it's an offset expression, we need to keep
5678 the brace in. */
5679 if (intel_parser.op_modifier != OFFSET_FLAT)
5680 intel_parser.is_mem = 1;
5681 else
5682 strcat (intel_parser.disp, "[");
4a1805b1 5683
64a0c779 5684 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5685 if (*intel_parser.disp != '\0'
5686 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5687 strcat (intel_parser.disp, "+");
5688
21d6c4af
DN		 5689 if (intel_expr () && intel_match_token (']'))
5690 {
5691 /* Preserve brackets when the operand is an offset expression. */
5692 if (intel_parser.op_modifier == OFFSET_FLAT)
5693 strcat (intel_parser.disp, "]");
5694
5695 return intel_e10_1 ();
5696 }
5697 else
5698 return 0;
64a0c779
DN		 5699 }
5700
5701 /* e10' Empty */
5702 else
5703 return 1;
5704}
5705
64a0c779 5706/* e11 ( expr )
b77a7acd 5707 | [ expr ]
64a0c779
DN		 5708 | BYTE
5709 | WORD
5710 | DWORD
5711 | QWORD
5712 | XWORD
4a1805b1 5713 | $
64a0c779
DN		 5714 | .
5715 | register
5716 | id
5717 | constant */
5718static int
5719intel_e11 ()
5720{
5721 /* e11 ( expr ) */
5722 if (cur_token.code == '(')
5723 {
5724 intel_match_token ('(');
5725 strcat (intel_parser.disp, "(");
5726
5727 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5728 {
5729 strcat (intel_parser.disp, ")");
5730 return 1;
5731 }
64a0c779
DN		 5732 else
5733 return 0;
5734 }
5735
5736 /* e11 [ expr ] */
5737 else if (cur_token.code == '[')
5738 {
5739 intel_match_token ('[');
21d6c4af
DN		 5740
5741 /* Mark as a memory operand only if it's not already known to be an
5742 offset expression. If it's an offset expression, we need to keep
5743 the brace in. */
5744 if (intel_parser.op_modifier != OFFSET_FLAT)
5745 intel_parser.is_mem = 1;
5746 else
5747 strcat (intel_parser.disp, "[");
4a1805b1 5748
64a0c779
DN		 5749 /* Operands for jump/call inside brackets denote absolute addresses. */
5750 if (current_templates->start->opcode_modifier & Jump
5751 || current_templates->start->opcode_modifier & JumpDword
5752 || current_templates->start->opcode_modifier & JumpByte
5753 || current_templates->start->opcode_modifier & JumpInterSegment)
5754 i.types[this_operand] |= JumpAbsolute;
5755
5756 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5757 if (*intel_parser.disp != '\0'
5758 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5759 strcat (intel_parser.disp, "+");
5760
21d6c4af
DN		 5761 if (intel_expr () && intel_match_token (']'))
5762 {
5763 /* Preserve brackets when the operand is an offset expression. */
5764 if (intel_parser.op_modifier == OFFSET_FLAT)
5765 strcat (intel_parser.disp, "]");
5766
5767 return 1;
5768 }
5769 else
5770 return 0;
64a0c779
DN		 5771 }
5772
4a1805b1 5773 /* e11 BYTE
64a0c779
DN		 5774 | WORD
5775 | DWORD
5776 | QWORD
5777 | XWORD */
5778 else if (cur_token.code == T_BYTE
5779 || cur_token.code == T_WORD
5780 || cur_token.code == T_DWORD
5781 || cur_token.code == T_QWORD
5782 || cur_token.code == T_XWORD)
5783 {
5784 intel_match_token (cur_token.code);
5785
5786 return 1;
5787 }
5788
5789 /* e11 $
5790 | . */
5791 else if (cur_token.code == '$' || cur_token.code == '.')
5792 {
5793 strcat (intel_parser.disp, cur_token.str);
5794 intel_match_token (cur_token.code);
21d6c4af
DN		 5795
5796 /* Mark as a memory operand only if it's not already known to be an
5797 offset expression. */
5798 if (intel_parser.op_modifier != OFFSET_FLAT)
5799 intel_parser.is_mem = 1;
64a0c779
DN		 5800
5801 return 1;
5802 }
5803
5804 /* e11 register */
5805 else if (cur_token.code == T_REG)
5806 {
5807 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5808
5809 intel_match_token (T_REG);
5810
5811 /* Check for segment change. */
5812 if (cur_token.code == ':')
5813 {
5814 if (reg->reg_type & (SReg2 | SReg3))
5815 {
5816 switch (reg->reg_num)
5817 {
5818 case 0:
5819 i.seg[i.mem_operands] = &es;
5820 break;
5821 case 1:
5822 i.seg[i.mem_operands] = &cs;
5823 break;
5824 case 2:
5825 i.seg[i.mem_operands] = &ss;
5826 break;
5827 case 3:
5828 i.seg[i.mem_operands] = &ds;
5829 break;
5830 case 4:
5831 i.seg[i.mem_operands] = &fs;
5832 break;
5833 case 5:
5834 i.seg[i.mem_operands] = &gs;
5835 break;
5836 }
5837 }
5838 else
5839 {
5840 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5841 return 0;
5842 }
5843 }
5844
5845 /* Not a segment register. Check for register scaling. */
5846 else if (cur_token.code == '*')
5847 {
5848 if (!intel_parser.is_mem)
5849 {
5850 as_bad (_("Register scaling only allowed in memory operands."));
5851 return 0;
5852 }
5853
4a1805b1 5854 /* What follows must be a valid scale. */
64a0c779
DN		 5855 if (intel_match_token ('*')
5856 && strchr ("01248", *cur_token.str))
5857 {
5858 i.index_reg = reg;
5859 i.types[this_operand] |= BaseIndex;
5860
5861 /* Set the scale after setting the register (otherwise,
5862 i386_scale will complain) */
5863 i386_scale (cur_token.str);
5864 intel_match_token (T_CONST);
5865 }
5866 else
5867 {
5868 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5869 cur_token.str);
5870 return 0;
5871 }
5872 }
5873
5874 /* No scaling. If this is a memory operand, the register is either a
5875 base register (first occurrence) or an index register (second
5876 occurrence). */
5877 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5878 {
5879 if (i.base_reg && i.index_reg)
5880 {
5881 as_bad (_("Too many register references in memory operand.\n"));
5882 return 0;
5883 }
5884
5885 if (i.base_reg == NULL)
5886 i.base_reg = reg;
5887 else
5888 i.index_reg = reg;
5889
5890 i.types[this_operand] |= BaseIndex;
5891 }
5892
5893 /* Offset modifier. Add the register to the displacement string to be
5894 parsed as an immediate expression after we're done. */
5895 else if (intel_parser.op_modifier == OFFSET_FLAT)
5896 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5897
64a0c779
DN		 5898 /* It's neither base nor index nor offset. */
5899 else
5900 {
5901 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5902 i.op[this_operand].regs = reg;
5903 i.reg_operands++;
5904 }
5905
5906 /* Since registers are not part of the displacement string (except
5907 when we're parsing offset operands), we may need to remove any
5908 preceding '+' from the displacement string. */
5909 if (*intel_parser.disp != '\0'
5910 && intel_parser.op_modifier != OFFSET_FLAT)
5911 {
5912 char *s = intel_parser.disp;
5913 s += strlen (s) - 1;
5914 if (*s == '+')
5915 *s = '\0';
5916 }
5917
5918 return 1;
5919 }
4a1805b1 5920
64a0c779
DN		 5921 /* e11 id */
5922 else if (cur_token.code == T_ID)
5923 {
5924 /* Add the identifier to the displacement string. */
5925 strcat (intel_parser.disp, cur_token.str);
5926 intel_match_token (T_ID);
5927
5928 /* The identifier represents a memory reference only if it's not
5929 preceded by an offset modifier. */
21d6c4af 5930 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5931 intel_parser.is_mem = 1;
5932
5933 return 1;
5934 }
5935
5936 /* e11 constant */
5937 else if (cur_token.code == T_CONST
e5cb08ac 5938 || cur_token.code == '-'
64a0c779
DN		 5939 || cur_token.code == '+')
5940 {
5941 char *save_str;
5942
5943 /* Allow constants that start with `+' or `-'. */
5944 if (cur_token.code == '-' || cur_token.code == '+')
5945 {
5946 strcat (intel_parser.disp, cur_token.str);
5947 intel_match_token (cur_token.code);
5948 if (cur_token.code != T_CONST)
5949 {
5950 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5951 cur_token.str);
5952 return 0;
5953 }
5954 }
5955
e5cb08ac 5956 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5957 if (save_str == NULL)
bc805888 5958 abort ();
64a0c779
DN		 5959 strcpy (save_str, cur_token.str);
5960
5961 /* Get the next token to check for register scaling. */
5962 intel_match_token (cur_token.code);
5963
5964 /* Check if this constant is a scaling factor for an index register. */
5965 if (cur_token.code == '*')
5966 {
5967 if (intel_match_token ('*') && cur_token.code == T_REG)
5968 {
5969 if (!intel_parser.is_mem)
5970 {
5971 as_bad (_("Register scaling only allowed in memory operands."));
5972 return 0;
5973 }
5974
4a1805b1 5975 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5976 a valid scale. */
5977 if (strchr ("01248", *save_str))
5978 {
5979 i.index_reg = cur_token.reg;
5980 i.types[this_operand] |= BaseIndex;
5981
5982 /* Set the scale after setting the register (otherwise,
5983 i386_scale will complain) */
5984 i386_scale (save_str);
5985 intel_match_token (T_REG);
5986
5987 /* Since registers are not part of the displacement
5988 string, we may need to remove any preceding '+' from
5989 the displacement string. */
5990 if (*intel_parser.disp != '\0')
5991 {
5992 char *s = intel_parser.disp;
5993 s += strlen (s) - 1;
5994 if (*s == '+')
5995 *s = '\0';
5996 }
5997
5998 free (save_str);
5999
6000 return 1;
6001 }
6002 else
6003 return 0;
6004 }
6005
6006 /* The constant was not used for register scaling. Since we have
6007 already consumed the token following `*' we now need to put it
6008 back in the stream. */
6009 else
6010 intel_putback_token ();
6011 }
6012
6013 /* Add the constant to the displacement string. */
6014 strcat (intel_parser.disp, save_str);
6015 free (save_str);
6016
6017 return 1;
6018 }
6019
64a0c779
DN		 6020 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6021 return 0;
6022}
6023
64a0c779
DN		 6024/* Match the given token against cur_token. If they match, read the next
6025 token from the operand string. */
6026static int
6027intel_match_token (code)
e5cb08ac 6028 int code;
64a0c779
DN		 6029{
6030 if (cur_token.code == code)
6031 {
6032 intel_get_token ();
6033 return 1;
6034 }
6035 else
6036 {
6037 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6038 return 0;
6039 }
6040}
6041
64a0c779
DN		 6042/* Read a new token from intel_parser.op_string and store it in cur_token. */
6043static void
6044intel_get_token ()
6045{
6046 char *end_op;
6047 const reg_entry *reg;
6048 struct intel_token new_token;
6049
6050 new_token.code = T_NIL;
6051 new_token.reg = NULL;
6052 new_token.str = NULL;
6053
4a1805b1 6054 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6055 cur_token to prev_token. */
6056 if (prev_token.str)
6057 free (prev_token.str);
6058
6059 prev_token = cur_token;
6060
6061 /* Skip whitespace. */
6062 while (is_space_char (*intel_parser.op_string))
6063 intel_parser.op_string++;
6064
6065 /* Return an empty token if we find nothing else on the line. */
6066 if (*intel_parser.op_string == '\0')
6067 {
6068 cur_token = new_token;
6069 return;
6070 }
6071
6072 /* The new token cannot be larger than the remainder of the operand
6073 string. */
e5cb08ac 6074 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6075 if (new_token.str == NULL)
bc805888 6076 abort ();
64a0c779
DN		 6077 new_token.str[0] = '\0';
6078
6079 if (strchr ("0123456789", *intel_parser.op_string))
6080 {
6081 char *p = new_token.str;
6082 char *q = intel_parser.op_string;
6083 new_token.code = T_CONST;
6084
6085 /* Allow any kind of identifier char to encompass floating point and
6086 hexadecimal numbers. */
6087 while (is_identifier_char (*q))
6088 *p++ = *q++;
6089 *p = '\0';
6090
6091 /* Recognize special symbol names [0-9][bf]. */
6092 if (strlen (intel_parser.op_string) == 2
4a1805b1 6093 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6094 || intel_parser.op_string[1] == 'f'))
6095 new_token.code = T_ID;
6096 }
6097
6098 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6099 {
6100 new_token.code = *intel_parser.op_string;
6101 new_token.str[0] = *intel_parser.op_string;
6102 new_token.str[1] = '\0';
6103 }
6104
6105 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6106 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6107 {
6108 new_token.code = T_REG;
6109 new_token.reg = reg;
6110
6111 if (*intel_parser.op_string == REGISTER_PREFIX)
6112 {
6113 new_token.str[0] = REGISTER_PREFIX;
6114 new_token.str[1] = '\0';
6115 }
6116
6117 strcat (new_token.str, reg->reg_name);
6118 }
6119
6120 else if (is_identifier_char (*intel_parser.op_string))
6121 {
6122 char *p = new_token.str;
6123 char *q = intel_parser.op_string;
6124
6125 /* A '.' or '$' followed by an identifier char is an identifier.
6126 Otherwise, it's operator '.' followed by an expression. */
6127 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6128 {
6129 new_token.code = *q;
6130 new_token.str[0] = *q;
6131 new_token.str[1] = '\0';
6132 }
6133 else
6134 {
6135 while (is_identifier_char (*q) || *q == '@')
6136 *p++ = *q++;
6137 *p = '\0';
6138
6139 if (strcasecmp (new_token.str, "BYTE") == 0)
6140 new_token.code = T_BYTE;
6141
6142 else if (strcasecmp (new_token.str, "WORD") == 0)
6143 new_token.code = T_WORD;
6144
6145 else if (strcasecmp (new_token.str, "DWORD") == 0)
6146 new_token.code = T_DWORD;
6147
6148 else if (strcasecmp (new_token.str, "QWORD") == 0)
6149 new_token.code = T_QWORD;
6150
6151 else if (strcasecmp (new_token.str, "XWORD") == 0)
6152 new_token.code = T_XWORD;
6153
6154 else if (strcasecmp (new_token.str, "PTR") == 0)
6155 new_token.code = T_PTR;
6156
6157 else if (strcasecmp (new_token.str, "SHORT") == 0)
6158 new_token.code = T_SHORT;
6159
6160 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6161 {
6162 new_token.code = T_OFFSET;
6163
6164 /* ??? This is not mentioned in the MASM grammar but gcc
6165 makes use of it with -mintel-syntax. OFFSET may be
6166 followed by FLAT: */
6167 if (strncasecmp (q, " FLAT:", 6) == 0)
6168 strcat (new_token.str, " FLAT:");
6169 }
6170
6171 /* ??? This is not mentioned in the MASM grammar. */
6172 else if (strcasecmp (new_token.str, "FLAT") == 0)
6173 new_token.code = T_OFFSET;
6174
6175 else
6176 new_token.code = T_ID;
6177 }
6178 }
6179
6180 else
6181 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6182
6183 intel_parser.op_string += strlen (new_token.str);
6184 cur_token = new_token;
6185}
6186
64a0c779
DN		 6187/* Put cur_token back into the token stream and make cur_token point to
6188 prev_token. */
6189static void
6190intel_putback_token ()
6191{
6192 intel_parser.op_string -= strlen (cur_token.str);
6193 free (cur_token.str);
6194 cur_token = prev_token;
4a1805b1 6195
64a0c779
DN		 6196 /* Forget prev_token. */
6197 prev_token.code = T_NIL;
6198 prev_token.reg = NULL;
6199 prev_token.str = NULL;
6200}
GDB Binutils - Deliverables
This page took 0.832344 seconds and 4 git commands to generate.