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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0f10071e 3 2000, 2001, 2002, 2003, 2004
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132
RH		 35#include "opcode/i386.h"
36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
29b0f896
AM		 65static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
66static INLINE int fits_in_signed_byte PARAMS ((offsetT));
67static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
69static INLINE int fits_in_signed_word PARAMS ((offsetT));
70static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
71static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 72static int smallest_imm_type PARAMS ((offsetT));
73static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 74static int add_prefix PARAMS ((unsigned int));
3e73aa7c 75static void set_code_flag PARAMS ((int));
47926f60 76static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 77static void set_intel_syntax PARAMS ((int));
e413e4e9 78static void set_cpu_arch PARAMS ((int));
6482c264
NC		 79#ifdef TE_PE
80static void pe_directive_secrel PARAMS ((int));
81#endif
29b0f896
AM		 82static char *output_invalid PARAMS ((int c));
83static int i386_operand PARAMS ((char *operand_string));
84static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
85static const reg_entry *parse_register PARAMS ((char *reg_string,
86 char **end_op));
87static char *parse_insn PARAMS ((char *, char *));
88static char *parse_operands PARAMS ((char *, const char *));
89static void swap_operands PARAMS ((void));
90static void optimize_imm PARAMS ((void));
91static void optimize_disp PARAMS ((void));
92static int match_template PARAMS ((void));
93static int check_string PARAMS ((void));
94static int process_suffix PARAMS ((void));
95static int check_byte_reg PARAMS ((void));
96static int check_long_reg PARAMS ((void));
97static int check_qword_reg PARAMS ((void));
98static int check_word_reg PARAMS ((void));
99static int finalize_imm PARAMS ((void));
100static int process_operands PARAMS ((void));
101static const seg_entry *build_modrm_byte PARAMS ((void));
102static void output_insn PARAMS ((void));
103static void output_branch PARAMS ((void));
104static void output_jump PARAMS ((void));
105static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 106static void output_imm PARAMS ((fragS *insn_start_frag,
107 offsetT insn_start_off));
108static void output_disp PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
29b0f896
AM		 110#ifndef I386COFF
111static void s_bss PARAMS ((int));
252b5132
RH		 112#endif
113
a847613f 114static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 115
252b5132 116/* 'md_assemble ()' gathers together information and puts it into a
47926f60 117 i386_insn. */
252b5132 118
520dc8e8
AM		 119union i386_op
120 {
121 expressionS *disps;
122 expressionS *imms;
123 const reg_entry *regs;
124 };
125
252b5132
RH		 126struct _i386_insn
127 {
47926f60 128 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 129 template tm;
130
131 /* SUFFIX holds the instruction mnemonic suffix if given.
132 (e.g. 'l' for 'movl') */
133 char suffix;
134
47926f60 135 /* OPERANDS gives the number of given operands. */
252b5132
RH		 136 unsigned int operands;
137
138 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
139 of given register, displacement, memory operands and immediate
47926f60 140 operands. */
252b5132
RH		 141 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
142
143 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 144 use OP[i] for the corresponding operand. */
252b5132
RH		 145 unsigned int types[MAX_OPERANDS];
146
520dc8e8
AM		 147 /* Displacement expression, immediate expression, or register for each
148 operand. */
149 union i386_op op[MAX_OPERANDS];
252b5132 150
3e73aa7c
JH		 151 /* Flags for operands. */
152 unsigned int flags[MAX_OPERANDS];
153#define Operand_PCrel 1
154
252b5132 155 /* Relocation type for operand */
f86103b7 156 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 157
252b5132
RH		 158 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
159 the base index byte below. */
160 const reg_entry *base_reg;
161 const reg_entry *index_reg;
162 unsigned int log2_scale_factor;
163
164 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 165 explicit segment overrides are given. */
ce8a8b2f 166 const seg_entry *seg[2];
252b5132
RH		 167
168 /* PREFIX holds all the given prefix opcodes (usually null).
169 PREFIXES is the number of prefix opcodes. */
170 unsigned int prefixes;
171 unsigned char prefix[MAX_PREFIXES];
172
173 /* RM and SIB are the modrm byte and the sib byte where the
174 addressing modes of this insn are encoded. */
175
176 modrm_byte rm;
3e73aa7c 177 rex_byte rex;
252b5132
RH		 178 sib_byte sib;
179 };
180
181typedef struct _i386_insn i386_insn;
182
183/* List of chars besides those in app.c:symbol_chars that can start an
184 operand. Used to prevent the scrubber eating vital white-space. */
185#ifdef LEX_AT
200dbde8 186const char extra_symbol_chars[] = "*%-(@[";
252b5132 187#else
200dbde8 188const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 189#endif
190
29b0f896
AM		 191#if (defined (TE_I386AIX) \
192 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
193 && !defined (TE_LINUX) \
194 && !defined (TE_FreeBSD) \
195 && !defined (TE_NetBSD)))
252b5132 196/* This array holds the chars that always start a comment. If the
ce8a8b2f 197 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 198const char comment_chars[] = "#/";
199#define PREFIX_SEPARATOR '\\'
252b5132
RH		 200
201/* This array holds the chars that only start a comment at the beginning of
202 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 203 .line and .file directives will appear in the pre-processed output.
204 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 205 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 206 #NO_APP at the beginning of its output.
207 Also note that comments started like this one will always work if
252b5132 208 '/' isn't otherwise defined. */
0d9f6d04 209const char line_comment_chars[] = "#";
29b0f896 210
252b5132 211#else
29b0f896
AM		 212/* Putting '/' here makes it impossible to use the divide operator.
213 However, we need it for compatibility with SVR4 systems. */
214const char comment_chars[] = "#";
215#define PREFIX_SEPARATOR '/'
216
0d9f6d04 217const char line_comment_chars[] = "/#";
252b5132
RH		 218#endif
219
63a0b638 220const char line_separator_chars[] = ";";
252b5132 221
ce8a8b2f
AM		 222/* Chars that can be used to separate mant from exp in floating point
223 nums. */
252b5132
RH		 224const char EXP_CHARS[] = "eE";
225
ce8a8b2f
AM		 226/* Chars that mean this number is a floating point constant
227 As in 0f12.456
228 or 0d1.2345e12. */
252b5132
RH		 229const char FLT_CHARS[] = "fFdDxX";
230
ce8a8b2f 231/* Tables for lexical analysis. */
252b5132
RH		 232static char mnemonic_chars[256];
233static char register_chars[256];
234static char operand_chars[256];
235static char identifier_chars[256];
236static char digit_chars[256];
237
ce8a8b2f 238/* Lexical macros. */
252b5132
RH		 239#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
240#define is_operand_char(x) (operand_chars[(unsigned char) x])
241#define is_register_char(x) (register_chars[(unsigned char) x])
242#define is_space_char(x) ((x) == ' ')
243#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
244#define is_digit_char(x) (digit_chars[(unsigned char) x])
245
0234cb7c 246/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 247static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
248
249/* md_assemble() always leaves the strings it's passed unaltered. To
250 effect this we maintain a stack of saved characters that we've smashed
251 with '\0's (indicating end of strings for various sub-fields of the
47926f60 252 assembler instruction). */
252b5132 253static char save_stack[32];
ce8a8b2f 254static char *save_stack_p;
252b5132
RH		 255#define END_STRING_AND_SAVE(s) \
256 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
257#define RESTORE_END_STRING(s) \
258 do { *(s) = *--save_stack_p; } while (0)
259
47926f60 260/* The instruction we're assembling. */
252b5132
RH		 261static i386_insn i;
262
263/* Possible templates for current insn. */
264static const templates *current_templates;
265
47926f60 266/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 267static expressionS disp_expressions[2], im_expressions[2];
268
47926f60
KH		 269/* Current operand we are working on. */
270static int this_operand;
252b5132 271
3e73aa7c
JH		 272/* We support four different modes. FLAG_CODE variable is used to distinguish
273 these. */
274
275enum flag_code {
276 CODE_32BIT,
277 CODE_16BIT,
278 CODE_64BIT };
f3c180ae 279#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 280
281static enum flag_code flag_code;
282static int use_rela_relocations = 0;
283
284/* The names used to print error messages. */
b77a7acd 285static const char *flag_code_names[] =
3e73aa7c
JH		 286 {
287 "32",
288 "16",
289 "64"
290 };
252b5132 291
47926f60
KH		 292/* 1 for intel syntax,
293 0 if att syntax. */
294static int intel_syntax = 0;
252b5132 295
47926f60
KH		 296/* 1 if register prefix % not required. */
297static int allow_naked_reg = 0;
252b5132 298
47926f60
KH		 299/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
300 leave, push, and pop instructions so that gcc has the same stack
301 frame as in 32 bit mode. */
302static char stackop_size = '\0';
eecb386c 303
12b55ccc
L		 304/* Non-zero to optimize code alignment. */
305int optimize_align_code = 1;
306
47926f60
KH		 307/* Non-zero to quieten some warnings. */
308static int quiet_warnings = 0;
a38cf1db 309
47926f60
KH		 310/* CPU name. */
311static const char *cpu_arch_name = NULL;
a38cf1db 312
47926f60 313/* CPU feature flags. */
29b0f896 314static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 315
fddf5b5b
AM		 316/* If set, conditional jumps are not automatically promoted to handle
317 larger than a byte offset. */
318static unsigned int no_cond_jump_promotion = 0;
319
29b0f896
AM		 320/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
321symbolS *GOT_symbol;
322
a4447b93
RH		 323/* The dwarf2 return column, adjusted for 32 or 64 bit. */
324unsigned int x86_dwarf2_return_column;
325
326/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
327int x86_cie_data_alignment;
328
252b5132 329/* Interface to relax_segment.
fddf5b5b
AM		 330 There are 3 major relax states for 386 jump insns because the
331 different types of jumps add different sizes to frags when we're
332 figuring out what sort of jump to choose to reach a given label. */
252b5132 333
47926f60 334/* Types. */
93c2a809
AM		 335#define UNCOND_JUMP 0
336#define COND_JUMP 1
337#define COND_JUMP86 2
fddf5b5b 338
47926f60 339/* Sizes. */
252b5132
RH		 340#define CODE16 1
341#define SMALL 0
29b0f896 342#define SMALL16 (SMALL | CODE16)
252b5132 343#define BIG 2
29b0f896 344#define BIG16 (BIG | CODE16)
252b5132
RH		 345
346#ifndef INLINE
347#ifdef __GNUC__
348#define INLINE __inline__
349#else
350#define INLINE
351#endif
352#endif
353
fddf5b5b
AM		 354#define ENCODE_RELAX_STATE(type, size) \
355 ((relax_substateT) (((type) << 2) | (size)))
356#define TYPE_FROM_RELAX_STATE(s) \
357 ((s) >> 2)
358#define DISP_SIZE_FROM_RELAX_STATE(s) \
359 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 360
361/* This table is used by relax_frag to promote short jumps to long
362 ones where necessary. SMALL (short) jumps may be promoted to BIG
363 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
364 don't allow a short jump in a 32 bit code segment to be promoted to
365 a 16 bit offset jump because it's slower (requires data size
366 prefix), and doesn't work, unless the destination is in the bottom
367 64k of the code segment (The top 16 bits of eip are zeroed). */
368
369const relax_typeS md_relax_table[] =
370{
24eab124
AM		 371 /* The fields are:
372 1) most positive reach of this state,
373 2) most negative reach of this state,
93c2a809 374 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 375 4) which index into the table to try if we can't fit into this one. */
252b5132 376
fddf5b5b 377 /* UNCOND_JUMP states. */
93c2a809
AM		 378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
380 /* dword jmp adds 4 bytes to frag:
381 0 extra opcode bytes, 4 displacement bytes. */
252b5132 382 {0, 0, 4, 0},
93c2a809
AM		 383 /* word jmp adds 2 byte2 to frag:
384 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 385 {0, 0, 2, 0},
386
93c2a809
AM		 387 /* COND_JUMP states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
fddf5b5b 393 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 394 1 extra opcode byte, 2 displacement bytes. */
395 {0, 0, 3, 0},
396
397 /* COND_JUMP86 states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
403 /* word conditionals add 4 bytes to frag:
404 1 displacement byte and a 3 byte long branch insn. */
405 {0, 0, 4, 0}
252b5132
RH		 406};
407
e413e4e9
AM		 408static const arch_entry cpu_arch[] = {
409 {"i8086", Cpu086 },
410 {"i186", Cpu086|Cpu186 },
411 {"i286", Cpu086|Cpu186|Cpu286 },
412 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
413 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
414 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
415 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
416 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
417 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 418 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 419 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
420 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 421 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 422 {NULL, 0 }
423};
424
29b0f896
AM		 425const pseudo_typeS md_pseudo_table[] =
426{
427#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
428 {"align", s_align_bytes, 0},
429#else
430 {"align", s_align_ptwo, 0},
431#endif
432 {"arch", set_cpu_arch, 0},
433#ifndef I386COFF
434 {"bss", s_bss, 0},
435#endif
436 {"ffloat", float_cons, 'f'},
437 {"dfloat", float_cons, 'd'},
438 {"tfloat", float_cons, 'x'},
439 {"value", cons, 2},
440 {"noopt", s_ignore, 0},
441 {"optim", s_ignore, 0},
442 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
443 {"code16", set_code_flag, CODE_16BIT},
444 {"code32", set_code_flag, CODE_32BIT},
445 {"code64", set_code_flag, CODE_64BIT},
446 {"intel_syntax", set_intel_syntax, 1},
447 {"att_syntax", set_intel_syntax, 0},
c6682705 448 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 449 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 450#ifdef TE_PE
451 {"secrel32", pe_directive_secrel, 0},
452#endif
29b0f896
AM		 453 {0, 0, 0}
454};
455
456/* For interface with expression (). */
457extern char *input_line_pointer;
458
459/* Hash table for instruction mnemonic lookup. */
460static struct hash_control *op_hash;
461
462/* Hash table for register lookup. */
463static struct hash_control *reg_hash;
464\f
252b5132
RH		 465void
466i386_align_code (fragP, count)
467 fragS *fragP;
468 int count;
469{
ce8a8b2f
AM		 470 /* Various efficient no-op patterns for aligning code labels.
471 Note: Don't try to assemble the instructions in the comments.
472 0L and 0w are not legal. */
252b5132
RH		 473 static const char f32_1[] =
474 {0x90}; /* nop */
475 static const char f32_2[] =
476 {0x89,0xf6}; /* movl %esi,%esi */
477 static const char f32_3[] =
478 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
479 static const char f32_4[] =
480 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
481 static const char f32_5[] =
482 {0x90, /* nop */
483 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
484 static const char f32_6[] =
485 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
486 static const char f32_7[] =
487 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
488 static const char f32_8[] =
489 {0x90, /* nop */
490 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
491 static const char f32_9[] =
492 {0x89,0xf6, /* movl %esi,%esi */
493 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
494 static const char f32_10[] =
495 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
496 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
497 static const char f32_11[] =
498 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
499 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
500 static const char f32_12[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
502 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
503 static const char f32_13[] =
504 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
505 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
506 static const char f32_14[] =
507 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
508 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
509 static const char f32_15[] =
510 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
511 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 512 static const char f16_3[] =
513 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 514 static const char f16_4[] =
515 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
516 static const char f16_5[] =
517 {0x90, /* nop */
518 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
519 static const char f16_6[] =
520 {0x89,0xf6, /* mov %si,%si */
521 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
522 static const char f16_7[] =
523 {0x8d,0x74,0x00, /* lea 0(%si),%si */
524 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
525 static const char f16_8[] =
526 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
527 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
528 static const char *const f32_patt[] = {
529 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
530 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
531 };
532 static const char *const f16_patt[] = {
c3332e24 533 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 534 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
535 };
536
33fef721
JH		 537 if (count <= 0 || count > 15)
538 return;
3e73aa7c 539
33fef721
JH		 540 /* The recommended way to pad 64bit code is to use NOPs preceded by
541 maximally four 0x66 prefixes. Balance the size of nops. */
542 if (flag_code == CODE_64BIT)
252b5132 543 {
33fef721
JH		 544 int i;
545 int nnops = (count + 3) / 4;
546 int len = count / nnops;
547 int remains = count - nnops * len;
548 int pos = 0;
549
550 for (i = 0; i < remains; i++)
252b5132 551 {
33fef721
JH		 552 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
553 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
554 pos += len + 1;
555 }
556 for (; i < nnops; i++)
557 {
558 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
559 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
560 pos += len;
252b5132 561 }
252b5132 562 }
33fef721
JH		 563 else
564 if (flag_code == CODE_16BIT)
565 {
566 memcpy (fragP->fr_literal + fragP->fr_fix,
567 f16_patt[count - 1], count);
568 if (count > 8)
569 /* Adjust jump offset. */
570 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
571 }
572 else
573 memcpy (fragP->fr_literal + fragP->fr_fix,
574 f32_patt[count - 1], count);
575 fragP->fr_var = count;
252b5132
RH		 576}
577
252b5132
RH		 578static INLINE unsigned int
579mode_from_disp_size (t)
580 unsigned int t;
581{
3e73aa7c 582 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 583}
584
585static INLINE int
586fits_in_signed_byte (num)
847f7ad4 587 offsetT num;
252b5132
RH		 588{
589 return (num >= -128) && (num <= 127);
47926f60 590}
252b5132
RH		 591
592static INLINE int
593fits_in_unsigned_byte (num)
847f7ad4 594 offsetT num;
252b5132
RH		 595{
596 return (num & 0xff) == num;
47926f60 597}
252b5132
RH		 598
599static INLINE int
600fits_in_unsigned_word (num)
847f7ad4 601 offsetT num;
252b5132
RH		 602{
603 return (num & 0xffff) == num;
47926f60 604}
252b5132
RH		 605
606static INLINE int
607fits_in_signed_word (num)
847f7ad4 608 offsetT num;
252b5132
RH		 609{
610 return (-32768 <= num) && (num <= 32767);
47926f60 611}
3e73aa7c
JH		 612static INLINE int
613fits_in_signed_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (!(((offsetT) -1 << 31) & num)
620 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
621#endif
622} /* fits_in_signed_long() */
623static INLINE int
624fits_in_unsigned_long (num)
625 offsetT num ATTRIBUTE_UNUSED;
626{
627#ifndef BFD64
628 return 1;
629#else
630 return (num & (((offsetT) 2 << 31) - 1)) == num;
631#endif
632} /* fits_in_unsigned_long() */
252b5132
RH		 633
634static int
635smallest_imm_type (num)
847f7ad4 636 offsetT num;
252b5132 637{
a847613f 638 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 639 {
640 /* This code is disabled on the 486 because all the Imm1 forms
641 in the opcode table are slower on the i486. They're the
642 versions with the implicitly specified single-position
643 displacement, which has another syntax if you really want to
644 use that form. */
645 if (num == 1)
3e73aa7c 646 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 647 }
252b5132 648 return (fits_in_signed_byte (num)
3e73aa7c 649 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 650 : fits_in_unsigned_byte (num)
3e73aa7c 651 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 652 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 653 ? (Imm16 | Imm32 | Imm32S | Imm64)
654 : fits_in_signed_long (num)
655 ? (Imm32 | Imm32S | Imm64)
656 : fits_in_unsigned_long (num)
657 ? (Imm32 | Imm64)
658 : Imm64);
47926f60 659}
252b5132 660
847f7ad4
AM		 661static offsetT
662offset_in_range (val, size)
663 offsetT val;
664 int size;
665{
508866be 666 addressT mask;
ba2adb93 667
847f7ad4
AM		 668 switch (size)
669 {
508866be
L		 670 case 1: mask = ((addressT) 1 << 8) - 1; break;
671 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 672 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 673#ifdef BFD64
674 case 8: mask = ((addressT) 2 << 63) - 1; break;
675#endif
47926f60 676 default: abort ();
847f7ad4
AM		 677 }
678
ba2adb93 679 /* If BFD64, sign extend val. */
3e73aa7c
JH		 680 if (!use_rela_relocations)
681 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
682 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 683
47926f60 684 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 685 {
686 char buf1[40], buf2[40];
687
688 sprint_value (buf1, val);
689 sprint_value (buf2, val & mask);
690 as_warn (_("%s shortened to %s"), buf1, buf2);
691 }
692 return val & mask;
693}
694
252b5132
RH		 695/* Returns 0 if attempting to add a prefix where one from the same
696 class already exists, 1 if non rep/repne added, 2 if rep/repne
697 added. */
698static int
699add_prefix (prefix)
700 unsigned int prefix;
701{
702 int ret = 1;
703 int q;
704
29b0f896
AM		 705 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
706 && flag_code == CODE_64BIT)
3e73aa7c
JH		 707 q = REX_PREFIX;
708 else
709 switch (prefix)
710 {
711 default:
712 abort ();
713
714 case CS_PREFIX_OPCODE:
715 case DS_PREFIX_OPCODE:
716 case ES_PREFIX_OPCODE:
717 case FS_PREFIX_OPCODE:
718 case GS_PREFIX_OPCODE:
719 case SS_PREFIX_OPCODE:
720 q = SEG_PREFIX;
721 break;
252b5132 722
3e73aa7c
JH		 723 case REPNE_PREFIX_OPCODE:
724 case REPE_PREFIX_OPCODE:
725 ret = 2;
726 /* fall thru */
727 case LOCK_PREFIX_OPCODE:
728 q = LOCKREP_PREFIX;
729 break;
252b5132 730
3e73aa7c
JH		 731 case FWAIT_OPCODE:
732 q = WAIT_PREFIX;
733 break;
252b5132 734
3e73aa7c
JH		 735 case ADDR_PREFIX_OPCODE:
736 q = ADDR_PREFIX;
737 break;
252b5132 738
3e73aa7c
JH		 739 case DATA_PREFIX_OPCODE:
740 q = DATA_PREFIX;
741 break;
742 }
252b5132 743
29b0f896 744 if (i.prefix[q] != 0)
252b5132
RH		 745 {
746 as_bad (_("same type of prefix used twice"));
747 return 0;
748 }
749
750 i.prefixes += 1;
751 i.prefix[q] = prefix;
752 return ret;
753}
754
755static void
3e73aa7c 756set_code_flag (value)
e5cb08ac 757 int value;
eecb386c 758{
3e73aa7c
JH		 759 flag_code = value;
760 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
761 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
762 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
763 {
764 as_bad (_("64bit mode not supported on this CPU."));
765 }
766 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
767 {
768 as_bad (_("32bit mode not supported on this CPU."));
769 }
eecb386c
AM		 770 stackop_size = '\0';
771}
772
773static void
3e73aa7c
JH		 774set_16bit_gcc_code_flag (new_code_flag)
775 int new_code_flag;
252b5132 776{
3e73aa7c
JH		 777 flag_code = new_code_flag;
778 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
779 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
780 stackop_size = 'l';
252b5132
RH		 781}
782
783static void
784set_intel_syntax (syntax_flag)
eecb386c 785 int syntax_flag;
252b5132
RH		 786{
787 /* Find out if register prefixing is specified. */
788 int ask_naked_reg = 0;
789
790 SKIP_WHITESPACE ();
29b0f896 791 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 792 {
793 char *string = input_line_pointer;
794 int e = get_symbol_end ();
795
47926f60 796 if (strcmp (string, "prefix") == 0)
252b5132 797 ask_naked_reg = 1;
47926f60 798 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 799 ask_naked_reg = -1;
800 else
d0b47220 801 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 802 *input_line_pointer = e;
803 }
804 demand_empty_rest_of_line ();
c3332e24 805
252b5132
RH		 806 intel_syntax = syntax_flag;
807
808 if (ask_naked_reg == 0)
f86103b7
AM		 809 allow_naked_reg = (intel_syntax
810 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 811 else
812 allow_naked_reg = (ask_naked_reg < 0);
813}
814
e413e4e9
AM		 815static void
816set_cpu_arch (dummy)
47926f60 817 int dummy ATTRIBUTE_UNUSED;
e413e4e9 818{
47926f60 819 SKIP_WHITESPACE ();
e413e4e9 820
29b0f896 821 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 822 {
823 char *string = input_line_pointer;
824 int e = get_symbol_end ();
825 int i;
826
827 for (i = 0; cpu_arch[i].name; i++)
828 {
829 if (strcmp (string, cpu_arch[i].name) == 0)
830 {
831 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 832 cpu_arch_flags = (cpu_arch[i].flags
833 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 834 break;
835 }
836 }
837 if (!cpu_arch[i].name)
838 as_bad (_("no such architecture: `%s'"), string);
839
840 *input_line_pointer = e;
841 }
842 else
843 as_bad (_("missing cpu architecture"));
844
fddf5b5b
AM		 845 no_cond_jump_promotion = 0;
846 if (*input_line_pointer == ','
29b0f896 847 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 848 {
849 char *string = ++input_line_pointer;
850 int e = get_symbol_end ();
851
852 if (strcmp (string, "nojumps") == 0)
853 no_cond_jump_promotion = 1;
854 else if (strcmp (string, "jumps") == 0)
855 ;
856 else
857 as_bad (_("no such architecture modifier: `%s'"), string);
858
859 *input_line_pointer = e;
860 }
861
e413e4e9
AM		 862 demand_empty_rest_of_line ();
863}
864
b9d79e03
JH		 865unsigned long
866i386_mach ()
867{
868 if (!strcmp (default_arch, "x86_64"))
869 return bfd_mach_x86_64;
870 else if (!strcmp (default_arch, "i386"))
871 return bfd_mach_i386_i386;
872 else
873 as_fatal (_("Unknown architecture"));
874}
b9d79e03 875\f
252b5132
RH		 876void
877md_begin ()
878{
879 const char *hash_err;
880
47926f60 881 /* Initialize op_hash hash table. */
252b5132
RH		 882 op_hash = hash_new ();
883
884 {
29b0f896
AM		 885 const template *optab;
886 templates *core_optab;
252b5132 887
47926f60
KH		 888 /* Setup for loop. */
889 optab = i386_optab;
252b5132
RH		 890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
892
893 while (1)
894 {
895 ++optab;
896 if (optab->name == NULL
897 || strcmp (optab->name, (optab - 1)->name) != 0)
898 {
899 /* different name --> ship out current template list;
47926f60 900 add to hash table; & begin anew. */
252b5132
RH		 901 core_optab->end = optab;
902 hash_err = hash_insert (op_hash,
903 (optab - 1)->name,
904 (PTR) core_optab);
905 if (hash_err)
906 {
252b5132
RH		 907 as_fatal (_("Internal Error: Can't hash %s: %s"),
908 (optab - 1)->name,
909 hash_err);
910 }
911 if (optab->name == NULL)
912 break;
913 core_optab = (templates *) xmalloc (sizeof (templates));
914 core_optab->start = optab;
915 }
916 }
917 }
918
47926f60 919 /* Initialize reg_hash hash table. */
252b5132
RH		 920 reg_hash = hash_new ();
921 {
29b0f896 922 const reg_entry *regtab;
252b5132
RH		 923
924 for (regtab = i386_regtab;
925 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
926 regtab++)
927 {
928 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
929 if (hash_err)
3e73aa7c
JH		 930 as_fatal (_("Internal Error: Can't hash %s: %s"),
931 regtab->reg_name,
932 hash_err);
252b5132
RH		 933 }
934 }
935
47926f60 936 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 937 {
29b0f896
AM		 938 int c;
939 char *p;
252b5132
RH		 940
941 for (c = 0; c < 256; c++)
942 {
3882b010 943 if (ISDIGIT (c))
252b5132
RH		 944 {
945 digit_chars[c] = c;
946 mnemonic_chars[c] = c;
947 register_chars[c] = c;
948 operand_chars[c] = c;
949 }
3882b010 950 else if (ISLOWER (c))
252b5132
RH		 951 {
952 mnemonic_chars[c] = c;
953 register_chars[c] = c;
954 operand_chars[c] = c;
955 }
3882b010 956 else if (ISUPPER (c))
252b5132 957 {
3882b010 958 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 959 register_chars[c] = mnemonic_chars[c];
960 operand_chars[c] = c;
961 }
962
3882b010 963 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 964 identifier_chars[c] = c;
965 else if (c >= 128)
966 {
967 identifier_chars[c] = c;
968 operand_chars[c] = c;
969 }
970 }
971
972#ifdef LEX_AT
973 identifier_chars['@'] = '@';
974#endif
252b5132
RH		 975 digit_chars['-'] = '-';
976 identifier_chars['_'] = '_';
977 identifier_chars['.'] = '.';
978
979 for (p = operand_special_chars; *p != '\0'; p++)
980 operand_chars[(unsigned char) *p] = *p;
981 }
982
983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
985 {
986 record_alignment (text_section, 2);
987 record_alignment (data_section, 2);
988 record_alignment (bss_section, 2);
989 }
990#endif
a4447b93
RH		 991
992 if (flag_code == CODE_64BIT)
993 {
994 x86_dwarf2_return_column = 16;
995 x86_cie_data_alignment = -8;
996 }
997 else
998 {
999 x86_dwarf2_return_column = 8;
1000 x86_cie_data_alignment = -4;
1001 }
252b5132
RH		 1002}
1003
1004void
1005i386_print_statistics (file)
1006 FILE *file;
1007{
1008 hash_print_statistics (file, "i386 opcode", op_hash);
1009 hash_print_statistics (file, "i386 register", reg_hash);
1010}
1011\f
252b5132
RH		 1012#ifdef DEBUG386
1013
ce8a8b2f 1014/* Debugging routines for md_assemble. */
252b5132
RH		 1015static void pi PARAMS ((char *, i386_insn *));
1016static void pte PARAMS ((template *));
1017static void pt PARAMS ((unsigned int));
1018static void pe PARAMS ((expressionS *));
1019static void ps PARAMS ((symbolS *));
1020
1021static void
1022pi (line, x)
1023 char *line;
1024 i386_insn *x;
1025{
09f131f2 1026 unsigned int i;
252b5132
RH		 1027
1028 fprintf (stdout, "%s: template ", line);
1029 pte (&x->tm);
09f131f2
JH		 1030 fprintf (stdout, " address: base %s index %s scale %x\n",
1031 x->base_reg ? x->base_reg->reg_name : "none",
1032 x->index_reg ? x->index_reg->reg_name : "none",
1033 x->log2_scale_factor);
1034 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1035 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1036 fprintf (stdout, " sib: base %x index %x scale %x\n",
1037 x->sib.base, x->sib.index, x->sib.scale);
1038 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1039 (x->rex & REX_MODE64) != 0,
1040 (x->rex & REX_EXTX) != 0,
1041 (x->rex & REX_EXTY) != 0,
1042 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1043 for (i = 0; i < x->operands; i++)
1044 {
1045 fprintf (stdout, " #%d: ", i + 1);
1046 pt (x->types[i]);
1047 fprintf (stdout, "\n");
1048 if (x->types[i]
3f4438ab 1049 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1050 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1051 if (x->types[i] & Imm)
520dc8e8 1052 pe (x->op[i].imms);
252b5132 1053 if (x->types[i] & Disp)
520dc8e8 1054 pe (x->op[i].disps);
252b5132
RH		 1055 }
1056}
1057
1058static void
1059pte (t)
1060 template *t;
1061{
09f131f2 1062 unsigned int i;
252b5132 1063 fprintf (stdout, " %d operands ", t->operands);
47926f60 1064 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1065 if (t->extension_opcode != None)
1066 fprintf (stdout, "ext %x ", t->extension_opcode);
1067 if (t->opcode_modifier & D)
1068 fprintf (stdout, "D");
1069 if (t->opcode_modifier & W)
1070 fprintf (stdout, "W");
1071 fprintf (stdout, "\n");
1072 for (i = 0; i < t->operands; i++)
1073 {
1074 fprintf (stdout, " #%d type ", i + 1);
1075 pt (t->operand_types[i]);
1076 fprintf (stdout, "\n");
1077 }
1078}
1079
1080static void
1081pe (e)
1082 expressionS *e;
1083{
24eab124 1084 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1085 fprintf (stdout, " add_number %ld (%lx)\n",
1086 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1087 if (e->X_add_symbol)
1088 {
1089 fprintf (stdout, " add_symbol ");
1090 ps (e->X_add_symbol);
1091 fprintf (stdout, "\n");
1092 }
1093 if (e->X_op_symbol)
1094 {
1095 fprintf (stdout, " op_symbol ");
1096 ps (e->X_op_symbol);
1097 fprintf (stdout, "\n");
1098 }
1099}
1100
1101static void
1102ps (s)
1103 symbolS *s;
1104{
1105 fprintf (stdout, "%s type %s%s",
1106 S_GET_NAME (s),
1107 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1108 segment_name (S_GET_SEGMENT (s)));
1109}
1110
1111struct type_name
1112 {
1113 unsigned int mask;
1114 char *tname;
1115 }
1116
29b0f896 1117static const type_names[] =
252b5132
RH		 1118{
1119 { Reg8, "r8" },
1120 { Reg16, "r16" },
1121 { Reg32, "r32" },
09f131f2 1122 { Reg64, "r64" },
252b5132
RH		 1123 { Imm8, "i8" },
1124 { Imm8S, "i8s" },
1125 { Imm16, "i16" },
1126 { Imm32, "i32" },
09f131f2
JH		 1127 { Imm32S, "i32s" },
1128 { Imm64, "i64" },
252b5132
RH		 1129 { Imm1, "i1" },
1130 { BaseIndex, "BaseIndex" },
1131 { Disp8, "d8" },
1132 { Disp16, "d16" },
1133 { Disp32, "d32" },
09f131f2
JH		 1134 { Disp32S, "d32s" },
1135 { Disp64, "d64" },
252b5132
RH		 1136 { InOutPortReg, "InOutPortReg" },
1137 { ShiftCount, "ShiftCount" },
1138 { Control, "control reg" },
1139 { Test, "test reg" },
1140 { Debug, "debug reg" },
1141 { FloatReg, "FReg" },
1142 { FloatAcc, "FAcc" },
1143 { SReg2, "SReg2" },
1144 { SReg3, "SReg3" },
1145 { Acc, "Acc" },
1146 { JumpAbsolute, "Jump Absolute" },
1147 { RegMMX, "rMMX" },
3f4438ab 1148 { RegXMM, "rXMM" },
252b5132
RH		 1149 { EsSeg, "es" },
1150 { 0, "" }
1151};
1152
1153static void
1154pt (t)
1155 unsigned int t;
1156{
29b0f896 1157 const struct type_name *ty;
252b5132 1158
09f131f2
JH		 1159 for (ty = type_names; ty->mask; ty++)
1160 if (t & ty->mask)
1161 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1162 fflush (stdout);
1163}
1164
1165#endif /* DEBUG386 */
1166\f
29b0f896
AM		 1167static bfd_reloc_code_real_type reloc
1168 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1169
1170static bfd_reloc_code_real_type
3e73aa7c 1171reloc (size, pcrel, sign, other)
252b5132
RH		 1172 int size;
1173 int pcrel;
3e73aa7c 1174 int sign;
252b5132
RH		 1175 bfd_reloc_code_real_type other;
1176{
47926f60
KH		 1177 if (other != NO_RELOC)
1178 return other;
252b5132
RH		 1179
1180 if (pcrel)
1181 {
3e73aa7c 1182 if (!sign)
e5cb08ac 1183 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1184 switch (size)
1185 {
1186 case 1: return BFD_RELOC_8_PCREL;
1187 case 2: return BFD_RELOC_16_PCREL;
1188 case 4: return BFD_RELOC_32_PCREL;
1189 }
d0b47220 1190 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1191 }
1192 else
1193 {
3e73aa7c 1194 if (sign)
e5cb08ac 1195 switch (size)
3e73aa7c
JH		 1196 {
1197 case 4: return BFD_RELOC_X86_64_32S;
1198 }
1199 else
1200 switch (size)
1201 {
1202 case 1: return BFD_RELOC_8;
1203 case 2: return BFD_RELOC_16;
1204 case 4: return BFD_RELOC_32;
1205 case 8: return BFD_RELOC_64;
1206 }
1207 as_bad (_("can not do %s %d byte relocation"),
1208 sign ? "signed" : "unsigned", size);
252b5132
RH		 1209 }
1210
bfb32b52 1211 abort ();
252b5132
RH		 1212 return BFD_RELOC_NONE;
1213}
1214
47926f60
KH		 1215/* Here we decide which fixups can be adjusted to make them relative to
1216 the beginning of the section instead of the symbol. Basically we need
1217 to make sure that the dynamic relocations are done correctly, so in
1218 some cases we force the original symbol to be used. */
1219
252b5132 1220int
c0c949c7 1221tc_i386_fix_adjustable (fixP)
31312f95 1222 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1223{
6d249963 1224#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1225 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1226 return 1;
1227
a161fe53
AM		 1228 /* Don't adjust pc-relative references to merge sections in 64-bit
1229 mode. */
1230 if (use_rela_relocations
1231 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1232 && fixP->fx_pcrel)
252b5132 1233 return 0;
31312f95 1234
8d01d9a9
AJ		 1235 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1236 and changed later by validate_fix. */
1237 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1238 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1239 return 0;
1240
ce8a8b2f 1241 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1242 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1243 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1244 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1245 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1246 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1247 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1248 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1249 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1250 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1251 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1252 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1253 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1254 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1255 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1256 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1257 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1258 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1259 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1260 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1261 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1262 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1263 return 0;
31312f95 1264#endif
252b5132
RH		 1265 return 1;
1266}
252b5132 1267
29b0f896 1268static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1269
1270static int
252b5132 1271intel_float_operand (mnemonic)
29b0f896 1272 const char *mnemonic;
252b5132 1273{
47926f60 1274 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1275 return 2;
252b5132
RH		 1276
1277 if (mnemonic[0] == 'f')
1278 return 1;
1279
1280 return 0;
1281}
1282
1283/* This is the guts of the machine-dependent assembler. LINE points to a
1284 machine dependent instruction. This function is supposed to emit
1285 the frags/bytes it assembles to. */
1286
1287void
1288md_assemble (line)
1289 char *line;
1290{
252b5132 1291 int j;
252b5132
RH		 1292 char mnemonic[MAX_MNEM_SIZE];
1293
47926f60 1294 /* Initialize globals. */
252b5132
RH		 1295 memset (&i, '\0', sizeof (i));
1296 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1297 i.reloc[j] = NO_RELOC;
252b5132
RH		 1298 memset (disp_expressions, '\0', sizeof (disp_expressions));
1299 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1300 save_stack_p = save_stack;
252b5132
RH		 1301
1302 /* First parse an instruction mnemonic & call i386_operand for the operands.
1303 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1304 start of a (possibly prefixed) mnemonic. */
252b5132 1305
29b0f896
AM		 1306 line = parse_insn (line, mnemonic);
1307 if (line == NULL)
1308 return;
252b5132 1309
29b0f896
AM		 1310 line = parse_operands (line, mnemonic);
1311 if (line == NULL)
1312 return;
252b5132 1313
29b0f896
AM		 1314 /* Now we've parsed the mnemonic into a set of templates, and have the
1315 operands at hand. */
1316
1317 /* All intel opcodes have reversed operands except for "bound" and
1318 "enter". We also don't reverse intersegment "jmp" and "call"
1319 instructions with 2 immediate operands so that the immediate segment
1320 precedes the offset, as it does when in AT&T mode. "enter" and the
1321 intersegment "jmp" and "call" instructions are the only ones that
1322 have two immediate operands. */
1323 if (intel_syntax && i.operands > 1
1324 && (strcmp (mnemonic, "bound") != 0)
1325 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1326 swap_operands ();
1327
1328 if (i.imm_operands)
1329 optimize_imm ();
1330
1331 if (i.disp_operands)
1332 optimize_disp ();
1333
1334 /* Next, we find a template that matches the given insn,
1335 making sure the overlap of the given operands types is consistent
1336 with the template operand types. */
252b5132 1337
29b0f896
AM		 1338 if (!match_template ())
1339 return;
252b5132 1340
cd61ebfe
AM		 1341 if (intel_syntax)
1342 {
1343 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1344 if (SYSV386_COMPAT
1345 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1346 i.tm.base_opcode ^= FloatR;
1347
1348 /* Zap movzx and movsx suffix. The suffix may have been set from
1349 "word ptr" or "byte ptr" on the source operand, but we'll use
1350 the suffix later to choose the destination register. */
1351 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1352 i.suffix = 0;
1353 }
24eab124 1354
29b0f896
AM		 1355 if (i.tm.opcode_modifier & FWait)
1356 if (!add_prefix (FWAIT_OPCODE))
1357 return;
252b5132 1358
29b0f896
AM		 1359 /* Check string instruction segment overrides. */
1360 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1361 {
1362 if (!check_string ())
5dd0794d 1363 return;
29b0f896 1364 }
5dd0794d 1365
29b0f896
AM		 1366 if (!process_suffix ())
1367 return;
e413e4e9 1368
29b0f896
AM		 1369 /* Make still unresolved immediate matches conform to size of immediate
1370 given in i.suffix. */
1371 if (!finalize_imm ())
1372 return;
252b5132 1373
29b0f896
AM		 1374 if (i.types[0] & Imm1)
1375 i.imm_operands = 0; /* kludge for shift insns. */
1376 if (i.types[0] & ImplicitRegister)
1377 i.reg_operands--;
1378 if (i.types[1] & ImplicitRegister)
1379 i.reg_operands--;
1380 if (i.types[2] & ImplicitRegister)
1381 i.reg_operands--;
252b5132 1382
29b0f896
AM		 1383 if (i.tm.opcode_modifier & ImmExt)
1384 {
02fc3089
L		 1385 expressionS *exp;
1386
ca164297
L		 1387 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1388 {
67c1ffbe 1389 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1390 operands with an opcode suffix which is coded in the same
1391 place as an 8-bit immediate field would be. Here we check
1392 those operands and remove them afterwards. */
1393 unsigned int x;
1394
a4622f40 1395 for (x = 0; x < i.operands; x++)
ca164297
L		 1396 if (i.op[x].regs->reg_num != x)
1397 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1398 i.op[x].regs->reg_name, x + 1, i.tm.name);
1399 i.operands = 0;
1400 }
1401
29b0f896
AM		 1402 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1403 opcode suffix which is coded in the same place as an 8-bit
1404 immediate field would be. Here we fake an 8-bit immediate
1405 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1406
29b0f896 1407 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1408
29b0f896
AM		 1409 exp = &im_expressions[i.imm_operands++];
1410 i.op[i.operands].imms = exp;
1411 i.types[i.operands++] = Imm8;
1412 exp->X_op = O_constant;
1413 exp->X_add_number = i.tm.extension_opcode;
1414 i.tm.extension_opcode = None;
1415 }
252b5132 1416
29b0f896
AM		 1417 /* For insns with operands there are more diddles to do to the opcode. */
1418 if (i.operands)
1419 {
1420 if (!process_operands ())
1421 return;
1422 }
1423 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1424 {
1425 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1426 as_warn (_("translating to `%sp'"), i.tm.name);
1427 }
252b5132 1428
29b0f896
AM		 1429 /* Handle conversion of 'int $3' --> special int3 insn. */
1430 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1431 {
1432 i.tm.base_opcode = INT3_OPCODE;
1433 i.imm_operands = 0;
1434 }
252b5132 1435
29b0f896
AM		 1436 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1437 && i.op[0].disps->X_op == O_constant)
1438 {
1439 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1440 the absolute address given by the constant. Since ix86 jumps and
1441 calls are pc relative, we need to generate a reloc. */
1442 i.op[0].disps->X_add_symbol = &abs_symbol;
1443 i.op[0].disps->X_op = O_symbol;
1444 }
252b5132 1445
29b0f896
AM		 1446 if ((i.tm.opcode_modifier & Rex64) != 0)
1447 i.rex |= REX_MODE64;
252b5132 1448
29b0f896
AM		 1449 /* For 8 bit registers we need an empty rex prefix. Also if the
1450 instruction already has a prefix, we need to convert old
1451 registers to new ones. */
773f551c 1452
29b0f896
AM		 1453 if (((i.types[0] & Reg8) != 0
1454 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1455 || ((i.types[1] & Reg8) != 0
1456 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1457 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1458 && i.rex != 0))
1459 {
1460 int x;
726c5dcd 1461
29b0f896
AM		 1462 i.rex |= REX_OPCODE;
1463 for (x = 0; x < 2; x++)
1464 {
1465 /* Look for 8 bit operand that uses old registers. */
1466 if ((i.types[x] & Reg8) != 0
1467 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1468 {
29b0f896
AM		 1469 /* In case it is "hi" register, give up. */
1470 if (i.op[x].regs->reg_num > 3)
1471 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1472 i.op[x].regs->reg_name);
773f551c 1473
29b0f896
AM		 1474 /* Otherwise it is equivalent to the extended register.
1475 Since the encoding doesn't change this is merely
1476 cosmetic cleanup for debug output. */
1477
1478 i.op[x].regs = i.op[x].regs + 8;
773f551c 1479 }
29b0f896
AM		 1480 }
1481 }
773f551c 1482
29b0f896
AM		 1483 if (i.rex != 0)
1484 add_prefix (REX_OPCODE | i.rex);
1485
1486 /* We are ready to output the insn. */
1487 output_insn ();
1488}
1489
1490static char *
1491parse_insn (line, mnemonic)
1492 char *line;
1493 char *mnemonic;
1494{
1495 char *l = line;
1496 char *token_start = l;
1497 char *mnem_p;
1498
1499 /* Non-zero if we found a prefix only acceptable with string insns. */
1500 const char *expecting_string_instruction = NULL;
45288df1 1501
29b0f896
AM		 1502 while (1)
1503 {
1504 mnem_p = mnemonic;
1505 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1506 {
1507 mnem_p++;
1508 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1509 {
29b0f896
AM		 1510 as_bad (_("no such instruction: `%s'"), token_start);
1511 return NULL;
1512 }
1513 l++;
1514 }
1515 if (!is_space_char (*l)
1516 && *l != END_OF_INSN
1517 && *l != PREFIX_SEPARATOR
1518 && *l != ',')
1519 {
1520 as_bad (_("invalid character %s in mnemonic"),
1521 output_invalid (*l));
1522 return NULL;
1523 }
1524 if (token_start == l)
1525 {
1526 if (*l == PREFIX_SEPARATOR)
1527 as_bad (_("expecting prefix; got nothing"));
1528 else
1529 as_bad (_("expecting mnemonic; got nothing"));
1530 return NULL;
1531 }
45288df1 1532
29b0f896
AM		 1533 /* Look up instruction (or prefix) via hash table. */
1534 current_templates = hash_find (op_hash, mnemonic);
47926f60 1535
29b0f896
AM		 1536 if (*l != END_OF_INSN
1537 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1538 && current_templates
1539 && (current_templates->start->opcode_modifier & IsPrefix))
1540 {
1541 /* If we are in 16-bit mode, do not allow addr16 or data16.
1542 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1543 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1544 && flag_code != CODE_64BIT
1545 && (((current_templates->start->opcode_modifier & Size32) != 0)
1546 ^ (flag_code == CODE_16BIT)))
1547 {
1548 as_bad (_("redundant %s prefix"),
1549 current_templates->start->name);
1550 return NULL;
45288df1 1551 }
29b0f896
AM		 1552 /* Add prefix, checking for repeated prefixes. */
1553 switch (add_prefix (current_templates->start->base_opcode))
1554 {
1555 case 0:
1556 return NULL;
1557 case 2:
1558 expecting_string_instruction = current_templates->start->name;
1559 break;
1560 }
1561 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1562 token_start = ++l;
1563 }
1564 else
1565 break;
1566 }
45288df1 1567
29b0f896
AM		 1568 if (!current_templates)
1569 {
1570 /* See if we can get a match by trimming off a suffix. */
1571 switch (mnem_p[-1])
1572 {
1573 case WORD_MNEM_SUFFIX:
1574 case BYTE_MNEM_SUFFIX:
1575 case QWORD_MNEM_SUFFIX:
1576 i.suffix = mnem_p[-1];
1577 mnem_p[-1] = '\0';
1578 current_templates = hash_find (op_hash, mnemonic);
1579 break;
1580 case SHORT_MNEM_SUFFIX:
1581 case LONG_MNEM_SUFFIX:
1582 if (!intel_syntax)
1583 {
1584 i.suffix = mnem_p[-1];
1585 mnem_p[-1] = '\0';
1586 current_templates = hash_find (op_hash, mnemonic);
1587 }
1588 break;
252b5132 1589
29b0f896
AM		 1590 /* Intel Syntax. */
1591 case 'd':
1592 if (intel_syntax)
1593 {
1594 if (intel_float_operand (mnemonic))
1595 i.suffix = SHORT_MNEM_SUFFIX;
1596 else
1597 i.suffix = LONG_MNEM_SUFFIX;
1598 mnem_p[-1] = '\0';
1599 current_templates = hash_find (op_hash, mnemonic);
1600 }
1601 break;
1602 }
1603 if (!current_templates)
1604 {
1605 as_bad (_("no such instruction: `%s'"), token_start);
1606 return NULL;
1607 }
1608 }
252b5132 1609
29b0f896
AM		 1610 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1611 {
1612 /* Check for a branch hint. We allow ",pt" and ",pn" for
1613 predict taken and predict not taken respectively.
1614 I'm not sure that branch hints actually do anything on loop
1615 and jcxz insns (JumpByte) for current Pentium4 chips. They
1616 may work in the future and it doesn't hurt to accept them
1617 now. */
1618 if (l[0] == ',' && l[1] == 'p')
1619 {
1620 if (l[2] == 't')
1621 {
1622 if (!add_prefix (DS_PREFIX_OPCODE))
1623 return NULL;
1624 l += 3;
1625 }
1626 else if (l[2] == 'n')
1627 {
1628 if (!add_prefix (CS_PREFIX_OPCODE))
1629 return NULL;
1630 l += 3;
1631 }
1632 }
1633 }
1634 /* Any other comma loses. */
1635 if (*l == ',')
1636 {
1637 as_bad (_("invalid character %s in mnemonic"),
1638 output_invalid (*l));
1639 return NULL;
1640 }
252b5132 1641
29b0f896
AM		 1642 /* Check if instruction is supported on specified architecture. */
1643 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1644 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1645 {
1646 as_warn (_("`%s' is not supported on `%s'"),
1647 current_templates->start->name, cpu_arch_name);
1648 }
1649 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1650 {
1651 as_warn (_("use .code16 to ensure correct addressing mode"));
1652 }
252b5132 1653
29b0f896
AM		 1654 /* Check for rep/repne without a string instruction. */
1655 if (expecting_string_instruction
1656 && !(current_templates->start->opcode_modifier & IsString))
1657 {
1658 as_bad (_("expecting string instruction after `%s'"),
1659 expecting_string_instruction);
1660 return NULL;
1661 }
252b5132 1662
29b0f896
AM		 1663 return l;
1664}
252b5132 1665
29b0f896
AM		 1666static char *
1667parse_operands (l, mnemonic)
1668 char *l;
1669 const char *mnemonic;
1670{
1671 char *token_start;
3138f287 1672
29b0f896
AM		 1673 /* 1 if operand is pending after ','. */
1674 unsigned int expecting_operand = 0;
252b5132 1675
29b0f896
AM		 1676 /* Non-zero if operand parens not balanced. */
1677 unsigned int paren_not_balanced;
1678
1679 while (*l != END_OF_INSN)
1680 {
1681 /* Skip optional white space before operand. */
1682 if (is_space_char (*l))
1683 ++l;
1684 if (!is_operand_char (*l) && *l != END_OF_INSN)
1685 {
1686 as_bad (_("invalid character %s before operand %d"),
1687 output_invalid (*l),
1688 i.operands + 1);
1689 return NULL;
1690 }
1691 token_start = l; /* after white space */
1692 paren_not_balanced = 0;
1693 while (paren_not_balanced || *l != ',')
1694 {
1695 if (*l == END_OF_INSN)
1696 {
1697 if (paren_not_balanced)
1698 {
1699 if (!intel_syntax)
1700 as_bad (_("unbalanced parenthesis in operand %d."),
1701 i.operands + 1);
1702 else
1703 as_bad (_("unbalanced brackets in operand %d."),
1704 i.operands + 1);
1705 return NULL;
1706 }
1707 else
1708 break; /* we are done */
1709 }
1710 else if (!is_operand_char (*l) && !is_space_char (*l))
1711 {
1712 as_bad (_("invalid character %s in operand %d"),
1713 output_invalid (*l),
1714 i.operands + 1);
1715 return NULL;
1716 }
1717 if (!intel_syntax)
1718 {
1719 if (*l == '(')
1720 ++paren_not_balanced;
1721 if (*l == ')')
1722 --paren_not_balanced;
1723 }
1724 else
1725 {
1726 if (*l == '[')
1727 ++paren_not_balanced;
1728 if (*l == ']')
1729 --paren_not_balanced;
1730 }
1731 l++;
1732 }
1733 if (l != token_start)
1734 { /* Yes, we've read in another operand. */
1735 unsigned int operand_ok;
1736 this_operand = i.operands++;
1737 if (i.operands > MAX_OPERANDS)
1738 {
1739 as_bad (_("spurious operands; (%d operands/instruction max)"),
1740 MAX_OPERANDS);
1741 return NULL;
1742 }
1743 /* Now parse operand adding info to 'i' as we go along. */
1744 END_STRING_AND_SAVE (l);
1745
1746 if (intel_syntax)
1747 operand_ok =
1748 i386_intel_operand (token_start,
1749 intel_float_operand (mnemonic));
1750 else
1751 operand_ok = i386_operand (token_start);
1752
1753 RESTORE_END_STRING (l);
1754 if (!operand_ok)
1755 return NULL;
1756 }
1757 else
1758 {
1759 if (expecting_operand)
1760 {
1761 expecting_operand_after_comma:
1762 as_bad (_("expecting operand after ','; got nothing"));
1763 return NULL;
1764 }
1765 if (*l == ',')
1766 {
1767 as_bad (_("expecting operand before ','; got nothing"));
1768 return NULL;
1769 }
1770 }
7f3f1ea2 1771
29b0f896
AM		 1772 /* Now *l must be either ',' or END_OF_INSN. */
1773 if (*l == ',')
1774 {
1775 if (*++l == END_OF_INSN)
1776 {
1777 /* Just skip it, if it's \n complain. */
1778 goto expecting_operand_after_comma;
1779 }
1780 expecting_operand = 1;
1781 }
1782 }
1783 return l;
1784}
7f3f1ea2 1785
29b0f896
AM		 1786static void
1787swap_operands ()
1788{
1789 union i386_op temp_op;
1790 unsigned int temp_type;
f86103b7 1791 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1792 int xchg1 = 0;
1793 int xchg2 = 0;
252b5132 1794
29b0f896
AM		 1795 if (i.operands == 2)
1796 {
1797 xchg1 = 0;
1798 xchg2 = 1;
1799 }
1800 else if (i.operands == 3)
1801 {
1802 xchg1 = 0;
1803 xchg2 = 2;
1804 }
1805 temp_type = i.types[xchg2];
1806 i.types[xchg2] = i.types[xchg1];
1807 i.types[xchg1] = temp_type;
1808 temp_op = i.op[xchg2];
1809 i.op[xchg2] = i.op[xchg1];
1810 i.op[xchg1] = temp_op;
1811 temp_reloc = i.reloc[xchg2];
1812 i.reloc[xchg2] = i.reloc[xchg1];
1813 i.reloc[xchg1] = temp_reloc;
1814
1815 if (i.mem_operands == 2)
1816 {
1817 const seg_entry *temp_seg;
1818 temp_seg = i.seg[0];
1819 i.seg[0] = i.seg[1];
1820 i.seg[1] = temp_seg;
1821 }
1822}
252b5132 1823
29b0f896
AM		 1824/* Try to ensure constant immediates are represented in the smallest
1825 opcode possible. */
1826static void
1827optimize_imm ()
1828{
1829 char guess_suffix = 0;
1830 int op;
252b5132 1831
29b0f896
AM		 1832 if (i.suffix)
1833 guess_suffix = i.suffix;
1834 else if (i.reg_operands)
1835 {
1836 /* Figure out a suffix from the last register operand specified.
1837 We can't do this properly yet, ie. excluding InOutPortReg,
1838 but the following works for instructions with immediates.
1839 In any case, we can't set i.suffix yet. */
1840 for (op = i.operands; --op >= 0;)
1841 if (i.types[op] & Reg)
252b5132 1842 {
29b0f896
AM		 1843 if (i.types[op] & Reg8)
1844 guess_suffix = BYTE_MNEM_SUFFIX;
1845 else if (i.types[op] & Reg16)
1846 guess_suffix = WORD_MNEM_SUFFIX;
1847 else if (i.types[op] & Reg32)
1848 guess_suffix = LONG_MNEM_SUFFIX;
1849 else if (i.types[op] & Reg64)
1850 guess_suffix = QWORD_MNEM_SUFFIX;
1851 break;
252b5132 1852 }
29b0f896
AM		 1853 }
1854 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1855 guess_suffix = WORD_MNEM_SUFFIX;
1856
1857 for (op = i.operands; --op >= 0;)
1858 if (i.types[op] & Imm)
1859 {
1860 switch (i.op[op].imms->X_op)
252b5132 1861 {
29b0f896
AM		 1862 case O_constant:
1863 /* If a suffix is given, this operand may be shortened. */
1864 switch (guess_suffix)
252b5132 1865 {
29b0f896
AM		 1866 case LONG_MNEM_SUFFIX:
1867 i.types[op] |= Imm32 | Imm64;
1868 break;
1869 case WORD_MNEM_SUFFIX:
1870 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1871 break;
1872 case BYTE_MNEM_SUFFIX:
1873 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1874 break;
252b5132 1875 }
252b5132 1876
29b0f896
AM		 1877 /* If this operand is at most 16 bits, convert it
1878 to a signed 16 bit number before trying to see
1879 whether it will fit in an even smaller size.
1880 This allows a 16-bit operand such as $0xffe0 to
1881 be recognised as within Imm8S range. */
1882 if ((i.types[op] & Imm16)
1883 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1884 {
29b0f896
AM		 1885 i.op[op].imms->X_add_number =
1886 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1887 }
1888 if ((i.types[op] & Imm32)
1889 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1890 == 0))
1891 {
1892 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1893 ^ ((offsetT) 1 << 31))
1894 - ((offsetT) 1 << 31));
1895 }
1896 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1897
29b0f896
AM		 1898 /* We must avoid matching of Imm32 templates when 64bit
1899 only immediate is available. */
1900 if (guess_suffix == QWORD_MNEM_SUFFIX)
1901 i.types[op] &= ~Imm32;
1902 break;
252b5132 1903
29b0f896
AM		 1904 case O_absent:
1905 case O_register:
1906 abort ();
1907
1908 /* Symbols and expressions. */
1909 default:
1910 /* Convert symbolic operand to proper sizes for matching. */
1911 switch (guess_suffix)
1912 {
1913 case QWORD_MNEM_SUFFIX:
1914 i.types[op] = Imm64 | Imm32S;
1915 break;
1916 case LONG_MNEM_SUFFIX:
1917 i.types[op] = Imm32 | Imm64;
1918 break;
1919 case WORD_MNEM_SUFFIX:
1920 i.types[op] = Imm16 | Imm32 | Imm64;
1921 break;
1922 break;
1923 case BYTE_MNEM_SUFFIX:
1924 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1925 break;
1926 break;
252b5132 1927 }
29b0f896 1928 break;
252b5132 1929 }
29b0f896
AM		 1930 }
1931}
47926f60 1932
29b0f896
AM		 1933/* Try to use the smallest displacement type too. */
1934static void
1935optimize_disp ()
1936{
1937 int op;
3e73aa7c 1938
29b0f896
AM		 1939 for (op = i.operands; --op >= 0;)
1940 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1941 {
29b0f896
AM		 1942 offsetT disp = i.op[op].disps->X_add_number;
1943
1944 if (i.types[op] & Disp16)
252b5132 1945 {
29b0f896
AM		 1946 /* We know this operand is at most 16 bits, so
1947 convert to a signed 16 bit number before trying
1948 to see whether it will fit in an even smaller
1949 size. */
1950
1951 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1952 }
29b0f896 1953 else if (i.types[op] & Disp32)
252b5132 1954 {
29b0f896
AM		 1955 /* We know this operand is at most 32 bits, so convert to a
1956 signed 32 bit number before trying to see whether it will
1957 fit in an even smaller size. */
1958 disp &= (((offsetT) 2 << 31) - 1);
1959 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1960 }
29b0f896 1961 if (flag_code == CODE_64BIT)
252b5132 1962 {
29b0f896
AM		 1963 if (fits_in_signed_long (disp))
1964 i.types[op] |= Disp32S;
1965 if (fits_in_unsigned_long (disp))
1966 i.types[op] |= Disp32;
252b5132 1967 }
29b0f896
AM		 1968 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1969 && fits_in_signed_byte (disp))
1970 i.types[op] |= Disp8;
252b5132 1971 }
29b0f896
AM		 1972}
1973
1974static int
1975match_template ()
1976{
1977 /* Points to template once we've found it. */
1978 const template *t;
1979 unsigned int overlap0, overlap1, overlap2;
1980 unsigned int found_reverse_match;
1981 int suffix_check;
1982
1983#define MATCH(overlap, given, template) \
1984 ((overlap & ~JumpAbsolute) \
1985 && (((given) & (BaseIndex | JumpAbsolute)) \
1986 == ((overlap) & (BaseIndex | JumpAbsolute))))
1987
1988 /* If given types r0 and r1 are registers they must be of the same type
1989 unless the expected operand type register overlap is null.
1990 Note that Acc in a template matches every size of reg. */
1991#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1992 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1993 || ((g0) & Reg) == ((g1) & Reg) \
1994 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1995
1996 overlap0 = 0;
1997 overlap1 = 0;
1998 overlap2 = 0;
1999 found_reverse_match = 0;
2000 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2001 ? No_bSuf
2002 : (i.suffix == WORD_MNEM_SUFFIX
2003 ? No_wSuf
2004 : (i.suffix == SHORT_MNEM_SUFFIX
2005 ? No_sSuf
2006 : (i.suffix == LONG_MNEM_SUFFIX
2007 ? No_lSuf
2008 : (i.suffix == QWORD_MNEM_SUFFIX
2009 ? No_qSuf
2010 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2011 ? No_xSuf : 0))))));
2012
2013 for (t = current_templates->start;
2014 t < current_templates->end;
2015 t++)
2016 {
2017 /* Must have right number of operands. */
2018 if (i.operands != t->operands)
2019 continue;
2020
2021 /* Check the suffix, except for some instructions in intel mode. */
2022 if ((t->opcode_modifier & suffix_check)
2023 && !(intel_syntax
2024 && (t->opcode_modifier & IgnoreSize))
2025 && !(intel_syntax
2026 && t->base_opcode == 0xd9
2027 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2028 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2029 continue;
2030
2031 /* Do not verify operands when there are none. */
2032 else if (!t->operands)
2033 {
2034 if (t->cpu_flags & ~cpu_arch_flags)
2035 continue;
2036 /* We've found a match; break out of loop. */
2037 break;
2038 }
252b5132 2039
29b0f896
AM		 2040 overlap0 = i.types[0] & t->operand_types[0];
2041 switch (t->operands)
2042 {
2043 case 1:
2044 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2045 continue;
2046 break;
2047 case 2:
2048 case 3:
2049 overlap1 = i.types[1] & t->operand_types[1];
2050 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2051 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2052 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2053 t->operand_types[0],
2054 overlap1, i.types[1],
2055 t->operand_types[1]))
2056 {
2057 /* Check if other direction is valid ... */
2058 if ((t->opcode_modifier & (D | FloatD)) == 0)
2059 continue;
2060
2061 /* Try reversing direction of operands. */
2062 overlap0 = i.types[0] & t->operand_types[1];
2063 overlap1 = i.types[1] & t->operand_types[0];
2064 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2065 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2066 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2067 t->operand_types[1],
2068 overlap1, i.types[1],
2069 t->operand_types[0]))
2070 {
2071 /* Does not match either direction. */
2072 continue;
2073 }
2074 /* found_reverse_match holds which of D or FloatDR
2075 we've found. */
2076 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2077 }
2078 /* Found a forward 2 operand match here. */
2079 else if (t->operands == 3)
2080 {
2081 /* Here we make use of the fact that there are no
2082 reverse match 3 operand instructions, and all 3
2083 operand instructions only need to be checked for
2084 register consistency between operands 2 and 3. */
2085 overlap2 = i.types[2] & t->operand_types[2];
2086 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2087 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2088 t->operand_types[1],
2089 overlap2, i.types[2],
2090 t->operand_types[2]))
2091
2092 continue;
2093 }
2094 /* Found either forward/reverse 2 or 3 operand match here:
2095 slip through to break. */
2096 }
2097 if (t->cpu_flags & ~cpu_arch_flags)
2098 {
2099 found_reverse_match = 0;
2100 continue;
2101 }
2102 /* We've found a match; break out of loop. */
2103 break;
2104 }
2105
2106 if (t == current_templates->end)
2107 {
2108 /* We found no match. */
2109 as_bad (_("suffix or operands invalid for `%s'"),
2110 current_templates->start->name);
2111 return 0;
2112 }
252b5132 2113
29b0f896
AM		 2114 if (!quiet_warnings)
2115 {
2116 if (!intel_syntax
2117 && ((i.types[0] & JumpAbsolute)
2118 != (t->operand_types[0] & JumpAbsolute)))
2119 {
2120 as_warn (_("indirect %s without `*'"), t->name);
2121 }
2122
2123 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2124 == (IsPrefix | IgnoreSize))
2125 {
2126 /* Warn them that a data or address size prefix doesn't
2127 affect assembly of the next line of code. */
2128 as_warn (_("stand-alone `%s' prefix"), t->name);
2129 }
2130 }
2131
2132 /* Copy the template we found. */
2133 i.tm = *t;
2134 if (found_reverse_match)
2135 {
2136 /* If we found a reverse match we must alter the opcode
2137 direction bit. found_reverse_match holds bits to change
2138 (different for int & float insns). */
2139
2140 i.tm.base_opcode ^= found_reverse_match;
2141
2142 i.tm.operand_types[0] = t->operand_types[1];
2143 i.tm.operand_types[1] = t->operand_types[0];
2144 }
2145
2146 return 1;
2147}
2148
2149static int
2150check_string ()
2151{
2152 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2153 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2154 {
2155 if (i.seg[0] != NULL && i.seg[0] != &es)
2156 {
2157 as_bad (_("`%s' operand %d must use `%%es' segment"),
2158 i.tm.name,
2159 mem_op + 1);
2160 return 0;
2161 }
2162 /* There's only ever one segment override allowed per instruction.
2163 This instruction possibly has a legal segment override on the
2164 second operand, so copy the segment to where non-string
2165 instructions store it, allowing common code. */
2166 i.seg[0] = i.seg[1];
2167 }
2168 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2169 {
2170 if (i.seg[1] != NULL && i.seg[1] != &es)
2171 {
2172 as_bad (_("`%s' operand %d must use `%%es' segment"),
2173 i.tm.name,
2174 mem_op + 2);
2175 return 0;
2176 }
2177 }
2178 return 1;
2179}
2180
2181static int
2182process_suffix ()
2183{
2184 /* If matched instruction specifies an explicit instruction mnemonic
2185 suffix, use it. */
2186 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2187 {
2188 if (i.tm.opcode_modifier & Size16)
2189 i.suffix = WORD_MNEM_SUFFIX;
2190 else if (i.tm.opcode_modifier & Size64)
2191 i.suffix = QWORD_MNEM_SUFFIX;
2192 else
2193 i.suffix = LONG_MNEM_SUFFIX;
2194 }
2195 else if (i.reg_operands)
2196 {
2197 /* If there's no instruction mnemonic suffix we try to invent one
2198 based on register operands. */
2199 if (!i.suffix)
2200 {
2201 /* We take i.suffix from the last register operand specified,
2202 Destination register type is more significant than source
2203 register type. */
2204 int op;
2205 for (op = i.operands; --op >= 0;)
2206 if ((i.types[op] & Reg)
2207 && !(i.tm.operand_types[op] & InOutPortReg))
2208 {
2209 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2210 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2211 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2212 LONG_MNEM_SUFFIX);
2213 break;
2214 }
2215 }
2216 else if (i.suffix == BYTE_MNEM_SUFFIX)
2217 {
2218 if (!check_byte_reg ())
2219 return 0;
2220 }
2221 else if (i.suffix == LONG_MNEM_SUFFIX)
2222 {
2223 if (!check_long_reg ())
2224 return 0;
2225 }
2226 else if (i.suffix == QWORD_MNEM_SUFFIX)
2227 {
2228 if (!check_qword_reg ())
2229 return 0;
2230 }
2231 else if (i.suffix == WORD_MNEM_SUFFIX)
2232 {
2233 if (!check_word_reg ())
2234 return 0;
2235 }
2236 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2237 /* Do nothing if the instruction is going to ignore the prefix. */
2238 ;
2239 else
2240 abort ();
2241 }
2242 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2243 {
2244 i.suffix = stackop_size;
2245 }
252b5132 2246
29b0f896
AM		 2247 /* Change the opcode based on the operand size given by i.suffix;
2248 We need not change things for byte insns. */
252b5132 2249
29b0f896
AM		 2250 if (!i.suffix && (i.tm.opcode_modifier & W))
2251 {
2252 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2253 return 0;
2254 }
252b5132 2255
29b0f896
AM		 2256 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2257 {
2258 /* It's not a byte, select word/dword operation. */
2259 if (i.tm.opcode_modifier & W)
2260 {
2261 if (i.tm.opcode_modifier & ShortForm)
2262 i.tm.base_opcode |= 8;
2263 else
2264 i.tm.base_opcode |= 1;
2265 }
0f3f3d8b 2266
29b0f896
AM		 2267 /* Now select between word & dword operations via the operand
2268 size prefix, except for instructions that will ignore this
2269 prefix anyway. */
2270 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2271 && !(i.tm.opcode_modifier & IgnoreSize)
2272 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2273 || (flag_code == CODE_64BIT
2274 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2275 {
2276 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2277 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2278 prefix = ADDR_PREFIX_OPCODE;
252b5132 2279
29b0f896
AM		 2280 if (!add_prefix (prefix))
2281 return 0;
24eab124 2282 }
252b5132 2283
29b0f896
AM		 2284 /* Set mode64 for an operand. */
2285 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2286 && flag_code == CODE_64BIT
29b0f896 2287 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2288 i.rex |= REX_MODE64;
3e73aa7c 2289
29b0f896
AM		 2290 /* Size floating point instruction. */
2291 if (i.suffix == LONG_MNEM_SUFFIX)
2292 {
2293 if (i.tm.opcode_modifier & FloatMF)
2294 i.tm.base_opcode ^= 4;
2295 }
2296 }
7ecd2f8b 2297
29b0f896
AM		 2298 return 1;
2299}
3e73aa7c 2300
29b0f896
AM		 2301static int
2302check_byte_reg ()
2303{
2304 int op;
2305 for (op = i.operands; --op >= 0;)
2306 {
2307 /* If this is an eight bit register, it's OK. If it's the 16 or
2308 32 bit version of an eight bit register, we will just use the
2309 low portion, and that's OK too. */
2310 if (i.types[op] & Reg8)
2311 continue;
2312
2313 /* movzx and movsx should not generate this warning. */
2314 if (intel_syntax
2315 && (i.tm.base_opcode == 0xfb7
2316 || i.tm.base_opcode == 0xfb6
2317 || i.tm.base_opcode == 0x63
2318 || i.tm.base_opcode == 0xfbe
2319 || i.tm.base_opcode == 0xfbf))
2320 continue;
2321
2322 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2323#if 0
2324 /* Check that the template allows eight bit regs. This
2325 kills insns such as `orb $1,%edx', which maybe should be
2326 allowed. */
2327 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2328#endif
2329 )
2330 {
2331 /* Prohibit these changes in the 64bit mode, since the
2332 lowering is more complicated. */
2333 if (flag_code == CODE_64BIT
2334 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2335 {
0f3f3d8b 2336 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2337 i.op[op].regs->reg_name,
2338 i.suffix);
2339 return 0;
2340 }
2341#if REGISTER_WARNINGS
2342 if (!quiet_warnings
2343 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2344 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2345 (i.op[op].regs + (i.types[op] & Reg16
2346 ? REGNAM_AL - REGNAM_AX
2347 : REGNAM_AL - REGNAM_EAX))->reg_name,
2348 i.op[op].regs->reg_name,
2349 i.suffix);
2350#endif
2351 continue;
2352 }
2353 /* Any other register is bad. */
2354 if (i.types[op] & (Reg | RegMMX | RegXMM
2355 | SReg2 | SReg3
2356 | Control | Debug | Test
2357 | FloatReg | FloatAcc))
2358 {
2359 as_bad (_("`%%%s' not allowed with `%s%c'"),
2360 i.op[op].regs->reg_name,
2361 i.tm.name,
2362 i.suffix);
2363 return 0;
2364 }
2365 }
2366 return 1;
2367}
2368
2369static int
2370check_long_reg ()
2371{
2372 int op;
2373
2374 for (op = i.operands; --op >= 0;)
2375 /* Reject eight bit registers, except where the template requires
2376 them. (eg. movzb) */
2377 if ((i.types[op] & Reg8) != 0
2378 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2379 {
2380 as_bad (_("`%%%s' not allowed with `%s%c'"),
2381 i.op[op].regs->reg_name,
2382 i.tm.name,
2383 i.suffix);
2384 return 0;
2385 }
2386 /* Warn if the e prefix on a general reg is missing. */
2387 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2388 && (i.types[op] & Reg16) != 0
2389 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2390 {
2391 /* Prohibit these changes in the 64bit mode, since the
2392 lowering is more complicated. */
2393 if (flag_code == CODE_64BIT)
252b5132 2394 {
0f3f3d8b 2395 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2396 i.op[op].regs->reg_name,
2397 i.suffix);
2398 return 0;
252b5132 2399 }
29b0f896
AM		 2400#if REGISTER_WARNINGS
2401 else
2402 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2403 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2404 i.op[op].regs->reg_name,
2405 i.suffix);
2406#endif
252b5132 2407 }
29b0f896
AM		 2408 /* Warn if the r prefix on a general reg is missing. */
2409 else if ((i.types[op] & Reg64) != 0
2410 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2411 {
0f3f3d8b 2412 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2413 i.op[op].regs->reg_name,
2414 i.suffix);
2415 return 0;
2416 }
2417 return 1;
2418}
252b5132 2419
29b0f896
AM		 2420static int
2421check_qword_reg ()
2422{
2423 int op;
252b5132 2424
29b0f896
AM		 2425 for (op = i.operands; --op >= 0; )
2426 /* Reject eight bit registers, except where the template requires
2427 them. (eg. movzb) */
2428 if ((i.types[op] & Reg8) != 0
2429 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2430 {
2431 as_bad (_("`%%%s' not allowed with `%s%c'"),
2432 i.op[op].regs->reg_name,
2433 i.tm.name,
2434 i.suffix);
2435 return 0;
2436 }
2437 /* Warn if the e prefix on a general reg is missing. */
2438 else if (((i.types[op] & Reg16) != 0
2439 || (i.types[op] & Reg32) != 0)
2440 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2441 {
2442 /* Prohibit these changes in the 64bit mode, since the
2443 lowering is more complicated. */
0f3f3d8b 2444 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2445 i.op[op].regs->reg_name,
2446 i.suffix);
2447 return 0;
252b5132 2448 }
29b0f896
AM		 2449 return 1;
2450}
252b5132 2451
29b0f896
AM		 2452static int
2453check_word_reg ()
2454{
2455 int op;
2456 for (op = i.operands; --op >= 0;)
2457 /* Reject eight bit registers, except where the template requires
2458 them. (eg. movzb) */
2459 if ((i.types[op] & Reg8) != 0
2460 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2461 {
2462 as_bad (_("`%%%s' not allowed with `%s%c'"),
2463 i.op[op].regs->reg_name,
2464 i.tm.name,
2465 i.suffix);
2466 return 0;
2467 }
2468 /* Warn if the e prefix on a general reg is present. */
2469 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2470 && (i.types[op] & Reg32) != 0
2471 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2472 {
29b0f896
AM		 2473 /* Prohibit these changes in the 64bit mode, since the
2474 lowering is more complicated. */
2475 if (flag_code == CODE_64BIT)
252b5132 2476 {
0f3f3d8b 2477 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2478 i.op[op].regs->reg_name,
2479 i.suffix);
2480 return 0;
252b5132 2481 }
29b0f896
AM		 2482 else
2483#if REGISTER_WARNINGS
2484 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2485 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2486 i.op[op].regs->reg_name,
2487 i.suffix);
2488#endif
2489 }
2490 return 1;
2491}
252b5132 2492
29b0f896
AM		 2493static int
2494finalize_imm ()
2495{
2496 unsigned int overlap0, overlap1, overlap2;
2497
2498 overlap0 = i.types[0] & i.tm.operand_types[0];
2499 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2500 && overlap0 != Imm8 && overlap0 != Imm8S
2501 && overlap0 != Imm16 && overlap0 != Imm32S
2502 && overlap0 != Imm32 && overlap0 != Imm64)
2503 {
2504 if (i.suffix)
2505 {
2506 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2507 ? Imm8 | Imm8S
2508 : (i.suffix == WORD_MNEM_SUFFIX
2509 ? Imm16
2510 : (i.suffix == QWORD_MNEM_SUFFIX
2511 ? Imm64 | Imm32S
2512 : Imm32)));
2513 }
2514 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2515 || overlap0 == (Imm16 | Imm32)
2516 || overlap0 == (Imm16 | Imm32S))
2517 {
2518 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2519 ? Imm16 : Imm32S);
2520 }
2521 if (overlap0 != Imm8 && overlap0 != Imm8S
2522 && overlap0 != Imm16 && overlap0 != Imm32S
2523 && overlap0 != Imm32 && overlap0 != Imm64)
2524 {
2525 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2526 return 0;
2527 }
2528 }
2529 i.types[0] = overlap0;
2530
2531 overlap1 = i.types[1] & i.tm.operand_types[1];
2532 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2533 && overlap1 != Imm8 && overlap1 != Imm8S
2534 && overlap1 != Imm16 && overlap1 != Imm32S
2535 && overlap1 != Imm32 && overlap1 != Imm64)
2536 {
2537 if (i.suffix)
2538 {
2539 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2540 ? Imm8 | Imm8S
2541 : (i.suffix == WORD_MNEM_SUFFIX
2542 ? Imm16
2543 : (i.suffix == QWORD_MNEM_SUFFIX
2544 ? Imm64 | Imm32S
2545 : Imm32)));
2546 }
2547 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2548 || overlap1 == (Imm16 | Imm32)
2549 || overlap1 == (Imm16 | Imm32S))
2550 {
2551 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2552 ? Imm16 : Imm32S);
2553 }
2554 if (overlap1 != Imm8 && overlap1 != Imm8S
2555 && overlap1 != Imm16 && overlap1 != Imm32S
2556 && overlap1 != Imm32 && overlap1 != Imm64)
2557 {
2558 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2559 return 0;
2560 }
2561 }
2562 i.types[1] = overlap1;
2563
2564 overlap2 = i.types[2] & i.tm.operand_types[2];
2565 assert ((overlap2 & Imm) == 0);
2566 i.types[2] = overlap2;
2567
2568 return 1;
2569}
2570
2571static int
2572process_operands ()
2573{
2574 /* Default segment register this instruction will use for memory
2575 accesses. 0 means unknown. This is only for optimizing out
2576 unnecessary segment overrides. */
2577 const seg_entry *default_seg = 0;
2578
2579 /* The imul $imm, %reg instruction is converted into
2580 imul $imm, %reg, %reg, and the clr %reg instruction
2581 is converted into xor %reg, %reg. */
2582 if (i.tm.opcode_modifier & regKludge)
2583 {
2584 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2585 /* Pretend we saw the extra register operand. */
2586 assert (i.op[first_reg_op + 1].regs == 0);
2587 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2588 i.types[first_reg_op + 1] = i.types[first_reg_op];
2589 i.reg_operands = 2;
2590 }
2591
2592 if (i.tm.opcode_modifier & ShortForm)
2593 {
2594 /* The register or float register operand is in operand 0 or 1. */
2595 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2596 /* Register goes in low 3 bits of opcode. */
2597 i.tm.base_opcode |= i.op[op].regs->reg_num;
2598 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2599 i.rex |= REX_EXTZ;
2600 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2601 {
2602 /* Warn about some common errors, but press on regardless.
2603 The first case can be generated by gcc (<= 2.8.1). */
2604 if (i.operands == 2)
2605 {
2606 /* Reversed arguments on faddp, fsubp, etc. */
2607 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2608 i.op[1].regs->reg_name,
2609 i.op[0].regs->reg_name);
2610 }
2611 else
2612 {
2613 /* Extraneous `l' suffix on fp insn. */
2614 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2615 i.op[0].regs->reg_name);
2616 }
2617 }
2618 }
2619 else if (i.tm.opcode_modifier & Modrm)
2620 {
2621 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2622 must be put into the modrm byte). Now, we make the modrm and
2623 index base bytes based on all the info we've collected. */
29b0f896
AM		 2624
2625 default_seg = build_modrm_byte ();
2626 }
2627 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2628 {
2629 if (i.tm.base_opcode == POP_SEG_SHORT
2630 && i.op[0].regs->reg_num == 1)
2631 {
2632 as_bad (_("you can't `pop %%cs'"));
2633 return 0;
2634 }
2635 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2636 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2637 i.rex |= REX_EXTZ;
2638 }
2639 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2640 {
2641 default_seg = &ds;
2642 }
2643 else if ((i.tm.opcode_modifier & IsString) != 0)
2644 {
2645 /* For the string instructions that allow a segment override
2646 on one of their operands, the default segment is ds. */
2647 default_seg = &ds;
2648 }
2649
52271982
AM		 2650 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2651 as_warn (_("segment override on `lea' is ineffectual"));
2652
2653 /* If a segment was explicitly specified, and the specified segment
2654 is not the default, use an opcode prefix to select it. If we
2655 never figured out what the default segment is, then default_seg
2656 will be zero at this point, and the specified segment prefix will
2657 always be used. */
29b0f896
AM		 2658 if ((i.seg[0]) && (i.seg[0] != default_seg))
2659 {
2660 if (!add_prefix (i.seg[0]->seg_prefix))
2661 return 0;
2662 }
2663 return 1;
2664}
2665
2666static const seg_entry *
2667build_modrm_byte ()
2668{
2669 const seg_entry *default_seg = 0;
2670
2671 /* i.reg_operands MUST be the number of real register operands;
2672 implicit registers do not count. */
2673 if (i.reg_operands == 2)
2674 {
2675 unsigned int source, dest;
2676 source = ((i.types[0]
2677 & (Reg | RegMMX | RegXMM
2678 | SReg2 | SReg3
2679 | Control | Debug | Test))
2680 ? 0 : 1);
2681 dest = source + 1;
2682
2683 i.rm.mode = 3;
2684 /* One of the register operands will be encoded in the i.tm.reg
2685 field, the other in the combined i.tm.mode and i.tm.regmem
2686 fields. If no form of this instruction supports a memory
2687 destination operand, then we assume the source operand may
2688 sometimes be a memory operand and so we need to store the
2689 destination in the i.rm.reg field. */
2690 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2691 {
2692 i.rm.reg = i.op[dest].regs->reg_num;
2693 i.rm.regmem = i.op[source].regs->reg_num;
2694 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2695 i.rex |= REX_EXTX;
2696 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2697 i.rex |= REX_EXTZ;
2698 }
2699 else
2700 {
2701 i.rm.reg = i.op[source].regs->reg_num;
2702 i.rm.regmem = i.op[dest].regs->reg_num;
2703 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2704 i.rex |= REX_EXTZ;
2705 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2706 i.rex |= REX_EXTX;
2707 }
2708 }
2709 else
2710 { /* If it's not 2 reg operands... */
2711 if (i.mem_operands)
2712 {
2713 unsigned int fake_zero_displacement = 0;
2714 unsigned int op = ((i.types[0] & AnyMem)
2715 ? 0
2716 : (i.types[1] & AnyMem) ? 1 : 2);
2717
2718 default_seg = &ds;
2719
2720 if (i.base_reg == 0)
2721 {
2722 i.rm.mode = 0;
2723 if (!i.disp_operands)
2724 fake_zero_displacement = 1;
2725 if (i.index_reg == 0)
2726 {
2727 /* Operand is just <disp> */
2728 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2729 && (flag_code != CODE_64BIT))
2730 {
2731 i.rm.regmem = NO_BASE_REGISTER_16;
2732 i.types[op] &= ~Disp;
2733 i.types[op] |= Disp16;
2734 }
2735 else if (flag_code != CODE_64BIT
2736 || (i.prefix[ADDR_PREFIX] != 0))
2737 {
2738 i.rm.regmem = NO_BASE_REGISTER;
2739 i.types[op] &= ~Disp;
2740 i.types[op] |= Disp32;
2741 }
2742 else
2743 {
2744 /* 64bit mode overwrites the 32bit absolute
2745 addressing by RIP relative addressing and
2746 absolute addressing is encoded by one of the
2747 redundant SIB forms. */
2748 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2749 i.sib.base = NO_BASE_REGISTER;
2750 i.sib.index = NO_INDEX_REGISTER;
2751 i.types[op] &= ~Disp;
2752 i.types[op] |= Disp32S;
2753 }
2754 }
2755 else /* !i.base_reg && i.index_reg */
2756 {
2757 i.sib.index = i.index_reg->reg_num;
2758 i.sib.base = NO_BASE_REGISTER;
2759 i.sib.scale = i.log2_scale_factor;
2760 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2761 i.types[op] &= ~Disp;
2762 if (flag_code != CODE_64BIT)
2763 i.types[op] |= Disp32; /* Must be 32 bit */
2764 else
2765 i.types[op] |= Disp32S;
2766 if ((i.index_reg->reg_flags & RegRex) != 0)
2767 i.rex |= REX_EXTY;
2768 }
2769 }
2770 /* RIP addressing for 64bit mode. */
2771 else if (i.base_reg->reg_type == BaseIndex)
2772 {
2773 i.rm.regmem = NO_BASE_REGISTER;
2774 i.types[op] &= ~Disp;
2775 i.types[op] |= Disp32S;
2776 i.flags[op] = Operand_PCrel;
2777 }
2778 else if (i.base_reg->reg_type & Reg16)
2779 {
2780 switch (i.base_reg->reg_num)
2781 {
2782 case 3: /* (%bx) */
2783 if (i.index_reg == 0)
2784 i.rm.regmem = 7;
2785 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2786 i.rm.regmem = i.index_reg->reg_num - 6;
2787 break;
2788 case 5: /* (%bp) */
2789 default_seg = &ss;
2790 if (i.index_reg == 0)
2791 {
2792 i.rm.regmem = 6;
2793 if ((i.types[op] & Disp) == 0)
2794 {
2795 /* fake (%bp) into 0(%bp) */
2796 i.types[op] |= Disp8;
252b5132 2797 fake_zero_displacement = 1;
29b0f896
AM		 2798 }
2799 }
2800 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2801 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2802 break;
2803 default: /* (%si) -> 4 or (%di) -> 5 */
2804 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2805 }
2806 i.rm.mode = mode_from_disp_size (i.types[op]);
2807 }
2808 else /* i.base_reg and 32/64 bit mode */
2809 {
2810 if (flag_code == CODE_64BIT
2811 && (i.types[op] & Disp))
2812 {
2813 if (i.types[op] & Disp8)
2814 i.types[op] = Disp8 | Disp32S;
2815 else
2816 i.types[op] = Disp32S;
2817 }
2818 i.rm.regmem = i.base_reg->reg_num;
2819 if ((i.base_reg->reg_flags & RegRex) != 0)
2820 i.rex |= REX_EXTZ;
2821 i.sib.base = i.base_reg->reg_num;
2822 /* x86-64 ignores REX prefix bit here to avoid decoder
2823 complications. */
2824 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2825 {
2826 default_seg = &ss;
2827 if (i.disp_operands == 0)
2828 {
2829 fake_zero_displacement = 1;
2830 i.types[op] |= Disp8;
2831 }
2832 }
2833 else if (i.base_reg->reg_num == ESP_REG_NUM)
2834 {
2835 default_seg = &ss;
2836 }
2837 i.sib.scale = i.log2_scale_factor;
2838 if (i.index_reg == 0)
2839 {
2840 /* <disp>(%esp) becomes two byte modrm with no index
2841 register. We've already stored the code for esp
2842 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2843 Any base register besides %esp will not use the
2844 extra modrm byte. */
2845 i.sib.index = NO_INDEX_REGISTER;
2846#if !SCALE1_WHEN_NO_INDEX
2847 /* Another case where we force the second modrm byte. */
2848 if (i.log2_scale_factor)
2849 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2850#endif
29b0f896
AM		 2851 }
2852 else
2853 {
2854 i.sib.index = i.index_reg->reg_num;
2855 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2856 if ((i.index_reg->reg_flags & RegRex) != 0)
2857 i.rex |= REX_EXTY;
2858 }
2859 i.rm.mode = mode_from_disp_size (i.types[op]);
2860 }
252b5132 2861
29b0f896
AM		 2862 if (fake_zero_displacement)
2863 {
2864 /* Fakes a zero displacement assuming that i.types[op]
2865 holds the correct displacement size. */
2866 expressionS *exp;
2867
2868 assert (i.op[op].disps == 0);
2869 exp = &disp_expressions[i.disp_operands++];
2870 i.op[op].disps = exp;
2871 exp->X_op = O_constant;
2872 exp->X_add_number = 0;
2873 exp->X_add_symbol = (symbolS *) 0;
2874 exp->X_op_symbol = (symbolS *) 0;
2875 }
2876 }
252b5132 2877
29b0f896
AM		 2878 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2879 (if any) based on i.tm.extension_opcode. Again, we must be
2880 careful to make sure that segment/control/debug/test/MMX
2881 registers are coded into the i.rm.reg field. */
2882 if (i.reg_operands)
2883 {
2884 unsigned int op =
2885 ((i.types[0]
2886 & (Reg | RegMMX | RegXMM
2887 | SReg2 | SReg3
2888 | Control | Debug | Test))
2889 ? 0
2890 : ((i.types[1]
2891 & (Reg | RegMMX | RegXMM
2892 | SReg2 | SReg3
2893 | Control | Debug | Test))
2894 ? 1
2895 : 2));
2896 /* If there is an extension opcode to put here, the register
2897 number must be put into the regmem field. */
2898 if (i.tm.extension_opcode != None)
2899 {
2900 i.rm.regmem = i.op[op].regs->reg_num;
2901 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2902 i.rex |= REX_EXTZ;
2903 }
2904 else
2905 {
2906 i.rm.reg = i.op[op].regs->reg_num;
2907 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2908 i.rex |= REX_EXTX;
2909 }
252b5132 2910
29b0f896
AM		 2911 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2912 must set it to 3 to indicate this is a register operand
2913 in the regmem field. */
2914 if (!i.mem_operands)
2915 i.rm.mode = 3;
2916 }
252b5132 2917
29b0f896
AM		 2918 /* Fill in i.rm.reg field with extension opcode (if any). */
2919 if (i.tm.extension_opcode != None)
2920 i.rm.reg = i.tm.extension_opcode;
2921 }
2922 return default_seg;
2923}
252b5132 2924
29b0f896
AM		 2925static void
2926output_branch ()
2927{
2928 char *p;
2929 int code16;
2930 int prefix;
2931 relax_substateT subtype;
2932 symbolS *sym;
2933 offsetT off;
2934
2935 code16 = 0;
2936 if (flag_code == CODE_16BIT)
2937 code16 = CODE16;
2938
2939 prefix = 0;
2940 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2941 {
29b0f896
AM		 2942 prefix = 1;
2943 i.prefixes -= 1;
2944 code16 ^= CODE16;
252b5132 2945 }
29b0f896
AM		 2946 /* Pentium4 branch hints. */
2947 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2948 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2949 {
29b0f896
AM		 2950 prefix++;
2951 i.prefixes--;
2952 }
2953 if (i.prefix[REX_PREFIX] != 0)
2954 {
2955 prefix++;
2956 i.prefixes--;
2f66722d
AM		 2957 }
2958
29b0f896
AM		 2959 if (i.prefixes != 0 && !intel_syntax)
2960 as_warn (_("skipping prefixes on this instruction"));
2961
2962 /* It's always a symbol; End frag & setup for relax.
2963 Make sure there is enough room in this frag for the largest
2964 instruction we may generate in md_convert_frag. This is 2
2965 bytes for the opcode and room for the prefix and largest
2966 displacement. */
2967 frag_grow (prefix + 2 + 4);
2968 /* Prefix and 1 opcode byte go in fr_fix. */
2969 p = frag_more (prefix + 1);
2970 if (i.prefix[DATA_PREFIX] != 0)
2971 *p++ = DATA_PREFIX_OPCODE;
2972 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2973 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2974 *p++ = i.prefix[SEG_PREFIX];
2975 if (i.prefix[REX_PREFIX] != 0)
2976 *p++ = i.prefix[REX_PREFIX];
2977 *p = i.tm.base_opcode;
2978
2979 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2980 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2981 else if ((cpu_arch_flags & Cpu386) != 0)
2982 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2983 else
2984 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2985 subtype |= code16;
3e73aa7c 2986
29b0f896
AM		 2987 sym = i.op[0].disps->X_add_symbol;
2988 off = i.op[0].disps->X_add_number;
3e73aa7c 2989
29b0f896
AM		 2990 if (i.op[0].disps->X_op != O_constant
2991 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2992 {
29b0f896
AM		 2993 /* Handle complex expressions. */
2994 sym = make_expr_symbol (i.op[0].disps);
2995 off = 0;
2996 }
3e73aa7c 2997
29b0f896
AM		 2998 /* 1 possible extra opcode + 4 byte displacement go in var part.
2999 Pass reloc in fr_var. */
3000 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3001}
3e73aa7c 3002
29b0f896
AM		 3003static void
3004output_jump ()
3005{
3006 char *p;
3007 int size;
3e02c1cc 3008 fixS *fixP;
29b0f896
AM		 3009
3010 if (i.tm.opcode_modifier & JumpByte)
3011 {
3012 /* This is a loop or jecxz type instruction. */
3013 size = 1;
3014 if (i.prefix[ADDR_PREFIX] != 0)
3015 {
3016 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3017 i.prefixes -= 1;
3018 }
3019 /* Pentium4 branch hints. */
3020 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3021 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3022 {
3023 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3024 i.prefixes--;
3e73aa7c
JH		 3025 }
3026 }
29b0f896
AM		 3027 else
3028 {
3029 int code16;
3e73aa7c 3030
29b0f896
AM		 3031 code16 = 0;
3032 if (flag_code == CODE_16BIT)
3033 code16 = CODE16;
3e73aa7c 3034
29b0f896
AM		 3035 if (i.prefix[DATA_PREFIX] != 0)
3036 {
3037 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3038 i.prefixes -= 1;
3039 code16 ^= CODE16;
3040 }
252b5132 3041
29b0f896
AM		 3042 size = 4;
3043 if (code16)
3044 size = 2;
3045 }
9fcc94b6 3046
29b0f896
AM		 3047 if (i.prefix[REX_PREFIX] != 0)
3048 {
3049 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3050 i.prefixes -= 1;
3051 }
252b5132 3052
29b0f896
AM		 3053 if (i.prefixes != 0 && !intel_syntax)
3054 as_warn (_("skipping prefixes on this instruction"));
e0890092 3055
29b0f896
AM		 3056 p = frag_more (1 + size);
3057 *p++ = i.tm.base_opcode;
e0890092 3058
3e02c1cc
AM		 3059 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3060 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3061
3062 /* All jumps handled here are signed, but don't use a signed limit
3063 check for 32 and 16 bit jumps as we want to allow wrap around at
3064 4G and 64k respectively. */
3065 if (size == 1)
3066 fixP->fx_signed = 1;
29b0f896 3067}
e0890092 3068
29b0f896
AM		 3069static void
3070output_interseg_jump ()
3071{
3072 char *p;
3073 int size;
3074 int prefix;
3075 int code16;
252b5132 3076
29b0f896
AM		 3077 code16 = 0;
3078 if (flag_code == CODE_16BIT)
3079 code16 = CODE16;
a217f122 3080
29b0f896
AM		 3081 prefix = 0;
3082 if (i.prefix[DATA_PREFIX] != 0)
3083 {
3084 prefix = 1;
3085 i.prefixes -= 1;
3086 code16 ^= CODE16;
3087 }
3088 if (i.prefix[REX_PREFIX] != 0)
3089 {
3090 prefix++;
3091 i.prefixes -= 1;
3092 }
252b5132 3093
29b0f896
AM		 3094 size = 4;
3095 if (code16)
3096 size = 2;
252b5132 3097
29b0f896
AM		 3098 if (i.prefixes != 0 && !intel_syntax)
3099 as_warn (_("skipping prefixes on this instruction"));
252b5132 3100
29b0f896
AM		 3101 /* 1 opcode; 2 segment; offset */
3102 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3103
29b0f896
AM		 3104 if (i.prefix[DATA_PREFIX] != 0)
3105 *p++ = DATA_PREFIX_OPCODE;
252b5132 3106
29b0f896
AM		 3107 if (i.prefix[REX_PREFIX] != 0)
3108 *p++ = i.prefix[REX_PREFIX];
252b5132 3109
29b0f896
AM		 3110 *p++ = i.tm.base_opcode;
3111 if (i.op[1].imms->X_op == O_constant)
3112 {
3113 offsetT n = i.op[1].imms->X_add_number;
252b5132 3114
29b0f896
AM		 3115 if (size == 2
3116 && !fits_in_unsigned_word (n)
3117 && !fits_in_signed_word (n))
3118 {
3119 as_bad (_("16-bit jump out of range"));
3120 return;
3121 }
3122 md_number_to_chars (p, n, size);
3123 }
3124 else
3125 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3126 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3127 if (i.op[0].imms->X_op != O_constant)
3128 as_bad (_("can't handle non absolute segment in `%s'"),
3129 i.tm.name);
3130 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3131}
a217f122 3132
29b0f896
AM		 3133static void
3134output_insn ()
3135{
2bbd9c25
JJ		 3136 fragS *insn_start_frag;
3137 offsetT insn_start_off;
3138
29b0f896
AM		 3139 /* Tie dwarf2 debug info to the address at the start of the insn.
3140 We can't do this after the insn has been output as the current
3141 frag may have been closed off. eg. by frag_var. */
3142 dwarf2_emit_insn (0);
3143
2bbd9c25
JJ		 3144 insn_start_frag = frag_now;
3145 insn_start_off = frag_now_fix ();
3146
29b0f896
AM		 3147 /* Output jumps. */
3148 if (i.tm.opcode_modifier & Jump)
3149 output_branch ();
3150 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3151 output_jump ();
3152 else if (i.tm.opcode_modifier & JumpInterSegment)
3153 output_interseg_jump ();
3154 else
3155 {
3156 /* Output normal instructions here. */
3157 char *p;
3158 unsigned char *q;
252b5132 3159
0f10071e
ML		 3160 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3161 have 3 bytes. We may use one more higher byte to specify a prefix
3162 the instruction requires. */
3163 if ((i.tm.cpu_flags & CpuPadLock) != 0
3164 && (i.tm.base_opcode & 0xff000000) != 0)
3165 {
3166 unsigned int prefix;
3167 prefix = (i.tm.base_opcode >> 24) & 0xff;
3168
3169 if (prefix != REPE_PREFIX_OPCODE
3170 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3171 add_prefix (prefix);
3172 }
3173 else
3174 if ((i.tm.cpu_flags & CpuPadLock) == 0
3175 && (i.tm.base_opcode & 0xff0000) != 0)
3176 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3177
29b0f896
AM		 3178 /* The prefix bytes. */
3179 for (q = i.prefix;
3180 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3181 q++)
3182 {
3183 if (*q)
3184 {
3185 p = frag_more (1);
3186 md_number_to_chars (p, (valueT) *q, 1);
3187 }
3188 }
252b5132 3189
29b0f896
AM		 3190 /* Now the opcode; be careful about word order here! */
3191 if (fits_in_unsigned_byte (i.tm.base_opcode))
3192 {
3193 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3194 }
3195 else
3196 {
0f10071e
ML		 3197 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3198 {
3199 p = frag_more (3);
3200 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3201 }
3202 else
3203 p = frag_more (2);
3204
29b0f896
AM		 3205 /* Put out high byte first: can't use md_number_to_chars! */
3206 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3207 *p = i.tm.base_opcode & 0xff;
3208 }
3e73aa7c 3209
29b0f896
AM		 3210 /* Now the modrm byte and sib byte (if present). */
3211 if (i.tm.opcode_modifier & Modrm)
3212 {
3213 p = frag_more (1);
3214 md_number_to_chars (p,
3215 (valueT) (i.rm.regmem << 0
3216 | i.rm.reg << 3
3217 | i.rm.mode << 6),
3218 1);
3219 /* If i.rm.regmem == ESP (4)
3220 && i.rm.mode != (Register mode)
3221 && not 16 bit
3222 ==> need second modrm byte. */
3223 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3224 && i.rm.mode != 3
3225 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3226 {
3227 p = frag_more (1);
3228 md_number_to_chars (p,
3229 (valueT) (i.sib.base << 0
3230 | i.sib.index << 3
3231 | i.sib.scale << 6),
3232 1);
3233 }
3234 }
3e73aa7c 3235
29b0f896 3236 if (i.disp_operands)
2bbd9c25 3237 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3238
29b0f896 3239 if (i.imm_operands)
2bbd9c25 3240 output_imm (insn_start_frag, insn_start_off);
29b0f896 3241 }
252b5132 3242
29b0f896
AM		 3243#ifdef DEBUG386
3244 if (flag_debug)
3245 {
3246 pi (line, &i);
3247 }
3248#endif /* DEBUG386 */
3249}
252b5132 3250
29b0f896 3251static void
2bbd9c25
JJ		 3252output_disp (insn_start_frag, insn_start_off)
3253 fragS *insn_start_frag;
3254 offsetT insn_start_off;
29b0f896
AM		 3255{
3256 char *p;
3257 unsigned int n;
252b5132 3258
29b0f896
AM		 3259 for (n = 0; n < i.operands; n++)
3260 {
3261 if (i.types[n] & Disp)
3262 {
3263 if (i.op[n].disps->X_op == O_constant)
3264 {
3265 int size;
3266 offsetT val;
252b5132 3267
29b0f896
AM		 3268 size = 4;
3269 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3270 {
3271 size = 2;
3272 if (i.types[n] & Disp8)
3273 size = 1;
3274 if (i.types[n] & Disp64)
3275 size = 8;
3276 }
3277 val = offset_in_range (i.op[n].disps->X_add_number,
3278 size);
3279 p = frag_more (size);
3280 md_number_to_chars (p, val, size);
3281 }
3282 else
3283 {
f86103b7 3284 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3285 int size = 4;
3286 int sign = 0;
3287 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3288
3289 /* The PC relative address is computed relative
3290 to the instruction boundary, so in case immediate
3291 fields follows, we need to adjust the value. */
3292 if (pcrel && i.imm_operands)
3293 {
3294 int imm_size = 4;
3295 unsigned int n1;
252b5132 3296
29b0f896
AM		 3297 for (n1 = 0; n1 < i.operands; n1++)
3298 if (i.types[n1] & Imm)
252b5132 3299 {
29b0f896 3300 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3301 {
29b0f896
AM		 3302 imm_size = 2;
3303 if (i.types[n1] & (Imm8 | Imm8S))
3304 imm_size = 1;
3305 if (i.types[n1] & Imm64)
3306 imm_size = 8;
252b5132 3307 }
29b0f896 3308 break;
252b5132 3309 }
29b0f896
AM		 3310 /* We should find the immediate. */
3311 if (n1 == i.operands)
3312 abort ();
3313 i.op[n].disps->X_add_number -= imm_size;
3314 }
520dc8e8 3315
29b0f896
AM		 3316 if (i.types[n] & Disp32S)
3317 sign = 1;
3e73aa7c 3318
29b0f896
AM		 3319 if (i.types[n] & (Disp16 | Disp64))
3320 {
3321 size = 2;
3322 if (i.types[n] & Disp64)
3323 size = 8;
3324 }
520dc8e8 3325
29b0f896 3326 p = frag_more (size);
2bbd9c25 3327 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
2bbd9c25
JJ		 3328 if (reloc_type == BFD_RELOC_32
3329 && GOT_symbol
3330 && GOT_symbol == i.op[n].disps->X_add_symbol
3331 && (i.op[n].disps->X_op == O_symbol
3332 || (i.op[n].disps->X_op == O_add
3333 && ((symbol_get_value_expression
3334 (i.op[n].disps->X_op_symbol)->X_op)
3335 == O_subtract))))
3336 {
3337 offsetT add;
3338
3339 if (insn_start_frag == frag_now)
3340 add = (p - frag_now->fr_literal) - insn_start_off;
3341 else
3342 {
3343 fragS *fr;
3344
3345 add = insn_start_frag->fr_fix - insn_start_off;
3346 for (fr = insn_start_frag->fr_next;
3347 fr && fr != frag_now; fr = fr->fr_next)
3348 add += fr->fr_fix;
3349 add += p - frag_now->fr_literal;
3350 }
3351
3352 /* We don't support dynamic linking on x86-64 yet. */
3353 if (flag_code == CODE_64BIT)
3354 abort ();
3355 reloc_type = BFD_RELOC_386_GOTPC;
3356 i.op[n].disps->X_add_number += add;
3357 }
062cd5e7 3358 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3359 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3360 }
3361 }
3362 }
3363}
252b5132 3364
29b0f896 3365static void
2bbd9c25
JJ		 3366output_imm (insn_start_frag, insn_start_off)
3367 fragS *insn_start_frag;
3368 offsetT insn_start_off;
29b0f896
AM		 3369{
3370 char *p;
3371 unsigned int n;
252b5132 3372
29b0f896
AM		 3373 for (n = 0; n < i.operands; n++)
3374 {
3375 if (i.types[n] & Imm)
3376 {
3377 if (i.op[n].imms->X_op == O_constant)
3378 {
3379 int size;
3380 offsetT val;
b4cac588 3381
29b0f896
AM		 3382 size = 4;
3383 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3384 {
3385 size = 2;
3386 if (i.types[n] & (Imm8 | Imm8S))
3387 size = 1;
3388 else if (i.types[n] & Imm64)
3389 size = 8;
3390 }
3391 val = offset_in_range (i.op[n].imms->X_add_number,
3392 size);
3393 p = frag_more (size);
3394 md_number_to_chars (p, val, size);
3395 }
3396 else
3397 {
3398 /* Not absolute_section.
3399 Need a 32-bit fixup (don't support 8bit
3400 non-absolute imms). Try to support other
3401 sizes ... */
f86103b7 3402 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3403 int size = 4;
3404 int sign = 0;
3405
3406 if ((i.types[n] & (Imm32S))
3407 && i.suffix == QWORD_MNEM_SUFFIX)
3408 sign = 1;
3409 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3410 {
3411 size = 2;
3412 if (i.types[n] & (Imm8 | Imm8S))
3413 size = 1;
3414 if (i.types[n] & Imm64)
3415 size = 8;
3416 }
520dc8e8 3417
29b0f896
AM		 3418 p = frag_more (size);
3419 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3420
2bbd9c25
JJ		 3421 /* This is tough to explain. We end up with this one if we
3422 * have operands that look like
3423 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3424 * obtain the absolute address of the GOT, and it is strongly
3425 * preferable from a performance point of view to avoid using
3426 * a runtime relocation for this. The actual sequence of
3427 * instructions often look something like:
3428 *
3429 * call .L66
3430 * .L66:
3431 * popl %ebx
3432 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3433 *
3434 * The call and pop essentially return the absolute address
3435 * of the label .L66 and store it in %ebx. The linker itself
3436 * will ultimately change the first operand of the addl so
3437 * that %ebx points to the GOT, but to keep things simple, the
3438 * .o file must have this operand set so that it generates not
3439 * the absolute address of .L66, but the absolute address of
3440 * itself. This allows the linker itself simply treat a GOTPC
3441 * relocation as asking for a pcrel offset to the GOT to be
3442 * added in, and the addend of the relocation is stored in the
3443 * operand field for the instruction itself.
3444 *
3445 * Our job here is to fix the operand so that it would add
3446 * the correct offset so that %ebx would point to itself. The
3447 * thing that is tricky is that .-.L66 will point to the
3448 * beginning of the instruction, so we need to further modify
3449 * the operand so that it will point to itself. There are
3450 * other cases where you have something like:
3451 *
3452 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3453 *
3454 * and here no correction would be required. Internally in
3455 * the assembler we treat operands of this form as not being
3456 * pcrel since the '.' is explicitly mentioned, and I wonder
3457 * whether it would simplify matters to do it this way. Who
3458 * knows. In earlier versions of the PIC patches, the
3459 * pcrel_adjust field was used to store the correction, but
3460 * since the expression is not pcrel, I felt it would be
3461 * confusing to do it this way. */
3462
29b0f896
AM		 3463 if (reloc_type == BFD_RELOC_32
3464 && GOT_symbol
3465 && GOT_symbol == i.op[n].imms->X_add_symbol
3466 && (i.op[n].imms->X_op == O_symbol
3467 || (i.op[n].imms->X_op == O_add
3468 && ((symbol_get_value_expression
3469 (i.op[n].imms->X_op_symbol)->X_op)
3470 == O_subtract))))
3471 {
2bbd9c25
JJ		 3472 offsetT add;
3473
3474 if (insn_start_frag == frag_now)
3475 add = (p - frag_now->fr_literal) - insn_start_off;
3476 else
3477 {
3478 fragS *fr;
3479
3480 add = insn_start_frag->fr_fix - insn_start_off;
3481 for (fr = insn_start_frag->fr_next;
3482 fr && fr != frag_now; fr = fr->fr_next)
3483 add += fr->fr_fix;
3484 add += p - frag_now->fr_literal;
3485 }
3486
29b0f896
AM		 3487 /* We don't support dynamic linking on x86-64 yet. */
3488 if (flag_code == CODE_64BIT)
3489 abort ();
3490 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3491 i.op[n].imms->X_add_number += add;
29b0f896 3492 }
29b0f896
AM		 3493 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3494 i.op[n].imms, 0, reloc_type);
3495 }
3496 }
3497 }
252b5132
RH		 3498}
3499\f
f3c180ae 3500#ifndef LEX_AT
f86103b7 3501static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
f3c180ae
AM		 3502
3503/* Parse operands of the form
3504 <symbol>@GOTOFF+<nnn>
3505 and similar .plt or .got references.
3506
3507 If we find one, set up the correct relocation in RELOC and copy the
3508 input string, minus the `@GOTOFF' into a malloc'd buffer for
3509 parsing by the calling routine. Return this buffer, and if ADJUST
3510 is non-null set it to the length of the string we removed from the
3511 input line. Otherwise return NULL. */
3512static char *
3513lex_got (reloc, adjust)
f86103b7 3514 enum bfd_reloc_code_real *reloc;
f3c180ae
AM		 3515 int *adjust;
3516{
3517 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3518 static const struct {
3519 const char *str;
f86103b7 3520 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
f3c180ae 3521 } gotrel[] = {
13ae64f3
JJ		 3522 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3523 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3524 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3525 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3526 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3527 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3528 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3529 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3530 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3531 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3532 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3533 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3534 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3535 };
3536 char *cp;
3537 unsigned int j;
3538
3539 for (cp = input_line_pointer; *cp != '@'; cp++)
3540 if (is_end_of_line[(unsigned char) *cp])
3541 return NULL;
3542
3543 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3544 {
3545 int len;
3546
3547 len = strlen (gotrel[j].str);
28f81592 3548 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3549 {
3550 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3551 {
28f81592
AM		 3552 int first, second;
3553 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3554
3555 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3556 if (adjust)
3557 *adjust = len;
f3c180ae
AM		 3558
3559 if (GOT_symbol == NULL)
3560 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3561
3562 /* Replace the relocation token with ' ', so that
3563 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3564
3565 /* The length of the first part of our input line. */
f3c180ae 3566 first = cp - input_line_pointer;
28f81592
AM		 3567
3568 /* The second part goes from after the reloc token until
3569 (and including) an end_of_line char. Don't use strlen
3570 here as the end_of_line char may not be a NUL. */
3571 past_reloc = cp + 1 + len;
3572 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3573 ;
3574 second = cp - past_reloc;
3575
3576 /* Allocate and copy string. The trailing NUL shouldn't
3577 be necessary, but be safe. */
3578 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3579 memcpy (tmpbuf, input_line_pointer, first);
3580 tmpbuf[first] = ' ';
28f81592
AM		 3581 memcpy (tmpbuf + first + 1, past_reloc, second);
3582 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3583 return tmpbuf;
3584 }
3585
3586 as_bad (_("@%s reloc is not supported in %s bit mode"),
3587 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3588 return NULL;
3589 }
3590 }
3591
3592 /* Might be a symbol version string. Don't as_bad here. */
3593 return NULL;
3594}
3595
3596/* x86_cons_fix_new is called via the expression parsing code when a
3597 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3598static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3599
3600void
3601x86_cons_fix_new (frag, off, len, exp)
3602 fragS *frag;
3603 unsigned int off;
3604 unsigned int len;
3605 expressionS *exp;
3606{
f86103b7 3607 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
f3c180ae
AM		 3608 got_reloc = NO_RELOC;
3609 fix_new_exp (frag, off, len, exp, 0, r);
3610}
3611
3612void
3613x86_cons (exp, size)
3614 expressionS *exp;
3615 int size;
3616{
3617 if (size == 4)
3618 {
3619 /* Handle @GOTOFF and the like in an expression. */
3620 char *save;
3621 char *gotfree_input_line;
3622 int adjust;
3623
3624 save = input_line_pointer;
3625 gotfree_input_line = lex_got (&got_reloc, &adjust);
3626 if (gotfree_input_line)
3627 input_line_pointer = gotfree_input_line;
3628
3629 expression (exp);
3630
3631 if (gotfree_input_line)
3632 {
3633 /* expression () has merrily parsed up to the end of line,
3634 or a comma - in the wrong buffer. Transfer how far
3635 input_line_pointer has moved to the right buffer. */
3636 input_line_pointer = (save
3637 + (input_line_pointer - gotfree_input_line)
3638 + adjust);
3639 free (gotfree_input_line);
3640 }
3641 }
3642 else
3643 expression (exp);
3644}
3645#endif
3646
6482c264
NC		 3647#ifdef TE_PE
3648
3649#define O_secrel (O_max + 1)
3650
3651void
3652x86_pe_cons_fix_new (frag, off, len, exp)
3653 fragS *frag;
3654 unsigned int off;
3655 unsigned int len;
3656 expressionS *exp;
3657{
3658 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3659
3660 if (exp->X_op == O_secrel)
3661 {
3662 exp->X_op = O_symbol;
3663 r = BFD_RELOC_32_SECREL;
3664 }
3665
3666 fix_new_exp (frag, off, len, exp, 0, r);
3667}
3668
3669static void
3670pe_directive_secrel (dummy)
3671 int dummy ATTRIBUTE_UNUSED;
3672{
3673 expressionS exp;
3674
3675 do
3676 {
3677 expression (&exp);
3678 if (exp.X_op == O_symbol)
3679 exp.X_op = O_secrel;
3680
3681 emit_expr (&exp, 4);
3682 }
3683 while (*input_line_pointer++ == ',');
3684
3685 input_line_pointer--;
3686 demand_empty_rest_of_line ();
3687}
3688
3689#endif
3690
252b5132
RH		 3691static int i386_immediate PARAMS ((char *));
3692
3693static int
3694i386_immediate (imm_start)
3695 char *imm_start;
3696{
3697 char *save_input_line_pointer;
f3c180ae
AM		 3698#ifndef LEX_AT
3699 char *gotfree_input_line;
3700#endif
252b5132 3701 segT exp_seg = 0;
47926f60 3702 expressionS *exp;
252b5132
RH		 3703
3704 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3705 {
d0b47220 3706 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3707 return 0;
3708 }
3709
3710 exp = &im_expressions[i.imm_operands++];
520dc8e8 3711 i.op[this_operand].imms = exp;
252b5132
RH		 3712
3713 if (is_space_char (*imm_start))
3714 ++imm_start;
3715
3716 save_input_line_pointer = input_line_pointer;
3717 input_line_pointer = imm_start;
3718
3719#ifndef LEX_AT
f3c180ae
AM		 3720 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3721 if (gotfree_input_line)
3722 input_line_pointer = gotfree_input_line;
252b5132
RH		 3723#endif
3724
3725 exp_seg = expression (exp);
3726
83183c0c 3727 SKIP_WHITESPACE ();
252b5132 3728 if (*input_line_pointer)
f3c180ae 3729 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3730
3731 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3732#ifndef LEX_AT
3733 if (gotfree_input_line)
3734 free (gotfree_input_line);
3735#endif
252b5132 3736
2daf4fd8 3737 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3738 {
47926f60 3739 /* Missing or bad expr becomes absolute 0. */
d0b47220 3740 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3741 imm_start);
252b5132
RH		 3742 exp->X_op = O_constant;
3743 exp->X_add_number = 0;
3744 exp->X_add_symbol = (symbolS *) 0;
3745 exp->X_op_symbol = (symbolS *) 0;
252b5132 3746 }
3e73aa7c 3747 else if (exp->X_op == O_constant)
252b5132 3748 {
47926f60 3749 /* Size it properly later. */
3e73aa7c
JH		 3750 i.types[this_operand] |= Imm64;
3751 /* If BFD64, sign extend val. */
3752 if (!use_rela_relocations)
3753 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3754 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3755 }
4c63da97 3756#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 3757 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3758 && exp_seg != absolute_section
47926f60 3759 && exp_seg != text_section
24eab124
AM		 3760 && exp_seg != data_section
3761 && exp_seg != bss_section
3762 && exp_seg != undefined_section
f86103b7 3763 && !bfd_is_com_section (exp_seg))
252b5132 3764 {
d0b47220 3765 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 3766 return 0;
3767 }
3768#endif
3769 else
3770 {
3771 /* This is an address. The size of the address will be
24eab124 3772 determined later, depending on destination register,
3e73aa7c
JH		 3773 suffix, or the default for the section. */
3774 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3775 }
3776
3777 return 1;
3778}
3779
551c1ca1 3780static char *i386_scale PARAMS ((char *));
252b5132 3781
551c1ca1 3782static char *
252b5132
RH		 3783i386_scale (scale)
3784 char *scale;
3785{
551c1ca1
AM		 3786 offsetT val;
3787 char *save = input_line_pointer;
252b5132 3788
551c1ca1
AM		 3789 input_line_pointer = scale;
3790 val = get_absolute_expression ();
3791
3792 switch (val)
252b5132 3793 {
551c1ca1
AM		 3794 case 0:
3795 case 1:
252b5132
RH		 3796 i.log2_scale_factor = 0;
3797 break;
551c1ca1 3798 case 2:
252b5132
RH		 3799 i.log2_scale_factor = 1;
3800 break;
551c1ca1 3801 case 4:
252b5132
RH		 3802 i.log2_scale_factor = 2;
3803 break;
551c1ca1 3804 case 8:
252b5132
RH		 3805 i.log2_scale_factor = 3;
3806 break;
3807 default:
252b5132 3808 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3809 scale);
551c1ca1
AM		 3810 input_line_pointer = save;
3811 return NULL;
252b5132 3812 }
29b0f896 3813 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3814 {
3815 as_warn (_("scale factor of %d without an index register"),
24eab124 3816 1 << i.log2_scale_factor);
252b5132
RH		 3817#if SCALE1_WHEN_NO_INDEX
3818 i.log2_scale_factor = 0;
3819#endif
3820 }
551c1ca1
AM		 3821 scale = input_line_pointer;
3822 input_line_pointer = save;
3823 return scale;
252b5132
RH		 3824}
3825
3826static int i386_displacement PARAMS ((char *, char *));
3827
3828static int
3829i386_displacement (disp_start, disp_end)
3830 char *disp_start;
3831 char *disp_end;
3832{
29b0f896 3833 expressionS *exp;
252b5132
RH		 3834 segT exp_seg = 0;
3835 char *save_input_line_pointer;
f3c180ae
AM		 3836#ifndef LEX_AT
3837 char *gotfree_input_line;
3838#endif
252b5132
RH		 3839 int bigdisp = Disp32;
3840
3e73aa7c 3841 if (flag_code == CODE_64BIT)
7ecd2f8b 3842 {
29b0f896
AM		 3843 if (i.prefix[ADDR_PREFIX] == 0)
3844 bigdisp = Disp64;
7ecd2f8b
JH		 3845 }
3846 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3847 bigdisp = Disp16;
252b5132
RH		 3848 i.types[this_operand] |= bigdisp;
3849
3850 exp = &disp_expressions[i.disp_operands];
520dc8e8 3851 i.op[this_operand].disps = exp;
252b5132
RH		 3852 i.disp_operands++;
3853 save_input_line_pointer = input_line_pointer;
3854 input_line_pointer = disp_start;
3855 END_STRING_AND_SAVE (disp_end);
3856
3857#ifndef GCC_ASM_O_HACK
3858#define GCC_ASM_O_HACK 0
3859#endif
3860#if GCC_ASM_O_HACK
3861 END_STRING_AND_SAVE (disp_end + 1);
3862 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3863 && displacement_string_end[-1] == '+')
252b5132
RH		 3864 {
3865 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3866 constraint within gcc asm statements.
3867 For instance:
3868
3869 #define _set_tssldt_desc(n,addr,limit,type) \
3870 __asm__ __volatile__ ( \
3871 "movw %w2,%0\n\t" \
3872 "movw %w1,2+%0\n\t" \
3873 "rorl $16,%1\n\t" \
3874 "movb %b1,4+%0\n\t" \
3875 "movb %4,5+%0\n\t" \
3876 "movb $0,6+%0\n\t" \
3877 "movb %h1,7+%0\n\t" \
3878 "rorl $16,%1" \
3879 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3880
3881 This works great except that the output assembler ends
3882 up looking a bit weird if it turns out that there is
3883 no offset. You end up producing code that looks like:
3884
3885 #APP
3886 movw $235,(%eax)
3887 movw %dx,2+(%eax)
3888 rorl $16,%edx
3889 movb %dl,4+(%eax)
3890 movb $137,5+(%eax)
3891 movb $0,6+(%eax)
3892 movb %dh,7+(%eax)
3893 rorl $16,%edx
3894 #NO_APP
3895
47926f60 3896 So here we provide the missing zero. */
24eab124
AM		 3897
3898 *displacement_string_end = '0';
252b5132
RH		 3899 }
3900#endif
3901#ifndef LEX_AT
f3c180ae
AM		 3902 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3903 if (gotfree_input_line)
3904 input_line_pointer = gotfree_input_line;
252b5132
RH		 3905#endif
3906
24eab124 3907 exp_seg = expression (exp);
252b5132 3908
636c26b0
AM		 3909 SKIP_WHITESPACE ();
3910 if (*input_line_pointer)
3911 as_bad (_("junk `%s' after expression"), input_line_pointer);
3912#if GCC_ASM_O_HACK
3913 RESTORE_END_STRING (disp_end + 1);
3914#endif
3915 RESTORE_END_STRING (disp_end);
3916 input_line_pointer = save_input_line_pointer;
3917#ifndef LEX_AT
3918 if (gotfree_input_line)
3919 free (gotfree_input_line);
3920#endif
3921
24eab124
AM		 3922 /* We do this to make sure that the section symbol is in
3923 the symbol table. We will ultimately change the relocation
47926f60 3924 to be relative to the beginning of the section. */
1ae12ab7
AM		 3925 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3926 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3927 {
636c26b0
AM		 3928 if (exp->X_op != O_symbol)
3929 {
3930 as_bad (_("bad expression used with @%s"),
3931 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3932 ? "GOTPCREL"
3933 : "GOTOFF"));
3934 return 0;
3935 }
3936
e5cb08ac 3937 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3938 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3939 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3940 exp->X_op = O_subtract;
3941 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3942 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3943 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3944 else
29b0f896 3945 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3946 }
252b5132 3947
2daf4fd8
AM		 3948 if (exp->X_op == O_absent || exp->X_op == O_big)
3949 {
47926f60 3950 /* Missing or bad expr becomes absolute 0. */
d0b47220 3951 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3952 disp_start);
3953 exp->X_op = O_constant;
3954 exp->X_add_number = 0;
3955 exp->X_add_symbol = (symbolS *) 0;
3956 exp->X_op_symbol = (symbolS *) 0;
3957 }
3958
4c63da97 3959#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3960 if (exp->X_op != O_constant
45288df1 3961 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3962 && exp_seg != absolute_section
45288df1
AM		 3963 && exp_seg != text_section
3964 && exp_seg != data_section
3965 && exp_seg != bss_section
31312f95 3966 && exp_seg != undefined_section
f86103b7 3967 && !bfd_is_com_section (exp_seg))
24eab124 3968 {
d0b47220 3969 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 3970 return 0;
3971 }
252b5132 3972#endif
3e73aa7c
JH		 3973 else if (flag_code == CODE_64BIT)
3974 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3975 return 1;
3976}
3977
e5cb08ac 3978static int i386_index_check PARAMS ((const char *));
252b5132 3979
eecb386c 3980/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3981 Return 1 on success, 0 on a failure. */
3982
252b5132 3983static int
eecb386c
AM		 3984i386_index_check (operand_string)
3985 const char *operand_string;
252b5132 3986{
3e73aa7c 3987 int ok;
24eab124 3988#if INFER_ADDR_PREFIX
eecb386c
AM		 3989 int fudged = 0;
3990
24eab124
AM		 3991 tryprefix:
3992#endif
3e73aa7c
JH		 3993 ok = 1;
3994 if (flag_code == CODE_64BIT)
3995 {
7ecd2f8b
JH		 3996 if (i.prefix[ADDR_PREFIX] == 0)
3997 {
3998 /* 64bit checks. */
3999 if ((i.base_reg
4000 && ((i.base_reg->reg_type & Reg64) == 0)
4001 && (i.base_reg->reg_type != BaseIndex
4002 || i.index_reg))
4003 || (i.index_reg
29b0f896
AM		 4004 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
4005 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 4006 ok = 0;
4007 }
4008 else
4009 {
4010 /* 32bit checks. */
4011 if ((i.base_reg
4012 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4013 || (i.index_reg
29b0f896
AM		 4014 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4015 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 4016 ok = 0;
4017 }
3e73aa7c
JH		 4018 }
4019 else
4020 {
4021 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4022 {
4023 /* 16bit checks. */
4024 if ((i.base_reg
29b0f896
AM		 4025 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4026 != (Reg16 | BaseIndex)))
3e73aa7c 4027 || (i.index_reg
29b0f896
AM		 4028 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4029 != (Reg16 | BaseIndex))
4030 || !(i.base_reg
4031 && i.base_reg->reg_num < 6
4032 && i.index_reg->reg_num >= 6
4033 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4034 ok = 0;
4035 }
4036 else
e5cb08ac 4037 {
3e73aa7c
JH		 4038 /* 32bit checks. */
4039 if ((i.base_reg
4040 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4041 || (i.index_reg
29b0f896
AM		 4042 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4043 != (Reg32 | BaseIndex))))
e5cb08ac 4044 ok = 0;
3e73aa7c
JH		 4045 }
4046 }
4047 if (!ok)
24eab124
AM		 4048 {
4049#if INFER_ADDR_PREFIX
3e73aa7c
JH		 4050 if (flag_code != CODE_64BIT
4051 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 4052 {
4053 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4054 i.prefixes += 1;
b23bac36
AM		 4055 /* Change the size of any displacement too. At most one of
4056 Disp16 or Disp32 is set.
4057 FIXME. There doesn't seem to be any real need for separate
4058 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4059 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 4060 if (i.types[this_operand] & (Disp16 | Disp32))
4061 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4062 fudged = 1;
24eab124
AM		 4063 goto tryprefix;
4064 }
eecb386c
AM		 4065 if (fudged)
4066 as_bad (_("`%s' is not a valid base/index expression"),
4067 operand_string);
4068 else
c388dee8 4069#endif
eecb386c
AM		 4070 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4071 operand_string,
3e73aa7c 4072 flag_code_names[flag_code]);
eecb386c 4073 return 0;
24eab124
AM		 4074 }
4075 return 1;
4076}
252b5132 4077
252b5132 4078/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4079 on error. */
252b5132 4080
252b5132
RH		 4081static int
4082i386_operand (operand_string)
4083 char *operand_string;
4084{
af6bdddf
AM		 4085 const reg_entry *r;
4086 char *end_op;
24eab124 4087 char *op_string = operand_string;
252b5132 4088
24eab124 4089 if (is_space_char (*op_string))
252b5132
RH		 4090 ++op_string;
4091
24eab124 4092 /* We check for an absolute prefix (differentiating,
47926f60 4093 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4094 if (*op_string == ABSOLUTE_PREFIX)
4095 {
4096 ++op_string;
4097 if (is_space_char (*op_string))
4098 ++op_string;
4099 i.types[this_operand] |= JumpAbsolute;
4100 }
252b5132 4101
47926f60 4102 /* Check if operand is a register. */
af6bdddf
AM		 4103 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4104 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4105 {
24eab124
AM		 4106 /* Check for a segment override by searching for ':' after a
4107 segment register. */
4108 op_string = end_op;
4109 if (is_space_char (*op_string))
4110 ++op_string;
4111 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4112 {
4113 switch (r->reg_num)
4114 {
4115 case 0:
4116 i.seg[i.mem_operands] = &es;
4117 break;
4118 case 1:
4119 i.seg[i.mem_operands] = &cs;
4120 break;
4121 case 2:
4122 i.seg[i.mem_operands] = &ss;
4123 break;
4124 case 3:
4125 i.seg[i.mem_operands] = &ds;
4126 break;
4127 case 4:
4128 i.seg[i.mem_operands] = &fs;
4129 break;
4130 case 5:
4131 i.seg[i.mem_operands] = &gs;
4132 break;
4133 }
252b5132 4134
24eab124 4135 /* Skip the ':' and whitespace. */
252b5132
RH		 4136 ++op_string;
4137 if (is_space_char (*op_string))
24eab124 4138 ++op_string;
252b5132 4139
24eab124
AM		 4140 if (!is_digit_char (*op_string)
4141 && !is_identifier_char (*op_string)
4142 && *op_string != '('
4143 && *op_string != ABSOLUTE_PREFIX)
4144 {
4145 as_bad (_("bad memory operand `%s'"), op_string);
4146 return 0;
4147 }
47926f60 4148 /* Handle case of %es:*foo. */
24eab124
AM		 4149 if (*op_string == ABSOLUTE_PREFIX)
4150 {
4151 ++op_string;
4152 if (is_space_char (*op_string))
4153 ++op_string;
4154 i.types[this_operand] |= JumpAbsolute;
4155 }
4156 goto do_memory_reference;
4157 }
4158 if (*op_string)
4159 {
d0b47220 4160 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4161 return 0;
4162 }
4163 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4164 i.op[this_operand].regs = r;
24eab124
AM		 4165 i.reg_operands++;
4166 }
af6bdddf
AM		 4167 else if (*op_string == REGISTER_PREFIX)
4168 {
4169 as_bad (_("bad register name `%s'"), op_string);
4170 return 0;
4171 }
24eab124 4172 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4173 {
24eab124
AM		 4174 ++op_string;
4175 if (i.types[this_operand] & JumpAbsolute)
4176 {
d0b47220 4177 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4178 return 0;
4179 }
4180 if (!i386_immediate (op_string))
4181 return 0;
4182 }
4183 else if (is_digit_char (*op_string)
4184 || is_identifier_char (*op_string)
e5cb08ac 4185 || *op_string == '(')
24eab124 4186 {
47926f60 4187 /* This is a memory reference of some sort. */
af6bdddf 4188 char *base_string;
252b5132 4189
47926f60 4190 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4191 char *displacement_string_start;
4192 char *displacement_string_end;
252b5132 4193
24eab124 4194 do_memory_reference:
24eab124
AM		 4195 if ((i.mem_operands == 1
4196 && (current_templates->start->opcode_modifier & IsString) == 0)
4197 || i.mem_operands == 2)
4198 {
4199 as_bad (_("too many memory references for `%s'"),
4200 current_templates->start->name);
4201 return 0;
4202 }
252b5132 4203
24eab124
AM		 4204 /* Check for base index form. We detect the base index form by
4205 looking for an ')' at the end of the operand, searching
4206 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4207 after the '('. */
af6bdddf 4208 base_string = op_string + strlen (op_string);
c3332e24 4209
af6bdddf
AM		 4210 --base_string;
4211 if (is_space_char (*base_string))
4212 --base_string;
252b5132 4213
47926f60 4214 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4215 displacement_string_start = op_string;
4216 displacement_string_end = base_string + 1;
252b5132 4217
24eab124
AM		 4218 if (*base_string == ')')
4219 {
af6bdddf 4220 char *temp_string;
24eab124
AM		 4221 unsigned int parens_balanced = 1;
4222 /* We've already checked that the number of left & right ()'s are
47926f60 4223 equal, so this loop will not be infinite. */
24eab124
AM		 4224 do
4225 {
4226 base_string--;
4227 if (*base_string == ')')
4228 parens_balanced++;
4229 if (*base_string == '(')
4230 parens_balanced--;
4231 }
4232 while (parens_balanced);
c3332e24 4233
af6bdddf 4234 temp_string = base_string;
c3332e24 4235
24eab124 4236 /* Skip past '(' and whitespace. */
252b5132
RH		 4237 ++base_string;
4238 if (is_space_char (*base_string))
24eab124 4239 ++base_string;
252b5132 4240
af6bdddf
AM		 4241 if (*base_string == ','
4242 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4243 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4244 {
af6bdddf 4245 displacement_string_end = temp_string;
252b5132 4246
af6bdddf 4247 i.types[this_operand] |= BaseIndex;
252b5132 4248
af6bdddf 4249 if (i.base_reg)
24eab124 4250 {
24eab124
AM		 4251 base_string = end_op;
4252 if (is_space_char (*base_string))
4253 ++base_string;
af6bdddf
AM		 4254 }
4255
4256 /* There may be an index reg or scale factor here. */
4257 if (*base_string == ',')
4258 {
4259 ++base_string;
4260 if (is_space_char (*base_string))
4261 ++base_string;
4262
4263 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4264 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4265 {
af6bdddf 4266 base_string = end_op;
24eab124
AM		 4267 if (is_space_char (*base_string))
4268 ++base_string;
af6bdddf
AM		 4269 if (*base_string == ',')
4270 {
4271 ++base_string;
4272 if (is_space_char (*base_string))
4273 ++base_string;
4274 }
e5cb08ac 4275 else if (*base_string != ')')
af6bdddf
AM		 4276 {
4277 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4278 operand_string);
4279 return 0;
4280 }
24eab124 4281 }
af6bdddf 4282 else if (*base_string == REGISTER_PREFIX)
24eab124 4283 {
af6bdddf 4284 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4285 return 0;
4286 }
252b5132 4287
47926f60 4288 /* Check for scale factor. */
551c1ca1 4289 if (*base_string != ')')
af6bdddf 4290 {
551c1ca1
AM		 4291 char *end_scale = i386_scale (base_string);
4292
4293 if (!end_scale)
af6bdddf 4294 return 0;
24eab124 4295
551c1ca1 4296 base_string = end_scale;
af6bdddf
AM		 4297 if (is_space_char (*base_string))
4298 ++base_string;
4299 if (*base_string != ')')
4300 {
4301 as_bad (_("expecting `)' after scale factor in `%s'"),
4302 operand_string);
4303 return 0;
4304 }
4305 }
4306 else if (!i.index_reg)
24eab124 4307 {
af6bdddf
AM		 4308 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4309 *base_string);
24eab124
AM		 4310 return 0;
4311 }
4312 }
af6bdddf 4313 else if (*base_string != ')')
24eab124 4314 {
af6bdddf
AM		 4315 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4316 operand_string);
24eab124
AM		 4317 return 0;
4318 }
c3332e24 4319 }
af6bdddf 4320 else if (*base_string == REGISTER_PREFIX)
c3332e24 4321 {
af6bdddf 4322 as_bad (_("bad register name `%s'"), base_string);
24eab124 4323 return 0;
c3332e24 4324 }
24eab124
AM		 4325 }
4326
4327 /* If there's an expression beginning the operand, parse it,
4328 assuming displacement_string_start and
4329 displacement_string_end are meaningful. */
4330 if (displacement_string_start != displacement_string_end)
4331 {
4332 if (!i386_displacement (displacement_string_start,
4333 displacement_string_end))
4334 return 0;
4335 }
4336
4337 /* Special case for (%dx) while doing input/output op. */
4338 if (i.base_reg
4339 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4340 && i.index_reg == 0
4341 && i.log2_scale_factor == 0
4342 && i.seg[i.mem_operands] == 0
4343 && (i.types[this_operand] & Disp) == 0)
4344 {
4345 i.types[this_operand] = InOutPortReg;
4346 return 1;
4347 }
4348
eecb386c
AM		 4349 if (i386_index_check (operand_string) == 0)
4350 return 0;
24eab124
AM		 4351 i.mem_operands++;
4352 }
4353 else
ce8a8b2f
AM		 4354 {
4355 /* It's not a memory operand; argh! */
24eab124
AM		 4356 as_bad (_("invalid char %s beginning operand %d `%s'"),
4357 output_invalid (*op_string),
4358 this_operand + 1,
4359 op_string);
4360 return 0;
4361 }
47926f60 4362 return 1; /* Normal return. */
252b5132
RH		 4363}
4364\f
ee7fcc42
AM		 4365/* md_estimate_size_before_relax()
4366
4367 Called just before relax() for rs_machine_dependent frags. The x86
4368 assembler uses these frags to handle variable size jump
4369 instructions.
4370
4371 Any symbol that is now undefined will not become defined.
4372 Return the correct fr_subtype in the frag.
4373 Return the initial "guess for variable size of frag" to caller.
4374 The guess is actually the growth beyond the fixed part. Whatever
4375 we do to grow the fixed or variable part contributes to our
4376 returned value. */
4377
252b5132
RH		 4378int
4379md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4380 fragS *fragP;
4381 segT segment;
252b5132 4382{
252b5132 4383 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4384 check for un-relaxable symbols. On an ELF system, we can't relax
4385 an externally visible symbol, because it may be overridden by a
4386 shared library. */
4387 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4388#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4389 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4390 && (S_IS_EXTERNAL (fragP->fr_symbol)
4391 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4392#endif
4393 )
252b5132 4394 {
b98ef147
AM		 4395 /* Symbol is undefined in this segment, or we need to keep a
4396 reloc so that weak symbols can be overridden. */
4397 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4398 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4399 unsigned char *opcode;
4400 int old_fr_fix;
f6af82bd 4401
ee7fcc42
AM		 4402 if (fragP->fr_var != NO_RELOC)
4403 reloc_type = fragP->fr_var;
b98ef147 4404 else if (size == 2)
f6af82bd
AM		 4405 reloc_type = BFD_RELOC_16_PCREL;
4406 else
4407 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4408
ee7fcc42
AM		 4409 old_fr_fix = fragP->fr_fix;
4410 opcode = (unsigned char *) fragP->fr_opcode;
4411
fddf5b5b 4412 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4413 {
fddf5b5b
AM		 4414 case UNCOND_JUMP:
4415 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4416 opcode[0] = 0xe9;
252b5132 4417 fragP->fr_fix += size;
062cd5e7
AS		 4418 fix_new (fragP, old_fr_fix, size,
4419 fragP->fr_symbol,
4420 fragP->fr_offset, 1,
4421 reloc_type);
252b5132
RH		 4422 break;
4423
fddf5b5b 4424 case COND_JUMP86:
412167cb
AM		 4425 if (size == 2
4426 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4427 {
4428 /* Negate the condition, and branch past an
4429 unconditional jump. */
4430 opcode[0] ^= 1;
4431 opcode[1] = 3;
4432 /* Insert an unconditional jump. */
4433 opcode[2] = 0xe9;
4434 /* We added two extra opcode bytes, and have a two byte
4435 offset. */
4436 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4437 fix_new (fragP, old_fr_fix + 2, 2,
4438 fragP->fr_symbol,
4439 fragP->fr_offset, 1,
4440 reloc_type);
fddf5b5b
AM		 4441 break;
4442 }
4443 /* Fall through. */
4444
4445 case COND_JUMP:
412167cb
AM		 4446 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4447 {
3e02c1cc
AM		 4448 fixS *fixP;
4449
412167cb 4450 fragP->fr_fix += 1;
3e02c1cc
AM		 4451 fixP = fix_new (fragP, old_fr_fix, 1,
4452 fragP->fr_symbol,
4453 fragP->fr_offset, 1,
4454 BFD_RELOC_8_PCREL);
4455 fixP->fx_signed = 1;
412167cb
AM		 4456 break;
4457 }
93c2a809 4458
24eab124 4459 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4460 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4461 opcode[1] = opcode[0] + 0x10;
f6af82bd 4462 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4463 /* We've added an opcode byte. */
4464 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4465 fix_new (fragP, old_fr_fix + 1, size,
4466 fragP->fr_symbol,
4467 fragP->fr_offset, 1,
4468 reloc_type);
252b5132 4469 break;
fddf5b5b
AM		 4470
4471 default:
4472 BAD_CASE (fragP->fr_subtype);
4473 break;
252b5132
RH		 4474 }
4475 frag_wane (fragP);
ee7fcc42 4476 return fragP->fr_fix - old_fr_fix;
252b5132 4477 }
93c2a809 4478
93c2a809
AM		 4479 /* Guess size depending on current relax state. Initially the relax
4480 state will correspond to a short jump and we return 1, because
4481 the variable part of the frag (the branch offset) is one byte
4482 long. However, we can relax a section more than once and in that
4483 case we must either set fr_subtype back to the unrelaxed state,
4484 or return the value for the appropriate branch. */
4485 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4486}
4487
47926f60
KH		 4488/* Called after relax() is finished.
4489
4490 In: Address of frag.
4491 fr_type == rs_machine_dependent.
4492 fr_subtype is what the address relaxed to.
4493
4494 Out: Any fixSs and constants are set up.
4495 Caller will turn frag into a ".space 0". */
4496
252b5132
RH		 4497void
4498md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4499 bfd *abfd ATTRIBUTE_UNUSED;
4500 segT sec ATTRIBUTE_UNUSED;
29b0f896 4501 fragS *fragP;
252b5132 4502{
29b0f896 4503 unsigned char *opcode;
252b5132 4504 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4505 offsetT target_address;
4506 offsetT opcode_address;
252b5132 4507 unsigned int extension = 0;
847f7ad4 4508 offsetT displacement_from_opcode_start;
252b5132
RH		 4509
4510 opcode = (unsigned char *) fragP->fr_opcode;
4511
47926f60 4512 /* Address we want to reach in file space. */
252b5132 4513 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4514
47926f60 4515 /* Address opcode resides at in file space. */
252b5132
RH		 4516 opcode_address = fragP->fr_address + fragP->fr_fix;
4517
47926f60 4518 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4519 displacement_from_opcode_start = target_address - opcode_address;
4520
fddf5b5b 4521 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4522 {
47926f60
KH		 4523 /* Don't have to change opcode. */
4524 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4525 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4526 }
4527 else
4528 {
4529 if (no_cond_jump_promotion
4530 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4531 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4532
fddf5b5b
AM		 4533 switch (fragP->fr_subtype)
4534 {
4535 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4536 extension = 4; /* 1 opcode + 4 displacement */
4537 opcode[0] = 0xe9;
4538 where_to_put_displacement = &opcode[1];
4539 break;
252b5132 4540
fddf5b5b
AM		 4541 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4542 extension = 2; /* 1 opcode + 2 displacement */
4543 opcode[0] = 0xe9;
4544 where_to_put_displacement = &opcode[1];
4545 break;
252b5132 4546
fddf5b5b
AM		 4547 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4548 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4549 extension = 5; /* 2 opcode + 4 displacement */
4550 opcode[1] = opcode[0] + 0x10;
4551 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4552 where_to_put_displacement = &opcode[2];
4553 break;
252b5132 4554
fddf5b5b
AM		 4555 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4556 extension = 3; /* 2 opcode + 2 displacement */
4557 opcode[1] = opcode[0] + 0x10;
4558 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4559 where_to_put_displacement = &opcode[2];
4560 break;
252b5132 4561
fddf5b5b
AM		 4562 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4563 extension = 4;
4564 opcode[0] ^= 1;
4565 opcode[1] = 3;
4566 opcode[2] = 0xe9;
4567 where_to_put_displacement = &opcode[3];
4568 break;
4569
4570 default:
4571 BAD_CASE (fragP->fr_subtype);
4572 break;
4573 }
252b5132 4574 }
fddf5b5b 4575
47926f60 4576 /* Now put displacement after opcode. */
252b5132
RH		 4577 md_number_to_chars ((char *) where_to_put_displacement,
4578 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4579 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4580 fragP->fr_fix += extension;
4581}
4582\f
47926f60
KH		 4583/* Size of byte displacement jmp. */
4584int md_short_jump_size = 2;
4585
4586/* Size of dword displacement jmp. */
4587int md_long_jump_size = 5;
252b5132 4588
47926f60
KH		 4589/* Size of relocation record. */
4590const int md_reloc_size = 8;
252b5132
RH		 4591
4592void
4593md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4594 char *ptr;
4595 addressT from_addr, to_addr;
ab9da554
ILT		 4596 fragS *frag ATTRIBUTE_UNUSED;
4597 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4598{
847f7ad4 4599 offsetT offset;
252b5132
RH		 4600
4601 offset = to_addr - (from_addr + 2);
47926f60
KH		 4602 /* Opcode for byte-disp jump. */
4603 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4604 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4605}
4606
4607void
4608md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4609 char *ptr;
4610 addressT from_addr, to_addr;
a38cf1db
AM		 4611 fragS *frag ATTRIBUTE_UNUSED;
4612 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4613{
847f7ad4 4614 offsetT offset;
252b5132 4615
a38cf1db
AM		 4616 offset = to_addr - (from_addr + 5);
4617 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4618 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4619}
4620\f
4621/* Apply a fixup (fixS) to segment data, once it has been determined
4622 by our caller that we have all the info we need to fix it up.
4623
4624 On the 386, immediates, displacements, and data pointers are all in
4625 the same (little-endian) format, so we don't need to care about which
4626 we are handling. */
4627
94f592af
NC		 4628void
4629md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4630 /* The fix we're to put in. */
4631 fixS *fixP;
47926f60 4632 /* Pointer to the value of the bits. */
c6682705 4633 valueT *valP;
47926f60
KH		 4634 /* Segment fix is from. */
4635 segT seg ATTRIBUTE_UNUSED;
252b5132 4636{
94f592af 4637 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4638 valueT value = *valP;
252b5132 4639
f86103b7 4640#if !defined (TE_Mach)
93382f6d
AM		 4641 if (fixP->fx_pcrel)
4642 {
4643 switch (fixP->fx_r_type)
4644 {
5865bb77
ILT		 4645 default:
4646 break;
4647
93382f6d
AM		 4648 case BFD_RELOC_32:
4649 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4650 break;
4651 case BFD_RELOC_16:
4652 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4653 break;
4654 case BFD_RELOC_8:
4655 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4656 break;
4657 }
4658 }
252b5132 4659
a161fe53 4660 if (fixP->fx_addsy != NULL
31312f95
AM		 4661 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4662 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4663 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4664 && !use_rela_relocations)
252b5132 4665 {
31312f95
AM		 4666 /* This is a hack. There should be a better way to handle this.
4667 This covers for the fact that bfd_install_relocation will
4668 subtract the current location (for partial_inplace, PC relative
4669 relocations); see more below. */
252b5132
RH		 4670#ifndef OBJ_AOUT
4671 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4672#ifdef TE_PE
4673 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4674#endif
4675 )
4676 value += fixP->fx_where + fixP->fx_frag->fr_address;
4677#endif
4678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4679 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4680 {
6539b54b 4681 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4682
6539b54b 4683 if ((sym_seg == seg
2f66722d 4684 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4685 && sym_seg != absolute_section))
ae6063d4 4686 && !generic_force_reloc (fixP))
2f66722d
AM		 4687 {
4688 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4689 bfd_install_relocation subtracts them out again. I think
4690 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4691 it. FIXME. */
4692 value += fixP->fx_where + fixP->fx_frag->fr_address;
4693 }
252b5132
RH		 4694 }
4695#endif
4696#if defined (OBJ_COFF) && defined (TE_PE)
4697 /* For some reason, the PE format does not store a section
24eab124 4698 address offset for a PC relative symbol. */
252b5132
RH		 4699 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4700 value += md_pcrel_from (fixP);
4701#endif
4702 }
4703
4704 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4705 and we must not disappoint it. */
252b5132
RH		 4706#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4707 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4708 && fixP->fx_addsy)
47926f60
KH		 4709 switch (fixP->fx_r_type)
4710 {
4711 case BFD_RELOC_386_PLT32:
3e73aa7c 4712 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4713 /* Make the jump instruction point to the address of the operand. At
4714 runtime we merely add the offset to the actual PLT entry. */
4715 value = -4;
4716 break;
31312f95 4717
13ae64f3
JJ		 4718 case BFD_RELOC_386_TLS_GD:
4719 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4720 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4721 case BFD_RELOC_386_TLS_IE:
4722 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4723 case BFD_RELOC_X86_64_TLSGD:
4724 case BFD_RELOC_X86_64_TLSLD:
4725 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4726 value = 0; /* Fully resolved at runtime. No addend. */
4727 /* Fallthrough */
4728 case BFD_RELOC_386_TLS_LE:
4729 case BFD_RELOC_386_TLS_LDO_32:
4730 case BFD_RELOC_386_TLS_LE_32:
4731 case BFD_RELOC_X86_64_DTPOFF32:
4732 case BFD_RELOC_X86_64_TPOFF32:
4733 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4734 break;
4735
4736 case BFD_RELOC_386_GOT32:
4737 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4738 value = 0; /* Fully resolved at runtime. No addend. */
4739 break;
47926f60
KH		 4740
4741 case BFD_RELOC_VTABLE_INHERIT:
4742 case BFD_RELOC_VTABLE_ENTRY:
4743 fixP->fx_done = 0;
94f592af 4744 return;
47926f60
KH		 4745
4746 default:
4747 break;
4748 }
4749#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4750 *valP = value;
f86103b7 4751#endif /* !defined (TE_Mach) */
3e73aa7c 4752
3e73aa7c 4753 /* Are we finished with this relocation now? */
c6682705 4754 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 4755 fixP->fx_done = 1;
4756 else if (use_rela_relocations)
4757 {
4758 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4759 /* Remember value for tc_gen_reloc. */
4760 fixP->fx_addnumber = value;
3e73aa7c
JH		 4761 value = 0;
4762 }
f86103b7 4763
94f592af 4764 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4765}
252b5132 4766\f
252b5132
RH		 4767#define MAX_LITTLENUMS 6
4768
47926f60
KH		 4769/* Turn the string pointed to by litP into a floating point constant
4770 of type TYPE, and emit the appropriate bytes. The number of
4771 LITTLENUMS emitted is stored in *SIZEP. An error message is
4772 returned, or NULL on OK. */
4773
252b5132
RH		 4774char *
4775md_atof (type, litP, sizeP)
2ab9b79e 4776 int type;
252b5132
RH		 4777 char *litP;
4778 int *sizeP;
4779{
4780 int prec;
4781 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4782 LITTLENUM_TYPE *wordP;
4783 char *t;
4784
4785 switch (type)
4786 {
4787 case 'f':
4788 case 'F':
4789 prec = 2;
4790 break;
4791
4792 case 'd':
4793 case 'D':
4794 prec = 4;
4795 break;
4796
4797 case 'x':
4798 case 'X':
4799 prec = 5;
4800 break;
4801
4802 default:
4803 *sizeP = 0;
4804 return _("Bad call to md_atof ()");
4805 }
4806 t = atof_ieee (input_line_pointer, type, words);
4807 if (t)
4808 input_line_pointer = t;
4809
4810 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4811 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4812 the bigendian 386. */
4813 for (wordP = words + prec - 1; prec--;)
4814 {
4815 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4816 litP += sizeof (LITTLENUM_TYPE);
4817 }
4818 return 0;
4819}
4820\f
4821char output_invalid_buf[8];
4822
252b5132
RH		 4823static char *
4824output_invalid (c)
4825 int c;
4826{
3882b010 4827 if (ISPRINT (c))
252b5132
RH		 4828 sprintf (output_invalid_buf, "'%c'", c);
4829 else
4830 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4831 return output_invalid_buf;
4832}
4833
af6bdddf 4834/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4835
4836static const reg_entry *
4837parse_register (reg_string, end_op)
4838 char *reg_string;
4839 char **end_op;
4840{
af6bdddf
AM		 4841 char *s = reg_string;
4842 char *p;
252b5132
RH		 4843 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4844 const reg_entry *r;
4845
4846 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4847 if (*s == REGISTER_PREFIX)
4848 ++s;
4849
4850 if (is_space_char (*s))
4851 ++s;
4852
4853 p = reg_name_given;
af6bdddf 4854 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4855 {
4856 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4857 return (const reg_entry *) NULL;
4858 s++;
252b5132
RH		 4859 }
4860
6588847e
DN		 4861 /* For naked regs, make sure that we are not dealing with an identifier.
4862 This prevents confusing an identifier like `eax_var' with register
4863 `eax'. */
4864 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4865 return (const reg_entry *) NULL;
4866
af6bdddf 4867 *end_op = s;
252b5132
RH		 4868
4869 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4870
5f47d35b 4871 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4872 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4873 {
5f47d35b
AM		 4874 if (is_space_char (*s))
4875 ++s;
4876 if (*s == '(')
4877 {
af6bdddf 4878 ++s;
5f47d35b
AM		 4879 if (is_space_char (*s))
4880 ++s;
4881 if (*s >= '0' && *s <= '7')
4882 {
4883 r = &i386_float_regtab[*s - '0'];
af6bdddf 4884 ++s;
5f47d35b
AM		 4885 if (is_space_char (*s))
4886 ++s;
4887 if (*s == ')')
4888 {
4889 *end_op = s + 1;
4890 return r;
4891 }
5f47d35b 4892 }
47926f60 4893 /* We have "%st(" then garbage. */
5f47d35b
AM		 4894 return (const reg_entry *) NULL;
4895 }
4896 }
4897
1ae00879 4898 if (r != NULL
29b0f896 4899 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4900 && flag_code != CODE_64BIT)
4901 {
4902 return (const reg_entry *) NULL;
4903 }
4904
252b5132
RH		 4905 return r;
4906}
4907\f
4cc782b5 4908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 4909const char *md_shortopts = "kVQ:sqn";
252b5132 4910#else
12b55ccc 4911const char *md_shortopts = "qn";
252b5132 4912#endif
6e0b89ee 4913
252b5132 4914struct option md_longopts[] = {
3e73aa7c
JH		 4915#define OPTION_32 (OPTION_MD_BASE + 0)
4916 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4917#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4918#define OPTION_64 (OPTION_MD_BASE + 1)
4919 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4920#endif
252b5132
RH		 4921 {NULL, no_argument, NULL, 0}
4922};
4923size_t md_longopts_size = sizeof (md_longopts);
4924
4925int
4926md_parse_option (c, arg)
4927 int c;
ab9da554 4928 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4929{
4930 switch (c)
4931 {
12b55ccc
L		 4932 case 'n':
4933 optimize_align_code = 0;
4934 break;
4935
a38cf1db
AM		 4936 case 'q':
4937 quiet_warnings = 1;
252b5132
RH		 4938 break;
4939
4940#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4941 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4942 should be emitted or not. FIXME: Not implemented. */
4943 case 'Q':
252b5132
RH		 4944 break;
4945
4946 /* -V: SVR4 argument to print version ID. */
4947 case 'V':
4948 print_version_id ();
4949 break;
4950
a38cf1db
AM		 4951 /* -k: Ignore for FreeBSD compatibility. */
4952 case 'k':
252b5132 4953 break;
4cc782b5
ILT		 4954
4955 case 's':
4956 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4957 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4958 break;
6e0b89ee 4959
3e73aa7c
JH		 4960 case OPTION_64:
4961 {
4962 const char **list, **l;
4963
3e73aa7c
JH		 4964 list = bfd_target_list ();
4965 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4966 if (strcmp (*l, "elf64-x86-64") == 0)
4967 {
4968 default_arch = "x86_64";
4969 break;
4970 }
3e73aa7c 4971 if (*l == NULL)
6e0b89ee 4972 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4973 free (list);
4974 }
4975 break;
4976#endif
252b5132 4977
6e0b89ee
AM		 4978 case OPTION_32:
4979 default_arch = "i386";
4980 break;
4981
252b5132
RH		 4982 default:
4983 return 0;
4984 }
4985 return 1;
4986}
4987
4988void
4989md_show_usage (stream)
4990 FILE *stream;
4991{
4cc782b5
ILT		 4992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4993 fprintf (stream, _("\
a38cf1db
AM		 4994 -Q ignored\n\
4995 -V print assembler version number\n\
4996 -k ignored\n\
12b55ccc 4997 -n Do not optimize code alignment\n\
a38cf1db
AM		 4998 -q quieten some warnings\n\
4999 -s ignored\n"));
5000#else
5001 fprintf (stream, _("\
12b55ccc 5002 -n Do not optimize code alignment\n\
a38cf1db 5003 -q quieten some warnings\n"));
4cc782b5 5004#endif
252b5132
RH		 5005}
5006
3e73aa7c
JH		 5007#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5008 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5009
5010/* Pick the target format to use. */
5011
47926f60 5012const char *
252b5132
RH		 5013i386_target_format ()
5014{
3e73aa7c
JH		 5015 if (!strcmp (default_arch, "x86_64"))
5016 set_code_flag (CODE_64BIT);
5017 else if (!strcmp (default_arch, "i386"))
5018 set_code_flag (CODE_32BIT);
5019 else
5020 as_fatal (_("Unknown architecture"));
252b5132
RH		 5021 switch (OUTPUT_FLAVOR)
5022 {
4c63da97
AM		 5023#ifdef OBJ_MAYBE_AOUT
5024 case bfd_target_aout_flavour:
47926f60 5025 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5026#endif
5027#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5028 case bfd_target_coff_flavour:
5029 return "coff-i386";
4c63da97 5030#endif
3e73aa7c 5031#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5032 case bfd_target_elf_flavour:
3e73aa7c 5033 {
e5cb08ac
KH		 5034 if (flag_code == CODE_64BIT)
5035 use_rela_relocations = 1;
4ada7262 5036 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5037 }
4c63da97 5038#endif
252b5132
RH		 5039 default:
5040 abort ();
5041 return NULL;
5042 }
5043}
5044
47926f60 5045#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5046
5047#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5048void i386_elf_emit_arch_note ()
5049{
5050 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5051 && cpu_arch_name != NULL)
5052 {
5053 char *p;
5054 asection *seg = now_seg;
5055 subsegT subseg = now_subseg;
5056 Elf_Internal_Note i_note;
5057 Elf_External_Note e_note;
5058 asection *note_secp;
5059 int len;
5060
5061 /* Create the .note section. */
5062 note_secp = subseg_new (".note", 0);
5063 bfd_set_section_flags (stdoutput,
5064 note_secp,
5065 SEC_HAS_CONTENTS | SEC_READONLY);
5066
5067 /* Process the arch string. */
5068 len = strlen (cpu_arch_name);
5069
5070 i_note.namesz = len + 1;
5071 i_note.descsz = 0;
5072 i_note.type = NT_ARCH;
5073 p = frag_more (sizeof (e_note.namesz));
5074 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5075 p = frag_more (sizeof (e_note.descsz));
5076 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5077 p = frag_more (sizeof (e_note.type));
5078 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5079 p = frag_more (len + 1);
5080 strcpy (p, cpu_arch_name);
5081
5082 frag_align (2, 0, 0);
5083
5084 subseg_set (seg, subseg);
5085 }
5086}
5087#endif
252b5132 5088\f
252b5132
RH		 5089symbolS *
5090md_undefined_symbol (name)
5091 char *name;
5092{
18dc2407
ILT		 5093 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5094 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5095 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5096 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5097 {
5098 if (!GOT_symbol)
5099 {
5100 if (symbol_find (name))
5101 as_bad (_("GOT already in symbol table"));
5102 GOT_symbol = symbol_new (name, undefined_section,
5103 (valueT) 0, &zero_address_frag);
5104 };
5105 return GOT_symbol;
5106 }
252b5132
RH		 5107 return 0;
5108}
5109
5110/* Round up a section size to the appropriate boundary. */
47926f60 5111
252b5132
RH		 5112valueT
5113md_section_align (segment, size)
ab9da554 5114 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5115 valueT size;
5116{
4c63da97
AM		 5117#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5118 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5119 {
5120 /* For a.out, force the section size to be aligned. If we don't do
5121 this, BFD will align it for us, but it will not write out the
5122 final bytes of the section. This may be a bug in BFD, but it is
5123 easier to fix it here since that is how the other a.out targets
5124 work. */
5125 int align;
5126
5127 align = bfd_get_section_alignment (stdoutput, segment);
5128 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5129 }
252b5132
RH		 5130#endif
5131
5132 return size;
5133}
5134
5135/* On the i386, PC-relative offsets are relative to the start of the
5136 next instruction. That is, the address of the offset, plus its
5137 size, since the offset is always the last part of the insn. */
5138
5139long
5140md_pcrel_from (fixP)
5141 fixS *fixP;
5142{
5143 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5144}
5145
5146#ifndef I386COFF
5147
5148static void
5149s_bss (ignore)
ab9da554 5150 int ignore ATTRIBUTE_UNUSED;
252b5132 5151{
29b0f896 5152 int temp;
252b5132
RH		 5153
5154 temp = get_absolute_expression ();
5155 subseg_set (bss_section, (subsegT) temp);
5156 demand_empty_rest_of_line ();
5157}
5158
5159#endif
5160
252b5132
RH		 5161void
5162i386_validate_fix (fixp)
5163 fixS *fixp;
5164{
5165 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5166 {
3e73aa7c 5167 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5168 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5169 {
5170 if (flag_code != CODE_64BIT)
5171 abort ();
5172 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5173 }
5174 else
5175 {
5176 if (flag_code == CODE_64BIT)
5177 abort ();
5178 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5179 }
252b5132
RH		 5180 fixp->fx_subsy = 0;
5181 }
5182}
5183
252b5132
RH		 5184arelent *
5185tc_gen_reloc (section, fixp)
ab9da554 5186 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5187 fixS *fixp;
5188{
5189 arelent *rel;
5190 bfd_reloc_code_real_type code;
5191
5192 switch (fixp->fx_r_type)
5193 {
3e73aa7c
JH		 5194 case BFD_RELOC_X86_64_PLT32:
5195 case BFD_RELOC_X86_64_GOT32:
5196 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5197 case BFD_RELOC_386_PLT32:
5198 case BFD_RELOC_386_GOT32:
5199 case BFD_RELOC_386_GOTOFF:
5200 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5201 case BFD_RELOC_386_TLS_GD:
5202 case BFD_RELOC_386_TLS_LDM:
5203 case BFD_RELOC_386_TLS_LDO_32:
5204 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5205 case BFD_RELOC_386_TLS_IE:
5206 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5207 case BFD_RELOC_386_TLS_LE_32:
5208 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5209 case BFD_RELOC_X86_64_32S:
bffbf940
JJ		 5210 case BFD_RELOC_X86_64_TLSGD:
5211 case BFD_RELOC_X86_64_TLSLD:
5212 case BFD_RELOC_X86_64_DTPOFF32:
5213 case BFD_RELOC_X86_64_GOTTPOFF:
5214 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5215 case BFD_RELOC_RVA:
5216 case BFD_RELOC_VTABLE_ENTRY:
5217 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5218#ifdef TE_PE
5219 case BFD_RELOC_32_SECREL:
5220#endif
252b5132
RH		 5221 code = fixp->fx_r_type;
5222 break;
5223 default:
93382f6d 5224 if (fixp->fx_pcrel)
252b5132 5225 {
93382f6d
AM		 5226 switch (fixp->fx_size)
5227 {
5228 default:
b091f402
AM		 5229 as_bad_where (fixp->fx_file, fixp->fx_line,
5230 _("can not do %d byte pc-relative relocation"),
5231 fixp->fx_size);
93382f6d
AM		 5232 code = BFD_RELOC_32_PCREL;
5233 break;
5234 case 1: code = BFD_RELOC_8_PCREL; break;
5235 case 2: code = BFD_RELOC_16_PCREL; break;
5236 case 4: code = BFD_RELOC_32_PCREL; break;
5237 }
5238 }
5239 else
5240 {
5241 switch (fixp->fx_size)
5242 {
5243 default:
b091f402
AM		 5244 as_bad_where (fixp->fx_file, fixp->fx_line,
5245 _("can not do %d byte relocation"),
5246 fixp->fx_size);
93382f6d
AM		 5247 code = BFD_RELOC_32;
5248 break;
5249 case 1: code = BFD_RELOC_8; break;
5250 case 2: code = BFD_RELOC_16; break;
5251 case 4: code = BFD_RELOC_32; break;
937149dd 5252#ifdef BFD64
3e73aa7c 5253 case 8: code = BFD_RELOC_64; break;
937149dd 5254#endif
93382f6d 5255 }
252b5132
RH		 5256 }
5257 break;
5258 }
252b5132
RH		 5259
5260 if (code == BFD_RELOC_32
5261 && GOT_symbol
5262 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5263 {
5264 /* We don't support GOTPC on 64bit targets. */
5265 if (flag_code == CODE_64BIT)
bfb32b52 5266 abort ();
3e73aa7c
JH		 5267 code = BFD_RELOC_386_GOTPC;
5268 }
252b5132
RH		 5269
5270 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5271 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5272 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5273
5274 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5275 if (!use_rela_relocations)
5276 {
5277 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5278 vtable entry to be used in the relocation's section offset. */
5279 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5280 rel->address = fixp->fx_offset;
252b5132 5281
c6682705 5282 rel->addend = 0;
3e73aa7c
JH		 5283 }
5284 /* Use the rela in 64bit mode. */
252b5132 5285 else
3e73aa7c 5286 {
062cd5e7
AS		 5287 if (!fixp->fx_pcrel)
5288 rel->addend = fixp->fx_offset;
5289 else
5290 switch (code)
5291 {
5292 case BFD_RELOC_X86_64_PLT32:
5293 case BFD_RELOC_X86_64_GOT32:
5294 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5295 case BFD_RELOC_X86_64_TLSGD:
5296 case BFD_RELOC_X86_64_TLSLD:
5297 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5298 rel->addend = fixp->fx_offset - fixp->fx_size;
5299 break;
5300 default:
5301 rel->addend = (section->vma
5302 - fixp->fx_size
5303 + fixp->fx_addnumber
5304 + md_pcrel_from (fixp));
5305 break;
5306 }
3e73aa7c
JH		 5307 }
5308
252b5132
RH		 5309 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5310 if (rel->howto == NULL)
5311 {
5312 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5313 _("cannot represent relocation type %s"),
252b5132
RH		 5314 bfd_get_reloc_code_name (code));
5315 /* Set howto to a garbage value so that we can keep going. */
5316 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5317 assert (rel->howto != NULL);
5318 }
5319
5320 return rel;
5321}
5322
64a0c779
DN		 5323\f
5324/* Parse operands using Intel syntax. This implements a recursive descent
5325 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5326 Programmer's Guide.
5327
5328 FIXME: We do not recognize the full operand grammar defined in the MASM
5329 documentation. In particular, all the structure/union and
5330 high-level macro operands are missing.
5331
5332 Uppercase words are terminals, lower case words are non-terminals.
5333 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5334 bars '|' denote choices. Most grammar productions are implemented in
5335 functions called 'intel_<production>'.
5336
5337 Initial production is 'expr'.
5338
64a0c779
DN		 5339 addOp + | -
5340
5341 alpha [a-zA-Z]
5342
5343 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5344
5345 constant digits [[ radixOverride ]]
5346
5347 dataType BYTE | WORD | DWORD | QWORD | XWORD
5348
5349 digits decdigit
b77a7acd
AJ		 5350 | digits decdigit
5351 | digits hexdigit
64a0c779
DN		 5352
5353 decdigit [0-9]
5354
5355 e05 e05 addOp e06
b77a7acd 5356 | e06
64a0c779
DN		 5357
5358 e06 e06 mulOp e09
b77a7acd 5359 | e09
64a0c779
DN		 5360
5361 e09 OFFSET e10
5362 | e09 PTR e10
5363 | e09 : e10
5364 | e10
5365
5366 e10 e10 [ expr ]
b77a7acd 5367 | e11
64a0c779
DN		 5368
5369 e11 ( expr )
b77a7acd 5370 | [ expr ]
64a0c779
DN		 5371 | constant
5372 | dataType
5373 | id
5374 | $
5375 | register
5376
5377 => expr SHORT e05
b77a7acd 5378 | e05
64a0c779
DN		 5379
5380 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5381 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5382
5383 hexdigit a | b | c | d | e | f
b77a7acd 5384 | A | B | C | D | E | F
64a0c779
DN		 5385
5386 id alpha
b77a7acd 5387 | id alpha
64a0c779
DN		 5388 | id decdigit
5389
5390 mulOp * | / | MOD
5391
5392 quote " | '
5393
5394 register specialRegister
b77a7acd 5395 | gpRegister
64a0c779
DN		 5396 | byteRegister
5397
5398 segmentRegister CS | DS | ES | FS | GS | SS
5399
5400 specialRegister CR0 | CR2 | CR3
b77a7acd 5401 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5402 | TR3 | TR4 | TR5 | TR6 | TR7
5403
64a0c779
DN		 5404 We simplify the grammar in obvious places (e.g., register parsing is
5405 done by calling parse_register) and eliminate immediate left recursion
5406 to implement a recursive-descent parser.
5407
5408 expr SHORT e05
b77a7acd 5409 | e05
64a0c779
DN		 5410
5411 e05 e06 e05'
5412
5413 e05' addOp e06 e05'
b77a7acd 5414 | Empty
64a0c779
DN		 5415
5416 e06 e09 e06'
5417
5418 e06' mulOp e09 e06'
b77a7acd 5419 | Empty
64a0c779
DN		 5420
5421 e09 OFFSET e10 e09'
b77a7acd 5422 | e10 e09'
64a0c779
DN		 5423
5424 e09' PTR e10 e09'
b77a7acd 5425 | : e10 e09'
64a0c779
DN		 5426 | Empty
5427
5428 e10 e11 e10'
5429
5430 e10' [ expr ] e10'
b77a7acd 5431 | Empty
64a0c779
DN		 5432
5433 e11 ( expr )
b77a7acd 5434 | [ expr ]
64a0c779
DN		 5435 | BYTE
5436 | WORD
5437 | DWORD
5438 | QWORD
5439 | XWORD
5440 | .
5441 | $
5442 | register
5443 | id
5444 | constant */
5445
5446/* Parsing structure for the intel syntax parser. Used to implement the
5447 semantic actions for the operand grammar. */
5448struct intel_parser_s
5449 {
5450 char *op_string; /* The string being parsed. */
5451 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5452 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5453 int is_mem; /* 1 if operand is memory reference. */
5454 const reg_entry *reg; /* Last register reference found. */
5455 char *disp; /* Displacement string being built. */
5456 };
5457
5458static struct intel_parser_s intel_parser;
5459
5460/* Token structure for parsing intel syntax. */
5461struct intel_token
5462 {
5463 int code; /* Token code. */
5464 const reg_entry *reg; /* Register entry for register tokens. */
5465 char *str; /* String representation. */
5466 };
5467
5468static struct intel_token cur_token, prev_token;
5469
50705ef4
AM		 5470/* Token codes for the intel parser. Since T_SHORT is already used
5471 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5472#define T_NIL -1
5473#define T_CONST 1
5474#define T_REG 2
5475#define T_BYTE 3
5476#define T_WORD 4
5477#define T_DWORD 5
5478#define T_QWORD 6
5479#define T_XWORD 7
50705ef4 5480#undef T_SHORT
64a0c779
DN		 5481#define T_SHORT 8
5482#define T_OFFSET 9
5483#define T_PTR 10
5484#define T_ID 11
5485
5486/* Prototypes for intel parser functions. */
5487static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5488static void intel_get_token PARAMS ((void));
5489static void intel_putback_token PARAMS ((void));
5490static int intel_expr PARAMS ((void));
5491static int intel_e05 PARAMS ((void));
5492static int intel_e05_1 PARAMS ((void));
5493static int intel_e06 PARAMS ((void));
5494static int intel_e06_1 PARAMS ((void));
5495static int intel_e09 PARAMS ((void));
5496static int intel_e09_1 PARAMS ((void));
5497static int intel_e10 PARAMS ((void));
5498static int intel_e10_1 PARAMS ((void));
5499static int intel_e11 PARAMS ((void));
64a0c779 5500
64a0c779
DN		 5501static int
5502i386_intel_operand (operand_string, got_a_float)
5503 char *operand_string;
5504 int got_a_float;
5505{
5506 int ret;
5507 char *p;
5508
5509 /* Initialize token holders. */
5510 cur_token.code = prev_token.code = T_NIL;
5511 cur_token.reg = prev_token.reg = NULL;
5512 cur_token.str = prev_token.str = NULL;
5513
5514 /* Initialize parser structure. */
e5cb08ac 5515 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5516 if (p == NULL)
5517 abort ();
5518 strcpy (intel_parser.op_string, operand_string);
5519 intel_parser.got_a_float = got_a_float;
5520 intel_parser.op_modifier = -1;
5521 intel_parser.is_mem = 0;
5522 intel_parser.reg = NULL;
e5cb08ac 5523 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5524 if (intel_parser.disp == NULL)
5525 abort ();
5526 intel_parser.disp[0] = '\0';
5527
5528 /* Read the first token and start the parser. */
5529 intel_get_token ();
5530 ret = intel_expr ();
5531
5532 if (ret)
5533 {
5534 /* If we found a memory reference, hand it over to i386_displacement
5535 to fill in the rest of the operand fields. */
5536 if (intel_parser.is_mem)
5537 {
5538 if ((i.mem_operands == 1
5539 && (current_templates->start->opcode_modifier & IsString) == 0)
5540 || i.mem_operands == 2)
5541 {
5542 as_bad (_("too many memory references for '%s'"),
5543 current_templates->start->name);
5544 ret = 0;
5545 }
5546 else
5547 {
5548 char *s = intel_parser.disp;
5549 i.mem_operands++;
5550
5551 /* Add the displacement expression. */
5552 if (*s != '\0')
a4622f40
AM		 5553 ret = i386_displacement (s, s + strlen (s));
5554 if (ret)
5555 ret = i386_index_check (operand_string);
64a0c779
DN		 5556 }
5557 }
5558
5559 /* Constant and OFFSET expressions are handled by i386_immediate. */
5560 else if (intel_parser.op_modifier == OFFSET_FLAT
5561 || intel_parser.reg == NULL)
5562 ret = i386_immediate (intel_parser.disp);
5563 }
5564
5565 free (p);
5566 free (intel_parser.disp);
5567
5568 return ret;
5569}
5570
64a0c779 5571/* expr SHORT e05
b77a7acd 5572 | e05 */
64a0c779
DN		 5573static int
5574intel_expr ()
5575{
5576 /* expr SHORT e05 */
5577 if (cur_token.code == T_SHORT)
5578 {
5579 intel_parser.op_modifier = SHORT;
5580 intel_match_token (T_SHORT);
5581
5582 return (intel_e05 ());
5583 }
5584
5585 /* expr e05 */
5586 else
5587 return intel_e05 ();
5588}
5589
64a0c779
DN		 5590/* e05 e06 e05'
5591
4a1805b1 5592 e05' addOp e06 e05'
64a0c779
DN		 5593 | Empty */
5594static int
5595intel_e05 ()
5596{
5597 return (intel_e06 () && intel_e05_1 ());
5598}
5599
5600static int
5601intel_e05_1 ()
5602{
5603 /* e05' addOp e06 e05' */
5604 if (cur_token.code == '+' || cur_token.code == '-')
5605 {
5606 strcat (intel_parser.disp, cur_token.str);
5607 intel_match_token (cur_token.code);
5608
5609 return (intel_e06 () && intel_e05_1 ());
5610 }
5611
5612 /* e05' Empty */
5613 else
5614 return 1;
4a1805b1 5615}
64a0c779
DN		 5616
5617/* e06 e09 e06'
5618
5619 e06' mulOp e09 e06'
b77a7acd 5620 | Empty */
64a0c779
DN		 5621static int
5622intel_e06 ()
5623{
5624 return (intel_e09 () && intel_e06_1 ());
5625}
5626
5627static int
5628intel_e06_1 ()
5629{
5630 /* e06' mulOp e09 e06' */
5631 if (cur_token.code == '*' || cur_token.code == '/')
5632 {
5633 strcat (intel_parser.disp, cur_token.str);
5634 intel_match_token (cur_token.code);
5635
5636 return (intel_e09 () && intel_e06_1 ());
5637 }
4a1805b1 5638
64a0c779 5639 /* e06' Empty */
4a1805b1 5640 else
64a0c779
DN		 5641 return 1;
5642}
5643
64a0c779 5644/* e09 OFFSET e10 e09'
b77a7acd 5645 | e10 e09'
64a0c779
DN		 5646
5647 e09' PTR e10 e09'
b77a7acd 5648 | : e10 e09'
64a0c779
DN		 5649 | Empty */
5650static int
5651intel_e09 ()
5652{
5653 /* e09 OFFSET e10 e09' */
5654 if (cur_token.code == T_OFFSET)
5655 {
5656 intel_parser.is_mem = 0;
5657 intel_parser.op_modifier = OFFSET_FLAT;
5658 intel_match_token (T_OFFSET);
5659
5660 return (intel_e10 () && intel_e09_1 ());
5661 }
5662
5663 /* e09 e10 e09' */
5664 else
5665 return (intel_e10 () && intel_e09_1 ());
5666}
5667
5668static int
5669intel_e09_1 ()
5670{
5671 /* e09' PTR e10 e09' */
5672 if (cur_token.code == T_PTR)
5673 {
5674 if (prev_token.code == T_BYTE)
5675 i.suffix = BYTE_MNEM_SUFFIX;
5676
5677 else if (prev_token.code == T_WORD)
5678 {
5679 if (intel_parser.got_a_float == 2) /* "fi..." */
5680 i.suffix = SHORT_MNEM_SUFFIX;
5681 else
5682 i.suffix = WORD_MNEM_SUFFIX;
5683 }
5684
5685 else if (prev_token.code == T_DWORD)
5686 {
5687 if (intel_parser.got_a_float == 1) /* "f..." */
5688 i.suffix = SHORT_MNEM_SUFFIX;
5689 else
5690 i.suffix = LONG_MNEM_SUFFIX;
5691 }
5692
5693 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5694 {
5695 if (intel_parser.got_a_float == 1) /* "f..." */
5696 i.suffix = LONG_MNEM_SUFFIX;
5697 else
3e73aa7c 5698 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5699 }
64a0c779
DN		 5700
5701 else if (prev_token.code == T_XWORD)
5702 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5703
5704 else
5705 {
5706 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5707 return 0;
5708 }
5709
5710 intel_match_token (T_PTR);
5711
5712 return (intel_e10 () && intel_e09_1 ());
5713 }
5714
5715 /* e09 : e10 e09' */
5716 else if (cur_token.code == ':')
5717 {
21d6c4af
DN		 5718 /* Mark as a memory operand only if it's not already known to be an
5719 offset expression. */
5720 if (intel_parser.op_modifier != OFFSET_FLAT)
5721 intel_parser.is_mem = 1;
64a0c779
DN		 5722
5723 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5724 }
5725
5726 /* e09' Empty */
5727 else
5728 return 1;
5729}
5730
5731/* e10 e11 e10'
5732
5733 e10' [ expr ] e10'
b77a7acd 5734 | Empty */
64a0c779
DN		 5735static int
5736intel_e10 ()
5737{
5738 return (intel_e11 () && intel_e10_1 ());
5739}
5740
5741static int
5742intel_e10_1 ()
5743{
5744 /* e10' [ expr ] e10' */
5745 if (cur_token.code == '[')
5746 {
5747 intel_match_token ('[');
21d6c4af
DN		 5748
5749 /* Mark as a memory operand only if it's not already known to be an
5750 offset expression. If it's an offset expression, we need to keep
5751 the brace in. */
5752 if (intel_parser.op_modifier != OFFSET_FLAT)
5753 intel_parser.is_mem = 1;
5754 else
5755 strcat (intel_parser.disp, "[");
4a1805b1 5756
64a0c779 5757 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5758 if (*intel_parser.disp != '\0'
5759 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5760 strcat (intel_parser.disp, "+");
5761
21d6c4af
DN		 5762 if (intel_expr () && intel_match_token (']'))
5763 {
5764 /* Preserve brackets when the operand is an offset expression. */
5765 if (intel_parser.op_modifier == OFFSET_FLAT)
5766 strcat (intel_parser.disp, "]");
5767
5768 return intel_e10_1 ();
5769 }
5770 else
5771 return 0;
64a0c779
DN		 5772 }
5773
5774 /* e10' Empty */
5775 else
5776 return 1;
5777}
5778
64a0c779 5779/* e11 ( expr )
b77a7acd 5780 | [ expr ]
64a0c779
DN		 5781 | BYTE
5782 | WORD
5783 | DWORD
5784 | QWORD
5785 | XWORD
4a1805b1 5786 | $
64a0c779
DN		 5787 | .
5788 | register
5789 | id
5790 | constant */
5791static int
5792intel_e11 ()
5793{
5794 /* e11 ( expr ) */
5795 if (cur_token.code == '(')
5796 {
5797 intel_match_token ('(');
5798 strcat (intel_parser.disp, "(");
5799
5800 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5801 {
5802 strcat (intel_parser.disp, ")");
5803 return 1;
5804 }
64a0c779
DN		 5805 else
5806 return 0;
5807 }
5808
5809 /* e11 [ expr ] */
5810 else if (cur_token.code == '[')
5811 {
5812 intel_match_token ('[');
21d6c4af
DN		 5813
5814 /* Mark as a memory operand only if it's not already known to be an
5815 offset expression. If it's an offset expression, we need to keep
5816 the brace in. */
5817 if (intel_parser.op_modifier != OFFSET_FLAT)
5818 intel_parser.is_mem = 1;
5819 else
5820 strcat (intel_parser.disp, "[");
4a1805b1 5821
64a0c779
DN		 5822 /* Operands for jump/call inside brackets denote absolute addresses. */
5823 if (current_templates->start->opcode_modifier & Jump
5824 || current_templates->start->opcode_modifier & JumpDword
5825 || current_templates->start->opcode_modifier & JumpByte
5826 || current_templates->start->opcode_modifier & JumpInterSegment)
5827 i.types[this_operand] |= JumpAbsolute;
5828
5829 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5830 if (*intel_parser.disp != '\0'
5831 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5832 strcat (intel_parser.disp, "+");
5833
21d6c4af
DN		 5834 if (intel_expr () && intel_match_token (']'))
5835 {
5836 /* Preserve brackets when the operand is an offset expression. */
5837 if (intel_parser.op_modifier == OFFSET_FLAT)
5838 strcat (intel_parser.disp, "]");
5839
5840 return 1;
5841 }
5842 else
5843 return 0;
64a0c779
DN		 5844 }
5845
4a1805b1 5846 /* e11 BYTE
64a0c779
DN		 5847 | WORD
5848 | DWORD
5849 | QWORD
5850 | XWORD */
5851 else if (cur_token.code == T_BYTE
5852 || cur_token.code == T_WORD
5853 || cur_token.code == T_DWORD
5854 || cur_token.code == T_QWORD
5855 || cur_token.code == T_XWORD)
5856 {
5857 intel_match_token (cur_token.code);
5858
5859 return 1;
5860 }
5861
5862 /* e11 $
5863 | . */
5864 else if (cur_token.code == '$' || cur_token.code == '.')
5865 {
5866 strcat (intel_parser.disp, cur_token.str);
5867 intel_match_token (cur_token.code);
21d6c4af
DN		 5868
5869 /* Mark as a memory operand only if it's not already known to be an
5870 offset expression. */
5871 if (intel_parser.op_modifier != OFFSET_FLAT)
5872 intel_parser.is_mem = 1;
64a0c779
DN		 5873
5874 return 1;
5875 }
5876
5877 /* e11 register */
5878 else if (cur_token.code == T_REG)
5879 {
5880 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5881
5882 intel_match_token (T_REG);
5883
5884 /* Check for segment change. */
5885 if (cur_token.code == ':')
5886 {
5887 if (reg->reg_type & (SReg2 | SReg3))
5888 {
5889 switch (reg->reg_num)
5890 {
5891 case 0:
5892 i.seg[i.mem_operands] = &es;
5893 break;
5894 case 1:
5895 i.seg[i.mem_operands] = &cs;
5896 break;
5897 case 2:
5898 i.seg[i.mem_operands] = &ss;
5899 break;
5900 case 3:
5901 i.seg[i.mem_operands] = &ds;
5902 break;
5903 case 4:
5904 i.seg[i.mem_operands] = &fs;
5905 break;
5906 case 5:
5907 i.seg[i.mem_operands] = &gs;
5908 break;
5909 }
5910 }
5911 else
5912 {
5913 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5914 return 0;
5915 }
5916 }
5917
5918 /* Not a segment register. Check for register scaling. */
5919 else if (cur_token.code == '*')
5920 {
5921 if (!intel_parser.is_mem)
5922 {
5923 as_bad (_("Register scaling only allowed in memory operands."));
5924 return 0;
5925 }
5926
4a1805b1 5927 /* What follows must be a valid scale. */
64a0c779
DN		 5928 if (intel_match_token ('*')
5929 && strchr ("01248", *cur_token.str))
5930 {
5931 i.index_reg = reg;
5932 i.types[this_operand] |= BaseIndex;
5933
5934 /* Set the scale after setting the register (otherwise,
5935 i386_scale will complain) */
5936 i386_scale (cur_token.str);
5937 intel_match_token (T_CONST);
5938 }
5939 else
5940 {
5941 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5942 cur_token.str);
5943 return 0;
5944 }
5945 }
5946
5947 /* No scaling. If this is a memory operand, the register is either a
5948 base register (first occurrence) or an index register (second
5949 occurrence). */
5950 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5951 {
5952 if (i.base_reg && i.index_reg)
5953 {
5954 as_bad (_("Too many register references in memory operand.\n"));
5955 return 0;
5956 }
5957
5958 if (i.base_reg == NULL)
5959 i.base_reg = reg;
5960 else
5961 i.index_reg = reg;
5962
5963 i.types[this_operand] |= BaseIndex;
5964 }
5965
5966 /* Offset modifier. Add the register to the displacement string to be
5967 parsed as an immediate expression after we're done. */
5968 else if (intel_parser.op_modifier == OFFSET_FLAT)
5969 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5970
64a0c779
DN		 5971 /* It's neither base nor index nor offset. */
5972 else
5973 {
5974 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5975 i.op[this_operand].regs = reg;
5976 i.reg_operands++;
5977 }
5978
5979 /* Since registers are not part of the displacement string (except
5980 when we're parsing offset operands), we may need to remove any
5981 preceding '+' from the displacement string. */
5982 if (*intel_parser.disp != '\0'
5983 && intel_parser.op_modifier != OFFSET_FLAT)
5984 {
5985 char *s = intel_parser.disp;
5986 s += strlen (s) - 1;
5987 if (*s == '+')
5988 *s = '\0';
5989 }
5990
5991 return 1;
5992 }
4a1805b1 5993
64a0c779
DN		 5994 /* e11 id */
5995 else if (cur_token.code == T_ID)
5996 {
5997 /* Add the identifier to the displacement string. */
5998 strcat (intel_parser.disp, cur_token.str);
5999 intel_match_token (T_ID);
6000
6001 /* The identifier represents a memory reference only if it's not
6002 preceded by an offset modifier. */
21d6c4af 6003 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6004 intel_parser.is_mem = 1;
6005
6006 return 1;
6007 }
6008
6009 /* e11 constant */
6010 else if (cur_token.code == T_CONST
e5cb08ac 6011 || cur_token.code == '-'
64a0c779
DN		 6012 || cur_token.code == '+')
6013 {
6014 char *save_str;
6015
6016 /* Allow constants that start with `+' or `-'. */
6017 if (cur_token.code == '-' || cur_token.code == '+')
6018 {
6019 strcat (intel_parser.disp, cur_token.str);
6020 intel_match_token (cur_token.code);
6021 if (cur_token.code != T_CONST)
6022 {
6023 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6024 cur_token.str);
6025 return 0;
6026 }
6027 }
6028
e5cb08ac 6029 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6030 if (save_str == NULL)
bc805888 6031 abort ();
64a0c779
DN		 6032 strcpy (save_str, cur_token.str);
6033
6034 /* Get the next token to check for register scaling. */
6035 intel_match_token (cur_token.code);
6036
6037 /* Check if this constant is a scaling factor for an index register. */
6038 if (cur_token.code == '*')
6039 {
6040 if (intel_match_token ('*') && cur_token.code == T_REG)
6041 {
6042 if (!intel_parser.is_mem)
6043 {
6044 as_bad (_("Register scaling only allowed in memory operands."));
6045 return 0;
6046 }
6047
4a1805b1 6048 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6049 a valid scale. */
6050 if (strchr ("01248", *save_str))
6051 {
6052 i.index_reg = cur_token.reg;
6053 i.types[this_operand] |= BaseIndex;
6054
6055 /* Set the scale after setting the register (otherwise,
6056 i386_scale will complain) */
6057 i386_scale (save_str);
6058 intel_match_token (T_REG);
6059
6060 /* Since registers are not part of the displacement
6061 string, we may need to remove any preceding '+' from
6062 the displacement string. */
6063 if (*intel_parser.disp != '\0')
6064 {
6065 char *s = intel_parser.disp;
6066 s += strlen (s) - 1;
6067 if (*s == '+')
6068 *s = '\0';
6069 }
6070
6071 free (save_str);
6072
6073 return 1;
6074 }
6075 else
6076 return 0;
6077 }
6078
6079 /* The constant was not used for register scaling. Since we have
6080 already consumed the token following `*' we now need to put it
6081 back in the stream. */
6082 else
6083 intel_putback_token ();
6084 }
6085
6086 /* Add the constant to the displacement string. */
6087 strcat (intel_parser.disp, save_str);
6088 free (save_str);
6089
6090 return 1;
6091 }
6092
64a0c779
DN		 6093 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6094 return 0;
6095}
6096
64a0c779
DN		 6097/* Match the given token against cur_token. If they match, read the next
6098 token from the operand string. */
6099static int
6100intel_match_token (code)
e5cb08ac 6101 int code;
64a0c779
DN		 6102{
6103 if (cur_token.code == code)
6104 {
6105 intel_get_token ();
6106 return 1;
6107 }
6108 else
6109 {
6110 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6111 return 0;
6112 }
6113}
6114
64a0c779
DN		 6115/* Read a new token from intel_parser.op_string and store it in cur_token. */
6116static void
6117intel_get_token ()
6118{
6119 char *end_op;
6120 const reg_entry *reg;
6121 struct intel_token new_token;
6122
6123 new_token.code = T_NIL;
6124 new_token.reg = NULL;
6125 new_token.str = NULL;
6126
4a1805b1 6127 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6128 cur_token to prev_token. */
6129 if (prev_token.str)
6130 free (prev_token.str);
6131
6132 prev_token = cur_token;
6133
6134 /* Skip whitespace. */
6135 while (is_space_char (*intel_parser.op_string))
6136 intel_parser.op_string++;
6137
6138 /* Return an empty token if we find nothing else on the line. */
6139 if (*intel_parser.op_string == '\0')
6140 {
6141 cur_token = new_token;
6142 return;
6143 }
6144
6145 /* The new token cannot be larger than the remainder of the operand
6146 string. */
e5cb08ac 6147 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6148 if (new_token.str == NULL)
bc805888 6149 abort ();
64a0c779
DN		 6150 new_token.str[0] = '\0';
6151
6152 if (strchr ("0123456789", *intel_parser.op_string))
6153 {
6154 char *p = new_token.str;
6155 char *q = intel_parser.op_string;
6156 new_token.code = T_CONST;
6157
6158 /* Allow any kind of identifier char to encompass floating point and
6159 hexadecimal numbers. */
6160 while (is_identifier_char (*q))
6161 *p++ = *q++;
6162 *p = '\0';
6163
6164 /* Recognize special symbol names [0-9][bf]. */
6165 if (strlen (intel_parser.op_string) == 2
4a1805b1 6166 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6167 || intel_parser.op_string[1] == 'f'))
6168 new_token.code = T_ID;
6169 }
6170
6171 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6172 {
6173 new_token.code = *intel_parser.op_string;
6174 new_token.str[0] = *intel_parser.op_string;
6175 new_token.str[1] = '\0';
6176 }
6177
6178 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6179 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6180 {
6181 new_token.code = T_REG;
6182 new_token.reg = reg;
6183
6184 if (*intel_parser.op_string == REGISTER_PREFIX)
6185 {
6186 new_token.str[0] = REGISTER_PREFIX;
6187 new_token.str[1] = '\0';
6188 }
6189
6190 strcat (new_token.str, reg->reg_name);
6191 }
6192
6193 else if (is_identifier_char (*intel_parser.op_string))
6194 {
6195 char *p = new_token.str;
6196 char *q = intel_parser.op_string;
6197
6198 /* A '.' or '$' followed by an identifier char is an identifier.
6199 Otherwise, it's operator '.' followed by an expression. */
6200 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6201 {
6202 new_token.code = *q;
6203 new_token.str[0] = *q;
6204 new_token.str[1] = '\0';
6205 }
6206 else
6207 {
6208 while (is_identifier_char (*q) || *q == '@')
6209 *p++ = *q++;
6210 *p = '\0';
6211
6212 if (strcasecmp (new_token.str, "BYTE") == 0)
6213 new_token.code = T_BYTE;
6214
6215 else if (strcasecmp (new_token.str, "WORD") == 0)
6216 new_token.code = T_WORD;
6217
6218 else if (strcasecmp (new_token.str, "DWORD") == 0)
6219 new_token.code = T_DWORD;
6220
6221 else if (strcasecmp (new_token.str, "QWORD") == 0)
6222 new_token.code = T_QWORD;
6223
6224 else if (strcasecmp (new_token.str, "XWORD") == 0)
6225 new_token.code = T_XWORD;
6226
6227 else if (strcasecmp (new_token.str, "PTR") == 0)
6228 new_token.code = T_PTR;
6229
6230 else if (strcasecmp (new_token.str, "SHORT") == 0)
6231 new_token.code = T_SHORT;
6232
6233 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6234 {
6235 new_token.code = T_OFFSET;
6236
6237 /* ??? This is not mentioned in the MASM grammar but gcc
6238 makes use of it with -mintel-syntax. OFFSET may be
6239 followed by FLAT: */
6240 if (strncasecmp (q, " FLAT:", 6) == 0)
6241 strcat (new_token.str, " FLAT:");
6242 }
6243
6244 /* ??? This is not mentioned in the MASM grammar. */
6245 else if (strcasecmp (new_token.str, "FLAT") == 0)
6246 new_token.code = T_OFFSET;
6247
6248 else
6249 new_token.code = T_ID;
6250 }
6251 }
6252
6253 else
6254 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6255
6256 intel_parser.op_string += strlen (new_token.str);
6257 cur_token = new_token;
6258}
6259
64a0c779
DN		 6260/* Put cur_token back into the token stream and make cur_token point to
6261 prev_token. */
6262static void
6263intel_putback_token ()
6264{
6265 intel_parser.op_string -= strlen (cur_token.str);
6266 free (cur_token.str);
6267 cur_token = prev_token;
4a1805b1 6268
64a0c779
DN		 6269 /* Forget prev_token. */
6270 prev_token.code = T_NIL;
6271 prev_token.reg = NULL;
6272 prev_token.str = NULL;
6273}
54cfded0 6274
a4447b93 6275int
54cfded0
AM		 6276tc_x86_regname_to_dw2regnum (const char *regname)
6277{
6278 unsigned int regnum;
6279 unsigned int regnames_count;
6280 char *regnames_32[] =
6281 {
a4447b93
RH		 6282 "eax", "ecx", "edx", "ebx",
6283 "esp", "ebp", "esi", "edi",
54cfded0
AM		 6284 "eip"
6285 };
6286 char *regnames_64[] =
6287 {
6288 "rax", "rbx", "rcx", "rdx",
6289 "rdi", "rsi", "rbp", "rsp",
6290 "r8", "r9", "r10", "r11",
6291 "r12", "r13", "r14", "r15",
6292 "rip"
6293 };
6294 char **regnames;
6295
6296 if (flag_code == CODE_64BIT)
6297 {
6298 regnames = regnames_64;
0cea6190 6299 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6300 }
6301 else
6302 {
6303 regnames = regnames_32;
0cea6190 6304 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6305 }
6306
6307 for (regnum = 0; regnum < regnames_count; regnum++)
6308 if (strcmp (regname, regnames[regnum]) == 0)
6309 return regnum;
6310
54cfded0
AM		 6311 return -1;
6312}
6313
6314void
6315tc_x86_frame_initial_instructions (void)
6316{
a4447b93
RH		 6317 static unsigned int sp_regno;
6318
6319 if (!sp_regno)
6320 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6321 ? "rsp" : "esp");
6322
6323 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6324 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6325}
GDB Binutils - Deliverables
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