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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
eecb386c 308
12b55ccc
L		 309/* Non-zero to optimize code alignment. */
310int optimize_align_code = 1;
311
47926f60
KH		 312/* Non-zero to quieten some warnings. */
313static int quiet_warnings = 0;
a38cf1db 314
47926f60
KH		 315/* CPU name. */
316static const char *cpu_arch_name = NULL;
5c6af06e 317static const char *cpu_sub_arch_name = NULL;
a38cf1db 318
47926f60 319/* CPU feature flags. */
29b0f896 320static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 321
fddf5b5b
AM		 322/* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324static unsigned int no_cond_jump_promotion = 0;
325
29b0f896
AM		 326/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
327symbolS *GOT_symbol;
328
a4447b93
RH		 329/* The dwarf2 return column, adjusted for 32 or 64 bit. */
330unsigned int x86_dwarf2_return_column;
331
332/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333int x86_cie_data_alignment;
334
252b5132 335/* Interface to relax_segment.
fddf5b5b
AM		 336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
252b5132 339
47926f60 340/* Types. */
93c2a809
AM		 341#define UNCOND_JUMP 0
342#define COND_JUMP 1
343#define COND_JUMP86 2
fddf5b5b 344
47926f60 345/* Sizes. */
252b5132
RH		 346#define CODE16 1
347#define SMALL 0
29b0f896 348#define SMALL16 (SMALL | CODE16)
252b5132 349#define BIG 2
29b0f896 350#define BIG16 (BIG | CODE16)
252b5132
RH		 351
352#ifndef INLINE
353#ifdef __GNUC__
354#define INLINE __inline__
355#else
356#define INLINE
357#endif
358#endif
359
fddf5b5b
AM		 360#define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362#define TYPE_FROM_RELAX_STATE(s) \
363 ((s) >> 2)
364#define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 366
367/* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
374
375const relax_typeS md_relax_table[] =
376{
24eab124
AM		 377 /* The fields are:
378 1) most positive reach of this state,
379 2) most negative reach of this state,
93c2a809 380 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 381 4) which index into the table to try if we can't fit into this one. */
252b5132 382
fddf5b5b 383 /* UNCOND_JUMP states. */
93c2a809
AM		 384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
252b5132 388 {0, 0, 4, 0},
93c2a809
AM		 389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 391 {0, 0, 2, 0},
392
93c2a809
AM		 393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
398 {0, 0, 5, 0},
fddf5b5b 399 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 400 1 extra opcode byte, 2 displacement bytes. */
401 {0, 0, 3, 0},
402
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
411 {0, 0, 4, 0}
252b5132
RH		 412};
413
e413e4e9
AM		 414static const arch_entry cpu_arch[] = {
415 {"i8086", Cpu086 },
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
432 {".mmx", CpuMMX },
433 {".sse", CpuMMX|CpuMMX2|CpuSSE },
434 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
435 {".3dnow", CpuMMX|Cpu3dnow },
436 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
437 {".padlock", CpuPadLock },
e413e4e9
AM		 438 {NULL, 0 }
439};
440
29b0f896
AM		 441const pseudo_typeS md_pseudo_table[] =
442{
443#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes, 0},
445#else
446 {"align", s_align_ptwo, 0},
447#endif
448 {"arch", set_cpu_arch, 0},
449#ifndef I386COFF
450 {"bss", s_bss, 0},
451#endif
452 {"ffloat", float_cons, 'f'},
453 {"dfloat", float_cons, 'd'},
454 {"tfloat", float_cons, 'x'},
455 {"value", cons, 2},
456 {"noopt", s_ignore, 0},
457 {"optim", s_ignore, 0},
458 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
459 {"code16", set_code_flag, CODE_16BIT},
460 {"code32", set_code_flag, CODE_32BIT},
461 {"code64", set_code_flag, CODE_64BIT},
462 {"intel_syntax", set_intel_syntax, 1},
463 {"att_syntax", set_intel_syntax, 0},
c6682705 464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 465 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 466#ifdef TE_PE
467 {"secrel32", pe_directive_secrel, 0},
468#endif
29b0f896
AM		 469 {0, 0, 0}
470};
471
472/* For interface with expression (). */
473extern char *input_line_pointer;
474
475/* Hash table for instruction mnemonic lookup. */
476static struct hash_control *op_hash;
477
478/* Hash table for register lookup. */
479static struct hash_control *reg_hash;
480\f
252b5132
RH		 481void
482i386_align_code (fragP, count)
483 fragS *fragP;
484 int count;
485{
ce8a8b2f
AM		 486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
252b5132
RH		 489 static const char f32_1[] =
490 {0x90}; /* nop */
491 static const char f32_2[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5[] =
498 {0x90, /* nop */
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8[] =
505 {0x90, /* nop */
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 528 static const char f16_3[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 530 static const char f16_4[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5[] =
533 {0x90, /* nop */
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt[] = {
545 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
546 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
547 };
548 static const char *const f16_patt[] = {
c3332e24 549 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 550 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
551 };
552
33fef721
JH		 553 if (count <= 0 || count > 15)
554 return;
3e73aa7c 555
33fef721
JH		 556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code == CODE_64BIT)
252b5132 559 {
33fef721
JH		 560 int i;
561 int nnops = (count + 3) / 4;
562 int len = count / nnops;
563 int remains = count - nnops * len;
564 int pos = 0;
565
566 for (i = 0; i < remains; i++)
252b5132 567 {
33fef721
JH		 568 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
569 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
570 pos += len + 1;
571 }
572 for (; i < nnops; i++)
573 {
574 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
575 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
576 pos += len;
252b5132 577 }
252b5132 578 }
33fef721
JH		 579 else
580 if (flag_code == CODE_16BIT)
581 {
582 memcpy (fragP->fr_literal + fragP->fr_fix,
583 f16_patt[count - 1], count);
584 if (count > 8)
585 /* Adjust jump offset. */
586 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
587 }
588 else
589 memcpy (fragP->fr_literal + fragP->fr_fix,
590 f32_patt[count - 1], count);
591 fragP->fr_var = count;
252b5132
RH		 592}
593
252b5132
RH		 594static INLINE unsigned int
595mode_from_disp_size (t)
596 unsigned int t;
597{
3e73aa7c 598 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 599}
600
601static INLINE int
602fits_in_signed_byte (num)
847f7ad4 603 offsetT num;
252b5132
RH		 604{
605 return (num >= -128) && (num <= 127);
47926f60 606}
252b5132
RH		 607
608static INLINE int
609fits_in_unsigned_byte (num)
847f7ad4 610 offsetT num;
252b5132
RH		 611{
612 return (num & 0xff) == num;
47926f60 613}
252b5132
RH		 614
615static INLINE int
616fits_in_unsigned_word (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num & 0xffff) == num;
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_signed_word (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (-32768 <= num) && (num <= 32767);
47926f60 627}
3e73aa7c
JH		 628static INLINE int
629fits_in_signed_long (num)
630 offsetT num ATTRIBUTE_UNUSED;
631{
632#ifndef BFD64
633 return 1;
634#else
635 return (!(((offsetT) -1 << 31) & num)
636 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
637#endif
638} /* fits_in_signed_long() */
639static INLINE int
640fits_in_unsigned_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
642{
643#ifndef BFD64
644 return 1;
645#else
646 return (num & (((offsetT) 2 << 31) - 1)) == num;
647#endif
648} /* fits_in_unsigned_long() */
252b5132
RH		 649
650static int
651smallest_imm_type (num)
847f7ad4 652 offsetT num;
252b5132 653{
a847613f 654 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 655 {
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
660 use that form. */
661 if (num == 1)
3e73aa7c 662 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 663 }
252b5132 664 return (fits_in_signed_byte (num)
3e73aa7c 665 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 666 : fits_in_unsigned_byte (num)
3e73aa7c 667 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 668 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 669 ? (Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_signed_long (num)
671 ? (Imm32 | Imm32S | Imm64)
672 : fits_in_unsigned_long (num)
673 ? (Imm32 | Imm64)
674 : Imm64);
47926f60 675}
252b5132 676
847f7ad4
AM		 677static offsetT
678offset_in_range (val, size)
679 offsetT val;
680 int size;
681{
508866be 682 addressT mask;
ba2adb93 683
847f7ad4
AM		 684 switch (size)
685 {
508866be
L		 686 case 1: mask = ((addressT) 1 << 8) - 1; break;
687 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 688 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 689#ifdef BFD64
690 case 8: mask = ((addressT) 2 << 63) - 1; break;
691#endif
47926f60 692 default: abort ();
847f7ad4
AM		 693 }
694
ba2adb93 695 /* If BFD64, sign extend val. */
3e73aa7c
JH		 696 if (!use_rela_relocations)
697 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
698 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 699
47926f60 700 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 701 {
702 char buf1[40], buf2[40];
703
704 sprint_value (buf1, val);
705 sprint_value (buf2, val & mask);
706 as_warn (_("%s shortened to %s"), buf1, buf2);
707 }
708 return val & mask;
709}
710
252b5132
RH		 711/* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
713 added. */
714static int
715add_prefix (prefix)
716 unsigned int prefix;
717{
718 int ret = 1;
719 int q;
720
29b0f896
AM		 721 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
722 && flag_code == CODE_64BIT)
3e73aa7c
JH		 723 q = REX_PREFIX;
724 else
725 switch (prefix)
726 {
727 default:
728 abort ();
729
730 case CS_PREFIX_OPCODE:
731 case DS_PREFIX_OPCODE:
732 case ES_PREFIX_OPCODE:
733 case FS_PREFIX_OPCODE:
734 case GS_PREFIX_OPCODE:
735 case SS_PREFIX_OPCODE:
736 q = SEG_PREFIX;
737 break;
252b5132 738
3e73aa7c
JH		 739 case REPNE_PREFIX_OPCODE:
740 case REPE_PREFIX_OPCODE:
741 ret = 2;
742 /* fall thru */
743 case LOCK_PREFIX_OPCODE:
744 q = LOCKREP_PREFIX;
745 break;
252b5132 746
3e73aa7c
JH		 747 case FWAIT_OPCODE:
748 q = WAIT_PREFIX;
749 break;
252b5132 750
3e73aa7c
JH		 751 case ADDR_PREFIX_OPCODE:
752 q = ADDR_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case DATA_PREFIX_OPCODE:
756 q = DATA_PREFIX;
757 break;
758 }
252b5132 759
29b0f896 760 if (i.prefix[q] != 0)
252b5132
RH		 761 {
762 as_bad (_("same type of prefix used twice"));
763 return 0;
764 }
765
766 i.prefixes += 1;
767 i.prefix[q] = prefix;
768 return ret;
769}
770
771static void
3e73aa7c 772set_code_flag (value)
e5cb08ac 773 int value;
eecb386c 774{
3e73aa7c
JH		 775 flag_code = value;
776 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
777 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
779 {
780 as_bad (_("64bit mode not supported on this CPU."));
781 }
782 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
783 {
784 as_bad (_("32bit mode not supported on this CPU."));
785 }
eecb386c
AM		 786 stackop_size = '\0';
787}
788
789static void
3e73aa7c
JH		 790set_16bit_gcc_code_flag (new_code_flag)
791 int new_code_flag;
252b5132 792{
3e73aa7c
JH		 793 flag_code = new_code_flag;
794 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
795 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 796 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 797}
798
799static void
800set_intel_syntax (syntax_flag)
eecb386c 801 int syntax_flag;
252b5132
RH		 802{
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg = 0;
805
806 SKIP_WHITESPACE ();
29b0f896 807 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 808 {
809 char *string = input_line_pointer;
810 int e = get_symbol_end ();
811
47926f60 812 if (strcmp (string, "prefix") == 0)
252b5132 813 ask_naked_reg = 1;
47926f60 814 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 815 ask_naked_reg = -1;
816 else
d0b47220 817 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 818 *input_line_pointer = e;
819 }
820 demand_empty_rest_of_line ();
c3332e24 821
252b5132
RH		 822 intel_syntax = syntax_flag;
823
824 if (ask_naked_reg == 0)
f86103b7
AM		 825 allow_naked_reg = (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 827 else
828 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 829
830 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
831 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 832}
833
e413e4e9
AM		 834static void
835set_cpu_arch (dummy)
47926f60 836 int dummy ATTRIBUTE_UNUSED;
e413e4e9 837{
47926f60 838 SKIP_WHITESPACE ();
e413e4e9 839
29b0f896 840 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 841 {
842 char *string = input_line_pointer;
843 int e = get_symbol_end ();
844 int i;
845
846 for (i = 0; cpu_arch[i].name; i++)
847 {
848 if (strcmp (string, cpu_arch[i].name) == 0)
849 {
5c6af06e
JB		 850 if (*string != '.')
851 {
852 cpu_arch_name = cpu_arch[i].name;
853 cpu_sub_arch_name = NULL;
854 cpu_arch_flags = (cpu_arch[i].flags
855 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
856 break;
857 }
858 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
859 {
860 cpu_sub_arch_name = cpu_arch[i].name;
861 cpu_arch_flags |= cpu_arch[i].flags;
862 }
863 *input_line_pointer = e;
864 demand_empty_rest_of_line ();
865 return;
e413e4e9
AM		 866 }
867 }
868 if (!cpu_arch[i].name)
869 as_bad (_("no such architecture: `%s'"), string);
870
871 *input_line_pointer = e;
872 }
873 else
874 as_bad (_("missing cpu architecture"));
875
fddf5b5b
AM		 876 no_cond_jump_promotion = 0;
877 if (*input_line_pointer == ','
29b0f896 878 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 879 {
880 char *string = ++input_line_pointer;
881 int e = get_symbol_end ();
882
883 if (strcmp (string, "nojumps") == 0)
884 no_cond_jump_promotion = 1;
885 else if (strcmp (string, "jumps") == 0)
886 ;
887 else
888 as_bad (_("no such architecture modifier: `%s'"), string);
889
890 *input_line_pointer = e;
891 }
892
e413e4e9
AM		 893 demand_empty_rest_of_line ();
894}
895
b9d79e03
JH		 896unsigned long
897i386_mach ()
898{
899 if (!strcmp (default_arch, "x86_64"))
900 return bfd_mach_x86_64;
901 else if (!strcmp (default_arch, "i386"))
902 return bfd_mach_i386_i386;
903 else
904 as_fatal (_("Unknown architecture"));
905}
b9d79e03 906\f
252b5132
RH		 907void
908md_begin ()
909{
910 const char *hash_err;
911
47926f60 912 /* Initialize op_hash hash table. */
252b5132
RH		 913 op_hash = hash_new ();
914
915 {
29b0f896
AM		 916 const template *optab;
917 templates *core_optab;
252b5132 918
47926f60
KH		 919 /* Setup for loop. */
920 optab = i386_optab;
252b5132
RH		 921 core_optab = (templates *) xmalloc (sizeof (templates));
922 core_optab->start = optab;
923
924 while (1)
925 {
926 ++optab;
927 if (optab->name == NULL
928 || strcmp (optab->name, (optab - 1)->name) != 0)
929 {
930 /* different name --> ship out current template list;
47926f60 931 add to hash table; & begin anew. */
252b5132
RH		 932 core_optab->end = optab;
933 hash_err = hash_insert (op_hash,
934 (optab - 1)->name,
935 (PTR) core_optab);
936 if (hash_err)
937 {
252b5132
RH		 938 as_fatal (_("Internal Error: Can't hash %s: %s"),
939 (optab - 1)->name,
940 hash_err);
941 }
942 if (optab->name == NULL)
943 break;
944 core_optab = (templates *) xmalloc (sizeof (templates));
945 core_optab->start = optab;
946 }
947 }
948 }
949
47926f60 950 /* Initialize reg_hash hash table. */
252b5132
RH		 951 reg_hash = hash_new ();
952 {
29b0f896 953 const reg_entry *regtab;
252b5132
RH		 954
955 for (regtab = i386_regtab;
956 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
957 regtab++)
958 {
959 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
960 if (hash_err)
3e73aa7c
JH		 961 as_fatal (_("Internal Error: Can't hash %s: %s"),
962 regtab->reg_name,
963 hash_err);
252b5132
RH		 964 }
965 }
966
47926f60 967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 968 {
29b0f896
AM		 969 int c;
970 char *p;
252b5132
RH		 971
972 for (c = 0; c < 256; c++)
973 {
3882b010 974 if (ISDIGIT (c))
252b5132
RH		 975 {
976 digit_chars[c] = c;
977 mnemonic_chars[c] = c;
978 register_chars[c] = c;
979 operand_chars[c] = c;
980 }
3882b010 981 else if (ISLOWER (c))
252b5132
RH		 982 {
983 mnemonic_chars[c] = c;
984 register_chars[c] = c;
985 operand_chars[c] = c;
986 }
3882b010 987 else if (ISUPPER (c))
252b5132 988 {
3882b010 989 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 990 register_chars[c] = mnemonic_chars[c];
991 operand_chars[c] = c;
992 }
993
3882b010 994 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 995 identifier_chars[c] = c;
996 else if (c >= 128)
997 {
998 identifier_chars[c] = c;
999 operand_chars[c] = c;
1000 }
1001 }
1002
1003#ifdef LEX_AT
1004 identifier_chars['@'] = '@';
32137342
NC		 1005#endif
1006#ifdef LEX_QM
1007 identifier_chars['?'] = '?';
1008 operand_chars['?'] = '?';
252b5132 1009#endif
252b5132
RH		 1010 digit_chars['-'] = '-';
1011 identifier_chars['_'] = '_';
1012 identifier_chars['.'] = '.';
1013
1014 for (p = operand_special_chars; *p != '\0'; p++)
1015 operand_chars[(unsigned char) *p] = *p;
1016 }
1017
1018#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1019 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1020 {
1021 record_alignment (text_section, 2);
1022 record_alignment (data_section, 2);
1023 record_alignment (bss_section, 2);
1024 }
1025#endif
a4447b93
RH		 1026
1027 if (flag_code == CODE_64BIT)
1028 {
1029 x86_dwarf2_return_column = 16;
1030 x86_cie_data_alignment = -8;
1031 }
1032 else
1033 {
1034 x86_dwarf2_return_column = 8;
1035 x86_cie_data_alignment = -4;
1036 }
252b5132
RH		 1037}
1038
1039void
1040i386_print_statistics (file)
1041 FILE *file;
1042{
1043 hash_print_statistics (file, "i386 opcode", op_hash);
1044 hash_print_statistics (file, "i386 register", reg_hash);
1045}
1046\f
252b5132
RH		 1047#ifdef DEBUG386
1048
ce8a8b2f 1049/* Debugging routines for md_assemble. */
252b5132
RH		 1050static void pi PARAMS ((char *, i386_insn *));
1051static void pte PARAMS ((template *));
1052static void pt PARAMS ((unsigned int));
1053static void pe PARAMS ((expressionS *));
1054static void ps PARAMS ((symbolS *));
1055
1056static void
1057pi (line, x)
1058 char *line;
1059 i386_insn *x;
1060{
09f131f2 1061 unsigned int i;
252b5132
RH		 1062
1063 fprintf (stdout, "%s: template ", line);
1064 pte (&x->tm);
09f131f2
JH		 1065 fprintf (stdout, " address: base %s index %s scale %x\n",
1066 x->base_reg ? x->base_reg->reg_name : "none",
1067 x->index_reg ? x->index_reg->reg_name : "none",
1068 x->log2_scale_factor);
1069 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1070 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1071 fprintf (stdout, " sib: base %x index %x scale %x\n",
1072 x->sib.base, x->sib.index, x->sib.scale);
1073 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1074 (x->rex & REX_MODE64) != 0,
1075 (x->rex & REX_EXTX) != 0,
1076 (x->rex & REX_EXTY) != 0,
1077 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1078 for (i = 0; i < x->operands; i++)
1079 {
1080 fprintf (stdout, " #%d: ", i + 1);
1081 pt (x->types[i]);
1082 fprintf (stdout, "\n");
1083 if (x->types[i]
3f4438ab 1084 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1085 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1086 if (x->types[i] & Imm)
520dc8e8 1087 pe (x->op[i].imms);
252b5132 1088 if (x->types[i] & Disp)
520dc8e8 1089 pe (x->op[i].disps);
252b5132
RH		 1090 }
1091}
1092
1093static void
1094pte (t)
1095 template *t;
1096{
09f131f2 1097 unsigned int i;
252b5132 1098 fprintf (stdout, " %d operands ", t->operands);
47926f60 1099 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1100 if (t->extension_opcode != None)
1101 fprintf (stdout, "ext %x ", t->extension_opcode);
1102 if (t->opcode_modifier & D)
1103 fprintf (stdout, "D");
1104 if (t->opcode_modifier & W)
1105 fprintf (stdout, "W");
1106 fprintf (stdout, "\n");
1107 for (i = 0; i < t->operands; i++)
1108 {
1109 fprintf (stdout, " #%d type ", i + 1);
1110 pt (t->operand_types[i]);
1111 fprintf (stdout, "\n");
1112 }
1113}
1114
1115static void
1116pe (e)
1117 expressionS *e;
1118{
24eab124 1119 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1120 fprintf (stdout, " add_number %ld (%lx)\n",
1121 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1122 if (e->X_add_symbol)
1123 {
1124 fprintf (stdout, " add_symbol ");
1125 ps (e->X_add_symbol);
1126 fprintf (stdout, "\n");
1127 }
1128 if (e->X_op_symbol)
1129 {
1130 fprintf (stdout, " op_symbol ");
1131 ps (e->X_op_symbol);
1132 fprintf (stdout, "\n");
1133 }
1134}
1135
1136static void
1137ps (s)
1138 symbolS *s;
1139{
1140 fprintf (stdout, "%s type %s%s",
1141 S_GET_NAME (s),
1142 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1143 segment_name (S_GET_SEGMENT (s)));
1144}
1145
1146struct type_name
1147 {
1148 unsigned int mask;
1149 char *tname;
1150 }
1151
29b0f896 1152static const type_names[] =
252b5132
RH		 1153{
1154 { Reg8, "r8" },
1155 { Reg16, "r16" },
1156 { Reg32, "r32" },
09f131f2 1157 { Reg64, "r64" },
252b5132
RH		 1158 { Imm8, "i8" },
1159 { Imm8S, "i8s" },
1160 { Imm16, "i16" },
1161 { Imm32, "i32" },
09f131f2
JH		 1162 { Imm32S, "i32s" },
1163 { Imm64, "i64" },
252b5132
RH		 1164 { Imm1, "i1" },
1165 { BaseIndex, "BaseIndex" },
1166 { Disp8, "d8" },
1167 { Disp16, "d16" },
1168 { Disp32, "d32" },
09f131f2
JH		 1169 { Disp32S, "d32s" },
1170 { Disp64, "d64" },
252b5132
RH		 1171 { InOutPortReg, "InOutPortReg" },
1172 { ShiftCount, "ShiftCount" },
1173 { Control, "control reg" },
1174 { Test, "test reg" },
1175 { Debug, "debug reg" },
1176 { FloatReg, "FReg" },
1177 { FloatAcc, "FAcc" },
1178 { SReg2, "SReg2" },
1179 { SReg3, "SReg3" },
1180 { Acc, "Acc" },
1181 { JumpAbsolute, "Jump Absolute" },
1182 { RegMMX, "rMMX" },
3f4438ab 1183 { RegXMM, "rXMM" },
252b5132
RH		 1184 { EsSeg, "es" },
1185 { 0, "" }
1186};
1187
1188static void
1189pt (t)
1190 unsigned int t;
1191{
29b0f896 1192 const struct type_name *ty;
252b5132 1193
09f131f2
JH		 1194 for (ty = type_names; ty->mask; ty++)
1195 if (t & ty->mask)
1196 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1197 fflush (stdout);
1198}
1199
1200#endif /* DEBUG386 */
1201\f
29b0f896
AM		 1202static bfd_reloc_code_real_type reloc
1203 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1204
1205static bfd_reloc_code_real_type
3e73aa7c 1206reloc (size, pcrel, sign, other)
252b5132
RH		 1207 int size;
1208 int pcrel;
3e73aa7c 1209 int sign;
252b5132
RH		 1210 bfd_reloc_code_real_type other;
1211{
47926f60
KH		 1212 if (other != NO_RELOC)
1213 return other;
252b5132
RH		 1214
1215 if (pcrel)
1216 {
3e73aa7c 1217 if (!sign)
e5cb08ac 1218 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1219 switch (size)
1220 {
1221 case 1: return BFD_RELOC_8_PCREL;
1222 case 2: return BFD_RELOC_16_PCREL;
1223 case 4: return BFD_RELOC_32_PCREL;
1224 }
d0b47220 1225 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1226 }
1227 else
1228 {
3e73aa7c 1229 if (sign)
e5cb08ac 1230 switch (size)
3e73aa7c
JH		 1231 {
1232 case 4: return BFD_RELOC_X86_64_32S;
1233 }
1234 else
1235 switch (size)
1236 {
1237 case 1: return BFD_RELOC_8;
1238 case 2: return BFD_RELOC_16;
1239 case 4: return BFD_RELOC_32;
1240 case 8: return BFD_RELOC_64;
1241 }
1242 as_bad (_("can not do %s %d byte relocation"),
1243 sign ? "signed" : "unsigned", size);
252b5132
RH		 1244 }
1245
bfb32b52 1246 abort ();
252b5132
RH		 1247 return BFD_RELOC_NONE;
1248}
1249
47926f60
KH		 1250/* Here we decide which fixups can be adjusted to make them relative to
1251 the beginning of the section instead of the symbol. Basically we need
1252 to make sure that the dynamic relocations are done correctly, so in
1253 some cases we force the original symbol to be used. */
1254
252b5132 1255int
c0c949c7 1256tc_i386_fix_adjustable (fixP)
31312f95 1257 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1258{
6d249963 1259#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1260 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1261 return 1;
1262
a161fe53
AM		 1263 /* Don't adjust pc-relative references to merge sections in 64-bit
1264 mode. */
1265 if (use_rela_relocations
1266 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1267 && fixP->fx_pcrel)
252b5132 1268 return 0;
31312f95 1269
8d01d9a9
AJ		 1270 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1271 and changed later by validate_fix. */
1272 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1273 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1274 return 0;
1275
ce8a8b2f 1276 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1277 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1278 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1279 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1280 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1281 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1282 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1283 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1284 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1285 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1288 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1289 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1290 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1291 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1292 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1293 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1296 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1297 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1298 return 0;
31312f95 1299#endif
252b5132
RH		 1300 return 1;
1301}
252b5132 1302
29b0f896 1303static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1304
1305static int
252b5132 1306intel_float_operand (mnemonic)
29b0f896 1307 const char *mnemonic;
252b5132 1308{
9306ca4a
JB		 1309 /* Note that the value returned is meaningful only for opcodes with (memory)
1310 operands, hence the code here is free to improperly handle opcodes that
1311 have no operands (for better performance and smaller code). */
1312
1313 if (mnemonic[0] != 'f')
1314 return 0; /* non-math */
1315
1316 switch (mnemonic[1])
1317 {
1318 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1319 the fs segment override prefix not currently handled because no
1320 call path can make opcodes without operands get here */
1321 case 'i':
1322 return 2 /* integer op */;
1323 case 'l':
1324 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1325 return 3; /* fldcw/fldenv */
1326 break;
1327 case 'n':
1328 if (mnemonic[2] != 'o' /* fnop */)
1329 return 3; /* non-waiting control op */
1330 break;
1331 case 'r':
1332 if (mnemonic[2] == 's')
1333 return 3; /* frstor/frstpm */
1334 break;
1335 case 's':
1336 if (mnemonic[2] == 'a')
1337 return 3; /* fsave */
1338 if (mnemonic[2] == 't')
1339 {
1340 switch (mnemonic[3])
1341 {
1342 case 'c': /* fstcw */
1343 case 'd': /* fstdw */
1344 case 'e': /* fstenv */
1345 case 's': /* fsts[gw] */
1346 return 3;
1347 }
1348 }
1349 break;
1350 case 'x':
1351 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1352 return 0; /* fxsave/fxrstor are not really math ops */
1353 break;
1354 }
252b5132 1355
9306ca4a 1356 return 1;
252b5132
RH		 1357}
1358
1359/* This is the guts of the machine-dependent assembler. LINE points to a
1360 machine dependent instruction. This function is supposed to emit
1361 the frags/bytes it assembles to. */
1362
1363void
1364md_assemble (line)
1365 char *line;
1366{
252b5132 1367 int j;
252b5132
RH		 1368 char mnemonic[MAX_MNEM_SIZE];
1369
47926f60 1370 /* Initialize globals. */
252b5132
RH		 1371 memset (&i, '\0', sizeof (i));
1372 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1373 i.reloc[j] = NO_RELOC;
252b5132
RH		 1374 memset (disp_expressions, '\0', sizeof (disp_expressions));
1375 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1376 save_stack_p = save_stack;
252b5132
RH		 1377
1378 /* First parse an instruction mnemonic & call i386_operand for the operands.
1379 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1380 start of a (possibly prefixed) mnemonic. */
252b5132 1381
29b0f896
AM		 1382 line = parse_insn (line, mnemonic);
1383 if (line == NULL)
1384 return;
252b5132 1385
29b0f896
AM		 1386 line = parse_operands (line, mnemonic);
1387 if (line == NULL)
1388 return;
252b5132 1389
29b0f896
AM		 1390 /* Now we've parsed the mnemonic into a set of templates, and have the
1391 operands at hand. */
1392
1393 /* All intel opcodes have reversed operands except for "bound" and
1394 "enter". We also don't reverse intersegment "jmp" and "call"
1395 instructions with 2 immediate operands so that the immediate segment
1396 precedes the offset, as it does when in AT&T mode. "enter" and the
1397 intersegment "jmp" and "call" instructions are the only ones that
1398 have two immediate operands. */
1399 if (intel_syntax && i.operands > 1
1400 && (strcmp (mnemonic, "bound") != 0)
1401 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1402 swap_operands ();
1403
1404 if (i.imm_operands)
1405 optimize_imm ();
1406
1407 if (i.disp_operands)
1408 optimize_disp ();
1409
1410 /* Next, we find a template that matches the given insn,
1411 making sure the overlap of the given operands types is consistent
1412 with the template operand types. */
252b5132 1413
29b0f896
AM		 1414 if (!match_template ())
1415 return;
252b5132 1416
cd61ebfe
AM		 1417 if (intel_syntax)
1418 {
1419 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1420 if (SYSV386_COMPAT
1421 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1422 i.tm.base_opcode ^= FloatR;
1423
1424 /* Zap movzx and movsx suffix. The suffix may have been set from
1425 "word ptr" or "byte ptr" on the source operand, but we'll use
1426 the suffix later to choose the destination register. */
1427 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1428 {
1429 if (i.reg_operands < 2
1430 && !i.suffix
1431 && (~i.tm.opcode_modifier
1432 & (No_bSuf
1433 | No_wSuf
1434 | No_lSuf
1435 | No_sSuf
1436 | No_xSuf
1437 | No_qSuf)))
1438 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1439
1440 i.suffix = 0;
1441 }
cd61ebfe 1442 }
24eab124 1443
29b0f896
AM		 1444 if (i.tm.opcode_modifier & FWait)
1445 if (!add_prefix (FWAIT_OPCODE))
1446 return;
252b5132 1447
29b0f896
AM		 1448 /* Check string instruction segment overrides. */
1449 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1450 {
1451 if (!check_string ())
5dd0794d 1452 return;
29b0f896 1453 }
5dd0794d 1454
29b0f896
AM		 1455 if (!process_suffix ())
1456 return;
e413e4e9 1457
29b0f896
AM		 1458 /* Make still unresolved immediate matches conform to size of immediate
1459 given in i.suffix. */
1460 if (!finalize_imm ())
1461 return;
252b5132 1462
29b0f896
AM		 1463 if (i.types[0] & Imm1)
1464 i.imm_operands = 0; /* kludge for shift insns. */
1465 if (i.types[0] & ImplicitRegister)
1466 i.reg_operands--;
1467 if (i.types[1] & ImplicitRegister)
1468 i.reg_operands--;
1469 if (i.types[2] & ImplicitRegister)
1470 i.reg_operands--;
252b5132 1471
29b0f896
AM		 1472 if (i.tm.opcode_modifier & ImmExt)
1473 {
02fc3089
L		 1474 expressionS *exp;
1475
ca164297
L		 1476 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1477 {
67c1ffbe 1478 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1479 operands with an opcode suffix which is coded in the same
1480 place as an 8-bit immediate field would be. Here we check
1481 those operands and remove them afterwards. */
1482 unsigned int x;
1483
a4622f40 1484 for (x = 0; x < i.operands; x++)
ca164297
L		 1485 if (i.op[x].regs->reg_num != x)
1486 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1487 i.op[x].regs->reg_name, x + 1, i.tm.name);
1488 i.operands = 0;
1489 }
1490
29b0f896
AM		 1491 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1492 opcode suffix which is coded in the same place as an 8-bit
1493 immediate field would be. Here we fake an 8-bit immediate
1494 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1495
29b0f896 1496 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1497
29b0f896
AM		 1498 exp = &im_expressions[i.imm_operands++];
1499 i.op[i.operands].imms = exp;
1500 i.types[i.operands++] = Imm8;
1501 exp->X_op = O_constant;
1502 exp->X_add_number = i.tm.extension_opcode;
1503 i.tm.extension_opcode = None;
1504 }
252b5132 1505
29b0f896
AM		 1506 /* For insns with operands there are more diddles to do to the opcode. */
1507 if (i.operands)
1508 {
1509 if (!process_operands ())
1510 return;
1511 }
1512 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1513 {
1514 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1515 as_warn (_("translating to `%sp'"), i.tm.name);
1516 }
252b5132 1517
29b0f896
AM		 1518 /* Handle conversion of 'int $3' --> special int3 insn. */
1519 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1520 {
1521 i.tm.base_opcode = INT3_OPCODE;
1522 i.imm_operands = 0;
1523 }
252b5132 1524
29b0f896
AM		 1525 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1526 && i.op[0].disps->X_op == O_constant)
1527 {
1528 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1529 the absolute address given by the constant. Since ix86 jumps and
1530 calls are pc relative, we need to generate a reloc. */
1531 i.op[0].disps->X_add_symbol = &abs_symbol;
1532 i.op[0].disps->X_op = O_symbol;
1533 }
252b5132 1534
29b0f896
AM		 1535 if ((i.tm.opcode_modifier & Rex64) != 0)
1536 i.rex |= REX_MODE64;
252b5132 1537
29b0f896
AM		 1538 /* For 8 bit registers we need an empty rex prefix. Also if the
1539 instruction already has a prefix, we need to convert old
1540 registers to new ones. */
773f551c 1541
29b0f896
AM		 1542 if (((i.types[0] & Reg8) != 0
1543 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1544 || ((i.types[1] & Reg8) != 0
1545 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1546 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1547 && i.rex != 0))
1548 {
1549 int x;
726c5dcd 1550
29b0f896
AM		 1551 i.rex |= REX_OPCODE;
1552 for (x = 0; x < 2; x++)
1553 {
1554 /* Look for 8 bit operand that uses old registers. */
1555 if ((i.types[x] & Reg8) != 0
1556 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1557 {
29b0f896
AM		 1558 /* In case it is "hi" register, give up. */
1559 if (i.op[x].regs->reg_num > 3)
0477af35 1560 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1561 i.op[x].regs->reg_name);
773f551c 1562
29b0f896
AM		 1563 /* Otherwise it is equivalent to the extended register.
1564 Since the encoding doesn't change this is merely
1565 cosmetic cleanup for debug output. */
1566
1567 i.op[x].regs = i.op[x].regs + 8;
773f551c 1568 }
29b0f896
AM		 1569 }
1570 }
773f551c 1571
29b0f896
AM		 1572 if (i.rex != 0)
1573 add_prefix (REX_OPCODE | i.rex);
1574
1575 /* We are ready to output the insn. */
1576 output_insn ();
1577}
1578
1579static char *
1580parse_insn (line, mnemonic)
1581 char *line;
1582 char *mnemonic;
1583{
1584 char *l = line;
1585 char *token_start = l;
1586 char *mnem_p;
5c6af06e
JB		 1587 int supported;
1588 const template *t;
29b0f896
AM		 1589
1590 /* Non-zero if we found a prefix only acceptable with string insns. */
1591 const char *expecting_string_instruction = NULL;
45288df1 1592
29b0f896
AM		 1593 while (1)
1594 {
1595 mnem_p = mnemonic;
1596 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1597 {
1598 mnem_p++;
1599 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1600 {
29b0f896
AM		 1601 as_bad (_("no such instruction: `%s'"), token_start);
1602 return NULL;
1603 }
1604 l++;
1605 }
1606 if (!is_space_char (*l)
1607 && *l != END_OF_INSN
1608 && *l != PREFIX_SEPARATOR
1609 && *l != ',')
1610 {
1611 as_bad (_("invalid character %s in mnemonic"),
1612 output_invalid (*l));
1613 return NULL;
1614 }
1615 if (token_start == l)
1616 {
1617 if (*l == PREFIX_SEPARATOR)
1618 as_bad (_("expecting prefix; got nothing"));
1619 else
1620 as_bad (_("expecting mnemonic; got nothing"));
1621 return NULL;
1622 }
45288df1 1623
29b0f896
AM		 1624 /* Look up instruction (or prefix) via hash table. */
1625 current_templates = hash_find (op_hash, mnemonic);
47926f60 1626
29b0f896
AM		 1627 if (*l != END_OF_INSN
1628 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1629 && current_templates
1630 && (current_templates->start->opcode_modifier & IsPrefix))
1631 {
1632 /* If we are in 16-bit mode, do not allow addr16 or data16.
1633 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1634 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1635 && flag_code != CODE_64BIT
1636 && (((current_templates->start->opcode_modifier & Size32) != 0)
1637 ^ (flag_code == CODE_16BIT)))
1638 {
1639 as_bad (_("redundant %s prefix"),
1640 current_templates->start->name);
1641 return NULL;
45288df1 1642 }
29b0f896
AM		 1643 /* Add prefix, checking for repeated prefixes. */
1644 switch (add_prefix (current_templates->start->base_opcode))
1645 {
1646 case 0:
1647 return NULL;
1648 case 2:
1649 expecting_string_instruction = current_templates->start->name;
1650 break;
1651 }
1652 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1653 token_start = ++l;
1654 }
1655 else
1656 break;
1657 }
45288df1 1658
29b0f896
AM		 1659 if (!current_templates)
1660 {
1661 /* See if we can get a match by trimming off a suffix. */
1662 switch (mnem_p[-1])
1663 {
1664 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1665 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1666 i.suffix = SHORT_MNEM_SUFFIX;
1667 else
29b0f896
AM		 1668 case BYTE_MNEM_SUFFIX:
1669 case QWORD_MNEM_SUFFIX:
1670 i.suffix = mnem_p[-1];
1671 mnem_p[-1] = '\0';
1672 current_templates = hash_find (op_hash, mnemonic);
1673 break;
1674 case SHORT_MNEM_SUFFIX:
1675 case LONG_MNEM_SUFFIX:
1676 if (!intel_syntax)
1677 {
1678 i.suffix = mnem_p[-1];
1679 mnem_p[-1] = '\0';
1680 current_templates = hash_find (op_hash, mnemonic);
1681 }
1682 break;
252b5132 1683
29b0f896
AM		 1684 /* Intel Syntax. */
1685 case 'd':
1686 if (intel_syntax)
1687 {
9306ca4a 1688 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1689 i.suffix = SHORT_MNEM_SUFFIX;
1690 else
1691 i.suffix = LONG_MNEM_SUFFIX;
1692 mnem_p[-1] = '\0';
1693 current_templates = hash_find (op_hash, mnemonic);
1694 }
1695 break;
1696 }
1697 if (!current_templates)
1698 {
1699 as_bad (_("no such instruction: `%s'"), token_start);
1700 return NULL;
1701 }
1702 }
252b5132 1703
29b0f896
AM		 1704 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1705 {
1706 /* Check for a branch hint. We allow ",pt" and ",pn" for
1707 predict taken and predict not taken respectively.
1708 I'm not sure that branch hints actually do anything on loop
1709 and jcxz insns (JumpByte) for current Pentium4 chips. They
1710 may work in the future and it doesn't hurt to accept them
1711 now. */
1712 if (l[0] == ',' && l[1] == 'p')
1713 {
1714 if (l[2] == 't')
1715 {
1716 if (!add_prefix (DS_PREFIX_OPCODE))
1717 return NULL;
1718 l += 3;
1719 }
1720 else if (l[2] == 'n')
1721 {
1722 if (!add_prefix (CS_PREFIX_OPCODE))
1723 return NULL;
1724 l += 3;
1725 }
1726 }
1727 }
1728 /* Any other comma loses. */
1729 if (*l == ',')
1730 {
1731 as_bad (_("invalid character %s in mnemonic"),
1732 output_invalid (*l));
1733 return NULL;
1734 }
252b5132 1735
29b0f896 1736 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1737 supported = 0;
1738 for (t = current_templates->start; t < current_templates->end; ++t)
1739 {
1740 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1741 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1742 supported |= 1;
1743 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1744 supported |= 2;
1745 }
1746 if (!(supported & 2))
1747 {
1748 as_bad (flag_code == CODE_64BIT
1749 ? _("`%s' is not supported in 64-bit mode")
1750 : _("`%s' is only supported in 64-bit mode"),
1751 current_templates->start->name);
1752 return NULL;
1753 }
1754 if (!(supported & 1))
29b0f896 1755 {
5c6af06e
JB		 1756 as_warn (_("`%s' is not supported on `%s%s'"),
1757 current_templates->start->name,
1758 cpu_arch_name,
1759 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1760 }
1761 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1762 {
1763 as_warn (_("use .code16 to ensure correct addressing mode"));
1764 }
252b5132 1765
29b0f896
AM		 1766 /* Check for rep/repne without a string instruction. */
1767 if (expecting_string_instruction
1768 && !(current_templates->start->opcode_modifier & IsString))
1769 {
1770 as_bad (_("expecting string instruction after `%s'"),
1771 expecting_string_instruction);
1772 return NULL;
1773 }
252b5132 1774
29b0f896
AM		 1775 return l;
1776}
252b5132 1777
29b0f896
AM		 1778static char *
1779parse_operands (l, mnemonic)
1780 char *l;
1781 const char *mnemonic;
1782{
1783 char *token_start;
3138f287 1784
29b0f896
AM		 1785 /* 1 if operand is pending after ','. */
1786 unsigned int expecting_operand = 0;
252b5132 1787
29b0f896
AM		 1788 /* Non-zero if operand parens not balanced. */
1789 unsigned int paren_not_balanced;
1790
1791 while (*l != END_OF_INSN)
1792 {
1793 /* Skip optional white space before operand. */
1794 if (is_space_char (*l))
1795 ++l;
1796 if (!is_operand_char (*l) && *l != END_OF_INSN)
1797 {
1798 as_bad (_("invalid character %s before operand %d"),
1799 output_invalid (*l),
1800 i.operands + 1);
1801 return NULL;
1802 }
1803 token_start = l; /* after white space */
1804 paren_not_balanced = 0;
1805 while (paren_not_balanced || *l != ',')
1806 {
1807 if (*l == END_OF_INSN)
1808 {
1809 if (paren_not_balanced)
1810 {
1811 if (!intel_syntax)
1812 as_bad (_("unbalanced parenthesis in operand %d."),
1813 i.operands + 1);
1814 else
1815 as_bad (_("unbalanced brackets in operand %d."),
1816 i.operands + 1);
1817 return NULL;
1818 }
1819 else
1820 break; /* we are done */
1821 }
1822 else if (!is_operand_char (*l) && !is_space_char (*l))
1823 {
1824 as_bad (_("invalid character %s in operand %d"),
1825 output_invalid (*l),
1826 i.operands + 1);
1827 return NULL;
1828 }
1829 if (!intel_syntax)
1830 {
1831 if (*l == '(')
1832 ++paren_not_balanced;
1833 if (*l == ')')
1834 --paren_not_balanced;
1835 }
1836 else
1837 {
1838 if (*l == '[')
1839 ++paren_not_balanced;
1840 if (*l == ']')
1841 --paren_not_balanced;
1842 }
1843 l++;
1844 }
1845 if (l != token_start)
1846 { /* Yes, we've read in another operand. */
1847 unsigned int operand_ok;
1848 this_operand = i.operands++;
1849 if (i.operands > MAX_OPERANDS)
1850 {
1851 as_bad (_("spurious operands; (%d operands/instruction max)"),
1852 MAX_OPERANDS);
1853 return NULL;
1854 }
1855 /* Now parse operand adding info to 'i' as we go along. */
1856 END_STRING_AND_SAVE (l);
1857
1858 if (intel_syntax)
1859 operand_ok =
1860 i386_intel_operand (token_start,
1861 intel_float_operand (mnemonic));
1862 else
1863 operand_ok = i386_operand (token_start);
1864
1865 RESTORE_END_STRING (l);
1866 if (!operand_ok)
1867 return NULL;
1868 }
1869 else
1870 {
1871 if (expecting_operand)
1872 {
1873 expecting_operand_after_comma:
1874 as_bad (_("expecting operand after ','; got nothing"));
1875 return NULL;
1876 }
1877 if (*l == ',')
1878 {
1879 as_bad (_("expecting operand before ','; got nothing"));
1880 return NULL;
1881 }
1882 }
7f3f1ea2 1883
29b0f896
AM		 1884 /* Now *l must be either ',' or END_OF_INSN. */
1885 if (*l == ',')
1886 {
1887 if (*++l == END_OF_INSN)
1888 {
1889 /* Just skip it, if it's \n complain. */
1890 goto expecting_operand_after_comma;
1891 }
1892 expecting_operand = 1;
1893 }
1894 }
1895 return l;
1896}
7f3f1ea2 1897
29b0f896
AM		 1898static void
1899swap_operands ()
1900{
1901 union i386_op temp_op;
1902 unsigned int temp_type;
f86103b7 1903 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1904 int xchg1 = 0;
1905 int xchg2 = 0;
252b5132 1906
29b0f896
AM		 1907 if (i.operands == 2)
1908 {
1909 xchg1 = 0;
1910 xchg2 = 1;
1911 }
1912 else if (i.operands == 3)
1913 {
1914 xchg1 = 0;
1915 xchg2 = 2;
1916 }
1917 temp_type = i.types[xchg2];
1918 i.types[xchg2] = i.types[xchg1];
1919 i.types[xchg1] = temp_type;
1920 temp_op = i.op[xchg2];
1921 i.op[xchg2] = i.op[xchg1];
1922 i.op[xchg1] = temp_op;
1923 temp_reloc = i.reloc[xchg2];
1924 i.reloc[xchg2] = i.reloc[xchg1];
1925 i.reloc[xchg1] = temp_reloc;
1926
1927 if (i.mem_operands == 2)
1928 {
1929 const seg_entry *temp_seg;
1930 temp_seg = i.seg[0];
1931 i.seg[0] = i.seg[1];
1932 i.seg[1] = temp_seg;
1933 }
1934}
252b5132 1935
29b0f896
AM		 1936/* Try to ensure constant immediates are represented in the smallest
1937 opcode possible. */
1938static void
1939optimize_imm ()
1940{
1941 char guess_suffix = 0;
1942 int op;
252b5132 1943
29b0f896
AM		 1944 if (i.suffix)
1945 guess_suffix = i.suffix;
1946 else if (i.reg_operands)
1947 {
1948 /* Figure out a suffix from the last register operand specified.
1949 We can't do this properly yet, ie. excluding InOutPortReg,
1950 but the following works for instructions with immediates.
1951 In any case, we can't set i.suffix yet. */
1952 for (op = i.operands; --op >= 0;)
1953 if (i.types[op] & Reg)
252b5132 1954 {
29b0f896
AM		 1955 if (i.types[op] & Reg8)
1956 guess_suffix = BYTE_MNEM_SUFFIX;
1957 else if (i.types[op] & Reg16)
1958 guess_suffix = WORD_MNEM_SUFFIX;
1959 else if (i.types[op] & Reg32)
1960 guess_suffix = LONG_MNEM_SUFFIX;
1961 else if (i.types[op] & Reg64)
1962 guess_suffix = QWORD_MNEM_SUFFIX;
1963 break;
252b5132 1964 }
29b0f896
AM		 1965 }
1966 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1967 guess_suffix = WORD_MNEM_SUFFIX;
1968
1969 for (op = i.operands; --op >= 0;)
1970 if (i.types[op] & Imm)
1971 {
1972 switch (i.op[op].imms->X_op)
252b5132 1973 {
29b0f896
AM		 1974 case O_constant:
1975 /* If a suffix is given, this operand may be shortened. */
1976 switch (guess_suffix)
252b5132 1977 {
29b0f896
AM		 1978 case LONG_MNEM_SUFFIX:
1979 i.types[op] |= Imm32 | Imm64;
1980 break;
1981 case WORD_MNEM_SUFFIX:
1982 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1983 break;
1984 case BYTE_MNEM_SUFFIX:
1985 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1986 break;
252b5132 1987 }
252b5132 1988
29b0f896
AM		 1989 /* If this operand is at most 16 bits, convert it
1990 to a signed 16 bit number before trying to see
1991 whether it will fit in an even smaller size.
1992 This allows a 16-bit operand such as $0xffe0 to
1993 be recognised as within Imm8S range. */
1994 if ((i.types[op] & Imm16)
1995 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1996 {
29b0f896
AM		 1997 i.op[op].imms->X_add_number =
1998 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1999 }
2000 if ((i.types[op] & Imm32)
2001 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2002 == 0))
2003 {
2004 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2005 ^ ((offsetT) 1 << 31))
2006 - ((offsetT) 1 << 31));
2007 }
2008 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2009
29b0f896
AM		 2010 /* We must avoid matching of Imm32 templates when 64bit
2011 only immediate is available. */
2012 if (guess_suffix == QWORD_MNEM_SUFFIX)
2013 i.types[op] &= ~Imm32;
2014 break;
252b5132 2015
29b0f896
AM		 2016 case O_absent:
2017 case O_register:
2018 abort ();
2019
2020 /* Symbols and expressions. */
2021 default:
2022 /* Convert symbolic operand to proper sizes for matching. */
2023 switch (guess_suffix)
2024 {
2025 case QWORD_MNEM_SUFFIX:
2026 i.types[op] = Imm64 | Imm32S;
2027 break;
2028 case LONG_MNEM_SUFFIX:
20f0a1fc 2029 i.types[op] = Imm32;
29b0f896
AM		 2030 break;
2031 case WORD_MNEM_SUFFIX:
20f0a1fc 2032 i.types[op] = Imm16;
29b0f896
AM		 2033 break;
2034 case BYTE_MNEM_SUFFIX:
20f0a1fc 2035 i.types[op] = Imm8 | Imm8S;
29b0f896 2036 break;
252b5132 2037 }
29b0f896 2038 break;
252b5132 2039 }
29b0f896
AM		 2040 }
2041}
47926f60 2042
29b0f896
AM		 2043/* Try to use the smallest displacement type too. */
2044static void
2045optimize_disp ()
2046{
2047 int op;
3e73aa7c 2048
29b0f896
AM		 2049 for (op = i.operands; --op >= 0;)
2050 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 2051 {
29b0f896
AM		 2052 offsetT disp = i.op[op].disps->X_add_number;
2053
2054 if (i.types[op] & Disp16)
252b5132 2055 {
29b0f896
AM		 2056 /* We know this operand is at most 16 bits, so
2057 convert to a signed 16 bit number before trying
2058 to see whether it will fit in an even smaller
2059 size. */
2060
2061 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 2062 }
29b0f896 2063 else if (i.types[op] & Disp32)
252b5132 2064 {
29b0f896
AM		 2065 /* We know this operand is at most 32 bits, so convert to a
2066 signed 32 bit number before trying to see whether it will
2067 fit in an even smaller size. */
2068 disp &= (((offsetT) 2 << 31) - 1);
2069 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 2070 }
29b0f896 2071 if (flag_code == CODE_64BIT)
252b5132 2072 {
29b0f896
AM		 2073 if (fits_in_signed_long (disp))
2074 i.types[op] |= Disp32S;
2075 if (fits_in_unsigned_long (disp))
2076 i.types[op] |= Disp32;
252b5132 2077 }
29b0f896
AM		 2078 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2079 && fits_in_signed_byte (disp))
2080 i.types[op] |= Disp8;
252b5132 2081 }
29b0f896
AM		 2082}
2083
2084static int
2085match_template ()
2086{
2087 /* Points to template once we've found it. */
2088 const template *t;
2089 unsigned int overlap0, overlap1, overlap2;
2090 unsigned int found_reverse_match;
2091 int suffix_check;
2092
2093#define MATCH(overlap, given, template) \
2094 ((overlap & ~JumpAbsolute) \
2095 && (((given) & (BaseIndex | JumpAbsolute)) \
2096 == ((overlap) & (BaseIndex | JumpAbsolute))))
2097
2098 /* If given types r0 and r1 are registers they must be of the same type
2099 unless the expected operand type register overlap is null.
2100 Note that Acc in a template matches every size of reg. */
2101#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2102 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2103 || ((g0) & Reg) == ((g1) & Reg) \
2104 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2105
2106 overlap0 = 0;
2107 overlap1 = 0;
2108 overlap2 = 0;
2109 found_reverse_match = 0;
2110 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2111 ? No_bSuf
2112 : (i.suffix == WORD_MNEM_SUFFIX
2113 ? No_wSuf
2114 : (i.suffix == SHORT_MNEM_SUFFIX
2115 ? No_sSuf
2116 : (i.suffix == LONG_MNEM_SUFFIX
2117 ? No_lSuf
2118 : (i.suffix == QWORD_MNEM_SUFFIX
2119 ? No_qSuf
2120 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2121 ? No_xSuf : 0))))));
2122
20f0a1fc
NC		 2123 t = current_templates->start;
2124 if (i.suffix == QWORD_MNEM_SUFFIX
2125 && flag_code != CODE_64BIT
9306ca4a
JB		 2126 && (intel_syntax
2127 ? !(t->opcode_modifier & IgnoreSize)
2128 && !intel_float_operand (t->name)
2129 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2130 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2131 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2132 && (t->base_opcode != 0x0fc7
2133 || t->extension_opcode != 1 /* cmpxchg8b */))
2134 t = current_templates->end;
2135 for (; t < current_templates->end; t++)
29b0f896
AM		 2136 {
2137 /* Must have right number of operands. */
2138 if (i.operands != t->operands)
2139 continue;
2140
2141 /* Check the suffix, except for some instructions in intel mode. */
2142 if ((t->opcode_modifier & suffix_check)
2143 && !(intel_syntax
9306ca4a 2144 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2145 continue;
2146
2147 /* Do not verify operands when there are none. */
2148 else if (!t->operands)
2149 {
2150 if (t->cpu_flags & ~cpu_arch_flags)
2151 continue;
2152 /* We've found a match; break out of loop. */
2153 break;
2154 }
252b5132 2155
29b0f896
AM		 2156 overlap0 = i.types[0] & t->operand_types[0];
2157 switch (t->operands)
2158 {
2159 case 1:
2160 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2161 continue;
2162 break;
2163 case 2:
2164 case 3:
2165 overlap1 = i.types[1] & t->operand_types[1];
2166 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2167 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2168 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2169 t->operand_types[0],
2170 overlap1, i.types[1],
2171 t->operand_types[1]))
2172 {
2173 /* Check if other direction is valid ... */
2174 if ((t->opcode_modifier & (D | FloatD)) == 0)
2175 continue;
2176
2177 /* Try reversing direction of operands. */
2178 overlap0 = i.types[0] & t->operand_types[1];
2179 overlap1 = i.types[1] & t->operand_types[0];
2180 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2181 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2182 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2183 t->operand_types[1],
2184 overlap1, i.types[1],
2185 t->operand_types[0]))
2186 {
2187 /* Does not match either direction. */
2188 continue;
2189 }
2190 /* found_reverse_match holds which of D or FloatDR
2191 we've found. */
2192 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2193 }
2194 /* Found a forward 2 operand match here. */
2195 else if (t->operands == 3)
2196 {
2197 /* Here we make use of the fact that there are no
2198 reverse match 3 operand instructions, and all 3
2199 operand instructions only need to be checked for
2200 register consistency between operands 2 and 3. */
2201 overlap2 = i.types[2] & t->operand_types[2];
2202 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2203 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2204 t->operand_types[1],
2205 overlap2, i.types[2],
2206 t->operand_types[2]))
2207
2208 continue;
2209 }
2210 /* Found either forward/reverse 2 or 3 operand match here:
2211 slip through to break. */
2212 }
2213 if (t->cpu_flags & ~cpu_arch_flags)
2214 {
2215 found_reverse_match = 0;
2216 continue;
2217 }
2218 /* We've found a match; break out of loop. */
2219 break;
2220 }
2221
2222 if (t == current_templates->end)
2223 {
2224 /* We found no match. */
2225 as_bad (_("suffix or operands invalid for `%s'"),
2226 current_templates->start->name);
2227 return 0;
2228 }
252b5132 2229
29b0f896
AM		 2230 if (!quiet_warnings)
2231 {
2232 if (!intel_syntax
2233 && ((i.types[0] & JumpAbsolute)
2234 != (t->operand_types[0] & JumpAbsolute)))
2235 {
2236 as_warn (_("indirect %s without `*'"), t->name);
2237 }
2238
2239 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2240 == (IsPrefix | IgnoreSize))
2241 {
2242 /* Warn them that a data or address size prefix doesn't
2243 affect assembly of the next line of code. */
2244 as_warn (_("stand-alone `%s' prefix"), t->name);
2245 }
2246 }
2247
2248 /* Copy the template we found. */
2249 i.tm = *t;
2250 if (found_reverse_match)
2251 {
2252 /* If we found a reverse match we must alter the opcode
2253 direction bit. found_reverse_match holds bits to change
2254 (different for int & float insns). */
2255
2256 i.tm.base_opcode ^= found_reverse_match;
2257
2258 i.tm.operand_types[0] = t->operand_types[1];
2259 i.tm.operand_types[1] = t->operand_types[0];
2260 }
2261
2262 return 1;
2263}
2264
2265static int
2266check_string ()
2267{
2268 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2269 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2270 {
2271 if (i.seg[0] != NULL && i.seg[0] != &es)
2272 {
2273 as_bad (_("`%s' operand %d must use `%%es' segment"),
2274 i.tm.name,
2275 mem_op + 1);
2276 return 0;
2277 }
2278 /* There's only ever one segment override allowed per instruction.
2279 This instruction possibly has a legal segment override on the
2280 second operand, so copy the segment to where non-string
2281 instructions store it, allowing common code. */
2282 i.seg[0] = i.seg[1];
2283 }
2284 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2285 {
2286 if (i.seg[1] != NULL && i.seg[1] != &es)
2287 {
2288 as_bad (_("`%s' operand %d must use `%%es' segment"),
2289 i.tm.name,
2290 mem_op + 2);
2291 return 0;
2292 }
2293 }
2294 return 1;
2295}
2296
2297static int
543613e9 2298process_suffix (void)
29b0f896
AM		 2299{
2300 /* If matched instruction specifies an explicit instruction mnemonic
2301 suffix, use it. */
2302 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2303 {
2304 if (i.tm.opcode_modifier & Size16)
2305 i.suffix = WORD_MNEM_SUFFIX;
2306 else if (i.tm.opcode_modifier & Size64)
2307 i.suffix = QWORD_MNEM_SUFFIX;
2308 else
2309 i.suffix = LONG_MNEM_SUFFIX;
2310 }
2311 else if (i.reg_operands)
2312 {
2313 /* If there's no instruction mnemonic suffix we try to invent one
2314 based on register operands. */
2315 if (!i.suffix)
2316 {
2317 /* We take i.suffix from the last register operand specified,
2318 Destination register type is more significant than source
2319 register type. */
2320 int op;
543613e9 2321
29b0f896
AM		 2322 for (op = i.operands; --op >= 0;)
2323 if ((i.types[op] & Reg)
2324 && !(i.tm.operand_types[op] & InOutPortReg))
2325 {
2326 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2327 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2328 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2329 LONG_MNEM_SUFFIX);
2330 break;
2331 }
2332 }
2333 else if (i.suffix == BYTE_MNEM_SUFFIX)
2334 {
2335 if (!check_byte_reg ())
2336 return 0;
2337 }
2338 else if (i.suffix == LONG_MNEM_SUFFIX)
2339 {
2340 if (!check_long_reg ())
2341 return 0;
2342 }
2343 else if (i.suffix == QWORD_MNEM_SUFFIX)
2344 {
2345 if (!check_qword_reg ())
2346 return 0;
2347 }
2348 else if (i.suffix == WORD_MNEM_SUFFIX)
2349 {
2350 if (!check_word_reg ())
2351 return 0;
2352 }
2353 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2354 /* Do nothing if the instruction is going to ignore the prefix. */
2355 ;
2356 else
2357 abort ();
2358 }
9306ca4a
JB		 2359 else if ((i.tm.opcode_modifier & DefaultSize)
2360 && !i.suffix
2361 /* exclude fldenv/frstor/fsave/fstenv */
2362 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2363 {
2364 i.suffix = stackop_size;
2365 }
9306ca4a
JB		 2366 else if (intel_syntax
2367 && !i.suffix
2368 && ((i.tm.operand_types[0] & JumpAbsolute)
2369 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2370 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2371 && i.tm.extension_opcode <= 3)))
2372 {
2373 switch (flag_code)
2374 {
2375 case CODE_64BIT:
2376 if (!(i.tm.opcode_modifier & No_qSuf))
2377 {
2378 i.suffix = QWORD_MNEM_SUFFIX;
2379 break;
2380 }
2381 case CODE_32BIT:
2382 if (!(i.tm.opcode_modifier & No_lSuf))
2383 i.suffix = LONG_MNEM_SUFFIX;
2384 break;
2385 case CODE_16BIT:
2386 if (!(i.tm.opcode_modifier & No_wSuf))
2387 i.suffix = WORD_MNEM_SUFFIX;
2388 break;
2389 }
2390 }
252b5132 2391
9306ca4a 2392 if (!i.suffix)
29b0f896 2393 {
9306ca4a
JB		 2394 if (!intel_syntax)
2395 {
2396 if (i.tm.opcode_modifier & W)
2397 {
2398 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2399 return 0;
2400 }
2401 }
2402 else
2403 {
2404 unsigned int suffixes = ~i.tm.opcode_modifier
2405 & (No_bSuf
2406 | No_wSuf
2407 | No_lSuf
2408 | No_sSuf
2409 | No_xSuf
2410 | No_qSuf);
2411
2412 if ((i.tm.opcode_modifier & W)
2413 || ((suffixes & (suffixes - 1))
2414 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2415 {
2416 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2417 return 0;
2418 }
2419 }
29b0f896 2420 }
252b5132 2421
9306ca4a
JB		 2422 /* Change the opcode based on the operand size given by i.suffix;
2423 We don't need to change things for byte insns. */
2424
29b0f896
AM		 2425 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2426 {
2427 /* It's not a byte, select word/dword operation. */
2428 if (i.tm.opcode_modifier & W)
2429 {
2430 if (i.tm.opcode_modifier & ShortForm)
2431 i.tm.base_opcode |= 8;
2432 else
2433 i.tm.base_opcode |= 1;
2434 }
0f3f3d8b 2435
29b0f896
AM		 2436 /* Now select between word & dword operations via the operand
2437 size prefix, except for instructions that will ignore this
2438 prefix anyway. */
2439 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2440 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2441 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2442 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2443 || (flag_code == CODE_64BIT
2444 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2445 {
2446 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2447
29b0f896
AM		 2448 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2449 prefix = ADDR_PREFIX_OPCODE;
252b5132 2450
29b0f896
AM		 2451 if (!add_prefix (prefix))
2452 return 0;
24eab124 2453 }
252b5132 2454
29b0f896
AM		 2455 /* Set mode64 for an operand. */
2456 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2457 && flag_code == CODE_64BIT
29b0f896 2458 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2459 i.rex |= REX_MODE64;
3e73aa7c 2460
29b0f896
AM		 2461 /* Size floating point instruction. */
2462 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2463 if (i.tm.opcode_modifier & FloatMF)
2464 i.tm.base_opcode ^= 4;
29b0f896 2465 }
7ecd2f8b 2466
29b0f896
AM		 2467 return 1;
2468}
3e73aa7c 2469
29b0f896 2470static int
543613e9 2471check_byte_reg (void)
29b0f896
AM		 2472{
2473 int op;
543613e9 2474
29b0f896
AM		 2475 for (op = i.operands; --op >= 0;)
2476 {
2477 /* If this is an eight bit register, it's OK. If it's the 16 or
2478 32 bit version of an eight bit register, we will just use the
2479 low portion, and that's OK too. */
2480 if (i.types[op] & Reg8)
2481 continue;
2482
2483 /* movzx and movsx should not generate this warning. */
2484 if (intel_syntax
2485 && (i.tm.base_opcode == 0xfb7
2486 || i.tm.base_opcode == 0xfb6
2487 || i.tm.base_opcode == 0x63
2488 || i.tm.base_opcode == 0xfbe
2489 || i.tm.base_opcode == 0xfbf))
2490 continue;
2491
65ec77d2 2492 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2493 {
2494 /* Prohibit these changes in the 64bit mode, since the
2495 lowering is more complicated. */
2496 if (flag_code == CODE_64BIT
2497 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2498 {
0f3f3d8b 2499 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2500 i.op[op].regs->reg_name,
2501 i.suffix);
2502 return 0;
2503 }
2504#if REGISTER_WARNINGS
2505 if (!quiet_warnings
2506 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2507 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2508 (i.op[op].regs + (i.types[op] & Reg16
2509 ? REGNAM_AL - REGNAM_AX
2510 : REGNAM_AL - REGNAM_EAX))->reg_name,
2511 i.op[op].regs->reg_name,
2512 i.suffix);
2513#endif
2514 continue;
2515 }
2516 /* Any other register is bad. */
2517 if (i.types[op] & (Reg | RegMMX | RegXMM
2518 | SReg2 | SReg3
2519 | Control | Debug | Test
2520 | FloatReg | FloatAcc))
2521 {
2522 as_bad (_("`%%%s' not allowed with `%s%c'"),
2523 i.op[op].regs->reg_name,
2524 i.tm.name,
2525 i.suffix);
2526 return 0;
2527 }
2528 }
2529 return 1;
2530}
2531
2532static int
2533check_long_reg ()
2534{
2535 int op;
2536
2537 for (op = i.operands; --op >= 0;)
2538 /* Reject eight bit registers, except where the template requires
2539 them. (eg. movzb) */
2540 if ((i.types[op] & Reg8) != 0
2541 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2542 {
2543 as_bad (_("`%%%s' not allowed with `%s%c'"),
2544 i.op[op].regs->reg_name,
2545 i.tm.name,
2546 i.suffix);
2547 return 0;
2548 }
2549 /* Warn if the e prefix on a general reg is missing. */
2550 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2551 && (i.types[op] & Reg16) != 0
2552 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2553 {
2554 /* Prohibit these changes in the 64bit mode, since the
2555 lowering is more complicated. */
2556 if (flag_code == CODE_64BIT)
252b5132 2557 {
0f3f3d8b 2558 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2559 i.op[op].regs->reg_name,
2560 i.suffix);
2561 return 0;
252b5132 2562 }
29b0f896
AM		 2563#if REGISTER_WARNINGS
2564 else
2565 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2566 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2567 i.op[op].regs->reg_name,
2568 i.suffix);
2569#endif
252b5132 2570 }
29b0f896
AM		 2571 /* Warn if the r prefix on a general reg is missing. */
2572 else if ((i.types[op] & Reg64) != 0
2573 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2574 {
0f3f3d8b 2575 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2576 i.op[op].regs->reg_name,
2577 i.suffix);
2578 return 0;
2579 }
2580 return 1;
2581}
252b5132 2582
29b0f896
AM		 2583static int
2584check_qword_reg ()
2585{
2586 int op;
252b5132 2587
29b0f896
AM		 2588 for (op = i.operands; --op >= 0; )
2589 /* Reject eight bit registers, except where the template requires
2590 them. (eg. movzb) */
2591 if ((i.types[op] & Reg8) != 0
2592 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2593 {
2594 as_bad (_("`%%%s' not allowed with `%s%c'"),
2595 i.op[op].regs->reg_name,
2596 i.tm.name,
2597 i.suffix);
2598 return 0;
2599 }
2600 /* Warn if the e prefix on a general reg is missing. */
2601 else if (((i.types[op] & Reg16) != 0
2602 || (i.types[op] & Reg32) != 0)
2603 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2604 {
2605 /* Prohibit these changes in the 64bit mode, since the
2606 lowering is more complicated. */
0f3f3d8b 2607 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2608 i.op[op].regs->reg_name,
2609 i.suffix);
2610 return 0;
252b5132 2611 }
29b0f896
AM		 2612 return 1;
2613}
252b5132 2614
29b0f896
AM		 2615static int
2616check_word_reg ()
2617{
2618 int op;
2619 for (op = i.operands; --op >= 0;)
2620 /* Reject eight bit registers, except where the template requires
2621 them. (eg. movzb) */
2622 if ((i.types[op] & Reg8) != 0
2623 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2624 {
2625 as_bad (_("`%%%s' not allowed with `%s%c'"),
2626 i.op[op].regs->reg_name,
2627 i.tm.name,
2628 i.suffix);
2629 return 0;
2630 }
2631 /* Warn if the e prefix on a general reg is present. */
2632 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2633 && (i.types[op] & Reg32) != 0
2634 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2635 {
29b0f896
AM		 2636 /* Prohibit these changes in the 64bit mode, since the
2637 lowering is more complicated. */
2638 if (flag_code == CODE_64BIT)
252b5132 2639 {
0f3f3d8b 2640 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2641 i.op[op].regs->reg_name,
2642 i.suffix);
2643 return 0;
252b5132 2644 }
29b0f896
AM		 2645 else
2646#if REGISTER_WARNINGS
2647 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2648 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2649 i.op[op].regs->reg_name,
2650 i.suffix);
2651#endif
2652 }
2653 return 1;
2654}
252b5132 2655
29b0f896
AM		 2656static int
2657finalize_imm ()
2658{
2659 unsigned int overlap0, overlap1, overlap2;
2660
2661 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2662 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2663 && overlap0 != Imm8 && overlap0 != Imm8S
2664 && overlap0 != Imm16 && overlap0 != Imm32S
2665 && overlap0 != Imm32 && overlap0 != Imm64)
2666 {
2667 if (i.suffix)
2668 {
2669 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2670 ? Imm8 | Imm8S
2671 : (i.suffix == WORD_MNEM_SUFFIX
2672 ? Imm16
2673 : (i.suffix == QWORD_MNEM_SUFFIX
2674 ? Imm64 | Imm32S
2675 : Imm32)));
2676 }
2677 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2678 || overlap0 == (Imm16 | Imm32)
2679 || overlap0 == (Imm16 | Imm32S))
2680 {
2681 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2682 ? Imm16 : Imm32S);
2683 }
2684 if (overlap0 != Imm8 && overlap0 != Imm8S
2685 && overlap0 != Imm16 && overlap0 != Imm32S
2686 && overlap0 != Imm32 && overlap0 != Imm64)
2687 {
2688 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2689 return 0;
2690 }
2691 }
2692 i.types[0] = overlap0;
2693
2694 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2695 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2696 && overlap1 != Imm8 && overlap1 != Imm8S
2697 && overlap1 != Imm16 && overlap1 != Imm32S
2698 && overlap1 != Imm32 && overlap1 != Imm64)
2699 {
2700 if (i.suffix)
2701 {
2702 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2703 ? Imm8 | Imm8S
2704 : (i.suffix == WORD_MNEM_SUFFIX
2705 ? Imm16
2706 : (i.suffix == QWORD_MNEM_SUFFIX
2707 ? Imm64 | Imm32S
2708 : Imm32)));
2709 }
2710 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2711 || overlap1 == (Imm16 | Imm32)
2712 || overlap1 == (Imm16 | Imm32S))
2713 {
2714 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2715 ? Imm16 : Imm32S);
2716 }
2717 if (overlap1 != Imm8 && overlap1 != Imm8S
2718 && overlap1 != Imm16 && overlap1 != Imm32S
2719 && overlap1 != Imm32 && overlap1 != Imm64)
2720 {
2721 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2722 return 0;
2723 }
2724 }
2725 i.types[1] = overlap1;
2726
2727 overlap2 = i.types[2] & i.tm.operand_types[2];
2728 assert ((overlap2 & Imm) == 0);
2729 i.types[2] = overlap2;
2730
2731 return 1;
2732}
2733
2734static int
2735process_operands ()
2736{
2737 /* Default segment register this instruction will use for memory
2738 accesses. 0 means unknown. This is only for optimizing out
2739 unnecessary segment overrides. */
2740 const seg_entry *default_seg = 0;
2741
2742 /* The imul $imm, %reg instruction is converted into
2743 imul $imm, %reg, %reg, and the clr %reg instruction
2744 is converted into xor %reg, %reg. */
2745 if (i.tm.opcode_modifier & regKludge)
2746 {
2747 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2748 /* Pretend we saw the extra register operand. */
2749 assert (i.op[first_reg_op + 1].regs == 0);
2750 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2751 i.types[first_reg_op + 1] = i.types[first_reg_op];
2752 i.reg_operands = 2;
2753 }
2754
2755 if (i.tm.opcode_modifier & ShortForm)
2756 {
2757 /* The register or float register operand is in operand 0 or 1. */
2758 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2759 /* Register goes in low 3 bits of opcode. */
2760 i.tm.base_opcode |= i.op[op].regs->reg_num;
2761 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2762 i.rex |= REX_EXTZ;
2763 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2764 {
2765 /* Warn about some common errors, but press on regardless.
2766 The first case can be generated by gcc (<= 2.8.1). */
2767 if (i.operands == 2)
2768 {
2769 /* Reversed arguments on faddp, fsubp, etc. */
2770 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2771 i.op[1].regs->reg_name,
2772 i.op[0].regs->reg_name);
2773 }
2774 else
2775 {
2776 /* Extraneous `l' suffix on fp insn. */
2777 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2778 i.op[0].regs->reg_name);
2779 }
2780 }
2781 }
2782 else if (i.tm.opcode_modifier & Modrm)
2783 {
2784 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2785 must be put into the modrm byte). Now, we make the modrm and
2786 index base bytes based on all the info we've collected. */
29b0f896
AM		 2787
2788 default_seg = build_modrm_byte ();
2789 }
2790 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2791 {
2792 if (i.tm.base_opcode == POP_SEG_SHORT
2793 && i.op[0].regs->reg_num == 1)
2794 {
2795 as_bad (_("you can't `pop %%cs'"));
2796 return 0;
2797 }
2798 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2799 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2800 i.rex |= REX_EXTZ;
2801 }
2802 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2803 {
2804 default_seg = &ds;
2805 }
2806 else if ((i.tm.opcode_modifier & IsString) != 0)
2807 {
2808 /* For the string instructions that allow a segment override
2809 on one of their operands, the default segment is ds. */
2810 default_seg = &ds;
2811 }
2812
52271982
AM		 2813 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2814 as_warn (_("segment override on `lea' is ineffectual"));
2815
2816 /* If a segment was explicitly specified, and the specified segment
2817 is not the default, use an opcode prefix to select it. If we
2818 never figured out what the default segment is, then default_seg
2819 will be zero at this point, and the specified segment prefix will
2820 always be used. */
29b0f896
AM		 2821 if ((i.seg[0]) && (i.seg[0] != default_seg))
2822 {
2823 if (!add_prefix (i.seg[0]->seg_prefix))
2824 return 0;
2825 }
2826 return 1;
2827}
2828
2829static const seg_entry *
2830build_modrm_byte ()
2831{
2832 const seg_entry *default_seg = 0;
2833
2834 /* i.reg_operands MUST be the number of real register operands;
2835 implicit registers do not count. */
2836 if (i.reg_operands == 2)
2837 {
2838 unsigned int source, dest;
2839 source = ((i.types[0]
2840 & (Reg | RegMMX | RegXMM
2841 | SReg2 | SReg3
2842 | Control | Debug | Test))
2843 ? 0 : 1);
2844 dest = source + 1;
2845
2846 i.rm.mode = 3;
2847 /* One of the register operands will be encoded in the i.tm.reg
2848 field, the other in the combined i.tm.mode and i.tm.regmem
2849 fields. If no form of this instruction supports a memory
2850 destination operand, then we assume the source operand may
2851 sometimes be a memory operand and so we need to store the
2852 destination in the i.rm.reg field. */
2853 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2854 {
2855 i.rm.reg = i.op[dest].regs->reg_num;
2856 i.rm.regmem = i.op[source].regs->reg_num;
2857 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2858 i.rex |= REX_EXTX;
2859 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2860 i.rex |= REX_EXTZ;
2861 }
2862 else
2863 {
2864 i.rm.reg = i.op[source].regs->reg_num;
2865 i.rm.regmem = i.op[dest].regs->reg_num;
2866 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2867 i.rex |= REX_EXTZ;
2868 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2869 i.rex |= REX_EXTX;
2870 }
c4a530c5
JB		 2871 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2872 {
2873 if (!((i.types[0] | i.types[1]) & Control))
2874 abort ();
2875 i.rex &= ~(REX_EXTX | REX_EXTZ);
2876 add_prefix (LOCK_PREFIX_OPCODE);
2877 }
29b0f896
AM		 2878 }
2879 else
2880 { /* If it's not 2 reg operands... */
2881 if (i.mem_operands)
2882 {
2883 unsigned int fake_zero_displacement = 0;
2884 unsigned int op = ((i.types[0] & AnyMem)
2885 ? 0
2886 : (i.types[1] & AnyMem) ? 1 : 2);
2887
2888 default_seg = &ds;
2889
2890 if (i.base_reg == 0)
2891 {
2892 i.rm.mode = 0;
2893 if (!i.disp_operands)
2894 fake_zero_displacement = 1;
2895 if (i.index_reg == 0)
2896 {
2897 /* Operand is just <disp> */
20f0a1fc 2898 if (flag_code == CODE_64BIT)
29b0f896
AM		 2899 {
2900 /* 64bit mode overwrites the 32bit absolute
2901 addressing by RIP relative addressing and
2902 absolute addressing is encoded by one of the
2903 redundant SIB forms. */
2904 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2905 i.sib.base = NO_BASE_REGISTER;
2906 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 2907 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2908 }
2909 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2910 {
2911 i.rm.regmem = NO_BASE_REGISTER_16;
2912 i.types[op] = Disp16;
2913 }
2914 else
2915 {
2916 i.rm.regmem = NO_BASE_REGISTER;
2917 i.types[op] = Disp32;
29b0f896
AM		 2918 }
2919 }
2920 else /* !i.base_reg && i.index_reg */
2921 {
2922 i.sib.index = i.index_reg->reg_num;
2923 i.sib.base = NO_BASE_REGISTER;
2924 i.sib.scale = i.log2_scale_factor;
2925 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2926 i.types[op] &= ~Disp;
2927 if (flag_code != CODE_64BIT)
2928 i.types[op] |= Disp32; /* Must be 32 bit */
2929 else
2930 i.types[op] |= Disp32S;
2931 if ((i.index_reg->reg_flags & RegRex) != 0)
2932 i.rex |= REX_EXTY;
2933 }
2934 }
2935 /* RIP addressing for 64bit mode. */
2936 else if (i.base_reg->reg_type == BaseIndex)
2937 {
2938 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 2939 i.types[op] &= ~ Disp;
29b0f896
AM		 2940 i.types[op] |= Disp32S;
2941 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 2942 if (! i.disp_operands)
2943 fake_zero_displacement = 1;
29b0f896
AM		 2944 }
2945 else if (i.base_reg->reg_type & Reg16)
2946 {
2947 switch (i.base_reg->reg_num)
2948 {
2949 case 3: /* (%bx) */
2950 if (i.index_reg == 0)
2951 i.rm.regmem = 7;
2952 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2953 i.rm.regmem = i.index_reg->reg_num - 6;
2954 break;
2955 case 5: /* (%bp) */
2956 default_seg = &ss;
2957 if (i.index_reg == 0)
2958 {
2959 i.rm.regmem = 6;
2960 if ((i.types[op] & Disp) == 0)
2961 {
2962 /* fake (%bp) into 0(%bp) */
2963 i.types[op] |= Disp8;
252b5132 2964 fake_zero_displacement = 1;
29b0f896
AM		 2965 }
2966 }
2967 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2968 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2969 break;
2970 default: /* (%si) -> 4 or (%di) -> 5 */
2971 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2972 }
2973 i.rm.mode = mode_from_disp_size (i.types[op]);
2974 }
2975 else /* i.base_reg and 32/64 bit mode */
2976 {
2977 if (flag_code == CODE_64BIT
2978 && (i.types[op] & Disp))
20f0a1fc
NC		 2979 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
2980
29b0f896
AM		 2981 i.rm.regmem = i.base_reg->reg_num;
2982 if ((i.base_reg->reg_flags & RegRex) != 0)
2983 i.rex |= REX_EXTZ;
2984 i.sib.base = i.base_reg->reg_num;
2985 /* x86-64 ignores REX prefix bit here to avoid decoder
2986 complications. */
2987 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2988 {
2989 default_seg = &ss;
2990 if (i.disp_operands == 0)
2991 {
2992 fake_zero_displacement = 1;
2993 i.types[op] |= Disp8;
2994 }
2995 }
2996 else if (i.base_reg->reg_num == ESP_REG_NUM)
2997 {
2998 default_seg = &ss;
2999 }
3000 i.sib.scale = i.log2_scale_factor;
3001 if (i.index_reg == 0)
3002 {
3003 /* <disp>(%esp) becomes two byte modrm with no index
3004 register. We've already stored the code for esp
3005 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3006 Any base register besides %esp will not use the
3007 extra modrm byte. */
3008 i.sib.index = NO_INDEX_REGISTER;
3009#if !SCALE1_WHEN_NO_INDEX
3010 /* Another case where we force the second modrm byte. */
3011 if (i.log2_scale_factor)
3012 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3013#endif
29b0f896
AM		 3014 }
3015 else
3016 {
3017 i.sib.index = i.index_reg->reg_num;
3018 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3019 if ((i.index_reg->reg_flags & RegRex) != 0)
3020 i.rex |= REX_EXTY;
3021 }
3022 i.rm.mode = mode_from_disp_size (i.types[op]);
3023 }
252b5132 3024
29b0f896
AM		 3025 if (fake_zero_displacement)
3026 {
3027 /* Fakes a zero displacement assuming that i.types[op]
3028 holds the correct displacement size. */
3029 expressionS *exp;
3030
3031 assert (i.op[op].disps == 0);
3032 exp = &disp_expressions[i.disp_operands++];
3033 i.op[op].disps = exp;
3034 exp->X_op = O_constant;
3035 exp->X_add_number = 0;
3036 exp->X_add_symbol = (symbolS *) 0;
3037 exp->X_op_symbol = (symbolS *) 0;
3038 }
3039 }
252b5132 3040
29b0f896
AM		 3041 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3042 (if any) based on i.tm.extension_opcode. Again, we must be
3043 careful to make sure that segment/control/debug/test/MMX
3044 registers are coded into the i.rm.reg field. */
3045 if (i.reg_operands)
3046 {
3047 unsigned int op =
3048 ((i.types[0]
3049 & (Reg | RegMMX | RegXMM
3050 | SReg2 | SReg3
3051 | Control | Debug | Test))
3052 ? 0
3053 : ((i.types[1]
3054 & (Reg | RegMMX | RegXMM
3055 | SReg2 | SReg3
3056 | Control | Debug | Test))
3057 ? 1
3058 : 2));
3059 /* If there is an extension opcode to put here, the register
3060 number must be put into the regmem field. */
3061 if (i.tm.extension_opcode != None)
3062 {
3063 i.rm.regmem = i.op[op].regs->reg_num;
3064 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3065 i.rex |= REX_EXTZ;
3066 }
3067 else
3068 {
3069 i.rm.reg = i.op[op].regs->reg_num;
3070 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3071 i.rex |= REX_EXTX;
3072 }
252b5132 3073
29b0f896
AM		 3074 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3075 must set it to 3 to indicate this is a register operand
3076 in the regmem field. */
3077 if (!i.mem_operands)
3078 i.rm.mode = 3;
3079 }
252b5132 3080
29b0f896
AM		 3081 /* Fill in i.rm.reg field with extension opcode (if any). */
3082 if (i.tm.extension_opcode != None)
3083 i.rm.reg = i.tm.extension_opcode;
3084 }
3085 return default_seg;
3086}
252b5132 3087
29b0f896
AM		 3088static void
3089output_branch ()
3090{
3091 char *p;
3092 int code16;
3093 int prefix;
3094 relax_substateT subtype;
3095 symbolS *sym;
3096 offsetT off;
3097
3098 code16 = 0;
3099 if (flag_code == CODE_16BIT)
3100 code16 = CODE16;
3101
3102 prefix = 0;
3103 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3104 {
29b0f896
AM		 3105 prefix = 1;
3106 i.prefixes -= 1;
3107 code16 ^= CODE16;
252b5132 3108 }
29b0f896
AM		 3109 /* Pentium4 branch hints. */
3110 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3111 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3112 {
29b0f896
AM		 3113 prefix++;
3114 i.prefixes--;
3115 }
3116 if (i.prefix[REX_PREFIX] != 0)
3117 {
3118 prefix++;
3119 i.prefixes--;
2f66722d
AM		 3120 }
3121
29b0f896
AM		 3122 if (i.prefixes != 0 && !intel_syntax)
3123 as_warn (_("skipping prefixes on this instruction"));
3124
3125 /* It's always a symbol; End frag & setup for relax.
3126 Make sure there is enough room in this frag for the largest
3127 instruction we may generate in md_convert_frag. This is 2
3128 bytes for the opcode and room for the prefix and largest
3129 displacement. */
3130 frag_grow (prefix + 2 + 4);
3131 /* Prefix and 1 opcode byte go in fr_fix. */
3132 p = frag_more (prefix + 1);
3133 if (i.prefix[DATA_PREFIX] != 0)
3134 *p++ = DATA_PREFIX_OPCODE;
3135 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3136 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3137 *p++ = i.prefix[SEG_PREFIX];
3138 if (i.prefix[REX_PREFIX] != 0)
3139 *p++ = i.prefix[REX_PREFIX];
3140 *p = i.tm.base_opcode;
3141
3142 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3143 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3144 else if ((cpu_arch_flags & Cpu386) != 0)
3145 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3146 else
3147 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3148 subtype |= code16;
3e73aa7c 3149
29b0f896
AM		 3150 sym = i.op[0].disps->X_add_symbol;
3151 off = i.op[0].disps->X_add_number;
3e73aa7c 3152
29b0f896
AM		 3153 if (i.op[0].disps->X_op != O_constant
3154 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3155 {
29b0f896
AM		 3156 /* Handle complex expressions. */
3157 sym = make_expr_symbol (i.op[0].disps);
3158 off = 0;
3159 }
3e73aa7c 3160
29b0f896
AM		 3161 /* 1 possible extra opcode + 4 byte displacement go in var part.
3162 Pass reloc in fr_var. */
3163 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3164}
3e73aa7c 3165
29b0f896
AM		 3166static void
3167output_jump ()
3168{
3169 char *p;
3170 int size;
3e02c1cc 3171 fixS *fixP;
29b0f896
AM		 3172
3173 if (i.tm.opcode_modifier & JumpByte)
3174 {
3175 /* This is a loop or jecxz type instruction. */
3176 size = 1;
3177 if (i.prefix[ADDR_PREFIX] != 0)
3178 {
3179 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3180 i.prefixes -= 1;
3181 }
3182 /* Pentium4 branch hints. */
3183 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3184 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3185 {
3186 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3187 i.prefixes--;
3e73aa7c
JH		 3188 }
3189 }
29b0f896
AM		 3190 else
3191 {
3192 int code16;
3e73aa7c 3193
29b0f896
AM		 3194 code16 = 0;
3195 if (flag_code == CODE_16BIT)
3196 code16 = CODE16;
3e73aa7c 3197
29b0f896
AM		 3198 if (i.prefix[DATA_PREFIX] != 0)
3199 {
3200 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3201 i.prefixes -= 1;
3202 code16 ^= CODE16;
3203 }
252b5132 3204
29b0f896
AM		 3205 size = 4;
3206 if (code16)
3207 size = 2;
3208 }
9fcc94b6 3209
29b0f896
AM		 3210 if (i.prefix[REX_PREFIX] != 0)
3211 {
3212 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3213 i.prefixes -= 1;
3214 }
252b5132 3215
29b0f896
AM		 3216 if (i.prefixes != 0 && !intel_syntax)
3217 as_warn (_("skipping prefixes on this instruction"));
e0890092 3218
29b0f896
AM		 3219 p = frag_more (1 + size);
3220 *p++ = i.tm.base_opcode;
e0890092 3221
3e02c1cc
AM		 3222 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3223 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3224
3225 /* All jumps handled here are signed, but don't use a signed limit
3226 check for 32 and 16 bit jumps as we want to allow wrap around at
3227 4G and 64k respectively. */
3228 if (size == 1)
3229 fixP->fx_signed = 1;
29b0f896 3230}
e0890092 3231
29b0f896
AM		 3232static void
3233output_interseg_jump ()
3234{
3235 char *p;
3236 int size;
3237 int prefix;
3238 int code16;
252b5132 3239
29b0f896
AM		 3240 code16 = 0;
3241 if (flag_code == CODE_16BIT)
3242 code16 = CODE16;
a217f122 3243
29b0f896
AM		 3244 prefix = 0;
3245 if (i.prefix[DATA_PREFIX] != 0)
3246 {
3247 prefix = 1;
3248 i.prefixes -= 1;
3249 code16 ^= CODE16;
3250 }
3251 if (i.prefix[REX_PREFIX] != 0)
3252 {
3253 prefix++;
3254 i.prefixes -= 1;
3255 }
252b5132 3256
29b0f896
AM		 3257 size = 4;
3258 if (code16)
3259 size = 2;
252b5132 3260
29b0f896
AM		 3261 if (i.prefixes != 0 && !intel_syntax)
3262 as_warn (_("skipping prefixes on this instruction"));
252b5132 3263
29b0f896
AM		 3264 /* 1 opcode; 2 segment; offset */
3265 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3266
29b0f896
AM		 3267 if (i.prefix[DATA_PREFIX] != 0)
3268 *p++ = DATA_PREFIX_OPCODE;
252b5132 3269
29b0f896
AM		 3270 if (i.prefix[REX_PREFIX] != 0)
3271 *p++ = i.prefix[REX_PREFIX];
252b5132 3272
29b0f896
AM		 3273 *p++ = i.tm.base_opcode;
3274 if (i.op[1].imms->X_op == O_constant)
3275 {
3276 offsetT n = i.op[1].imms->X_add_number;
252b5132 3277
29b0f896
AM		 3278 if (size == 2
3279 && !fits_in_unsigned_word (n)
3280 && !fits_in_signed_word (n))
3281 {
3282 as_bad (_("16-bit jump out of range"));
3283 return;
3284 }
3285 md_number_to_chars (p, n, size);
3286 }
3287 else
3288 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3289 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3290 if (i.op[0].imms->X_op != O_constant)
3291 as_bad (_("can't handle non absolute segment in `%s'"),
3292 i.tm.name);
3293 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3294}
a217f122 3295
29b0f896
AM		 3296static void
3297output_insn ()
3298{
2bbd9c25
JJ		 3299 fragS *insn_start_frag;
3300 offsetT insn_start_off;
3301
29b0f896
AM		 3302 /* Tie dwarf2 debug info to the address at the start of the insn.
3303 We can't do this after the insn has been output as the current
3304 frag may have been closed off. eg. by frag_var. */
3305 dwarf2_emit_insn (0);
3306
2bbd9c25
JJ		 3307 insn_start_frag = frag_now;
3308 insn_start_off = frag_now_fix ();
3309
29b0f896
AM		 3310 /* Output jumps. */
3311 if (i.tm.opcode_modifier & Jump)
3312 output_branch ();
3313 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3314 output_jump ();
3315 else if (i.tm.opcode_modifier & JumpInterSegment)
3316 output_interseg_jump ();
3317 else
3318 {
3319 /* Output normal instructions here. */
3320 char *p;
3321 unsigned char *q;
252b5132 3322
0f10071e
ML		 3323 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
3324 have 3 bytes. We may use one more higher byte to specify a prefix
3325 the instruction requires. */
3326 if ((i.tm.cpu_flags & CpuPadLock) != 0
3327 && (i.tm.base_opcode & 0xff000000) != 0)
3328 {
3329 unsigned int prefix;
3330 prefix = (i.tm.base_opcode >> 24) & 0xff;
3331
3332 if (prefix != REPE_PREFIX_OPCODE
3333 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3334 add_prefix (prefix);
3335 }
3336 else
3337 if ((i.tm.cpu_flags & CpuPadLock) == 0
3338 && (i.tm.base_opcode & 0xff0000) != 0)
3339 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3340
29b0f896
AM		 3341 /* The prefix bytes. */
3342 for (q = i.prefix;
3343 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3344 q++)
3345 {
3346 if (*q)
3347 {
3348 p = frag_more (1);
3349 md_number_to_chars (p, (valueT) *q, 1);
3350 }
3351 }
252b5132 3352
29b0f896
AM		 3353 /* Now the opcode; be careful about word order here! */
3354 if (fits_in_unsigned_byte (i.tm.base_opcode))
3355 {
3356 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3357 }
3358 else
3359 {
0f10071e
ML		 3360 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3361 {
3362 p = frag_more (3);
3363 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3364 }
3365 else
3366 p = frag_more (2);
3367
29b0f896
AM		 3368 /* Put out high byte first: can't use md_number_to_chars! */
3369 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3370 *p = i.tm.base_opcode & 0xff;
3371 }
3e73aa7c 3372
29b0f896
AM		 3373 /* Now the modrm byte and sib byte (if present). */
3374 if (i.tm.opcode_modifier & Modrm)
3375 {
3376 p = frag_more (1);
3377 md_number_to_chars (p,
3378 (valueT) (i.rm.regmem << 0
3379 | i.rm.reg << 3
3380 | i.rm.mode << 6),
3381 1);
3382 /* If i.rm.regmem == ESP (4)
3383 && i.rm.mode != (Register mode)
3384 && not 16 bit
3385 ==> need second modrm byte. */
3386 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3387 && i.rm.mode != 3
3388 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3389 {
3390 p = frag_more (1);
3391 md_number_to_chars (p,
3392 (valueT) (i.sib.base << 0
3393 | i.sib.index << 3
3394 | i.sib.scale << 6),
3395 1);
3396 }
3397 }
3e73aa7c 3398
29b0f896 3399 if (i.disp_operands)
2bbd9c25 3400 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3401
29b0f896 3402 if (i.imm_operands)
2bbd9c25 3403 output_imm (insn_start_frag, insn_start_off);
29b0f896 3404 }
252b5132 3405
29b0f896
AM		 3406#ifdef DEBUG386
3407 if (flag_debug)
3408 {
3409 pi (line, &i);
3410 }
3411#endif /* DEBUG386 */
3412}
252b5132 3413
29b0f896 3414static void
2bbd9c25
JJ		 3415output_disp (insn_start_frag, insn_start_off)
3416 fragS *insn_start_frag;
3417 offsetT insn_start_off;
29b0f896
AM		 3418{
3419 char *p;
3420 unsigned int n;
252b5132 3421
29b0f896
AM		 3422 for (n = 0; n < i.operands; n++)
3423 {
3424 if (i.types[n] & Disp)
3425 {
3426 if (i.op[n].disps->X_op == O_constant)
3427 {
3428 int size;
3429 offsetT val;
252b5132 3430
29b0f896
AM		 3431 size = 4;
3432 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3433 {
3434 size = 2;
3435 if (i.types[n] & Disp8)
3436 size = 1;
3437 if (i.types[n] & Disp64)
3438 size = 8;
3439 }
3440 val = offset_in_range (i.op[n].disps->X_add_number,
3441 size);
3442 p = frag_more (size);
3443 md_number_to_chars (p, val, size);
3444 }
3445 else
3446 {
f86103b7 3447 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3448 int size = 4;
3449 int sign = 0;
3450 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3451
3452 /* The PC relative address is computed relative
3453 to the instruction boundary, so in case immediate
3454 fields follows, we need to adjust the value. */
3455 if (pcrel && i.imm_operands)
3456 {
3457 int imm_size = 4;
3458 unsigned int n1;
252b5132 3459
29b0f896
AM		 3460 for (n1 = 0; n1 < i.operands; n1++)
3461 if (i.types[n1] & Imm)
252b5132 3462 {
29b0f896 3463 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3464 {
29b0f896
AM		 3465 imm_size = 2;
3466 if (i.types[n1] & (Imm8 | Imm8S))
3467 imm_size = 1;
3468 if (i.types[n1] & Imm64)
3469 imm_size = 8;
252b5132 3470 }
29b0f896 3471 break;
252b5132 3472 }
29b0f896
AM		 3473 /* We should find the immediate. */
3474 if (n1 == i.operands)
3475 abort ();
3476 i.op[n].disps->X_add_number -= imm_size;
3477 }
520dc8e8 3478
29b0f896
AM		 3479 if (i.types[n] & Disp32S)
3480 sign = 1;
3e73aa7c 3481
29b0f896
AM		 3482 if (i.types[n] & (Disp16 | Disp64))
3483 {
3484 size = 2;
3485 if (i.types[n] & Disp64)
3486 size = 8;
3487 }
520dc8e8 3488
29b0f896 3489 p = frag_more (size);
2bbd9c25 3490 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
2bbd9c25
JJ		 3491 if (reloc_type == BFD_RELOC_32
3492 && GOT_symbol
3493 && GOT_symbol == i.op[n].disps->X_add_symbol
3494 && (i.op[n].disps->X_op == O_symbol
3495 || (i.op[n].disps->X_op == O_add
3496 && ((symbol_get_value_expression
3497 (i.op[n].disps->X_op_symbol)->X_op)
3498 == O_subtract))))
3499 {
3500 offsetT add;
3501
3502 if (insn_start_frag == frag_now)
3503 add = (p - frag_now->fr_literal) - insn_start_off;
3504 else
3505 {
3506 fragS *fr;
3507
3508 add = insn_start_frag->fr_fix - insn_start_off;
3509 for (fr = insn_start_frag->fr_next;
3510 fr && fr != frag_now; fr = fr->fr_next)
3511 add += fr->fr_fix;
3512 add += p - frag_now->fr_literal;
3513 }
3514
3515 /* We don't support dynamic linking on x86-64 yet. */
3516 if (flag_code == CODE_64BIT)
3517 abort ();
3518 reloc_type = BFD_RELOC_386_GOTPC;
3519 i.op[n].disps->X_add_number += add;
3520 }
062cd5e7 3521 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3522 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3523 }
3524 }
3525 }
3526}
252b5132 3527
29b0f896 3528static void
2bbd9c25
JJ		 3529output_imm (insn_start_frag, insn_start_off)
3530 fragS *insn_start_frag;
3531 offsetT insn_start_off;
29b0f896
AM		 3532{
3533 char *p;
3534 unsigned int n;
252b5132 3535
29b0f896
AM		 3536 for (n = 0; n < i.operands; n++)
3537 {
3538 if (i.types[n] & Imm)
3539 {
3540 if (i.op[n].imms->X_op == O_constant)
3541 {
3542 int size;
3543 offsetT val;
b4cac588 3544
29b0f896
AM		 3545 size = 4;
3546 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3547 {
3548 size = 2;
3549 if (i.types[n] & (Imm8 | Imm8S))
3550 size = 1;
3551 else if (i.types[n] & Imm64)
3552 size = 8;
3553 }
3554 val = offset_in_range (i.op[n].imms->X_add_number,
3555 size);
3556 p = frag_more (size);
3557 md_number_to_chars (p, val, size);
3558 }
3559 else
3560 {
3561 /* Not absolute_section.
3562 Need a 32-bit fixup (don't support 8bit
3563 non-absolute imms). Try to support other
3564 sizes ... */
f86103b7 3565 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3566 int size = 4;
3567 int sign = 0;
3568
3569 if ((i.types[n] & (Imm32S))
3570 && i.suffix == QWORD_MNEM_SUFFIX)
3571 sign = 1;
3572 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3573 {
3574 size = 2;
3575 if (i.types[n] & (Imm8 | Imm8S))
3576 size = 1;
3577 if (i.types[n] & Imm64)
3578 size = 8;
3579 }
520dc8e8 3580
29b0f896
AM		 3581 p = frag_more (size);
3582 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3583
2bbd9c25
JJ		 3584 /* This is tough to explain. We end up with this one if we
3585 * have operands that look like
3586 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3587 * obtain the absolute address of the GOT, and it is strongly
3588 * preferable from a performance point of view to avoid using
3589 * a runtime relocation for this. The actual sequence of
3590 * instructions often look something like:
3591 *
3592 * call .L66
3593 * .L66:
3594 * popl %ebx
3595 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3596 *
3597 * The call and pop essentially return the absolute address
3598 * of the label .L66 and store it in %ebx. The linker itself
3599 * will ultimately change the first operand of the addl so
3600 * that %ebx points to the GOT, but to keep things simple, the
3601 * .o file must have this operand set so that it generates not
3602 * the absolute address of .L66, but the absolute address of
3603 * itself. This allows the linker itself simply treat a GOTPC
3604 * relocation as asking for a pcrel offset to the GOT to be
3605 * added in, and the addend of the relocation is stored in the
3606 * operand field for the instruction itself.
3607 *
3608 * Our job here is to fix the operand so that it would add
3609 * the correct offset so that %ebx would point to itself. The
3610 * thing that is tricky is that .-.L66 will point to the
3611 * beginning of the instruction, so we need to further modify
3612 * the operand so that it will point to itself. There are
3613 * other cases where you have something like:
3614 *
3615 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3616 *
3617 * and here no correction would be required. Internally in
3618 * the assembler we treat operands of this form as not being
3619 * pcrel since the '.' is explicitly mentioned, and I wonder
3620 * whether it would simplify matters to do it this way. Who
3621 * knows. In earlier versions of the PIC patches, the
3622 * pcrel_adjust field was used to store the correction, but
3623 * since the expression is not pcrel, I felt it would be
3624 * confusing to do it this way. */
3625
29b0f896
AM		 3626 if (reloc_type == BFD_RELOC_32
3627 && GOT_symbol
3628 && GOT_symbol == i.op[n].imms->X_add_symbol
3629 && (i.op[n].imms->X_op == O_symbol
3630 || (i.op[n].imms->X_op == O_add
3631 && ((symbol_get_value_expression
3632 (i.op[n].imms->X_op_symbol)->X_op)
3633 == O_subtract))))
3634 {
2bbd9c25
JJ		 3635 offsetT add;
3636
3637 if (insn_start_frag == frag_now)
3638 add = (p - frag_now->fr_literal) - insn_start_off;
3639 else
3640 {
3641 fragS *fr;
3642
3643 add = insn_start_frag->fr_fix - insn_start_off;
3644 for (fr = insn_start_frag->fr_next;
3645 fr && fr != frag_now; fr = fr->fr_next)
3646 add += fr->fr_fix;
3647 add += p - frag_now->fr_literal;
3648 }
3649
29b0f896
AM		 3650 /* We don't support dynamic linking on x86-64 yet. */
3651 if (flag_code == CODE_64BIT)
3652 abort ();
3653 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3654 i.op[n].imms->X_add_number += add;
29b0f896 3655 }
29b0f896
AM		 3656 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3657 i.op[n].imms, 0, reloc_type);
3658 }
3659 }
3660 }
252b5132
RH		 3661}
3662\f
f3c180ae 3663#ifndef LEX_AT
f86103b7 3664static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
f3c180ae
AM		 3665
3666/* Parse operands of the form
3667 <symbol>@GOTOFF+<nnn>
3668 and similar .plt or .got references.
3669
3670 If we find one, set up the correct relocation in RELOC and copy the
3671 input string, minus the `@GOTOFF' into a malloc'd buffer for
3672 parsing by the calling routine. Return this buffer, and if ADJUST
3673 is non-null set it to the length of the string we removed from the
3674 input line. Otherwise return NULL. */
3675static char *
3676lex_got (reloc, adjust)
f86103b7 3677 enum bfd_reloc_code_real *reloc;
f3c180ae
AM		 3678 int *adjust;
3679{
3680 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3681 static const struct {
3682 const char *str;
f86103b7 3683 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
f3c180ae 3684 } gotrel[] = {
13ae64f3
JJ		 3685 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3686 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3687 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3688 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3689 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3690 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3691 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3692 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3693 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3694 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3695 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3696 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3697 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3698 };
3699 char *cp;
3700 unsigned int j;
3701
3702 for (cp = input_line_pointer; *cp != '@'; cp++)
3703 if (is_end_of_line[(unsigned char) *cp])
3704 return NULL;
3705
3706 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3707 {
3708 int len;
3709
3710 len = strlen (gotrel[j].str);
28f81592 3711 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3712 {
3713 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3714 {
28f81592
AM		 3715 int first, second;
3716 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3717
3718 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3719 if (adjust)
3720 *adjust = len;
f3c180ae
AM		 3721
3722 if (GOT_symbol == NULL)
3723 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3724
3725 /* Replace the relocation token with ' ', so that
3726 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3727
3728 /* The length of the first part of our input line. */
f3c180ae 3729 first = cp - input_line_pointer;
28f81592
AM		 3730
3731 /* The second part goes from after the reloc token until
3732 (and including) an end_of_line char. Don't use strlen
3733 here as the end_of_line char may not be a NUL. */
3734 past_reloc = cp + 1 + len;
3735 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3736 ;
3737 second = cp - past_reloc;
3738
3739 /* Allocate and copy string. The trailing NUL shouldn't
3740 be necessary, but be safe. */
3741 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3742 memcpy (tmpbuf, input_line_pointer, first);
3743 tmpbuf[first] = ' ';
28f81592
AM		 3744 memcpy (tmpbuf + first + 1, past_reloc, second);
3745 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3746 return tmpbuf;
3747 }
3748
3749 as_bad (_("@%s reloc is not supported in %s bit mode"),
3750 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3751 return NULL;
3752 }
3753 }
3754
3755 /* Might be a symbol version string. Don't as_bad here. */
3756 return NULL;
3757}
3758
3759/* x86_cons_fix_new is called via the expression parsing code when a
3760 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3761static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3762
3763void
3764x86_cons_fix_new (frag, off, len, exp)
3765 fragS *frag;
3766 unsigned int off;
3767 unsigned int len;
3768 expressionS *exp;
3769{
f86103b7 3770 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
f3c180ae
AM		 3771 got_reloc = NO_RELOC;
3772 fix_new_exp (frag, off, len, exp, 0, r);
3773}
3774
3775void
3776x86_cons (exp, size)
3777 expressionS *exp;
3778 int size;
3779{
3780 if (size == 4)
3781 {
3782 /* Handle @GOTOFF and the like in an expression. */
3783 char *save;
3784 char *gotfree_input_line;
3785 int adjust;
3786
3787 save = input_line_pointer;
3788 gotfree_input_line = lex_got (&got_reloc, &adjust);
3789 if (gotfree_input_line)
3790 input_line_pointer = gotfree_input_line;
3791
3792 expression (exp);
3793
3794 if (gotfree_input_line)
3795 {
3796 /* expression () has merrily parsed up to the end of line,
3797 or a comma - in the wrong buffer. Transfer how far
3798 input_line_pointer has moved to the right buffer. */
3799 input_line_pointer = (save
3800 + (input_line_pointer - gotfree_input_line)
3801 + adjust);
3802 free (gotfree_input_line);
3803 }
3804 }
3805 else
3806 expression (exp);
3807}
3808#endif
3809
6482c264
NC		 3810#ifdef TE_PE
3811
6482c264
NC		 3812void
3813x86_pe_cons_fix_new (frag, off, len, exp)
3814 fragS *frag;
3815 unsigned int off;
3816 unsigned int len;
3817 expressionS *exp;
3818{
3819 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3820
3821 if (exp->X_op == O_secrel)
3822 {
3823 exp->X_op = O_symbol;
3824 r = BFD_RELOC_32_SECREL;
3825 }
3826
3827 fix_new_exp (frag, off, len, exp, 0, r);
3828}
3829
3830static void
3831pe_directive_secrel (dummy)
3832 int dummy ATTRIBUTE_UNUSED;
3833{
3834 expressionS exp;
3835
3836 do
3837 {
3838 expression (&exp);
3839 if (exp.X_op == O_symbol)
3840 exp.X_op = O_secrel;
3841
3842 emit_expr (&exp, 4);
3843 }
3844 while (*input_line_pointer++ == ',');
3845
3846 input_line_pointer--;
3847 demand_empty_rest_of_line ();
3848}
3849
3850#endif
3851
252b5132
RH		 3852static int i386_immediate PARAMS ((char *));
3853
3854static int
3855i386_immediate (imm_start)
3856 char *imm_start;
3857{
3858 char *save_input_line_pointer;
f3c180ae
AM		 3859#ifndef LEX_AT
3860 char *gotfree_input_line;
3861#endif
252b5132 3862 segT exp_seg = 0;
47926f60 3863 expressionS *exp;
252b5132
RH		 3864
3865 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3866 {
d0b47220 3867 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3868 return 0;
3869 }
3870
3871 exp = &im_expressions[i.imm_operands++];
520dc8e8 3872 i.op[this_operand].imms = exp;
252b5132
RH		 3873
3874 if (is_space_char (*imm_start))
3875 ++imm_start;
3876
3877 save_input_line_pointer = input_line_pointer;
3878 input_line_pointer = imm_start;
3879
3880#ifndef LEX_AT
f3c180ae
AM		 3881 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3882 if (gotfree_input_line)
3883 input_line_pointer = gotfree_input_line;
252b5132
RH		 3884#endif
3885
3886 exp_seg = expression (exp);
3887
83183c0c 3888 SKIP_WHITESPACE ();
252b5132 3889 if (*input_line_pointer)
f3c180ae 3890 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3891
3892 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3893#ifndef LEX_AT
3894 if (gotfree_input_line)
3895 free (gotfree_input_line);
3896#endif
252b5132 3897
2daf4fd8 3898 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3899 {
47926f60 3900 /* Missing or bad expr becomes absolute 0. */
d0b47220 3901 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3902 imm_start);
252b5132
RH		 3903 exp->X_op = O_constant;
3904 exp->X_add_number = 0;
3905 exp->X_add_symbol = (symbolS *) 0;
3906 exp->X_op_symbol = (symbolS *) 0;
252b5132 3907 }
3e73aa7c 3908 else if (exp->X_op == O_constant)
252b5132 3909 {
47926f60 3910 /* Size it properly later. */
3e73aa7c
JH		 3911 i.types[this_operand] |= Imm64;
3912 /* If BFD64, sign extend val. */
3913 if (!use_rela_relocations)
3914 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3915 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3916 }
4c63da97 3917#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 3918 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3919 && exp_seg != absolute_section
47926f60 3920 && exp_seg != text_section
24eab124
AM		 3921 && exp_seg != data_section
3922 && exp_seg != bss_section
3923 && exp_seg != undefined_section
f86103b7 3924 && !bfd_is_com_section (exp_seg))
252b5132 3925 {
d0b47220 3926 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 3927 return 0;
3928 }
3929#endif
3930 else
3931 {
3932 /* This is an address. The size of the address will be
24eab124 3933 determined later, depending on destination register,
3e73aa7c
JH		 3934 suffix, or the default for the section. */
3935 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3936 }
3937
3938 return 1;
3939}
3940
551c1ca1 3941static char *i386_scale PARAMS ((char *));
252b5132 3942
551c1ca1 3943static char *
252b5132
RH		 3944i386_scale (scale)
3945 char *scale;
3946{
551c1ca1
AM		 3947 offsetT val;
3948 char *save = input_line_pointer;
252b5132 3949
551c1ca1
AM		 3950 input_line_pointer = scale;
3951 val = get_absolute_expression ();
3952
3953 switch (val)
252b5132 3954 {
551c1ca1 3955 case 1:
252b5132
RH		 3956 i.log2_scale_factor = 0;
3957 break;
551c1ca1 3958 case 2:
252b5132
RH		 3959 i.log2_scale_factor = 1;
3960 break;
551c1ca1 3961 case 4:
252b5132
RH		 3962 i.log2_scale_factor = 2;
3963 break;
551c1ca1 3964 case 8:
252b5132
RH		 3965 i.log2_scale_factor = 3;
3966 break;
3967 default:
252b5132 3968 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3969 scale);
551c1ca1
AM		 3970 input_line_pointer = save;
3971 return NULL;
252b5132 3972 }
29b0f896 3973 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3974 {
3975 as_warn (_("scale factor of %d without an index register"),
24eab124 3976 1 << i.log2_scale_factor);
252b5132
RH		 3977#if SCALE1_WHEN_NO_INDEX
3978 i.log2_scale_factor = 0;
3979#endif
3980 }
551c1ca1
AM		 3981 scale = input_line_pointer;
3982 input_line_pointer = save;
3983 return scale;
252b5132
RH		 3984}
3985
3986static int i386_displacement PARAMS ((char *, char *));
3987
3988static int
3989i386_displacement (disp_start, disp_end)
3990 char *disp_start;
3991 char *disp_end;
3992{
29b0f896 3993 expressionS *exp;
252b5132
RH		 3994 segT exp_seg = 0;
3995 char *save_input_line_pointer;
f3c180ae
AM		 3996#ifndef LEX_AT
3997 char *gotfree_input_line;
3998#endif
252b5132
RH		 3999 int bigdisp = Disp32;
4000
3e73aa7c 4001 if (flag_code == CODE_64BIT)
7ecd2f8b 4002 {
29b0f896
AM		 4003 if (i.prefix[ADDR_PREFIX] == 0)
4004 bigdisp = Disp64;
7ecd2f8b
JH		 4005 }
4006 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4007 bigdisp = Disp16;
252b5132
RH		 4008 i.types[this_operand] |= bigdisp;
4009
4010 exp = &disp_expressions[i.disp_operands];
520dc8e8 4011 i.op[this_operand].disps = exp;
252b5132
RH		 4012 i.disp_operands++;
4013 save_input_line_pointer = input_line_pointer;
4014 input_line_pointer = disp_start;
4015 END_STRING_AND_SAVE (disp_end);
4016
4017#ifndef GCC_ASM_O_HACK
4018#define GCC_ASM_O_HACK 0
4019#endif
4020#if GCC_ASM_O_HACK
4021 END_STRING_AND_SAVE (disp_end + 1);
4022 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4023 && displacement_string_end[-1] == '+')
252b5132
RH		 4024 {
4025 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4026 constraint within gcc asm statements.
4027 For instance:
4028
4029 #define _set_tssldt_desc(n,addr,limit,type) \
4030 __asm__ __volatile__ ( \
4031 "movw %w2,%0\n\t" \
4032 "movw %w1,2+%0\n\t" \
4033 "rorl $16,%1\n\t" \
4034 "movb %b1,4+%0\n\t" \
4035 "movb %4,5+%0\n\t" \
4036 "movb $0,6+%0\n\t" \
4037 "movb %h1,7+%0\n\t" \
4038 "rorl $16,%1" \
4039 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4040
4041 This works great except that the output assembler ends
4042 up looking a bit weird if it turns out that there is
4043 no offset. You end up producing code that looks like:
4044
4045 #APP
4046 movw $235,(%eax)
4047 movw %dx,2+(%eax)
4048 rorl $16,%edx
4049 movb %dl,4+(%eax)
4050 movb $137,5+(%eax)
4051 movb $0,6+(%eax)
4052 movb %dh,7+(%eax)
4053 rorl $16,%edx
4054 #NO_APP
4055
47926f60 4056 So here we provide the missing zero. */
24eab124
AM		 4057
4058 *displacement_string_end = '0';
252b5132
RH		 4059 }
4060#endif
4061#ifndef LEX_AT
f3c180ae
AM		 4062 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4063 if (gotfree_input_line)
4064 input_line_pointer = gotfree_input_line;
252b5132
RH		 4065#endif
4066
24eab124 4067 exp_seg = expression (exp);
252b5132 4068
636c26b0
AM		 4069 SKIP_WHITESPACE ();
4070 if (*input_line_pointer)
4071 as_bad (_("junk `%s' after expression"), input_line_pointer);
4072#if GCC_ASM_O_HACK
4073 RESTORE_END_STRING (disp_end + 1);
4074#endif
4075 RESTORE_END_STRING (disp_end);
4076 input_line_pointer = save_input_line_pointer;
4077#ifndef LEX_AT
4078 if (gotfree_input_line)
4079 free (gotfree_input_line);
4080#endif
4081
24eab124
AM		 4082 /* We do this to make sure that the section symbol is in
4083 the symbol table. We will ultimately change the relocation
47926f60 4084 to be relative to the beginning of the section. */
1ae12ab7
AM		 4085 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4086 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 4087 {
636c26b0
AM		 4088 if (exp->X_op != O_symbol)
4089 {
4090 as_bad (_("bad expression used with @%s"),
4091 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4092 ? "GOTPCREL"
4093 : "GOTOFF"));
4094 return 0;
4095 }
4096
e5cb08ac 4097 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4098 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4099 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4100 exp->X_op = O_subtract;
4101 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4102 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4103 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 4104 else
29b0f896 4105 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4106 }
252b5132 4107
2daf4fd8
AM		 4108 if (exp->X_op == O_absent || exp->X_op == O_big)
4109 {
47926f60 4110 /* Missing or bad expr becomes absolute 0. */
d0b47220 4111 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4112 disp_start);
4113 exp->X_op = O_constant;
4114 exp->X_add_number = 0;
4115 exp->X_add_symbol = (symbolS *) 0;
4116 exp->X_op_symbol = (symbolS *) 0;
4117 }
4118
4c63da97 4119#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4120 if (exp->X_op != O_constant
45288df1 4121 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4122 && exp_seg != absolute_section
45288df1
AM		 4123 && exp_seg != text_section
4124 && exp_seg != data_section
4125 && exp_seg != bss_section
31312f95 4126 && exp_seg != undefined_section
f86103b7 4127 && !bfd_is_com_section (exp_seg))
24eab124 4128 {
d0b47220 4129 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4130 return 0;
4131 }
252b5132 4132#endif
3e73aa7c
JH		 4133 else if (flag_code == CODE_64BIT)
4134 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 4135 return 1;
4136}
4137
e5cb08ac 4138static int i386_index_check PARAMS ((const char *));
252b5132 4139
eecb386c 4140/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4141 Return 1 on success, 0 on a failure. */
4142
252b5132 4143static int
eecb386c
AM		 4144i386_index_check (operand_string)
4145 const char *operand_string;
252b5132 4146{
3e73aa7c 4147 int ok;
24eab124 4148#if INFER_ADDR_PREFIX
eecb386c
AM		 4149 int fudged = 0;
4150
24eab124
AM		 4151 tryprefix:
4152#endif
3e73aa7c 4153 ok = 1;
20f0a1fc
NC		 4154 if (flag_code == CODE_64BIT)
4155 {
4156 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4157
4158 if ((i.base_reg
4159 && ((i.base_reg->reg_type & RegXX) == 0)
4160 && (i.base_reg->reg_type != BaseIndex
4161 || i.index_reg))
4162 || (i.index_reg
4163 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4164 != (RegXX | BaseIndex))))
4165 ok = 0;
3e73aa7c
JH		 4166 }
4167 else
4168 {
4169 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4170 {
4171 /* 16bit checks. */
4172 if ((i.base_reg
29b0f896
AM		 4173 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4174 != (Reg16 | BaseIndex)))
3e73aa7c 4175 || (i.index_reg
29b0f896
AM		 4176 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4177 != (Reg16 | BaseIndex))
4178 || !(i.base_reg
4179 && i.base_reg->reg_num < 6
4180 && i.index_reg->reg_num >= 6
4181 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4182 ok = 0;
4183 }
4184 else
e5cb08ac 4185 {
3e73aa7c
JH		 4186 /* 32bit checks. */
4187 if ((i.base_reg
4188 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4189 || (i.index_reg
29b0f896
AM		 4190 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4191 != (Reg32 | BaseIndex))))
e5cb08ac 4192 ok = 0;
3e73aa7c
JH		 4193 }
4194 }
4195 if (!ok)
24eab124
AM		 4196 {
4197#if INFER_ADDR_PREFIX
20f0a1fc 4198 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4199 {
4200 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4201 i.prefixes += 1;
b23bac36
AM		 4202 /* Change the size of any displacement too. At most one of
4203 Disp16 or Disp32 is set.
4204 FIXME. There doesn't seem to be any real need for separate
4205 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4206 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4207 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4208 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4209 fudged = 1;
24eab124
AM		 4210 goto tryprefix;
4211 }
eecb386c
AM		 4212 if (fudged)
4213 as_bad (_("`%s' is not a valid base/index expression"),
4214 operand_string);
4215 else
c388dee8 4216#endif
eecb386c
AM		 4217 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4218 operand_string,
3e73aa7c 4219 flag_code_names[flag_code]);
24eab124 4220 }
20f0a1fc 4221 return ok;
24eab124 4222}
252b5132 4223
252b5132 4224/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4225 on error. */
252b5132 4226
252b5132
RH		 4227static int
4228i386_operand (operand_string)
4229 char *operand_string;
4230{
af6bdddf
AM		 4231 const reg_entry *r;
4232 char *end_op;
24eab124 4233 char *op_string = operand_string;
252b5132 4234
24eab124 4235 if (is_space_char (*op_string))
252b5132
RH		 4236 ++op_string;
4237
24eab124 4238 /* We check for an absolute prefix (differentiating,
47926f60 4239 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4240 if (*op_string == ABSOLUTE_PREFIX)
4241 {
4242 ++op_string;
4243 if (is_space_char (*op_string))
4244 ++op_string;
4245 i.types[this_operand] |= JumpAbsolute;
4246 }
252b5132 4247
47926f60 4248 /* Check if operand is a register. */
af6bdddf
AM		 4249 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4250 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4251 {
24eab124
AM		 4252 /* Check for a segment override by searching for ':' after a
4253 segment register. */
4254 op_string = end_op;
4255 if (is_space_char (*op_string))
4256 ++op_string;
4257 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4258 {
4259 switch (r->reg_num)
4260 {
4261 case 0:
4262 i.seg[i.mem_operands] = &es;
4263 break;
4264 case 1:
4265 i.seg[i.mem_operands] = &cs;
4266 break;
4267 case 2:
4268 i.seg[i.mem_operands] = &ss;
4269 break;
4270 case 3:
4271 i.seg[i.mem_operands] = &ds;
4272 break;
4273 case 4:
4274 i.seg[i.mem_operands] = &fs;
4275 break;
4276 case 5:
4277 i.seg[i.mem_operands] = &gs;
4278 break;
4279 }
252b5132 4280
24eab124 4281 /* Skip the ':' and whitespace. */
252b5132
RH		 4282 ++op_string;
4283 if (is_space_char (*op_string))
24eab124 4284 ++op_string;
252b5132 4285
24eab124
AM		 4286 if (!is_digit_char (*op_string)
4287 && !is_identifier_char (*op_string)
4288 && *op_string != '('
4289 && *op_string != ABSOLUTE_PREFIX)
4290 {
4291 as_bad (_("bad memory operand `%s'"), op_string);
4292 return 0;
4293 }
47926f60 4294 /* Handle case of %es:*foo. */
24eab124
AM		 4295 if (*op_string == ABSOLUTE_PREFIX)
4296 {
4297 ++op_string;
4298 if (is_space_char (*op_string))
4299 ++op_string;
4300 i.types[this_operand] |= JumpAbsolute;
4301 }
4302 goto do_memory_reference;
4303 }
4304 if (*op_string)
4305 {
d0b47220 4306 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4307 return 0;
4308 }
4309 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4310 i.op[this_operand].regs = r;
24eab124
AM		 4311 i.reg_operands++;
4312 }
af6bdddf
AM		 4313 else if (*op_string == REGISTER_PREFIX)
4314 {
4315 as_bad (_("bad register name `%s'"), op_string);
4316 return 0;
4317 }
24eab124 4318 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4319 {
24eab124
AM		 4320 ++op_string;
4321 if (i.types[this_operand] & JumpAbsolute)
4322 {
d0b47220 4323 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4324 return 0;
4325 }
4326 if (!i386_immediate (op_string))
4327 return 0;
4328 }
4329 else if (is_digit_char (*op_string)
4330 || is_identifier_char (*op_string)
e5cb08ac 4331 || *op_string == '(')
24eab124 4332 {
47926f60 4333 /* This is a memory reference of some sort. */
af6bdddf 4334 char *base_string;
252b5132 4335
47926f60 4336 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4337 char *displacement_string_start;
4338 char *displacement_string_end;
252b5132 4339
24eab124 4340 do_memory_reference:
24eab124
AM		 4341 if ((i.mem_operands == 1
4342 && (current_templates->start->opcode_modifier & IsString) == 0)
4343 || i.mem_operands == 2)
4344 {
4345 as_bad (_("too many memory references for `%s'"),
4346 current_templates->start->name);
4347 return 0;
4348 }
252b5132 4349
24eab124
AM		 4350 /* Check for base index form. We detect the base index form by
4351 looking for an ')' at the end of the operand, searching
4352 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4353 after the '('. */
af6bdddf 4354 base_string = op_string + strlen (op_string);
c3332e24 4355
af6bdddf
AM		 4356 --base_string;
4357 if (is_space_char (*base_string))
4358 --base_string;
252b5132 4359
47926f60 4360 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4361 displacement_string_start = op_string;
4362 displacement_string_end = base_string + 1;
252b5132 4363
24eab124
AM		 4364 if (*base_string == ')')
4365 {
af6bdddf 4366 char *temp_string;
24eab124
AM		 4367 unsigned int parens_balanced = 1;
4368 /* We've already checked that the number of left & right ()'s are
47926f60 4369 equal, so this loop will not be infinite. */
24eab124
AM		 4370 do
4371 {
4372 base_string--;
4373 if (*base_string == ')')
4374 parens_balanced++;
4375 if (*base_string == '(')
4376 parens_balanced--;
4377 }
4378 while (parens_balanced);
c3332e24 4379
af6bdddf 4380 temp_string = base_string;
c3332e24 4381
24eab124 4382 /* Skip past '(' and whitespace. */
252b5132
RH		 4383 ++base_string;
4384 if (is_space_char (*base_string))
24eab124 4385 ++base_string;
252b5132 4386
af6bdddf
AM		 4387 if (*base_string == ','
4388 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4389 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4390 {
af6bdddf 4391 displacement_string_end = temp_string;
252b5132 4392
af6bdddf 4393 i.types[this_operand] |= BaseIndex;
252b5132 4394
af6bdddf 4395 if (i.base_reg)
24eab124 4396 {
24eab124
AM		 4397 base_string = end_op;
4398 if (is_space_char (*base_string))
4399 ++base_string;
af6bdddf
AM		 4400 }
4401
4402 /* There may be an index reg or scale factor here. */
4403 if (*base_string == ',')
4404 {
4405 ++base_string;
4406 if (is_space_char (*base_string))
4407 ++base_string;
4408
4409 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4410 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4411 {
af6bdddf 4412 base_string = end_op;
24eab124
AM		 4413 if (is_space_char (*base_string))
4414 ++base_string;
af6bdddf
AM		 4415 if (*base_string == ',')
4416 {
4417 ++base_string;
4418 if (is_space_char (*base_string))
4419 ++base_string;
4420 }
e5cb08ac 4421 else if (*base_string != ')')
af6bdddf
AM		 4422 {
4423 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4424 operand_string);
4425 return 0;
4426 }
24eab124 4427 }
af6bdddf 4428 else if (*base_string == REGISTER_PREFIX)
24eab124 4429 {
af6bdddf 4430 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4431 return 0;
4432 }
252b5132 4433
47926f60 4434 /* Check for scale factor. */
551c1ca1 4435 if (*base_string != ')')
af6bdddf 4436 {
551c1ca1
AM		 4437 char *end_scale = i386_scale (base_string);
4438
4439 if (!end_scale)
af6bdddf 4440 return 0;
24eab124 4441
551c1ca1 4442 base_string = end_scale;
af6bdddf
AM		 4443 if (is_space_char (*base_string))
4444 ++base_string;
4445 if (*base_string != ')')
4446 {
4447 as_bad (_("expecting `)' after scale factor in `%s'"),
4448 operand_string);
4449 return 0;
4450 }
4451 }
4452 else if (!i.index_reg)
24eab124 4453 {
af6bdddf
AM		 4454 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4455 *base_string);
24eab124
AM		 4456 return 0;
4457 }
4458 }
af6bdddf 4459 else if (*base_string != ')')
24eab124 4460 {
af6bdddf
AM		 4461 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4462 operand_string);
24eab124
AM		 4463 return 0;
4464 }
c3332e24 4465 }
af6bdddf 4466 else if (*base_string == REGISTER_PREFIX)
c3332e24 4467 {
af6bdddf 4468 as_bad (_("bad register name `%s'"), base_string);
24eab124 4469 return 0;
c3332e24 4470 }
24eab124
AM		 4471 }
4472
4473 /* If there's an expression beginning the operand, parse it,
4474 assuming displacement_string_start and
4475 displacement_string_end are meaningful. */
4476 if (displacement_string_start != displacement_string_end)
4477 {
4478 if (!i386_displacement (displacement_string_start,
4479 displacement_string_end))
4480 return 0;
4481 }
4482
4483 /* Special case for (%dx) while doing input/output op. */
4484 if (i.base_reg
4485 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4486 && i.index_reg == 0
4487 && i.log2_scale_factor == 0
4488 && i.seg[i.mem_operands] == 0
4489 && (i.types[this_operand] & Disp) == 0)
4490 {
4491 i.types[this_operand] = InOutPortReg;
4492 return 1;
4493 }
4494
eecb386c
AM		 4495 if (i386_index_check (operand_string) == 0)
4496 return 0;
24eab124
AM		 4497 i.mem_operands++;
4498 }
4499 else
ce8a8b2f
AM		 4500 {
4501 /* It's not a memory operand; argh! */
24eab124
AM		 4502 as_bad (_("invalid char %s beginning operand %d `%s'"),
4503 output_invalid (*op_string),
4504 this_operand + 1,
4505 op_string);
4506 return 0;
4507 }
47926f60 4508 return 1; /* Normal return. */
252b5132
RH		 4509}
4510\f
ee7fcc42
AM		 4511/* md_estimate_size_before_relax()
4512
4513 Called just before relax() for rs_machine_dependent frags. The x86
4514 assembler uses these frags to handle variable size jump
4515 instructions.
4516
4517 Any symbol that is now undefined will not become defined.
4518 Return the correct fr_subtype in the frag.
4519 Return the initial "guess for variable size of frag" to caller.
4520 The guess is actually the growth beyond the fixed part. Whatever
4521 we do to grow the fixed or variable part contributes to our
4522 returned value. */
4523
252b5132
RH		 4524int
4525md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4526 fragS *fragP;
4527 segT segment;
252b5132 4528{
252b5132 4529 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4530 check for un-relaxable symbols. On an ELF system, we can't relax
4531 an externally visible symbol, because it may be overridden by a
4532 shared library. */
4533 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4535 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4536 && (S_IS_EXTERNAL (fragP->fr_symbol)
4537 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4538#endif
4539 )
252b5132 4540 {
b98ef147
AM		 4541 /* Symbol is undefined in this segment, or we need to keep a
4542 reloc so that weak symbols can be overridden. */
4543 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4544 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4545 unsigned char *opcode;
4546 int old_fr_fix;
f6af82bd 4547
ee7fcc42
AM		 4548 if (fragP->fr_var != NO_RELOC)
4549 reloc_type = fragP->fr_var;
b98ef147 4550 else if (size == 2)
f6af82bd
AM		 4551 reloc_type = BFD_RELOC_16_PCREL;
4552 else
4553 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4554
ee7fcc42
AM		 4555 old_fr_fix = fragP->fr_fix;
4556 opcode = (unsigned char *) fragP->fr_opcode;
4557
fddf5b5b 4558 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4559 {
fddf5b5b
AM		 4560 case UNCOND_JUMP:
4561 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4562 opcode[0] = 0xe9;
252b5132 4563 fragP->fr_fix += size;
062cd5e7
AS		 4564 fix_new (fragP, old_fr_fix, size,
4565 fragP->fr_symbol,
4566 fragP->fr_offset, 1,
4567 reloc_type);
252b5132
RH		 4568 break;
4569
fddf5b5b 4570 case COND_JUMP86:
412167cb
AM		 4571 if (size == 2
4572 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4573 {
4574 /* Negate the condition, and branch past an
4575 unconditional jump. */
4576 opcode[0] ^= 1;
4577 opcode[1] = 3;
4578 /* Insert an unconditional jump. */
4579 opcode[2] = 0xe9;
4580 /* We added two extra opcode bytes, and have a two byte
4581 offset. */
4582 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4583 fix_new (fragP, old_fr_fix + 2, 2,
4584 fragP->fr_symbol,
4585 fragP->fr_offset, 1,
4586 reloc_type);
fddf5b5b
AM		 4587 break;
4588 }
4589 /* Fall through. */
4590
4591 case COND_JUMP:
412167cb
AM		 4592 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4593 {
3e02c1cc
AM		 4594 fixS *fixP;
4595
412167cb 4596 fragP->fr_fix += 1;
3e02c1cc
AM		 4597 fixP = fix_new (fragP, old_fr_fix, 1,
4598 fragP->fr_symbol,
4599 fragP->fr_offset, 1,
4600 BFD_RELOC_8_PCREL);
4601 fixP->fx_signed = 1;
412167cb
AM		 4602 break;
4603 }
93c2a809 4604
24eab124 4605 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4606 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4607 opcode[1] = opcode[0] + 0x10;
f6af82bd 4608 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4609 /* We've added an opcode byte. */
4610 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4611 fix_new (fragP, old_fr_fix + 1, size,
4612 fragP->fr_symbol,
4613 fragP->fr_offset, 1,
4614 reloc_type);
252b5132 4615 break;
fddf5b5b
AM		 4616
4617 default:
4618 BAD_CASE (fragP->fr_subtype);
4619 break;
252b5132
RH		 4620 }
4621 frag_wane (fragP);
ee7fcc42 4622 return fragP->fr_fix - old_fr_fix;
252b5132 4623 }
93c2a809 4624
93c2a809
AM		 4625 /* Guess size depending on current relax state. Initially the relax
4626 state will correspond to a short jump and we return 1, because
4627 the variable part of the frag (the branch offset) is one byte
4628 long. However, we can relax a section more than once and in that
4629 case we must either set fr_subtype back to the unrelaxed state,
4630 or return the value for the appropriate branch. */
4631 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4632}
4633
47926f60
KH		 4634/* Called after relax() is finished.
4635
4636 In: Address of frag.
4637 fr_type == rs_machine_dependent.
4638 fr_subtype is what the address relaxed to.
4639
4640 Out: Any fixSs and constants are set up.
4641 Caller will turn frag into a ".space 0". */
4642
252b5132
RH		 4643void
4644md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4645 bfd *abfd ATTRIBUTE_UNUSED;
4646 segT sec ATTRIBUTE_UNUSED;
29b0f896 4647 fragS *fragP;
252b5132 4648{
29b0f896 4649 unsigned char *opcode;
252b5132 4650 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4651 offsetT target_address;
4652 offsetT opcode_address;
252b5132 4653 unsigned int extension = 0;
847f7ad4 4654 offsetT displacement_from_opcode_start;
252b5132
RH		 4655
4656 opcode = (unsigned char *) fragP->fr_opcode;
4657
47926f60 4658 /* Address we want to reach in file space. */
252b5132 4659 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4660
47926f60 4661 /* Address opcode resides at in file space. */
252b5132
RH		 4662 opcode_address = fragP->fr_address + fragP->fr_fix;
4663
47926f60 4664 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4665 displacement_from_opcode_start = target_address - opcode_address;
4666
fddf5b5b 4667 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4668 {
47926f60
KH		 4669 /* Don't have to change opcode. */
4670 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4671 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4672 }
4673 else
4674 {
4675 if (no_cond_jump_promotion
4676 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4677 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4678
fddf5b5b
AM		 4679 switch (fragP->fr_subtype)
4680 {
4681 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4682 extension = 4; /* 1 opcode + 4 displacement */
4683 opcode[0] = 0xe9;
4684 where_to_put_displacement = &opcode[1];
4685 break;
252b5132 4686
fddf5b5b
AM		 4687 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4688 extension = 2; /* 1 opcode + 2 displacement */
4689 opcode[0] = 0xe9;
4690 where_to_put_displacement = &opcode[1];
4691 break;
252b5132 4692
fddf5b5b
AM		 4693 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4694 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4695 extension = 5; /* 2 opcode + 4 displacement */
4696 opcode[1] = opcode[0] + 0x10;
4697 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4698 where_to_put_displacement = &opcode[2];
4699 break;
252b5132 4700
fddf5b5b
AM		 4701 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4702 extension = 3; /* 2 opcode + 2 displacement */
4703 opcode[1] = opcode[0] + 0x10;
4704 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4705 where_to_put_displacement = &opcode[2];
4706 break;
252b5132 4707
fddf5b5b
AM		 4708 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4709 extension = 4;
4710 opcode[0] ^= 1;
4711 opcode[1] = 3;
4712 opcode[2] = 0xe9;
4713 where_to_put_displacement = &opcode[3];
4714 break;
4715
4716 default:
4717 BAD_CASE (fragP->fr_subtype);
4718 break;
4719 }
252b5132 4720 }
fddf5b5b 4721
47926f60 4722 /* Now put displacement after opcode. */
252b5132
RH		 4723 md_number_to_chars ((char *) where_to_put_displacement,
4724 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4725 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4726 fragP->fr_fix += extension;
4727}
4728\f
47926f60
KH		 4729/* Size of byte displacement jmp. */
4730int md_short_jump_size = 2;
4731
4732/* Size of dword displacement jmp. */
4733int md_long_jump_size = 5;
252b5132 4734
47926f60
KH		 4735/* Size of relocation record. */
4736const int md_reloc_size = 8;
252b5132
RH		 4737
4738void
4739md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4740 char *ptr;
4741 addressT from_addr, to_addr;
ab9da554
ILT		 4742 fragS *frag ATTRIBUTE_UNUSED;
4743 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4744{
847f7ad4 4745 offsetT offset;
252b5132
RH		 4746
4747 offset = to_addr - (from_addr + 2);
47926f60
KH		 4748 /* Opcode for byte-disp jump. */
4749 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4750 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4751}
4752
4753void
4754md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4755 char *ptr;
4756 addressT from_addr, to_addr;
a38cf1db
AM		 4757 fragS *frag ATTRIBUTE_UNUSED;
4758 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4759{
847f7ad4 4760 offsetT offset;
252b5132 4761
a38cf1db
AM		 4762 offset = to_addr - (from_addr + 5);
4763 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4764 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4765}
4766\f
4767/* Apply a fixup (fixS) to segment data, once it has been determined
4768 by our caller that we have all the info we need to fix it up.
4769
4770 On the 386, immediates, displacements, and data pointers are all in
4771 the same (little-endian) format, so we don't need to care about which
4772 we are handling. */
4773
94f592af
NC		 4774void
4775md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4776 /* The fix we're to put in. */
4777 fixS *fixP;
47926f60 4778 /* Pointer to the value of the bits. */
c6682705 4779 valueT *valP;
47926f60
KH		 4780 /* Segment fix is from. */
4781 segT seg ATTRIBUTE_UNUSED;
252b5132 4782{
94f592af 4783 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4784 valueT value = *valP;
252b5132 4785
f86103b7 4786#if !defined (TE_Mach)
93382f6d
AM		 4787 if (fixP->fx_pcrel)
4788 {
4789 switch (fixP->fx_r_type)
4790 {
5865bb77
ILT		 4791 default:
4792 break;
4793
93382f6d
AM		 4794 case BFD_RELOC_32:
4795 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4796 break;
4797 case BFD_RELOC_16:
4798 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4799 break;
4800 case BFD_RELOC_8:
4801 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4802 break;
4803 }
4804 }
252b5132 4805
a161fe53 4806 if (fixP->fx_addsy != NULL
31312f95
AM		 4807 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4808 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4809 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4810 && !use_rela_relocations)
252b5132 4811 {
31312f95
AM		 4812 /* This is a hack. There should be a better way to handle this.
4813 This covers for the fact that bfd_install_relocation will
4814 subtract the current location (for partial_inplace, PC relative
4815 relocations); see more below. */
252b5132
RH		 4816#ifndef OBJ_AOUT
4817 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4818#ifdef TE_PE
4819 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4820#endif
4821 )
4822 value += fixP->fx_where + fixP->fx_frag->fr_address;
4823#endif
4824#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4825 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4826 {
6539b54b 4827 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4828
6539b54b 4829 if ((sym_seg == seg
2f66722d 4830 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4831 && sym_seg != absolute_section))
ae6063d4 4832 && !generic_force_reloc (fixP))
2f66722d
AM		 4833 {
4834 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4835 bfd_install_relocation subtracts them out again. I think
4836 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4837 it. FIXME. */
4838 value += fixP->fx_where + fixP->fx_frag->fr_address;
4839 }
252b5132
RH		 4840 }
4841#endif
4842#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4843 /* For some reason, the PE format does not store a
4844 section address offset for a PC relative symbol. */
4845 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4846#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4847 || S_IS_WEAK (fixP->fx_addsy)
4848#endif
4849 )
252b5132
RH		 4850 value += md_pcrel_from (fixP);
4851#endif
4852 }
4853
4854 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4855 and we must not disappoint it. */
252b5132
RH		 4856#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4857 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4858 && fixP->fx_addsy)
47926f60
KH		 4859 switch (fixP->fx_r_type)
4860 {
4861 case BFD_RELOC_386_PLT32:
3e73aa7c 4862 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4863 /* Make the jump instruction point to the address of the operand. At
4864 runtime we merely add the offset to the actual PLT entry. */
4865 value = -4;
4866 break;
31312f95 4867
13ae64f3
JJ		 4868 case BFD_RELOC_386_TLS_GD:
4869 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4870 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4871 case BFD_RELOC_386_TLS_IE:
4872 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4873 case BFD_RELOC_X86_64_TLSGD:
4874 case BFD_RELOC_X86_64_TLSLD:
4875 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4876 value = 0; /* Fully resolved at runtime. No addend. */
4877 /* Fallthrough */
4878 case BFD_RELOC_386_TLS_LE:
4879 case BFD_RELOC_386_TLS_LDO_32:
4880 case BFD_RELOC_386_TLS_LE_32:
4881 case BFD_RELOC_X86_64_DTPOFF32:
4882 case BFD_RELOC_X86_64_TPOFF32:
4883 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4884 break;
4885
4886 case BFD_RELOC_386_GOT32:
4887 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4888 value = 0; /* Fully resolved at runtime. No addend. */
4889 break;
47926f60
KH		 4890
4891 case BFD_RELOC_VTABLE_INHERIT:
4892 case BFD_RELOC_VTABLE_ENTRY:
4893 fixP->fx_done = 0;
94f592af 4894 return;
47926f60
KH		 4895
4896 default:
4897 break;
4898 }
4899#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4900 *valP = value;
f86103b7 4901#endif /* !defined (TE_Mach) */
3e73aa7c 4902
3e73aa7c 4903 /* Are we finished with this relocation now? */
c6682705 4904 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 4905 fixP->fx_done = 1;
4906 else if (use_rela_relocations)
4907 {
4908 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4909 /* Remember value for tc_gen_reloc. */
4910 fixP->fx_addnumber = value;
3e73aa7c
JH		 4911 value = 0;
4912 }
f86103b7 4913
94f592af 4914 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4915}
252b5132 4916\f
252b5132
RH		 4917#define MAX_LITTLENUMS 6
4918
47926f60
KH		 4919/* Turn the string pointed to by litP into a floating point constant
4920 of type TYPE, and emit the appropriate bytes. The number of
4921 LITTLENUMS emitted is stored in *SIZEP. An error message is
4922 returned, or NULL on OK. */
4923
252b5132
RH		 4924char *
4925md_atof (type, litP, sizeP)
2ab9b79e 4926 int type;
252b5132
RH		 4927 char *litP;
4928 int *sizeP;
4929{
4930 int prec;
4931 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4932 LITTLENUM_TYPE *wordP;
4933 char *t;
4934
4935 switch (type)
4936 {
4937 case 'f':
4938 case 'F':
4939 prec = 2;
4940 break;
4941
4942 case 'd':
4943 case 'D':
4944 prec = 4;
4945 break;
4946
4947 case 'x':
4948 case 'X':
4949 prec = 5;
4950 break;
4951
4952 default:
4953 *sizeP = 0;
4954 return _("Bad call to md_atof ()");
4955 }
4956 t = atof_ieee (input_line_pointer, type, words);
4957 if (t)
4958 input_line_pointer = t;
4959
4960 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4961 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4962 the bigendian 386. */
4963 for (wordP = words + prec - 1; prec--;)
4964 {
4965 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4966 litP += sizeof (LITTLENUM_TYPE);
4967 }
4968 return 0;
4969}
4970\f
4971char output_invalid_buf[8];
4972
252b5132
RH		 4973static char *
4974output_invalid (c)
4975 int c;
4976{
3882b010 4977 if (ISPRINT (c))
252b5132
RH		 4978 sprintf (output_invalid_buf, "'%c'", c);
4979 else
4980 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4981 return output_invalid_buf;
4982}
4983
af6bdddf 4984/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4985
4986static const reg_entry *
4987parse_register (reg_string, end_op)
4988 char *reg_string;
4989 char **end_op;
4990{
af6bdddf
AM		 4991 char *s = reg_string;
4992 char *p;
252b5132
RH		 4993 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4994 const reg_entry *r;
4995
4996 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4997 if (*s == REGISTER_PREFIX)
4998 ++s;
4999
5000 if (is_space_char (*s))
5001 ++s;
5002
5003 p = reg_name_given;
af6bdddf 5004 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5005 {
5006 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5007 return (const reg_entry *) NULL;
5008 s++;
252b5132
RH		 5009 }
5010
6588847e
DN		 5011 /* For naked regs, make sure that we are not dealing with an identifier.
5012 This prevents confusing an identifier like `eax_var' with register
5013 `eax'. */
5014 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5015 return (const reg_entry *) NULL;
5016
af6bdddf 5017 *end_op = s;
252b5132
RH		 5018
5019 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5020
5f47d35b 5021 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5022 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5023 {
5f47d35b
AM		 5024 if (is_space_char (*s))
5025 ++s;
5026 if (*s == '(')
5027 {
af6bdddf 5028 ++s;
5f47d35b
AM		 5029 if (is_space_char (*s))
5030 ++s;
5031 if (*s >= '0' && *s <= '7')
5032 {
5033 r = &i386_float_regtab[*s - '0'];
af6bdddf 5034 ++s;
5f47d35b
AM		 5035 if (is_space_char (*s))
5036 ++s;
5037 if (*s == ')')
5038 {
5039 *end_op = s + 1;
5040 return r;
5041 }
5f47d35b 5042 }
47926f60 5043 /* We have "%st(" then garbage. */
5f47d35b
AM		 5044 return (const reg_entry *) NULL;
5045 }
5046 }
5047
1ae00879 5048 if (r != NULL
20f0a1fc 5049 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5050 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5051 && flag_code != CODE_64BIT)
20f0a1fc 5052 return (const reg_entry *) NULL;
1ae00879 5053
252b5132
RH		 5054 return r;
5055}
5056\f
4cc782b5 5057#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5058const char *md_shortopts = "kVQ:sqn";
252b5132 5059#else
12b55ccc 5060const char *md_shortopts = "qn";
252b5132 5061#endif
6e0b89ee 5062
252b5132 5063struct option md_longopts[] = {
3e73aa7c
JH		 5064#define OPTION_32 (OPTION_MD_BASE + 0)
5065 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5066#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5067#define OPTION_64 (OPTION_MD_BASE + 1)
5068 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5069#endif
252b5132
RH		 5070 {NULL, no_argument, NULL, 0}
5071};
5072size_t md_longopts_size = sizeof (md_longopts);
5073
5074int
5075md_parse_option (c, arg)
5076 int c;
ab9da554 5077 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5078{
5079 switch (c)
5080 {
12b55ccc
L		 5081 case 'n':
5082 optimize_align_code = 0;
5083 break;
5084
a38cf1db
AM		 5085 case 'q':
5086 quiet_warnings = 1;
252b5132
RH		 5087 break;
5088
5089#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5090 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5091 should be emitted or not. FIXME: Not implemented. */
5092 case 'Q':
252b5132
RH		 5093 break;
5094
5095 /* -V: SVR4 argument to print version ID. */
5096 case 'V':
5097 print_version_id ();
5098 break;
5099
a38cf1db
AM		 5100 /* -k: Ignore for FreeBSD compatibility. */
5101 case 'k':
252b5132 5102 break;
4cc782b5
ILT		 5103
5104 case 's':
5105 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5106 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5107 break;
6e0b89ee 5108
3e73aa7c
JH		 5109 case OPTION_64:
5110 {
5111 const char **list, **l;
5112
3e73aa7c
JH		 5113 list = bfd_target_list ();
5114 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5115 if (strcmp (*l, "elf64-x86-64") == 0)
5116 {
5117 default_arch = "x86_64";
5118 break;
5119 }
3e73aa7c 5120 if (*l == NULL)
6e0b89ee 5121 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5122 free (list);
5123 }
5124 break;
5125#endif
252b5132 5126
6e0b89ee
AM		 5127 case OPTION_32:
5128 default_arch = "i386";
5129 break;
5130
252b5132
RH		 5131 default:
5132 return 0;
5133 }
5134 return 1;
5135}
5136
5137void
5138md_show_usage (stream)
5139 FILE *stream;
5140{
4cc782b5
ILT		 5141#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5142 fprintf (stream, _("\
a38cf1db
AM		 5143 -Q ignored\n\
5144 -V print assembler version number\n\
5145 -k ignored\n\
12b55ccc 5146 -n Do not optimize code alignment\n\
a38cf1db
AM		 5147 -q quieten some warnings\n\
5148 -s ignored\n"));
5149#else
5150 fprintf (stream, _("\
12b55ccc 5151 -n Do not optimize code alignment\n\
a38cf1db 5152 -q quieten some warnings\n"));
4cc782b5 5153#endif
252b5132
RH		 5154}
5155
3e73aa7c
JH		 5156#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5157 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5158
5159/* Pick the target format to use. */
5160
47926f60 5161const char *
252b5132
RH		 5162i386_target_format ()
5163{
3e73aa7c
JH		 5164 if (!strcmp (default_arch, "x86_64"))
5165 set_code_flag (CODE_64BIT);
5166 else if (!strcmp (default_arch, "i386"))
5167 set_code_flag (CODE_32BIT);
5168 else
5169 as_fatal (_("Unknown architecture"));
252b5132
RH		 5170 switch (OUTPUT_FLAVOR)
5171 {
4c63da97
AM		 5172#ifdef OBJ_MAYBE_AOUT
5173 case bfd_target_aout_flavour:
47926f60 5174 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5175#endif
5176#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5177 case bfd_target_coff_flavour:
5178 return "coff-i386";
4c63da97 5179#endif
3e73aa7c 5180#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5181 case bfd_target_elf_flavour:
3e73aa7c 5182 {
e5cb08ac
KH		 5183 if (flag_code == CODE_64BIT)
5184 use_rela_relocations = 1;
4ada7262 5185 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5186 }
4c63da97 5187#endif
252b5132
RH		 5188 default:
5189 abort ();
5190 return NULL;
5191 }
5192}
5193
47926f60 5194#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5195
5196#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5197void i386_elf_emit_arch_note ()
5198{
5199 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5200 && cpu_arch_name != NULL)
5201 {
5202 char *p;
5203 asection *seg = now_seg;
5204 subsegT subseg = now_subseg;
5205 Elf_Internal_Note i_note;
5206 Elf_External_Note e_note;
5207 asection *note_secp;
5208 int len;
5209
5210 /* Create the .note section. */
5211 note_secp = subseg_new (".note", 0);
5212 bfd_set_section_flags (stdoutput,
5213 note_secp,
5214 SEC_HAS_CONTENTS | SEC_READONLY);
5215
5216 /* Process the arch string. */
5217 len = strlen (cpu_arch_name);
5218
5219 i_note.namesz = len + 1;
5220 i_note.descsz = 0;
5221 i_note.type = NT_ARCH;
5222 p = frag_more (sizeof (e_note.namesz));
5223 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5224 p = frag_more (sizeof (e_note.descsz));
5225 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5226 p = frag_more (sizeof (e_note.type));
5227 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5228 p = frag_more (len + 1);
5229 strcpy (p, cpu_arch_name);
5230
5231 frag_align (2, 0, 0);
5232
5233 subseg_set (seg, subseg);
5234 }
5235}
5236#endif
252b5132 5237\f
252b5132
RH		 5238symbolS *
5239md_undefined_symbol (name)
5240 char *name;
5241{
18dc2407
ILT		 5242 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5243 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5244 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5245 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5246 {
5247 if (!GOT_symbol)
5248 {
5249 if (symbol_find (name))
5250 as_bad (_("GOT already in symbol table"));
5251 GOT_symbol = symbol_new (name, undefined_section,
5252 (valueT) 0, &zero_address_frag);
5253 };
5254 return GOT_symbol;
5255 }
252b5132
RH		 5256 return 0;
5257}
5258
5259/* Round up a section size to the appropriate boundary. */
47926f60 5260
252b5132
RH		 5261valueT
5262md_section_align (segment, size)
ab9da554 5263 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5264 valueT size;
5265{
4c63da97
AM		 5266#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5267 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5268 {
5269 /* For a.out, force the section size to be aligned. If we don't do
5270 this, BFD will align it for us, but it will not write out the
5271 final bytes of the section. This may be a bug in BFD, but it is
5272 easier to fix it here since that is how the other a.out targets
5273 work. */
5274 int align;
5275
5276 align = bfd_get_section_alignment (stdoutput, segment);
5277 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5278 }
252b5132
RH		 5279#endif
5280
5281 return size;
5282}
5283
5284/* On the i386, PC-relative offsets are relative to the start of the
5285 next instruction. That is, the address of the offset, plus its
5286 size, since the offset is always the last part of the insn. */
5287
5288long
5289md_pcrel_from (fixP)
5290 fixS *fixP;
5291{
5292 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5293}
5294
5295#ifndef I386COFF
5296
5297static void
5298s_bss (ignore)
ab9da554 5299 int ignore ATTRIBUTE_UNUSED;
252b5132 5300{
29b0f896 5301 int temp;
252b5132
RH		 5302
5303 temp = get_absolute_expression ();
5304 subseg_set (bss_section, (subsegT) temp);
5305 demand_empty_rest_of_line ();
5306}
5307
5308#endif
5309
252b5132
RH		 5310void
5311i386_validate_fix (fixp)
5312 fixS *fixp;
5313{
5314 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5315 {
3e73aa7c 5316 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5317 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5318 {
5319 if (flag_code != CODE_64BIT)
5320 abort ();
5321 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5322 }
5323 else
5324 {
5325 if (flag_code == CODE_64BIT)
5326 abort ();
5327 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5328 }
252b5132
RH		 5329 fixp->fx_subsy = 0;
5330 }
5331}
5332
252b5132
RH		 5333arelent *
5334tc_gen_reloc (section, fixp)
ab9da554 5335 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5336 fixS *fixp;
5337{
5338 arelent *rel;
5339 bfd_reloc_code_real_type code;
5340
5341 switch (fixp->fx_r_type)
5342 {
3e73aa7c
JH		 5343 case BFD_RELOC_X86_64_PLT32:
5344 case BFD_RELOC_X86_64_GOT32:
5345 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5346 case BFD_RELOC_386_PLT32:
5347 case BFD_RELOC_386_GOT32:
5348 case BFD_RELOC_386_GOTOFF:
5349 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5350 case BFD_RELOC_386_TLS_GD:
5351 case BFD_RELOC_386_TLS_LDM:
5352 case BFD_RELOC_386_TLS_LDO_32:
5353 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5354 case BFD_RELOC_386_TLS_IE:
5355 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5356 case BFD_RELOC_386_TLS_LE_32:
5357 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5358 case BFD_RELOC_X86_64_32S:
bffbf940
JJ		 5359 case BFD_RELOC_X86_64_TLSGD:
5360 case BFD_RELOC_X86_64_TLSLD:
5361 case BFD_RELOC_X86_64_DTPOFF32:
5362 case BFD_RELOC_X86_64_GOTTPOFF:
5363 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5364 case BFD_RELOC_RVA:
5365 case BFD_RELOC_VTABLE_ENTRY:
5366 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5367#ifdef TE_PE
5368 case BFD_RELOC_32_SECREL:
5369#endif
252b5132
RH		 5370 code = fixp->fx_r_type;
5371 break;
5372 default:
93382f6d 5373 if (fixp->fx_pcrel)
252b5132 5374 {
93382f6d
AM		 5375 switch (fixp->fx_size)
5376 {
5377 default:
b091f402
AM		 5378 as_bad_where (fixp->fx_file, fixp->fx_line,
5379 _("can not do %d byte pc-relative relocation"),
5380 fixp->fx_size);
93382f6d
AM		 5381 code = BFD_RELOC_32_PCREL;
5382 break;
5383 case 1: code = BFD_RELOC_8_PCREL; break;
5384 case 2: code = BFD_RELOC_16_PCREL; break;
5385 case 4: code = BFD_RELOC_32_PCREL; break;
5386 }
5387 }
5388 else
5389 {
5390 switch (fixp->fx_size)
5391 {
5392 default:
b091f402
AM		 5393 as_bad_where (fixp->fx_file, fixp->fx_line,
5394 _("can not do %d byte relocation"),
5395 fixp->fx_size);
93382f6d
AM		 5396 code = BFD_RELOC_32;
5397 break;
5398 case 1: code = BFD_RELOC_8; break;
5399 case 2: code = BFD_RELOC_16; break;
5400 case 4: code = BFD_RELOC_32; break;
937149dd 5401#ifdef BFD64
3e73aa7c 5402 case 8: code = BFD_RELOC_64; break;
937149dd 5403#endif
93382f6d 5404 }
252b5132
RH		 5405 }
5406 break;
5407 }
252b5132
RH		 5408
5409 if (code == BFD_RELOC_32
5410 && GOT_symbol
5411 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5412 {
5413 /* We don't support GOTPC on 64bit targets. */
5414 if (flag_code == CODE_64BIT)
bfb32b52 5415 abort ();
3e73aa7c
JH		 5416 code = BFD_RELOC_386_GOTPC;
5417 }
252b5132
RH		 5418
5419 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5420 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5421 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5422
5423 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5424
3e73aa7c
JH		 5425 if (!use_rela_relocations)
5426 {
5427 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5428 vtable entry to be used in the relocation's section offset. */
5429 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5430 rel->address = fixp->fx_offset;
252b5132 5431
c6682705 5432 rel->addend = 0;
3e73aa7c
JH		 5433 }
5434 /* Use the rela in 64bit mode. */
252b5132 5435 else
3e73aa7c 5436 {
062cd5e7
AS		 5437 if (!fixp->fx_pcrel)
5438 rel->addend = fixp->fx_offset;
5439 else
5440 switch (code)
5441 {
5442 case BFD_RELOC_X86_64_PLT32:
5443 case BFD_RELOC_X86_64_GOT32:
5444 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5445 case BFD_RELOC_X86_64_TLSGD:
5446 case BFD_RELOC_X86_64_TLSLD:
5447 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5448 rel->addend = fixp->fx_offset - fixp->fx_size;
5449 break;
5450 default:
5451 rel->addend = (section->vma
5452 - fixp->fx_size
5453 + fixp->fx_addnumber
5454 + md_pcrel_from (fixp));
5455 break;
5456 }
3e73aa7c
JH		 5457 }
5458
252b5132
RH		 5459 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5460 if (rel->howto == NULL)
5461 {
5462 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5463 _("cannot represent relocation type %s"),
252b5132
RH		 5464 bfd_get_reloc_code_name (code));
5465 /* Set howto to a garbage value so that we can keep going. */
5466 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5467 assert (rel->howto != NULL);
5468 }
5469
5470 return rel;
5471}
5472
64a0c779
DN		 5473\f
5474/* Parse operands using Intel syntax. This implements a recursive descent
5475 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5476 Programmer's Guide.
5477
5478 FIXME: We do not recognize the full operand grammar defined in the MASM
5479 documentation. In particular, all the structure/union and
5480 high-level macro operands are missing.
5481
5482 Uppercase words are terminals, lower case words are non-terminals.
5483 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5484 bars '|' denote choices. Most grammar productions are implemented in
5485 functions called 'intel_<production>'.
5486
5487 Initial production is 'expr'.
5488
9306ca4a 5489 addOp + | -
64a0c779
DN		 5490
5491 alpha [a-zA-Z]
5492
9306ca4a
JB		 5493 binOp & | AND | \| | OR | ^ | XOR
5494
64a0c779
DN		 5495 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5496
5497 constant digits [[ radixOverride ]]
5498
9306ca4a 5499 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5500
5501 digits decdigit
b77a7acd
AJ		 5502 | digits decdigit
5503 | digits hexdigit
64a0c779
DN		 5504
5505 decdigit [0-9]
5506
9306ca4a
JB		 5507 e04 e04 addOp e05
5508 | e05
5509
5510 e05 e05 binOp e06
b77a7acd 5511 | e06
64a0c779
DN		 5512
5513 e06 e06 mulOp e09
b77a7acd 5514 | e09
64a0c779
DN		 5515
5516 e09 OFFSET e10
9306ca4a
JB		 5517 | ~ e10
5518 | NOT e10
64a0c779
DN		 5519 | e09 PTR e10
5520 | e09 : e10
5521 | e10
5522
5523 e10 e10 [ expr ]
b77a7acd 5524 | e11
64a0c779
DN		 5525
5526 e11 ( expr )
b77a7acd 5527 | [ expr ]
64a0c779
DN		 5528 | constant
5529 | dataType
5530 | id
5531 | $
5532 | register
5533
9306ca4a
JB		 5534 => expr SHORT e04
5535 | e04
64a0c779
DN		 5536
5537 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5538 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5539
5540 hexdigit a | b | c | d | e | f
b77a7acd 5541 | A | B | C | D | E | F
64a0c779
DN		 5542
5543 id alpha
b77a7acd 5544 | id alpha
64a0c779
DN		 5545 | id decdigit
5546
9306ca4a 5547 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5548
5549 quote " | '
5550
5551 register specialRegister
b77a7acd 5552 | gpRegister
64a0c779
DN		 5553 | byteRegister
5554
5555 segmentRegister CS | DS | ES | FS | GS | SS
5556
9306ca4a 5557 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5558 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5559 | TR3 | TR4 | TR5 | TR6 | TR7
5560
64a0c779
DN		 5561 We simplify the grammar in obvious places (e.g., register parsing is
5562 done by calling parse_register) and eliminate immediate left recursion
5563 to implement a recursive-descent parser.
5564
9306ca4a
JB		 5565 expr SHORT e04
5566 | e04
5567
5568 e04 e05 e04'
5569
5570 e04' addOp e05 e04'
5571 | Empty
64a0c779
DN		 5572
5573 e05 e06 e05'
5574
9306ca4a 5575 e05' binOp e06 e05'
b77a7acd 5576 | Empty
64a0c779
DN		 5577
5578 e06 e09 e06'
5579
5580 e06' mulOp e09 e06'
b77a7acd 5581 | Empty
64a0c779
DN		 5582
5583 e09 OFFSET e10 e09'
9306ca4a
JB		 5584 | ~ e10
5585 | NOT e10
b77a7acd 5586 | e10 e09'
64a0c779
DN		 5587
5588 e09' PTR e10 e09'
b77a7acd 5589 | : e10 e09'
64a0c779
DN		 5590 | Empty
5591
5592 e10 e11 e10'
5593
5594 e10' [ expr ] e10'
b77a7acd 5595 | Empty
64a0c779
DN		 5596
5597 e11 ( expr )
b77a7acd 5598 | [ expr ]
64a0c779
DN		 5599 | BYTE
5600 | WORD
5601 | DWORD
9306ca4a 5602 | FWORD
64a0c779 5603 | QWORD
9306ca4a
JB		 5604 | TBYTE
5605 | OWORD
5606 | XMMWORD
64a0c779
DN		 5607 | .
5608 | $
5609 | register
5610 | id
5611 | constant */
5612
5613/* Parsing structure for the intel syntax parser. Used to implement the
5614 semantic actions for the operand grammar. */
5615struct intel_parser_s
5616 {
5617 char *op_string; /* The string being parsed. */
5618 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5619 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5620 int is_mem; /* 1 if operand is memory reference. */
5621 const reg_entry *reg; /* Last register reference found. */
5622 char *disp; /* Displacement string being built. */
5623 };
5624
5625static struct intel_parser_s intel_parser;
5626
5627/* Token structure for parsing intel syntax. */
5628struct intel_token
5629 {
5630 int code; /* Token code. */
5631 const reg_entry *reg; /* Register entry for register tokens. */
5632 char *str; /* String representation. */
5633 };
5634
5635static struct intel_token cur_token, prev_token;
5636
50705ef4
AM		 5637/* Token codes for the intel parser. Since T_SHORT is already used
5638 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5639#define T_NIL -1
5640#define T_CONST 1
5641#define T_REG 2
5642#define T_BYTE 3
5643#define T_WORD 4
9306ca4a
JB		 5644#define T_DWORD 5
5645#define T_FWORD 6
5646#define T_QWORD 7
5647#define T_TBYTE 8
5648#define T_XMMWORD 9
50705ef4 5649#undef T_SHORT
9306ca4a
JB		 5650#define T_SHORT 10
5651#define T_OFFSET 11
5652#define T_PTR 12
5653#define T_ID 13
5654#define T_SHL 14
5655#define T_SHR 15
64a0c779
DN		 5656
5657/* Prototypes for intel parser functions. */
5658static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5659static void intel_get_token PARAMS ((void));
5660static void intel_putback_token PARAMS ((void));
5661static int intel_expr PARAMS ((void));
9306ca4a
JB		 5662static int intel_e04 PARAMS ((void));
5663static int intel_e04_1 PARAMS ((void));
cce0cbdc
DN		 5664static int intel_e05 PARAMS ((void));
5665static int intel_e05_1 PARAMS ((void));
5666static int intel_e06 PARAMS ((void));
5667static int intel_e06_1 PARAMS ((void));
5668static int intel_e09 PARAMS ((void));
5669static int intel_e09_1 PARAMS ((void));
5670static int intel_e10 PARAMS ((void));
5671static int intel_e10_1 PARAMS ((void));
5672static int intel_e11 PARAMS ((void));
64a0c779 5673
64a0c779
DN		 5674static int
5675i386_intel_operand (operand_string, got_a_float)
5676 char *operand_string;
5677 int got_a_float;
5678{
5679 int ret;
5680 char *p;
5681
5682 /* Initialize token holders. */
5683 cur_token.code = prev_token.code = T_NIL;
5684 cur_token.reg = prev_token.reg = NULL;
5685 cur_token.str = prev_token.str = NULL;
5686
5687 /* Initialize parser structure. */
e5cb08ac 5688 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5689 if (p == NULL)
5690 abort ();
5691 strcpy (intel_parser.op_string, operand_string);
5692 intel_parser.got_a_float = got_a_float;
5693 intel_parser.op_modifier = -1;
5694 intel_parser.is_mem = 0;
5695 intel_parser.reg = NULL;
e5cb08ac 5696 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5697 if (intel_parser.disp == NULL)
5698 abort ();
5699 intel_parser.disp[0] = '\0';
5700
5701 /* Read the first token and start the parser. */
5702 intel_get_token ();
5703 ret = intel_expr ();
5704
5705 if (ret)
5706 {
9306ca4a
JB		 5707 if (cur_token.code != T_NIL)
5708 {
5709 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5710 current_templates->start->name, cur_token.str);
5711 ret = 0;
5712 }
64a0c779
DN		 5713 /* If we found a memory reference, hand it over to i386_displacement
5714 to fill in the rest of the operand fields. */
9306ca4a 5715 else if (intel_parser.is_mem)
64a0c779
DN		 5716 {
5717 if ((i.mem_operands == 1
5718 && (current_templates->start->opcode_modifier & IsString) == 0)
5719 || i.mem_operands == 2)
5720 {
5721 as_bad (_("too many memory references for '%s'"),
5722 current_templates->start->name);
5723 ret = 0;
5724 }
5725 else
5726 {
5727 char *s = intel_parser.disp;
5728 i.mem_operands++;
5729
5730 /* Add the displacement expression. */
5731 if (*s != '\0')
a4622f40
AM		 5732 ret = i386_displacement (s, s + strlen (s));
5733 if (ret)
5734 ret = i386_index_check (operand_string);
64a0c779
DN		 5735 }
5736 }
5737
5738 /* Constant and OFFSET expressions are handled by i386_immediate. */
9306ca4a 5739 else if (intel_parser.op_modifier == T_OFFSET
64a0c779
DN		 5740 || intel_parser.reg == NULL)
5741 ret = i386_immediate (intel_parser.disp);
5742 }
5743
5744 free (p);
5745 free (intel_parser.disp);
5746
5747 return ret;
5748}
5749
9306ca4a
JB		 5750/* expr SHORT e04
5751 | e04 */
64a0c779
DN		 5752static int
5753intel_expr ()
5754{
9306ca4a 5755 /* expr SHORT e04 */
64a0c779
DN		 5756 if (cur_token.code == T_SHORT)
5757 {
9306ca4a 5758 intel_parser.op_modifier = T_SHORT;
64a0c779
DN		 5759 intel_match_token (T_SHORT);
5760
9306ca4a
JB		 5761 return (intel_e04 ());
5762 }
5763
5764 /* expr e04 */
5765 else
5766 return intel_e04 ();
5767}
5768
5769/* e04 e06 e04'
5770
5771 e04' addOp e06 e04'
5772 | Empty */
5773static int
5774intel_e04 ()
5775{
5776 return (intel_e05 () && intel_e04_1 ());
5777}
5778
5779static int
5780intel_e04_1 ()
5781{
5782 /* e04' addOp e05 e04' */
5783 if (cur_token.code == '+' || cur_token.code == '-')
5784 {
5785 char str[2];
5786
5787 str[0] = cur_token.code;
5788 str[1] = 0;
5789 strcat (intel_parser.disp, str);
5790 intel_match_token (cur_token.code);
5791
5792 return (intel_e05 () && intel_e04_1 ());
64a0c779
DN		 5793 }
5794
9306ca4a 5795 /* e04' Empty */
64a0c779 5796 else
9306ca4a 5797 return 1;
64a0c779
DN		 5798}
5799
64a0c779
DN		 5800/* e05 e06 e05'
5801
9306ca4a 5802 e05' binOp e06 e05'
64a0c779
DN		 5803 | Empty */
5804static int
5805intel_e05 ()
5806{
5807 return (intel_e06 () && intel_e05_1 ());
5808}
5809
5810static int
5811intel_e05_1 ()
5812{
9306ca4a
JB		 5813 /* e05' binOp e06 e05' */
5814 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
64a0c779 5815 {
9306ca4a
JB		 5816 char str[2];
5817
5818 str[0] = cur_token.code;
5819 str[1] = 0;
5820 strcat (intel_parser.disp, str);
64a0c779
DN		 5821 intel_match_token (cur_token.code);
5822
5823 return (intel_e06 () && intel_e05_1 ());
5824 }
5825
5826 /* e05' Empty */
5827 else
5828 return 1;
4a1805b1 5829}
64a0c779
DN		 5830
5831/* e06 e09 e06'
5832
5833 e06' mulOp e09 e06'
b77a7acd 5834 | Empty */
64a0c779
DN		 5835static int
5836intel_e06 ()
5837{
5838 return (intel_e09 () && intel_e06_1 ());
5839}
5840
5841static int
5842intel_e06_1 ()
5843{
5844 /* e06' mulOp e09 e06' */
9306ca4a 5845 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
64a0c779 5846 {
9306ca4a
JB		 5847 char str[2];
5848
5849 str[0] = cur_token.code;
5850 str[1] = 0;
5851 strcat (intel_parser.disp, str);
5852 intel_match_token (cur_token.code);
5853
5854 return (intel_e09 () && intel_e06_1 ());
5855 }
5856 else if (cur_token.code == T_SHL)
5857 {
5858 strcat (intel_parser.disp, "<<");
5859 intel_match_token (cur_token.code);
5860
5861 return (intel_e09 () && intel_e06_1 ());
5862 }
5863 else if (cur_token.code == T_SHR)
5864 {
5865 strcat (intel_parser.disp, ">>");
64a0c779
DN		 5866 intel_match_token (cur_token.code);
5867
5868 return (intel_e09 () && intel_e06_1 ());
5869 }
4a1805b1 5870
64a0c779 5871 /* e06' Empty */
4a1805b1 5872 else
64a0c779
DN		 5873 return 1;
5874}
5875
64a0c779 5876/* e09 OFFSET e10 e09'
b77a7acd 5877 | e10 e09'
64a0c779 5878
9306ca4a
JB		 5879 e09 ~ e10 e09'
5880 | NOT e10 e09'
5881 | e10 e09'
5882
64a0c779 5883 e09' PTR e10 e09'
b77a7acd 5884 | : e10 e09'
64a0c779
DN		 5885 | Empty */
5886static int
5887intel_e09 ()
5888{
5889 /* e09 OFFSET e10 e09' */
5890 if (cur_token.code == T_OFFSET)
5891 {
5892 intel_parser.is_mem = 0;
9306ca4a 5893 intel_parser.op_modifier = T_OFFSET;
64a0c779
DN		 5894 intel_match_token (T_OFFSET);
5895
5896 return (intel_e10 () && intel_e09_1 ());
5897 }
5898
9306ca4a
JB		 5899 /* e09 NOT e10 e09' */
5900 else if (cur_token.code == '~')
5901 {
5902 char str[2];
5903
5904 str[0] = cur_token.code;
5905 str[1] = 0;
5906 strcat (intel_parser.disp, str);
5907 intel_match_token (cur_token.code);
5908
5909 return (intel_e10 () && intel_e09_1 ());
5910 }
5911
64a0c779
DN		 5912 /* e09 e10 e09' */
5913 else
5914 return (intel_e10 () && intel_e09_1 ());
5915}
5916
5917static int
5918intel_e09_1 ()
5919{
5920 /* e09' PTR e10 e09' */
5921 if (cur_token.code == T_PTR)
5922 {
9306ca4a
JB		 5923 char suffix;
5924
64a0c779 5925 if (prev_token.code == T_BYTE)
9306ca4a 5926 suffix = BYTE_MNEM_SUFFIX;
64a0c779
DN		 5927
5928 else if (prev_token.code == T_WORD)
5929 {
9306ca4a
JB		 5930 if (current_templates->start->name[0] == 'l'
5931 && current_templates->start->name[2] == 's'
5932 && current_templates->start->name[3] == 0)
5933 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
5934 else if (intel_parser.got_a_float == 2) /* "fi..." */
5935 suffix = SHORT_MNEM_SUFFIX;
64a0c779 5936 else
9306ca4a 5937 suffix = WORD_MNEM_SUFFIX;
64a0c779
DN		 5938 }
5939
5940 else if (prev_token.code == T_DWORD)
5941 {
9306ca4a
JB		 5942 if (current_templates->start->name[0] == 'l'
5943 && current_templates->start->name[2] == 's'
5944 && current_templates->start->name[3] == 0)
5945 suffix = WORD_MNEM_SUFFIX;
5946 else if (flag_code == CODE_16BIT
5947 && (current_templates->start->opcode_modifier
5948 & (Jump|JumpDword|JumpInterSegment)))
5949 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5950 else if (intel_parser.got_a_float == 1) /* "f..." */
5951 suffix = SHORT_MNEM_SUFFIX;
64a0c779 5952 else
9306ca4a
JB		 5953 suffix = LONG_MNEM_SUFFIX;
5954 }
5955
5956 else if (prev_token.code == T_FWORD)
5957 {
5958 if (current_templates->start->name[0] == 'l'
5959 && current_templates->start->name[2] == 's'
5960 && current_templates->start->name[3] == 0)
5961 suffix = LONG_MNEM_SUFFIX;
5962 else if (!intel_parser.got_a_float)
5963 {
5964 if (flag_code == CODE_16BIT)
5965 add_prefix (DATA_PREFIX_OPCODE);
5966 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5967 }
5968 else
5969 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
64a0c779
DN		 5970 }
5971
5972 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5973 {
5974 if (intel_parser.got_a_float == 1) /* "f..." */
9306ca4a 5975 suffix = LONG_MNEM_SUFFIX;
f16b83df 5976 else
9306ca4a 5977 suffix = QWORD_MNEM_SUFFIX;
f16b83df 5978 }
64a0c779 5979
9306ca4a
JB		 5980 else if (prev_token.code == T_TBYTE)
5981 {
5982 if (intel_parser.got_a_float == 1)
5983 suffix = LONG_DOUBLE_MNEM_SUFFIX;
5984 else
5985 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
5986 }
5987
5988 else if (prev_token.code == T_XMMWORD)
5989 {
5990 /* XXX ignored for now, but accepted since gcc uses it */
5991 suffix = 0;
5992 }
64a0c779
DN		 5993
5994 else
5995 {
0477af35 5996 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
64a0c779
DN		 5997 return 0;
5998 }
5999
9306ca4a
JB		 6000 if (current_templates->start->base_opcode == 0x8d /* lea */)
6001 ;
6002 else if (!i.suffix)
6003 i.suffix = suffix;
6004 else if (i.suffix != suffix)
6005 {
6006 as_bad (_("Conflicting operand modifiers"));
6007 return 0;
6008 }
6009
64a0c779
DN		 6010 intel_match_token (T_PTR);
6011
6012 return (intel_e10 () && intel_e09_1 ());
6013 }
6014
6015 /* e09 : e10 e09' */
6016 else if (cur_token.code == ':')
6017 {
21d6c4af
DN		 6018 /* Mark as a memory operand only if it's not already known to be an
6019 offset expression. */
9306ca4a 6020 if (intel_parser.op_modifier != T_OFFSET)
21d6c4af 6021 intel_parser.is_mem = 1;
64a0c779
DN		 6022
6023 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
6024 }
6025
6026 /* e09' Empty */
6027 else
6028 return 1;
6029}
6030
6031/* e10 e11 e10'
6032
6033 e10' [ expr ] e10'
b77a7acd 6034 | Empty */
64a0c779
DN		 6035static int
6036intel_e10 ()
6037{
6038 return (intel_e11 () && intel_e10_1 ());
6039}
6040
6041static int
6042intel_e10_1 ()
6043{
6044 /* e10' [ expr ] e10' */
6045 if (cur_token.code == '[')
6046 {
6047 intel_match_token ('[');
21d6c4af
DN		 6048
6049 /* Mark as a memory operand only if it's not already known to be an
6050 offset expression. If it's an offset expression, we need to keep
6051 the brace in. */
9306ca4a 6052 if (intel_parser.op_modifier != T_OFFSET)
21d6c4af
DN		 6053 intel_parser.is_mem = 1;
6054 else
6055 strcat (intel_parser.disp, "[");
4a1805b1 6056
64a0c779 6057 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 6058 if (*intel_parser.disp != '\0'
6059 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 6060 strcat (intel_parser.disp, "+");
6061
21d6c4af
DN		 6062 if (intel_expr () && intel_match_token (']'))
6063 {
6064 /* Preserve brackets when the operand is an offset expression. */
9306ca4a 6065 if (intel_parser.op_modifier == T_OFFSET)
21d6c4af
DN		 6066 strcat (intel_parser.disp, "]");
6067
6068 return intel_e10_1 ();
6069 }
6070 else
6071 return 0;
64a0c779
DN		 6072 }
6073
6074 /* e10' Empty */
6075 else
6076 return 1;
6077}
6078
64a0c779 6079/* e11 ( expr )
b77a7acd 6080 | [ expr ]
64a0c779
DN		 6081 | BYTE
6082 | WORD
6083 | DWORD
9306ca4a 6084 | FWORD
64a0c779 6085 | QWORD
9306ca4a
JB		 6086 | TBYTE
6087 | OWORD
6088 | XMMWORD
4a1805b1 6089 | $
64a0c779
DN		 6090 | .
6091 | register
6092 | id
6093 | constant */
6094static int
6095intel_e11 ()
6096{
6097 /* e11 ( expr ) */
6098 if (cur_token.code == '(')
6099 {
6100 intel_match_token ('(');
6101 strcat (intel_parser.disp, "(");
6102
6103 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6104 {
6105 strcat (intel_parser.disp, ")");
6106 return 1;
6107 }
64a0c779
DN		 6108 else
6109 return 0;
6110 }
6111
6112 /* e11 [ expr ] */
6113 else if (cur_token.code == '[')
6114 {
6115 intel_match_token ('[');
21d6c4af
DN		 6116
6117 /* Mark as a memory operand only if it's not already known to be an
6118 offset expression. If it's an offset expression, we need to keep
6119 the brace in. */
9306ca4a 6120 if (intel_parser.op_modifier != T_OFFSET)
21d6c4af
DN		 6121 intel_parser.is_mem = 1;
6122 else
6123 strcat (intel_parser.disp, "[");
4a1805b1 6124
64a0c779 6125 /* Operands for jump/call inside brackets denote absolute addresses. */
9306ca4a
JB		 6126 if (current_templates->start->opcode_modifier
6127 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6128 i.types[this_operand] |= JumpAbsolute;
6129
6130 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 6131 if (*intel_parser.disp != '\0'
6132 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 6133 strcat (intel_parser.disp, "+");
6134
21d6c4af
DN		 6135 if (intel_expr () && intel_match_token (']'))
6136 {
6137 /* Preserve brackets when the operand is an offset expression. */
9306ca4a 6138 if (intel_parser.op_modifier == T_OFFSET)
21d6c4af
DN		 6139 strcat (intel_parser.disp, "]");
6140
6141 return 1;
6142 }
6143 else
6144 return 0;
64a0c779
DN		 6145 }
6146
4a1805b1 6147 /* e11 BYTE
64a0c779
DN		 6148 | WORD
6149 | DWORD
9306ca4a 6150 | FWORD
64a0c779 6151 | QWORD
9306ca4a
JB		 6152 | TBYTE
6153 | OWORD
6154 | XMMWORD */
64a0c779
DN		 6155 else if (cur_token.code == T_BYTE
6156 || cur_token.code == T_WORD
6157 || cur_token.code == T_DWORD
9306ca4a 6158 || cur_token.code == T_FWORD
64a0c779 6159 || cur_token.code == T_QWORD
9306ca4a
JB		 6160 || cur_token.code == T_TBYTE
6161 || cur_token.code == T_XMMWORD)
64a0c779
DN		 6162 {
6163 intel_match_token (cur_token.code);
6164
167c3097
JB		 6165 if (cur_token.code != T_PTR)
6166 {
6167 /* It must have been an identifier; add it to the displacement string. */
6168 strcat (intel_parser.disp, prev_token.str);
6169
6170 /* The identifier represents a memory reference only if it's not
6171 preceded by an offset modifier and if it's not an equate. */
6172 if (intel_parser.op_modifier != T_OFFSET)
6173 {
6174 symbolS *symbolP;
6175
6176 symbolP = symbol_find(prev_token.str);
6177 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6178 intel_parser.is_mem = 1;
6179 }
6180 }
6181
64a0c779
DN		 6182 return 1;
6183 }
6184
6185 /* e11 $
6186 | . */
9306ca4a 6187 else if (cur_token.code == '.')
64a0c779
DN		 6188 {
6189 strcat (intel_parser.disp, cur_token.str);
6190 intel_match_token (cur_token.code);
21d6c4af
DN		 6191
6192 /* Mark as a memory operand only if it's not already known to be an
6193 offset expression. */
9306ca4a 6194 if (intel_parser.op_modifier != T_OFFSET)
21d6c4af 6195 intel_parser.is_mem = 1;
64a0c779
DN		 6196
6197 return 1;
6198 }
6199
6200 /* e11 register */
6201 else if (cur_token.code == T_REG)
6202 {
6203 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6204
6205 intel_match_token (T_REG);
6206
6207 /* Check for segment change. */
6208 if (cur_token.code == ':')
6209 {
6210 if (reg->reg_type & (SReg2 | SReg3))
6211 {
6212 switch (reg->reg_num)
6213 {
6214 case 0:
6215 i.seg[i.mem_operands] = &es;
6216 break;
6217 case 1:
6218 i.seg[i.mem_operands] = &cs;
6219 break;
6220 case 2:
6221 i.seg[i.mem_operands] = &ss;
6222 break;
6223 case 3:
6224 i.seg[i.mem_operands] = &ds;
6225 break;
6226 case 4:
6227 i.seg[i.mem_operands] = &fs;
6228 break;
6229 case 5:
6230 i.seg[i.mem_operands] = &gs;
6231 break;
6232 }
6233 }
6234 else
6235 {
6236 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6237 return 0;
6238 }
6239 }
6240
6241 /* Not a segment register. Check for register scaling. */
6242 else if (cur_token.code == '*')
6243 {
6244 if (!intel_parser.is_mem)
6245 {
6246 as_bad (_("Register scaling only allowed in memory operands."));
6247 return 0;
6248 }
6249
4a1805b1 6250 /* What follows must be a valid scale. */
64a0c779
DN		 6251 if (intel_match_token ('*')
6252 && strchr ("01248", *cur_token.str))
6253 {
6254 i.index_reg = reg;
6255 i.types[this_operand] |= BaseIndex;
6256
6257 /* Set the scale after setting the register (otherwise,
6258 i386_scale will complain) */
6259 i386_scale (cur_token.str);
6260 intel_match_token (T_CONST);
6261 }
6262 else
6263 {
6264 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6265 cur_token.str);
6266 return 0;
6267 }
6268 }
6269
6270 /* No scaling. If this is a memory operand, the register is either a
6271 base register (first occurrence) or an index register (second
6272 occurrence). */
6273 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
6274 {
6275 if (i.base_reg && i.index_reg)
6276 {
0477af35 6277 as_bad (_("Too many register references in memory operand."));
64a0c779
DN		 6278 return 0;
6279 }
6280
6281 if (i.base_reg == NULL)
6282 i.base_reg = reg;
6283 else
6284 i.index_reg = reg;
6285
6286 i.types[this_operand] |= BaseIndex;
6287 }
6288
6289 /* Offset modifier. Add the register to the displacement string to be
6290 parsed as an immediate expression after we're done. */
9306ca4a 6291 else if (intel_parser.op_modifier == T_OFFSET)
64a0c779 6292 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 6293
64a0c779
DN		 6294 /* It's neither base nor index nor offset. */
6295 else
6296 {
6297 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6298 i.op[this_operand].regs = reg;
6299 i.reg_operands++;
6300 }
6301
6302 /* Since registers are not part of the displacement string (except
6303 when we're parsing offset operands), we may need to remove any
6304 preceding '+' from the displacement string. */
6305 if (*intel_parser.disp != '\0'
9306ca4a 6306 && intel_parser.op_modifier != T_OFFSET)
64a0c779
DN		 6307 {
6308 char *s = intel_parser.disp;
6309 s += strlen (s) - 1;
6310 if (*s == '+')
6311 *s = '\0';
6312 }
6313
6314 return 1;
6315 }
4a1805b1 6316
64a0c779
DN		 6317 /* e11 id */
6318 else if (cur_token.code == T_ID)
6319 {
6320 /* Add the identifier to the displacement string. */
6321 strcat (intel_parser.disp, cur_token.str);
64a0c779
DN		 6322
6323 /* The identifier represents a memory reference only if it's not
9306ca4a
JB		 6324 preceded by an offset modifier and if it's not an equate. */
6325 if (intel_parser.op_modifier != T_OFFSET)
6326 {
6327 symbolS *symbolP;
6328
6329 symbolP = symbol_find(cur_token.str);
6330 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6331 intel_parser.is_mem = 1;
6332 }
64a0c779 6333
9306ca4a 6334 intel_match_token (T_ID);
64a0c779
DN		 6335 return 1;
6336 }
6337
6338 /* e11 constant */
6339 else if (cur_token.code == T_CONST
e5cb08ac 6340 || cur_token.code == '-'
64a0c779
DN		 6341 || cur_token.code == '+')
6342 {
6343 char *save_str;
6344
6345 /* Allow constants that start with `+' or `-'. */
6346 if (cur_token.code == '-' || cur_token.code == '+')
6347 {
6348 strcat (intel_parser.disp, cur_token.str);
6349 intel_match_token (cur_token.code);
6350 if (cur_token.code != T_CONST)
6351 {
0477af35 6352 as_bad (_("Syntax error. Expecting a constant. Got `%s'."),
64a0c779
DN		 6353 cur_token.str);
6354 return 0;
6355 }
6356 }
6357
e5cb08ac 6358 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6359 if (save_str == NULL)
bc805888 6360 abort ();
64a0c779
DN		 6361 strcpy (save_str, cur_token.str);
6362
6363 /* Get the next token to check for register scaling. */
6364 intel_match_token (cur_token.code);
6365
6366 /* Check if this constant is a scaling factor for an index register. */
6367 if (cur_token.code == '*')
6368 {
6369 if (intel_match_token ('*') && cur_token.code == T_REG)
6370 {
6371 if (!intel_parser.is_mem)
6372 {
6373 as_bad (_("Register scaling only allowed in memory operands."));
6374 return 0;
6375 }
6376
4a1805b1 6377 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6378 a valid scale. */
6379 if (strchr ("01248", *save_str))
6380 {
6381 i.index_reg = cur_token.reg;
6382 i.types[this_operand] |= BaseIndex;
6383
6384 /* Set the scale after setting the register (otherwise,
6385 i386_scale will complain) */
6386 i386_scale (save_str);
6387 intel_match_token (T_REG);
6388
6389 /* Since registers are not part of the displacement
6390 string, we may need to remove any preceding '+' from
6391 the displacement string. */
6392 if (*intel_parser.disp != '\0')
6393 {
6394 char *s = intel_parser.disp;
6395 s += strlen (s) - 1;
6396 if (*s == '+')
6397 *s = '\0';
6398 }
6399
6400 free (save_str);
6401
6402 return 1;
6403 }
6404 else
6405 return 0;
6406 }
6407
6408 /* The constant was not used for register scaling. Since we have
6409 already consumed the token following `*' we now need to put it
6410 back in the stream. */
6411 else
6412 intel_putback_token ();
6413 }
6414
6415 /* Add the constant to the displacement string. */
6416 strcat (intel_parser.disp, save_str);
6417 free (save_str);
6418
6419 return 1;
6420 }
6421
64a0c779
DN		 6422 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6423 return 0;
6424}
6425
64a0c779
DN		 6426/* Match the given token against cur_token. If they match, read the next
6427 token from the operand string. */
6428static int
6429intel_match_token (code)
e5cb08ac 6430 int code;
64a0c779
DN		 6431{
6432 if (cur_token.code == code)
6433 {
6434 intel_get_token ();
6435 return 1;
6436 }
6437 else
6438 {
0477af35 6439 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6440 return 0;
6441 }
6442}
6443
64a0c779
DN		 6444/* Read a new token from intel_parser.op_string and store it in cur_token. */
6445static void
6446intel_get_token ()
6447{
6448 char *end_op;
6449 const reg_entry *reg;
6450 struct intel_token new_token;
6451
6452 new_token.code = T_NIL;
6453 new_token.reg = NULL;
6454 new_token.str = NULL;
6455
4a1805b1 6456 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6457 cur_token to prev_token. */
6458 if (prev_token.str)
6459 free (prev_token.str);
6460
6461 prev_token = cur_token;
6462
6463 /* Skip whitespace. */
6464 while (is_space_char (*intel_parser.op_string))
6465 intel_parser.op_string++;
6466
6467 /* Return an empty token if we find nothing else on the line. */
6468 if (*intel_parser.op_string == '\0')
6469 {
6470 cur_token = new_token;
6471 return;
6472 }
6473
6474 /* The new token cannot be larger than the remainder of the operand
6475 string. */
e5cb08ac 6476 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6477 if (new_token.str == NULL)
bc805888 6478 abort ();
64a0c779
DN		 6479 new_token.str[0] = '\0';
6480
6481 if (strchr ("0123456789", *intel_parser.op_string))
6482 {
6483 char *p = new_token.str;
6484 char *q = intel_parser.op_string;
6485 new_token.code = T_CONST;
6486
6487 /* Allow any kind of identifier char to encompass floating point and
6488 hexadecimal numbers. */
6489 while (is_identifier_char (*q))
6490 *p++ = *q++;
6491 *p = '\0';
6492
6493 /* Recognize special symbol names [0-9][bf]. */
6494 if (strlen (intel_parser.op_string) == 2
4a1805b1 6495 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6496 || intel_parser.op_string[1] == 'f'))
6497 new_token.code = T_ID;
6498 }
6499
64a0c779
DN		 6500 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6501 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6502 {
6503 new_token.code = T_REG;
6504 new_token.reg = reg;
6505
6506 if (*intel_parser.op_string == REGISTER_PREFIX)
6507 {
6508 new_token.str[0] = REGISTER_PREFIX;
6509 new_token.str[1] = '\0';
6510 }
6511
6512 strcat (new_token.str, reg->reg_name);
6513 }
6514
6515 else if (is_identifier_char (*intel_parser.op_string))
6516 {
6517 char *p = new_token.str;
6518 char *q = intel_parser.op_string;
6519
6520 /* A '.' or '$' followed by an identifier char is an identifier.
6521 Otherwise, it's operator '.' followed by an expression. */
6522 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6523 {
9306ca4a
JB		 6524 new_token.code = '.';
6525 new_token.str[0] = '.';
64a0c779
DN		 6526 new_token.str[1] = '\0';
6527 }
6528 else
6529 {
6530 while (is_identifier_char (*q) || *q == '@')
6531 *p++ = *q++;
6532 *p = '\0';
6533
9306ca4a
JB		 6534 if (strcasecmp (new_token.str, "NOT") == 0)
6535 new_token.code = '~';
6536
6537 else if (strcasecmp (new_token.str, "MOD") == 0)
6538 new_token.code = '%';
6539
6540 else if (strcasecmp (new_token.str, "AND") == 0)
6541 new_token.code = '&';
6542
6543 else if (strcasecmp (new_token.str, "OR") == 0)
6544 new_token.code = '|';
6545
6546 else if (strcasecmp (new_token.str, "XOR") == 0)
6547 new_token.code = '^';
6548
6549 else if (strcasecmp (new_token.str, "SHL") == 0)
6550 new_token.code = T_SHL;
6551
6552 else if (strcasecmp (new_token.str, "SHR") == 0)
6553 new_token.code = T_SHR;
6554
6555 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6556 new_token.code = T_BYTE;
6557
6558 else if (strcasecmp (new_token.str, "WORD") == 0)
6559 new_token.code = T_WORD;
6560
6561 else if (strcasecmp (new_token.str, "DWORD") == 0)
6562 new_token.code = T_DWORD;
6563
9306ca4a
JB		 6564 else if (strcasecmp (new_token.str, "FWORD") == 0)
6565 new_token.code = T_FWORD;
6566
64a0c779
DN		 6567 else if (strcasecmp (new_token.str, "QWORD") == 0)
6568 new_token.code = T_QWORD;
6569
9306ca4a
JB		 6570 else if (strcasecmp (new_token.str, "TBYTE") == 0
6571 /* XXX remove (gcc still uses it) */
6572 || strcasecmp (new_token.str, "XWORD") == 0)
6573 new_token.code = T_TBYTE;
6574
6575 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6576 || strcasecmp (new_token.str, "OWORD") == 0)
6577 new_token.code = T_XMMWORD;
64a0c779
DN		 6578
6579 else if (strcasecmp (new_token.str, "PTR") == 0)
6580 new_token.code = T_PTR;
6581
6582 else if (strcasecmp (new_token.str, "SHORT") == 0)
6583 new_token.code = T_SHORT;
6584
6585 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6586 {
6587 new_token.code = T_OFFSET;
6588
6589 /* ??? This is not mentioned in the MASM grammar but gcc
6590 makes use of it with -mintel-syntax. OFFSET may be
6591 followed by FLAT: */
6592 if (strncasecmp (q, " FLAT:", 6) == 0)
6593 strcat (new_token.str, " FLAT:");
6594 }
6595
6596 /* ??? This is not mentioned in the MASM grammar. */
6597 else if (strcasecmp (new_token.str, "FLAT") == 0)
6598 new_token.code = T_OFFSET;
6599
6600 else
6601 new_token.code = T_ID;
6602 }
6603 }
6604
9306ca4a
JB		 6605 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6606 {
6607 new_token.code = *intel_parser.op_string;
6608 new_token.str[0] = *intel_parser.op_string;
6609 new_token.str[1] = '\0';
6610 }
6611
6612 else if (strchr ("<>", *intel_parser.op_string)
6613 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6614 {
6615 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6616 new_token.str[0] = *intel_parser.op_string;
6617 new_token.str[1] = *intel_parser.op_string;
6618 new_token.str[2] = '\0';
6619 }
6620
64a0c779 6621 else
0477af35 6622 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6623
6624 intel_parser.op_string += strlen (new_token.str);
6625 cur_token = new_token;
6626}
6627
64a0c779
DN		 6628/* Put cur_token back into the token stream and make cur_token point to
6629 prev_token. */
6630static void
6631intel_putback_token ()
6632{
6633 intel_parser.op_string -= strlen (cur_token.str);
6634 free (cur_token.str);
6635 cur_token = prev_token;
4a1805b1 6636
64a0c779
DN		 6637 /* Forget prev_token. */
6638 prev_token.code = T_NIL;
6639 prev_token.reg = NULL;
6640 prev_token.str = NULL;
6641}
54cfded0 6642
a4447b93 6643int
54cfded0
AM		 6644tc_x86_regname_to_dw2regnum (const char *regname)
6645{
6646 unsigned int regnum;
6647 unsigned int regnames_count;
6648 char *regnames_32[] =
6649 {
a4447b93
RH		 6650 "eax", "ecx", "edx", "ebx",
6651 "esp", "ebp", "esi", "edi",
54cfded0
AM		 6652 "eip"
6653 };
6654 char *regnames_64[] =
6655 {
6656 "rax", "rbx", "rcx", "rdx",
6657 "rdi", "rsi", "rbp", "rsp",
6658 "r8", "r9", "r10", "r11",
6659 "r12", "r13", "r14", "r15",
6660 "rip"
6661 };
6662 char **regnames;
6663
6664 if (flag_code == CODE_64BIT)
6665 {
6666 regnames = regnames_64;
0cea6190 6667 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6668 }
6669 else
6670 {
6671 regnames = regnames_32;
0cea6190 6672 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6673 }
6674
6675 for (regnum = 0; regnum < regnames_count; regnum++)
6676 if (strcmp (regname, regnames[regnum]) == 0)
6677 return regnum;
6678
54cfded0
AM		 6679 return -1;
6680}
6681
6682void
6683tc_x86_frame_initial_instructions (void)
6684{
a4447b93
RH		 6685 static unsigned int sp_regno;
6686
6687 if (!sp_regno)
6688 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6689 ? "rsp" : "esp");
6690
6691 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6692 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6693}
d2b2c203
DJ		 6694
6695int
6696i386_elf_section_type (const char *str, size_t len)
6697{
6698 if (flag_code == CODE_64BIT
6699 && len == sizeof ("unwind") - 1
6700 && strncmp (str, "unwind", 6) == 0)
6701 return SHT_X86_64_UNWIND;
6702
6703 return -1;
6704}
bb41ade5
AM		 6705
6706#ifdef TE_PE
6707void
6708tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6709{
6710 expressionS expr;
6711
6712 expr.X_op = O_secrel;
6713 expr.X_add_symbol = symbol;
6714 expr.X_add_number = 0;
6715 emit_expr (&expr, size);
6716}
6717#endif
GDB Binutils - Deliverables
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