projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
41be57ca
MM		 12019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
2
3 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
4 sve_size_13 icode to account for variant behaviour of
5 pmull{t,b}.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
8 sve_size_13 icode to account for variant behaviour of
9 pmull{t,b}.
10 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
11 (OP_SVE_VVV_Q_D): Add new qualifier.
12 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
13 (struct aarch64_opcode): Split pmull{t,b} into those requiring
14 AES and those not.
15
9d3bf266
JB		 162019-07-01 Jan Beulich <jbeulich@suse.com>
17
18 * opcodes/i386-gen.c (operand_type_init): Remove
19 OPERAND_TYPE_VEC_IMM4 entry.
20 (operand_types): Remove Vec_Imm4.
21 * opcodes/i386-opc.h (Vec_Imm4): Delete.
22 (union i386_operand_type): Remove vec_imm4.
23 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
24 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
25
c3949f43
JB		 262019-07-01 Jan Beulich <jbeulich@suse.com>
27
28 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
29 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
30 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
31 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
32 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
33 monitorx, mwaitx): Drop ImmExt from operand-less forms.
34 * i386-tbl.h: Re-generate.
35
5641ec01
JB		 362019-07-01 Jan Beulich <jbeulich@suse.com>
37
38 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
39 register operands.
40 * i386-tbl.h: Re-generate.
41
79dec6b7
JB		 422019-07-01 Jan Beulich <jbeulich@suse.com>
43
44 * i386-opc.tbl (C): New.
45 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
46 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
47 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
48 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
49 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
50 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
51 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
52 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
53 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
54 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
55 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
56 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
57 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
58 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
59 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
60 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
61 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
62 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
63 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
64 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
65 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
66 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
67 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
68 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
69 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
70 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
71 flavors.
72 * i386-tbl.h: Re-generate.
73
a0a1771e
JB		 742019-07-01 Jan Beulich <jbeulich@suse.com>
75
76 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
77 register operands.
78 * i386-tbl.h: Re-generate.
79
cd546e7b
JB		 802019-07-01 Jan Beulich <jbeulich@suse.com>
81
82 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
83 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
84 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
85 * i386-tbl.h: Re-generate.
86
e3bba3fc
JB		 872019-07-01 Jan Beulich <jbeulich@suse.com>
88
89 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
90 Disp8MemShift from register only templates.
91 * i386-tbl.h: Re-generate.
92
36cc073e
JB		 932019-07-01 Jan Beulich <jbeulich@suse.com>
94
95 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
96 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
97 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
98 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
99 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
100 EVEX_W_0F11_P_3_M_1): Delete.
101 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
102 EVEX_W_0F11_P_3): New.
103 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
104 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
105 MOD_EVEX_0F11_PREFIX_3 table entries.
106 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
107 PREFIX_EVEX_0F11 table entries.
108 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
109 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
110 EVEX_W_0F11_P_3_M_{0,1} table entries.
111
219920a7
JB		 1122019-07-01 Jan Beulich <jbeulich@suse.com>
113
114 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
115 Delete.
116
e395f487
L		 1172019-06-27 H.J. Lu <hongjiu.lu@intel.com>
118
119 PR binutils/24719
120 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
121 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
122 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
123 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
124 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
125 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
126 EVEX_LEN_0F38C7_R_6_P_2_W_1.
127 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
128 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
129 PREFIX_EVEX_0F38C6_REG_6 entries.
130 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
131 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
132 EVEX_W_0F38C7_R_6_P_2 entries.
133 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
134 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
135 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
136 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
137 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
138 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
139 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
140
2b7bcc87
JB		 1412019-06-27 Jan Beulich <jbeulich@suse.com>
142
143 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
144 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
145 VEX_LEN_0F2D_P_3): Delete.
146 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
147 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
148 (prefix_table): ... here.
149
c1dc7af5
JB		 1502019-06-27 Jan Beulich <jbeulich@suse.com>
151
152 * i386-dis.c (Iq): Delete.
153 (Id): New.
154 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
155 TBM insns.
156 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
157 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
158 (OP_E_memory): Also honor needindex when deciding whether an
159 address size prefix needs printing.
160 (OP_I): Remove handling of q_mode. Add handling of d_mode.
161
d7560e2d
JW		 1622019-06-26 Jim Wilson <jimw@sifive.com>
163
164 PR binutils/24739
165 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
166 Set info->display_endian to info->endian_code.
167
2c703856
JB		 1682019-06-25 Jan Beulich <jbeulich@suse.com>
169
170 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
171 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
172 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
173 OPERAND_TYPE_ACC64 entries.
174 * i386-init.h: Re-generate.
175
54fbadc0
JB		 1762019-06-25 Jan Beulich <jbeulich@suse.com>
177
178 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
179 Delete.
180 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
181 of dqa_mode.
182 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
183 entries here.
184 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
185 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
186
a280ab8e
JB		 1872019-06-25 Jan Beulich <jbeulich@suse.com>
188
189 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
190 variables.
191
e1a1babd
JB		 1922019-06-25 Jan Beulich <jbeulich@suse.com>
193
194 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
195 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
196 movnti.
d7560e2d 197 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 198 * i386-tbl.h: Re-generate.
199
b8364fa7
JB		 2002019-06-25 Jan Beulich <jbeulich@suse.com>
201
202 * i386-opc.tbl (and): Mark Imm8S form for optimization.
203 * i386-tbl.h: Re-generate.
204
ad692897
L		 2052019-06-21 H.J. Lu <hongjiu.lu@intel.com>
206
207 * i386-dis-evex.h: Break into ...
208 * i386-dis-evex-len.h: New file.
209 * i386-dis-evex-mod.h: Likewise.
210 * i386-dis-evex-prefix.h: Likewise.
211 * i386-dis-evex-reg.h: Likewise.
212 * i386-dis-evex-w.h: Likewise.
213 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
214 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
215 i386-dis-evex-mod.h.
216
f0a6222e
L		 2172019-06-19 H.J. Lu <hongjiu.lu@intel.com>
218
219 PR binutils/24700
220 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
221 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
222 EVEX_W_0F385B_P_2.
223 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
224 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
225 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
226 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
227 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
228 EVEX_LEN_0F385B_P_2_W_1.
229 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
230 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
231 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
232 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
233 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
234 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
235 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
236 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
237 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
238 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
239
6e1c90b7
L		 2402019-06-17 H.J. Lu <hongjiu.lu@intel.com>
241
242 PR binutils/24691
243 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
244 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
245 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
246 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
247 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
248 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
249 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
250 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
251 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
252 EVEX_LEN_0F3A43_P_2_W_1.
253 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
254 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
255 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
256 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
257 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
258 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
259 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
260 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
261 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
262 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
263 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
264 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
265
bcc5a6eb
NC		 2662019-06-14 Nick Clifton <nickc@redhat.com>
267
268 * po/fr.po; Updated French translation.
269
e4c4ac46
SH		 2702019-06-13 Stafford Horne <shorne@gmail.com>
271
272 * or1k-asm.c: Regenerated.
273 * or1k-desc.c: Regenerated.
274 * or1k-desc.h: Regenerated.
275 * or1k-dis.c: Regenerated.
276 * or1k-ibld.c: Regenerated.
277 * or1k-opc.c: Regenerated.
278 * or1k-opc.h: Regenerated.
279 * or1k-opinst.c: Regenerated.
280
a0e44ef5
PB		 2812019-06-12 Peter Bergner <bergner@linux.ibm.com>
282
283 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
284
12efd68d
L		 2852019-06-05 H.J. Lu <hongjiu.lu@intel.com>
286
287 PR binutils/24633
288 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
289 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
290 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
291 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
292 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
293 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
294 EVEX_LEN_0F3A1B_P_2_W_1.
295 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
296 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
297 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
298 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
299 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
300 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
301 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
302 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
303
63c6fc6c
L		 3042019-06-04 H.J. Lu <hongjiu.lu@intel.com>
305
306 PR binutils/24626
307 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
308 EVEX.vvvv when disassembling VEX and EVEX instructions.
309 (OP_VEX): Set vex.register_specifier to 0 after readding
310 vex.register_specifier.
311 (OP_Vex_2src_1): Likewise.
312 (OP_Vex_2src_2): Likewise.
313 (OP_LWP_E): Likewise.
314 (OP_EX_Vex): Don't check vex.register_specifier.
315 (OP_XMM_Vex): Likewise.
316
9186c494
L		 3172019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
318 Lili Cui <lili.cui@intel.com>
319
320 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
321 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
322 instructions.
323 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
324 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
325 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
326 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
327 (i386_cpu_flags): Add cpuavx512_vp2intersect.
328 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
329 * i386-init.h: Regenerated.
330 * i386-tbl.h: Likewise.
331
5d79adc4
L		 3322019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
333 Lili Cui <lili.cui@intel.com>
334
335 * doc/c-i386.texi: Document enqcmd.
336 * testsuite/gas/i386/enqcmd-intel.d: New file.
337 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
338 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
339 * testsuite/gas/i386/enqcmd.d: Likewise.
340 * testsuite/gas/i386/enqcmd.s: Likewise.
341 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
342 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
343 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
344 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
345 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
346 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
347 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
348 and x86-64-enqcmd.
349
a9d96ab9
AH		 3502019-06-04 Alan Hayward <alan.hayward@arm.com>
351
352 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
353
4f6d070a
AM		 3542019-06-03 Alan Modra <amodra@gmail.com>
355
356 * ppc-dis.c (prefix_opcd_indices): Correct size.
357
a2f4b66c
L		 3582019-05-28 H.J. Lu <hongjiu.lu@intel.com>
359
360 PR gas/24625
361 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
362 Disp8ShiftVL.
363 * i386-tbl.h: Regenerated.
364
405b5bd8
AM		 3652019-05-24 Alan Modra <amodra@gmail.com>
366
367 * po/POTFILES.in: Regenerate.
368
8acf1435
PB		 3692019-05-24 Peter Bergner <bergner@linux.ibm.com>
370 Alan Modra <amodra@gmail.com>
371
372 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
373 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
374 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
375 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
376 XTOP>): Define and add entries.
377 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
378 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
379 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
380 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
381
dd7efa79
PB		 3822019-05-24 Peter Bergner <bergner@linux.ibm.com>
383 Alan Modra <amodra@gmail.com>
384
385 * ppc-dis.c (ppc_opts): Add "future" entry.
386 (PREFIX_OPCD_SEGS): Define.
387 (prefix_opcd_indices): New array.
388 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
389 (lookup_prefix): New function.
390 (print_insn_powerpc): Handle 64-bit prefix instructions.
391 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
392 (PMRR, POWERXX): Define.
393 (prefix_opcodes): New instruction table.
394 (prefix_num_opcodes): New constant.
395
79472b45
JM		 3962019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
397
398 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
399 * configure: Regenerated.
400 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
401 and cpu/bpf.opc.
402 (HFILES): Add bpf-desc.h and bpf-opc.h.
403 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
404 bpf-ibld.c and bpf-opc.c.
405 (BPF_DEPS): Define.
406 * Makefile.in: Regenerated.
407 * disassemble.c (ARCH_bpf): Define.
408 (disassembler): Add case for bfd_arch_bpf.
409 (disassemble_init_for_target): Likewise.
410 (enum epbf_isa_attr): Define.
411 * disassemble.h: extern print_insn_bpf.
412 * bpf-asm.c: Generated.
413 * bpf-opc.h: Likewise.
414 * bpf-opc.c: Likewise.
415 * bpf-ibld.c: Likewise.
416 * bpf-dis.c: Likewise.
417 * bpf-desc.h: Likewise.
418 * bpf-desc.c: Likewise.
419
ba6cd17f
SD		 4202019-05-21 Sudakshina Das <sudi.das@arm.com>
421
422 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
423 and VMSR with the new operands.
424
e39c1607
SD		 4252019-05-21 Sudakshina Das <sudi.das@arm.com>
426
427 * arm-dis.c (enum mve_instructions): New enum
428 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
429 and cneg.
430 (mve_opcodes): New instructions as above.
431 (is_mve_encoding_conflict): Add cases for csinc, csinv,
432 csneg and csel.
433 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
434
23d00a41
SD		 4352019-05-21 Sudakshina Das <sudi.das@arm.com>
436
437 * arm-dis.c (emun mve_instructions): Updated for new instructions.
438 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
439 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
440 uqshl, urshrl and urshr.
441 (is_mve_okay_in_it): Add new instructions to TRUE list.
442 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
443 (print_insn_mve): Updated to accept new %j,
444 %<bitfield>m and %<bitfield>n patterns.
445
cd4797ee
FS		 4462019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
447
448 * mips-opc.c (mips_builtin_opcodes): Change source register
449 constraint for DAUI.
450
999b073b
NC		 4512019-05-20 Nick Clifton <nickc@redhat.com>
452
453 * po/fr.po: Updated French translation.
454
14b456f2
AV		 4552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
456 Michael Collison <michael.collison@arm.com>
457
458 * arm-dis.c (thumb32_opcodes): Add new instructions.
459 (enum mve_instructions): Likewise.
460 (enum mve_undefined): Add new reasons.
461 (is_mve_encoding_conflict): Handle new instructions.
462 (is_mve_undefined): Likewise.
463 (is_mve_unpredictable): Likewise.
464 (print_mve_undefined): Likewise.
465 (print_mve_size): Likewise.
466
f49bb598
AV		 4672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
468 Michael Collison <michael.collison@arm.com>
469
470 * arm-dis.c (thumb32_opcodes): Add new instructions.
471 (enum mve_instructions): Likewise.
472 (is_mve_encoding_conflict): Handle new instructions.
473 (is_mve_undefined): Likewise.
474 (is_mve_unpredictable): Likewise.
475 (print_mve_size): Likewise.
476
56858bea
AV		 4772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
478 Michael Collison <michael.collison@arm.com>
479
480 * arm-dis.c (thumb32_opcodes): Add new instructions.
481 (enum mve_instructions): Likewise.
482 (is_mve_encoding_conflict): Likewise.
483 (is_mve_unpredictable): Likewise.
484 (print_mve_size): Likewise.
485
e523f101
AV		 4862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
487 Michael Collison <michael.collison@arm.com>
488
489 * arm-dis.c (thumb32_opcodes): Add new instructions.
490 (enum mve_instructions): Likewise.
491 (is_mve_encoding_conflict): Handle new instructions.
492 (is_mve_undefined): Likewise.
493 (is_mve_unpredictable): Likewise.
494 (print_mve_size): Likewise.
495
66dcaa5d
AV		 4962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
497 Michael Collison <michael.collison@arm.com>
498
499 * arm-dis.c (thumb32_opcodes): Add new instructions.
500 (enum mve_instructions): Likewise.
501 (is_mve_encoding_conflict): Handle new instructions.
502 (is_mve_undefined): Likewise.
503 (is_mve_unpredictable): Likewise.
504 (print_mve_size): Likewise.
505 (print_insn_mve): Likewise.
506
d052b9b7
AV		 5072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
508 Michael Collison <michael.collison@arm.com>
509
510 * arm-dis.c (thumb32_opcodes): Add new instructions.
511 (print_insn_thumb32): Handle new instructions.
512
ed63aa17
AV		 5132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
514 Michael Collison <michael.collison@arm.com>
515
516 * arm-dis.c (enum mve_instructions): Add new instructions.
517 (enum mve_undefined): Add new reasons.
518 (is_mve_encoding_conflict): Handle new instructions.
519 (is_mve_undefined): Likewise.
520 (is_mve_unpredictable): Likewise.
521 (print_mve_undefined): Likewise.
522 (print_mve_size): Likewise.
523 (print_mve_shift_n): Likewise.
524 (print_insn_mve): Likewise.
525
897b9bbc
AV		 5262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
527 Michael Collison <michael.collison@arm.com>
528
529 * arm-dis.c (enum mve_instructions): Add new instructions.
530 (is_mve_encoding_conflict): Handle new instructions.
531 (is_mve_unpredictable): Likewise.
532 (print_mve_rotate): Likewise.
533 (print_mve_size): Likewise.
534 (print_insn_mve): Likewise.
535
1c8f2df8
AV		 5362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
537 Michael Collison <michael.collison@arm.com>
538
539 * arm-dis.c (enum mve_instructions): Add new instructions.
540 (is_mve_encoding_conflict): Handle new instructions.
541 (is_mve_unpredictable): Likewise.
542 (print_mve_size): Likewise.
543 (print_insn_mve): Likewise.
544
d3b63143
AV		 5452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
546 Michael Collison <michael.collison@arm.com>
547
548 * arm-dis.c (enum mve_instructions): Add new instructions.
549 (enum mve_undefined): Add new reasons.
550 (is_mve_encoding_conflict): Handle new instructions.
551 (is_mve_undefined): Likewise.
552 (is_mve_unpredictable): Likewise.
553 (print_mve_undefined): Likewise.
554 (print_mve_size): Likewise.
555 (print_insn_mve): Likewise.
556
14925797
AV		 5572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
558 Michael Collison <michael.collison@arm.com>
559
560 * arm-dis.c (enum mve_instructions): Add new instructions.
561 (is_mve_encoding_conflict): Handle new instructions.
562 (is_mve_undefined): Likewise.
563 (is_mve_unpredictable): Likewise.
564 (print_mve_size): Likewise.
565 (print_insn_mve): Likewise.
566
c507f10b
AV		 5672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
568 Michael Collison <michael.collison@arm.com>
569
570 * arm-dis.c (enum mve_instructions): Add new instructions.
571 (enum mve_unpredictable): Add new reasons.
572 (enum mve_undefined): Likewise.
573 (is_mve_okay_in_it): Handle new isntructions.
574 (is_mve_encoding_conflict): Likewise.
575 (is_mve_undefined): Likewise.
576 (is_mve_unpredictable): Likewise.
577 (print_mve_vmov_index): Likewise.
578 (print_simd_imm8): Likewise.
579 (print_mve_undefined): Likewise.
580 (print_mve_unpredictable): Likewise.
581 (print_mve_size): Likewise.
582 (print_insn_mve): Likewise.
583
bf0b396d
AV		 5842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
585 Michael Collison <michael.collison@arm.com>
586
587 * arm-dis.c (enum mve_instructions): Add new instructions.
588 (enum mve_unpredictable): Add new reasons.
589 (enum mve_undefined): Likewise.
590 (is_mve_encoding_conflict): Handle new instructions.
591 (is_mve_undefined): Likewise.
592 (is_mve_unpredictable): Likewise.
593 (print_mve_undefined): Likewise.
594 (print_mve_unpredictable): Likewise.
595 (print_mve_rounding_mode): Likewise.
596 (print_mve_vcvt_size): Likewise.
597 (print_mve_size): Likewise.
598 (print_insn_mve): Likewise.
599
ef1576a1
AV		 6002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
601 Michael Collison <michael.collison@arm.com>
602
603 * arm-dis.c (enum mve_instructions): Add new instructions.
604 (enum mve_unpredictable): Add new reasons.
605 (enum mve_undefined): Likewise.
606 (is_mve_undefined): Handle new instructions.
607 (is_mve_unpredictable): Likewise.
608 (print_mve_undefined): Likewise.
609 (print_mve_unpredictable): Likewise.
610 (print_mve_size): Likewise.
611 (print_insn_mve): Likewise.
612
aef6d006
AV		 6132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
614 Michael Collison <michael.collison@arm.com>
615
616 * arm-dis.c (enum mve_instructions): Add new instructions.
617 (enum mve_undefined): Add new reasons.
618 (insns): Add new instructions.
619 (is_mve_encoding_conflict):
620 (print_mve_vld_str_addr): New print function.
621 (is_mve_undefined): Handle new instructions.
622 (is_mve_unpredictable): Likewise.
623 (print_mve_undefined): Likewise.
624 (print_mve_size): Likewise.
625 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
626 (print_insn_mve): Handle new operands.
627
04d54ace
AV		 6282019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
629 Michael Collison <michael.collison@arm.com>
630
631 * arm-dis.c (enum mve_instructions): Add new instructions.
632 (enum mve_unpredictable): Add new reasons.
633 (is_mve_encoding_conflict): Handle new instructions.
634 (is_mve_unpredictable): Likewise.
635 (mve_opcodes): Add new instructions.
636 (print_mve_unpredictable): Handle new reasons.
637 (print_mve_register_blocks): New print function.
638 (print_mve_size): Handle new instructions.
639 (print_insn_mve): Likewise.
640
9743db03
AV		 6412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
642 Michael Collison <michael.collison@arm.com>
643
644 * arm-dis.c (enum mve_instructions): Add new instructions.
645 (enum mve_unpredictable): Add new reasons.
646 (enum mve_undefined): Likewise.
647 (is_mve_encoding_conflict): Handle new instructions.
648 (is_mve_undefined): Likewise.
649 (is_mve_unpredictable): Likewise.
650 (coprocessor_opcodes): Move NEON VDUP from here...
651 (neon_opcodes): ... to here.
652 (mve_opcodes): Add new instructions.
653 (print_mve_undefined): Handle new reasons.
654 (print_mve_unpredictable): Likewise.
655 (print_mve_size): Handle new instructions.
656 (print_insn_neon): Handle vdup.
657 (print_insn_mve): Handle new operands.
658
143275ea
AV		 6592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
660 Michael Collison <michael.collison@arm.com>
661
662 * arm-dis.c (enum mve_instructions): Add new instructions.
663 (enum mve_unpredictable): Add new values.
664 (mve_opcodes): Add new instructions.
665 (vec_condnames): New array with vector conditions.
666 (mve_predicatenames): New array with predicate suffixes.
667 (mve_vec_sizename): New array with vector sizes.
668 (enum vpt_pred_state): New enum with vector predication states.
669 (struct vpt_block): New struct type for vpt blocks.
670 (vpt_block_state): Global struct to keep track of state.
671 (mve_extract_pred_mask): New helper function.
672 (num_instructions_vpt_block): Likewise.
673 (mark_outside_vpt_block): Likewise.
674 (mark_inside_vpt_block): Likewise.
675 (invert_next_predicate_state): Likewise.
676 (update_next_predicate_state): Likewise.
677 (update_vpt_block_state): Likewise.
678 (is_vpt_instruction): Likewise.
679 (is_mve_encoding_conflict): Add entries for new instructions.
680 (is_mve_unpredictable): Likewise.
681 (print_mve_unpredictable): Handle new cases.
682 (print_instruction_predicate): Likewise.
683 (print_mve_size): New function.
684 (print_vec_condition): New function.
685 (print_insn_mve): Handle vpt blocks and new print operands.
686
f08d8ce3
AV		 6872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
688
689 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
690 8, 14 and 15 for Armv8.1-M Mainline.
691
73cd51e5
AV		 6922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
693 Michael Collison <michael.collison@arm.com>
694
695 * arm-dis.c (enum mve_instructions): New enum.
696 (enum mve_unpredictable): Likewise.
697 (enum mve_undefined): Likewise.
698 (struct mopcode32): New struct.
699 (is_mve_okay_in_it): New function.
700 (is_mve_architecture): Likewise.
701 (arm_decode_field): Likewise.
702 (arm_decode_field_multiple): Likewise.
703 (is_mve_encoding_conflict): Likewise.
704 (is_mve_undefined): Likewise.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_undefined): Likewise.
707 (print_mve_unpredictable): Likewise.
708 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
709 (print_insn_mve): New function.
710 (print_insn_thumb32): Handle MVE architecture.
711 (select_arm_features): Force thumb for Armv8.1-m Mainline.
712
3076e594
NC		 7132019-05-10 Nick Clifton <nickc@redhat.com>
714
715 PR 24538
716 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
717 end of the table prematurely.
718
387e7624
FS		 7192019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
720
721 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
722 macros for R6.
723
0067be51
AM		 7242019-05-11 Alan Modra <amodra@gmail.com>
725
726 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
727 when -Mraw is in effect.
728
42e6288f
MM		 7292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
730
731 * aarch64-dis-2.c: Regenerate.
732 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
733 (OP_SVE_BBB): New variant set.
734 (OP_SVE_DDDD): New variant set.
735 (OP_SVE_HHH): New variant set.
736 (OP_SVE_HHHU): New variant set.
737 (OP_SVE_SSS): New variant set.
738 (OP_SVE_SSSU): New variant set.
739 (OP_SVE_SHH): New variant set.
740 (OP_SVE_SBBU): New variant set.
741 (OP_SVE_DSS): New variant set.
742 (OP_SVE_DHHU): New variant set.
743 (OP_SVE_VMV_HSD_BHS): New variant set.
744 (OP_SVE_VVU_HSD_BHS): New variant set.
745 (OP_SVE_VVVU_SD_BH): New variant set.
746 (OP_SVE_VVVU_BHSD): New variant set.
747 (OP_SVE_VVV_QHD_DBS): New variant set.
748 (OP_SVE_VVV_HSD_BHS): New variant set.
749 (OP_SVE_VVV_HSD_BHS2): New variant set.
750 (OP_SVE_VVV_BHS_HSD): New variant set.
751 (OP_SVE_VV_BHS_HSD): New variant set.
752 (OP_SVE_VVV_SD): New variant set.
753 (OP_SVE_VVU_BHS_HSD): New variant set.
754 (OP_SVE_VZVV_SD): New variant set.
755 (OP_SVE_VZVV_BH): New variant set.
756 (OP_SVE_VZV_SD): New variant set.
757 (aarch64_opcode_table): Add sve2 instructions.
758
28ed815a
MM		 7592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
760
761 * aarch64-asm-2.c: Regenerated.
762 * aarch64-dis-2.c: Regenerated.
763 * aarch64-opc-2.c: Regenerated.
764 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
765 for SVE_SHLIMM_UNPRED_22.
766 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
767 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
768 operand.
769
fd1dc4a0
MM		 7702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
771
772 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
773 sve_size_tsz_bhs iclass encode.
774 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
775 sve_size_tsz_bhs iclass decode.
776
31e36ab3
MM		 7772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
778
779 * aarch64-asm-2.c: Regenerated.
780 * aarch64-dis-2.c: Regenerated.
781 * aarch64-opc-2.c: Regenerated.
782 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
783 for SVE_Zm4_11_INDEX.
784 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
785 (fields): Handle SVE_i2h field.
786 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
787 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
788
1be5f94f
MM		 7892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
790
791 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
792 sve_shift_tsz_bhsd iclass encode.
793 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
794 sve_shift_tsz_bhsd iclass decode.
795
3c17238b
MM		 7962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
797
798 * aarch64-asm-2.c: Regenerated.
799 * aarch64-dis-2.c: Regenerated.
800 * aarch64-opc-2.c: Regenerated.
801 * aarch64-asm.c (aarch64_ins_sve_shrimm):
802 (aarch64_encode_variant_using_iclass): Handle
803 sve_shift_tsz_hsd iclass encode.
804 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
805 sve_shift_tsz_hsd iclass decode.
806 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
807 for SVE_SHRIMM_UNPRED_22.
808 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
809 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
810 operand.
811
cd50a87a
MM		 8122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
813
814 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
815 sve_size_013 iclass encode.
816 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
817 sve_size_013 iclass decode.
818
3c705960
MM		 8192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
820
821 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
822 sve_size_bh iclass encode.
823 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
824 sve_size_bh iclass decode.
825
0a57e14f
MM		 8262019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
827
828 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
829 sve_size_sd2 iclass encode.
830 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
831 sve_size_sd2 iclass decode.
832 * aarch64-opc.c (fields): Handle SVE_sz2 field.
833 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
834
c469c864
MM		 8352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
836
837 * aarch64-asm-2.c: Regenerated.
838 * aarch64-dis-2.c: Regenerated.
839 * aarch64-opc-2.c: Regenerated.
840 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
841 for SVE_ADDR_ZX.
842 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
843 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
844
116adc27
MM		 8452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
846
847 * aarch64-asm-2.c: Regenerated.
848 * aarch64-dis-2.c: Regenerated.
849 * aarch64-opc-2.c: Regenerated.
850 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
851 for SVE_Zm3_11_INDEX.
852 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
853 (fields): Handle SVE_i3l and SVE_i3h2 fields.
854 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
855 fields.
856 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
857
3bd82c86
MM		 8582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
859
860 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
861 sve_size_hsd2 iclass encode.
862 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
863 sve_size_hsd2 iclass decode.
864 * aarch64-opc.c (fields): Handle SVE_size field.
865 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
866
adccc507
MM		 8672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
868
869 * aarch64-asm-2.c: Regenerated.
870 * aarch64-dis-2.c: Regenerated.
871 * aarch64-opc-2.c: Regenerated.
872 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
873 for SVE_IMM_ROT3.
874 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
875 (fields): Handle SVE_rot3 field.
876 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
877 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
878
5cd99750
MM		 8792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
880
881 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
882 instructions.
883
7ce2460a
MM		 8842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
885
886 * aarch64-tbl.h
887 (aarch64_feature_sve2, aarch64_feature_sve2aes,
888 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
889 aarch64_feature_sve2bitperm): New feature sets.
890 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
891 for feature set addresses.
892 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
893 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
894
41cee089
FS		 8952019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
896 Faraz Shahbazker <fshahbazker@wavecomp.com>
897
898 * mips-dis.c (mips_calculate_combination_ases): Add ISA
899 argument and set ASE_EVA_R6 appropriately.
900 (set_default_mips_dis_options): Pass ISA to above.
901 (parse_mips_dis_option): Likewise.
902 * mips-opc.c (EVAR6): New macro.
903 (mips_builtin_opcodes): Add llwpe, scwpe.
904
b83b4b13
SD		 9052019-05-01 Sudakshina Das <sudi.das@arm.com>
906
907 * aarch64-asm-2.c: Regenerated.
908 * aarch64-dis-2.c: Regenerated.
909 * aarch64-opc-2.c: Regenerated.
910 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
911 AARCH64_OPND_TME_UIMM16.
912 (aarch64_print_operand): Likewise.
913 * aarch64-tbl.h (QL_IMM_NIL): New.
914 (TME): New.
915 (_TME_INSN): New.
916 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
917
4a90ce95
JD		 9182019-04-29 John Darrington <john@darrington.wattle.id.au>
919
920 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
921
a45328b9
AB		 9222019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
923 Faraz Shahbazker <fshahbazker@wavecomp.com>
924
925 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
926
d10be0cb
JD		 9272019-04-24 John Darrington <john@darrington.wattle.id.au>
928
929 * s12z-opc.h: Add extern "C" bracketing to help
930 users who wish to use this interface in c++ code.
931
a679f24e
JD		 9322019-04-24 John Darrington <john@darrington.wattle.id.au>
933
934 * s12z-opc.c (bm_decode): Handle bit map operations with the
935 "reserved0" mode.
936
32c36c3c
AV		 9372019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
938
939 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
940 specifier. Add entries for VLDR and VSTR of system registers.
941 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
942 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
943 of %J and %K format specifier.
944
efd6b359
AV		 9452019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
946
947 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
948 Add new entries for VSCCLRM instruction.
949 (print_insn_coprocessor): Handle new %C format control code.
950
6b0dd094
AV		 9512019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
952
953 * arm-dis.c (enum isa): New enum.
954 (struct sopcode32): New structure.
955 (coprocessor_opcodes): change type of entries to struct sopcode32 and
956 set isa field of all current entries to ANY.
957 (print_insn_coprocessor): Change type of insn to struct sopcode32.
958 Only match an entry if its isa field allows the current mode.
959
4b5a202f
AV		 9602019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
961
962 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
963 CLRM.
964 (print_insn_thumb32): Add logic to print %n CLRM register list.
965
60f993ce
AV		 9662019-04-15 Sudakshina Das <sudi.das@arm.com>
967
968 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
969 and %Q patterns.
970
f6b2b12d
AV		 9712019-04-15 Sudakshina Das <sudi.das@arm.com>
972
973 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
974 (print_insn_thumb32): Edit the switch case for %Z.
975
1889da70
AV		 9762019-04-15 Sudakshina Das <sudi.das@arm.com>
977
978 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
979
65d1bc05
AV		 9802019-04-15 Sudakshina Das <sudi.das@arm.com>
981
982 * arm-dis.c (thumb32_opcodes): New instruction bfl.
983
1caf72a5
AV		 9842019-04-15 Sudakshina Das <sudi.das@arm.com>
985
986 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
987
f1c7f421
AV		 9882019-04-15 Sudakshina Das <sudi.das@arm.com>
989
990 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
991 Arm register with r13 and r15 unpredictable.
992 (thumb32_opcodes): New instructions for bfx and bflx.
993
4389b29a
AV		 9942019-04-15 Sudakshina Das <sudi.das@arm.com>
995
996 * arm-dis.c (thumb32_opcodes): New instructions for bf.
997
e5d6e09e
AV		 9982019-04-15 Sudakshina Das <sudi.das@arm.com>
999
1000 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1001
e12437dc
AV		 10022019-04-15 Sudakshina Das <sudi.das@arm.com>
1003
1004 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1005
031254f2
AV		 10062019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1007
1008 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1009
e5a557ac
JD		 10102019-04-12 John Darrington <john@darrington.wattle.id.au>
1011
1012 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1013 "optr". ("operator" is a reserved word in c++).
1014
bd7ceb8d
SD		 10152019-04-11 Sudakshina Das <sudi.das@arm.com>
1016
1017 * aarch64-opc.c (aarch64_print_operand): Add case for
1018 AARCH64_OPND_Rt_SP.
1019 (verify_constraints): Likewise.
1020 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1021 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1022 to accept Rt|SP as first operand.
1023 (AARCH64_OPERANDS): Add new Rt_SP.
1024 * aarch64-asm-2.c: Regenerated.
1025 * aarch64-dis-2.c: Regenerated.
1026 * aarch64-opc-2.c: Regenerated.
1027
e54010f1
SD		 10282019-04-11 Sudakshina Das <sudi.das@arm.com>
1029
1030 * aarch64-asm-2.c: Regenerated.
1031 * aarch64-dis-2.c: Likewise.
1032 * aarch64-opc-2.c: Likewise.
1033 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1034
7e96e219
RS		 10352019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1036
1037 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1038
6f2791d5
L		 10392019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1042 * i386-init.h: Regenerated.
1043
e392bad3
AM		 10442019-04-07 Alan Modra <amodra@gmail.com>
1045
1046 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1047 op_separator to control printing of spaces, comma and parens
1048 rather than need_comma, need_paren and spaces vars.
1049
dffaa15c
AM		 10502019-04-07 Alan Modra <amodra@gmail.com>
1051
1052 PR 24421
1053 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1054 (print_insn_neon, print_insn_arm): Likewise.
1055
d6aab7a1
XG		 10562019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1057
1058 * i386-dis-evex.h (evex_table): Updated to support BF16
1059 instructions.
1060 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1061 and EVEX_W_0F3872_P_3.
1062 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1063 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1064 * i386-opc.h (enum): Add CpuAVX512_BF16.
1065 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1066 * i386-opc.tbl: Add AVX512 BF16 instructions.
1067 * i386-init.h: Regenerated.
1068 * i386-tbl.h: Likewise.
1069
66e85460
AM		 10702019-04-05 Alan Modra <amodra@gmail.com>
1071
1072 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1073 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1074 to favour printing of "-" branch hint when using the "y" bit.
1075 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1076
c2b1c275
AM		 10772019-04-05 Alan Modra <amodra@gmail.com>
1078
1079 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1080 opcode until first operand is output.
1081
aae9718e
PB		 10822019-04-04 Peter Bergner <bergner@linux.ibm.com>
1083
1084 PR gas/24349
1085 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1086 (valid_bo_post_v2): Add support for 'at' branch hints.
1087 (insert_bo): Only error on branch on ctr.
1088 (get_bo_hint_mask): New function.
1089 (insert_boe): Add new 'branch_taken' formal argument. Add support
1090 for inserting 'at' branch hints.
1091 (extract_boe): Add new 'branch_taken' formal argument. Add support
1092 for extracting 'at' branch hints.
1093 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1094 (BOE): Delete operand.
1095 (BOM, BOP): New operands.
1096 (RM): Update value.
1097 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1098 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1099 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1100 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1101 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1102 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1103 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1104 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1105 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1106 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1107 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1108 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1109 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1110 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1111 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1112 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1113 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1114 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1115 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1116 bttarl+>: New extended mnemonics.
1117
96a86c01
AM		 11182019-03-28 Alan Modra <amodra@gmail.com>
1119
1120 PR 24390
1121 * ppc-opc.c (BTF): Define.
1122 (powerpc_opcodes): Use for mtfsb*.
1123 * ppc-dis.c (print_insn_powerpc): Print fields with both
1124 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1125
796d6298
TC		 11262019-03-25 Tamar Christina <tamar.christina@arm.com>
1127
1128 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1129 (mapping_symbol_for_insn): Implement new algorithm.
1130 (print_insn): Remove duplicate code.
1131
60df3720
TC		 11322019-03-25 Tamar Christina <tamar.christina@arm.com>
1133
1134 * aarch64-dis.c (print_insn_aarch64):
1135 Implement override.
1136
51457761
TC		 11372019-03-25 Tamar Christina <tamar.christina@arm.com>
1138
1139 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1140 order.
1141
53b2f36b
TC		 11422019-03-25 Tamar Christina <tamar.christina@arm.com>
1143
1144 * aarch64-dis.c (last_stop_offset): New.
1145 (print_insn_aarch64): Use stop_offset.
1146
89199bb5
L		 11472019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1148
1149 PR gas/24359
1150 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1151 CPU_ANY_AVX2_FLAGS.
1152 * i386-init.h: Regenerated.
1153
97ed31ae
L		 11542019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1155
1156 PR gas/24348
1157 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1158 vmovdqu16, vmovdqu32 and vmovdqu64.
1159 * i386-tbl.h: Regenerated.
1160
0919bfe9
AK		 11612019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1162
1163 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1164 from vstrszb, vstrszh, and vstrszf.
1165
11662019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1167
1168 * s390-opc.txt: Add instruction descriptions.
1169
21820ebe
JW		 11702019-02-08 Jim Wilson <jimw@sifive.com>
1171
1172 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1173 <bne>: Likewise.
1174
f7dd2fb2
TC		 11752019-02-07 Tamar Christina <tamar.christina@arm.com>
1176
1177 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1178
6456d318
TC		 11792019-02-07 Tamar Christina <tamar.christina@arm.com>
1180
1181 PR binutils/23212
1182 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1183 * aarch64-opc.c (verify_elem_sd): New.
1184 (fields): Add FLD_sz entr.
1185 * aarch64-tbl.h (_SIMD_INSN): New.
1186 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1187 fmulx scalar and vector by element isns.
1188
4a83b610
NC		 11892019-02-07 Nick Clifton <nickc@redhat.com>
1190
1191 * po/sv.po: Updated Swedish translation.
1192
fc60b8c8
AK		 11932019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1194
1195 * s390-mkopc.c (main): Accept arch13 as cpu string.
1196 * s390-opc.c: Add new instruction formats and instruction opcode
1197 masks.
1198 * s390-opc.txt: Add new arch13 instructions.
1199
e10620d3
TC		 12002019-01-25 Sudakshina Das <sudi.das@arm.com>
1201
1202 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1203 (aarch64_opcode): Change encoding for stg, stzg
1204 st2g and st2zg.
1205 * aarch64-asm-2.c: Regenerated.
1206 * aarch64-dis-2.c: Regenerated.
1207 * aarch64-opc-2.c: Regenerated.
1208
20a4ca55
SD		 12092019-01-25 Sudakshina Das <sudi.das@arm.com>
1210
1211 * aarch64-asm-2.c: Regenerated.
1212 * aarch64-dis-2.c: Likewise.
1213 * aarch64-opc-2.c: Likewise.
1214 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1215
550fd7bf
SD		 12162019-01-25 Sudakshina Das <sudi.das@arm.com>
1217 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1218
1219 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1220 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1221 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1222 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1223 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1224 case for ldstgv_indexed.
1225 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1226 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1227 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1228 * aarch64-asm-2.c: Regenerated.
1229 * aarch64-dis-2.c: Regenerated.
1230 * aarch64-opc-2.c: Regenerated.
1231
d9938630
NC		 12322019-01-23 Nick Clifton <nickc@redhat.com>
1233
1234 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1235
375cd423
NC		 12362019-01-21 Nick Clifton <nickc@redhat.com>
1237
1238 * po/de.po: Updated German translation.
1239 * po/uk.po: Updated Ukranian translation.
1240
57299f48
CX		 12412019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1242 * mips-dis.c (mips_arch_choices): Fix typo in
1243 gs464, gs464e and gs264e descriptors.
1244
f48dfe41
NC		 12452019-01-19 Nick Clifton <nickc@redhat.com>
1246
1247 * configure: Regenerate.
1248 * po/opcodes.pot: Regenerate.
1249
f974f26c
NC		 12502018-06-24 Nick Clifton <nickc@redhat.com>
1251
1252 2.32 branch created.
1253
39f286cd
JD		 12542019-01-09 John Darrington <john@darrington.wattle.id.au>
1255
448b8ca8
JD		 1256 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1257 if it is null.
1258 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1259 zero.
1260
3107326d
AP		 12612019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1262
1263 * configure: Regenerate.
1264
7e9ca91e
AM		 12652019-01-07 Alan Modra <amodra@gmail.com>
1266
1267 * configure: Regenerate.
1268 * po/POTFILES.in: Regenerate.
1269
ef1ad42b
JD		 12702019-01-03 John Darrington <john@darrington.wattle.id.au>
1271
1272 * s12z-opc.c: New file.
1273 * s12z-opc.h: New file.
1274 * s12z-dis.c: Removed all code not directly related to display
1275 of instructions. Used the interface provided by the new files
1276 instead.
1277 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1278 * Makefile.in: Regenerate.
ef1ad42b 1279 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1280 * configure: Regenerate.
ef1ad42b 1281
82704155
AM		 12822019-01-01 Alan Modra <amodra@gmail.com>
1283
1284 Update year range in copyright notice of all files.
1285
d5c04e1b 1286For older changes see ChangeLog-2018
3499769a 1287\f
d5c04e1b 1288Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1289
1290Copying and distribution of this file, with or without modification,
1291are permitted in any medium without royalty provided the copyright
1292notice and this notice are preserved.
1293
1294Local Variables:
1295mode: change-log
1296left-margin: 8
1297fill-column: 74
1298version-control: never
1299End:
GDB Binutils - Deliverables
This page took 0.308794 seconds and 4 git commands to generate.