projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 42e6288f MM |
1 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 2 | ||
| 3 | * aarch64-dis-2.c: Regenerate. | |
| 4 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
| 5 | (OP_SVE_BBB): New variant set. | |
| 6 | (OP_SVE_DDDD): New variant set. | |
| 7 | (OP_SVE_HHH): New variant set. | |
| 8 | (OP_SVE_HHHU): New variant set. | |
| 9 | (OP_SVE_SSS): New variant set. | |
| 10 | (OP_SVE_SSSU): New variant set. | |
| 11 | (OP_SVE_SHH): New variant set. | |
| 12 | (OP_SVE_SBBU): New variant set. | |
| 13 | (OP_SVE_DSS): New variant set. | |
| 14 | (OP_SVE_DHHU): New variant set. | |
| 15 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
| 16 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
| 17 | (OP_SVE_VVVU_SD_BH): New variant set. | |
| 18 | (OP_SVE_VVVU_BHSD): New variant set. | |
| 19 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
| 20 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
| 21 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
| 22 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
| 23 | (OP_SVE_VV_BHS_HSD): New variant set. | |
| 24 | (OP_SVE_VVV_SD): New variant set. | |
| 25 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
| 26 | (OP_SVE_VZVV_SD): New variant set. | |
| 27 | (OP_SVE_VZVV_BH): New variant set. | |
| 28 | (OP_SVE_VZV_SD): New variant set. | |
| 29 | (aarch64_opcode_table): Add sve2 instructions. | |
| 30 | ||
| 28ed815a MM |
31 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 32 | ||
| 33 | * aarch64-asm-2.c: Regenerated. | |
| 34 | * aarch64-dis-2.c: Regenerated. | |
| 35 | * aarch64-opc-2.c: Regenerated. | |
| 36 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 37 | for SVE_SHLIMM_UNPRED_22. | |
| 38 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
| 39 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
| 40 | operand. | |
| 41 | ||
| fd1dc4a0 MM |
42 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 43 | ||
| 44 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 45 | sve_size_tsz_bhs iclass encode. | |
| 46 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 47 | sve_size_tsz_bhs iclass decode. | |
| 48 | ||
| 31e36ab3 MM |
49 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 50 | ||
| 51 | * aarch64-asm-2.c: Regenerated. | |
| 52 | * aarch64-dis-2.c: Regenerated. | |
| 53 | * aarch64-opc-2.c: Regenerated. | |
| 54 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 55 | for SVE_Zm4_11_INDEX. | |
| 56 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
| 57 | (fields): Handle SVE_i2h field. | |
| 58 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
| 59 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
| 60 | ||
| 1be5f94f MM |
61 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 62 | ||
| 63 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 64 | sve_shift_tsz_bhsd iclass encode. | |
| 65 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 66 | sve_shift_tsz_bhsd iclass decode. | |
| 67 | ||
| 3c17238b MM |
68 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 69 | ||
| 70 | * aarch64-asm-2.c: Regenerated. | |
| 71 | * aarch64-dis-2.c: Regenerated. | |
| 72 | * aarch64-opc-2.c: Regenerated. | |
| 73 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
| 74 | (aarch64_encode_variant_using_iclass): Handle | |
| 75 | sve_shift_tsz_hsd iclass encode. | |
| 76 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 77 | sve_shift_tsz_hsd iclass decode. | |
| 78 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 79 | for SVE_SHRIMM_UNPRED_22. | |
| 80 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
| 81 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
| 82 | operand. | |
| 83 | ||
| cd50a87a MM |
84 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 85 | ||
| 86 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 87 | sve_size_013 iclass encode. | |
| 88 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 89 | sve_size_013 iclass decode. | |
| 90 | ||
| 3c705960 MM |
91 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 92 | ||
| 93 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 94 | sve_size_bh iclass encode. | |
| 95 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 96 | sve_size_bh iclass decode. | |
| 97 | ||
| 0a57e14f MM |
98 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 99 | ||
| 100 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 101 | sve_size_sd2 iclass encode. | |
| 102 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 103 | sve_size_sd2 iclass decode. | |
| 104 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
| 105 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
| 106 | ||
| c469c864 MM |
107 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 108 | ||
| 109 | * aarch64-asm-2.c: Regenerated. | |
| 110 | * aarch64-dis-2.c: Regenerated. | |
| 111 | * aarch64-opc-2.c: Regenerated. | |
| 112 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 113 | for SVE_ADDR_ZX. | |
| 114 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
| 115 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
| 116 | ||
| 116adc27 MM |
117 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 118 | ||
| 119 | * aarch64-asm-2.c: Regenerated. | |
| 120 | * aarch64-dis-2.c: Regenerated. | |
| 121 | * aarch64-opc-2.c: Regenerated. | |
| 122 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 123 | for SVE_Zm3_11_INDEX. | |
| 124 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
| 125 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
| 126 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
| 127 | fields. | |
| 128 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
| 129 | ||
| 3bd82c86 MM |
130 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 131 | ||
| 132 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 133 | sve_size_hsd2 iclass encode. | |
| 134 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 135 | sve_size_hsd2 iclass decode. | |
| 136 | * aarch64-opc.c (fields): Handle SVE_size field. | |
| 137 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
| 138 | ||
| adccc507 MM |
139 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 140 | ||
| 141 | * aarch64-asm-2.c: Regenerated. | |
| 142 | * aarch64-dis-2.c: Regenerated. | |
| 143 | * aarch64-opc-2.c: Regenerated. | |
| 144 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 145 | for SVE_IMM_ROT3. | |
| 146 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
| 147 | (fields): Handle SVE_rot3 field. | |
| 148 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
| 149 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
| 150 | ||
| 5cd99750 MM |
151 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 152 | ||
| 153 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
| 154 | instructions. | |
| 155 | ||
| 7ce2460a MM |
156 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 157 | ||
| 158 | * aarch64-tbl.h | |
| 159 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
| 160 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
| 161 | aarch64_feature_sve2bitperm): New feature sets. | |
| 162 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
| 163 | for feature set addresses. | |
| 164 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
| 165 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
| 166 | ||
| 41cee089 FS |
167 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
| 168 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 169 | ||
| 170 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
| 171 | argument and set ASE_EVA_R6 appropriately. | |
| 172 | (set_default_mips_dis_options): Pass ISA to above. | |
| 173 | (parse_mips_dis_option): Likewise. | |
| 174 | * mips-opc.c (EVAR6): New macro. | |
| 175 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
| 176 | ||
| b83b4b13 SD |
177 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
| 178 | ||
| 179 | * aarch64-asm-2.c: Regenerated. | |
| 180 | * aarch64-dis-2.c: Regenerated. | |
| 181 | * aarch64-opc-2.c: Regenerated. | |
| 182 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
| 183 | AARCH64_OPND_TME_UIMM16. | |
| 184 | (aarch64_print_operand): Likewise. | |
| 185 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
| 186 | (TME): New. | |
| 187 | (_TME_INSN): New. | |
| 188 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
| 189 | ||
| 4a90ce95 JD |
190 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
| 191 | ||
| 192 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
| 193 | ||
| a45328b9 AB |
194 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
| 195 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 196 | ||
| 197 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
| 198 | ||
| d10be0cb JD |
199 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 200 | ||
| 201 | * s12z-opc.h: Add extern "C" bracketing to help | |
| 202 | users who wish to use this interface in c++ code. | |
| 203 | ||
| a679f24e JD |
204 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 205 | ||
| 206 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
| 207 | "reserved0" mode. | |
| 208 | ||
| 32c36c3c AV |
209 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 210 | ||
| 211 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
| 212 | specifier. Add entries for VLDR and VSTR of system registers. | |
| 213 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
| 214 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
| 215 | of %J and %K format specifier. | |
| 216 | ||
| efd6b359 AV |
217 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 218 | ||
| 219 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
| 220 | Add new entries for VSCCLRM instruction. | |
| 221 | (print_insn_coprocessor): Handle new %C format control code. | |
| 222 | ||
| 6b0dd094 AV |
223 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 224 | ||
| 225 | * arm-dis.c (enum isa): New enum. | |
| 226 | (struct sopcode32): New structure. | |
| 227 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
| 228 | set isa field of all current entries to ANY. | |
| 229 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
| 230 | Only match an entry if its isa field allows the current mode. | |
| 231 | ||
| 4b5a202f AV |
232 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 233 | ||
| 234 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
| 235 | CLRM. | |
| 236 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
| 237 | ||
| 60f993ce AV |
238 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 239 | ||
| 240 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
| 241 | and %Q patterns. | |
| 242 | ||
| f6b2b12d AV |
243 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 244 | ||
| 245 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
| 246 | (print_insn_thumb32): Edit the switch case for %Z. | |
| 247 | ||
| 1889da70 AV |
248 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 249 | ||
| 250 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
| 251 | ||
| 65d1bc05 AV |
252 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 253 | ||
| 254 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
| 255 | ||
| 1caf72a5 AV |
256 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 257 | ||
| 258 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
| 259 | ||
| f1c7f421 AV |
260 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 261 | ||
| 262 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
| 263 | Arm register with r13 and r15 unpredictable. | |
| 264 | (thumb32_opcodes): New instructions for bfx and bflx. | |
| 265 | ||
| 4389b29a AV |
266 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 267 | ||
| 268 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
| 269 | ||
| e5d6e09e AV |
270 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 271 | ||
| 272 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
| 273 | ||
| e12437dc AV |
274 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 275 | ||
| 276 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
| 277 | ||
| 031254f2 AV |
278 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 279 | ||
| 280 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
| 281 | ||
| e5a557ac JD |
282 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
| 283 | ||
| 284 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
| 285 | "optr". ("operator" is a reserved word in c++). | |
| 286 | ||
| bd7ceb8d SD |
287 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 288 | ||
| 289 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
| 290 | AARCH64_OPND_Rt_SP. | |
| 291 | (verify_constraints): Likewise. | |
| 292 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
| 293 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
| 294 | to accept Rt|SP as first operand. | |
| 295 | (AARCH64_OPERANDS): Add new Rt_SP. | |
| 296 | * aarch64-asm-2.c: Regenerated. | |
| 297 | * aarch64-dis-2.c: Regenerated. | |
| 298 | * aarch64-opc-2.c: Regenerated. | |
| 299 | ||
| e54010f1 SD |
300 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 301 | ||
| 302 | * aarch64-asm-2.c: Regenerated. | |
| 303 | * aarch64-dis-2.c: Likewise. | |
| 304 | * aarch64-opc-2.c: Likewise. | |
| 305 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
| 306 | ||
| 7e96e219 RS |
307 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
| 308 | ||
| 309 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
| 310 | ||
| 6f2791d5 L |
311 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
| 312 | ||
| 313 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
| 314 | * i386-init.h: Regenerated. | |
| 315 | ||
| e392bad3 AM |
316 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 317 | ||
| 318 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
| 319 | op_separator to control printing of spaces, comma and parens | |
| 320 | rather than need_comma, need_paren and spaces vars. | |
| 321 | ||
| dffaa15c AM |
322 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 323 | ||
| 324 | PR 24421 | |
| 325 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
| 326 | (print_insn_neon, print_insn_arm): Likewise. | |
| 327 | ||
| d6aab7a1 XG |
328 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
| 329 | ||
| 330 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
| 331 | instructions. | |
| 332 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
| 333 | and EVEX_W_0F3872_P_3. | |
| 334 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
| 335 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
| 336 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
| 337 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
| 338 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
| 339 | * i386-init.h: Regenerated. | |
| 340 | * i386-tbl.h: Likewise. | |
| 341 | ||
| 66e85460 AM |
342 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 343 | ||
| 344 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
| 345 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
| 346 | to favour printing of "-" branch hint when using the "y" bit. | |
| 347 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
| 348 | ||
| c2b1c275 AM |
349 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 350 | ||
| 351 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
| 352 | opcode until first operand is output. | |
| 353 | ||
| aae9718e PB |
354 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
| 355 | ||
| 356 | PR gas/24349 | |
| 357 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
| 358 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
| 359 | (insert_bo): Only error on branch on ctr. | |
| 360 | (get_bo_hint_mask): New function. | |
| 361 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
| 362 | for inserting 'at' branch hints. | |
| 363 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
| 364 | for extracting 'at' branch hints. | |
| 365 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
| 366 | (BOE): Delete operand. | |
| 367 | (BOM, BOP): New operands. | |
| 368 | (RM): Update value. | |
| 369 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
| 370 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
| 371 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
| 372 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
| 373 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
| 374 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
| 375 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
| 376 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
| 377 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
| 378 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
| 379 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
| 380 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
| 381 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
| 382 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
| 383 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
| 384 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
| 385 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
| 386 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
| 387 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
| 388 | bttarl+>: New extended mnemonics. | |
| 389 | ||
| 96a86c01 AM |
390 | 2019-03-28 Alan Modra <amodra@gmail.com> |
| 391 | ||
| 392 | PR 24390 | |
| 393 | * ppc-opc.c (BTF): Define. | |
| 394 | (powerpc_opcodes): Use for mtfsb*. | |
| 395 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
| 396 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
| 397 | ||
| 796d6298 TC |
398 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 399 | ||
| 400 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
| 401 | (mapping_symbol_for_insn): Implement new algorithm. | |
| 402 | (print_insn): Remove duplicate code. | |
| 403 | ||
| 60df3720 TC |
404 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 405 | ||
| 406 | * aarch64-dis.c (print_insn_aarch64): | |
| 407 | Implement override. | |
| 408 | ||
| 51457761 TC |
409 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 410 | ||
| 411 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
| 412 | order. | |
| 413 | ||
| 53b2f36b TC |
414 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 415 | ||
| 416 | * aarch64-dis.c (last_stop_offset): New. | |
| 417 | (print_insn_aarch64): Use stop_offset. | |
| 418 | ||
| 89199bb5 L |
419 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
| 420 | ||
| 421 | PR gas/24359 | |
| 422 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
| 423 | CPU_ANY_AVX2_FLAGS. | |
| 424 | * i386-init.h: Regenerated. | |
| 425 | ||
| 97ed31ae L |
426 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
| 427 | ||
| 428 | PR gas/24348 | |
| 429 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
| 430 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
| 431 | * i386-tbl.h: Regenerated. | |
| 432 | ||
| 0919bfe9 AK |
433 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
| 434 | ||
| 435 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
| 436 | from vstrszb, vstrszh, and vstrszf. | |
| 437 | ||
| 438 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
| 439 | ||
| 440 | * s390-opc.txt: Add instruction descriptions. | |
| 441 | ||
| 21820ebe JW |
442 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
| 443 | ||
| 444 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
| 445 | <bne>: Likewise. | |
| 446 | ||
| f7dd2fb2 TC |
447 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 448 | ||
| 449 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
| 450 | ||
| 6456d318 TC |
451 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 452 | ||
| 453 | PR binutils/23212 | |
| 454 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
| 455 | * aarch64-opc.c (verify_elem_sd): New. | |
| 456 | (fields): Add FLD_sz entr. | |
| 457 | * aarch64-tbl.h (_SIMD_INSN): New. | |
| 458 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
| 459 | fmulx scalar and vector by element isns. | |
| 460 | ||
| 4a83b610 NC |
461 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
| 462 | ||
| 463 | * po/sv.po: Updated Swedish translation. | |
| 464 | ||
| fc60b8c8 AK |
465 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
| 466 | ||
| 467 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
| 468 | * s390-opc.c: Add new instruction formats and instruction opcode | |
| 469 | masks. | |
| 470 | * s390-opc.txt: Add new arch13 instructions. | |
| 471 | ||
| e10620d3 TC |
472 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 473 | ||
| 474 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
| 475 | (aarch64_opcode): Change encoding for stg, stzg | |
| 476 | st2g and st2zg. | |
| 477 | * aarch64-asm-2.c: Regenerated. | |
| 478 | * aarch64-dis-2.c: Regenerated. | |
| 479 | * aarch64-opc-2.c: Regenerated. | |
| 480 | ||
| 20a4ca55 SD |
481 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 482 | ||
| 483 | * aarch64-asm-2.c: Regenerated. | |
| 484 | * aarch64-dis-2.c: Likewise. | |
| 485 | * aarch64-opc-2.c: Likewise. | |
| 486 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
| 487 | ||
| 550fd7bf SD |
488 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 489 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
| 490 | ||
| 491 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
| 492 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
| 493 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
| 494 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
| 495 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
| 496 | case for ldstgv_indexed. | |
| 497 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
| 498 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
| 499 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
| 500 | * aarch64-asm-2.c: Regenerated. | |
| 501 | * aarch64-dis-2.c: Regenerated. | |
| 502 | * aarch64-opc-2.c: Regenerated. | |
| 503 | ||
| d9938630 NC |
504 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
| 505 | ||
| 506 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
| 507 | ||
| 375cd423 NC |
508 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
| 509 | ||
| 510 | * po/de.po: Updated German translation. | |
| 511 | * po/uk.po: Updated Ukranian translation. | |
| 512 | ||
| 57299f48 CX |
513 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
| 514 | * mips-dis.c (mips_arch_choices): Fix typo in | |
| 515 | gs464, gs464e and gs264e descriptors. | |
| 516 | ||
| f48dfe41 NC |
517 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
| 518 | ||
| 519 | * configure: Regenerate. | |
| 520 | * po/opcodes.pot: Regenerate. | |
| 521 | ||
| f974f26c NC |
522 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 523 | ||
| 524 | 2.32 branch created. | |
| 525 | ||
| 39f286cd JD |
526 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
| 527 | ||
| 448b8ca8 JD |
528 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
| 529 | if it is null. | |
| 530 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
| 39f286cd JD |
531 | zero. |
| 532 | ||
| 3107326d AP |
533 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
| 534 | ||
| 535 | * configure: Regenerate. | |
| 536 | ||
| 7e9ca91e AM |
537 | 2019-01-07 Alan Modra <amodra@gmail.com> |
| 538 | ||
| 539 | * configure: Regenerate. | |
| 540 | * po/POTFILES.in: Regenerate. | |
| 541 | ||
| ef1ad42b JD |
542 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
| 543 | ||
| 544 | * s12z-opc.c: New file. | |
| 545 | * s12z-opc.h: New file. | |
| 546 | * s12z-dis.c: Removed all code not directly related to display | |
| 547 | of instructions. Used the interface provided by the new files | |
| 548 | instead. | |
| 549 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
| 7e9ca91e | 550 | * Makefile.in: Regenerate. |
| ef1ad42b | 551 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
| 7e9ca91e | 552 | * configure: Regenerate. |
| ef1ad42b | 553 | |
| 82704155 AM |
554 | 2019-01-01 Alan Modra <amodra@gmail.com> |
| 555 | ||
| 556 | Update year range in copyright notice of all files. | |
| 557 | ||
| d5c04e1b | 558 | For older changes see ChangeLog-2018 |
| 3499769a | 559 | \f |
| d5c04e1b | 560 | Copyright (C) 2019 Free Software Foundation, Inc. |
| 3499769a AM |
561 | |
| 562 | Copying and distribution of this file, with or without modification, | |
| 563 | are permitted in any medium without royalty provided the copyright | |
| 564 | notice and this notice are preserved. | |
| 565 | ||
| 566 | Local Variables: | |
| 567 | mode: change-log | |
| 568 | left-margin: 8 | |
| 569 | fill-column: 74 | |
| 570 | version-control: never | |
| 571 | End: |