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AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension.
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
CommitLineData
a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
e950b345 297 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 298 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 299 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
300 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 301 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 302 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
303 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
304 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
305 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
306 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 307 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 308 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
309 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 310 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
311 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
116b6019
RS		 312 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
313 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 314 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 315 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
316 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 317 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 318 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
319 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
320 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
321 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 322 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
a06ea964
NC		 323};
324
325enum aarch64_operand_class
326aarch64_get_operand_class (enum aarch64_opnd type)
327{
328 return aarch64_operands[type].op_class;
329}
330
331const char *
332aarch64_get_operand_name (enum aarch64_opnd type)
333{
334 return aarch64_operands[type].name;
335}
336
337/* Get operand description string.
338 This is usually for the diagnosis purpose. */
339const char *
340aarch64_get_operand_desc (enum aarch64_opnd type)
341{
342 return aarch64_operands[type].desc;
343}
344
345/* Table of all conditional affixes. */
346const aarch64_cond aarch64_conds[16] =
347{
bb7eff52
RS		 348 {{"eq", "none"}, 0x0},
349 {{"ne", "any"}, 0x1},
350 {{"cs", "hs", "nlast"}, 0x2},
351 {{"cc", "lo", "ul", "last"}, 0x3},
352 {{"mi", "first"}, 0x4},
353 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 354 {{"vs"}, 0x6},
355 {{"vc"}, 0x7},
bb7eff52
RS		 356 {{"hi", "pmore"}, 0x8},
357 {{"ls", "plast"}, 0x9},
358 {{"ge", "tcont"}, 0xa},
359 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 360 {{"gt"}, 0xc},
361 {{"le"}, 0xd},
362 {{"al"}, 0xe},
363 {{"nv"}, 0xf},
364};
365
366const aarch64_cond *
367get_cond_from_value (aarch64_insn value)
368{
369 assert (value < 16);
370 return &aarch64_conds[(unsigned int) value];
371}
372
373const aarch64_cond *
374get_inverted_cond (const aarch64_cond *cond)
375{
376 return &aarch64_conds[cond->value ^ 0x1];
377}
378
379/* Table describing the operand extension/shifting operators; indexed by
380 enum aarch64_modifier_kind.
381
382 The value column provides the most common values for encoding modifiers,
383 which enables table-driven encoding/decoding for the modifiers. */
384const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
385{
386 {"none", 0x0},
387 {"msl", 0x0},
388 {"ror", 0x3},
389 {"asr", 0x2},
390 {"lsr", 0x1},
391 {"lsl", 0x0},
392 {"uxtb", 0x0},
393 {"uxth", 0x1},
394 {"uxtw", 0x2},
395 {"uxtx", 0x3},
396 {"sxtb", 0x4},
397 {"sxth", 0x5},
398 {"sxtw", 0x6},
399 {"sxtx", 0x7},
2442d846 400 {"mul", 0x0},
98907a70 401 {"mul vl", 0x0},
a06ea964
NC		 402 {NULL, 0},
403};
404
405enum aarch64_modifier_kind
406aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
407{
408 return desc - aarch64_operand_modifiers;
409}
410
411aarch64_insn
412aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
413{
414 return aarch64_operand_modifiers[kind].value;
415}
416
417enum aarch64_modifier_kind
418aarch64_get_operand_modifier_from_value (aarch64_insn value,
419 bfd_boolean extend_p)
420{
421 if (extend_p == TRUE)
422 return AARCH64_MOD_UXTB + value;
423 else
424 return AARCH64_MOD_LSL - value;
425}
426
427bfd_boolean
428aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
429{
430 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
431 ? TRUE : FALSE;
432}
433
434static inline bfd_boolean
435aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
436{
437 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
438 ? TRUE : FALSE;
439}
440
441const struct aarch64_name_value_pair aarch64_barrier_options[16] =
442{
443 { "#0x00", 0x0 },
444 { "oshld", 0x1 },
445 { "oshst", 0x2 },
446 { "osh", 0x3 },
447 { "#0x04", 0x4 },
448 { "nshld", 0x5 },
449 { "nshst", 0x6 },
450 { "nsh", 0x7 },
451 { "#0x08", 0x8 },
452 { "ishld", 0x9 },
453 { "ishst", 0xa },
454 { "ish", 0xb },
455 { "#0x0c", 0xc },
456 { "ld", 0xd },
457 { "st", 0xe },
458 { "sy", 0xf },
459};
460
9ed608f9
MW		 461/* Table describing the operands supported by the aliases of the HINT
462 instruction.
463
464 The name column is the operand that is accepted for the alias. The value
465 column is the hint number of the alias. The list of operands is terminated
466 by NULL in the name column. */
467
468const struct aarch64_name_value_pair aarch64_hint_options[] =
469{
ff605452
SD		 470 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
471 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
472 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
473 { "c", HINT_OPD_C }, /* BTI C. */
474 { "j", HINT_OPD_J }, /* BTI J. */
475 { "jc", HINT_OPD_JC }, /* BTI JC. */
476 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 477};
478
a32c3ff8 479/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 480 l -> level: 1-3
481 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 482#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 483const struct aarch64_name_value_pair aarch64_prfops[32] =
484{
485 { "pldl1keep", B(0, 1, 0) },
486 { "pldl1strm", B(0, 1, 1) },
487 { "pldl2keep", B(0, 2, 0) },
488 { "pldl2strm", B(0, 2, 1) },
489 { "pldl3keep", B(0, 3, 0) },
490 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 491 { NULL, 0x06 },
492 { NULL, 0x07 },
a32c3ff8
NC		 493 { "plil1keep", B(1, 1, 0) },
494 { "plil1strm", B(1, 1, 1) },
495 { "plil2keep", B(1, 2, 0) },
496 { "plil2strm", B(1, 2, 1) },
497 { "plil3keep", B(1, 3, 0) },
498 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 499 { NULL, 0x0e },
500 { NULL, 0x0f },
a32c3ff8
NC		 501 { "pstl1keep", B(2, 1, 0) },
502 { "pstl1strm", B(2, 1, 1) },
503 { "pstl2keep", B(2, 2, 0) },
504 { "pstl2strm", B(2, 2, 1) },
505 { "pstl3keep", B(2, 3, 0) },
506 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 507 { NULL, 0x16 },
508 { NULL, 0x17 },
509 { NULL, 0x18 },
510 { NULL, 0x19 },
511 { NULL, 0x1a },
512 { NULL, 0x1b },
513 { NULL, 0x1c },
514 { NULL, 0x1d },
515 { NULL, 0x1e },
516 { NULL, 0x1f },
a06ea964
NC		 517};
518#undef B
519\f
520/* Utilities on value constraint. */
521
522static inline int
523value_in_range_p (int64_t value, int low, int high)
524{
525 return (value >= low && value <= high) ? 1 : 0;
526}
527
98907a70 528/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 529static inline int
530value_aligned_p (int64_t value, int align)
531{
98907a70 532 return (value % align) == 0;
a06ea964
NC		 533}
534
535/* A signed value fits in a field. */
536static inline int
537value_fit_signed_field_p (int64_t value, unsigned width)
538{
539 assert (width < 32);
540 if (width < sizeof (value) * 8)
541 {
542 int64_t lim = (int64_t)1 << (width - 1);
543 if (value >= -lim && value < lim)
544 return 1;
545 }
546 return 0;
547}
548
549/* An unsigned value fits in a field. */
550static inline int
551value_fit_unsigned_field_p (int64_t value, unsigned width)
552{
553 assert (width < 32);
554 if (width < sizeof (value) * 8)
555 {
556 int64_t lim = (int64_t)1 << width;
557 if (value >= 0 && value < lim)
558 return 1;
559 }
560 return 0;
561}
562
563/* Return 1 if OPERAND is SP or WSP. */
564int
565aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
566{
567 return ((aarch64_get_operand_class (operand->type)
568 == AARCH64_OPND_CLASS_INT_REG)
569 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
570 && operand->reg.regno == 31);
571}
572
573/* Return 1 if OPERAND is XZR or WZP. */
574int
575aarch64_zero_register_p (const aarch64_opnd_info *operand)
576{
577 return ((aarch64_get_operand_class (operand->type)
578 == AARCH64_OPND_CLASS_INT_REG)
579 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
580 && operand->reg.regno == 31);
581}
582
583/* Return true if the operand *OPERAND that has the operand code
584 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
585 qualified by the qualifier TARGET. */
586
587static inline int
588operand_also_qualified_p (const struct aarch64_opnd_info *operand,
589 aarch64_opnd_qualifier_t target)
590{
591 switch (operand->qualifier)
592 {
593 case AARCH64_OPND_QLF_W:
594 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
595 return 1;
596 break;
597 case AARCH64_OPND_QLF_X:
598 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
599 return 1;
600 break;
601 case AARCH64_OPND_QLF_WSP:
602 if (target == AARCH64_OPND_QLF_W
603 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
604 return 1;
605 break;
606 case AARCH64_OPND_QLF_SP:
607 if (target == AARCH64_OPND_QLF_X
608 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
609 return 1;
610 break;
611 default:
612 break;
613 }
614
615 return 0;
616}
617
618/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
619 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
620
621 Return NIL if more than one expected qualifiers are found. */
622
623aarch64_opnd_qualifier_t
624aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
625 int idx,
626 const aarch64_opnd_qualifier_t known_qlf,
627 int known_idx)
628{
629 int i, saved_i;
630
631 /* Special case.
632
633 When the known qualifier is NIL, we have to assume that there is only
634 one qualifier sequence in the *QSEQ_LIST and return the corresponding
635 qualifier directly. One scenario is that for instruction
636 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
637 which has only one possible valid qualifier sequence
638 NIL, S_D
639 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
640 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
641
642 Because the qualifier NIL has dual roles in the qualifier sequence:
643 it can mean no qualifier for the operand, or the qualifer sequence is
644 not in use (when all qualifiers in the sequence are NILs), we have to
645 handle this special case here. */
646 if (known_qlf == AARCH64_OPND_NIL)
647 {
648 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
649 return qseq_list[0][idx];
650 }
651
652 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
653 {
654 if (qseq_list[i][known_idx] == known_qlf)
655 {
656 if (saved_i != -1)
657 /* More than one sequences are found to have KNOWN_QLF at
658 KNOWN_IDX. */
659 return AARCH64_OPND_NIL;
660 saved_i = i;
661 }
662 }
663
664 return qseq_list[saved_i][idx];
665}
666
667enum operand_qualifier_kind
668{
669 OQK_NIL,
670 OQK_OPD_VARIANT,
671 OQK_VALUE_IN_RANGE,
672 OQK_MISC,
673};
674
675/* Operand qualifier description. */
676struct operand_qualifier_data
677{
678 /* The usage of the three data fields depends on the qualifier kind. */
679 int data0;
680 int data1;
681 int data2;
682 /* Description. */
683 const char *desc;
684 /* Kind. */
685 enum operand_qualifier_kind kind;
686};
687
688/* Indexed by the operand qualifier enumerators. */
689struct operand_qualifier_data aarch64_opnd_qualifiers[] =
690{
691 {0, 0, 0, "NIL", OQK_NIL},
692
693 /* Operand variant qualifiers.
694 First 3 fields:
695 element size, number of elements and common value for encoding. */
696
697 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
698 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
699 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
700 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
701
702 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
703 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
704 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
705 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
706 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 707 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964 708
a3b3345a 709 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 710 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
711 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 712 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 713 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
714 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
715 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
716 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
717 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
718 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
719 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
720
d50c751e
RS		 721 {0, 0, 0, "z", OQK_OPD_VARIANT},
722 {0, 0, 0, "m", OQK_OPD_VARIANT},
723
fb3265b3
SD		 724 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
725 {16, 0, 0, "tag", OQK_OPD_VARIANT},
726
a06ea964
NC		 727 /* Qualifiers constraining the value range.
728 First 3 fields:
729 Lower bound, higher bound, unused. */
730
a6a51754 731 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 732 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
733 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
734 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
735 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
736 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
737 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
738
739 /* Qualifiers for miscellaneous purpose.
740 First 3 fields:
741 unused, unused and unused. */
742
743 {0, 0, 0, "lsl", 0},
744 {0, 0, 0, "msl", 0},
745
746 {0, 0, 0, "retrieving", 0},
747};
748
749static inline bfd_boolean
750operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
751{
752 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
753 ? TRUE : FALSE;
754}
755
756static inline bfd_boolean
757qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
758{
759 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
760 ? TRUE : FALSE;
761}
762
763const char*
764aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
765{
766 return aarch64_opnd_qualifiers[qualifier].desc;
767}
768
769/* Given an operand qualifier, return the expected data element size
770 of a qualified operand. */
771unsigned char
772aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
773{
774 assert (operand_variant_qualifier_p (qualifier) == TRUE);
775 return aarch64_opnd_qualifiers[qualifier].data0;
776}
777
778unsigned char
779aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
780{
781 assert (operand_variant_qualifier_p (qualifier) == TRUE);
782 return aarch64_opnd_qualifiers[qualifier].data1;
783}
784
785aarch64_insn
786aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
787{
788 assert (operand_variant_qualifier_p (qualifier) == TRUE);
789 return aarch64_opnd_qualifiers[qualifier].data2;
790}
791
792static int
793get_lower_bound (aarch64_opnd_qualifier_t qualifier)
794{
795 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
796 return aarch64_opnd_qualifiers[qualifier].data0;
797}
798
799static int
800get_upper_bound (aarch64_opnd_qualifier_t qualifier)
801{
802 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
803 return aarch64_opnd_qualifiers[qualifier].data1;
804}
805
806#ifdef DEBUG_AARCH64
807void
808aarch64_verbose (const char *str, ...)
809{
810 va_list ap;
811 va_start (ap, str);
812 printf ("#### ");
813 vprintf (str, ap);
814 printf ("\n");
815 va_end (ap);
816}
817
818static inline void
819dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
820{
821 int i;
822 printf ("#### \t");
823 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
824 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
825 printf ("\n");
826}
827
828static void
829dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
830 const aarch64_opnd_qualifier_t *qualifier)
831{
832 int i;
833 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
834
835 aarch64_verbose ("dump_match_qualifiers:");
836 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
837 curr[i] = opnd[i].qualifier;
838 dump_qualifier_sequence (curr);
839 aarch64_verbose ("against");
840 dump_qualifier_sequence (qualifier);
841}
842#endif /* DEBUG_AARCH64 */
843
a68f4cd2
TC		 844/* This function checks if the given instruction INSN is a destructive
845 instruction based on the usage of the registers. It does not recognize
846 unary destructive instructions. */
847bfd_boolean
848aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
849{
850 int i = 0;
851 const enum aarch64_opnd *opnds = opcode->operands;
852
853 if (opnds[0] == AARCH64_OPND_NIL)
854 return FALSE;
855
856 while (opnds[++i] != AARCH64_OPND_NIL)
857 if (opnds[i] == opnds[0])
858 return TRUE;
859
860 return FALSE;
861}
862
a06ea964
NC		 863/* TODO improve this, we can have an extra field at the runtime to
864 store the number of operands rather than calculating it every time. */
865
866int
867aarch64_num_of_operands (const aarch64_opcode *opcode)
868{
869 int i = 0;
870 const enum aarch64_opnd *opnds = opcode->operands;
871 while (opnds[i++] != AARCH64_OPND_NIL)
872 ;
873 --i;
874 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
875 return i;
876}
877
878/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
879 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
880
881 N.B. on the entry, it is very likely that only some operands in *INST
882 have had their qualifiers been established.
883
884 If STOP_AT is not -1, the function will only try to match
885 the qualifier sequence for operands before and including the operand
886 of index STOP_AT; and on success *RET will only be filled with the first
887 (STOP_AT+1) qualifiers.
888
889 A couple examples of the matching algorithm:
890
891 X,W,NIL should match
892 X,W,NIL
893
894 NIL,NIL should match
895 X ,NIL
896
897 Apart from serving the main encoding routine, this can also be called
898 during or after the operand decoding. */
899
900int
901aarch64_find_best_match (const aarch64_inst *inst,
902 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
903 int stop_at, aarch64_opnd_qualifier_t *ret)
904{
905 int found = 0;
906 int i, num_opnds;
907 const aarch64_opnd_qualifier_t *qualifiers;
908
909 num_opnds = aarch64_num_of_operands (inst->opcode);
910 if (num_opnds == 0)
911 {
912 DEBUG_TRACE ("SUCCEED: no operand");
913 return 1;
914 }
915
916 if (stop_at < 0 || stop_at >= num_opnds)
917 stop_at = num_opnds - 1;
918
919 /* For each pattern. */
920 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
921 {
922 int j;
923 qualifiers = *qualifiers_list;
924
925 /* Start as positive. */
926 found = 1;
927
928 DEBUG_TRACE ("%d", i);
929#ifdef DEBUG_AARCH64
930 if (debug_dump)
931 dump_match_qualifiers (inst->operands, qualifiers);
932#endif
933
934 /* Most opcodes has much fewer patterns in the list.
935 First NIL qualifier indicates the end in the list. */
936 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
937 {
938 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
939 if (i)
940 found = 0;
941 break;
942 }
943
944 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
945 {
946 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
947 {
948 /* Either the operand does not have qualifier, or the qualifier
949 for the operand needs to be deduced from the qualifier
950 sequence.
951 In the latter case, any constraint checking related with
952 the obtained qualifier should be done later in
953 operand_general_constraint_met_p. */
954 continue;
955 }
956 else if (*qualifiers != inst->operands[j].qualifier)
957 {
958 /* Unless the target qualifier can also qualify the operand
959 (which has already had a non-nil qualifier), non-equal
960 qualifiers are generally un-matched. */
961 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
962 continue;
963 else
964 {
965 found = 0;
966 break;
967 }
968 }
969 else
970 continue; /* Equal qualifiers are certainly matched. */
971 }
972
973 /* Qualifiers established. */
974 if (found == 1)
975 break;
976 }
977
978 if (found == 1)
979 {
980 /* Fill the result in *RET. */
981 int j;
982 qualifiers = *qualifiers_list;
983
984 DEBUG_TRACE ("complete qualifiers using list %d", i);
985#ifdef DEBUG_AARCH64
986 if (debug_dump)
987 dump_qualifier_sequence (qualifiers);
988#endif
989
990 for (j = 0; j <= stop_at; ++j, ++qualifiers)
991 ret[j] = *qualifiers;
992 for (; j < AARCH64_MAX_OPND_NUM; ++j)
993 ret[j] = AARCH64_OPND_QLF_NIL;
994
995 DEBUG_TRACE ("SUCCESS");
996 return 1;
997 }
998
999 DEBUG_TRACE ("FAIL");
1000 return 0;
1001}
1002
1003/* Operand qualifier matching and resolving.
1004
1005 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1006 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1007
1008 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1009 succeeds. */
1010
1011static int
1012match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1013{
4989adac 1014 int i, nops;
a06ea964
NC		 1015 aarch64_opnd_qualifier_seq_t qualifiers;
1016
1017 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1018 qualifiers))
1019 {
1020 DEBUG_TRACE ("matching FAIL");
1021 return 0;
1022 }
1023
4989adac
RS		 1024 if (inst->opcode->flags & F_STRICT)
1025 {
1026 /* Require an exact qualifier match, even for NIL qualifiers. */
1027 nops = aarch64_num_of_operands (inst->opcode);
1028 for (i = 0; i < nops; ++i)
1029 if (inst->operands[i].qualifier != qualifiers[i])
1030 return FALSE;
1031 }
1032
a06ea964
NC		 1033 /* Update the qualifiers. */
1034 if (update_p == TRUE)
1035 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1036 {
1037 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1038 break;
1039 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1040 "update %s with %s for operand %d",
1041 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1042 aarch64_get_qualifier_name (qualifiers[i]), i);
1043 inst->operands[i].qualifier = qualifiers[i];
1044 }
1045
1046 DEBUG_TRACE ("matching SUCCESS");
1047 return 1;
1048}
1049
1050/* Return TRUE if VALUE is a wide constant that can be moved into a general
1051 register by MOVZ.
1052
1053 IS32 indicates whether value is a 32-bit immediate or not.
1054 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1055 amount will be returned in *SHIFT_AMOUNT. */
1056
1057bfd_boolean
1058aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1059{
1060 int amount;
1061
1062 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1063
1064 if (is32)
1065 {
1066 /* Allow all zeros or all ones in top 32-bits, so that
1067 32-bit constant expressions like ~0x80000000 are
1068 permitted. */
1069 uint64_t ext = value;
1070 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1071 /* Immediate out of range. */
1072 return FALSE;
1073 value &= (int64_t) 0xffffffff;
1074 }
1075
1076 /* first, try movz then movn */
1077 amount = -1;
1078 if ((value & ((int64_t) 0xffff << 0)) == value)
1079 amount = 0;
1080 else if ((value & ((int64_t) 0xffff << 16)) == value)
1081 amount = 16;
1082 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1083 amount = 32;
1084 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1085 amount = 48;
1086
1087 if (amount == -1)
1088 {
1089 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1090 return FALSE;
1091 }
1092
1093 if (shift_amount != NULL)
1094 *shift_amount = amount;
1095
1096 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1097
1098 return TRUE;
1099}
1100
1101/* Build the accepted values for immediate logical SIMD instructions.
1102
1103 The standard encodings of the immediate value are:
1104 N imms immr SIMD size R S
1105 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1106 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1107 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1108 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1109 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1110 0 11110s 00000r 2 UInt(r) UInt(s)
1111 where all-ones value of S is reserved.
1112
1113 Let's call E the SIMD size.
1114
1115 The immediate value is: S+1 bits '1' rotated to the right by R.
1116
1117 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1118 (remember S != E - 1). */
1119
1120#define TOTAL_IMM_NB 5334
1121
1122typedef struct
1123{
1124 uint64_t imm;
1125 aarch64_insn encoding;
1126} simd_imm_encoding;
1127
1128static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1129
1130static int
1131simd_imm_encoding_cmp(const void *i1, const void *i2)
1132{
1133 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1134 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1135
1136 if (imm1->imm < imm2->imm)
1137 return -1;
1138 if (imm1->imm > imm2->imm)
1139 return +1;
1140 return 0;
1141}
1142
1143/* immediate bitfield standard encoding
1144 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1145 1 ssssss rrrrrr 64 rrrrrr ssssss
1146 0 0sssss 0rrrrr 32 rrrrr sssss
1147 0 10ssss 00rrrr 16 rrrr ssss
1148 0 110sss 000rrr 8 rrr sss
1149 0 1110ss 0000rr 4 rr ss
1150 0 11110s 00000r 2 r s */
1151static inline int
1152encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1153{
1154 return (is64 << 12) | (r << 6) | s;
1155}
1156
1157static void
1158build_immediate_table (void)
1159{
1160 uint32_t log_e, e, s, r, s_mask;
1161 uint64_t mask, imm;
1162 int nb_imms;
1163 int is64;
1164
1165 nb_imms = 0;
1166 for (log_e = 1; log_e <= 6; log_e++)
1167 {
1168 /* Get element size. */
1169 e = 1u << log_e;
1170 if (log_e == 6)
1171 {
1172 is64 = 1;
1173 mask = 0xffffffffffffffffull;
1174 s_mask = 0;
1175 }
1176 else
1177 {
1178 is64 = 0;
1179 mask = (1ull << e) - 1;
1180 /* log_e s_mask
1181 1 ((1 << 4) - 1) << 2 = 111100
1182 2 ((1 << 3) - 1) << 3 = 111000
1183 3 ((1 << 2) - 1) << 4 = 110000
1184 4 ((1 << 1) - 1) << 5 = 100000
1185 5 ((1 << 0) - 1) << 6 = 000000 */
1186 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1187 }
1188 for (s = 0; s < e - 1; s++)
1189 for (r = 0; r < e; r++)
1190 {
1191 /* s+1 consecutive bits to 1 (s < 63) */
1192 imm = (1ull << (s + 1)) - 1;
1193 /* rotate right by r */
1194 if (r != 0)
1195 imm = (imm >> r) | ((imm << (e - r)) & mask);
1196 /* replicate the constant depending on SIMD size */
1197 switch (log_e)
1198 {
1199 case 1: imm = (imm << 2) | imm;
1a0670f3 1200 /* Fall through. */
a06ea964 1201 case 2: imm = (imm << 4) | imm;
1a0670f3 1202 /* Fall through. */
a06ea964 1203 case 3: imm = (imm << 8) | imm;
1a0670f3 1204 /* Fall through. */
a06ea964 1205 case 4: imm = (imm << 16) | imm;
1a0670f3 1206 /* Fall through. */
a06ea964 1207 case 5: imm = (imm << 32) | imm;
1a0670f3 1208 /* Fall through. */
a06ea964
NC		 1209 case 6: break;
1210 default: abort ();
1211 }
1212 simd_immediates[nb_imms].imm = imm;
1213 simd_immediates[nb_imms].encoding =
1214 encode_immediate_bitfield(is64, s | s_mask, r);
1215 nb_imms++;
1216 }
1217 }
1218 assert (nb_imms == TOTAL_IMM_NB);
1219 qsort(simd_immediates, nb_imms,
1220 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1221}
1222
1223/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1224 be accepted by logical (immediate) instructions
1225 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1226
42408347 1227 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1228 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1229 VALUE will be returned in *ENCODING. */
1230
1231bfd_boolean
42408347 1232aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1233{
1234 simd_imm_encoding imm_enc;
1235 const simd_imm_encoding *imm_encoding;
1236 static bfd_boolean initialized = FALSE;
42408347
RS		 1237 uint64_t upper;
1238 int i;
a06ea964 1239
957f6b39
TC		 1240 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1241 value, esize);
a06ea964 1242
535b785f 1243 if (!initialized)
a06ea964
NC		 1244 {
1245 build_immediate_table ();
1246 initialized = TRUE;
1247 }
1248
42408347
RS		 1249 /* Allow all zeros or all ones in top bits, so that
1250 constant expressions like ~1 are permitted. */
1251 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1252 if ((value & ~upper) != value && (value | upper) != value)
1253 return FALSE;
7e105031 1254
42408347
RS		 1255 /* Replicate to a full 64-bit value. */
1256 value &= ~upper;
1257 for (i = esize * 8; i < 64; i *= 2)
1258 value |= (value << i);
a06ea964
NC		 1259
1260 imm_enc.imm = value;
1261 imm_encoding = (const simd_imm_encoding *)
1262 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1263 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1264 if (imm_encoding == NULL)
1265 {
1266 DEBUG_TRACE ("exit with FALSE");
1267 return FALSE;
1268 }
1269 if (encoding != NULL)
1270 *encoding = imm_encoding->encoding;
1271 DEBUG_TRACE ("exit with TRUE");
1272 return TRUE;
1273}
1274
1275/* If 64-bit immediate IMM is in the format of
1276 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1277 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1278 of value "abcdefgh". Otherwise return -1. */
1279int
1280aarch64_shrink_expanded_imm8 (uint64_t imm)
1281{
1282 int i, ret;
1283 uint32_t byte;
1284
1285 ret = 0;
1286 for (i = 0; i < 8; i++)
1287 {
1288 byte = (imm >> (8 * i)) & 0xff;
1289 if (byte == 0xff)
1290 ret |= 1 << i;
1291 else if (byte != 0x00)
1292 return -1;
1293 }
1294 return ret;
1295}
1296
1297/* Utility inline functions for operand_general_constraint_met_p. */
1298
1299static inline void
1300set_error (aarch64_operand_error *mismatch_detail,
1301 enum aarch64_operand_error_kind kind, int idx,
1302 const char* error)
1303{
1304 if (mismatch_detail == NULL)
1305 return;
1306 mismatch_detail->kind = kind;
1307 mismatch_detail->index = idx;
1308 mismatch_detail->error = error;
1309}
1310
4e50d5f8
YZ		 1311static inline void
1312set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1313 const char* error)
1314{
1315 if (mismatch_detail == NULL)
1316 return;
1317 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1318}
1319
a06ea964
NC		 1320static inline void
1321set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1322 int idx, int lower_bound, int upper_bound,
1323 const char* error)
1324{
1325 if (mismatch_detail == NULL)
1326 return;
1327 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1328 mismatch_detail->data[0] = lower_bound;
1329 mismatch_detail->data[1] = upper_bound;
1330}
1331
1332static inline void
1333set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1334 int idx, int lower_bound, int upper_bound)
1335{
1336 if (mismatch_detail == NULL)
1337 return;
1338 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1339 _("immediate value"));
1340}
1341
1342static inline void
1343set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1344 int idx, int lower_bound, int upper_bound)
1345{
1346 if (mismatch_detail == NULL)
1347 return;
1348 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1349 _("immediate offset"));
1350}
1351
1352static inline void
1353set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1354 int idx, int lower_bound, int upper_bound)
1355{
1356 if (mismatch_detail == NULL)
1357 return;
1358 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1359 _("register number"));
1360}
1361
1362static inline void
1363set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1364 int idx, int lower_bound, int upper_bound)
1365{
1366 if (mismatch_detail == NULL)
1367 return;
1368 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1369 _("register element index"));
1370}
1371
1372static inline void
1373set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1374 int idx, int lower_bound, int upper_bound)
1375{
1376 if (mismatch_detail == NULL)
1377 return;
1378 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1379 _("shift amount"));
1380}
1381
2442d846
RS		 1382/* Report that the MUL modifier in operand IDX should be in the range
1383 [LOWER_BOUND, UPPER_BOUND]. */
1384static inline void
1385set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1386 int idx, int lower_bound, int upper_bound)
1387{
1388 if (mismatch_detail == NULL)
1389 return;
1390 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1391 _("multiplier"));
1392}
1393
a06ea964
NC		 1394static inline void
1395set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1396 int alignment)
1397{
1398 if (mismatch_detail == NULL)
1399 return;
1400 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1401 mismatch_detail->data[0] = alignment;
1402}
1403
1404static inline void
1405set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1406 int expected_num)
1407{
1408 if (mismatch_detail == NULL)
1409 return;
1410 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1411 mismatch_detail->data[0] = expected_num;
1412}
1413
1414static inline void
1415set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1416 const char* error)
1417{
1418 if (mismatch_detail == NULL)
1419 return;
1420 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1421}
1422
1423/* General constraint checking based on operand code.
1424
1425 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1426 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1427
1428 This function has to be called after the qualifiers for all operands
1429 have been resolved.
1430
1431 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1432 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1433 of error message during the disassembling where error message is not
1434 wanted. We avoid the dynamic construction of strings of error messages
1435 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1436 use a combination of error code, static string and some integer data to
1437 represent an error. */
1438
1439static int
1440operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1441 enum aarch64_opnd type,
1442 const aarch64_opcode *opcode,
1443 aarch64_operand_error *mismatch_detail)
1444{
e950b345 1445 unsigned num, modifiers, shift;
a06ea964 1446 unsigned char size;
4df068de 1447 int64_t imm, min_value, max_value;
e950b345 1448 uint64_t uvalue, mask;
a06ea964
NC		 1449 const aarch64_opnd_info *opnd = opnds + idx;
1450 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1451
1452 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1453
1454 switch (aarch64_operands[type].op_class)
1455 {
1456 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1457 /* Check pair reg constraints for cas* instructions. */
1458 if (type == AARCH64_OPND_PAIRREG)
1459 {
1460 assert (idx == 1 || idx == 3);
1461 if (opnds[idx - 1].reg.regno % 2 != 0)
1462 {
1463 set_syntax_error (mismatch_detail, idx - 1,
1464 _("reg pair must start from even reg"));
1465 return 0;
1466 }
1467 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1468 {
1469 set_syntax_error (mismatch_detail, idx,
1470 _("reg pair must be contiguous"));
1471 return 0;
1472 }
1473 break;
1474 }
1475
a06ea964
NC		 1476 /* <Xt> may be optional in some IC and TLBI instructions. */
1477 if (type == AARCH64_OPND_Rt_SYS)
1478 {
1479 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1480 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1481 if (opnds[1].present
1482 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1483 {
1484 set_other_error (mismatch_detail, idx, _("extraneous register"));
1485 return 0;
1486 }
ea2deeec
MW		 1487 if (!opnds[1].present
1488 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1489 {
1490 set_other_error (mismatch_detail, idx, _("missing register"));
1491 return 0;
1492 }
1493 }
1494 switch (qualifier)
1495 {
1496 case AARCH64_OPND_QLF_WSP:
1497 case AARCH64_OPND_QLF_SP:
1498 if (!aarch64_stack_pointer_p (opnd))
1499 {
1500 set_other_error (mismatch_detail, idx,
1501 _("stack pointer register expected"));
1502 return 0;
1503 }
1504 break;
1505 default:
1506 break;
1507 }
1508 break;
1509
f11ad6bc
RS		 1510 case AARCH64_OPND_CLASS_SVE_REG:
1511 switch (type)
1512 {
582e12bf
RS		 1513 case AARCH64_OPND_SVE_Zm3_INDEX:
1514 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1515 case AARCH64_OPND_SVE_Zm4_INDEX:
1516 size = get_operand_fields_width (get_operand_from_code (type));
1517 shift = get_operand_specific_data (&aarch64_operands[type]);
1518 mask = (1 << shift) - 1;
1519 if (opnd->reg.regno > mask)
1520 {
1521 assert (mask == 7 || mask == 15);
1522 set_other_error (mismatch_detail, idx,
1523 mask == 15
1524 ? _("z0-z15 expected")
1525 : _("z0-z7 expected"));
1526 return 0;
1527 }
1528 mask = (1 << (size - shift)) - 1;
1529 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1530 {
1531 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1532 return 0;
1533 }
1534 break;
1535
f11ad6bc
RS		 1536 case AARCH64_OPND_SVE_Zn_INDEX:
1537 size = aarch64_get_qualifier_esize (opnd->qualifier);
1538 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1539 {
1540 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1541 0, 64 / size - 1);
1542 return 0;
1543 }
1544 break;
1545
1546 case AARCH64_OPND_SVE_ZnxN:
1547 case AARCH64_OPND_SVE_ZtxN:
1548 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1549 {
1550 set_other_error (mismatch_detail, idx,
1551 _("invalid register list"));
1552 return 0;
1553 }
1554 break;
1555
1556 default:
1557 break;
1558 }
1559 break;
1560
1561 case AARCH64_OPND_CLASS_PRED_REG:
1562 if (opnd->reg.regno >= 8
1563 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1564 {
1565 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1566 return 0;
1567 }
1568 break;
1569
68a64283
YZ		 1570 case AARCH64_OPND_CLASS_COND:
1571 if (type == AARCH64_OPND_COND1
1572 && (opnds[idx].cond->value & 0xe) == 0xe)
1573 {
1574 /* Not allow AL or NV. */
1575 set_syntax_error (mismatch_detail, idx, NULL);
1576 }
1577 break;
1578
a06ea964
NC		 1579 case AARCH64_OPND_CLASS_ADDRESS:
1580 /* Check writeback. */
1581 switch (opcode->iclass)
1582 {
1583 case ldst_pos:
1584 case ldst_unscaled:
1585 case ldstnapair_offs:
1586 case ldstpair_off:
1587 case ldst_unpriv:
1588 if (opnd->addr.writeback == 1)
1589 {
4e50d5f8
YZ		 1590 set_syntax_error (mismatch_detail, idx,
1591 _("unexpected address writeback"));
a06ea964
NC		 1592 return 0;
1593 }
1594 break;
3f06e550
SN		 1595 case ldst_imm10:
1596 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1597 {
1598 set_syntax_error (mismatch_detail, idx,
1599 _("unexpected address writeback"));
1600 return 0;
1601 }
1602 break;
a06ea964
NC		 1603 case ldst_imm9:
1604 case ldstpair_indexed:
1605 case asisdlsep:
1606 case asisdlsop:
1607 if (opnd->addr.writeback == 0)
1608 {
4e50d5f8
YZ		 1609 set_syntax_error (mismatch_detail, idx,
1610 _("address writeback expected"));
a06ea964
NC		 1611 return 0;
1612 }
1613 break;
1614 default:
1615 assert (opnd->addr.writeback == 0);
1616 break;
1617 }
1618 switch (type)
1619 {
1620 case AARCH64_OPND_ADDR_SIMM7:
1621 /* Scaled signed 7 bits immediate offset. */
1622 /* Get the size of the data element that is accessed, which may be
1623 different from that of the source register size,
1624 e.g. in strb/ldrb. */
1625 size = aarch64_get_qualifier_esize (opnd->qualifier);
1626 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1627 {
1628 set_offset_out_of_range_error (mismatch_detail, idx,
1629 -64 * size, 63 * size);
1630 return 0;
1631 }
1632 if (!value_aligned_p (opnd->addr.offset.imm, size))
1633 {
1634 set_unaligned_error (mismatch_detail, idx, size);
1635 return 0;
1636 }
1637 break;
f42f1a1d 1638 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1639 case AARCH64_OPND_ADDR_SIMM9:
1640 /* Unscaled signed 9 bits immediate offset. */
1641 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1642 {
1643 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1644 return 0;
1645 }
1646 break;
1647
1648 case AARCH64_OPND_ADDR_SIMM9_2:
1649 /* Unscaled signed 9 bits immediate offset, which has to be negative
1650 or unaligned. */
1651 size = aarch64_get_qualifier_esize (qualifier);
1652 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1653 && !value_aligned_p (opnd->addr.offset.imm, size))
1654 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1655 return 1;
1656 set_other_error (mismatch_detail, idx,
1657 _("negative or unaligned offset expected"));
1658 return 0;
1659
3f06e550
SN		 1660 case AARCH64_OPND_ADDR_SIMM10:
1661 /* Scaled signed 10 bits immediate offset. */
1662 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1663 {
1664 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1665 return 0;
1666 }
1667 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1668 {
1669 set_unaligned_error (mismatch_detail, idx, 8);
1670 return 0;
1671 }
1672 break;
1673
fb3265b3
SD		 1674 case AARCH64_OPND_ADDR_SIMM11:
1675 /* Signed 11 bits immediate offset (multiple of 16). */
1676 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1677 {
1678 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1679 return 0;
1680 }
1681
1682 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1683 {
1684 set_unaligned_error (mismatch_detail, idx, 16);
1685 return 0;
1686 }
1687 break;
1688
1689 case AARCH64_OPND_ADDR_SIMM13:
1690 /* Signed 13 bits immediate offset (multiple of 16). */
1691 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1692 {
1693 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1694 return 0;
1695 }
1696
1697 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1698 {
1699 set_unaligned_error (mismatch_detail, idx, 16);
1700 return 0;
1701 }
1702 break;
1703
a06ea964
NC		 1704 case AARCH64_OPND_SIMD_ADDR_POST:
1705 /* AdvSIMD load/store multiple structures, post-index. */
1706 assert (idx == 1);
1707 if (opnd->addr.offset.is_reg)
1708 {
1709 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1710 return 1;
1711 else
1712 {
1713 set_other_error (mismatch_detail, idx,
1714 _("invalid register offset"));
1715 return 0;
1716 }
1717 }
1718 else
1719 {
1720 const aarch64_opnd_info *prev = &opnds[idx-1];
1721 unsigned num_bytes; /* total number of bytes transferred. */
1722 /* The opcode dependent area stores the number of elements in
1723 each structure to be loaded/stored. */
1724 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1725 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1726 /* Special handling of loading single structure to all lane. */
1727 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1728 * aarch64_get_qualifier_esize (prev->qualifier);
1729 else
1730 num_bytes = prev->reglist.num_regs
1731 * aarch64_get_qualifier_esize (prev->qualifier)
1732 * aarch64_get_qualifier_nelem (prev->qualifier);
1733 if ((int) num_bytes != opnd->addr.offset.imm)
1734 {
1735 set_other_error (mismatch_detail, idx,
1736 _("invalid post-increment amount"));
1737 return 0;
1738 }
1739 }
1740 break;
1741
1742 case AARCH64_OPND_ADDR_REGOFF:
1743 /* Get the size of the data element that is accessed, which may be
1744 different from that of the source register size,
1745 e.g. in strb/ldrb. */
1746 size = aarch64_get_qualifier_esize (opnd->qualifier);
1747 /* It is either no shift or shift by the binary logarithm of SIZE. */
1748 if (opnd->shifter.amount != 0
1749 && opnd->shifter.amount != (int)get_logsz (size))
1750 {
1751 set_other_error (mismatch_detail, idx,
1752 _("invalid shift amount"));
1753 return 0;
1754 }
1755 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1756 operators. */
1757 switch (opnd->shifter.kind)
1758 {
1759 case AARCH64_MOD_UXTW:
1760 case AARCH64_MOD_LSL:
1761 case AARCH64_MOD_SXTW:
1762 case AARCH64_MOD_SXTX: break;
1763 default:
1764 set_other_error (mismatch_detail, idx,
1765 _("invalid extend/shift operator"));
1766 return 0;
1767 }
1768 break;
1769
1770 case AARCH64_OPND_ADDR_UIMM12:
1771 imm = opnd->addr.offset.imm;
1772 /* Get the size of the data element that is accessed, which may be
1773 different from that of the source register size,
1774 e.g. in strb/ldrb. */
1775 size = aarch64_get_qualifier_esize (qualifier);
1776 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1777 {
1778 set_offset_out_of_range_error (mismatch_detail, idx,
1779 0, 4095 * size);
1780 return 0;
1781 }
9de794e1 1782 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1783 {
1784 set_unaligned_error (mismatch_detail, idx, size);
1785 return 0;
1786 }
1787 break;
1788
1789 case AARCH64_OPND_ADDR_PCREL14:
1790 case AARCH64_OPND_ADDR_PCREL19:
1791 case AARCH64_OPND_ADDR_PCREL21:
1792 case AARCH64_OPND_ADDR_PCREL26:
1793 imm = opnd->imm.value;
1794 if (operand_need_shift_by_two (get_operand_from_code (type)))
1795 {
1796 /* The offset value in a PC-relative branch instruction is alway
1797 4-byte aligned and is encoded without the lowest 2 bits. */
1798 if (!value_aligned_p (imm, 4))
1799 {
1800 set_unaligned_error (mismatch_detail, idx, 4);
1801 return 0;
1802 }
1803 /* Right shift by 2 so that we can carry out the following check
1804 canonically. */
1805 imm >>= 2;
1806 }
1807 size = get_operand_fields_width (get_operand_from_code (type));
1808 if (!value_fit_signed_field_p (imm, size))
1809 {
1810 set_other_error (mismatch_detail, idx,
1811 _("immediate out of range"));
1812 return 0;
1813 }
1814 break;
1815
98907a70
RS		 1816 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1817 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1818 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1819 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1820 min_value = -8;
1821 max_value = 7;
1822 sve_imm_offset_vl:
1823 assert (!opnd->addr.offset.is_reg);
1824 assert (opnd->addr.preind);
1825 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1826 min_value *= num;
1827 max_value *= num;
1828 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1829 || (opnd->shifter.operator_present
1830 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1831 {
1832 set_other_error (mismatch_detail, idx,
1833 _("invalid addressing mode"));
1834 return 0;
1835 }
1836 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1837 {
1838 set_offset_out_of_range_error (mismatch_detail, idx,
1839 min_value, max_value);
1840 return 0;
1841 }
1842 if (!value_aligned_p (opnd->addr.offset.imm, num))
1843 {
1844 set_unaligned_error (mismatch_detail, idx, num);
1845 return 0;
1846 }
1847 break;
1848
1849 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1850 min_value = -32;
1851 max_value = 31;
1852 goto sve_imm_offset_vl;
1853
1854 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1855 min_value = -256;
1856 max_value = 255;
1857 goto sve_imm_offset_vl;
1858
4df068de
RS		 1859 case AARCH64_OPND_SVE_ADDR_RI_U6:
1860 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1861 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1862 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1863 min_value = 0;
1864 max_value = 63;
1865 sve_imm_offset:
1866 assert (!opnd->addr.offset.is_reg);
1867 assert (opnd->addr.preind);
1868 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1869 min_value *= num;
1870 max_value *= num;
1871 if (opnd->shifter.operator_present
1872 || opnd->shifter.amount_present)
1873 {
1874 set_other_error (mismatch_detail, idx,
1875 _("invalid addressing mode"));
1876 return 0;
1877 }
1878 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1879 {
1880 set_offset_out_of_range_error (mismatch_detail, idx,
1881 min_value, max_value);
1882 return 0;
1883 }
1884 if (!value_aligned_p (opnd->addr.offset.imm, num))
1885 {
1886 set_unaligned_error (mismatch_detail, idx, num);
1887 return 0;
1888 }
1889 break;
1890
582e12bf
RS		 1891 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1892 min_value = -8;
1893 max_value = 7;
1894 goto sve_imm_offset;
1895
c8d59609 1896 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1897 case AARCH64_OPND_SVE_ADDR_RR:
1898 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1899 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1900 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1901 case AARCH64_OPND_SVE_ADDR_RX:
1902 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1903 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1904 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1905 case AARCH64_OPND_SVE_ADDR_RZ:
1906 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1907 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1908 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1909 modifiers = 1 << AARCH64_MOD_LSL;
1910 sve_rr_operand:
1911 assert (opnd->addr.offset.is_reg);
1912 assert (opnd->addr.preind);
1913 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1914 && opnd->addr.offset.regno == 31)
1915 {
1916 set_other_error (mismatch_detail, idx,
1917 _("index register xzr is not allowed"));
1918 return 0;
1919 }
1920 if (((1 << opnd->shifter.kind) & modifiers) == 0
1921 || (opnd->shifter.amount
1922 != get_operand_specific_data (&aarch64_operands[type])))
1923 {
1924 set_other_error (mismatch_detail, idx,
1925 _("invalid addressing mode"));
1926 return 0;
1927 }
1928 break;
1929
1930 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1931 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1932 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1933 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1934 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1935 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1936 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1937 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1938 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1939 goto sve_rr_operand;
1940
1941 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1942 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1943 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1944 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1945 min_value = 0;
1946 max_value = 31;
1947 goto sve_imm_offset;
1948
1949 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1950 modifiers = 1 << AARCH64_MOD_LSL;
1951 sve_zz_operand:
1952 assert (opnd->addr.offset.is_reg);
1953 assert (opnd->addr.preind);
1954 if (((1 << opnd->shifter.kind) & modifiers) == 0
1955 || opnd->shifter.amount < 0
1956 || opnd->shifter.amount > 3)
1957 {
1958 set_other_error (mismatch_detail, idx,
1959 _("invalid addressing mode"));
1960 return 0;
1961 }
1962 break;
1963
1964 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1965 modifiers = (1 << AARCH64_MOD_SXTW);
1966 goto sve_zz_operand;
1967
1968 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1969 modifiers = 1 << AARCH64_MOD_UXTW;
1970 goto sve_zz_operand;
1971
a06ea964
NC		 1972 default:
1973 break;
1974 }
1975 break;
1976
1977 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 1978 if (type == AARCH64_OPND_LEt)
1979 {
1980 /* Get the upper bound for the element index. */
1981 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1982 if (!value_in_range_p (opnd->reglist.index, 0, num))
1983 {
1984 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1985 return 0;
1986 }
1987 }
a06ea964
NC		 1988 /* The opcode dependent area stores the number of elements in
1989 each structure to be loaded/stored. */
1990 num = get_opcode_dependent_value (opcode);
1991 switch (type)
1992 {
1993 case AARCH64_OPND_LVt:
1994 assert (num >= 1 && num <= 4);
1995 /* Unless LD1/ST1, the number of registers should be equal to that
1996 of the structure elements. */
1997 if (num != 1 && opnd->reglist.num_regs != num)
1998 {
1999 set_reg_list_error (mismatch_detail, idx, num);
2000 return 0;
2001 }
2002 break;
2003 case AARCH64_OPND_LVt_AL:
2004 case AARCH64_OPND_LEt:
2005 assert (num >= 1 && num <= 4);
2006 /* The number of registers should be equal to that of the structure
2007 elements. */
2008 if (opnd->reglist.num_regs != num)
2009 {
2010 set_reg_list_error (mismatch_detail, idx, num);
2011 return 0;
2012 }
2013 break;
2014 default:
2015 break;
2016 }
2017 break;
2018
2019 case AARCH64_OPND_CLASS_IMMEDIATE:
2020 /* Constraint check on immediate operand. */
2021 imm = opnd->imm.value;
2022 /* E.g. imm_0_31 constrains value to be 0..31. */
2023 if (qualifier_value_in_range_constraint_p (qualifier)
2024 && !value_in_range_p (imm, get_lower_bound (qualifier),
2025 get_upper_bound (qualifier)))
2026 {
2027 set_imm_out_of_range_error (mismatch_detail, idx,
2028 get_lower_bound (qualifier),
2029 get_upper_bound (qualifier));
2030 return 0;
2031 }
2032
2033 switch (type)
2034 {
2035 case AARCH64_OPND_AIMM:
2036 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2037 {
2038 set_other_error (mismatch_detail, idx,
2039 _("invalid shift operator"));
2040 return 0;
2041 }
2042 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2043 {
2044 set_other_error (mismatch_detail, idx,
ab3b8fcf 2045 _("shift amount must be 0 or 12"));
a06ea964
NC		 2046 return 0;
2047 }
2048 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2049 {
2050 set_other_error (mismatch_detail, idx,
2051 _("immediate out of range"));
2052 return 0;
2053 }
2054 break;
2055
2056 case AARCH64_OPND_HALF:
2057 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2058 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2059 {
2060 set_other_error (mismatch_detail, idx,
2061 _("invalid shift operator"));
2062 return 0;
2063 }
2064 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2065 if (!value_aligned_p (opnd->shifter.amount, 16))
2066 {
2067 set_other_error (mismatch_detail, idx,
ab3b8fcf 2068 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2069 return 0;
2070 }
2071 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2072 {
2073 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2074 0, size * 8 - 16);
2075 return 0;
2076 }
2077 if (opnd->imm.value < 0)
2078 {
2079 set_other_error (mismatch_detail, idx,
2080 _("negative immediate value not allowed"));
2081 return 0;
2082 }
2083 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2084 {
2085 set_other_error (mismatch_detail, idx,
2086 _("immediate out of range"));
2087 return 0;
2088 }
2089 break;
2090
2091 case AARCH64_OPND_IMM_MOV:
2092 {
42408347 2093 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2094 imm = opnd->imm.value;
2095 assert (idx == 1);
2096 switch (opcode->op)
2097 {
2098 case OP_MOV_IMM_WIDEN:
2099 imm = ~imm;
1a0670f3 2100 /* Fall through. */
a06ea964 2101 case OP_MOV_IMM_WIDE:
42408347 2102 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2103 {
2104 set_other_error (mismatch_detail, idx,
2105 _("immediate out of range"));
2106 return 0;
2107 }
2108 break;
2109 case OP_MOV_IMM_LOG:
42408347 2110 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2111 {
2112 set_other_error (mismatch_detail, idx,
2113 _("immediate out of range"));
2114 return 0;
2115 }
2116 break;
2117 default:
2118 assert (0);
2119 return 0;
2120 }
2121 }
2122 break;
2123
2124 case AARCH64_OPND_NZCV:
2125 case AARCH64_OPND_CCMP_IMM:
2126 case AARCH64_OPND_EXCEPTION:
2127 case AARCH64_OPND_UIMM4:
193614f2 2128 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2129 case AARCH64_OPND_UIMM7:
2130 case AARCH64_OPND_UIMM3_OP1:
2131 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2132 case AARCH64_OPND_SVE_UIMM3:
2133 case AARCH64_OPND_SVE_UIMM7:
2134 case AARCH64_OPND_SVE_UIMM8:
2135 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2136 size = get_operand_fields_width (get_operand_from_code (type));
2137 assert (size < 32);
2138 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2139 {
2140 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2141 (1 << size) - 1);
2142 return 0;
2143 }
2144 break;
2145
193614f2
SD		 2146 case AARCH64_OPND_UIMM10:
2147 /* Scaled unsigned 10 bits immediate offset. */
2148 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2149 {
2150 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2151 return 0;
2152 }
2153
2154 if (!value_aligned_p (opnd->imm.value, 16))
2155 {
2156 set_unaligned_error (mismatch_detail, idx, 16);
2157 return 0;
2158 }
2159 break;
2160
e950b345
RS		 2161 case AARCH64_OPND_SIMM5:
2162 case AARCH64_OPND_SVE_SIMM5:
2163 case AARCH64_OPND_SVE_SIMM5B:
2164 case AARCH64_OPND_SVE_SIMM6:
2165 case AARCH64_OPND_SVE_SIMM8:
2166 size = get_operand_fields_width (get_operand_from_code (type));
2167 assert (size < 32);
2168 if (!value_fit_signed_field_p (opnd->imm.value, size))
2169 {
2170 set_imm_out_of_range_error (mismatch_detail, idx,
2171 -(1 << (size - 1)),
2172 (1 << (size - 1)) - 1);
2173 return 0;
2174 }
2175 break;
2176
a06ea964 2177 case AARCH64_OPND_WIDTH:
d685192a 2178 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2179 && opnds[0].type == AARCH64_OPND_Rd);
2180 size = get_upper_bound (qualifier);
2181 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2182 /* lsb+width <= reg.size */
2183 {
2184 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2185 size - opnds[idx-1].imm.value);
2186 return 0;
2187 }
2188 break;
2189
2190 case AARCH64_OPND_LIMM:
e950b345 2191 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2192 {
2193 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2194 uint64_t uimm = opnd->imm.value;
2195 if (opcode->op == OP_BIC)
2196 uimm = ~uimm;
535b785f 2197 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2198 {
2199 set_other_error (mismatch_detail, idx,
2200 _("immediate out of range"));
2201 return 0;
2202 }
2203 }
a06ea964
NC		 2204 break;
2205
2206 case AARCH64_OPND_IMM0:
2207 case AARCH64_OPND_FPIMM0:
2208 if (opnd->imm.value != 0)
2209 {
2210 set_other_error (mismatch_detail, idx,
2211 _("immediate zero expected"));
2212 return 0;
2213 }
2214 break;
2215
c2c4ff8d
SN		 2216 case AARCH64_OPND_IMM_ROT1:
2217 case AARCH64_OPND_IMM_ROT2:
582e12bf 2218 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2219 if (opnd->imm.value != 0
2220 && opnd->imm.value != 90
2221 && opnd->imm.value != 180
2222 && opnd->imm.value != 270)
2223 {
2224 set_other_error (mismatch_detail, idx,
2225 _("rotate expected to be 0, 90, 180 or 270"));
2226 return 0;
2227 }
2228 break;
2229
2230 case AARCH64_OPND_IMM_ROT3:
582e12bf 2231 case AARCH64_OPND_SVE_IMM_ROT1:
c2c4ff8d
SN		 2232 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2233 {
2234 set_other_error (mismatch_detail, idx,
2235 _("rotate expected to be 90 or 270"));
2236 return 0;
2237 }
2238 break;
2239
a06ea964
NC		 2240 case AARCH64_OPND_SHLL_IMM:
2241 assert (idx == 2);
2242 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2243 if (opnd->imm.value != size)
2244 {
2245 set_other_error (mismatch_detail, idx,
2246 _("invalid shift amount"));
2247 return 0;
2248 }
2249 break;
2250
2251 case AARCH64_OPND_IMM_VLSL:
2252 size = aarch64_get_qualifier_esize (qualifier);
2253 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2254 {
2255 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2256 size * 8 - 1);
2257 return 0;
2258 }
2259 break;
2260
2261 case AARCH64_OPND_IMM_VLSR:
2262 size = aarch64_get_qualifier_esize (qualifier);
2263 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2264 {
2265 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2266 return 0;
2267 }
2268 break;
2269
2270 case AARCH64_OPND_SIMD_IMM:
2271 case AARCH64_OPND_SIMD_IMM_SFT:
2272 /* Qualifier check. */
2273 switch (qualifier)
2274 {
2275 case AARCH64_OPND_QLF_LSL:
2276 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2277 {
2278 set_other_error (mismatch_detail, idx,
2279 _("invalid shift operator"));
2280 return 0;
2281 }
2282 break;
2283 case AARCH64_OPND_QLF_MSL:
2284 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2285 {
2286 set_other_error (mismatch_detail, idx,
2287 _("invalid shift operator"));
2288 return 0;
2289 }
2290 break;
2291 case AARCH64_OPND_QLF_NIL:
2292 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2293 {
2294 set_other_error (mismatch_detail, idx,
2295 _("shift is not permitted"));
2296 return 0;
2297 }
2298 break;
2299 default:
2300 assert (0);
2301 return 0;
2302 }
2303 /* Is the immediate valid? */
2304 assert (idx == 1);
2305 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2306 {
d2865ed3
YZ		 2307 /* uimm8 or simm8 */
2308 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2309 {
d2865ed3 2310 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2311 return 0;
2312 }
2313 }
2314 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2315 {
2316 /* uimm64 is not
2317 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2318 ffffffffgggggggghhhhhhhh'. */
2319 set_other_error (mismatch_detail, idx,
2320 _("invalid value for immediate"));
2321 return 0;
2322 }
2323 /* Is the shift amount valid? */
2324 switch (opnd->shifter.kind)
2325 {
2326 case AARCH64_MOD_LSL:
2327 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2328 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2329 {
f5555712
YZ		 2330 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2331 (size - 1) * 8);
a06ea964
NC		 2332 return 0;
2333 }
f5555712 2334 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2335 {
f5555712 2336 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2337 return 0;
2338 }
2339 break;
2340 case AARCH64_MOD_MSL:
2341 /* Only 8 and 16 are valid shift amount. */
2342 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2343 {
2344 set_other_error (mismatch_detail, idx,
ab3b8fcf 2345 _("shift amount must be 0 or 16"));
a06ea964
NC		 2346 return 0;
2347 }
2348 break;
2349 default:
2350 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2351 {
2352 set_other_error (mismatch_detail, idx,
2353 _("invalid shift operator"));
2354 return 0;
2355 }
2356 break;
2357 }
2358 break;
2359
2360 case AARCH64_OPND_FPIMM:
2361 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2362 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2363 if (opnd->imm.is_fp == 0)
2364 {
2365 set_other_error (mismatch_detail, idx,
2366 _("floating-point immediate expected"));
2367 return 0;
2368 }
2369 /* The value is expected to be an 8-bit floating-point constant with
2370 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2371 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2372 instruction). */
2373 if (!value_in_range_p (opnd->imm.value, 0, 255))
2374 {
2375 set_other_error (mismatch_detail, idx,
2376 _("immediate out of range"));
2377 return 0;
2378 }
2379 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2380 {
2381 set_other_error (mismatch_detail, idx,
2382 _("invalid shift operator"));
2383 return 0;
2384 }
2385 break;
2386
e950b345
RS		 2387 case AARCH64_OPND_SVE_AIMM:
2388 min_value = 0;
2389 sve_aimm:
2390 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2391 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2392 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2393 uvalue = opnd->imm.value;
2394 shift = opnd->shifter.amount;
2395 if (size == 1)
2396 {
2397 if (shift != 0)
2398 {
2399 set_other_error (mismatch_detail, idx,
2400 _("no shift amount allowed for"
2401 " 8-bit constants"));
2402 return 0;
2403 }
2404 }
2405 else
2406 {
2407 if (shift != 0 && shift != 8)
2408 {
2409 set_other_error (mismatch_detail, idx,
2410 _("shift amount must be 0 or 8"));
2411 return 0;
2412 }
2413 if (shift == 0 && (uvalue & 0xff) == 0)
2414 {
2415 shift = 8;
2416 uvalue = (int64_t) uvalue / 256;
2417 }
2418 }
2419 mask >>= shift;
2420 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2421 {
2422 set_other_error (mismatch_detail, idx,
2423 _("immediate too big for element size"));
2424 return 0;
2425 }
2426 uvalue = (uvalue - min_value) & mask;
2427 if (uvalue > 0xff)
2428 {
2429 set_other_error (mismatch_detail, idx,
2430 _("invalid arithmetic immediate"));
2431 return 0;
2432 }
2433 break;
2434
2435 case AARCH64_OPND_SVE_ASIMM:
2436 min_value = -128;
2437 goto sve_aimm;
2438
165d4950
RS		 2439 case AARCH64_OPND_SVE_I1_HALF_ONE:
2440 assert (opnd->imm.is_fp);
2441 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2442 {
2443 set_other_error (mismatch_detail, idx,
2444 _("floating-point value must be 0.5 or 1.0"));
2445 return 0;
2446 }
2447 break;
2448
2449 case AARCH64_OPND_SVE_I1_HALF_TWO:
2450 assert (opnd->imm.is_fp);
2451 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2452 {
2453 set_other_error (mismatch_detail, idx,
2454 _("floating-point value must be 0.5 or 2.0"));
2455 return 0;
2456 }
2457 break;
2458
2459 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2460 assert (opnd->imm.is_fp);
2461 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2462 {
2463 set_other_error (mismatch_detail, idx,
2464 _("floating-point value must be 0.0 or 1.0"));
2465 return 0;
2466 }
2467 break;
2468
e950b345
RS		 2469 case AARCH64_OPND_SVE_INV_LIMM:
2470 {
2471 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2472 uint64_t uimm = ~opnd->imm.value;
2473 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2474 {
2475 set_other_error (mismatch_detail, idx,
2476 _("immediate out of range"));
2477 return 0;
2478 }
2479 }
2480 break;
2481
2482 case AARCH64_OPND_SVE_LIMM_MOV:
2483 {
2484 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2485 uint64_t uimm = opnd->imm.value;
2486 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2487 {
2488 set_other_error (mismatch_detail, idx,
2489 _("immediate out of range"));
2490 return 0;
2491 }
2492 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2493 {
2494 set_other_error (mismatch_detail, idx,
2495 _("invalid replicated MOV immediate"));
2496 return 0;
2497 }
2498 }
2499 break;
2500
2442d846
RS		 2501 case AARCH64_OPND_SVE_PATTERN_SCALED:
2502 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2503 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2504 {
2505 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2506 return 0;
2507 }
2508 break;
2509
e950b345
RS		 2510 case AARCH64_OPND_SVE_SHLIMM_PRED:
2511 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2512 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2513 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2514 {
2515 set_imm_out_of_range_error (mismatch_detail, idx,
2516 0, 8 * size - 1);
2517 return 0;
2518 }
2519 break;
2520
2521 case AARCH64_OPND_SVE_SHRIMM_PRED:
2522 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2523 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2524 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2525 {
2526 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2527 return 0;
2528 }
2529 break;
2530
a06ea964
NC		 2531 default:
2532 break;
2533 }
2534 break;
2535
a06ea964
NC		 2536 case AARCH64_OPND_CLASS_SYSTEM:
2537 switch (type)
2538 {
2539 case AARCH64_OPND_PSTATEFIELD:
2540 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2541 /* MSR UAO, #uimm4
2542 MSR PAN, #uimm4
104fefee 2543 MSR SSBS,#uimm4
c2825638 2544 The immediate must be #0 or #1. */
0bff6e2d 2545 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2546 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2547 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2548 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2549 && opnds[1].imm.value > 1)
2550 {
2551 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2552 return 0;
2553 }
a06ea964
NC		 2554 /* MSR SPSel, #uimm4
2555 Uses uimm4 as a control value to select the stack pointer: if
2556 bit 0 is set it selects the current exception level's stack
2557 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2558 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2559 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2560 {
2561 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2562 return 0;
2563 }
2564 break;
2565 default:
2566 break;
2567 }
2568 break;
2569
2570 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2571 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2572 if (opcode->op == OP_FCMLA_ELEM)
2573 /* FCMLA index range depends on the vector size of other operands
2574 and is halfed because complex numbers take two elements. */
2575 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2576 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2577 else
2578 num = 16;
2579 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2580 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2581
a06ea964
NC		 2582 /* Index out-of-range. */
2583 if (!value_in_range_p (opnd->reglane.index, 0, num))
2584 {
2585 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2586 return 0;
2587 }
2588 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2589 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2590 number is encoded in "size:M:Rm":
2591 size <Vm>
2592 00 RESERVED
2593 01 0:Rm
2594 10 M:Rm
2595 11 RESERVED */
369c9167 2596 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2597 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2598 {
2599 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2600 return 0;
2601 }
2602 break;
2603
2604 case AARCH64_OPND_CLASS_MODIFIED_REG:
2605 assert (idx == 1 || idx == 2);
2606 switch (type)
2607 {
2608 case AARCH64_OPND_Rm_EXT:
535b785f 2609 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2610 && opnd->shifter.kind != AARCH64_MOD_LSL)
2611 {
2612 set_other_error (mismatch_detail, idx,
2613 _("extend operator expected"));
2614 return 0;
2615 }
2616 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2617 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2618 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2619 case. */
2620 if (!aarch64_stack_pointer_p (opnds + 0)
2621 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2622 {
2623 if (!opnd->shifter.operator_present)
2624 {
2625 set_other_error (mismatch_detail, idx,
2626 _("missing extend operator"));
2627 return 0;
2628 }
2629 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2630 {
2631 set_other_error (mismatch_detail, idx,
2632 _("'LSL' operator not allowed"));
2633 return 0;
2634 }
2635 }
2636 assert (opnd->shifter.operator_present /* Default to LSL. */
2637 || opnd->shifter.kind == AARCH64_MOD_LSL);
2638 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2639 {
2640 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2641 return 0;
2642 }
2643 /* In the 64-bit form, the final register operand is written as Wm
2644 for all but the (possibly omitted) UXTX/LSL and SXTX
2645 operators.
2646 N.B. GAS allows X register to be used with any operator as a
2647 programming convenience. */
2648 if (qualifier == AARCH64_OPND_QLF_X
2649 && opnd->shifter.kind != AARCH64_MOD_LSL
2650 && opnd->shifter.kind != AARCH64_MOD_UXTX
2651 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2652 {
2653 set_other_error (mismatch_detail, idx, _("W register expected"));
2654 return 0;
2655 }
2656 break;
2657
2658 case AARCH64_OPND_Rm_SFT:
2659 /* ROR is not available to the shifted register operand in
2660 arithmetic instructions. */
535b785f 2661 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2662 {
2663 set_other_error (mismatch_detail, idx,
2664 _("shift operator expected"));
2665 return 0;
2666 }
2667 if (opnd->shifter.kind == AARCH64_MOD_ROR
2668 && opcode->iclass != log_shift)
2669 {
2670 set_other_error (mismatch_detail, idx,
2671 _("'ROR' operator not allowed"));
2672 return 0;
2673 }
2674 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2675 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2676 {
2677 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2678 return 0;
2679 }
2680 break;
2681
2682 default:
2683 break;
2684 }
2685 break;
2686
2687 default:
2688 break;
2689 }
2690
2691 return 1;
2692}
2693
2694/* Main entrypoint for the operand constraint checking.
2695
2696 Return 1 if operands of *INST meet the constraint applied by the operand
2697 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2698 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2699 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2700 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2701 error kind when it is notified that an instruction does not pass the check).
2702
2703 Un-determined operand qualifiers may get established during the process. */
2704
2705int
2706aarch64_match_operands_constraint (aarch64_inst *inst,
2707 aarch64_operand_error *mismatch_detail)
2708{
2709 int i;
2710
2711 DEBUG_TRACE ("enter");
2712
0c608d6b
RS		 2713 /* Check for cases where a source register needs to be the same as the
2714 destination register. Do this before matching qualifiers since if
2715 an instruction has both invalid tying and invalid qualifiers,
2716 the error about qualifiers would suggest several alternative
2717 instructions that also have invalid tying. */
2718 i = inst->opcode->tied_operand;
2719 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2720 {
2721 if (mismatch_detail)
2722 {
2723 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2724 mismatch_detail->index = i;
2725 mismatch_detail->error = NULL;
2726 }
2727 return 0;
2728 }
2729
a06ea964
NC		 2730 /* Match operands' qualifier.
2731 *INST has already had qualifier establish for some, if not all, of
2732 its operands; we need to find out whether these established
2733 qualifiers match one of the qualifier sequence in
2734 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2735 with the corresponding qualifier in such a sequence.
2736 Only basic operand constraint checking is done here; the more thorough
2737 constraint checking will carried out by operand_general_constraint_met_p,
2738 which has be to called after this in order to get all of the operands'
2739 qualifiers established. */
2740 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2741 {
2742 DEBUG_TRACE ("FAIL on operand qualifier matching");
2743 if (mismatch_detail)
2744 {
2745 /* Return an error type to indicate that it is the qualifier
2746 matching failure; we don't care about which operand as there
2747 are enough information in the opcode table to reproduce it. */
2748 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2749 mismatch_detail->index = -1;
2750 mismatch_detail->error = NULL;
2751 }
2752 return 0;
2753 }
2754
2755 /* Match operands' constraint. */
2756 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2757 {
2758 enum aarch64_opnd type = inst->opcode->operands[i];
2759 if (type == AARCH64_OPND_NIL)
2760 break;
2761 if (inst->operands[i].skip)
2762 {
2763 DEBUG_TRACE ("skip the incomplete operand %d", i);
2764 continue;
2765 }
2766 if (operand_general_constraint_met_p (inst->operands, i, type,
2767 inst->opcode, mismatch_detail) == 0)
2768 {
2769 DEBUG_TRACE ("FAIL on operand %d", i);
2770 return 0;
2771 }
2772 }
2773
2774 DEBUG_TRACE ("PASS");
2775
2776 return 1;
2777}
2778
2779/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2780 Also updates the TYPE of each INST->OPERANDS with the corresponding
2781 value of OPCODE->OPERANDS.
2782
2783 Note that some operand qualifiers may need to be manually cleared by
2784 the caller before it further calls the aarch64_opcode_encode; by
2785 doing this, it helps the qualifier matching facilities work
2786 properly. */
2787
2788const aarch64_opcode*
2789aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2790{
2791 int i;
2792 const aarch64_opcode *old = inst->opcode;
2793
2794 inst->opcode = opcode;
2795
2796 /* Update the operand types. */
2797 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2798 {
2799 inst->operands[i].type = opcode->operands[i];
2800 if (opcode->operands[i] == AARCH64_OPND_NIL)
2801 break;
2802 }
2803
2804 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2805
2806 return old;
2807}
2808
2809int
2810aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2811{
2812 int i;
2813 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2814 if (operands[i] == operand)
2815 return i;
2816 else if (operands[i] == AARCH64_OPND_NIL)
2817 break;
2818 return -1;
2819}
2820\f
72e9f319
RS		 2821/* R0...R30, followed by FOR31. */
2822#define BANK(R, FOR31) \
2823 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2824 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2825 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2826 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2827/* [0][0] 32-bit integer regs with sp Wn
2828 [0][1] 64-bit integer regs with sp Xn sf=1
2829 [1][0] 32-bit integer regs with #0 Wn
2830 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2831static const char *int_reg[2][2][32] = {
72e9f319
RS		 2832#define R32(X) "w" #X
2833#define R64(X) "x" #X
2834 { BANK (R32, "wsp"), BANK (R64, "sp") },
2835 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2836#undef R64
2837#undef R32
2838};
4df068de
RS		 2839
2840/* Names of the SVE vector registers, first with .S suffixes,
2841 then with .D suffixes. */
2842
2843static const char *sve_reg[2][32] = {
2844#define ZS(X) "z" #X ".s"
2845#define ZD(X) "z" #X ".d"
2846 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2847#undef ZD
2848#undef ZS
2849};
72e9f319 2850#undef BANK
a06ea964
NC		 2851
2852/* Return the integer register name.
2853 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2854
2855static inline const char *
2856get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2857{
2858 const int has_zr = sp_reg_p ? 0 : 1;
2859 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2860 return int_reg[has_zr][is_64][regno];
2861}
2862
2863/* Like get_int_reg_name, but IS_64 is always 1. */
2864
2865static inline const char *
2866get_64bit_int_reg_name (int regno, int sp_reg_p)
2867{
2868 const int has_zr = sp_reg_p ? 0 : 1;
2869 return int_reg[has_zr][1][regno];
2870}
2871
01dbfe4c
RS		 2872/* Get the name of the integer offset register in OPND, using the shift type
2873 to decide whether it's a word or doubleword. */
2874
2875static inline const char *
2876get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2877{
2878 switch (opnd->shifter.kind)
2879 {
2880 case AARCH64_MOD_UXTW:
2881 case AARCH64_MOD_SXTW:
2882 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2883
2884 case AARCH64_MOD_LSL:
2885 case AARCH64_MOD_SXTX:
2886 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2887
2888 default:
2889 abort ();
2890 }
2891}
2892
4df068de
RS		 2893/* Get the name of the SVE vector offset register in OPND, using the operand
2894 qualifier to decide whether the suffix should be .S or .D. */
2895
2896static inline const char *
2897get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2898{
2899 assert (qualifier == AARCH64_OPND_QLF_S_S
2900 || qualifier == AARCH64_OPND_QLF_S_D);
2901 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2902}
2903
a06ea964
NC		 2904/* Types for expanding an encoded 8-bit value to a floating-point value. */
2905
2906typedef union
2907{
2908 uint64_t i;
2909 double d;
2910} double_conv_t;
2911
2912typedef union
2913{
2914 uint32_t i;
2915 float f;
2916} single_conv_t;
2917
cf86120b
MW		 2918typedef union
2919{
2920 uint32_t i;
2921 float f;
2922} half_conv_t;
2923
a06ea964
NC		 2924/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2925 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2926 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2927 single-precision floating-point value (SIZE == 4) or a double-precision
2928 floating-point value (SIZE == 8). A half-precision floating-point value
2929 (SIZE == 2) is expanded to a single-precision floating-point value. The
2930 expanded value is returned. */
a06ea964
NC		 2931
2932static uint64_t
cf86120b 2933expand_fp_imm (int size, uint32_t imm8)
a06ea964 2934{
57a024f4 2935 uint64_t imm = 0;
a06ea964
NC		 2936 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2937
2938 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2939 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2940 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2941 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2942 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2943 if (size == 8)
a06ea964
NC		 2944 {
2945 imm = (imm8_7 << (63-32)) /* imm8<7> */
2946 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2947 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2948 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2949 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2950 imm <<= 32;
2951 }
cf86120b 2952 else if (size == 4 || size == 2)
a06ea964
NC		 2953 {
2954 imm = (imm8_7 << 31) /* imm8<7> */
2955 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2956 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2957 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2958 }
cf86120b
MW		 2959 else
2960 {
2961 /* An unsupported size. */
2962 assert (0);
2963 }
a06ea964
NC		 2964
2965 return imm;
2966}
2967
2968/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2969 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2970 the register name that comes before the register number, such as "v". */
a06ea964 2971static void
8a7f0c1b
RS		 2972print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2973 const char *prefix)
a06ea964
NC		 2974{
2975 const int num_regs = opnd->reglist.num_regs;
2976 const int first_reg = opnd->reglist.first_regno;
2977 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2978 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2979 char tb[8]; /* Temporary buffer. */
2980
2981 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2982 assert (num_regs >= 1 && num_regs <= 4);
2983
2984 /* Prepare the index if any. */
2985 if (opnd->reglist.has_index)
1b7e3d2f
NC		 2986 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2987 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 2988 else
2989 tb[0] = '\0';
2990
2991 /* The hyphenated form is preferred for disassembly if there are
2992 more than two registers in the list, and the register numbers
2993 are monotonically increasing in increments of one. */
2994 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 2995 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2996 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 2997 else
2998 {
2999 const int reg0 = first_reg;
3000 const int reg1 = (first_reg + 1) & 0x1f;
3001 const int reg2 = (first_reg + 2) & 0x1f;
3002 const int reg3 = (first_reg + 3) & 0x1f;
3003
3004 switch (num_regs)
3005 {
3006 case 1:
8a7f0c1b 3007 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3008 break;
3009 case 2:
8a7f0c1b
RS		 3010 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3011 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3012 break;
3013 case 3:
8a7f0c1b
RS		 3014 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3015 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3016 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3017 break;
3018 case 4:
8a7f0c1b
RS		 3019 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3020 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3021 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3022 break;
3023 }
3024 }
3025}
3026
01dbfe4c
RS		 3027/* Print the register+immediate address in OPND to BUF, which has SIZE
3028 characters. BASE is the name of the base register. */
3029
3030static void
3031print_immediate_offset_address (char *buf, size_t size,
3032 const aarch64_opnd_info *opnd,
3033 const char *base)
3034{
3035 if (opnd->addr.writeback)
3036 {
3037 if (opnd->addr.preind)
ad43e107 3038 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
01dbfe4c 3039 else
ad43e107 3040 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3041 }
3042 else
3043 {
98907a70
RS		 3044 if (opnd->shifter.operator_present)
3045 {
3046 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3047 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3048 base, opnd->addr.offset.imm);
3049 }
3050 else if (opnd->addr.offset.imm)
ad43e107 3051 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3052 else
3053 snprintf (buf, size, "[%s]", base);
3054 }
3055}
3056
a06ea964 3057/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3058 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3059 the names of the base and offset registers. */
a06ea964
NC		 3060static void
3061print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3062 const aarch64_opnd_info *opnd,
3063 const char *base, const char *offset)
a06ea964 3064{
0d2f91fe 3065 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3066 bfd_boolean print_extend_p = TRUE;
3067 bfd_boolean print_amount_p = TRUE;
3068 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3069
a06ea964
NC		 3070 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3071 || !opnd->shifter.amount_present))
3072 {
3073 /* Not print the shift/extend amount when the amount is zero and
3074 when it is not the special case of 8-bit load/store instruction. */
3075 print_amount_p = FALSE;
3076 /* Likewise, no need to print the shift operator LSL in such a
3077 situation. */
01dbfe4c 3078 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3079 print_extend_p = FALSE;
3080 }
3081
3082 /* Prepare for the extend/shift. */
3083 if (print_extend_p)
3084 {
3085 if (print_amount_p)
ad43e107 3086 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3087 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3088 (opnd->shifter.amount % 100));
a06ea964 3089 else
ad43e107 3090 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3091 }
3092 else
3093 tb[0] = '\0';
3094
ad43e107 3095 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3096}
3097
3098/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3099 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3100 PC, PCREL_P and ADDRESS are used to pass in and return information about
3101 the PC-relative address calculation, where the PC value is passed in
3102 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3103 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3104 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3105
3106 The function serves both the disassembler and the assembler diagnostics
3107 issuer, which is the reason why it lives in this file. */
3108
3109void
3110aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3111 const aarch64_opcode *opcode,
3112 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3113 bfd_vma *address, char** notes)
a06ea964 3114{
bb7eff52 3115 unsigned int i, num_conds;
a06ea964
NC		 3116 const char *name = NULL;
3117 const aarch64_opnd_info *opnd = opnds + idx;
3118 enum aarch64_modifier_kind kind;
245d2e3f 3119 uint64_t addr, enum_value;
a06ea964
NC		 3120
3121 buf[0] = '\0';
3122 if (pcrel_p)
3123 *pcrel_p = 0;
3124
3125 switch (opnd->type)
3126 {
3127 case AARCH64_OPND_Rd:
3128 case AARCH64_OPND_Rn:
3129 case AARCH64_OPND_Rm:
3130 case AARCH64_OPND_Rt:
3131 case AARCH64_OPND_Rt2:
3132 case AARCH64_OPND_Rs:
3133 case AARCH64_OPND_Ra:
3134 case AARCH64_OPND_Rt_SYS:
ee804238 3135 case AARCH64_OPND_PAIRREG:
047cd301 3136 case AARCH64_OPND_SVE_Rm:
a06ea964 3137 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3138 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3139 generic optional-ness information. */
362c0c4d
JW		 3140 if (opnd->type == AARCH64_OPND_Rt_SYS)
3141 {
3142 if (!opnd->present)
3143 break;
3144 }
a06ea964 3145 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3146 else if (optional_operand_p (opcode, idx)
3147 && (opnd->reg.regno
3148 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3149 break;
3150 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3151 || opnd->qualifier == AARCH64_OPND_QLF_X);
3152 snprintf (buf, size, "%s",
3153 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3154 break;
3155
3156 case AARCH64_OPND_Rd_SP:
3157 case AARCH64_OPND_Rn_SP:
047cd301 3158 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3159 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3160 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3161 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3162 || opnd->qualifier == AARCH64_OPND_QLF_X
3163 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3164 snprintf (buf, size, "%s",
3165 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3166 break;
3167
3168 case AARCH64_OPND_Rm_EXT:
3169 kind = opnd->shifter.kind;
3170 assert (idx == 1 || idx == 2);
3171 if ((aarch64_stack_pointer_p (opnds)
3172 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3173 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3174 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3175 && kind == AARCH64_MOD_UXTW)
3176 || (opnd->qualifier == AARCH64_OPND_QLF_X
3177 && kind == AARCH64_MOD_UXTX)))
3178 {
3179 /* 'LSL' is the preferred form in this case. */
3180 kind = AARCH64_MOD_LSL;
3181 if (opnd->shifter.amount == 0)
3182 {
3183 /* Shifter omitted. */
3184 snprintf (buf, size, "%s",
3185 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3186 break;
3187 }
3188 }
3189 if (opnd->shifter.amount)
2442d846 3190 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3191 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3192 aarch64_operand_modifiers[kind].name,
3193 opnd->shifter.amount);
3194 else
3195 snprintf (buf, size, "%s, %s",
3196 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3197 aarch64_operand_modifiers[kind].name);
3198 break;
3199
3200 case AARCH64_OPND_Rm_SFT:
3201 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3202 || opnd->qualifier == AARCH64_OPND_QLF_X);
3203 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3204 snprintf (buf, size, "%s",
3205 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3206 else
2442d846 3207 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3208 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3209 aarch64_operand_modifiers[opnd->shifter.kind].name,
3210 opnd->shifter.amount);
3211 break;
3212
3213 case AARCH64_OPND_Fd:
3214 case AARCH64_OPND_Fn:
3215 case AARCH64_OPND_Fm:
3216 case AARCH64_OPND_Fa:
3217 case AARCH64_OPND_Ft:
3218 case AARCH64_OPND_Ft2:
3219 case AARCH64_OPND_Sd:
3220 case AARCH64_OPND_Sn:
3221 case AARCH64_OPND_Sm:
047cd301
RS		 3222 case AARCH64_OPND_SVE_VZn:
3223 case AARCH64_OPND_SVE_Vd:
3224 case AARCH64_OPND_SVE_Vm:
3225 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3226 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3227 opnd->reg.regno);
3228 break;
3229
f42f1a1d 3230 case AARCH64_OPND_Va:
a06ea964
NC		 3231 case AARCH64_OPND_Vd:
3232 case AARCH64_OPND_Vn:
3233 case AARCH64_OPND_Vm:
3234 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3235 aarch64_get_qualifier_name (opnd->qualifier));
3236 break;
3237
3238 case AARCH64_OPND_Ed:
3239 case AARCH64_OPND_En:
3240 case AARCH64_OPND_Em:
369c9167 3241 case AARCH64_OPND_Em16:
f42f1a1d 3242 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3243 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3244 aarch64_get_qualifier_name (opnd->qualifier),
3245 opnd->reglane.index);
3246 break;
3247
3248 case AARCH64_OPND_VdD1:
3249 case AARCH64_OPND_VnD1:
3250 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3251 break;
3252
3253 case AARCH64_OPND_LVn:
3254 case AARCH64_OPND_LVt:
3255 case AARCH64_OPND_LVt_AL:
3256 case AARCH64_OPND_LEt:
8a7f0c1b 3257 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3258 break;
3259
f11ad6bc
RS		 3260 case AARCH64_OPND_SVE_Pd:
3261 case AARCH64_OPND_SVE_Pg3:
3262 case AARCH64_OPND_SVE_Pg4_5:
3263 case AARCH64_OPND_SVE_Pg4_10:
3264 case AARCH64_OPND_SVE_Pg4_16:
3265 case AARCH64_OPND_SVE_Pm:
3266 case AARCH64_OPND_SVE_Pn:
3267 case AARCH64_OPND_SVE_Pt:
3268 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3269 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3270 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3271 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3272 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3273 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3274 else
3275 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3276 aarch64_get_qualifier_name (opnd->qualifier));
3277 break;
3278
3279 case AARCH64_OPND_SVE_Za_5:
3280 case AARCH64_OPND_SVE_Za_16:
3281 case AARCH64_OPND_SVE_Zd:
3282 case AARCH64_OPND_SVE_Zm_5:
3283 case AARCH64_OPND_SVE_Zm_16:
3284 case AARCH64_OPND_SVE_Zn:
3285 case AARCH64_OPND_SVE_Zt:
3286 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3287 snprintf (buf, size, "z%d", opnd->reg.regno);
3288 else
3289 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3290 aarch64_get_qualifier_name (opnd->qualifier));
3291 break;
3292
3293 case AARCH64_OPND_SVE_ZnxN:
3294 case AARCH64_OPND_SVE_ZtxN:
3295 print_register_list (buf, size, opnd, "z");
3296 break;
3297
582e12bf
RS		 3298 case AARCH64_OPND_SVE_Zm3_INDEX:
3299 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3300 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3301 case AARCH64_OPND_SVE_Zn_INDEX:
3302 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3303 aarch64_get_qualifier_name (opnd->qualifier),
3304 opnd->reglane.index);
3305 break;
3306
a6a51754
RL		 3307 case AARCH64_OPND_CRn:
3308 case AARCH64_OPND_CRm:
3309 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3310 break;
3311
3312 case AARCH64_OPND_IDX:
f42f1a1d 3313 case AARCH64_OPND_MASK:
a06ea964 3314 case AARCH64_OPND_IMM:
f42f1a1d 3315 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3316 case AARCH64_OPND_WIDTH:
3317 case AARCH64_OPND_UIMM3_OP1:
3318 case AARCH64_OPND_UIMM3_OP2:
3319 case AARCH64_OPND_BIT_NUM:
3320 case AARCH64_OPND_IMM_VLSL:
3321 case AARCH64_OPND_IMM_VLSR:
3322 case AARCH64_OPND_SHLL_IMM:
3323 case AARCH64_OPND_IMM0:
3324 case AARCH64_OPND_IMMR:
3325 case AARCH64_OPND_IMMS:
3326 case AARCH64_OPND_FBITS:
e950b345
RS		 3327 case AARCH64_OPND_SIMM5:
3328 case AARCH64_OPND_SVE_SHLIMM_PRED:
3329 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3330 case AARCH64_OPND_SVE_SHRIMM_PRED:
3331 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3332 case AARCH64_OPND_SVE_SIMM5:
3333 case AARCH64_OPND_SVE_SIMM5B:
3334 case AARCH64_OPND_SVE_SIMM6:
3335 case AARCH64_OPND_SVE_SIMM8:
3336 case AARCH64_OPND_SVE_UIMM3:
3337 case AARCH64_OPND_SVE_UIMM7:
3338 case AARCH64_OPND_SVE_UIMM8:
3339 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3340 case AARCH64_OPND_IMM_ROT1:
3341 case AARCH64_OPND_IMM_ROT2:
3342 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3343 case AARCH64_OPND_SVE_IMM_ROT1:
3344 case AARCH64_OPND_SVE_IMM_ROT2:
a06ea964
NC		 3345 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3346 break;
3347
165d4950
RS		 3348 case AARCH64_OPND_SVE_I1_HALF_ONE:
3349 case AARCH64_OPND_SVE_I1_HALF_TWO:
3350 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3351 {
3352 single_conv_t c;
3353 c.i = opnd->imm.value;
3354 snprintf (buf, size, "#%.1f", c.f);
3355 break;
3356 }
3357
245d2e3f
RS		 3358 case AARCH64_OPND_SVE_PATTERN:
3359 if (optional_operand_p (opcode, idx)
3360 && opnd->imm.value == get_optional_operand_default_value (opcode))
3361 break;
3362 enum_value = opnd->imm.value;
3363 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3364 if (aarch64_sve_pattern_array[enum_value])
3365 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3366 else
3367 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3368 break;
3369
2442d846
RS		 3370 case AARCH64_OPND_SVE_PATTERN_SCALED:
3371 if (optional_operand_p (opcode, idx)
3372 && !opnd->shifter.operator_present
3373 && opnd->imm.value == get_optional_operand_default_value (opcode))
3374 break;
3375 enum_value = opnd->imm.value;
3376 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3377 if (aarch64_sve_pattern_array[opnd->imm.value])
3378 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3379 else
3380 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3381 if (opnd->shifter.operator_present)
3382 {
3383 size_t len = strlen (buf);
3384 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3385 aarch64_operand_modifiers[opnd->shifter.kind].name,
3386 opnd->shifter.amount);
3387 }
3388 break;
3389
245d2e3f
RS		 3390 case AARCH64_OPND_SVE_PRFOP:
3391 enum_value = opnd->imm.value;
3392 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3393 if (aarch64_sve_prfop_array[enum_value])
3394 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3395 else
3396 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3397 break;
3398
fb098a1e
YZ		 3399 case AARCH64_OPND_IMM_MOV:
3400 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3401 {
3402 case 4: /* e.g. MOV Wd, #<imm32>. */
3403 {
3404 int imm32 = opnd->imm.value;
3405 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3406 }
3407 break;
3408 case 8: /* e.g. MOV Xd, #<imm64>. */
3409 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3410 opnd->imm.value, opnd->imm.value);
3411 break;
3412 default: assert (0);
3413 }
3414 break;
3415
a06ea964
NC		 3416 case AARCH64_OPND_FPIMM0:
3417 snprintf (buf, size, "#0.0");
3418 break;
3419
3420 case AARCH64_OPND_LIMM:
3421 case AARCH64_OPND_AIMM:
3422 case AARCH64_OPND_HALF:
e950b345
RS		 3423 case AARCH64_OPND_SVE_INV_LIMM:
3424 case AARCH64_OPND_SVE_LIMM:
3425 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3426 if (opnd->shifter.amount)
2442d846 3427 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3428 opnd->shifter.amount);
3429 else
3430 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3431 break;
3432
3433 case AARCH64_OPND_SIMD_IMM:
3434 case AARCH64_OPND_SIMD_IMM_SFT:
3435 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3436 || opnd->shifter.kind == AARCH64_MOD_NONE)
3437 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3438 else
2442d846 3439 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3440 aarch64_operand_modifiers[opnd->shifter.kind].name,
3441 opnd->shifter.amount);
3442 break;
3443
e950b345
RS		 3444 case AARCH64_OPND_SVE_AIMM:
3445 case AARCH64_OPND_SVE_ASIMM:
3446 if (opnd->shifter.amount)
3447 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3448 opnd->shifter.amount);
3449 else
3450 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3451 break;
3452
a06ea964
NC		 3453 case AARCH64_OPND_FPIMM:
3454 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3455 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3456 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3457 {
cf86120b
MW		 3458 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3459 {
3460 half_conv_t c;
3461 c.i = expand_fp_imm (2, opnd->imm.value);
3462 snprintf (buf, size, "#%.18e", c.f);
3463 }
3464 break;
a06ea964
NC		 3465 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3466 {
3467 single_conv_t c;
cf86120b 3468 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3469 snprintf (buf, size, "#%.18e", c.f);
3470 }
3471 break;
3472 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3473 {
3474 double_conv_t c;
cf86120b 3475 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3476 snprintf (buf, size, "#%.18e", c.d);
3477 }
3478 break;
3479 default: assert (0);
3480 }
3481 break;
3482
3483 case AARCH64_OPND_CCMP_IMM:
3484 case AARCH64_OPND_NZCV:
3485 case AARCH64_OPND_EXCEPTION:
3486 case AARCH64_OPND_UIMM4:
193614f2 3487 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3488 case AARCH64_OPND_UIMM7:
193614f2 3489 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3490 if (optional_operand_p (opcode, idx) == TRUE
3491 && (opnd->imm.value ==
3492 (int64_t) get_optional_operand_default_value (opcode)))
3493 /* Omit the operand, e.g. DCPS1. */
3494 break;
3495 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3496 break;
3497
3498 case AARCH64_OPND_COND:
68a64283 3499 case AARCH64_OPND_COND1:
a06ea964 3500 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3501 num_conds = ARRAY_SIZE (opnd->cond->names);
3502 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3503 {
3504 size_t len = strlen (buf);
3505 if (i == 1)
3506 snprintf (buf + len, size - len, " // %s = %s",
3507 opnd->cond->names[0], opnd->cond->names[i]);
3508 else
3509 snprintf (buf + len, size - len, ", %s",
3510 opnd->cond->names[i]);
3511 }
a06ea964
NC		 3512 break;
3513
3514 case AARCH64_OPND_ADDR_ADRP:
3515 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3516 + opnd->imm.value;
3517 if (pcrel_p)
3518 *pcrel_p = 1;
3519 if (address)
3520 *address = addr;
3521 /* This is not necessary during the disassembling, as print_address_func
3522 in the disassemble_info will take care of the printing. But some
3523 other callers may be still interested in getting the string in *STR,
3524 so here we do snprintf regardless. */
3525 snprintf (buf, size, "#0x%" PRIx64, addr);
3526 break;
3527
3528 case AARCH64_OPND_ADDR_PCREL14:
3529 case AARCH64_OPND_ADDR_PCREL19:
3530 case AARCH64_OPND_ADDR_PCREL21:
3531 case AARCH64_OPND_ADDR_PCREL26:
3532 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3533 if (pcrel_p)
3534 *pcrel_p = 1;
3535 if (address)
3536 *address = addr;
3537 /* This is not necessary during the disassembling, as print_address_func
3538 in the disassemble_info will take care of the printing. But some
3539 other callers may be still interested in getting the string in *STR,
3540 so here we do snprintf regardless. */
3541 snprintf (buf, size, "#0x%" PRIx64, addr);
3542 break;
3543
3544 case AARCH64_OPND_ADDR_SIMPLE:
3545 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3546 case AARCH64_OPND_SIMD_ADDR_POST:
3547 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3548 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3549 {
3550 if (opnd->addr.offset.is_reg)
3551 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3552 else
3553 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3554 }
3555 else
3556 snprintf (buf, size, "[%s]", name);
3557 break;
3558
3559 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3560 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3561 case AARCH64_OPND_SVE_ADDR_RR:
3562 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3563 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3564 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3565 case AARCH64_OPND_SVE_ADDR_RX:
3566 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3567 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3568 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3569 print_register_offset_address
3570 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3571 get_offset_int_reg_name (opnd));
a06ea964
NC		 3572 break;
3573
4df068de
RS		 3574 case AARCH64_OPND_SVE_ADDR_RZ:
3575 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3576 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3577 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3578 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3579 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3580 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3581 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3582 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3583 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3584 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3585 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3586 print_register_offset_address
3587 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3588 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3589 break;
3590
a06ea964
NC		 3591 case AARCH64_OPND_ADDR_SIMM7:
3592 case AARCH64_OPND_ADDR_SIMM9:
3593 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3594 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3595 case AARCH64_OPND_ADDR_SIMM11:
3596 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3597 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3598 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS		 3599 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3600 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3601 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3602 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3603 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3604 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3605 case AARCH64_OPND_SVE_ADDR_RI_U6:
3606 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3607 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3608 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3609 print_immediate_offset_address
3610 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3611 break;
3612
4df068de
RS		 3613 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3614 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3615 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3616 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3617 print_immediate_offset_address
3618 (buf, size, opnd,
3619 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3620 break;
3621
3622 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3623 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3624 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3625 print_register_offset_address
3626 (buf, size, opnd,
3627 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3628 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3629 break;
3630
a06ea964
NC		 3631 case AARCH64_OPND_ADDR_UIMM12:
3632 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3633 if (opnd->addr.offset.imm)
ad43e107 3634 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3635 else
3636 snprintf (buf, size, "[%s]", name);
3637 break;
3638
3639 case AARCH64_OPND_SYSREG:
3640 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3641 {
3642 bfd_boolean exact_match
3643 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3644 == opnd->sysreg.flags;
3645
3646 /* Try and find an exact match, But if that fails, return the first
3647 partial match that was found. */
3648 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3649 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3650 && (name == NULL || exact_match))
3651 {
3652 name = aarch64_sys_regs[i].name;
3653 if (exact_match)
3654 {
3655 if (notes)
3656 *notes = NULL;
3657 break;
3658 }
3659
3660 /* If we didn't match exactly, that means the presense of a flag
3661 indicates what we didn't want for this instruction. e.g. If
3662 F_REG_READ is there, that means we were looking for a write
3663 register. See aarch64_ext_sysreg. */
3664 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3665 *notes = _("reading from a write-only register");
f9830ec1 3666 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3667 *notes = _("writing to a read-only register");
f9830ec1
TC		 3668 }
3669 }
3670
3671 if (name)
3672 snprintf (buf, size, "%s", name);
a06ea964
NC		 3673 else
3674 {
3675 /* Implementation defined system register. */
561a72d4 3676 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3677 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3678 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3679 value & 0x7);
3680 }
3681 break;
3682
3683 case AARCH64_OPND_PSTATEFIELD:
3684 for (i = 0; aarch64_pstatefields[i].name; ++i)
3685 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3686 break;
3687 assert (aarch64_pstatefields[i].name);
3688 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3689 break;
3690
3691 case AARCH64_OPND_SYSREG_AT:
3692 case AARCH64_OPND_SYSREG_DC:
3693 case AARCH64_OPND_SYSREG_IC:
3694 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3695 case AARCH64_OPND_SYSREG_SR:
875880c6 3696 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3697 break;
3698
3699 case AARCH64_OPND_BARRIER:
3700 snprintf (buf, size, "%s", opnd->barrier->name);
3701 break;
3702
3703 case AARCH64_OPND_BARRIER_ISB:
3704 /* Operand can be omitted, e.g. in DCPS1. */
3705 if (! optional_operand_p (opcode, idx)
3706 || (opnd->barrier->value
3707 != get_optional_operand_default_value (opcode)))
3708 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3709 break;
3710
3711 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3712 if (opnd->prfop->name != NULL)
3713 snprintf (buf, size, "%s", opnd->prfop->name);
3714 else
3715 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3716 break;
3717
1e6f4800 3718 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3719 case AARCH64_OPND_BTI_TARGET:
3720 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3721 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3722 break;
3723
a06ea964
NC		 3724 default:
3725 assert (0);
3726 }
3727}
3728\f
3729#define CPENC(op0,op1,crn,crm,op2) \
3730 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3731 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3732#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3733 /* for 3.9.10 System Instructions */
3734#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3735
3736#define C0 0
3737#define C1 1
3738#define C2 2
3739#define C3 3
3740#define C4 4
3741#define C5 5
3742#define C6 6
3743#define C7 7
3744#define C8 8
3745#define C9 9
3746#define C10 10
3747#define C11 11
3748#define C12 12
3749#define C13 13
3750#define C14 14
3751#define C15 15
3752
f9830ec1
TC		 3753/* TODO there is one more issues need to be resolved
3754 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3755const aarch64_sys_reg aarch64_sys_regs [] =
3756{
3757 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3758 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3759 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3760 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3761 { "sp_el0", CPEN_(0,C1,0), 0 },
3762 { "spsel", CPEN_(0,C2,0), 0 },
3763 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3764 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3765 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3766 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3767 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3768 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3769 { "fpcr", CPEN_(3,C4,0), 0 },
3770 { "fpsr", CPEN_(3,C4,1), 0 },
3771 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3772 { "dlr_el0", CPEN_(3,C5,1), 0 },
3773 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3774 { "elr_el2", CPEN_(4,C0,1), 0 },
3775 { "sp_el1", CPEN_(4,C1,0), 0 },
3776 { "spsr_irq", CPEN_(4,C3,0), 0 },
3777 { "spsr_abt", CPEN_(4,C3,1), 0 },
3778 { "spsr_und", CPEN_(4,C3,2), 0 },
3779 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3780 { "spsr_el3", CPEN_(6,C0,0), 0 },
3781 { "elr_el3", CPEN_(6,C0,1), 0 },
3782 { "sp_el2", CPEN_(6,C1,0), 0 },
3783 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3784 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3785 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3786 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3787 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3788 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3789 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3790 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3791 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3792 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3793 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3794 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3795 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3796 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3797 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3798 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3799 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3800 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3801 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3802 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3803 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3804 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3805 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3806 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3807 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3808 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3809 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3810 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3811 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3812 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3813 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3814 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3815 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3816 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3817 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3818 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3819 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3820 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3821 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3822 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3823 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3824 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3825 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3826 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3827 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3828 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3829 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3830 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3831 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3832 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3833 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3834 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3835 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3836 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3837 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3838 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3839 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3840 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3841 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3842 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3843 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3844 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3845 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3846 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3847 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3848 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3849 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3850 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3851 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3852 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3853 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3854 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3855 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3856 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3857 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3858 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3859 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3860 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3861 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3862 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3863 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3864 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3865 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3866 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3867 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3868 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3869 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3870 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3871 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3872 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3873 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3874 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3875 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3876 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3877 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3878 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3879 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3880 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3881 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3882 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3883 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3884 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3885 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3886 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3887 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3888 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3889 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3890 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3891 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3892 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3893 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3894 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3895 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3896 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3897 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3898 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3899 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3900 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3901 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3902 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3903 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3904 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3905 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3906 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3907 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3908 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3909 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3910 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3911 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3912 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3913 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3914 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3915 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3916 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3917 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3918 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3919 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3920 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3921 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3922 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3923 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3924 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3925 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
70f3d23a
SD		 3926 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
3927 { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
3928 { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
3929 { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
3930 { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
3931 { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
3932 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3933 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
49eec193 3934 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3935 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3936 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3937 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3938 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3939 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3940 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3941 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3942 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3943 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3944 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3945 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3946 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3947 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3948 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3949 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 3950 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 3951 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3952 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 3953 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 3954 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 3955 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 3956 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 3957 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 3958 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 3959 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 3960 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 3961 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 3962 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 3963 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3964 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3965 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3966 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3967 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3968 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3969 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 3970 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3971 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3972 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3973 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3974 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3975 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3976 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3977 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 3978 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 3979 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3980 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 3981 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3982 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 3983 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3984 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 3985 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3986 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3987 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3988 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3989 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3990 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3991 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3992 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3993 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3994 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3995 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3996 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3997 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3998 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3999 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4000 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4001 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4002 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4003 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4004 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4005 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4006 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4007 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4008 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4009 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4010 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4011 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4012 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4013 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4014 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4015 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4016 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4017 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4018 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4019 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4020 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4021 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4022 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4023 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4024 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4025 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4026 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4027 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4028 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4029 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4030 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4031 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4032 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4033 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4034 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4035 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4036 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4037 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4038 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4039 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4040 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4041 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4042 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4043 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4044 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4045 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4046 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4047 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4048 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4049 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4050 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4051 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4052 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4053 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4054 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4055 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4056 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4057 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4058 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4059 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4060 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4061 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4062 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4063 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4064 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4065 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4066 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4067 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4068 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4069 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4070 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4071 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4072 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4073 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4074 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4075 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4076 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4077 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4078 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4079 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4080 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4081 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4082 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4083 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4084 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4085 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4086 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4087 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4088 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4089 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4090 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4091 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4092 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4093 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4094 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4095 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4096 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4097 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4098 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4099 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4100 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4101 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4102 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4103 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4104 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4105 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4106 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4107 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4108 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4109 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4110 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4111 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4112 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4113 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4114 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4115 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4116 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4117 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4118 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4119 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4120 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4121 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4122 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4123 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4124 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4125 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4126 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4127 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4128 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4129 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4130 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4131 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4132 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4133 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4134 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4135 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4136 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4137 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4138 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4139 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4140 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4141 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4142 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4143 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4144 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4145 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4146 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4147 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4148 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4149 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4150
4151 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4152 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4153 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4154 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4155 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4156 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4157 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4158 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4159 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4160 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4161 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4162 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4163};
4164
49eec193
YZ		 4165bfd_boolean
4166aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4167{
4168 return (reg->flags & F_DEPRECATED) != 0;
4169}
4170
f21cce2c
MW		 4171bfd_boolean
4172aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4173 const aarch64_sys_reg *reg)
4174{
4175 if (!(reg->flags & F_ARCHEXT))
4176 return TRUE;
4177
4178 /* PAN. Values are from aarch64_sys_regs. */
4179 if (reg->value == CPEN_(0,C2,3)
4180 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4181 return FALSE;
4182
a97330e7
SD		 4183 /* SCXTNUM_ELx registers. */
4184 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4185 || reg->value == CPENC (3, 0, C13, C0, 7)
4186 || reg->value == CPENC (3, 4, C13, C0, 7)
4187 || reg->value == CPENC (3, 6, C13, C0, 7)
4188 || reg->value == CPENC (3, 5, C13, C0, 7))
4189 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4190 return FALSE;
4191
4192 /* ID_PFR2_EL1 register. */
4193 if (reg->value == CPENC(3, 0, C0, C3, 4)
4194 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4195 return FALSE;
4196
104fefee
SD		 4197 /* SSBS. Values are from aarch64_sys_regs. */
4198 if (reg->value == CPEN_(3,C2,6)
4199 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4200 return FALSE;
4201
250aafa4
MW		 4202 /* Virtualization host extensions: system registers. */
4203 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4204 || reg->value == CPENC (3, 4, C13, C0, 1)
4205 || reg->value == CPENC (3, 4, C14, C3, 0)
4206 || reg->value == CPENC (3, 4, C14, C3, 1)
4207 || reg->value == CPENC (3, 4, C14, C3, 2))
4208 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4209 return FALSE;
4210
4211 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4212 if ((reg->value == CPEN_ (5, C0, 0)
4213 || reg->value == CPEN_ (5, C0, 1)
4214 || reg->value == CPENC (3, 5, C1, C0, 0)
4215 || reg->value == CPENC (3, 5, C1, C0, 2)
4216 || reg->value == CPENC (3, 5, C2, C0, 0)
4217 || reg->value == CPENC (3, 5, C2, C0, 1)
4218 || reg->value == CPENC (3, 5, C2, C0, 2)
4219 || reg->value == CPENC (3, 5, C5, C1, 0)
4220 || reg->value == CPENC (3, 5, C5, C1, 1)
4221 || reg->value == CPENC (3, 5, C5, C2, 0)
4222 || reg->value == CPENC (3, 5, C6, C0, 0)
4223 || reg->value == CPENC (3, 5, C10, C2, 0)
4224 || reg->value == CPENC (3, 5, C10, C3, 0)
4225 || reg->value == CPENC (3, 5, C12, C0, 0)
4226 || reg->value == CPENC (3, 5, C13, C0, 1)
4227 || reg->value == CPENC (3, 5, C14, C1, 0))
4228 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4229 return FALSE;
4230
4231 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4232 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4233 || reg->value == CPENC (3, 5, C14, C2, 1)
4234 || reg->value == CPENC (3, 5, C14, C2, 2)
4235 || reg->value == CPENC (3, 5, C14, C3, 0)
4236 || reg->value == CPENC (3, 5, C14, C3, 1)
4237 || reg->value == CPENC (3, 5, C14, C3, 2))
4238 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4239 return FALSE;
1a04d1a7
MW		 4240
4241 /* ARMv8.2 features. */
6479e48e
MW		 4242
4243 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4244 if (reg->value == CPENC (3, 0, C0, C7, 2)
4245 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4246 return FALSE;
4247
6479e48e
MW		 4248 /* PSTATE.UAO. */
4249 if (reg->value == CPEN_ (0, C2, 4)
4250 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4251 return FALSE;
4252
47f81142
MW		 4253 /* RAS extension. */
4254
651657fa
MW		 4255 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4256 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4257 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4258 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4259 || reg->value == CPENC (3, 0, C5, C3, 2)
4260 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4261 || reg->value == CPENC (3, 0, C5, C4, 0)
4262 || reg->value == CPENC (3, 0, C5, C4, 1)
4263 || reg->value == CPENC (3, 0, C5, C4, 2)
4264 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4265 || reg->value == CPENC (3, 0, C5, C5, 0)
4266 || reg->value == CPENC (3, 0, C5, C5, 1))
4267 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4268 return FALSE;
4269
4270 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4271 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4272 || reg->value == CPENC (3, 0, C12, C1, 1)
4273 || reg->value == CPENC (3, 4, C12, C1, 1))
4274 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4275 return FALSE;
4276
55c144e6
MW		 4277 /* Statistical Profiling extension. */
4278 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4279 || reg->value == CPENC (3, 0, C9, C10, 1)
4280 || reg->value == CPENC (3, 0, C9, C10, 3)
4281 || reg->value == CPENC (3, 0, C9, C10, 7)
4282 || reg->value == CPENC (3, 0, C9, C9, 0)
4283 || reg->value == CPENC (3, 0, C9, C9, 2)
4284 || reg->value == CPENC (3, 0, C9, C9, 3)
4285 || reg->value == CPENC (3, 0, C9, C9, 4)
4286 || reg->value == CPENC (3, 0, C9, C9, 5)
4287 || reg->value == CPENC (3, 0, C9, C9, 6)
4288 || reg->value == CPENC (3, 0, C9, C9, 7)
4289 || reg->value == CPENC (3, 4, C9, C9, 0)
4290 || reg->value == CPENC (3, 5, C9, C9, 0))
4291 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4292 return FALSE;
4293
b0bfa7b5
SN		 4294 /* ARMv8.3 Pointer authentication keys. */
4295 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4296 || reg->value == CPENC (3, 0, C2, C1, 1)
4297 || reg->value == CPENC (3, 0, C2, C1, 2)
4298 || reg->value == CPENC (3, 0, C2, C1, 3)
4299 || reg->value == CPENC (3, 0, C2, C2, 0)
4300 || reg->value == CPENC (3, 0, C2, C2, 1)
4301 || reg->value == CPENC (3, 0, C2, C2, 2)
4302 || reg->value == CPENC (3, 0, C2, C2, 3)
4303 || reg->value == CPENC (3, 0, C2, C3, 0)
4304 || reg->value == CPENC (3, 0, C2, C3, 1))
4305 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4306 return FALSE;
4307
773fb663
RS		 4308 /* SVE. */
4309 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4310 || reg->value == CPENC (3, 0, C1, C2, 0)
4311 || reg->value == CPENC (3, 4, C1, C2, 0)
4312 || reg->value == CPENC (3, 6, C1, C2, 0)
4313 || reg->value == CPENC (3, 5, C1, C2, 0)
4314 || reg->value == CPENC (3, 0, C0, C0, 7))
4315 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4316 return FALSE;
4317
793a1948
TC		 4318 /* ARMv8.4 features. */
4319
4320 /* PSTATE.DIT. */
4321 if (reg->value == CPEN_ (3, C2, 5)
4322 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4323 return FALSE;
4324
4325 /* Virtualization extensions. */
4326 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4327 || reg->value == CPENC(3, 4, C2, C6, 0)
4328 || reg->value == CPENC(3, 4, C14, C4, 0)
4329 || reg->value == CPENC(3, 4, C14, C4, 2)
4330 || reg->value == CPENC(3, 4, C14, C4, 1)
4331 || reg->value == CPENC(3, 4, C14, C5, 0)
4332 || reg->value == CPENC(3, 4, C14, C5, 2)
4333 || reg->value == CPENC(3, 4, C14, C5, 1)
4334 || reg->value == CPENC(3, 4, C1, C3, 1)
4335 || reg->value == CPENC(3, 4, C2, C2, 0))
4336 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4337 return FALSE;
4338
4339 /* ARMv8.4 TLB instructions. */
4340 if ((reg->value == CPENS (0, C8, C1, 0)
4341 || reg->value == CPENS (0, C8, C1, 1)
4342 || reg->value == CPENS (0, C8, C1, 2)
4343 || reg->value == CPENS (0, C8, C1, 3)
4344 || reg->value == CPENS (0, C8, C1, 5)
4345 || reg->value == CPENS (0, C8, C1, 7)
4346 || reg->value == CPENS (4, C8, C4, 0)
4347 || reg->value == CPENS (4, C8, C4, 4)
4348 || reg->value == CPENS (4, C8, C1, 1)
4349 || reg->value == CPENS (4, C8, C1, 5)
4350 || reg->value == CPENS (4, C8, C1, 6)
4351 || reg->value == CPENS (6, C8, C1, 1)
4352 || reg->value == CPENS (6, C8, C1, 5)
4353 || reg->value == CPENS (4, C8, C1, 0)
4354 || reg->value == CPENS (4, C8, C1, 4)
4355 || reg->value == CPENS (6, C8, C1, 0)
4356 || reg->value == CPENS (0, C8, C6, 1)
4357 || reg->value == CPENS (0, C8, C6, 3)
4358 || reg->value == CPENS (0, C8, C6, 5)
4359 || reg->value == CPENS (0, C8, C6, 7)
4360 || reg->value == CPENS (0, C8, C2, 1)
4361 || reg->value == CPENS (0, C8, C2, 3)
4362 || reg->value == CPENS (0, C8, C2, 5)
4363 || reg->value == CPENS (0, C8, C2, 7)
4364 || reg->value == CPENS (0, C8, C5, 1)
4365 || reg->value == CPENS (0, C8, C5, 3)
4366 || reg->value == CPENS (0, C8, C5, 5)
4367 || reg->value == CPENS (0, C8, C5, 7)
4368 || reg->value == CPENS (4, C8, C0, 2)
4369 || reg->value == CPENS (4, C8, C0, 6)
4370 || reg->value == CPENS (4, C8, C4, 2)
4371 || reg->value == CPENS (4, C8, C4, 6)
4372 || reg->value == CPENS (4, C8, C4, 3)
4373 || reg->value == CPENS (4, C8, C4, 7)
4374 || reg->value == CPENS (4, C8, C6, 1)
4375 || reg->value == CPENS (4, C8, C6, 5)
4376 || reg->value == CPENS (4, C8, C2, 1)
4377 || reg->value == CPENS (4, C8, C2, 5)
4378 || reg->value == CPENS (4, C8, C5, 1)
4379 || reg->value == CPENS (4, C8, C5, 5)
4380 || reg->value == CPENS (6, C8, C6, 1)
4381 || reg->value == CPENS (6, C8, C6, 5)
4382 || reg->value == CPENS (6, C8, C2, 1)
4383 || reg->value == CPENS (6, C8, C2, 5)
4384 || reg->value == CPENS (6, C8, C5, 1)
4385 || reg->value == CPENS (6, C8, C5, 5))
4386 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4387 return FALSE;
4388
af4bcb4c
SD		 4389 /* Random Number Instructions. For now they are available
4390 (and optional) only with ARMv8.5-A. */
4391 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4392 || reg->value == CPENC (3, 3, C2, C4, 1))
4393 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4394 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4395 return FALSE;
4396
70f3d23a
SD		 4397 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4398 if ((reg->value == CPENC (3, 3, C4, C2, 7)
4399 || reg->value == CPENC (3, 0, C6, C6, 1)
4400 || reg->value == CPENC (3, 0, C6, C5, 0)
4401 || reg->value == CPENC (3, 4, C6, C5, 0)
4402 || reg->value == CPENC (3, 6, C6, C6, 0)
4403 || reg->value == CPENC (3, 5, C6, C6, 0)
4404 || reg->value == CPENC (3, 0, C1, C0, 5)
4405 || reg->value == CPENC (3, 0, C1, C0, 6))
4406 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4407 return FALSE;
4408
f21cce2c
MW		 4409 return TRUE;
4410}
4411
793a1948
TC		 4412/* The CPENC below is fairly misleading, the fields
4413 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4414 by ins_pstatefield, which just shifts the value by the width of the fields
4415 in a loop. So if you CPENC them only the first value will be set, the rest
4416 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4417 value of 0b110000000001000000 (0x30040) while what you want is
4418 0b011010 (0x1a). */
87b8eed7 4419const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4420{
87b8eed7
YZ		 4421 { "spsel", 0x05, 0 },
4422 { "daifset", 0x1e, 0 },
4423 { "daifclr", 0x1f, 0 },
f21cce2c 4424 { "pan", 0x04, F_ARCHEXT },
6479e48e 4425 { "uao", 0x03, F_ARCHEXT },
104fefee 4426 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4427 { "dit", 0x1a, F_ARCHEXT },
70f3d23a 4428 { "tco", 0x1c, F_ARCHEXT },
87b8eed7 4429 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4430};
4431
f21cce2c
MW		 4432bfd_boolean
4433aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4434 const aarch64_sys_reg *reg)
4435{
4436 if (!(reg->flags & F_ARCHEXT))
4437 return TRUE;
4438
4439 /* PAN. Values are from aarch64_pstatefields. */
4440 if (reg->value == 0x04
4441 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4442 return FALSE;
4443
6479e48e
MW		 4444 /* UAO. Values are from aarch64_pstatefields. */
4445 if (reg->value == 0x03
4446 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4447 return FALSE;
4448
104fefee
SD		 4449 /* SSBS. Values are from aarch64_pstatefields. */
4450 if (reg->value == 0x19
4451 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4452 return FALSE;
4453
793a1948
TC		 4454 /* DIT. Values are from aarch64_pstatefields. */
4455 if (reg->value == 0x1a
4456 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4457 return FALSE;
4458
70f3d23a
SD		 4459 /* TCO. Values are from aarch64_pstatefields. */
4460 if (reg->value == 0x1c
4461 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4462 return FALSE;
4463
f21cce2c
MW		 4464 return TRUE;
4465}
4466
a06ea964
NC		 4467const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4468{
4469 { "ialluis", CPENS(0,C7,C1,0), 0 },
4470 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4471 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4472 { 0, CPENS(0,0,0,0), 0 }
4473};
4474
4475const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4476{
ea2deeec 4477 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4478 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4479 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4480 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4481 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4482 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4483 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4484 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4485 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4486 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4487 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4488 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4489 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4490 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4491 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4492 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4493 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4494 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4495 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4496 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4497 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4498 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4499 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4500 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4501 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4502 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4503 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4504 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4505 { 0, CPENS(0,0,0,0), 0 }
4506};
4507
4508const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4509{
ea2deeec
MW		 4510 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4511 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4512 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4513 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4514 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4515 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4516 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4517 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4518 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4519 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4520 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4521 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4522 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4523 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4524 { 0, CPENS(0,0,0,0), 0 }
4525};
4526
4527const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4528{
4529 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4530 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4531 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4532 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4533 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4534 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4535 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4536 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4537 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4538 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4539 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4540 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4541 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4542 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4543 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4544 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4545 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4546 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4547 { "alle2", CPENS(4,C8,C7,0), 0 },
4548 { "alle2is", CPENS(4,C8,C3,0), 0 },
4549 { "alle1", CPENS(4,C8,C7,4), 0 },
4550 { "alle1is", CPENS(4,C8,C3,4), 0 },
4551 { "alle3", CPENS(6,C8,C7,0), 0 },
4552 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4553 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4554 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4555 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4556 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4557 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4558 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4559 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4560 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4561
4562 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4563 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4564 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4565 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4566 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4567 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4568 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4569 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4570 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4571 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4572 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4573 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4574 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4575 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4576 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4577 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4578
4579 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4580 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4581 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4582 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4583 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4584 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4585 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4586 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4587 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4588 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4589 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4590 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4591 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4592 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4593 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4594 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4595 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4596 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4597 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4598 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4599 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4600 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4601 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4602 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4603 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4604 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4605 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4606 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4607 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4608 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4609
a06ea964
NC		 4610 { 0, CPENS(0,0,0,0), 0 }
4611};
4612
2ac435d4
SD		 4613const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4614{
4615 /* RCTX is somewhat unique in a way that it has different values
4616 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4617 Thus op2 is masked out and instead encoded directly in the
4618 aarch64_opcode_table entries for the respective instructions. */
4619 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4620
4621 { 0, CPENS(0,0,0,0), 0 }
4622};
4623
ea2deeec
MW		 4624bfd_boolean
4625aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4626{
4627 return (sys_ins_reg->flags & F_HASXT) != 0;
4628}
4629
d6bf7ce6
MW		 4630extern bfd_boolean
4631aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4632 const aarch64_sys_ins_reg *reg)
4633{
4634 if (!(reg->flags & F_ARCHEXT))
4635 return TRUE;
4636
4637 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4638 if (reg->value == CPENS (3, C7, C12, 1)
4639 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4640 return FALSE;
4641
3fd229a4
SD		 4642 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4643 if (reg->value == CPENS (3, C7, C13, 1)
4644 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4645 return FALSE;
4646
3a0f69be
SD		 4647 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4648 if ((reg->value == CPENS (0, C7, C6, 3)
4649 || reg->value == CPENS (0, C7, C6, 4)
4650 || reg->value == CPENS (0, C7, C10, 4)
4651 || reg->value == CPENS (0, C7, C14, 4)
4652 || reg->value == CPENS (3, C7, C10, 3)
4653 || reg->value == CPENS (3, C7, C12, 3)
4654 || reg->value == CPENS (3, C7, C13, 3)
4655 || reg->value == CPENS (3, C7, C14, 3)
4656 || reg->value == CPENS (3, C7, C4, 3)
4657 || reg->value == CPENS (0, C7, C6, 5)
4658 || reg->value == CPENS (0, C7, C6, 6)
4659 || reg->value == CPENS (0, C7, C10, 6)
4660 || reg->value == CPENS (0, C7, C14, 6)
4661 || reg->value == CPENS (3, C7, C10, 5)
4662 || reg->value == CPENS (3, C7, C12, 5)
4663 || reg->value == CPENS (3, C7, C13, 5)
4664 || reg->value == CPENS (3, C7, C14, 5)
4665 || reg->value == CPENS (3, C7, C4, 4))
4666 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4667 return FALSE;
4668
63511907
MW		 4669 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4670 if ((reg->value == CPENS (0, C7, C9, 0)
4671 || reg->value == CPENS (0, C7, C9, 1))
4672 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4673 return FALSE;
4674
2ac435d4
SD		 4675 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4676 if (reg->value == CPENS (3, C7, C3, 0)
4677 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4678 return FALSE;
4679
d6bf7ce6
MW		 4680 return TRUE;
4681}
4682
a06ea964
NC		 4683#undef C0
4684#undef C1
4685#undef C2
4686#undef C3
4687#undef C4
4688#undef C5
4689#undef C6
4690#undef C7
4691#undef C8
4692#undef C9
4693#undef C10
4694#undef C11
4695#undef C12
4696#undef C13
4697#undef C14
4698#undef C15
4699
4bd13cde
NC		 4700#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4701#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4702
755b748f
TC		 4703static enum err_type
4704verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4705 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4706 bfd_boolean encoding ATTRIBUTE_UNUSED,
4707 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4708 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4709{
4710 int t = BITS (insn, 4, 0);
4711 int n = BITS (insn, 9, 5);
4712 int t2 = BITS (insn, 14, 10);
4713
4714 if (BIT (insn, 23))
4715 {
4716 /* Write back enabled. */
4717 if ((t == n || t2 == n) && n != 31)
755b748f 4718 return ERR_UND;
4bd13cde
NC		 4719 }
4720
4721 if (BIT (insn, 22))
4722 {
4723 /* Load */
4724 if (t == t2)
755b748f 4725 return ERR_UND;
4bd13cde
NC		 4726 }
4727
755b748f 4728 return ERR_OK;
4bd13cde
NC		 4729}
4730
a68f4cd2
TC		 4731/* Initialize an instruction sequence insn_sequence with the instruction INST.
4732 If INST is NULL the given insn_sequence is cleared and the sequence is left
4733 uninitialized. */
4734
4735void
4736init_insn_sequence (const struct aarch64_inst *inst,
4737 aarch64_instr_sequence *insn_sequence)
4738{
4739 int num_req_entries = 0;
4740 insn_sequence->next_insn = 0;
4741 insn_sequence->num_insns = num_req_entries;
4742 if (insn_sequence->instr)
4743 XDELETE (insn_sequence->instr);
4744 insn_sequence->instr = NULL;
4745
4746 if (inst)
4747 {
4748 insn_sequence->instr = XNEW (aarch64_inst);
4749 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4750 }
4751
4752 /* Handle all the cases here. May need to think of something smarter than
4753 a giant if/else chain if this grows. At that time, a lookup table may be
4754 best. */
4755 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4756 num_req_entries = 1;
4757
4758 if (insn_sequence->current_insns)
4759 XDELETEVEC (insn_sequence->current_insns);
4760 insn_sequence->current_insns = NULL;
4761
4762 if (num_req_entries != 0)
4763 {
4764 size_t size = num_req_entries * sizeof (aarch64_inst);
4765 insn_sequence->current_insns
4766 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4767 memset (insn_sequence->current_insns, 0, size);
4768 }
4769}
4770
4771
4772/* This function verifies that the instruction INST adheres to its specified
4773 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4774 returned and MISMATCH_DETAIL contains the reason why verification failed.
4775
4776 The function is called both during assembly and disassembly. If assembling
4777 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4778 and will contain the PC of the current instruction w.r.t to the section.
4779
4780 If ENCODING and PC=0 then you are at a start of a section. The constraints
4781 are verified against the given state insn_sequence which is updated as it
4782 transitions through the verification. */
4783
4784enum err_type
4785verify_constraints (const struct aarch64_inst *inst,
4786 const aarch64_insn insn ATTRIBUTE_UNUSED,
4787 bfd_vma pc,
4788 bfd_boolean encoding,
4789 aarch64_operand_error *mismatch_detail,
4790 aarch64_instr_sequence *insn_sequence)
4791{
4792 assert (inst);
4793 assert (inst->opcode);
4794
4795 const struct aarch64_opcode *opcode = inst->opcode;
4796 if (!opcode->constraints && !insn_sequence->instr)
4797 return ERR_OK;
4798
4799 assert (insn_sequence);
4800
4801 enum err_type res = ERR_OK;
4802
4803 /* This instruction puts a constraint on the insn_sequence. */
4804 if (opcode->flags & F_SCAN)
4805 {
4806 if (insn_sequence->instr)
4807 {
4808 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4809 mismatch_detail->error = _("instruction opens new dependency "
4810 "sequence without ending previous one");
4811 mismatch_detail->index = -1;
4812 mismatch_detail->non_fatal = TRUE;
4813 res = ERR_VFI;
4814 }
4815
4816 init_insn_sequence (inst, insn_sequence);
4817 return res;
4818 }
4819
4820 /* Verify constraints on an existing sequence. */
4821 if (insn_sequence->instr)
4822 {
4823 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4824 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4825 closed a previous one that we should have. */
4826 if (!encoding && pc == 0)
4827 {
4828 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4829 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4830 mismatch_detail->index = -1;
4831 mismatch_detail->non_fatal = TRUE;
4832 res = ERR_VFI;
4833 /* Reset the sequence. */
4834 init_insn_sequence (NULL, insn_sequence);
4835 return res;
4836 }
4837
4838 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4839 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4840 {
4841 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4842 instruction for better error messages. */
4843 if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
4844 {
4845 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4846 mismatch_detail->error = _("SVE instruction expected after "
4847 "`movprfx'");
4848 mismatch_detail->index = -1;
4849 mismatch_detail->non_fatal = TRUE;
4850 res = ERR_VFI;
4851 goto done;
4852 }
4853
4854 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4855 instruction that is allowed to be used with a MOVPRFX. */
4856 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4857 {
4858 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4859 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4860 "expected");
4861 mismatch_detail->index = -1;
4862 mismatch_detail->non_fatal = TRUE;
4863 res = ERR_VFI;
4864 goto done;
4865 }
4866
4867 /* Next check for usage of the predicate register. */
4868 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4869 aarch64_opnd_info blk_pred, inst_pred;
4870 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4871 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4872 bfd_boolean predicated = FALSE;
4873 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4874
4875 /* Determine if the movprfx instruction used is predicated or not. */
4876 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4877 {
4878 predicated = TRUE;
4879 blk_pred = insn_sequence->instr->operands[1];
4880 }
4881
4882 unsigned char max_elem_size = 0;
4883 unsigned char current_elem_size;
4884 int num_op_used = 0, last_op_usage = 0;
4885 int i, inst_pred_idx = -1;
4886 int num_ops = aarch64_num_of_operands (opcode);
4887 for (i = 0; i < num_ops; i++)
4888 {
4889 aarch64_opnd_info inst_op = inst->operands[i];
4890 switch (inst_op.type)
4891 {
4892 case AARCH64_OPND_SVE_Zd:
4893 case AARCH64_OPND_SVE_Zm_5:
4894 case AARCH64_OPND_SVE_Zm_16:
4895 case AARCH64_OPND_SVE_Zn:
4896 case AARCH64_OPND_SVE_Zt:
4897 case AARCH64_OPND_SVE_Vm:
4898 case AARCH64_OPND_SVE_Vn:
4899 case AARCH64_OPND_Va:
4900 case AARCH64_OPND_Vn:
4901 case AARCH64_OPND_Vm:
4902 case AARCH64_OPND_Sn:
4903 case AARCH64_OPND_Sm:
4904 case AARCH64_OPND_Rn:
4905 case AARCH64_OPND_Rm:
4906 case AARCH64_OPND_Rn_SP:
4907 case AARCH64_OPND_Rm_SP:
4908 if (inst_op.reg.regno == blk_dest.reg.regno)
4909 {
4910 num_op_used++;
4911 last_op_usage = i;
4912 }
4913 current_elem_size
4914 = aarch64_get_qualifier_esize (inst_op.qualifier);
4915 if (current_elem_size > max_elem_size)
4916 max_elem_size = current_elem_size;
4917 break;
4918 case AARCH64_OPND_SVE_Pd:
4919 case AARCH64_OPND_SVE_Pg3:
4920 case AARCH64_OPND_SVE_Pg4_5:
4921 case AARCH64_OPND_SVE_Pg4_10:
4922 case AARCH64_OPND_SVE_Pg4_16:
4923 case AARCH64_OPND_SVE_Pm:
4924 case AARCH64_OPND_SVE_Pn:
4925 case AARCH64_OPND_SVE_Pt:
4926 inst_pred = inst_op;
4927 inst_pred_idx = i;
4928 break;
4929 default:
4930 break;
4931 }
4932 }
4933
4934 assert (max_elem_size != 0);
4935 aarch64_opnd_info inst_dest = inst->operands[0];
4936 /* Determine the size that should be used to compare against the
4937 movprfx size. */
4938 current_elem_size
4939 = opcode->constraints & C_MAX_ELEM
4940 ? max_elem_size
4941 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4942
4943 /* If movprfx is predicated do some extra checks. */
4944 if (predicated)
4945 {
4946 /* The instruction must be predicated. */
4947 if (inst_pred_idx < 0)
4948 {
4949 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4950 mismatch_detail->error = _("predicated instruction expected "
4951 "after `movprfx'");
4952 mismatch_detail->index = -1;
4953 mismatch_detail->non_fatal = TRUE;
4954 res = ERR_VFI;
4955 goto done;
4956 }
4957
4958 /* The instruction must have a merging predicate. */
4959 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4960 {
4961 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4962 mismatch_detail->error = _("merging predicate expected due "
4963 "to preceding `movprfx'");
4964 mismatch_detail->index = inst_pred_idx;
4965 mismatch_detail->non_fatal = TRUE;
4966 res = ERR_VFI;
4967 goto done;
4968 }
4969
4970 /* The same register must be used in instruction. */
4971 if (blk_pred.reg.regno != inst_pred.reg.regno)
4972 {
4973 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4974 mismatch_detail->error = _("predicate register differs "
4975 "from that in preceding "
4976 "`movprfx'");
4977 mismatch_detail->index = inst_pred_idx;
4978 mismatch_detail->non_fatal = TRUE;
4979 res = ERR_VFI;
4980 goto done;
4981 }
4982 }
4983
4984 /* Destructive operations by definition must allow one usage of the
4985 same register. */
4986 int allowed_usage
4987 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4988
4989 /* Operand is not used at all. */
4990 if (num_op_used == 0)
4991 {
4992 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4993 mismatch_detail->error = _("output register of preceding "
4994 "`movprfx' not used in current "
4995 "instruction");
4996 mismatch_detail->index = 0;
4997 mismatch_detail->non_fatal = TRUE;
4998 res = ERR_VFI;
4999 goto done;
5000 }
5001
5002 /* We now know it's used, now determine exactly where it's used. */
5003 if (blk_dest.reg.regno != inst_dest.reg.regno)
5004 {
5005 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5006 mismatch_detail->error = _("output register of preceding "
5007 "`movprfx' expected as output");
5008 mismatch_detail->index = 0;
5009 mismatch_detail->non_fatal = TRUE;
5010 res = ERR_VFI;
5011 goto done;
5012 }
5013
5014 /* Operand used more than allowed for the specific opcode type. */
5015 if (num_op_used > allowed_usage)
5016 {
5017 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5018 mismatch_detail->error = _("output register of preceding "
5019 "`movprfx' used as input");
5020 mismatch_detail->index = last_op_usage;
5021 mismatch_detail->non_fatal = TRUE;
5022 res = ERR_VFI;
5023 goto done;
5024 }
5025
5026 /* Now the only thing left is the qualifiers checks. The register
5027 must have the same maximum element size. */
5028 if (inst_dest.qualifier
5029 && blk_dest.qualifier
5030 && current_elem_size
5031 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5032 {
5033 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5034 mismatch_detail->error = _("register size not compatible with "
5035 "previous `movprfx'");
5036 mismatch_detail->index = 0;
5037 mismatch_detail->non_fatal = TRUE;
5038 res = ERR_VFI;
5039 goto done;
5040 }
5041 }
5042
5043done:
5044 /* Add the new instruction to the sequence. */
5045 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5046 inst, sizeof (aarch64_inst));
5047
5048 /* Check if sequence is now full. */
5049 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5050 {
5051 /* Sequence is full, but we don't have anything special to do for now,
5052 so clear and reset it. */
5053 init_insn_sequence (NULL, insn_sequence);
5054 }
5055 }
5056
5057 return res;
5058}
5059
5060
e950b345
RS		 5061/* Return true if VALUE cannot be moved into an SVE register using DUP
5062 (with any element size, not just ESIZE) and if using DUPM would
5063 therefore be OK. ESIZE is the number of bytes in the immediate. */
5064
5065bfd_boolean
5066aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5067{
5068 int64_t svalue = uvalue;
5069 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5070
5071 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5072 return FALSE;
5073 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5074 {
5075 svalue = (int32_t) uvalue;
5076 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5077 {
5078 svalue = (int16_t) uvalue;
5079 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5080 return FALSE;
5081 }
5082 }
5083 if ((svalue & 0xff) == 0)
5084 svalue /= 256;
5085 return svalue < -128 || svalue >= 128;
5086}
5087
a06ea964
NC		 5088/* Include the opcode description table as well as the operand description
5089 table. */
20f55f38 5090#define VERIFIER(x) verify_##x
a06ea964 5091#include "aarch64-tbl.h"
GDB Binutils - Deliverables
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