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[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
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a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
31e36ab3 299 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
e950b345 300 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 301 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 302 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
303 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 304 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 305 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
306 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
307 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
308 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
309 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 310 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 311 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
312 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 313 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
314 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 315 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 316 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 317 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
0a57e14f 318 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
116b6019 319 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 320 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 321 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
322 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 323 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 324 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
325 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
326 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
327 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 328 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 329 { 22, 1 }, /* sz: 1-bit element size select. */
a06ea964
NC		 330};
331
332enum aarch64_operand_class
333aarch64_get_operand_class (enum aarch64_opnd type)
334{
335 return aarch64_operands[type].op_class;
336}
337
338const char *
339aarch64_get_operand_name (enum aarch64_opnd type)
340{
341 return aarch64_operands[type].name;
342}
343
344/* Get operand description string.
345 This is usually for the diagnosis purpose. */
346const char *
347aarch64_get_operand_desc (enum aarch64_opnd type)
348{
349 return aarch64_operands[type].desc;
350}
351
352/* Table of all conditional affixes. */
353const aarch64_cond aarch64_conds[16] =
354{
bb7eff52
RS		 355 {{"eq", "none"}, 0x0},
356 {{"ne", "any"}, 0x1},
357 {{"cs", "hs", "nlast"}, 0x2},
358 {{"cc", "lo", "ul", "last"}, 0x3},
359 {{"mi", "first"}, 0x4},
360 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 361 {{"vs"}, 0x6},
362 {{"vc"}, 0x7},
bb7eff52
RS		 363 {{"hi", "pmore"}, 0x8},
364 {{"ls", "plast"}, 0x9},
365 {{"ge", "tcont"}, 0xa},
366 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 367 {{"gt"}, 0xc},
368 {{"le"}, 0xd},
369 {{"al"}, 0xe},
370 {{"nv"}, 0xf},
371};
372
373const aarch64_cond *
374get_cond_from_value (aarch64_insn value)
375{
376 assert (value < 16);
377 return &aarch64_conds[(unsigned int) value];
378}
379
380const aarch64_cond *
381get_inverted_cond (const aarch64_cond *cond)
382{
383 return &aarch64_conds[cond->value ^ 0x1];
384}
385
386/* Table describing the operand extension/shifting operators; indexed by
387 enum aarch64_modifier_kind.
388
389 The value column provides the most common values for encoding modifiers,
390 which enables table-driven encoding/decoding for the modifiers. */
391const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
392{
393 {"none", 0x0},
394 {"msl", 0x0},
395 {"ror", 0x3},
396 {"asr", 0x2},
397 {"lsr", 0x1},
398 {"lsl", 0x0},
399 {"uxtb", 0x0},
400 {"uxth", 0x1},
401 {"uxtw", 0x2},
402 {"uxtx", 0x3},
403 {"sxtb", 0x4},
404 {"sxth", 0x5},
405 {"sxtw", 0x6},
406 {"sxtx", 0x7},
2442d846 407 {"mul", 0x0},
98907a70 408 {"mul vl", 0x0},
a06ea964
NC		 409 {NULL, 0},
410};
411
412enum aarch64_modifier_kind
413aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
414{
415 return desc - aarch64_operand_modifiers;
416}
417
418aarch64_insn
419aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
420{
421 return aarch64_operand_modifiers[kind].value;
422}
423
424enum aarch64_modifier_kind
425aarch64_get_operand_modifier_from_value (aarch64_insn value,
426 bfd_boolean extend_p)
427{
428 if (extend_p == TRUE)
429 return AARCH64_MOD_UXTB + value;
430 else
431 return AARCH64_MOD_LSL - value;
432}
433
434bfd_boolean
435aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
436{
437 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
438 ? TRUE : FALSE;
439}
440
441static inline bfd_boolean
442aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
443{
444 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
445 ? TRUE : FALSE;
446}
447
448const struct aarch64_name_value_pair aarch64_barrier_options[16] =
449{
450 { "#0x00", 0x0 },
451 { "oshld", 0x1 },
452 { "oshst", 0x2 },
453 { "osh", 0x3 },
454 { "#0x04", 0x4 },
455 { "nshld", 0x5 },
456 { "nshst", 0x6 },
457 { "nsh", 0x7 },
458 { "#0x08", 0x8 },
459 { "ishld", 0x9 },
460 { "ishst", 0xa },
461 { "ish", 0xb },
462 { "#0x0c", 0xc },
463 { "ld", 0xd },
464 { "st", 0xe },
465 { "sy", 0xf },
466};
467
9ed608f9
MW		 468/* Table describing the operands supported by the aliases of the HINT
469 instruction.
470
471 The name column is the operand that is accepted for the alias. The value
472 column is the hint number of the alias. The list of operands is terminated
473 by NULL in the name column. */
474
475const struct aarch64_name_value_pair aarch64_hint_options[] =
476{
ff605452
SD		 477 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
478 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
479 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
480 { "c", HINT_OPD_C }, /* BTI C. */
481 { "j", HINT_OPD_J }, /* BTI J. */
482 { "jc", HINT_OPD_JC }, /* BTI JC. */
483 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 484};
485
a32c3ff8 486/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 487 l -> level: 1-3
488 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 489#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 490const struct aarch64_name_value_pair aarch64_prfops[32] =
491{
492 { "pldl1keep", B(0, 1, 0) },
493 { "pldl1strm", B(0, 1, 1) },
494 { "pldl2keep", B(0, 2, 0) },
495 { "pldl2strm", B(0, 2, 1) },
496 { "pldl3keep", B(0, 3, 0) },
497 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 498 { NULL, 0x06 },
499 { NULL, 0x07 },
a32c3ff8
NC		 500 { "plil1keep", B(1, 1, 0) },
501 { "plil1strm", B(1, 1, 1) },
502 { "plil2keep", B(1, 2, 0) },
503 { "plil2strm", B(1, 2, 1) },
504 { "plil3keep", B(1, 3, 0) },
505 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 506 { NULL, 0x0e },
507 { NULL, 0x0f },
a32c3ff8
NC		 508 { "pstl1keep", B(2, 1, 0) },
509 { "pstl1strm", B(2, 1, 1) },
510 { "pstl2keep", B(2, 2, 0) },
511 { "pstl2strm", B(2, 2, 1) },
512 { "pstl3keep", B(2, 3, 0) },
513 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 514 { NULL, 0x16 },
515 { NULL, 0x17 },
516 { NULL, 0x18 },
517 { NULL, 0x19 },
518 { NULL, 0x1a },
519 { NULL, 0x1b },
520 { NULL, 0x1c },
521 { NULL, 0x1d },
522 { NULL, 0x1e },
523 { NULL, 0x1f },
a06ea964
NC		 524};
525#undef B
526\f
527/* Utilities on value constraint. */
528
529static inline int
530value_in_range_p (int64_t value, int low, int high)
531{
532 return (value >= low && value <= high) ? 1 : 0;
533}
534
98907a70 535/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 536static inline int
537value_aligned_p (int64_t value, int align)
538{
98907a70 539 return (value % align) == 0;
a06ea964
NC		 540}
541
542/* A signed value fits in a field. */
543static inline int
544value_fit_signed_field_p (int64_t value, unsigned width)
545{
546 assert (width < 32);
547 if (width < sizeof (value) * 8)
548 {
549 int64_t lim = (int64_t)1 << (width - 1);
550 if (value >= -lim && value < lim)
551 return 1;
552 }
553 return 0;
554}
555
556/* An unsigned value fits in a field. */
557static inline int
558value_fit_unsigned_field_p (int64_t value, unsigned width)
559{
560 assert (width < 32);
561 if (width < sizeof (value) * 8)
562 {
563 int64_t lim = (int64_t)1 << width;
564 if (value >= 0 && value < lim)
565 return 1;
566 }
567 return 0;
568}
569
570/* Return 1 if OPERAND is SP or WSP. */
571int
572aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
573{
574 return ((aarch64_get_operand_class (operand->type)
575 == AARCH64_OPND_CLASS_INT_REG)
576 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
577 && operand->reg.regno == 31);
578}
579
580/* Return 1 if OPERAND is XZR or WZP. */
581int
582aarch64_zero_register_p (const aarch64_opnd_info *operand)
583{
584 return ((aarch64_get_operand_class (operand->type)
585 == AARCH64_OPND_CLASS_INT_REG)
586 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
587 && operand->reg.regno == 31);
588}
589
590/* Return true if the operand *OPERAND that has the operand code
591 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
592 qualified by the qualifier TARGET. */
593
594static inline int
595operand_also_qualified_p (const struct aarch64_opnd_info *operand,
596 aarch64_opnd_qualifier_t target)
597{
598 switch (operand->qualifier)
599 {
600 case AARCH64_OPND_QLF_W:
601 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
602 return 1;
603 break;
604 case AARCH64_OPND_QLF_X:
605 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
606 return 1;
607 break;
608 case AARCH64_OPND_QLF_WSP:
609 if (target == AARCH64_OPND_QLF_W
610 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
611 return 1;
612 break;
613 case AARCH64_OPND_QLF_SP:
614 if (target == AARCH64_OPND_QLF_X
615 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
616 return 1;
617 break;
618 default:
619 break;
620 }
621
622 return 0;
623}
624
625/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
626 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
627
628 Return NIL if more than one expected qualifiers are found. */
629
630aarch64_opnd_qualifier_t
631aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
632 int idx,
633 const aarch64_opnd_qualifier_t known_qlf,
634 int known_idx)
635{
636 int i, saved_i;
637
638 /* Special case.
639
640 When the known qualifier is NIL, we have to assume that there is only
641 one qualifier sequence in the *QSEQ_LIST and return the corresponding
642 qualifier directly. One scenario is that for instruction
643 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
644 which has only one possible valid qualifier sequence
645 NIL, S_D
646 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
647 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
648
649 Because the qualifier NIL has dual roles in the qualifier sequence:
650 it can mean no qualifier for the operand, or the qualifer sequence is
651 not in use (when all qualifiers in the sequence are NILs), we have to
652 handle this special case here. */
653 if (known_qlf == AARCH64_OPND_NIL)
654 {
655 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
656 return qseq_list[0][idx];
657 }
658
659 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
660 {
661 if (qseq_list[i][known_idx] == known_qlf)
662 {
663 if (saved_i != -1)
664 /* More than one sequences are found to have KNOWN_QLF at
665 KNOWN_IDX. */
666 return AARCH64_OPND_NIL;
667 saved_i = i;
668 }
669 }
670
671 return qseq_list[saved_i][idx];
672}
673
674enum operand_qualifier_kind
675{
676 OQK_NIL,
677 OQK_OPD_VARIANT,
678 OQK_VALUE_IN_RANGE,
679 OQK_MISC,
680};
681
682/* Operand qualifier description. */
683struct operand_qualifier_data
684{
685 /* The usage of the three data fields depends on the qualifier kind. */
686 int data0;
687 int data1;
688 int data2;
689 /* Description. */
690 const char *desc;
691 /* Kind. */
692 enum operand_qualifier_kind kind;
693};
694
695/* Indexed by the operand qualifier enumerators. */
696struct operand_qualifier_data aarch64_opnd_qualifiers[] =
697{
698 {0, 0, 0, "NIL", OQK_NIL},
699
700 /* Operand variant qualifiers.
701 First 3 fields:
702 element size, number of elements and common value for encoding. */
703
704 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
705 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
706 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
707 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
708
709 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
710 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
711 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
712 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
713 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 714 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
df678013 715 {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964 716
a3b3345a 717 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 718 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
719 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 720 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 721 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
722 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
723 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
724 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
725 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
726 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
727 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
728
d50c751e
RS		 729 {0, 0, 0, "z", OQK_OPD_VARIANT},
730 {0, 0, 0, "m", OQK_OPD_VARIANT},
731
fb3265b3
SD		 732 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
733 {16, 0, 0, "tag", OQK_OPD_VARIANT},
734
a06ea964
NC		 735 /* Qualifiers constraining the value range.
736 First 3 fields:
737 Lower bound, higher bound, unused. */
738
a6a51754 739 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 740 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
741 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
742 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
743 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
744 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
745 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
746
747 /* Qualifiers for miscellaneous purpose.
748 First 3 fields:
749 unused, unused and unused. */
750
751 {0, 0, 0, "lsl", 0},
752 {0, 0, 0, "msl", 0},
753
754 {0, 0, 0, "retrieving", 0},
755};
756
757static inline bfd_boolean
758operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
759{
760 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
761 ? TRUE : FALSE;
762}
763
764static inline bfd_boolean
765qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
766{
767 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
768 ? TRUE : FALSE;
769}
770
771const char*
772aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
773{
774 return aarch64_opnd_qualifiers[qualifier].desc;
775}
776
777/* Given an operand qualifier, return the expected data element size
778 of a qualified operand. */
779unsigned char
780aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
781{
782 assert (operand_variant_qualifier_p (qualifier) == TRUE);
783 return aarch64_opnd_qualifiers[qualifier].data0;
784}
785
786unsigned char
787aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
788{
789 assert (operand_variant_qualifier_p (qualifier) == TRUE);
790 return aarch64_opnd_qualifiers[qualifier].data1;
791}
792
793aarch64_insn
794aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
795{
796 assert (operand_variant_qualifier_p (qualifier) == TRUE);
797 return aarch64_opnd_qualifiers[qualifier].data2;
798}
799
800static int
801get_lower_bound (aarch64_opnd_qualifier_t qualifier)
802{
803 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
804 return aarch64_opnd_qualifiers[qualifier].data0;
805}
806
807static int
808get_upper_bound (aarch64_opnd_qualifier_t qualifier)
809{
810 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
811 return aarch64_opnd_qualifiers[qualifier].data1;
812}
813
814#ifdef DEBUG_AARCH64
815void
816aarch64_verbose (const char *str, ...)
817{
818 va_list ap;
819 va_start (ap, str);
820 printf ("#### ");
821 vprintf (str, ap);
822 printf ("\n");
823 va_end (ap);
824}
825
826static inline void
827dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
828{
829 int i;
830 printf ("#### \t");
831 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
832 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
833 printf ("\n");
834}
835
836static void
837dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
838 const aarch64_opnd_qualifier_t *qualifier)
839{
840 int i;
841 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
842
843 aarch64_verbose ("dump_match_qualifiers:");
844 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
845 curr[i] = opnd[i].qualifier;
846 dump_qualifier_sequence (curr);
847 aarch64_verbose ("against");
848 dump_qualifier_sequence (qualifier);
849}
850#endif /* DEBUG_AARCH64 */
851
a68f4cd2
TC		 852/* This function checks if the given instruction INSN is a destructive
853 instruction based on the usage of the registers. It does not recognize
854 unary destructive instructions. */
855bfd_boolean
856aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
857{
858 int i = 0;
859 const enum aarch64_opnd *opnds = opcode->operands;
860
861 if (opnds[0] == AARCH64_OPND_NIL)
862 return FALSE;
863
864 while (opnds[++i] != AARCH64_OPND_NIL)
865 if (opnds[i] == opnds[0])
866 return TRUE;
867
868 return FALSE;
869}
870
a06ea964
NC		 871/* TODO improve this, we can have an extra field at the runtime to
872 store the number of operands rather than calculating it every time. */
873
874int
875aarch64_num_of_operands (const aarch64_opcode *opcode)
876{
877 int i = 0;
878 const enum aarch64_opnd *opnds = opcode->operands;
879 while (opnds[i++] != AARCH64_OPND_NIL)
880 ;
881 --i;
882 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
883 return i;
884}
885
886/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
887 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
888
889 N.B. on the entry, it is very likely that only some operands in *INST
890 have had their qualifiers been established.
891
892 If STOP_AT is not -1, the function will only try to match
893 the qualifier sequence for operands before and including the operand
894 of index STOP_AT; and on success *RET will only be filled with the first
895 (STOP_AT+1) qualifiers.
896
897 A couple examples of the matching algorithm:
898
899 X,W,NIL should match
900 X,W,NIL
901
902 NIL,NIL should match
903 X ,NIL
904
905 Apart from serving the main encoding routine, this can also be called
906 during or after the operand decoding. */
907
908int
909aarch64_find_best_match (const aarch64_inst *inst,
910 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
911 int stop_at, aarch64_opnd_qualifier_t *ret)
912{
913 int found = 0;
914 int i, num_opnds;
915 const aarch64_opnd_qualifier_t *qualifiers;
916
917 num_opnds = aarch64_num_of_operands (inst->opcode);
918 if (num_opnds == 0)
919 {
920 DEBUG_TRACE ("SUCCEED: no operand");
921 return 1;
922 }
923
924 if (stop_at < 0 || stop_at >= num_opnds)
925 stop_at = num_opnds - 1;
926
927 /* For each pattern. */
928 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
929 {
930 int j;
931 qualifiers = *qualifiers_list;
932
933 /* Start as positive. */
934 found = 1;
935
936 DEBUG_TRACE ("%d", i);
937#ifdef DEBUG_AARCH64
938 if (debug_dump)
939 dump_match_qualifiers (inst->operands, qualifiers);
940#endif
941
942 /* Most opcodes has much fewer patterns in the list.
943 First NIL qualifier indicates the end in the list. */
944 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
945 {
946 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
947 if (i)
948 found = 0;
949 break;
950 }
951
952 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
953 {
954 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
955 {
956 /* Either the operand does not have qualifier, or the qualifier
957 for the operand needs to be deduced from the qualifier
958 sequence.
959 In the latter case, any constraint checking related with
960 the obtained qualifier should be done later in
961 operand_general_constraint_met_p. */
962 continue;
963 }
964 else if (*qualifiers != inst->operands[j].qualifier)
965 {
966 /* Unless the target qualifier can also qualify the operand
967 (which has already had a non-nil qualifier), non-equal
968 qualifiers are generally un-matched. */
969 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
970 continue;
971 else
972 {
973 found = 0;
974 break;
975 }
976 }
977 else
978 continue; /* Equal qualifiers are certainly matched. */
979 }
980
981 /* Qualifiers established. */
982 if (found == 1)
983 break;
984 }
985
986 if (found == 1)
987 {
988 /* Fill the result in *RET. */
989 int j;
990 qualifiers = *qualifiers_list;
991
992 DEBUG_TRACE ("complete qualifiers using list %d", i);
993#ifdef DEBUG_AARCH64
994 if (debug_dump)
995 dump_qualifier_sequence (qualifiers);
996#endif
997
998 for (j = 0; j <= stop_at; ++j, ++qualifiers)
999 ret[j] = *qualifiers;
1000 for (; j < AARCH64_MAX_OPND_NUM; ++j)
1001 ret[j] = AARCH64_OPND_QLF_NIL;
1002
1003 DEBUG_TRACE ("SUCCESS");
1004 return 1;
1005 }
1006
1007 DEBUG_TRACE ("FAIL");
1008 return 0;
1009}
1010
1011/* Operand qualifier matching and resolving.
1012
1013 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1014 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1015
1016 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1017 succeeds. */
1018
1019static int
1020match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1021{
4989adac 1022 int i, nops;
a06ea964
NC		 1023 aarch64_opnd_qualifier_seq_t qualifiers;
1024
1025 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1026 qualifiers))
1027 {
1028 DEBUG_TRACE ("matching FAIL");
1029 return 0;
1030 }
1031
4989adac
RS		 1032 if (inst->opcode->flags & F_STRICT)
1033 {
1034 /* Require an exact qualifier match, even for NIL qualifiers. */
1035 nops = aarch64_num_of_operands (inst->opcode);
1036 for (i = 0; i < nops; ++i)
1037 if (inst->operands[i].qualifier != qualifiers[i])
1038 return FALSE;
1039 }
1040
a06ea964
NC		 1041 /* Update the qualifiers. */
1042 if (update_p == TRUE)
1043 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1044 {
1045 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1046 break;
1047 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1048 "update %s with %s for operand %d",
1049 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1050 aarch64_get_qualifier_name (qualifiers[i]), i);
1051 inst->operands[i].qualifier = qualifiers[i];
1052 }
1053
1054 DEBUG_TRACE ("matching SUCCESS");
1055 return 1;
1056}
1057
1058/* Return TRUE if VALUE is a wide constant that can be moved into a general
1059 register by MOVZ.
1060
1061 IS32 indicates whether value is a 32-bit immediate or not.
1062 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1063 amount will be returned in *SHIFT_AMOUNT. */
1064
1065bfd_boolean
1066aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1067{
1068 int amount;
1069
1070 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1071
1072 if (is32)
1073 {
1074 /* Allow all zeros or all ones in top 32-bits, so that
1075 32-bit constant expressions like ~0x80000000 are
1076 permitted. */
1077 uint64_t ext = value;
1078 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1079 /* Immediate out of range. */
1080 return FALSE;
1081 value &= (int64_t) 0xffffffff;
1082 }
1083
1084 /* first, try movz then movn */
1085 amount = -1;
1086 if ((value & ((int64_t) 0xffff << 0)) == value)
1087 amount = 0;
1088 else if ((value & ((int64_t) 0xffff << 16)) == value)
1089 amount = 16;
1090 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1091 amount = 32;
1092 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1093 amount = 48;
1094
1095 if (amount == -1)
1096 {
1097 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1098 return FALSE;
1099 }
1100
1101 if (shift_amount != NULL)
1102 *shift_amount = amount;
1103
1104 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1105
1106 return TRUE;
1107}
1108
1109/* Build the accepted values for immediate logical SIMD instructions.
1110
1111 The standard encodings of the immediate value are:
1112 N imms immr SIMD size R S
1113 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1114 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1115 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1116 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1117 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1118 0 11110s 00000r 2 UInt(r) UInt(s)
1119 where all-ones value of S is reserved.
1120
1121 Let's call E the SIMD size.
1122
1123 The immediate value is: S+1 bits '1' rotated to the right by R.
1124
1125 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1126 (remember S != E - 1). */
1127
1128#define TOTAL_IMM_NB 5334
1129
1130typedef struct
1131{
1132 uint64_t imm;
1133 aarch64_insn encoding;
1134} simd_imm_encoding;
1135
1136static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1137
1138static int
1139simd_imm_encoding_cmp(const void *i1, const void *i2)
1140{
1141 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1142 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1143
1144 if (imm1->imm < imm2->imm)
1145 return -1;
1146 if (imm1->imm > imm2->imm)
1147 return +1;
1148 return 0;
1149}
1150
1151/* immediate bitfield standard encoding
1152 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1153 1 ssssss rrrrrr 64 rrrrrr ssssss
1154 0 0sssss 0rrrrr 32 rrrrr sssss
1155 0 10ssss 00rrrr 16 rrrr ssss
1156 0 110sss 000rrr 8 rrr sss
1157 0 1110ss 0000rr 4 rr ss
1158 0 11110s 00000r 2 r s */
1159static inline int
1160encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1161{
1162 return (is64 << 12) | (r << 6) | s;
1163}
1164
1165static void
1166build_immediate_table (void)
1167{
1168 uint32_t log_e, e, s, r, s_mask;
1169 uint64_t mask, imm;
1170 int nb_imms;
1171 int is64;
1172
1173 nb_imms = 0;
1174 for (log_e = 1; log_e <= 6; log_e++)
1175 {
1176 /* Get element size. */
1177 e = 1u << log_e;
1178 if (log_e == 6)
1179 {
1180 is64 = 1;
1181 mask = 0xffffffffffffffffull;
1182 s_mask = 0;
1183 }
1184 else
1185 {
1186 is64 = 0;
1187 mask = (1ull << e) - 1;
1188 /* log_e s_mask
1189 1 ((1 << 4) - 1) << 2 = 111100
1190 2 ((1 << 3) - 1) << 3 = 111000
1191 3 ((1 << 2) - 1) << 4 = 110000
1192 4 ((1 << 1) - 1) << 5 = 100000
1193 5 ((1 << 0) - 1) << 6 = 000000 */
1194 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1195 }
1196 for (s = 0; s < e - 1; s++)
1197 for (r = 0; r < e; r++)
1198 {
1199 /* s+1 consecutive bits to 1 (s < 63) */
1200 imm = (1ull << (s + 1)) - 1;
1201 /* rotate right by r */
1202 if (r != 0)
1203 imm = (imm >> r) | ((imm << (e - r)) & mask);
1204 /* replicate the constant depending on SIMD size */
1205 switch (log_e)
1206 {
1207 case 1: imm = (imm << 2) | imm;
1a0670f3 1208 /* Fall through. */
a06ea964 1209 case 2: imm = (imm << 4) | imm;
1a0670f3 1210 /* Fall through. */
a06ea964 1211 case 3: imm = (imm << 8) | imm;
1a0670f3 1212 /* Fall through. */
a06ea964 1213 case 4: imm = (imm << 16) | imm;
1a0670f3 1214 /* Fall through. */
a06ea964 1215 case 5: imm = (imm << 32) | imm;
1a0670f3 1216 /* Fall through. */
a06ea964
NC		 1217 case 6: break;
1218 default: abort ();
1219 }
1220 simd_immediates[nb_imms].imm = imm;
1221 simd_immediates[nb_imms].encoding =
1222 encode_immediate_bitfield(is64, s | s_mask, r);
1223 nb_imms++;
1224 }
1225 }
1226 assert (nb_imms == TOTAL_IMM_NB);
1227 qsort(simd_immediates, nb_imms,
1228 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1229}
1230
1231/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1232 be accepted by logical (immediate) instructions
1233 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1234
42408347 1235 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1236 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1237 VALUE will be returned in *ENCODING. */
1238
1239bfd_boolean
42408347 1240aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1241{
1242 simd_imm_encoding imm_enc;
1243 const simd_imm_encoding *imm_encoding;
1244 static bfd_boolean initialized = FALSE;
42408347
RS		 1245 uint64_t upper;
1246 int i;
a06ea964 1247
957f6b39
TC		 1248 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1249 value, esize);
a06ea964 1250
535b785f 1251 if (!initialized)
a06ea964
NC		 1252 {
1253 build_immediate_table ();
1254 initialized = TRUE;
1255 }
1256
42408347
RS		 1257 /* Allow all zeros or all ones in top bits, so that
1258 constant expressions like ~1 are permitted. */
1259 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1260 if ((value & ~upper) != value && (value | upper) != value)
1261 return FALSE;
7e105031 1262
42408347
RS		 1263 /* Replicate to a full 64-bit value. */
1264 value &= ~upper;
1265 for (i = esize * 8; i < 64; i *= 2)
1266 value |= (value << i);
a06ea964
NC		 1267
1268 imm_enc.imm = value;
1269 imm_encoding = (const simd_imm_encoding *)
1270 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1271 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1272 if (imm_encoding == NULL)
1273 {
1274 DEBUG_TRACE ("exit with FALSE");
1275 return FALSE;
1276 }
1277 if (encoding != NULL)
1278 *encoding = imm_encoding->encoding;
1279 DEBUG_TRACE ("exit with TRUE");
1280 return TRUE;
1281}
1282
1283/* If 64-bit immediate IMM is in the format of
1284 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1285 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1286 of value "abcdefgh". Otherwise return -1. */
1287int
1288aarch64_shrink_expanded_imm8 (uint64_t imm)
1289{
1290 int i, ret;
1291 uint32_t byte;
1292
1293 ret = 0;
1294 for (i = 0; i < 8; i++)
1295 {
1296 byte = (imm >> (8 * i)) & 0xff;
1297 if (byte == 0xff)
1298 ret |= 1 << i;
1299 else if (byte != 0x00)
1300 return -1;
1301 }
1302 return ret;
1303}
1304
1305/* Utility inline functions for operand_general_constraint_met_p. */
1306
1307static inline void
1308set_error (aarch64_operand_error *mismatch_detail,
1309 enum aarch64_operand_error_kind kind, int idx,
1310 const char* error)
1311{
1312 if (mismatch_detail == NULL)
1313 return;
1314 mismatch_detail->kind = kind;
1315 mismatch_detail->index = idx;
1316 mismatch_detail->error = error;
1317}
1318
4e50d5f8
YZ		 1319static inline void
1320set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1321 const char* error)
1322{
1323 if (mismatch_detail == NULL)
1324 return;
1325 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1326}
1327
a06ea964
NC		 1328static inline void
1329set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1330 int idx, int lower_bound, int upper_bound,
1331 const char* error)
1332{
1333 if (mismatch_detail == NULL)
1334 return;
1335 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1336 mismatch_detail->data[0] = lower_bound;
1337 mismatch_detail->data[1] = upper_bound;
1338}
1339
1340static inline void
1341set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1342 int idx, int lower_bound, int upper_bound)
1343{
1344 if (mismatch_detail == NULL)
1345 return;
1346 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1347 _("immediate value"));
1348}
1349
1350static inline void
1351set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1352 int idx, int lower_bound, int upper_bound)
1353{
1354 if (mismatch_detail == NULL)
1355 return;
1356 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1357 _("immediate offset"));
1358}
1359
1360static inline void
1361set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1362 int idx, int lower_bound, int upper_bound)
1363{
1364 if (mismatch_detail == NULL)
1365 return;
1366 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1367 _("register number"));
1368}
1369
1370static inline void
1371set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1372 int idx, int lower_bound, int upper_bound)
1373{
1374 if (mismatch_detail == NULL)
1375 return;
1376 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1377 _("register element index"));
1378}
1379
1380static inline void
1381set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1382 int idx, int lower_bound, int upper_bound)
1383{
1384 if (mismatch_detail == NULL)
1385 return;
1386 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1387 _("shift amount"));
1388}
1389
2442d846
RS		 1390/* Report that the MUL modifier in operand IDX should be in the range
1391 [LOWER_BOUND, UPPER_BOUND]. */
1392static inline void
1393set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1394 int idx, int lower_bound, int upper_bound)
1395{
1396 if (mismatch_detail == NULL)
1397 return;
1398 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1399 _("multiplier"));
1400}
1401
a06ea964
NC		 1402static inline void
1403set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1404 int alignment)
1405{
1406 if (mismatch_detail == NULL)
1407 return;
1408 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1409 mismatch_detail->data[0] = alignment;
1410}
1411
1412static inline void
1413set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1414 int expected_num)
1415{
1416 if (mismatch_detail == NULL)
1417 return;
1418 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1419 mismatch_detail->data[0] = expected_num;
1420}
1421
1422static inline void
1423set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1424 const char* error)
1425{
1426 if (mismatch_detail == NULL)
1427 return;
1428 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1429}
1430
1431/* General constraint checking based on operand code.
1432
1433 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1434 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1435
1436 This function has to be called after the qualifiers for all operands
1437 have been resolved.
1438
1439 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1440 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1441 of error message during the disassembling where error message is not
1442 wanted. We avoid the dynamic construction of strings of error messages
1443 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1444 use a combination of error code, static string and some integer data to
1445 represent an error. */
1446
1447static int
1448operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1449 enum aarch64_opnd type,
1450 const aarch64_opcode *opcode,
1451 aarch64_operand_error *mismatch_detail)
1452{
e950b345 1453 unsigned num, modifiers, shift;
a06ea964 1454 unsigned char size;
4df068de 1455 int64_t imm, min_value, max_value;
e950b345 1456 uint64_t uvalue, mask;
a06ea964
NC		 1457 const aarch64_opnd_info *opnd = opnds + idx;
1458 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1459
1460 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1461
1462 switch (aarch64_operands[type].op_class)
1463 {
1464 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1465 /* Check pair reg constraints for cas* instructions. */
1466 if (type == AARCH64_OPND_PAIRREG)
1467 {
1468 assert (idx == 1 || idx == 3);
1469 if (opnds[idx - 1].reg.regno % 2 != 0)
1470 {
1471 set_syntax_error (mismatch_detail, idx - 1,
1472 _("reg pair must start from even reg"));
1473 return 0;
1474 }
1475 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1476 {
1477 set_syntax_error (mismatch_detail, idx,
1478 _("reg pair must be contiguous"));
1479 return 0;
1480 }
1481 break;
1482 }
1483
a06ea964
NC		 1484 /* <Xt> may be optional in some IC and TLBI instructions. */
1485 if (type == AARCH64_OPND_Rt_SYS)
1486 {
1487 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1488 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1489 if (opnds[1].present
1490 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1491 {
1492 set_other_error (mismatch_detail, idx, _("extraneous register"));
1493 return 0;
1494 }
ea2deeec
MW		 1495 if (!opnds[1].present
1496 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1497 {
1498 set_other_error (mismatch_detail, idx, _("missing register"));
1499 return 0;
1500 }
1501 }
1502 switch (qualifier)
1503 {
1504 case AARCH64_OPND_QLF_WSP:
1505 case AARCH64_OPND_QLF_SP:
1506 if (!aarch64_stack_pointer_p (opnd))
1507 {
1508 set_other_error (mismatch_detail, idx,
1509 _("stack pointer register expected"));
1510 return 0;
1511 }
1512 break;
1513 default:
1514 break;
1515 }
1516 break;
1517
f11ad6bc
RS		 1518 case AARCH64_OPND_CLASS_SVE_REG:
1519 switch (type)
1520 {
582e12bf
RS		 1521 case AARCH64_OPND_SVE_Zm3_INDEX:
1522 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1523 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 1524 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf
RS		 1525 case AARCH64_OPND_SVE_Zm4_INDEX:
1526 size = get_operand_fields_width (get_operand_from_code (type));
1527 shift = get_operand_specific_data (&aarch64_operands[type]);
1528 mask = (1 << shift) - 1;
1529 if (opnd->reg.regno > mask)
1530 {
1531 assert (mask == 7 || mask == 15);
1532 set_other_error (mismatch_detail, idx,
1533 mask == 15
1534 ? _("z0-z15 expected")
1535 : _("z0-z7 expected"));
1536 return 0;
1537 }
1538 mask = (1 << (size - shift)) - 1;
1539 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1540 {
1541 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1542 return 0;
1543 }
1544 break;
1545
f11ad6bc
RS		 1546 case AARCH64_OPND_SVE_Zn_INDEX:
1547 size = aarch64_get_qualifier_esize (opnd->qualifier);
1548 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1549 {
1550 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1551 0, 64 / size - 1);
1552 return 0;
1553 }
1554 break;
1555
1556 case AARCH64_OPND_SVE_ZnxN:
1557 case AARCH64_OPND_SVE_ZtxN:
1558 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1559 {
1560 set_other_error (mismatch_detail, idx,
1561 _("invalid register list"));
1562 return 0;
1563 }
1564 break;
1565
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case AARCH64_OPND_CLASS_PRED_REG:
1572 if (opnd->reg.regno >= 8
1573 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1574 {
1575 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1576 return 0;
1577 }
1578 break;
1579
68a64283
YZ		 1580 case AARCH64_OPND_CLASS_COND:
1581 if (type == AARCH64_OPND_COND1
1582 && (opnds[idx].cond->value & 0xe) == 0xe)
1583 {
1584 /* Not allow AL or NV. */
1585 set_syntax_error (mismatch_detail, idx, NULL);
1586 }
1587 break;
1588
a06ea964
NC		 1589 case AARCH64_OPND_CLASS_ADDRESS:
1590 /* Check writeback. */
1591 switch (opcode->iclass)
1592 {
1593 case ldst_pos:
1594 case ldst_unscaled:
1595 case ldstnapair_offs:
1596 case ldstpair_off:
1597 case ldst_unpriv:
1598 if (opnd->addr.writeback == 1)
1599 {
4e50d5f8
YZ		 1600 set_syntax_error (mismatch_detail, idx,
1601 _("unexpected address writeback"));
a06ea964
NC		 1602 return 0;
1603 }
1604 break;
3f06e550
SN		 1605 case ldst_imm10:
1606 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1607 {
1608 set_syntax_error (mismatch_detail, idx,
1609 _("unexpected address writeback"));
1610 return 0;
1611 }
1612 break;
a06ea964
NC		 1613 case ldst_imm9:
1614 case ldstpair_indexed:
1615 case asisdlsep:
1616 case asisdlsop:
1617 if (opnd->addr.writeback == 0)
1618 {
4e50d5f8
YZ		 1619 set_syntax_error (mismatch_detail, idx,
1620 _("address writeback expected"));
a06ea964
NC		 1621 return 0;
1622 }
1623 break;
1624 default:
1625 assert (opnd->addr.writeback == 0);
1626 break;
1627 }
1628 switch (type)
1629 {
1630 case AARCH64_OPND_ADDR_SIMM7:
1631 /* Scaled signed 7 bits immediate offset. */
1632 /* Get the size of the data element that is accessed, which may be
1633 different from that of the source register size,
1634 e.g. in strb/ldrb. */
1635 size = aarch64_get_qualifier_esize (opnd->qualifier);
1636 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1637 {
1638 set_offset_out_of_range_error (mismatch_detail, idx,
1639 -64 * size, 63 * size);
1640 return 0;
1641 }
1642 if (!value_aligned_p (opnd->addr.offset.imm, size))
1643 {
1644 set_unaligned_error (mismatch_detail, idx, size);
1645 return 0;
1646 }
1647 break;
f42f1a1d 1648 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1649 case AARCH64_OPND_ADDR_SIMM9:
1650 /* Unscaled signed 9 bits immediate offset. */
1651 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1652 {
1653 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1654 return 0;
1655 }
1656 break;
1657
1658 case AARCH64_OPND_ADDR_SIMM9_2:
1659 /* Unscaled signed 9 bits immediate offset, which has to be negative
1660 or unaligned. */
1661 size = aarch64_get_qualifier_esize (qualifier);
1662 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1663 && !value_aligned_p (opnd->addr.offset.imm, size))
1664 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1665 return 1;
1666 set_other_error (mismatch_detail, idx,
1667 _("negative or unaligned offset expected"));
1668 return 0;
1669
3f06e550
SN		 1670 case AARCH64_OPND_ADDR_SIMM10:
1671 /* Scaled signed 10 bits immediate offset. */
1672 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1673 {
1674 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1675 return 0;
1676 }
1677 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1678 {
1679 set_unaligned_error (mismatch_detail, idx, 8);
1680 return 0;
1681 }
1682 break;
1683
fb3265b3
SD		 1684 case AARCH64_OPND_ADDR_SIMM11:
1685 /* Signed 11 bits immediate offset (multiple of 16). */
1686 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1687 {
1688 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1689 return 0;
1690 }
1691
1692 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1693 {
1694 set_unaligned_error (mismatch_detail, idx, 16);
1695 return 0;
1696 }
1697 break;
1698
1699 case AARCH64_OPND_ADDR_SIMM13:
1700 /* Signed 13 bits immediate offset (multiple of 16). */
1701 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1702 {
1703 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1704 return 0;
1705 }
1706
1707 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1708 {
1709 set_unaligned_error (mismatch_detail, idx, 16);
1710 return 0;
1711 }
1712 break;
1713
a06ea964
NC		 1714 case AARCH64_OPND_SIMD_ADDR_POST:
1715 /* AdvSIMD load/store multiple structures, post-index. */
1716 assert (idx == 1);
1717 if (opnd->addr.offset.is_reg)
1718 {
1719 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1720 return 1;
1721 else
1722 {
1723 set_other_error (mismatch_detail, idx,
1724 _("invalid register offset"));
1725 return 0;
1726 }
1727 }
1728 else
1729 {
1730 const aarch64_opnd_info *prev = &opnds[idx-1];
1731 unsigned num_bytes; /* total number of bytes transferred. */
1732 /* The opcode dependent area stores the number of elements in
1733 each structure to be loaded/stored. */
1734 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1735 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1736 /* Special handling of loading single structure to all lane. */
1737 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1738 * aarch64_get_qualifier_esize (prev->qualifier);
1739 else
1740 num_bytes = prev->reglist.num_regs
1741 * aarch64_get_qualifier_esize (prev->qualifier)
1742 * aarch64_get_qualifier_nelem (prev->qualifier);
1743 if ((int) num_bytes != opnd->addr.offset.imm)
1744 {
1745 set_other_error (mismatch_detail, idx,
1746 _("invalid post-increment amount"));
1747 return 0;
1748 }
1749 }
1750 break;
1751
1752 case AARCH64_OPND_ADDR_REGOFF:
1753 /* Get the size of the data element that is accessed, which may be
1754 different from that of the source register size,
1755 e.g. in strb/ldrb. */
1756 size = aarch64_get_qualifier_esize (opnd->qualifier);
1757 /* It is either no shift or shift by the binary logarithm of SIZE. */
1758 if (opnd->shifter.amount != 0
1759 && opnd->shifter.amount != (int)get_logsz (size))
1760 {
1761 set_other_error (mismatch_detail, idx,
1762 _("invalid shift amount"));
1763 return 0;
1764 }
1765 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1766 operators. */
1767 switch (opnd->shifter.kind)
1768 {
1769 case AARCH64_MOD_UXTW:
1770 case AARCH64_MOD_LSL:
1771 case AARCH64_MOD_SXTW:
1772 case AARCH64_MOD_SXTX: break;
1773 default:
1774 set_other_error (mismatch_detail, idx,
1775 _("invalid extend/shift operator"));
1776 return 0;
1777 }
1778 break;
1779
1780 case AARCH64_OPND_ADDR_UIMM12:
1781 imm = opnd->addr.offset.imm;
1782 /* Get the size of the data element that is accessed, which may be
1783 different from that of the source register size,
1784 e.g. in strb/ldrb. */
1785 size = aarch64_get_qualifier_esize (qualifier);
1786 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1787 {
1788 set_offset_out_of_range_error (mismatch_detail, idx,
1789 0, 4095 * size);
1790 return 0;
1791 }
9de794e1 1792 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1793 {
1794 set_unaligned_error (mismatch_detail, idx, size);
1795 return 0;
1796 }
1797 break;
1798
1799 case AARCH64_OPND_ADDR_PCREL14:
1800 case AARCH64_OPND_ADDR_PCREL19:
1801 case AARCH64_OPND_ADDR_PCREL21:
1802 case AARCH64_OPND_ADDR_PCREL26:
1803 imm = opnd->imm.value;
1804 if (operand_need_shift_by_two (get_operand_from_code (type)))
1805 {
1806 /* The offset value in a PC-relative branch instruction is alway
1807 4-byte aligned and is encoded without the lowest 2 bits. */
1808 if (!value_aligned_p (imm, 4))
1809 {
1810 set_unaligned_error (mismatch_detail, idx, 4);
1811 return 0;
1812 }
1813 /* Right shift by 2 so that we can carry out the following check
1814 canonically. */
1815 imm >>= 2;
1816 }
1817 size = get_operand_fields_width (get_operand_from_code (type));
1818 if (!value_fit_signed_field_p (imm, size))
1819 {
1820 set_other_error (mismatch_detail, idx,
1821 _("immediate out of range"));
1822 return 0;
1823 }
1824 break;
1825
98907a70
RS		 1826 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1827 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1828 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1829 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1830 min_value = -8;
1831 max_value = 7;
1832 sve_imm_offset_vl:
1833 assert (!opnd->addr.offset.is_reg);
1834 assert (opnd->addr.preind);
1835 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1836 min_value *= num;
1837 max_value *= num;
1838 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1839 || (opnd->shifter.operator_present
1840 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1841 {
1842 set_other_error (mismatch_detail, idx,
1843 _("invalid addressing mode"));
1844 return 0;
1845 }
1846 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1847 {
1848 set_offset_out_of_range_error (mismatch_detail, idx,
1849 min_value, max_value);
1850 return 0;
1851 }
1852 if (!value_aligned_p (opnd->addr.offset.imm, num))
1853 {
1854 set_unaligned_error (mismatch_detail, idx, num);
1855 return 0;
1856 }
1857 break;
1858
1859 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1860 min_value = -32;
1861 max_value = 31;
1862 goto sve_imm_offset_vl;
1863
1864 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1865 min_value = -256;
1866 max_value = 255;
1867 goto sve_imm_offset_vl;
1868
4df068de
RS		 1869 case AARCH64_OPND_SVE_ADDR_RI_U6:
1870 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1871 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1872 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1873 min_value = 0;
1874 max_value = 63;
1875 sve_imm_offset:
1876 assert (!opnd->addr.offset.is_reg);
1877 assert (opnd->addr.preind);
1878 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1879 min_value *= num;
1880 max_value *= num;
1881 if (opnd->shifter.operator_present
1882 || opnd->shifter.amount_present)
1883 {
1884 set_other_error (mismatch_detail, idx,
1885 _("invalid addressing mode"));
1886 return 0;
1887 }
1888 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1889 {
1890 set_offset_out_of_range_error (mismatch_detail, idx,
1891 min_value, max_value);
1892 return 0;
1893 }
1894 if (!value_aligned_p (opnd->addr.offset.imm, num))
1895 {
1896 set_unaligned_error (mismatch_detail, idx, num);
1897 return 0;
1898 }
1899 break;
1900
582e12bf
RS		 1901 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1902 min_value = -8;
1903 max_value = 7;
1904 goto sve_imm_offset;
1905
c469c864
MM		 1906 case AARCH64_OPND_SVE_ADDR_ZX:
1907 /* Everything is already ensured by parse_operands or
1908 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1909 argument type). */
1910 assert (opnd->addr.offset.is_reg);
1911 assert (opnd->addr.preind);
1912 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1913 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1914 assert (opnd->shifter.operator_present == 0);
1915 break;
1916
c8d59609 1917 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1918 case AARCH64_OPND_SVE_ADDR_RR:
1919 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1920 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1921 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1922 case AARCH64_OPND_SVE_ADDR_RX:
1923 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1924 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1925 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1926 case AARCH64_OPND_SVE_ADDR_RZ:
1927 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1928 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1929 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1930 modifiers = 1 << AARCH64_MOD_LSL;
1931 sve_rr_operand:
1932 assert (opnd->addr.offset.is_reg);
1933 assert (opnd->addr.preind);
1934 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1935 && opnd->addr.offset.regno == 31)
1936 {
1937 set_other_error (mismatch_detail, idx,
1938 _("index register xzr is not allowed"));
1939 return 0;
1940 }
1941 if (((1 << opnd->shifter.kind) & modifiers) == 0
1942 || (opnd->shifter.amount
1943 != get_operand_specific_data (&aarch64_operands[type])))
1944 {
1945 set_other_error (mismatch_detail, idx,
1946 _("invalid addressing mode"));
1947 return 0;
1948 }
1949 break;
1950
1951 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1955 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1956 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1957 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1958 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1959 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1960 goto sve_rr_operand;
1961
1962 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1963 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1964 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1965 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1966 min_value = 0;
1967 max_value = 31;
1968 goto sve_imm_offset;
1969
1970 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1971 modifiers = 1 << AARCH64_MOD_LSL;
1972 sve_zz_operand:
1973 assert (opnd->addr.offset.is_reg);
1974 assert (opnd->addr.preind);
1975 if (((1 << opnd->shifter.kind) & modifiers) == 0
1976 || opnd->shifter.amount < 0
1977 || opnd->shifter.amount > 3)
1978 {
1979 set_other_error (mismatch_detail, idx,
1980 _("invalid addressing mode"));
1981 return 0;
1982 }
1983 break;
1984
1985 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1986 modifiers = (1 << AARCH64_MOD_SXTW);
1987 goto sve_zz_operand;
1988
1989 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1990 modifiers = 1 << AARCH64_MOD_UXTW;
1991 goto sve_zz_operand;
1992
a06ea964
NC		 1993 default:
1994 break;
1995 }
1996 break;
1997
1998 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 1999 if (type == AARCH64_OPND_LEt)
2000 {
2001 /* Get the upper bound for the element index. */
2002 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
2003 if (!value_in_range_p (opnd->reglist.index, 0, num))
2004 {
2005 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2006 return 0;
2007 }
2008 }
a06ea964
NC		 2009 /* The opcode dependent area stores the number of elements in
2010 each structure to be loaded/stored. */
2011 num = get_opcode_dependent_value (opcode);
2012 switch (type)
2013 {
2014 case AARCH64_OPND_LVt:
2015 assert (num >= 1 && num <= 4);
2016 /* Unless LD1/ST1, the number of registers should be equal to that
2017 of the structure elements. */
2018 if (num != 1 && opnd->reglist.num_regs != num)
2019 {
2020 set_reg_list_error (mismatch_detail, idx, num);
2021 return 0;
2022 }
2023 break;
2024 case AARCH64_OPND_LVt_AL:
2025 case AARCH64_OPND_LEt:
2026 assert (num >= 1 && num <= 4);
2027 /* The number of registers should be equal to that of the structure
2028 elements. */
2029 if (opnd->reglist.num_regs != num)
2030 {
2031 set_reg_list_error (mismatch_detail, idx, num);
2032 return 0;
2033 }
2034 break;
2035 default:
2036 break;
2037 }
2038 break;
2039
2040 case AARCH64_OPND_CLASS_IMMEDIATE:
2041 /* Constraint check on immediate operand. */
2042 imm = opnd->imm.value;
2043 /* E.g. imm_0_31 constrains value to be 0..31. */
2044 if (qualifier_value_in_range_constraint_p (qualifier)
2045 && !value_in_range_p (imm, get_lower_bound (qualifier),
2046 get_upper_bound (qualifier)))
2047 {
2048 set_imm_out_of_range_error (mismatch_detail, idx,
2049 get_lower_bound (qualifier),
2050 get_upper_bound (qualifier));
2051 return 0;
2052 }
2053
2054 switch (type)
2055 {
2056 case AARCH64_OPND_AIMM:
2057 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2058 {
2059 set_other_error (mismatch_detail, idx,
2060 _("invalid shift operator"));
2061 return 0;
2062 }
2063 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2064 {
2065 set_other_error (mismatch_detail, idx,
ab3b8fcf 2066 _("shift amount must be 0 or 12"));
a06ea964
NC		 2067 return 0;
2068 }
2069 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2070 {
2071 set_other_error (mismatch_detail, idx,
2072 _("immediate out of range"));
2073 return 0;
2074 }
2075 break;
2076
2077 case AARCH64_OPND_HALF:
2078 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2079 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2080 {
2081 set_other_error (mismatch_detail, idx,
2082 _("invalid shift operator"));
2083 return 0;
2084 }
2085 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2086 if (!value_aligned_p (opnd->shifter.amount, 16))
2087 {
2088 set_other_error (mismatch_detail, idx,
ab3b8fcf 2089 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2090 return 0;
2091 }
2092 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2093 {
2094 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2095 0, size * 8 - 16);
2096 return 0;
2097 }
2098 if (opnd->imm.value < 0)
2099 {
2100 set_other_error (mismatch_detail, idx,
2101 _("negative immediate value not allowed"));
2102 return 0;
2103 }
2104 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2105 {
2106 set_other_error (mismatch_detail, idx,
2107 _("immediate out of range"));
2108 return 0;
2109 }
2110 break;
2111
2112 case AARCH64_OPND_IMM_MOV:
2113 {
42408347 2114 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2115 imm = opnd->imm.value;
2116 assert (idx == 1);
2117 switch (opcode->op)
2118 {
2119 case OP_MOV_IMM_WIDEN:
2120 imm = ~imm;
1a0670f3 2121 /* Fall through. */
a06ea964 2122 case OP_MOV_IMM_WIDE:
42408347 2123 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2124 {
2125 set_other_error (mismatch_detail, idx,
2126 _("immediate out of range"));
2127 return 0;
2128 }
2129 break;
2130 case OP_MOV_IMM_LOG:
42408347 2131 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2132 {
2133 set_other_error (mismatch_detail, idx,
2134 _("immediate out of range"));
2135 return 0;
2136 }
2137 break;
2138 default:
2139 assert (0);
2140 return 0;
2141 }
2142 }
2143 break;
2144
2145 case AARCH64_OPND_NZCV:
2146 case AARCH64_OPND_CCMP_IMM:
2147 case AARCH64_OPND_EXCEPTION:
b83b4b13 2148 case AARCH64_OPND_TME_UIMM16:
a06ea964 2149 case AARCH64_OPND_UIMM4:
193614f2 2150 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2151 case AARCH64_OPND_UIMM7:
2152 case AARCH64_OPND_UIMM3_OP1:
2153 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2154 case AARCH64_OPND_SVE_UIMM3:
2155 case AARCH64_OPND_SVE_UIMM7:
2156 case AARCH64_OPND_SVE_UIMM8:
2157 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2158 size = get_operand_fields_width (get_operand_from_code (type));
2159 assert (size < 32);
2160 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2161 {
2162 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2163 (1 << size) - 1);
2164 return 0;
2165 }
2166 break;
2167
193614f2
SD		 2168 case AARCH64_OPND_UIMM10:
2169 /* Scaled unsigned 10 bits immediate offset. */
2170 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2171 {
2172 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2173 return 0;
2174 }
2175
2176 if (!value_aligned_p (opnd->imm.value, 16))
2177 {
2178 set_unaligned_error (mismatch_detail, idx, 16);
2179 return 0;
2180 }
2181 break;
2182
e950b345
RS		 2183 case AARCH64_OPND_SIMM5:
2184 case AARCH64_OPND_SVE_SIMM5:
2185 case AARCH64_OPND_SVE_SIMM5B:
2186 case AARCH64_OPND_SVE_SIMM6:
2187 case AARCH64_OPND_SVE_SIMM8:
2188 size = get_operand_fields_width (get_operand_from_code (type));
2189 assert (size < 32);
2190 if (!value_fit_signed_field_p (opnd->imm.value, size))
2191 {
2192 set_imm_out_of_range_error (mismatch_detail, idx,
2193 -(1 << (size - 1)),
2194 (1 << (size - 1)) - 1);
2195 return 0;
2196 }
2197 break;
2198
a06ea964 2199 case AARCH64_OPND_WIDTH:
d685192a 2200 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2201 && opnds[0].type == AARCH64_OPND_Rd);
2202 size = get_upper_bound (qualifier);
2203 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2204 /* lsb+width <= reg.size */
2205 {
2206 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2207 size - opnds[idx-1].imm.value);
2208 return 0;
2209 }
2210 break;
2211
2212 case AARCH64_OPND_LIMM:
e950b345 2213 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2214 {
2215 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2216 uint64_t uimm = opnd->imm.value;
2217 if (opcode->op == OP_BIC)
2218 uimm = ~uimm;
535b785f 2219 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2220 {
2221 set_other_error (mismatch_detail, idx,
2222 _("immediate out of range"));
2223 return 0;
2224 }
2225 }
a06ea964
NC		 2226 break;
2227
2228 case AARCH64_OPND_IMM0:
2229 case AARCH64_OPND_FPIMM0:
2230 if (opnd->imm.value != 0)
2231 {
2232 set_other_error (mismatch_detail, idx,
2233 _("immediate zero expected"));
2234 return 0;
2235 }
2236 break;
2237
c2c4ff8d
SN		 2238 case AARCH64_OPND_IMM_ROT1:
2239 case AARCH64_OPND_IMM_ROT2:
582e12bf 2240 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2241 if (opnd->imm.value != 0
2242 && opnd->imm.value != 90
2243 && opnd->imm.value != 180
2244 && opnd->imm.value != 270)
2245 {
2246 set_other_error (mismatch_detail, idx,
2247 _("rotate expected to be 0, 90, 180 or 270"));
2248 return 0;
2249 }
2250 break;
2251
2252 case AARCH64_OPND_IMM_ROT3:
582e12bf 2253 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2254 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2255 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2256 {
2257 set_other_error (mismatch_detail, idx,
2258 _("rotate expected to be 90 or 270"));
2259 return 0;
2260 }
2261 break;
2262
a06ea964
NC		 2263 case AARCH64_OPND_SHLL_IMM:
2264 assert (idx == 2);
2265 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2266 if (opnd->imm.value != size)
2267 {
2268 set_other_error (mismatch_detail, idx,
2269 _("invalid shift amount"));
2270 return 0;
2271 }
2272 break;
2273
2274 case AARCH64_OPND_IMM_VLSL:
2275 size = aarch64_get_qualifier_esize (qualifier);
2276 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2277 {
2278 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2279 size * 8 - 1);
2280 return 0;
2281 }
2282 break;
2283
2284 case AARCH64_OPND_IMM_VLSR:
2285 size = aarch64_get_qualifier_esize (qualifier);
2286 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2287 {
2288 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2289 return 0;
2290 }
2291 break;
2292
2293 case AARCH64_OPND_SIMD_IMM:
2294 case AARCH64_OPND_SIMD_IMM_SFT:
2295 /* Qualifier check. */
2296 switch (qualifier)
2297 {
2298 case AARCH64_OPND_QLF_LSL:
2299 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2300 {
2301 set_other_error (mismatch_detail, idx,
2302 _("invalid shift operator"));
2303 return 0;
2304 }
2305 break;
2306 case AARCH64_OPND_QLF_MSL:
2307 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2308 {
2309 set_other_error (mismatch_detail, idx,
2310 _("invalid shift operator"));
2311 return 0;
2312 }
2313 break;
2314 case AARCH64_OPND_QLF_NIL:
2315 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2316 {
2317 set_other_error (mismatch_detail, idx,
2318 _("shift is not permitted"));
2319 return 0;
2320 }
2321 break;
2322 default:
2323 assert (0);
2324 return 0;
2325 }
2326 /* Is the immediate valid? */
2327 assert (idx == 1);
2328 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2329 {
d2865ed3
YZ		 2330 /* uimm8 or simm8 */
2331 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2332 {
d2865ed3 2333 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2334 return 0;
2335 }
2336 }
2337 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2338 {
2339 /* uimm64 is not
2340 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2341 ffffffffgggggggghhhhhhhh'. */
2342 set_other_error (mismatch_detail, idx,
2343 _("invalid value for immediate"));
2344 return 0;
2345 }
2346 /* Is the shift amount valid? */
2347 switch (opnd->shifter.kind)
2348 {
2349 case AARCH64_MOD_LSL:
2350 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2351 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2352 {
f5555712
YZ		 2353 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2354 (size - 1) * 8);
a06ea964
NC		 2355 return 0;
2356 }
f5555712 2357 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2358 {
f5555712 2359 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2360 return 0;
2361 }
2362 break;
2363 case AARCH64_MOD_MSL:
2364 /* Only 8 and 16 are valid shift amount. */
2365 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2366 {
2367 set_other_error (mismatch_detail, idx,
ab3b8fcf 2368 _("shift amount must be 0 or 16"));
a06ea964
NC		 2369 return 0;
2370 }
2371 break;
2372 default:
2373 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2374 {
2375 set_other_error (mismatch_detail, idx,
2376 _("invalid shift operator"));
2377 return 0;
2378 }
2379 break;
2380 }
2381 break;
2382
2383 case AARCH64_OPND_FPIMM:
2384 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2385 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2386 if (opnd->imm.is_fp == 0)
2387 {
2388 set_other_error (mismatch_detail, idx,
2389 _("floating-point immediate expected"));
2390 return 0;
2391 }
2392 /* The value is expected to be an 8-bit floating-point constant with
2393 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2394 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2395 instruction). */
2396 if (!value_in_range_p (opnd->imm.value, 0, 255))
2397 {
2398 set_other_error (mismatch_detail, idx,
2399 _("immediate out of range"));
2400 return 0;
2401 }
2402 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2403 {
2404 set_other_error (mismatch_detail, idx,
2405 _("invalid shift operator"));
2406 return 0;
2407 }
2408 break;
2409
e950b345
RS		 2410 case AARCH64_OPND_SVE_AIMM:
2411 min_value = 0;
2412 sve_aimm:
2413 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2414 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2415 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2416 uvalue = opnd->imm.value;
2417 shift = opnd->shifter.amount;
2418 if (size == 1)
2419 {
2420 if (shift != 0)
2421 {
2422 set_other_error (mismatch_detail, idx,
2423 _("no shift amount allowed for"
2424 " 8-bit constants"));
2425 return 0;
2426 }
2427 }
2428 else
2429 {
2430 if (shift != 0 && shift != 8)
2431 {
2432 set_other_error (mismatch_detail, idx,
2433 _("shift amount must be 0 or 8"));
2434 return 0;
2435 }
2436 if (shift == 0 && (uvalue & 0xff) == 0)
2437 {
2438 shift = 8;
2439 uvalue = (int64_t) uvalue / 256;
2440 }
2441 }
2442 mask >>= shift;
2443 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2444 {
2445 set_other_error (mismatch_detail, idx,
2446 _("immediate too big for element size"));
2447 return 0;
2448 }
2449 uvalue = (uvalue - min_value) & mask;
2450 if (uvalue > 0xff)
2451 {
2452 set_other_error (mismatch_detail, idx,
2453 _("invalid arithmetic immediate"));
2454 return 0;
2455 }
2456 break;
2457
2458 case AARCH64_OPND_SVE_ASIMM:
2459 min_value = -128;
2460 goto sve_aimm;
2461
165d4950
RS		 2462 case AARCH64_OPND_SVE_I1_HALF_ONE:
2463 assert (opnd->imm.is_fp);
2464 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2465 {
2466 set_other_error (mismatch_detail, idx,
2467 _("floating-point value must be 0.5 or 1.0"));
2468 return 0;
2469 }
2470 break;
2471
2472 case AARCH64_OPND_SVE_I1_HALF_TWO:
2473 assert (opnd->imm.is_fp);
2474 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2475 {
2476 set_other_error (mismatch_detail, idx,
2477 _("floating-point value must be 0.5 or 2.0"));
2478 return 0;
2479 }
2480 break;
2481
2482 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2483 assert (opnd->imm.is_fp);
2484 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2485 {
2486 set_other_error (mismatch_detail, idx,
2487 _("floating-point value must be 0.0 or 1.0"));
2488 return 0;
2489 }
2490 break;
2491
e950b345
RS		 2492 case AARCH64_OPND_SVE_INV_LIMM:
2493 {
2494 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2495 uint64_t uimm = ~opnd->imm.value;
2496 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2497 {
2498 set_other_error (mismatch_detail, idx,
2499 _("immediate out of range"));
2500 return 0;
2501 }
2502 }
2503 break;
2504
2505 case AARCH64_OPND_SVE_LIMM_MOV:
2506 {
2507 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2508 uint64_t uimm = opnd->imm.value;
2509 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2510 {
2511 set_other_error (mismatch_detail, idx,
2512 _("immediate out of range"));
2513 return 0;
2514 }
2515 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2516 {
2517 set_other_error (mismatch_detail, idx,
2518 _("invalid replicated MOV immediate"));
2519 return 0;
2520 }
2521 }
2522 break;
2523
2442d846
RS		 2524 case AARCH64_OPND_SVE_PATTERN_SCALED:
2525 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2526 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2527 {
2528 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2529 return 0;
2530 }
2531 break;
2532
e950b345
RS		 2533 case AARCH64_OPND_SVE_SHLIMM_PRED:
2534 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 2535 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 2536 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2537 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2538 {
2539 set_imm_out_of_range_error (mismatch_detail, idx,
2540 0, 8 * size - 1);
2541 return 0;
2542 }
2543 break;
2544
2545 case AARCH64_OPND_SVE_SHRIMM_PRED:
2546 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 2547 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345 2548 {
3c17238b
MM		 2549 unsigned int index =
2550 (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
2551 size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier);
2552 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2553 {
2554 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
2555 return 0;
2556 }
2557 break;
2558 }
e950b345 2559
a06ea964
NC		 2560 default:
2561 break;
2562 }
2563 break;
2564
a06ea964
NC		 2565 case AARCH64_OPND_CLASS_SYSTEM:
2566 switch (type)
2567 {
2568 case AARCH64_OPND_PSTATEFIELD:
2569 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2570 /* MSR UAO, #uimm4
2571 MSR PAN, #uimm4
104fefee 2572 MSR SSBS,#uimm4
c2825638 2573 The immediate must be #0 or #1. */
0bff6e2d 2574 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2575 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2576 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2577 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2578 && opnds[1].imm.value > 1)
2579 {
2580 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2581 return 0;
2582 }
a06ea964
NC		 2583 /* MSR SPSel, #uimm4
2584 Uses uimm4 as a control value to select the stack pointer: if
2585 bit 0 is set it selects the current exception level's stack
2586 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2587 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2588 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2589 {
2590 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2591 return 0;
2592 }
2593 break;
2594 default:
2595 break;
2596 }
2597 break;
2598
2599 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2600 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2601 if (opcode->op == OP_FCMLA_ELEM)
2602 /* FCMLA index range depends on the vector size of other operands
2603 and is halfed because complex numbers take two elements. */
2604 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2605 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2606 else
2607 num = 16;
2608 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2609 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2610
a06ea964
NC		 2611 /* Index out-of-range. */
2612 if (!value_in_range_p (opnd->reglane.index, 0, num))
2613 {
2614 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2615 return 0;
2616 }
2617 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2618 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2619 number is encoded in "size:M:Rm":
2620 size <Vm>
2621 00 RESERVED
2622 01 0:Rm
2623 10 M:Rm
2624 11 RESERVED */
369c9167 2625 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2626 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2627 {
2628 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2629 return 0;
2630 }
2631 break;
2632
2633 case AARCH64_OPND_CLASS_MODIFIED_REG:
2634 assert (idx == 1 || idx == 2);
2635 switch (type)
2636 {
2637 case AARCH64_OPND_Rm_EXT:
535b785f 2638 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2639 && opnd->shifter.kind != AARCH64_MOD_LSL)
2640 {
2641 set_other_error (mismatch_detail, idx,
2642 _("extend operator expected"));
2643 return 0;
2644 }
2645 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2646 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2647 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2648 case. */
2649 if (!aarch64_stack_pointer_p (opnds + 0)
2650 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2651 {
2652 if (!opnd->shifter.operator_present)
2653 {
2654 set_other_error (mismatch_detail, idx,
2655 _("missing extend operator"));
2656 return 0;
2657 }
2658 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2659 {
2660 set_other_error (mismatch_detail, idx,
2661 _("'LSL' operator not allowed"));
2662 return 0;
2663 }
2664 }
2665 assert (opnd->shifter.operator_present /* Default to LSL. */
2666 || opnd->shifter.kind == AARCH64_MOD_LSL);
2667 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2668 {
2669 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2670 return 0;
2671 }
2672 /* In the 64-bit form, the final register operand is written as Wm
2673 for all but the (possibly omitted) UXTX/LSL and SXTX
2674 operators.
2675 N.B. GAS allows X register to be used with any operator as a
2676 programming convenience. */
2677 if (qualifier == AARCH64_OPND_QLF_X
2678 && opnd->shifter.kind != AARCH64_MOD_LSL
2679 && opnd->shifter.kind != AARCH64_MOD_UXTX
2680 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2681 {
2682 set_other_error (mismatch_detail, idx, _("W register expected"));
2683 return 0;
2684 }
2685 break;
2686
2687 case AARCH64_OPND_Rm_SFT:
2688 /* ROR is not available to the shifted register operand in
2689 arithmetic instructions. */
535b785f 2690 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2691 {
2692 set_other_error (mismatch_detail, idx,
2693 _("shift operator expected"));
2694 return 0;
2695 }
2696 if (opnd->shifter.kind == AARCH64_MOD_ROR
2697 && opcode->iclass != log_shift)
2698 {
2699 set_other_error (mismatch_detail, idx,
2700 _("'ROR' operator not allowed"));
2701 return 0;
2702 }
2703 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2704 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2705 {
2706 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2707 return 0;
2708 }
2709 break;
2710
2711 default:
2712 break;
2713 }
2714 break;
2715
2716 default:
2717 break;
2718 }
2719
2720 return 1;
2721}
2722
2723/* Main entrypoint for the operand constraint checking.
2724
2725 Return 1 if operands of *INST meet the constraint applied by the operand
2726 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2727 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2728 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2729 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2730 error kind when it is notified that an instruction does not pass the check).
2731
2732 Un-determined operand qualifiers may get established during the process. */
2733
2734int
2735aarch64_match_operands_constraint (aarch64_inst *inst,
2736 aarch64_operand_error *mismatch_detail)
2737{
2738 int i;
2739
2740 DEBUG_TRACE ("enter");
2741
0c608d6b
RS		 2742 /* Check for cases where a source register needs to be the same as the
2743 destination register. Do this before matching qualifiers since if
2744 an instruction has both invalid tying and invalid qualifiers,
2745 the error about qualifiers would suggest several alternative
2746 instructions that also have invalid tying. */
2747 i = inst->opcode->tied_operand;
2748 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2749 {
2750 if (mismatch_detail)
2751 {
2752 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2753 mismatch_detail->index = i;
2754 mismatch_detail->error = NULL;
2755 }
2756 return 0;
2757 }
2758
a06ea964
NC		 2759 /* Match operands' qualifier.
2760 *INST has already had qualifier establish for some, if not all, of
2761 its operands; we need to find out whether these established
2762 qualifiers match one of the qualifier sequence in
2763 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2764 with the corresponding qualifier in such a sequence.
2765 Only basic operand constraint checking is done here; the more thorough
2766 constraint checking will carried out by operand_general_constraint_met_p,
2767 which has be to called after this in order to get all of the operands'
2768 qualifiers established. */
2769 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2770 {
2771 DEBUG_TRACE ("FAIL on operand qualifier matching");
2772 if (mismatch_detail)
2773 {
2774 /* Return an error type to indicate that it is the qualifier
2775 matching failure; we don't care about which operand as there
2776 are enough information in the opcode table to reproduce it. */
2777 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2778 mismatch_detail->index = -1;
2779 mismatch_detail->error = NULL;
2780 }
2781 return 0;
2782 }
2783
2784 /* Match operands' constraint. */
2785 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2786 {
2787 enum aarch64_opnd type = inst->opcode->operands[i];
2788 if (type == AARCH64_OPND_NIL)
2789 break;
2790 if (inst->operands[i].skip)
2791 {
2792 DEBUG_TRACE ("skip the incomplete operand %d", i);
2793 continue;
2794 }
2795 if (operand_general_constraint_met_p (inst->operands, i, type,
2796 inst->opcode, mismatch_detail) == 0)
2797 {
2798 DEBUG_TRACE ("FAIL on operand %d", i);
2799 return 0;
2800 }
2801 }
2802
2803 DEBUG_TRACE ("PASS");
2804
2805 return 1;
2806}
2807
2808/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2809 Also updates the TYPE of each INST->OPERANDS with the corresponding
2810 value of OPCODE->OPERANDS.
2811
2812 Note that some operand qualifiers may need to be manually cleared by
2813 the caller before it further calls the aarch64_opcode_encode; by
2814 doing this, it helps the qualifier matching facilities work
2815 properly. */
2816
2817const aarch64_opcode*
2818aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2819{
2820 int i;
2821 const aarch64_opcode *old = inst->opcode;
2822
2823 inst->opcode = opcode;
2824
2825 /* Update the operand types. */
2826 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2827 {
2828 inst->operands[i].type = opcode->operands[i];
2829 if (opcode->operands[i] == AARCH64_OPND_NIL)
2830 break;
2831 }
2832
2833 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2834
2835 return old;
2836}
2837
2838int
2839aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2840{
2841 int i;
2842 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2843 if (operands[i] == operand)
2844 return i;
2845 else if (operands[i] == AARCH64_OPND_NIL)
2846 break;
2847 return -1;
2848}
2849\f
72e9f319
RS		 2850/* R0...R30, followed by FOR31. */
2851#define BANK(R, FOR31) \
2852 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2853 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2854 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2855 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2856/* [0][0] 32-bit integer regs with sp Wn
2857 [0][1] 64-bit integer regs with sp Xn sf=1
2858 [1][0] 32-bit integer regs with #0 Wn
2859 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2860static const char *int_reg[2][2][32] = {
72e9f319
RS		 2861#define R32(X) "w" #X
2862#define R64(X) "x" #X
2863 { BANK (R32, "wsp"), BANK (R64, "sp") },
2864 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2865#undef R64
2866#undef R32
2867};
4df068de
RS		 2868
2869/* Names of the SVE vector registers, first with .S suffixes,
2870 then with .D suffixes. */
2871
2872static const char *sve_reg[2][32] = {
2873#define ZS(X) "z" #X ".s"
2874#define ZD(X) "z" #X ".d"
2875 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2876#undef ZD
2877#undef ZS
2878};
72e9f319 2879#undef BANK
a06ea964
NC		 2880
2881/* Return the integer register name.
2882 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2883
2884static inline const char *
2885get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2886{
2887 const int has_zr = sp_reg_p ? 0 : 1;
2888 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2889 return int_reg[has_zr][is_64][regno];
2890}
2891
2892/* Like get_int_reg_name, but IS_64 is always 1. */
2893
2894static inline const char *
2895get_64bit_int_reg_name (int regno, int sp_reg_p)
2896{
2897 const int has_zr = sp_reg_p ? 0 : 1;
2898 return int_reg[has_zr][1][regno];
2899}
2900
01dbfe4c
RS		 2901/* Get the name of the integer offset register in OPND, using the shift type
2902 to decide whether it's a word or doubleword. */
2903
2904static inline const char *
2905get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2906{
2907 switch (opnd->shifter.kind)
2908 {
2909 case AARCH64_MOD_UXTW:
2910 case AARCH64_MOD_SXTW:
2911 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2912
2913 case AARCH64_MOD_LSL:
2914 case AARCH64_MOD_SXTX:
2915 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2916
2917 default:
2918 abort ();
2919 }
2920}
2921
4df068de
RS		 2922/* Get the name of the SVE vector offset register in OPND, using the operand
2923 qualifier to decide whether the suffix should be .S or .D. */
2924
2925static inline const char *
2926get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2927{
2928 assert (qualifier == AARCH64_OPND_QLF_S_S
2929 || qualifier == AARCH64_OPND_QLF_S_D);
2930 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2931}
2932
a06ea964
NC		 2933/* Types for expanding an encoded 8-bit value to a floating-point value. */
2934
2935typedef union
2936{
2937 uint64_t i;
2938 double d;
2939} double_conv_t;
2940
2941typedef union
2942{
2943 uint32_t i;
2944 float f;
2945} single_conv_t;
2946
cf86120b
MW		 2947typedef union
2948{
2949 uint32_t i;
2950 float f;
2951} half_conv_t;
2952
a06ea964
NC		 2953/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2954 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2955 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2956 single-precision floating-point value (SIZE == 4) or a double-precision
2957 floating-point value (SIZE == 8). A half-precision floating-point value
2958 (SIZE == 2) is expanded to a single-precision floating-point value. The
2959 expanded value is returned. */
a06ea964
NC		 2960
2961static uint64_t
cf86120b 2962expand_fp_imm (int size, uint32_t imm8)
a06ea964 2963{
57a024f4 2964 uint64_t imm = 0;
a06ea964
NC		 2965 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2966
2967 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2968 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2969 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2970 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2971 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2972 if (size == 8)
a06ea964
NC		 2973 {
2974 imm = (imm8_7 << (63-32)) /* imm8<7> */
2975 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2976 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2977 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2978 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2979 imm <<= 32;
2980 }
cf86120b 2981 else if (size == 4 || size == 2)
a06ea964
NC		 2982 {
2983 imm = (imm8_7 << 31) /* imm8<7> */
2984 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2985 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2986 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2987 }
cf86120b
MW		 2988 else
2989 {
2990 /* An unsupported size. */
2991 assert (0);
2992 }
a06ea964
NC		 2993
2994 return imm;
2995}
2996
2997/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2998 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2999 the register name that comes before the register number, such as "v". */
a06ea964 3000static void
8a7f0c1b
RS		 3001print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3002 const char *prefix)
a06ea964
NC		 3003{
3004 const int num_regs = opnd->reglist.num_regs;
3005 const int first_reg = opnd->reglist.first_regno;
3006 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
3007 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3008 char tb[8]; /* Temporary buffer. */
3009
3010 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3011 assert (num_regs >= 1 && num_regs <= 4);
3012
3013 /* Prepare the index if any. */
3014 if (opnd->reglist.has_index)
1b7e3d2f
NC		 3015 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3016 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 3017 else
3018 tb[0] = '\0';
3019
3020 /* The hyphenated form is preferred for disassembly if there are
3021 more than two registers in the list, and the register numbers
3022 are monotonically increasing in increments of one. */
3023 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3024 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3025 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3026 else
3027 {
3028 const int reg0 = first_reg;
3029 const int reg1 = (first_reg + 1) & 0x1f;
3030 const int reg2 = (first_reg + 2) & 0x1f;
3031 const int reg3 = (first_reg + 3) & 0x1f;
3032
3033 switch (num_regs)
3034 {
3035 case 1:
8a7f0c1b 3036 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3037 break;
3038 case 2:
8a7f0c1b
RS		 3039 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3040 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3041 break;
3042 case 3:
8a7f0c1b
RS		 3043 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3044 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3045 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3046 break;
3047 case 4:
8a7f0c1b
RS		 3048 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3049 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3050 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3051 break;
3052 }
3053 }
3054}
3055
01dbfe4c
RS		 3056/* Print the register+immediate address in OPND to BUF, which has SIZE
3057 characters. BASE is the name of the base register. */
3058
3059static void
3060print_immediate_offset_address (char *buf, size_t size,
3061 const aarch64_opnd_info *opnd,
3062 const char *base)
3063{
3064 if (opnd->addr.writeback)
3065 {
3066 if (opnd->addr.preind)
1820262b
DB		 3067 {
3068 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3069 snprintf (buf, size, "[%s]!", base);
3070 else
3071 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3072 }
01dbfe4c 3073 else
ad43e107 3074 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3075 }
3076 else
3077 {
98907a70
RS		 3078 if (opnd->shifter.operator_present)
3079 {
3080 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3081 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3082 base, opnd->addr.offset.imm);
3083 }
3084 else if (opnd->addr.offset.imm)
ad43e107 3085 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3086 else
3087 snprintf (buf, size, "[%s]", base);
3088 }
3089}
3090
a06ea964 3091/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3092 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3093 the names of the base and offset registers. */
a06ea964
NC		 3094static void
3095print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3096 const aarch64_opnd_info *opnd,
3097 const char *base, const char *offset)
a06ea964 3098{
0d2f91fe 3099 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3100 bfd_boolean print_extend_p = TRUE;
3101 bfd_boolean print_amount_p = TRUE;
3102 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3103
a06ea964
NC		 3104 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3105 || !opnd->shifter.amount_present))
3106 {
3107 /* Not print the shift/extend amount when the amount is zero and
3108 when it is not the special case of 8-bit load/store instruction. */
3109 print_amount_p = FALSE;
3110 /* Likewise, no need to print the shift operator LSL in such a
3111 situation. */
01dbfe4c 3112 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3113 print_extend_p = FALSE;
3114 }
3115
3116 /* Prepare for the extend/shift. */
3117 if (print_extend_p)
3118 {
3119 if (print_amount_p)
ad43e107 3120 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3121 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3122 (opnd->shifter.amount % 100));
a06ea964 3123 else
ad43e107 3124 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3125 }
3126 else
3127 tb[0] = '\0';
3128
ad43e107 3129 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3130}
3131
3132/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3133 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3134 PC, PCREL_P and ADDRESS are used to pass in and return information about
3135 the PC-relative address calculation, where the PC value is passed in
3136 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3137 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3138 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3139
3140 The function serves both the disassembler and the assembler diagnostics
3141 issuer, which is the reason why it lives in this file. */
3142
3143void
3144aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3145 const aarch64_opcode *opcode,
3146 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3147 bfd_vma *address, char** notes)
a06ea964 3148{
bb7eff52 3149 unsigned int i, num_conds;
a06ea964
NC		 3150 const char *name = NULL;
3151 const aarch64_opnd_info *opnd = opnds + idx;
3152 enum aarch64_modifier_kind kind;
245d2e3f 3153 uint64_t addr, enum_value;
a06ea964
NC		 3154
3155 buf[0] = '\0';
3156 if (pcrel_p)
3157 *pcrel_p = 0;
3158
3159 switch (opnd->type)
3160 {
3161 case AARCH64_OPND_Rd:
3162 case AARCH64_OPND_Rn:
3163 case AARCH64_OPND_Rm:
3164 case AARCH64_OPND_Rt:
3165 case AARCH64_OPND_Rt2:
3166 case AARCH64_OPND_Rs:
3167 case AARCH64_OPND_Ra:
3168 case AARCH64_OPND_Rt_SYS:
ee804238 3169 case AARCH64_OPND_PAIRREG:
047cd301 3170 case AARCH64_OPND_SVE_Rm:
a06ea964 3171 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3172 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3173 generic optional-ness information. */
362c0c4d
JW		 3174 if (opnd->type == AARCH64_OPND_Rt_SYS)
3175 {
3176 if (!opnd->present)
3177 break;
3178 }
a06ea964 3179 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3180 else if (optional_operand_p (opcode, idx)
3181 && (opnd->reg.regno
3182 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3183 break;
3184 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3185 || opnd->qualifier == AARCH64_OPND_QLF_X);
3186 snprintf (buf, size, "%s",
3187 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3188 break;
3189
3190 case AARCH64_OPND_Rd_SP:
3191 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3192 case AARCH64_OPND_Rt_SP:
047cd301 3193 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3194 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3195 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3196 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3197 || opnd->qualifier == AARCH64_OPND_QLF_X
3198 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3199 snprintf (buf, size, "%s",
3200 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3201 break;
3202
3203 case AARCH64_OPND_Rm_EXT:
3204 kind = opnd->shifter.kind;
3205 assert (idx == 1 || idx == 2);
3206 if ((aarch64_stack_pointer_p (opnds)
3207 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3208 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3209 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3210 && kind == AARCH64_MOD_UXTW)
3211 || (opnd->qualifier == AARCH64_OPND_QLF_X
3212 && kind == AARCH64_MOD_UXTX)))
3213 {
3214 /* 'LSL' is the preferred form in this case. */
3215 kind = AARCH64_MOD_LSL;
3216 if (opnd->shifter.amount == 0)
3217 {
3218 /* Shifter omitted. */
3219 snprintf (buf, size, "%s",
3220 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3221 break;
3222 }
3223 }
3224 if (opnd->shifter.amount)
2442d846 3225 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3226 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3227 aarch64_operand_modifiers[kind].name,
3228 opnd->shifter.amount);
3229 else
3230 snprintf (buf, size, "%s, %s",
3231 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3232 aarch64_operand_modifiers[kind].name);
3233 break;
3234
3235 case AARCH64_OPND_Rm_SFT:
3236 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3237 || opnd->qualifier == AARCH64_OPND_QLF_X);
3238 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3239 snprintf (buf, size, "%s",
3240 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3241 else
2442d846 3242 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3243 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3244 aarch64_operand_modifiers[opnd->shifter.kind].name,
3245 opnd->shifter.amount);
3246 break;
3247
3248 case AARCH64_OPND_Fd:
3249 case AARCH64_OPND_Fn:
3250 case AARCH64_OPND_Fm:
3251 case AARCH64_OPND_Fa:
3252 case AARCH64_OPND_Ft:
3253 case AARCH64_OPND_Ft2:
3254 case AARCH64_OPND_Sd:
3255 case AARCH64_OPND_Sn:
3256 case AARCH64_OPND_Sm:
047cd301
RS		 3257 case AARCH64_OPND_SVE_VZn:
3258 case AARCH64_OPND_SVE_Vd:
3259 case AARCH64_OPND_SVE_Vm:
3260 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3261 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3262 opnd->reg.regno);
3263 break;
3264
f42f1a1d 3265 case AARCH64_OPND_Va:
a06ea964
NC		 3266 case AARCH64_OPND_Vd:
3267 case AARCH64_OPND_Vn:
3268 case AARCH64_OPND_Vm:
3269 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3270 aarch64_get_qualifier_name (opnd->qualifier));
3271 break;
3272
3273 case AARCH64_OPND_Ed:
3274 case AARCH64_OPND_En:
3275 case AARCH64_OPND_Em:
369c9167 3276 case AARCH64_OPND_Em16:
f42f1a1d 3277 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3278 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3279 aarch64_get_qualifier_name (opnd->qualifier),
3280 opnd->reglane.index);
3281 break;
3282
3283 case AARCH64_OPND_VdD1:
3284 case AARCH64_OPND_VnD1:
3285 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3286 break;
3287
3288 case AARCH64_OPND_LVn:
3289 case AARCH64_OPND_LVt:
3290 case AARCH64_OPND_LVt_AL:
3291 case AARCH64_OPND_LEt:
8a7f0c1b 3292 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3293 break;
3294
f11ad6bc
RS		 3295 case AARCH64_OPND_SVE_Pd:
3296 case AARCH64_OPND_SVE_Pg3:
3297 case AARCH64_OPND_SVE_Pg4_5:
3298 case AARCH64_OPND_SVE_Pg4_10:
3299 case AARCH64_OPND_SVE_Pg4_16:
3300 case AARCH64_OPND_SVE_Pm:
3301 case AARCH64_OPND_SVE_Pn:
3302 case AARCH64_OPND_SVE_Pt:
3303 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3304 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3305 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3306 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3307 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3308 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3309 else
3310 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3311 aarch64_get_qualifier_name (opnd->qualifier));
3312 break;
3313
3314 case AARCH64_OPND_SVE_Za_5:
3315 case AARCH64_OPND_SVE_Za_16:
3316 case AARCH64_OPND_SVE_Zd:
3317 case AARCH64_OPND_SVE_Zm_5:
3318 case AARCH64_OPND_SVE_Zm_16:
3319 case AARCH64_OPND_SVE_Zn:
3320 case AARCH64_OPND_SVE_Zt:
3321 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3322 snprintf (buf, size, "z%d", opnd->reg.regno);
3323 else
3324 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3325 aarch64_get_qualifier_name (opnd->qualifier));
3326 break;
3327
3328 case AARCH64_OPND_SVE_ZnxN:
3329 case AARCH64_OPND_SVE_ZtxN:
3330 print_register_list (buf, size, opnd, "z");
3331 break;
3332
582e12bf
RS		 3333 case AARCH64_OPND_SVE_Zm3_INDEX:
3334 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3335 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 3336 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf 3337 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3338 case AARCH64_OPND_SVE_Zn_INDEX:
3339 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3340 aarch64_get_qualifier_name (opnd->qualifier),
3341 opnd->reglane.index);
3342 break;
3343
a6a51754
RL		 3344 case AARCH64_OPND_CRn:
3345 case AARCH64_OPND_CRm:
3346 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3347 break;
3348
3349 case AARCH64_OPND_IDX:
f42f1a1d 3350 case AARCH64_OPND_MASK:
a06ea964 3351 case AARCH64_OPND_IMM:
f42f1a1d 3352 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3353 case AARCH64_OPND_WIDTH:
3354 case AARCH64_OPND_UIMM3_OP1:
3355 case AARCH64_OPND_UIMM3_OP2:
3356 case AARCH64_OPND_BIT_NUM:
3357 case AARCH64_OPND_IMM_VLSL:
3358 case AARCH64_OPND_IMM_VLSR:
3359 case AARCH64_OPND_SHLL_IMM:
3360 case AARCH64_OPND_IMM0:
3361 case AARCH64_OPND_IMMR:
3362 case AARCH64_OPND_IMMS:
3363 case AARCH64_OPND_FBITS:
b83b4b13 3364 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3365 case AARCH64_OPND_SIMM5:
3366 case AARCH64_OPND_SVE_SHLIMM_PRED:
3367 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 3368 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 3369 case AARCH64_OPND_SVE_SHRIMM_PRED:
3370 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 3371 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345
RS		 3372 case AARCH64_OPND_SVE_SIMM5:
3373 case AARCH64_OPND_SVE_SIMM5B:
3374 case AARCH64_OPND_SVE_SIMM6:
3375 case AARCH64_OPND_SVE_SIMM8:
3376 case AARCH64_OPND_SVE_UIMM3:
3377 case AARCH64_OPND_SVE_UIMM7:
3378 case AARCH64_OPND_SVE_UIMM8:
3379 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3380 case AARCH64_OPND_IMM_ROT1:
3381 case AARCH64_OPND_IMM_ROT2:
3382 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3383 case AARCH64_OPND_SVE_IMM_ROT1:
3384 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3385 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3386 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3387 break;
3388
165d4950
RS		 3389 case AARCH64_OPND_SVE_I1_HALF_ONE:
3390 case AARCH64_OPND_SVE_I1_HALF_TWO:
3391 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3392 {
3393 single_conv_t c;
3394 c.i = opnd->imm.value;
3395 snprintf (buf, size, "#%.1f", c.f);
3396 break;
3397 }
3398
245d2e3f
RS		 3399 case AARCH64_OPND_SVE_PATTERN:
3400 if (optional_operand_p (opcode, idx)
3401 && opnd->imm.value == get_optional_operand_default_value (opcode))
3402 break;
3403 enum_value = opnd->imm.value;
3404 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3405 if (aarch64_sve_pattern_array[enum_value])
3406 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3407 else
3408 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3409 break;
3410
2442d846
RS		 3411 case AARCH64_OPND_SVE_PATTERN_SCALED:
3412 if (optional_operand_p (opcode, idx)
3413 && !opnd->shifter.operator_present
3414 && opnd->imm.value == get_optional_operand_default_value (opcode))
3415 break;
3416 enum_value = opnd->imm.value;
3417 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3418 if (aarch64_sve_pattern_array[opnd->imm.value])
3419 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3420 else
3421 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3422 if (opnd->shifter.operator_present)
3423 {
3424 size_t len = strlen (buf);
3425 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3426 aarch64_operand_modifiers[opnd->shifter.kind].name,
3427 opnd->shifter.amount);
3428 }
3429 break;
3430
245d2e3f
RS		 3431 case AARCH64_OPND_SVE_PRFOP:
3432 enum_value = opnd->imm.value;
3433 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3434 if (aarch64_sve_prfop_array[enum_value])
3435 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3436 else
3437 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3438 break;
3439
fb098a1e
YZ		 3440 case AARCH64_OPND_IMM_MOV:
3441 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3442 {
3443 case 4: /* e.g. MOV Wd, #<imm32>. */
3444 {
3445 int imm32 = opnd->imm.value;
3446 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3447 }
3448 break;
3449 case 8: /* e.g. MOV Xd, #<imm64>. */
3450 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3451 opnd->imm.value, opnd->imm.value);
3452 break;
3453 default: assert (0);
3454 }
3455 break;
3456
a06ea964
NC		 3457 case AARCH64_OPND_FPIMM0:
3458 snprintf (buf, size, "#0.0");
3459 break;
3460
3461 case AARCH64_OPND_LIMM:
3462 case AARCH64_OPND_AIMM:
3463 case AARCH64_OPND_HALF:
e950b345
RS		 3464 case AARCH64_OPND_SVE_INV_LIMM:
3465 case AARCH64_OPND_SVE_LIMM:
3466 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3467 if (opnd->shifter.amount)
2442d846 3468 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3469 opnd->shifter.amount);
3470 else
3471 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3472 break;
3473
3474 case AARCH64_OPND_SIMD_IMM:
3475 case AARCH64_OPND_SIMD_IMM_SFT:
3476 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3477 || opnd->shifter.kind == AARCH64_MOD_NONE)
3478 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3479 else
2442d846 3480 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3481 aarch64_operand_modifiers[opnd->shifter.kind].name,
3482 opnd->shifter.amount);
3483 break;
3484
e950b345
RS		 3485 case AARCH64_OPND_SVE_AIMM:
3486 case AARCH64_OPND_SVE_ASIMM:
3487 if (opnd->shifter.amount)
3488 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3489 opnd->shifter.amount);
3490 else
3491 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3492 break;
3493
a06ea964
NC		 3494 case AARCH64_OPND_FPIMM:
3495 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3496 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3497 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3498 {
cf86120b
MW		 3499 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3500 {
3501 half_conv_t c;
3502 c.i = expand_fp_imm (2, opnd->imm.value);
3503 snprintf (buf, size, "#%.18e", c.f);
3504 }
3505 break;
a06ea964
NC		 3506 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3507 {
3508 single_conv_t c;
cf86120b 3509 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3510 snprintf (buf, size, "#%.18e", c.f);
3511 }
3512 break;
3513 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3514 {
3515 double_conv_t c;
cf86120b 3516 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3517 snprintf (buf, size, "#%.18e", c.d);
3518 }
3519 break;
3520 default: assert (0);
3521 }
3522 break;
3523
3524 case AARCH64_OPND_CCMP_IMM:
3525 case AARCH64_OPND_NZCV:
3526 case AARCH64_OPND_EXCEPTION:
3527 case AARCH64_OPND_UIMM4:
193614f2 3528 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3529 case AARCH64_OPND_UIMM7:
193614f2 3530 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3531 if (optional_operand_p (opcode, idx) == TRUE
3532 && (opnd->imm.value ==
3533 (int64_t) get_optional_operand_default_value (opcode)))
3534 /* Omit the operand, e.g. DCPS1. */
3535 break;
3536 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3537 break;
3538
3539 case AARCH64_OPND_COND:
68a64283 3540 case AARCH64_OPND_COND1:
a06ea964 3541 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3542 num_conds = ARRAY_SIZE (opnd->cond->names);
3543 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3544 {
3545 size_t len = strlen (buf);
3546 if (i == 1)
3547 snprintf (buf + len, size - len, " // %s = %s",
3548 opnd->cond->names[0], opnd->cond->names[i]);
3549 else
3550 snprintf (buf + len, size - len, ", %s",
3551 opnd->cond->names[i]);
3552 }
a06ea964
NC		 3553 break;
3554
3555 case AARCH64_OPND_ADDR_ADRP:
3556 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3557 + opnd->imm.value;
3558 if (pcrel_p)
3559 *pcrel_p = 1;
3560 if (address)
3561 *address = addr;
3562 /* This is not necessary during the disassembling, as print_address_func
3563 in the disassemble_info will take care of the printing. But some
3564 other callers may be still interested in getting the string in *STR,
3565 so here we do snprintf regardless. */
3566 snprintf (buf, size, "#0x%" PRIx64, addr);
3567 break;
3568
3569 case AARCH64_OPND_ADDR_PCREL14:
3570 case AARCH64_OPND_ADDR_PCREL19:
3571 case AARCH64_OPND_ADDR_PCREL21:
3572 case AARCH64_OPND_ADDR_PCREL26:
3573 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3574 if (pcrel_p)
3575 *pcrel_p = 1;
3576 if (address)
3577 *address = addr;
3578 /* This is not necessary during the disassembling, as print_address_func
3579 in the disassemble_info will take care of the printing. But some
3580 other callers may be still interested in getting the string in *STR,
3581 so here we do snprintf regardless. */
3582 snprintf (buf, size, "#0x%" PRIx64, addr);
3583 break;
3584
3585 case AARCH64_OPND_ADDR_SIMPLE:
3586 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3587 case AARCH64_OPND_SIMD_ADDR_POST:
3588 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3589 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3590 {
3591 if (opnd->addr.offset.is_reg)
3592 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3593 else
3594 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3595 }
3596 else
3597 snprintf (buf, size, "[%s]", name);
3598 break;
3599
3600 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3601 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3602 case AARCH64_OPND_SVE_ADDR_RR:
3603 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3604 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3605 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3606 case AARCH64_OPND_SVE_ADDR_RX:
3607 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3608 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3609 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3610 print_register_offset_address
3611 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3612 get_offset_int_reg_name (opnd));
a06ea964
NC		 3613 break;
3614
c469c864
MM		 3615 case AARCH64_OPND_SVE_ADDR_ZX:
3616 print_register_offset_address
3617 (buf, size, opnd,
3618 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3619 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3620 break;
3621
4df068de
RS		 3622 case AARCH64_OPND_SVE_ADDR_RZ:
3623 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3624 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3625 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3626 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3627 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3628 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3629 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3630 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3631 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3632 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3633 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3634 print_register_offset_address
3635 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3636 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3637 break;
3638
a06ea964
NC		 3639 case AARCH64_OPND_ADDR_SIMM7:
3640 case AARCH64_OPND_ADDR_SIMM9:
3641 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3642 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3643 case AARCH64_OPND_ADDR_SIMM11:
3644 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3645 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3646 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS		 3647 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3648 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3649 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3650 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3651 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3652 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3653 case AARCH64_OPND_SVE_ADDR_RI_U6:
3654 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3655 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3656 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3657 print_immediate_offset_address
3658 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3659 break;
3660
4df068de
RS		 3661 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3662 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3663 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3664 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3665 print_immediate_offset_address
3666 (buf, size, opnd,
3667 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3668 break;
3669
3670 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3671 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3672 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3673 print_register_offset_address
3674 (buf, size, opnd,
3675 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3676 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3677 break;
3678
a06ea964
NC		 3679 case AARCH64_OPND_ADDR_UIMM12:
3680 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3681 if (opnd->addr.offset.imm)
ad43e107 3682 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3683 else
3684 snprintf (buf, size, "[%s]", name);
3685 break;
3686
3687 case AARCH64_OPND_SYSREG:
3688 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3689 {
3690 bfd_boolean exact_match
3691 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3692 == opnd->sysreg.flags;
3693
3694 /* Try and find an exact match, But if that fails, return the first
3695 partial match that was found. */
3696 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3697 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3698 && (name == NULL || exact_match))
3699 {
3700 name = aarch64_sys_regs[i].name;
3701 if (exact_match)
3702 {
3703 if (notes)
3704 *notes = NULL;
3705 break;
3706 }
3707
3708 /* If we didn't match exactly, that means the presense of a flag
3709 indicates what we didn't want for this instruction. e.g. If
3710 F_REG_READ is there, that means we were looking for a write
3711 register. See aarch64_ext_sysreg. */
3712 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3713 *notes = _("reading from a write-only register");
f9830ec1 3714 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3715 *notes = _("writing to a read-only register");
f9830ec1
TC		 3716 }
3717 }
3718
3719 if (name)
3720 snprintf (buf, size, "%s", name);
a06ea964
NC		 3721 else
3722 {
3723 /* Implementation defined system register. */
561a72d4 3724 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3725 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3726 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3727 value & 0x7);
3728 }
3729 break;
3730
3731 case AARCH64_OPND_PSTATEFIELD:
3732 for (i = 0; aarch64_pstatefields[i].name; ++i)
3733 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3734 break;
3735 assert (aarch64_pstatefields[i].name);
3736 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3737 break;
3738
3739 case AARCH64_OPND_SYSREG_AT:
3740 case AARCH64_OPND_SYSREG_DC:
3741 case AARCH64_OPND_SYSREG_IC:
3742 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3743 case AARCH64_OPND_SYSREG_SR:
875880c6 3744 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3745 break;
3746
3747 case AARCH64_OPND_BARRIER:
3748 snprintf (buf, size, "%s", opnd->barrier->name);
3749 break;
3750
3751 case AARCH64_OPND_BARRIER_ISB:
3752 /* Operand can be omitted, e.g. in DCPS1. */
3753 if (! optional_operand_p (opcode, idx)
3754 || (opnd->barrier->value
3755 != get_optional_operand_default_value (opcode)))
3756 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3757 break;
3758
3759 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3760 if (opnd->prfop->name != NULL)
3761 snprintf (buf, size, "%s", opnd->prfop->name);
3762 else
3763 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3764 break;
3765
1e6f4800 3766 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3767 case AARCH64_OPND_BTI_TARGET:
3768 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3769 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3770 break;
3771
a06ea964
NC		 3772 default:
3773 assert (0);
3774 }
3775}
3776\f
3777#define CPENC(op0,op1,crn,crm,op2) \
3778 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3779 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3780#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3781 /* for 3.9.10 System Instructions */
3782#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3783
3784#define C0 0
3785#define C1 1
3786#define C2 2
3787#define C3 3
3788#define C4 4
3789#define C5 5
3790#define C6 6
3791#define C7 7
3792#define C8 8
3793#define C9 9
3794#define C10 10
3795#define C11 11
3796#define C12 12
3797#define C13 13
3798#define C14 14
3799#define C15 15
3800
f9830ec1
TC		 3801/* TODO there is one more issues need to be resolved
3802 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3803const aarch64_sys_reg aarch64_sys_regs [] =
3804{
3805 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3806 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3807 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3808 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3809 { "sp_el0", CPEN_(0,C1,0), 0 },
3810 { "spsel", CPEN_(0,C2,0), 0 },
3811 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3812 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3813 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3814 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3815 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3816 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3817 { "fpcr", CPEN_(3,C4,0), 0 },
3818 { "fpsr", CPEN_(3,C4,1), 0 },
3819 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3820 { "dlr_el0", CPEN_(3,C5,1), 0 },
3821 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3822 { "elr_el2", CPEN_(4,C0,1), 0 },
3823 { "sp_el1", CPEN_(4,C1,0), 0 },
3824 { "spsr_irq", CPEN_(4,C3,0), 0 },
3825 { "spsr_abt", CPEN_(4,C3,1), 0 },
3826 { "spsr_und", CPEN_(4,C3,2), 0 },
3827 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3828 { "spsr_el3", CPEN_(6,C0,0), 0 },
3829 { "elr_el3", CPEN_(6,C0,1), 0 },
3830 { "sp_el2", CPEN_(6,C1,0), 0 },
3831 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3832 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3833 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3834 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3835 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3836 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3837 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3838 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3839 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3840 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3841 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3842 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3843 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3844 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3845 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3846 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3847 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3848 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3849 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3850 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3851 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3852 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3853 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3854 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3855 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3856 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3857 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3858 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3859 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3860 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3861 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3862 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3863 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3864 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3865 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3866 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3867 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3868 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3869 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3870 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3871 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3872 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3873 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3874 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3875 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3876 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3877 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3878 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3879 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3880 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3881 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3882 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3883 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3884 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3885 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3886 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3887 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3888 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3889 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3890 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3891 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3892 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3893 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3894 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3895 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3896 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3897 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3898 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3899 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3900 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3901 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3902 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3903 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3904 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3905 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3906 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3907 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3908 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3909 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3910 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3911 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3912 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3913 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3914 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3915 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3916 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3917 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3918 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3919 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3920 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3921 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3922 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3923 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3924 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3925 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3926 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3927 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3928 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3929 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3930 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3931 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3932 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3933 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3934 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3935 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3936 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3937 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3938 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3939 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3940 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3941 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3942 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3943 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3944 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3945 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3946 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3947 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3948 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3949 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3950 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3951 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3952 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3953 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3954 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3955 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3956 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3957 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3958 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3959 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3960 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3961 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3962 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3963 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3964 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3965 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3966 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3967 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3968 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3969 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3970 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3971 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3972 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3973 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
70f3d23a 3974 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
a051e2f3
KT		 3975 { "tfsre0_el1", CPENC(3,0,C5,C6,1), F_ARCHEXT },
3976 { "tfsr_el1", CPENC(3,0,C5,C6,0), F_ARCHEXT },
3977 { "tfsr_el2", CPENC(3,4,C5,C6,0), F_ARCHEXT },
3978 { "tfsr_el3", CPENC(3,6,C5,C6,0), F_ARCHEXT },
3979 { "tfsr_el12", CPENC(3,5,C5,C6,0), F_ARCHEXT },
70f3d23a
SD		 3980 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3981 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
a028026d 3982 { "gmid_el1", CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
49eec193 3983 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3984 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3985 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3986 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3987 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3988 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3989 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3990 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3991 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3992 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3993 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3994 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3995 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3996 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3997 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3998 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 3999 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 4000 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
4001 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 4002 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 4003 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 4004 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 4005 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 4006 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 4007 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 4008 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 4009 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 4010 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 4011 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 4012 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4013 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
4014 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
4015 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
4016 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
4017 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
4018 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 4019 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
4020 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
4021 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4022 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
4023 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
4024 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
4025 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
4026 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 4027 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 4028 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
4029 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 4030 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
4031 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 4032 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
4033 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 4034 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
4035 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
4036 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
4037 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
4038 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
4039 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
4040 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
4041 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
4042 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
4043 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
4044 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
4045 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
4046 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
4047 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
4048 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4049 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4050 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4051 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4052 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4053 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4054 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4055 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4056 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4057 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4058 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4059 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4060 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4061 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4062 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4063 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4064 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4065 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4066 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4067 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4068 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4069 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4070 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4071 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4072 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4073 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4074 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4075 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4076 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4077 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4078 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4079 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4080 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4081 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4082 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4083 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4084 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4085 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4086 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4087 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4088 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4089 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4090 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4091 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4092 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4093 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4094 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4095 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4096 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4097 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4098 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4099 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4100 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4101 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4102 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4103 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4104 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4105 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4106 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4107 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4108 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4109 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4110 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4111 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4112 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4113 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4114 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4115 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4116 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4117 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4118 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4119 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4120 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4121 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4122 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4123 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4124 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4125 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4126 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4127 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4128 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4129 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4130 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4131 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4132 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4133 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4134 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4135 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4136 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4137 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4138 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4139 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4140 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4141 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4142 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4143 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4144 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4145 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4146 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4147 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4148 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4149 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4150 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4151 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4152 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4153 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4154 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4155 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4156 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4157 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4158 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4159 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4160 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4161 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4162 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4163 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4164 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4165 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4166 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4167 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4168 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4169 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4170 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4171 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4172 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4173 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4174 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4175 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4176 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4177 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4178 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4179 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4180 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4181 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4182 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4183 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4184 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4185 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4186 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4187 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4188 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4189 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4190 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4191 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4192 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4193 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4194 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4195 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4196 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4197 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4198 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4199
4200 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4201 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4202 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4203 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4204 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4205 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4206 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4207 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4208 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4209 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4210 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4211 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4212};
4213
49eec193
YZ		 4214bfd_boolean
4215aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4216{
4217 return (reg->flags & F_DEPRECATED) != 0;
4218}
4219
f21cce2c
MW		 4220bfd_boolean
4221aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4222 const aarch64_sys_reg *reg)
4223{
4224 if (!(reg->flags & F_ARCHEXT))
4225 return TRUE;
4226
4227 /* PAN. Values are from aarch64_sys_regs. */
4228 if (reg->value == CPEN_(0,C2,3)
4229 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4230 return FALSE;
4231
a97330e7
SD		 4232 /* SCXTNUM_ELx registers. */
4233 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4234 || reg->value == CPENC (3, 0, C13, C0, 7)
4235 || reg->value == CPENC (3, 4, C13, C0, 7)
4236 || reg->value == CPENC (3, 6, C13, C0, 7)
4237 || reg->value == CPENC (3, 5, C13, C0, 7))
4238 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4239 return FALSE;
4240
4241 /* ID_PFR2_EL1 register. */
4242 if (reg->value == CPENC(3, 0, C0, C3, 4)
4243 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4244 return FALSE;
4245
104fefee
SD		 4246 /* SSBS. Values are from aarch64_sys_regs. */
4247 if (reg->value == CPEN_(3,C2,6)
4248 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4249 return FALSE;
4250
250aafa4
MW		 4251 /* Virtualization host extensions: system registers. */
4252 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4253 || reg->value == CPENC (3, 4, C13, C0, 1)
4254 || reg->value == CPENC (3, 4, C14, C3, 0)
4255 || reg->value == CPENC (3, 4, C14, C3, 1)
4256 || reg->value == CPENC (3, 4, C14, C3, 2))
4257 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4258 return FALSE;
4259
4260 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4261 if ((reg->value == CPEN_ (5, C0, 0)
4262 || reg->value == CPEN_ (5, C0, 1)
4263 || reg->value == CPENC (3, 5, C1, C0, 0)
4264 || reg->value == CPENC (3, 5, C1, C0, 2)
4265 || reg->value == CPENC (3, 5, C2, C0, 0)
4266 || reg->value == CPENC (3, 5, C2, C0, 1)
4267 || reg->value == CPENC (3, 5, C2, C0, 2)
4268 || reg->value == CPENC (3, 5, C5, C1, 0)
4269 || reg->value == CPENC (3, 5, C5, C1, 1)
4270 || reg->value == CPENC (3, 5, C5, C2, 0)
4271 || reg->value == CPENC (3, 5, C6, C0, 0)
4272 || reg->value == CPENC (3, 5, C10, C2, 0)
4273 || reg->value == CPENC (3, 5, C10, C3, 0)
4274 || reg->value == CPENC (3, 5, C12, C0, 0)
4275 || reg->value == CPENC (3, 5, C13, C0, 1)
4276 || reg->value == CPENC (3, 5, C14, C1, 0))
4277 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4278 return FALSE;
4279
4280 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4281 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4282 || reg->value == CPENC (3, 5, C14, C2, 1)
4283 || reg->value == CPENC (3, 5, C14, C2, 2)
4284 || reg->value == CPENC (3, 5, C14, C3, 0)
4285 || reg->value == CPENC (3, 5, C14, C3, 1)
4286 || reg->value == CPENC (3, 5, C14, C3, 2))
4287 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4288 return FALSE;
1a04d1a7
MW		 4289
4290 /* ARMv8.2 features. */
6479e48e
MW		 4291
4292 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4293 if (reg->value == CPENC (3, 0, C0, C7, 2)
4294 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4295 return FALSE;
4296
6479e48e
MW		 4297 /* PSTATE.UAO. */
4298 if (reg->value == CPEN_ (0, C2, 4)
4299 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4300 return FALSE;
4301
47f81142
MW		 4302 /* RAS extension. */
4303
651657fa
MW		 4304 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4305 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4306 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4307 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4308 || reg->value == CPENC (3, 0, C5, C3, 2)
4309 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4310 || reg->value == CPENC (3, 0, C5, C4, 0)
4311 || reg->value == CPENC (3, 0, C5, C4, 1)
4312 || reg->value == CPENC (3, 0, C5, C4, 2)
4313 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4314 || reg->value == CPENC (3, 0, C5, C5, 0)
4315 || reg->value == CPENC (3, 0, C5, C5, 1))
4316 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4317 return FALSE;
4318
4319 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4320 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4321 || reg->value == CPENC (3, 0, C12, C1, 1)
4322 || reg->value == CPENC (3, 4, C12, C1, 1))
4323 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4324 return FALSE;
4325
55c144e6
MW		 4326 /* Statistical Profiling extension. */
4327 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4328 || reg->value == CPENC (3, 0, C9, C10, 1)
4329 || reg->value == CPENC (3, 0, C9, C10, 3)
4330 || reg->value == CPENC (3, 0, C9, C10, 7)
4331 || reg->value == CPENC (3, 0, C9, C9, 0)
4332 || reg->value == CPENC (3, 0, C9, C9, 2)
4333 || reg->value == CPENC (3, 0, C9, C9, 3)
4334 || reg->value == CPENC (3, 0, C9, C9, 4)
4335 || reg->value == CPENC (3, 0, C9, C9, 5)
4336 || reg->value == CPENC (3, 0, C9, C9, 6)
4337 || reg->value == CPENC (3, 0, C9, C9, 7)
4338 || reg->value == CPENC (3, 4, C9, C9, 0)
4339 || reg->value == CPENC (3, 5, C9, C9, 0))
4340 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4341 return FALSE;
4342
b0bfa7b5
SN		 4343 /* ARMv8.3 Pointer authentication keys. */
4344 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4345 || reg->value == CPENC (3, 0, C2, C1, 1)
4346 || reg->value == CPENC (3, 0, C2, C1, 2)
4347 || reg->value == CPENC (3, 0, C2, C1, 3)
4348 || reg->value == CPENC (3, 0, C2, C2, 0)
4349 || reg->value == CPENC (3, 0, C2, C2, 1)
4350 || reg->value == CPENC (3, 0, C2, C2, 2)
4351 || reg->value == CPENC (3, 0, C2, C2, 3)
4352 || reg->value == CPENC (3, 0, C2, C3, 0)
4353 || reg->value == CPENC (3, 0, C2, C3, 1))
4354 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4355 return FALSE;
4356
773fb663
RS		 4357 /* SVE. */
4358 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4359 || reg->value == CPENC (3, 0, C1, C2, 0)
4360 || reg->value == CPENC (3, 4, C1, C2, 0)
4361 || reg->value == CPENC (3, 6, C1, C2, 0)
4362 || reg->value == CPENC (3, 5, C1, C2, 0)
4363 || reg->value == CPENC (3, 0, C0, C0, 7))
4364 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4365 return FALSE;
4366
793a1948
TC		 4367 /* ARMv8.4 features. */
4368
4369 /* PSTATE.DIT. */
4370 if (reg->value == CPEN_ (3, C2, 5)
4371 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4372 return FALSE;
4373
4374 /* Virtualization extensions. */
4375 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4376 || reg->value == CPENC(3, 4, C2, C6, 0)
4377 || reg->value == CPENC(3, 4, C14, C4, 0)
4378 || reg->value == CPENC(3, 4, C14, C4, 2)
4379 || reg->value == CPENC(3, 4, C14, C4, 1)
4380 || reg->value == CPENC(3, 4, C14, C5, 0)
4381 || reg->value == CPENC(3, 4, C14, C5, 2)
4382 || reg->value == CPENC(3, 4, C14, C5, 1)
4383 || reg->value == CPENC(3, 4, C1, C3, 1)
4384 || reg->value == CPENC(3, 4, C2, C2, 0))
4385 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4386 return FALSE;
4387
4388 /* ARMv8.4 TLB instructions. */
4389 if ((reg->value == CPENS (0, C8, C1, 0)
4390 || reg->value == CPENS (0, C8, C1, 1)
4391 || reg->value == CPENS (0, C8, C1, 2)
4392 || reg->value == CPENS (0, C8, C1, 3)
4393 || reg->value == CPENS (0, C8, C1, 5)
4394 || reg->value == CPENS (0, C8, C1, 7)
4395 || reg->value == CPENS (4, C8, C4, 0)
4396 || reg->value == CPENS (4, C8, C4, 4)
4397 || reg->value == CPENS (4, C8, C1, 1)
4398 || reg->value == CPENS (4, C8, C1, 5)
4399 || reg->value == CPENS (4, C8, C1, 6)
4400 || reg->value == CPENS (6, C8, C1, 1)
4401 || reg->value == CPENS (6, C8, C1, 5)
4402 || reg->value == CPENS (4, C8, C1, 0)
4403 || reg->value == CPENS (4, C8, C1, 4)
4404 || reg->value == CPENS (6, C8, C1, 0)
4405 || reg->value == CPENS (0, C8, C6, 1)
4406 || reg->value == CPENS (0, C8, C6, 3)
4407 || reg->value == CPENS (0, C8, C6, 5)
4408 || reg->value == CPENS (0, C8, C6, 7)
4409 || reg->value == CPENS (0, C8, C2, 1)
4410 || reg->value == CPENS (0, C8, C2, 3)
4411 || reg->value == CPENS (0, C8, C2, 5)
4412 || reg->value == CPENS (0, C8, C2, 7)
4413 || reg->value == CPENS (0, C8, C5, 1)
4414 || reg->value == CPENS (0, C8, C5, 3)
4415 || reg->value == CPENS (0, C8, C5, 5)
4416 || reg->value == CPENS (0, C8, C5, 7)
4417 || reg->value == CPENS (4, C8, C0, 2)
4418 || reg->value == CPENS (4, C8, C0, 6)
4419 || reg->value == CPENS (4, C8, C4, 2)
4420 || reg->value == CPENS (4, C8, C4, 6)
4421 || reg->value == CPENS (4, C8, C4, 3)
4422 || reg->value == CPENS (4, C8, C4, 7)
4423 || reg->value == CPENS (4, C8, C6, 1)
4424 || reg->value == CPENS (4, C8, C6, 5)
4425 || reg->value == CPENS (4, C8, C2, 1)
4426 || reg->value == CPENS (4, C8, C2, 5)
4427 || reg->value == CPENS (4, C8, C5, 1)
4428 || reg->value == CPENS (4, C8, C5, 5)
4429 || reg->value == CPENS (6, C8, C6, 1)
4430 || reg->value == CPENS (6, C8, C6, 5)
4431 || reg->value == CPENS (6, C8, C2, 1)
4432 || reg->value == CPENS (6, C8, C2, 5)
4433 || reg->value == CPENS (6, C8, C5, 1)
4434 || reg->value == CPENS (6, C8, C5, 5))
4435 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4436 return FALSE;
4437
af4bcb4c
SD		 4438 /* Random Number Instructions. For now they are available
4439 (and optional) only with ARMv8.5-A. */
4440 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4441 || reg->value == CPENC (3, 3, C2, C4, 1))
4442 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4443 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4444 return FALSE;
4445
70f3d23a
SD		 4446 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4447 if ((reg->value == CPENC (3, 3, C4, C2, 7)
a051e2f3
KT		 4448 || reg->value == CPENC (3, 0, C5, C6, 1)
4449 || reg->value == CPENC (3, 0, C5, C6, 0)
4450 || reg->value == CPENC (3, 4, C5, C6, 0)
4451 || reg->value == CPENC (3, 6, C5, C6, 0)
4452 || reg->value == CPENC (3, 5, C5, C6, 0)
70f3d23a 4453 || reg->value == CPENC (3, 0, C1, C0, 5)
a028026d
KT		 4454 || reg->value == CPENC (3, 0, C1, C0, 6)
4455 || reg->value == CPENC (3, 1, C0, C0, 4))
70f3d23a
SD		 4456 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4457 return FALSE;
4458
f21cce2c
MW		 4459 return TRUE;
4460}
4461
793a1948
TC		 4462/* The CPENC below is fairly misleading, the fields
4463 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4464 by ins_pstatefield, which just shifts the value by the width of the fields
4465 in a loop. So if you CPENC them only the first value will be set, the rest
4466 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4467 value of 0b110000000001000000 (0x30040) while what you want is
4468 0b011010 (0x1a). */
87b8eed7 4469const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4470{
87b8eed7
YZ		 4471 { "spsel", 0x05, 0 },
4472 { "daifset", 0x1e, 0 },
4473 { "daifclr", 0x1f, 0 },
f21cce2c 4474 { "pan", 0x04, F_ARCHEXT },
6479e48e 4475 { "uao", 0x03, F_ARCHEXT },
104fefee 4476 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4477 { "dit", 0x1a, F_ARCHEXT },
70f3d23a 4478 { "tco", 0x1c, F_ARCHEXT },
87b8eed7 4479 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4480};
4481
f21cce2c
MW		 4482bfd_boolean
4483aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4484 const aarch64_sys_reg *reg)
4485{
4486 if (!(reg->flags & F_ARCHEXT))
4487 return TRUE;
4488
4489 /* PAN. Values are from aarch64_pstatefields. */
4490 if (reg->value == 0x04
4491 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4492 return FALSE;
4493
6479e48e
MW		 4494 /* UAO. Values are from aarch64_pstatefields. */
4495 if (reg->value == 0x03
4496 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4497 return FALSE;
4498
104fefee
SD		 4499 /* SSBS. Values are from aarch64_pstatefields. */
4500 if (reg->value == 0x19
4501 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4502 return FALSE;
4503
793a1948
TC		 4504 /* DIT. Values are from aarch64_pstatefields. */
4505 if (reg->value == 0x1a
4506 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4507 return FALSE;
4508
70f3d23a
SD		 4509 /* TCO. Values are from aarch64_pstatefields. */
4510 if (reg->value == 0x1c
4511 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4512 return FALSE;
4513
f21cce2c
MW		 4514 return TRUE;
4515}
4516
a06ea964
NC		 4517const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4518{
4519 { "ialluis", CPENS(0,C7,C1,0), 0 },
4520 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4521 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4522 { 0, CPENS(0,0,0,0), 0 }
4523};
4524
4525const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4526{
ea2deeec 4527 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4528 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4529 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4530 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4531 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4532 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4533 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4534 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4535 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4536 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4537 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4538 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4539 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4540 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4541 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4542 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4543 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4544 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4545 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4546 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4547 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4548 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4549 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4550 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4551 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4552 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4553 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4554 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4555 { 0, CPENS(0,0,0,0), 0 }
4556};
4557
4558const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4559{
ea2deeec
MW		 4560 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4561 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4562 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4563 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4564 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4565 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4566 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4567 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4568 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4569 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4570 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4571 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4572 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4573 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4574 { 0, CPENS(0,0,0,0), 0 }
4575};
4576
4577const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4578{
4579 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4580 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4581 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4582 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4583 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4584 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4585 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4586 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4587 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4588 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4589 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4590 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4591 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4592 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4593 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4594 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4595 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4596 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4597 { "alle2", CPENS(4,C8,C7,0), 0 },
4598 { "alle2is", CPENS(4,C8,C3,0), 0 },
4599 { "alle1", CPENS(4,C8,C7,4), 0 },
4600 { "alle1is", CPENS(4,C8,C3,4), 0 },
4601 { "alle3", CPENS(6,C8,C7,0), 0 },
4602 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4603 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4604 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4605 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4606 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4607 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4608 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4609 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4610 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4611
4612 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4613 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4614 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4615 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4616 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4617 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4618 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4619 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4620 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4621 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4622 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4623 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4624 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4625 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4626 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4627 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4628
4629 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4630 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4631 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4632 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4633 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4634 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4635 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4636 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4637 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4638 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4639 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4640 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4641 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4642 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4643 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4644 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4645 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4646 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4647 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4648 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4649 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4650 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4651 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4652 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4653 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4654 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4655 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4656 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4657 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4658 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4659
a06ea964
NC		 4660 { 0, CPENS(0,0,0,0), 0 }
4661};
4662
2ac435d4
SD		 4663const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4664{
4665 /* RCTX is somewhat unique in a way that it has different values
4666 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4667 Thus op2 is masked out and instead encoded directly in the
4668 aarch64_opcode_table entries for the respective instructions. */
4669 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4670
4671 { 0, CPENS(0,0,0,0), 0 }
4672};
4673
ea2deeec
MW		 4674bfd_boolean
4675aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4676{
4677 return (sys_ins_reg->flags & F_HASXT) != 0;
4678}
4679
d6bf7ce6
MW		 4680extern bfd_boolean
4681aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4682 const aarch64_sys_ins_reg *reg)
4683{
4684 if (!(reg->flags & F_ARCHEXT))
4685 return TRUE;
4686
4687 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4688 if (reg->value == CPENS (3, C7, C12, 1)
4689 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4690 return FALSE;
4691
3fd229a4
SD		 4692 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4693 if (reg->value == CPENS (3, C7, C13, 1)
4694 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4695 return FALSE;
4696
3a0f69be
SD		 4697 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4698 if ((reg->value == CPENS (0, C7, C6, 3)
4699 || reg->value == CPENS (0, C7, C6, 4)
4700 || reg->value == CPENS (0, C7, C10, 4)
4701 || reg->value == CPENS (0, C7, C14, 4)
4702 || reg->value == CPENS (3, C7, C10, 3)
4703 || reg->value == CPENS (3, C7, C12, 3)
4704 || reg->value == CPENS (3, C7, C13, 3)
4705 || reg->value == CPENS (3, C7, C14, 3)
4706 || reg->value == CPENS (3, C7, C4, 3)
4707 || reg->value == CPENS (0, C7, C6, 5)
4708 || reg->value == CPENS (0, C7, C6, 6)
4709 || reg->value == CPENS (0, C7, C10, 6)
4710 || reg->value == CPENS (0, C7, C14, 6)
4711 || reg->value == CPENS (3, C7, C10, 5)
4712 || reg->value == CPENS (3, C7, C12, 5)
4713 || reg->value == CPENS (3, C7, C13, 5)
4714 || reg->value == CPENS (3, C7, C14, 5)
4715 || reg->value == CPENS (3, C7, C4, 4))
4716 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4717 return FALSE;
4718
63511907
MW		 4719 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4720 if ((reg->value == CPENS (0, C7, C9, 0)
4721 || reg->value == CPENS (0, C7, C9, 1))
4722 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4723 return FALSE;
4724
2ac435d4
SD		 4725 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4726 if (reg->value == CPENS (3, C7, C3, 0)
4727 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4728 return FALSE;
4729
d6bf7ce6
MW		 4730 return TRUE;
4731}
4732
a06ea964
NC		 4733#undef C0
4734#undef C1
4735#undef C2
4736#undef C3
4737#undef C4
4738#undef C5
4739#undef C6
4740#undef C7
4741#undef C8
4742#undef C9
4743#undef C10
4744#undef C11
4745#undef C12
4746#undef C13
4747#undef C14
4748#undef C15
4749
4bd13cde
NC		 4750#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4751#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4752
755b748f
TC		 4753static enum err_type
4754verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4755 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4756 bfd_boolean encoding ATTRIBUTE_UNUSED,
4757 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4758 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4759{
4760 int t = BITS (insn, 4, 0);
4761 int n = BITS (insn, 9, 5);
4762 int t2 = BITS (insn, 14, 10);
4763
4764 if (BIT (insn, 23))
4765 {
4766 /* Write back enabled. */
4767 if ((t == n || t2 == n) && n != 31)
755b748f 4768 return ERR_UND;
4bd13cde
NC		 4769 }
4770
4771 if (BIT (insn, 22))
4772 {
4773 /* Load */
4774 if (t == t2)
755b748f 4775 return ERR_UND;
4bd13cde
NC		 4776 }
4777
755b748f 4778 return ERR_OK;
4bd13cde
NC		 4779}
4780
6456d318
TC		 4781/* Verifier for vector by element 3 operands functions where the
4782 conditions `if sz:L == 11 then UNDEFINED` holds. */
4783
4784static enum err_type
4785verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4786 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4787 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4788 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4789{
4790 const aarch64_insn undef_pattern = 0x3;
4791 aarch64_insn value;
4792
4793 assert (inst->opcode);
4794 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4795 value = encoding ? inst->value : insn;
4796 assert (value);
4797
4798 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4799 return ERR_UND;
4800
4801 return ERR_OK;
4802}
4803
a68f4cd2
TC		 4804/* Initialize an instruction sequence insn_sequence with the instruction INST.
4805 If INST is NULL the given insn_sequence is cleared and the sequence is left
4806 uninitialized. */
4807
4808void
4809init_insn_sequence (const struct aarch64_inst *inst,
4810 aarch64_instr_sequence *insn_sequence)
4811{
4812 int num_req_entries = 0;
4813 insn_sequence->next_insn = 0;
4814 insn_sequence->num_insns = num_req_entries;
4815 if (insn_sequence->instr)
4816 XDELETE (insn_sequence->instr);
4817 insn_sequence->instr = NULL;
4818
4819 if (inst)
4820 {
4821 insn_sequence->instr = XNEW (aarch64_inst);
4822 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4823 }
4824
4825 /* Handle all the cases here. May need to think of something smarter than
4826 a giant if/else chain if this grows. At that time, a lookup table may be
4827 best. */
4828 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4829 num_req_entries = 1;
4830
4831 if (insn_sequence->current_insns)
4832 XDELETEVEC (insn_sequence->current_insns);
4833 insn_sequence->current_insns = NULL;
4834
4835 if (num_req_entries != 0)
4836 {
4837 size_t size = num_req_entries * sizeof (aarch64_inst);
4838 insn_sequence->current_insns
4839 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4840 memset (insn_sequence->current_insns, 0, size);
4841 }
4842}
4843
4844
4845/* This function verifies that the instruction INST adheres to its specified
4846 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4847 returned and MISMATCH_DETAIL contains the reason why verification failed.
4848
4849 The function is called both during assembly and disassembly. If assembling
4850 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4851 and will contain the PC of the current instruction w.r.t to the section.
4852
4853 If ENCODING and PC=0 then you are at a start of a section. The constraints
4854 are verified against the given state insn_sequence which is updated as it
4855 transitions through the verification. */
4856
4857enum err_type
4858verify_constraints (const struct aarch64_inst *inst,
4859 const aarch64_insn insn ATTRIBUTE_UNUSED,
4860 bfd_vma pc,
4861 bfd_boolean encoding,
4862 aarch64_operand_error *mismatch_detail,
4863 aarch64_instr_sequence *insn_sequence)
4864{
4865 assert (inst);
4866 assert (inst->opcode);
4867
4868 const struct aarch64_opcode *opcode = inst->opcode;
4869 if (!opcode->constraints && !insn_sequence->instr)
4870 return ERR_OK;
4871
4872 assert (insn_sequence);
4873
4874 enum err_type res = ERR_OK;
4875
4876 /* This instruction puts a constraint on the insn_sequence. */
4877 if (opcode->flags & F_SCAN)
4878 {
4879 if (insn_sequence->instr)
4880 {
4881 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4882 mismatch_detail->error = _("instruction opens new dependency "
4883 "sequence without ending previous one");
4884 mismatch_detail->index = -1;
4885 mismatch_detail->non_fatal = TRUE;
4886 res = ERR_VFI;
4887 }
4888
4889 init_insn_sequence (inst, insn_sequence);
4890 return res;
4891 }
4892
4893 /* Verify constraints on an existing sequence. */
4894 if (insn_sequence->instr)
4895 {
4896 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4897 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4898 closed a previous one that we should have. */
4899 if (!encoding && pc == 0)
4900 {
4901 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4902 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4903 mismatch_detail->index = -1;
4904 mismatch_detail->non_fatal = TRUE;
4905 res = ERR_VFI;
4906 /* Reset the sequence. */
4907 init_insn_sequence (NULL, insn_sequence);
4908 return res;
4909 }
4910
4911 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4912 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4913 {
4914 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4915 instruction for better error messages. */
5cd99750
MM		 4916 if (!opcode->avariant
4917 || !(*opcode->avariant &
4918 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 4919 {
4920 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4921 mismatch_detail->error = _("SVE instruction expected after "
4922 "`movprfx'");
4923 mismatch_detail->index = -1;
4924 mismatch_detail->non_fatal = TRUE;
4925 res = ERR_VFI;
4926 goto done;
4927 }
4928
4929 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4930 instruction that is allowed to be used with a MOVPRFX. */
4931 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4932 {
4933 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4934 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4935 "expected");
4936 mismatch_detail->index = -1;
4937 mismatch_detail->non_fatal = TRUE;
4938 res = ERR_VFI;
4939 goto done;
4940 }
4941
4942 /* Next check for usage of the predicate register. */
4943 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4944 aarch64_opnd_info blk_pred, inst_pred;
4945 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4946 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4947 bfd_boolean predicated = FALSE;
4948 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4949
4950 /* Determine if the movprfx instruction used is predicated or not. */
4951 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4952 {
4953 predicated = TRUE;
4954 blk_pred = insn_sequence->instr->operands[1];
4955 }
4956
4957 unsigned char max_elem_size = 0;
4958 unsigned char current_elem_size;
4959 int num_op_used = 0, last_op_usage = 0;
4960 int i, inst_pred_idx = -1;
4961 int num_ops = aarch64_num_of_operands (opcode);
4962 for (i = 0; i < num_ops; i++)
4963 {
4964 aarch64_opnd_info inst_op = inst->operands[i];
4965 switch (inst_op.type)
4966 {
4967 case AARCH64_OPND_SVE_Zd:
4968 case AARCH64_OPND_SVE_Zm_5:
4969 case AARCH64_OPND_SVE_Zm_16:
4970 case AARCH64_OPND_SVE_Zn:
4971 case AARCH64_OPND_SVE_Zt:
4972 case AARCH64_OPND_SVE_Vm:
4973 case AARCH64_OPND_SVE_Vn:
4974 case AARCH64_OPND_Va:
4975 case AARCH64_OPND_Vn:
4976 case AARCH64_OPND_Vm:
4977 case AARCH64_OPND_Sn:
4978 case AARCH64_OPND_Sm:
a68f4cd2
TC		 4979 if (inst_op.reg.regno == blk_dest.reg.regno)
4980 {
4981 num_op_used++;
4982 last_op_usage = i;
4983 }
4984 current_elem_size
4985 = aarch64_get_qualifier_esize (inst_op.qualifier);
4986 if (current_elem_size > max_elem_size)
4987 max_elem_size = current_elem_size;
4988 break;
4989 case AARCH64_OPND_SVE_Pd:
4990 case AARCH64_OPND_SVE_Pg3:
4991 case AARCH64_OPND_SVE_Pg4_5:
4992 case AARCH64_OPND_SVE_Pg4_10:
4993 case AARCH64_OPND_SVE_Pg4_16:
4994 case AARCH64_OPND_SVE_Pm:
4995 case AARCH64_OPND_SVE_Pn:
4996 case AARCH64_OPND_SVE_Pt:
4997 inst_pred = inst_op;
4998 inst_pred_idx = i;
4999 break;
5000 default:
5001 break;
5002 }
5003 }
5004
5005 assert (max_elem_size != 0);
5006 aarch64_opnd_info inst_dest = inst->operands[0];
5007 /* Determine the size that should be used to compare against the
5008 movprfx size. */
5009 current_elem_size
5010 = opcode->constraints & C_MAX_ELEM
5011 ? max_elem_size
5012 : aarch64_get_qualifier_esize (inst_dest.qualifier);
5013
5014 /* If movprfx is predicated do some extra checks. */
5015 if (predicated)
5016 {
5017 /* The instruction must be predicated. */
5018 if (inst_pred_idx < 0)
5019 {
5020 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5021 mismatch_detail->error = _("predicated instruction expected "
5022 "after `movprfx'");
5023 mismatch_detail->index = -1;
5024 mismatch_detail->non_fatal = TRUE;
5025 res = ERR_VFI;
5026 goto done;
5027 }
5028
5029 /* The instruction must have a merging predicate. */
5030 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
5031 {
5032 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5033 mismatch_detail->error = _("merging predicate expected due "
5034 "to preceding `movprfx'");
5035 mismatch_detail->index = inst_pred_idx;
5036 mismatch_detail->non_fatal = TRUE;
5037 res = ERR_VFI;
5038 goto done;
5039 }
5040
5041 /* The same register must be used in instruction. */
5042 if (blk_pred.reg.regno != inst_pred.reg.regno)
5043 {
5044 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5045 mismatch_detail->error = _("predicate register differs "
5046 "from that in preceding "
5047 "`movprfx'");
5048 mismatch_detail->index = inst_pred_idx;
5049 mismatch_detail->non_fatal = TRUE;
5050 res = ERR_VFI;
5051 goto done;
5052 }
5053 }
5054
5055 /* Destructive operations by definition must allow one usage of the
5056 same register. */
5057 int allowed_usage
5058 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5059
5060 /* Operand is not used at all. */
5061 if (num_op_used == 0)
5062 {
5063 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5064 mismatch_detail->error = _("output register of preceding "
5065 "`movprfx' not used in current "
5066 "instruction");
5067 mismatch_detail->index = 0;
5068 mismatch_detail->non_fatal = TRUE;
5069 res = ERR_VFI;
5070 goto done;
5071 }
5072
5073 /* We now know it's used, now determine exactly where it's used. */
5074 if (blk_dest.reg.regno != inst_dest.reg.regno)
5075 {
5076 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5077 mismatch_detail->error = _("output register of preceding "
5078 "`movprfx' expected as output");
5079 mismatch_detail->index = 0;
5080 mismatch_detail->non_fatal = TRUE;
5081 res = ERR_VFI;
5082 goto done;
5083 }
5084
5085 /* Operand used more than allowed for the specific opcode type. */
5086 if (num_op_used > allowed_usage)
5087 {
5088 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5089 mismatch_detail->error = _("output register of preceding "
5090 "`movprfx' used as input");
5091 mismatch_detail->index = last_op_usage;
5092 mismatch_detail->non_fatal = TRUE;
5093 res = ERR_VFI;
5094 goto done;
5095 }
5096
5097 /* Now the only thing left is the qualifiers checks. The register
5098 must have the same maximum element size. */
5099 if (inst_dest.qualifier
5100 && blk_dest.qualifier
5101 && current_elem_size
5102 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5103 {
5104 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5105 mismatch_detail->error = _("register size not compatible with "
5106 "previous `movprfx'");
5107 mismatch_detail->index = 0;
5108 mismatch_detail->non_fatal = TRUE;
5109 res = ERR_VFI;
5110 goto done;
5111 }
5112 }
5113
5114done:
5115 /* Add the new instruction to the sequence. */
5116 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5117 inst, sizeof (aarch64_inst));
5118
5119 /* Check if sequence is now full. */
5120 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5121 {
5122 /* Sequence is full, but we don't have anything special to do for now,
5123 so clear and reset it. */
5124 init_insn_sequence (NULL, insn_sequence);
5125 }
5126 }
5127
5128 return res;
5129}
5130
5131
e950b345
RS		 5132/* Return true if VALUE cannot be moved into an SVE register using DUP
5133 (with any element size, not just ESIZE) and if using DUPM would
5134 therefore be OK. ESIZE is the number of bytes in the immediate. */
5135
5136bfd_boolean
5137aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5138{
5139 int64_t svalue = uvalue;
5140 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5141
5142 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5143 return FALSE;
5144 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5145 {
5146 svalue = (int32_t) uvalue;
5147 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5148 {
5149 svalue = (int16_t) uvalue;
5150 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5151 return FALSE;
5152 }
5153 }
5154 if ((svalue & 0xff) == 0)
5155 svalue /= 256;
5156 return svalue < -128 || svalue >= 128;
5157}
5158
a06ea964
NC		 5159/* Include the opcode description table as well as the operand description
5160 table. */
20f55f38 5161#define VERIFIER(x) verify_##x
a06ea964 5162#include "aarch64-tbl.h"
GDB Binutils - Deliverables
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