projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix array overruns in the S12Z disassembler.
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
73cd51e5
AV		 358/* MVE opcodes. */
359
360struct mopcode32
361{
362 arm_feature_set arch; /* Architecture defining this insn. */
363 enum mve_instructions mve_op; /* Specific mve instruction for faster
364 decoding. */
365 unsigned long value; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask; /* Recognise insn if (op & mask) == value. */
367 const char * assembler; /* How to disassemble this insn. */
368};
369
6b0dd094
AV		 370enum isa {
371 ANY,
372 T32,
373 ARM
374};
375
376
377/* Shared (between Arm and Thumb mode) opcode. */
378struct sopcode32
379{
380 enum isa isa; /* Execution mode instruction availability. */
381 arm_feature_set arch; /* Architecture defining this insn. */
382 unsigned long value; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask; /* Recognise insn if (op & mask) == value. */
384 const char * assembler; /* How to disassemble this insn. */
385};
386
6b5d3a4d
ZW		 387struct opcode16
388{
823d2571 389 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 390 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 391 const char *assembler; /* How to disassemble this insn. */
392};
b7693d02 393
8f06b2d8 394/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 395
2fbad815 396 %% %
4a5329c6 397
c22aaad1 398 %c print condition code (always bits 28-31 in ARM mode)
37b37b2d 399 %q print shifter argument
e2efe87d
MGD		 400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
4a5329c6 402 %A print address for ldc/stc/ldf/stf instruction
16980d0b 403 %B print vstm/vldm register list
efd6b359 404 %C print vscclrm register list
4a5329c6 405 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
4a5329c6
ZW		 408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
412
33399f07 413 %<bitfield>c print as a condition code (for vsel)
4a5329c6 414 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 417 %<bitfield>d print the bitfield in decimal
16980d0b 418 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
4a5329c6
ZW		 423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
c28eeff2 428 %<bitfield>V print as a NEON D or Q register
6f1c2142 429 %<bitfield>E print a quarter-float immediate value
4a5329c6 430
16980d0b 431 %y<code> print a single precision VFP reg.
2fbad815 432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 433 %z<code> print a double precision VFP reg
2fbad815 434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 435
16980d0b
JB		 436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
43e65147 439
2fbad815 440 %L print as an iWMMXt N/M width field.
4a5329c6 441 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 442 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 443 versions.
444 %i print 5-bit immediate in bits 8,3..0
445 (print "32" when 0)
fe56b6ce 446 %r print register offset address for wldt/wstr instruction. */
2fbad815 447
21d799b5 448enum opcode_sentinel_enum
05413229
NC		 449{
450 SENTINEL_IWMMXT_START = 1,
451 SENTINEL_IWMMXT_END,
452 SENTINEL_GENERIC_START
453} opcode_sentinels;
454
aefd8a40 455#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 456#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 458#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 459
8f06b2d8 460/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 461
6b0dd094 462static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 463{
2fbad815 464 /* XScale instructions. */
6b0dd094 465 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 468 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 471 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 473 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 475 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 477
2fbad815 478 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 479 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
480 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 482 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 484 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 486 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 488 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 490 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 492 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 494 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 496 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 498 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 500 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 502 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 504 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 506 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 508 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 510 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 512 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 514 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 516 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 518 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 520 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 522 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 524 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 526 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 528 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 530 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 532 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 534 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 536 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 538 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 542 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 544 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 552 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 633 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 634
fe56b6ce 635 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 644 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 646 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 648 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 712 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 714 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 722
efd6b359
AV		 723 /* Armv8.1-M Mainline instructions. */
724 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
728
16a1fa25 729 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 730 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 732 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
734
fe56b6ce 735 /* Register load/store. */
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 768 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 772
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 781
fe56b6ce 782 /* Data transfer between ARM and NEON registers. */
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 797 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 799 /* Half-precision conversion instructions. */
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 802 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 804 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 806 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 808
fe56b6ce 809 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 810 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
ba6cd17f 812 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 814 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
ba6cd17f
SD		 828 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
ba6cd17f 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
823d2571 841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 842 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
ba6cd17f
SD		 856 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY, ARM_FEATURE_COPROC (FPU_MVE),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 874 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 876 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 878 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 888 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 892 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 894 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 908 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 910 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 912 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 914 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 920 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 922 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 936 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 938 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 940 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 942 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 968
969 /* Cirrus coprocessor instructions. */
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1048 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1142
62f3b8c8 1143 /* VFP Fused multiply add instructions. */
6b0dd094 1144 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1146 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1148 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1150 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1152 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1154 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1156 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1158 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1160
33399f07 1161 /* FP v5. */
6b0dd094 1162 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1164 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1166 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1168 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1170 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1172 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1174 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1176 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1178 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1180 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1182 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1184 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1186
05413229 1187 /* Generic coprocessor instructions. */
6b0dd094
AV		 1188 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
1189 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571 1190 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
6b0dd094 1191 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
823d2571
TG		 1192 0x0c500000, 0x0ff00000,
1193 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1194 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1195 0x0e000000, 0x0f000010,
1196 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1197 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1198 0x0e10f010, 0x0f10f010,
1199 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1200 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1201 0x0e100010, 0x0f100010,
1202 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1203 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571
TG		 1204 0x0e000010, 0x0f100010,
1205 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1206 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1207 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1208 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
823d2571 1209 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
2fbad815 1210
05413229 1211 /* V6 coprocessor instructions. */
6b0dd094 1212 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1213 0xfc500000, 0xfff00000,
1214 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
6b0dd094 1215 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
823d2571
TG		 1216 0xfc400000, 0xfff00000,
1217 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
8f06b2d8 1218
c28eeff2 1219 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1220 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1221 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1222 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1223 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1224 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1225 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1226 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1227 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1228 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1229 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1230 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1231 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1232 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1233 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1234 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1235 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1236 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1237 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1238 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1239 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1240
c604a79a 1241 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1242 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1243 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1244 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a
JW		 1245 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1246
dec41383 1247 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1248 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1249 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1250 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1251 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1252 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1253 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1254 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1255 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1256 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1257 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1258 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1259 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1260 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1261 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1263 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1264
05413229 1265 /* V5 coprocessor instructions. */
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1267 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571 1269 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1271 0xfe000000, 0xff000010,
1272 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1274 0xfe000010, 0xff100010,
1275 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
823d2571
TG		 1277 0xfe100010, 0xff100010,
1278 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1279
b0c11777
RL		 1280 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1281 cp_num: bit <11:8> == 0b1001.
1282 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1284 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1286 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1288 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1289 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1290 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1292 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1293 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1294 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1295 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1296 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1297 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1298 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1299 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1300 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1302 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1304 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1306 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1308 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1310 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1312 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1314 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1316 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1317 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1318 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1319 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1320 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1322 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1324 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1326 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1328 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1330 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1332 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1334 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1336 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1338 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1340 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1342 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1344 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1346 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1348 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1350 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1352 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1353
49e8a725 1354 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1356 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1357
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1359};
1360
16980d0b
JB		 1361/* Neon opcode table: This does not encode the top byte -- that is
1362 checked by the print_insn_neon routine, as it depends on whether we are
1363 doing thumb32 or arm32 disassembly. */
1364
1365/* print_insn_neon recognizes the following format control codes:
1366
1367 %% %
1368
c22aaad1 1369 %c print condition code
e2efe87d
MGD		 1370 %u print condition code (unconditional in ARM mode,
1371 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1372 %A print v{st,ld}[1234] operands
1373 %B print v{st,ld}[1234] any one operands
1374 %C print v{st,ld}[1234] single->all operands
1375 %D print scalar
1376 %E print vmov, vmvn, vorr, vbic encoded constant
1377 %F print vtbl,vtbx register list
1378
1379 %<bitfield>r print as an ARM register
1380 %<bitfield>d print the bitfield in decimal
1381 %<bitfield>e print the 2^N - bitfield in decimal
1382 %<bitfield>D print as a NEON D register
1383 %<bitfield>Q print as a NEON Q register
1384 %<bitfield>R print as a NEON D or Q register
1385 %<bitfield>Sn print byte scaled width limited by n
1386 %<bitfield>Tn print short scaled width limited by n
1387 %<bitfield>Un print long scaled width limited by n
43e65147 1388
16980d0b
JB		 1389 %<bitfield>'c print specified char iff bitfield is all ones
1390 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1391 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1392
1393static const struct opcode32 neon_opcodes[] =
1394{
fe56b6ce 1395 /* Extract. */
823d2571
TG		 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397 0xf2b00840, 0xffb00850,
1398 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1400 0xf2b00000, 0xffb00810,
1401 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1402
9743db03
AV		 1403 /* Data transfer between ARM and NEON registers. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1413 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1415 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1416
fe56b6ce 1417 /* Move data element to all lanes. */
823d2571
TG		 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1419 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1421 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1423 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1424
fe56b6ce 1425 /* Table lookup. */
823d2571
TG		 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1427 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1429 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1430
8e79c3df 1431 /* Half-precision conversions. */
823d2571
TG		 1432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1433 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1435 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1436
1437 /* NEON fused multiply add instructions. */
823d2571 1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1439 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1441 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1443 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1445 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1446
fe56b6ce 1447 /* Two registers, miscellaneous. */
823d2571
TG		 1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1449 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1451 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1453 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1455 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1457 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1459 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1460 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1461 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1462 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1463 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1465 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1467 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1469 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1481 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1483 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1485 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1491 0xf3b20300, 0xffb30fd0,
1492 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1496 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1500 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1520 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1522 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1524 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1526 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1532 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1534 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1538 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1540 0xf3bb0600, 0xffbf0e10,
823d2571 1541 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1543 0xf3b70600, 0xffbf0e10,
1544 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1545
fe56b6ce 1546 /* Three registers of the same length. */
823d2571
TG		 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1548 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1550 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1552 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1553 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1554 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1556 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1558 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1560 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1562 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1564 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1566 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1568 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1570 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1574 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1576 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1578 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1584 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1586 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1588 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1590 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1592 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1594 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1596 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1598 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1600 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1602 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1604 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1606 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1608 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1610 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1612 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1614 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1618 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1622 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1624 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1626 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1628 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1630 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1632 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1634 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1636 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1638 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1640 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1642 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1644 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1646 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1648 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1650 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1652 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1654 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1656 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664 0xf2000b00, 0xff800f10,
1665 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1667 0xf2000b10, 0xff800f10,
1668 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676 0xf3000b00, 0xff800f10,
1677 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1679 0xf2000000, 0xfe800f10,
1680 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682 0xf2000010, 0xfe800f10,
1683 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000100, 0xfe800f10,
1686 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688 0xf2000200, 0xfe800f10,
1689 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2000210, 0xfe800f10,
1692 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2000300, 0xfe800f10,
1695 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf2000310, 0xfe800f10,
1698 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf2000400, 0xfe800f10,
1701 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1703 0xf2000410, 0xfe800f10,
1704 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1706 0xf2000500, 0xfe800f10,
1707 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1709 0xf2000510, 0xfe800f10,
1710 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1712 0xf2000600, 0xfe800f10,
1713 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1715 0xf2000610, 0xfe800f10,
1716 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1718 0xf2000700, 0xfe800f10,
1719 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1721 0xf2000710, 0xfe800f10,
1722 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1724 0xf2000910, 0xfe800f10,
1725 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1727 0xf2000a00, 0xfe800f10,
1728 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1730 0xf2000a10, 0xfe800f10,
1731 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1733 0xf3000b10, 0xff800f10,
1734 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1736 0xf3000c10, 0xff800f10,
1737 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1738
fe56b6ce 1739 /* One register and an immediate value. */
823d2571
TG		 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1741 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1743 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1745 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1747 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1749 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1751 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1753 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1755 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1757 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1759 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1761 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1763 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1765 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1766
fe56b6ce 1767 /* Two registers and a shift amount. */
823d2571
TG		 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1769 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1771 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2880950, 0xfeb80fd0,
1780 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1786 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1788 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1798 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2900950, 0xfeb00fd0,
1803 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1807 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1813 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1819 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1825 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1831 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1837 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1843 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2a00950, 0xfea00fd0,
1848 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1852 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1854 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1882 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2a00e10, 0xfea00e90,
1887 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 1888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1889 0xf2a00c10, 0xfea00e90,
1890 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 1891
fe56b6ce 1892 /* Three registers of different lengths. */
823d2571
TG		 1893 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1894 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1896 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1898 0xf2800400, 0xff800f50,
1899 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2800600, 0xff800f50,
1902 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2800900, 0xff800f50,
1905 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf2800b00, 0xff800f50,
1908 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf2800d00, 0xff800f50,
1911 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf3800400, 0xff800f50,
1914 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf3800600, 0xff800f50,
1917 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1919 0xf2800000, 0xfe800f50,
1920 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2800100, 0xfe800f50,
1923 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2800200, 0xfe800f50,
1926 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2800300, 0xfe800f50,
1929 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2800500, 0xfe800f50,
1932 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2800700, 0xfe800f50,
1935 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2800800, 0xfe800f50,
1938 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf2800a00, 0xfe800f50,
1941 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf2800c00, 0xfe800f50,
1944 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 1945
fe56b6ce 1946 /* Two registers and a scalar. */
823d2571
TG		 1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1950 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1951 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1952 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1958 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1960 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1964 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1966 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1968 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1978 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1979 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1980 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1984 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1986 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 1990 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1992 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf2800240, 0xfe800f50,
1999 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2800640, 0xfe800f50,
2002 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf2800a40, 0xfe800f50,
2005 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2007 0xf2800e40, 0xff800f50,
2008 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2010 0xf2800f40, 0xff800f50,
2011 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2013 0xf3800e40, 0xff800f50,
2014 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2016 0xf3800f40, 0xff800f50,
2017 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2018 },
16980d0b 2019
fe56b6ce 2020 /* Element and structure load/store. */
823d2571
TG		 2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2026 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2032 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2038 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2044 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2050 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2056 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2059
2060 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2061};
2062
73cd51e5
AV		 2063/* mve opcode table. */
2064
2065/* print_insn_mve recognizes the following format control codes:
2066
2067 %% %
2068
ef1576a1
AV		 2069 %a print '+' or '-' or imm offset in vldr[bhwd] and
2070 vstr[bhwd]
9743db03 2071 %c print condition code
aef6d006
AV		 2072 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2073 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2074 %i print MVE predicate(s) for vpt and vpst
23d00a41 2075 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2076 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2077 %m print rounding mode for vcvt and vrint
143275ea 2078 %n print vector comparison code for predicated instruction
bf0b396d 2079 %s print size for various vcvt instructions
143275ea
AV		 2080 %v print vector predicate for instruction in predicated
2081 block
ef1576a1 2082 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2083 %w print writeback mode for MVE v{st,ld}[24]
2084 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2085 %E print vmov, vmvn, vorr, vbic encoded constant
2086 %N print generic index for vmov
14925797 2087 %T print bottom ('b') or top ('t') of source register
d3b63143 2088 %X print exchange field in vmla* instructions
04d54ace 2089
9743db03 2090 %<bitfield>r print as an ARM register
04d54ace 2091 %<bitfield>d print the bitfield in decimal
d3b63143 2092 %<bitfield>A print accumulate or not
e39c1607
SD		 2093 %<bitfield>c print bitfield as a condition code
2094 %<bitfield>C print bitfield as an inverted condition code
143275ea 2095 %<bitfield>Q print as a MVE Q register
c507f10b 2096 %<bitfield>F print as a MVE S register
143275ea
AV		 2097 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2098 UNPREDICTABLE
23d00a41
SD		 2099
2100 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2101 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2102 %<bitfield>I print carry flag or not
ef1576a1 2103 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2104 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2105 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2106 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2107 %<bitfield>o print rotate value for vcmul
1c8f2df8 2108 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2109 %<bitfield>x print the bitfield in hex.
1c8f2df8 2110 */
73cd51e5
AV		 2111
2112static const struct mopcode32 mve_opcodes[] =
2113{
143275ea
AV		 2114 /* MVE. */
2115
2116 {ARM_FEATURE_COPROC (FPU_MVE),
2117 MVE_VPST,
2118 0xfe310f4d, 0xffbf1fff,
2119 "vpst%i"
2120 },
2121
2122 /* Floating point VPT T1. */
2123 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2124 MVE_VPT_FP_T1,
2125 0xee310f00, 0xefb10f50,
2126 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2127 /* Floating point VPT T2. */
2128 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2129 MVE_VPT_FP_T2,
2130 0xee310f40, 0xefb10f50,
2131 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2132
2133 /* Vector VPT T1. */
2134 {ARM_FEATURE_COPROC (FPU_MVE),
2135 MVE_VPT_VEC_T1,
2136 0xfe010f00, 0xff811f51,
2137 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2138 /* Vector VPT T2. */
2139 {ARM_FEATURE_COPROC (FPU_MVE),
2140 MVE_VPT_VEC_T2,
2141 0xfe010f01, 0xff811f51,
2142 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2143 /* Vector VPT T3. */
2144 {ARM_FEATURE_COPROC (FPU_MVE),
2145 MVE_VPT_VEC_T3,
2146 0xfe011f00, 0xff811f50,
2147 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2148 /* Vector VPT T4. */
2149 {ARM_FEATURE_COPROC (FPU_MVE),
2150 MVE_VPT_VEC_T4,
2151 0xfe010f40, 0xff811f70,
2152 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2153 /* Vector VPT T5. */
2154 {ARM_FEATURE_COPROC (FPU_MVE),
2155 MVE_VPT_VEC_T5,
2156 0xfe010f60, 0xff811f70,
2157 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2158 /* Vector VPT T6. */
2159 {ARM_FEATURE_COPROC (FPU_MVE),
2160 MVE_VPT_VEC_T6,
2161 0xfe011f40, 0xff811f50,
2162 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2163
c507f10b
AV		 2164 /* Vector VBIC immediate. */
2165 {ARM_FEATURE_COPROC (FPU_MVE),
2166 MVE_VBIC_IMM,
2167 0xef800070, 0xefb81070,
2168 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2169
2170 /* Vector VBIC register. */
2171 {ARM_FEATURE_COPROC (FPU_MVE),
2172 MVE_VBIC_REG,
2173 0xef100150, 0xffb11f51,
2174 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2175
66dcaa5d
AV		 2176 /* Vector VABAV. */
2177 {ARM_FEATURE_COPROC (FPU_MVE),
2178 MVE_VABAV,
2179 0xee800f01, 0xefc10f51,
2180 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2181
2182 /* Vector VABD floating point. */
2183 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2184 MVE_VABD_FP,
2185 0xff200d40, 0xffa11f51,
2186 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2187
2188 /* Vector VABD. */
2189 {ARM_FEATURE_COPROC (FPU_MVE),
2190 MVE_VABD_VEC,
2191 0xef000740, 0xef811f51,
2192 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2193
2194 /* Vector VABS floating point. */
2195 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2196 MVE_VABS_FP,
2197 0xFFB10740, 0xFFB31FD1,
2198 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2199 /* Vector VABS. */
2200 {ARM_FEATURE_COPROC (FPU_MVE),
2201 MVE_VABS_VEC,
2202 0xffb10340, 0xffb31fd1,
2203 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2204
2205 /* Vector VADD floating point T1. */
2206 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2207 MVE_VADD_FP_T1,
2208 0xef000d40, 0xffa11f51,
2209 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2210 /* Vector VADD floating point T2. */
2211 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2212 MVE_VADD_FP_T2,
2213 0xee300f40, 0xefb11f70,
2214 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2215 /* Vector VADD T1. */
2216 {ARM_FEATURE_COPROC (FPU_MVE),
2217 MVE_VADD_VEC_T1,
2218 0xef000840, 0xff811f51,
2219 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2220 /* Vector VADD T2. */
2221 {ARM_FEATURE_COPROC (FPU_MVE),
2222 MVE_VADD_VEC_T2,
2223 0xee010f40, 0xff811f70,
2224 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2225
d3b63143
AV		 2226 /* Vector VADDLV. */
2227 {ARM_FEATURE_COPROC (FPU_MVE),
2228 MVE_VADDLV,
2229 0xee890f00, 0xef8f1fd1,
2230 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2231
2232 /* Vector VADDV. */
2233 {ARM_FEATURE_COPROC (FPU_MVE),
2234 MVE_VADDV,
2235 0xeef10f00, 0xeff31fd1,
2236 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2237
66dcaa5d
AV		 2238 /* Vector VADC. */
2239 {ARM_FEATURE_COPROC (FPU_MVE),
2240 MVE_VADC,
2241 0xee300f00, 0xffb10f51,
2242 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2243
e523f101
AV		 2244 /* Vector VAND. */
2245 {ARM_FEATURE_COPROC (FPU_MVE),
2246 MVE_VAND,
2247 0xef000150, 0xffb11f51,
2248 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2249
2250 /* Vector VBRSR register. */
2251 {ARM_FEATURE_COPROC (FPU_MVE),
2252 MVE_VBRSR,
2253 0xfe011e60, 0xff811f70,
2254 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2255
897b9bbc
AV		 2256 /* Vector VCADD floating point. */
2257 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2258 MVE_VCADD_FP,
2259 0xfc800840, 0xfea11f51,
2260 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2261
2262 /* Vector VCADD. */
2263 {ARM_FEATURE_COPROC (FPU_MVE),
2264 MVE_VCADD_VEC,
2265 0xfe000f00, 0xff810f51,
2266 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2267
e523f101
AV		 2268 /* Vector VCLS. */
2269 {ARM_FEATURE_COPROC (FPU_MVE),
2270 MVE_VCLS,
2271 0xffb00440, 0xffb31fd1,
2272 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2273
2274 /* Vector VCLZ. */
2275 {ARM_FEATURE_COPROC (FPU_MVE),
2276 MVE_VCLZ,
2277 0xffb004c0, 0xffb31fd1,
2278 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2279
897b9bbc
AV		 2280 /* Vector VCMLA. */
2281 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2282 MVE_VCMLA_FP,
2283 0xfc200840, 0xfe211f51,
2284 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2285
143275ea
AV		 2286 /* Vector VCMP floating point T1. */
2287 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2288 MVE_VCMP_FP_T1,
2289 0xee310f00, 0xeff1ef50,
2290 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2291
2292 /* Vector VCMP floating point T2. */
2293 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2294 MVE_VCMP_FP_T2,
2295 0xee310f40, 0xeff1ef50,
2296 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2297
2298 /* Vector VCMP T1. */
2299 {ARM_FEATURE_COPROC (FPU_MVE),
2300 MVE_VCMP_VEC_T1,
2301 0xfe010f00, 0xffc1ff51,
2302 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2303 /* Vector VCMP T2. */
2304 {ARM_FEATURE_COPROC (FPU_MVE),
2305 MVE_VCMP_VEC_T2,
2306 0xfe010f01, 0xffc1ff51,
2307 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2308 /* Vector VCMP T3. */
2309 {ARM_FEATURE_COPROC (FPU_MVE),
2310 MVE_VCMP_VEC_T3,
2311 0xfe011f00, 0xffc1ff50,
2312 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2313 /* Vector VCMP T4. */
2314 {ARM_FEATURE_COPROC (FPU_MVE),
2315 MVE_VCMP_VEC_T4,
2316 0xfe010f40, 0xffc1ff70,
2317 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2318 /* Vector VCMP T5. */
2319 {ARM_FEATURE_COPROC (FPU_MVE),
2320 MVE_VCMP_VEC_T5,
2321 0xfe010f60, 0xffc1ff70,
2322 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2323 /* Vector VCMP T6. */
2324 {ARM_FEATURE_COPROC (FPU_MVE),
2325 MVE_VCMP_VEC_T6,
2326 0xfe011f40, 0xffc1ff50,
2327 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2328
9743db03
AV		 2329 /* Vector VDUP. */
2330 {ARM_FEATURE_COPROC (FPU_MVE),
2331 MVE_VDUP,
2332 0xeea00b10, 0xffb10f5f,
2333 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2334
2335 /* Vector VEOR. */
2336 {ARM_FEATURE_COPROC (FPU_MVE),
2337 MVE_VEOR,
2338 0xff000150, 0xffd11f51,
2339 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340
2341 /* Vector VFMA, vector * scalar. */
2342 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2343 MVE_VFMA_FP_SCALAR,
2344 0xee310e40, 0xefb11f70,
2345 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2346
2347 /* Vector VFMA floating point. */
2348 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2349 MVE_VFMA_FP,
2350 0xef000c50, 0xffa11f51,
2351 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2352
2353 /* Vector VFMS floating point. */
2354 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2355 MVE_VFMS_FP,
2356 0xef200c50, 0xffa11f51,
2357 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
2359 /* Vector VFMAS, vector * scalar. */
2360 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2361 MVE_VFMAS_FP_SCALAR,
2362 0xee311e40, 0xefb11f70,
2363 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2364
2365 /* Vector VHADD T1. */
2366 {ARM_FEATURE_COPROC (FPU_MVE),
2367 MVE_VHADD_T1,
2368 0xef000040, 0xef811f51,
2369 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2370
2371 /* Vector VHADD T2. */
2372 {ARM_FEATURE_COPROC (FPU_MVE),
2373 MVE_VHADD_T2,
2374 0xee000f40, 0xef811f70,
2375 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2376
2377 /* Vector VHSUB T1. */
2378 {ARM_FEATURE_COPROC (FPU_MVE),
2379 MVE_VHSUB_T1,
2380 0xef000240, 0xef811f51,
2381 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2382
2383 /* Vector VHSUB T2. */
2384 {ARM_FEATURE_COPROC (FPU_MVE),
2385 MVE_VHSUB_T2,
2386 0xee001f40, 0xef811f70,
2387 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2388
897b9bbc
AV		 2389 /* Vector VCMUL. */
2390 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2391 MVE_VCMUL_FP,
2392 0xee300e00, 0xefb10f50,
2393 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2394
e523f101
AV		 2395 /* Vector VCTP. */
2396 {ARM_FEATURE_COPROC (FPU_MVE),
2397 MVE_VCTP,
2398 0xf000e801, 0xffc0ffff,
2399 "vctp%v.%20-21s\t%16-19r"},
2400
9743db03
AV		 2401 /* Vector VDUP. */
2402 {ARM_FEATURE_COPROC (FPU_MVE),
2403 MVE_VDUP,
2404 0xeea00b10, 0xffb10f5f,
2405 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2406
2407 /* Vector VRHADD. */
2408 {ARM_FEATURE_COPROC (FPU_MVE),
2409 MVE_VRHADD,
2410 0xef000140, 0xef811f51,
2411 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2412
bf0b396d
AV		 2413 /* Vector VCVT. */
2414 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2415 MVE_VCVT_FP_FIX_VEC,
2416 0xef800c50, 0xef801cd1,
2417 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2418
2419 /* Vector VCVT. */
2420 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2421 MVE_VCVT_BETWEEN_FP_INT,
2422 0xffb30640, 0xffb31e51,
2423 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2424
2425 /* Vector VCVT between single and half-precision float, bottom half. */
2426 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2427 MVE_VCVT_FP_HALF_FP,
2428 0xee3f0e01, 0xefbf1fd1,
2429 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2430
2431 /* Vector VCVT between single and half-precision float, top half. */
2432 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2433 MVE_VCVT_FP_HALF_FP,
2434 0xee3f1e01, 0xefbf1fd1,
2435 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2436
2437 /* Vector VCVT. */
2438 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2439 MVE_VCVT_FROM_FP_TO_INT,
2440 0xffb30040, 0xffb31c51,
2441 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2442
1c8f2df8
AV		 2443 /* Vector VDDUP. */
2444 {ARM_FEATURE_COPROC (FPU_MVE),
2445 MVE_VDDUP,
2446 0xee011f6e, 0xff811f7e,
2447 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2448
2449 /* Vector VDWDUP. */
2450 {ARM_FEATURE_COPROC (FPU_MVE),
2451 MVE_VDWDUP,
2452 0xee011f60, 0xff811f70,
2453 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2454
897b9bbc
AV		 2455 /* Vector VHCADD. */
2456 {ARM_FEATURE_COPROC (FPU_MVE),
2457 MVE_VHCADD,
2458 0xee000f00, 0xff810f51,
2459 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2460
1c8f2df8
AV		 2461 /* Vector VIWDUP. */
2462 {ARM_FEATURE_COPROC (FPU_MVE),
2463 MVE_VIWDUP,
2464 0xee010f60, 0xff811f70,
2465 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2466
2467 /* Vector VIDUP. */
2468 {ARM_FEATURE_COPROC (FPU_MVE),
2469 MVE_VIDUP,
2470 0xee010f6e, 0xff811f7e,
2471 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2472
04d54ace
AV		 2473 /* Vector VLD2. */
2474 {ARM_FEATURE_COPROC (FPU_MVE),
2475 MVE_VLD2,
2476 0xfc901e00, 0xff901e5f,
2477 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2478
2479 /* Vector VLD4. */
2480 {ARM_FEATURE_COPROC (FPU_MVE),
2481 MVE_VLD4,
2482 0xfc901e01, 0xff901e1f,
2483 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2484
ef1576a1
AV		 2485 /* Vector VLDRB gather load. */
2486 {ARM_FEATURE_COPROC (FPU_MVE),
2487 MVE_VLDRB_GATHER_T1,
2488 0xec900e00, 0xefb01e50,
2489 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2490
2491 /* Vector VLDRH gather load. */
2492 {ARM_FEATURE_COPROC (FPU_MVE),
2493 MVE_VLDRH_GATHER_T2,
2494 0xec900e10, 0xefb01e50,
2495 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2496
2497 /* Vector VLDRW gather load. */
2498 {ARM_FEATURE_COPROC (FPU_MVE),
2499 MVE_VLDRW_GATHER_T3,
2500 0xfc900f40, 0xffb01fd0,
2501 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2502
2503 /* Vector VLDRD gather load. */
2504 {ARM_FEATURE_COPROC (FPU_MVE),
2505 MVE_VLDRD_GATHER_T4,
2506 0xec900fd0, 0xefb01fd0,
2507 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2508
2509 /* Vector VLDRW gather load. */
2510 {ARM_FEATURE_COPROC (FPU_MVE),
2511 MVE_VLDRW_GATHER_T5,
2512 0xfd101e00, 0xff111f00,
2513 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2514
2515 /* Vector VLDRD gather load, variant T6. */
2516 {ARM_FEATURE_COPROC (FPU_MVE),
2517 MVE_VLDRD_GATHER_T6,
2518 0xfd101f00, 0xff111f00,
2519 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2520
aef6d006
AV		 2521 /* Vector VLDRB. */
2522 {ARM_FEATURE_COPROC (FPU_MVE),
2523 MVE_VLDRB_T1,
2524 0xec100e00, 0xee581e00,
2525 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2526
2527 /* Vector VLDRH. */
2528 {ARM_FEATURE_COPROC (FPU_MVE),
2529 MVE_VLDRH_T2,
2530 0xec180e00, 0xee581e00,
2531 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2532
2533 /* Vector VLDRB unsigned, variant T5. */
2534 {ARM_FEATURE_COPROC (FPU_MVE),
2535 MVE_VLDRB_T5,
2536 0xec101e00, 0xfe101f80,
2537 "vldrb%v.u8\t%13-15,22Q, %d"},
2538
2539 /* Vector VLDRH unsigned, variant T6. */
2540 {ARM_FEATURE_COPROC (FPU_MVE),
2541 MVE_VLDRH_T6,
2542 0xec101e80, 0xfe101f80,
2543 "vldrh%v.u16\t%13-15,22Q, %d"},
2544
2545 /* Vector VLDRW unsigned, variant T7. */
2546 {ARM_FEATURE_COPROC (FPU_MVE),
2547 MVE_VLDRW_T7,
2548 0xec101f00, 0xfe101f80,
2549 "vldrw%v.u32\t%13-15,22Q, %d"},
2550
56858bea
AV		 2551 /* Vector VMAX. */
2552 {ARM_FEATURE_COPROC (FPU_MVE),
2553 MVE_VMAX,
2554 0xef000640, 0xef811f51,
2555 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2556
2557 /* Vector VMAXA. */
2558 {ARM_FEATURE_COPROC (FPU_MVE),
2559 MVE_VMAXA,
2560 0xee330e81, 0xffb31fd1,
2561 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2562
2563 /* Vector VMAXNM floating point. */
2564 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2565 MVE_VMAXNM_FP,
2566 0xff000f50, 0xffa11f51,
2567 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2568
2569 /* Vector VMAXNMA floating point. */
2570 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2571 MVE_VMAXNMA_FP,
2572 0xee3f0e81, 0xefbf1fd1,
2573 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2574
2575 /* Vector VMAXNMV floating point. */
2576 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2577 MVE_VMAXNMV_FP,
2578 0xeeee0f00, 0xefff0fd1,
2579 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2580
2581 /* Vector VMAXNMAV floating point. */
2582 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2583 MVE_VMAXNMAV_FP,
2584 0xeeec0f00, 0xefff0fd1,
2585 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2586
2587 /* Vector VMAXV. */
2588 {ARM_FEATURE_COPROC (FPU_MVE),
2589 MVE_VMAXV,
2590 0xeee20f00, 0xeff30fd1,
2591 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2592
2593 /* Vector VMAXAV. */
2594 {ARM_FEATURE_COPROC (FPU_MVE),
2595 MVE_VMAXAV,
2596 0xeee00f00, 0xfff30fd1,
2597 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2598
2599 /* Vector VMIN. */
2600 {ARM_FEATURE_COPROC (FPU_MVE),
2601 MVE_VMIN,
2602 0xef000650, 0xef811f51,
2603 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2604
2605 /* Vector VMINA. */
2606 {ARM_FEATURE_COPROC (FPU_MVE),
2607 MVE_VMINA,
2608 0xee331e81, 0xffb31fd1,
2609 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2610
2611 /* Vector VMINNM floating point. */
2612 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2613 MVE_VMINNM_FP,
2614 0xff200f50, 0xffa11f51,
2615 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2616
2617 /* Vector VMINNMA floating point. */
2618 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2619 MVE_VMINNMA_FP,
2620 0xee3f1e81, 0xefbf1fd1,
2621 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2622
2623 /* Vector VMINNMV floating point. */
2624 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2625 MVE_VMINNMV_FP,
2626 0xeeee0f80, 0xefff0fd1,
2627 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2628
2629 /* Vector VMINNMAV floating point. */
2630 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2631 MVE_VMINNMAV_FP,
2632 0xeeec0f80, 0xefff0fd1,
2633 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2634
2635 /* Vector VMINV. */
2636 {ARM_FEATURE_COPROC (FPU_MVE),
2637 MVE_VMINV,
2638 0xeee20f80, 0xeff30fd1,
2639 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2640
2641 /* Vector VMINAV. */
2642 {ARM_FEATURE_COPROC (FPU_MVE),
2643 MVE_VMINAV,
2644 0xeee00f80, 0xfff30fd1,
2645 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2646
2647 /* Vector VMLA. */
2648 {ARM_FEATURE_COPROC (FPU_MVE),
2649 MVE_VMLA,
2650 0xee010e40, 0xef811f70,
2651 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2652
d3b63143
AV		 2653 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2654 opcode aliasing. */
2655 {ARM_FEATURE_COPROC (FPU_MVE),
2656 MVE_VMLALDAV,
2657 0xee801e00, 0xef801f51,
2658 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2659
2660 {ARM_FEATURE_COPROC (FPU_MVE),
2661 MVE_VMLALDAV,
2662 0xee800e00, 0xef801f51,
2663 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2664
2665 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2666 {ARM_FEATURE_COPROC (FPU_MVE),
2667 MVE_VMLADAV_T1,
2668 0xeef00e00, 0xeff01f51,
2669 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2670
2671 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2672 {ARM_FEATURE_COPROC (FPU_MVE),
2673 MVE_VMLADAV_T2,
2674 0xeef00f00, 0xeff11f51,
2675 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2676
2677 /* Vector VMLADAV T1 variant. */
2678 {ARM_FEATURE_COPROC (FPU_MVE),
2679 MVE_VMLADAV_T1,
2680 0xeef01e00, 0xeff01f51,
2681 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2682
2683 /* Vector VMLADAV T2 variant. */
2684 {ARM_FEATURE_COPROC (FPU_MVE),
2685 MVE_VMLADAV_T2,
2686 0xeef01f00, 0xeff11f51,
2687 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2688
2689 /* Vector VMLAS. */
2690 {ARM_FEATURE_COPROC (FPU_MVE),
2691 MVE_VMLAS,
2692 0xee011e40, 0xef811f70,
2693 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2694
2695 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2696 opcode aliasing. */
2697 {ARM_FEATURE_COPROC (FPU_MVE),
2698 MVE_VRMLSLDAVH,
2699 0xfe800e01, 0xff810f51,
2700 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2701
2702 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2703 opcdoe aliasing. */
2704 {ARM_FEATURE_COPROC (FPU_MVE),
2705 MVE_VMLSLDAV,
2706 0xee800e01, 0xff800f51,
2707 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2708
2709 /* Vector VMLSDAV T1 Variant. */
2710 {ARM_FEATURE_COPROC (FPU_MVE),
2711 MVE_VMLSDAV_T1,
2712 0xeef00e01, 0xfff00f51,
2713 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2714
2715 /* Vector VMLSDAV T2 Variant. */
2716 {ARM_FEATURE_COPROC (FPU_MVE),
2717 MVE_VMLSDAV_T2,
2718 0xfef00e01, 0xfff10f51,
2719 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2720
c507f10b
AV		 2721 /* Vector VMOV between gpr and half precision register, op == 0. */
2722 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2723 MVE_VMOV_HFP_TO_GP,
2724 0xee000910, 0xfff00f7f,
2725 "vmov.f16\t%7,16-19F, %12-15r"},
2726
2727 /* Vector VMOV between gpr and half precision register, op == 1. */
2728 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2729 MVE_VMOV_HFP_TO_GP,
2730 0xee100910, 0xfff00f7f,
2731 "vmov.f16\t%12-15r, %7,16-19F"},
2732
2733 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2734 MVE_VMOV_GP_TO_VEC_LANE,
2735 0xee000b10, 0xff900f1f,
2736 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2737
2738 /* Vector VORR immediate to vector.
2739 NOTE: MVE_VORR_IMM must appear in the table
2740 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2741 {ARM_FEATURE_COPROC (FPU_MVE),
2742 MVE_VORR_IMM,
2743 0xef800050, 0xefb810f0,
2744 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2745
ed63aa17
AV		 2746 /* Vector VQSHL T2 Variant.
2747 NOTE: MVE_VQSHL_T2 must appear in the table before
2748 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2749 {ARM_FEATURE_COPROC (FPU_MVE),
2750 MVE_VQSHL_T2,
2751 0xef800750, 0xef801fd1,
2752 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2753
2754 /* Vector VQSHLU T3 Variant
2755 NOTE: MVE_VQSHL_T2 must appear in the table before
2756 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2757
2758 {ARM_FEATURE_COPROC (FPU_MVE),
2759 MVE_VQSHLU_T3,
2760 0xff800650, 0xff801fd1,
2761 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2762
2763 /* Vector VRSHR
2764 NOTE: MVE_VRSHR must appear in the table before
2765 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2766 {ARM_FEATURE_COPROC (FPU_MVE),
2767 MVE_VRSHR,
2768 0xef800250, 0xef801fd1,
2769 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2770
2771 /* Vector VSHL.
2772 NOTE: MVE_VSHL must appear in the table before
2773 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2774 {ARM_FEATURE_COPROC (FPU_MVE),
2775 MVE_VSHL_T1,
2776 0xef800550, 0xff801fd1,
2777 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2778
2779 /* Vector VSHR
2780 NOTE: MVE_VSHR must appear in the table before
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE),
2783 MVE_VSHR,
2784 0xef800050, 0xef801fd1,
2785 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2786
2787 /* Vector VSLI
2788 NOTE: MVE_VSLI must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE),
2791 MVE_VSLI,
2792 0xff800550, 0xff801fd1,
2793 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2794
2795 /* Vector VSRI
2796 NOTE: MVE_VSRI must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798 {ARM_FEATURE_COPROC (FPU_MVE),
2799 MVE_VSRI,
2800 0xff800450, 0xff801fd1,
2801 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2802
c507f10b
AV		 2803 /* Vector VMOV immediate to vector,
2804 cmode == 11x1 -> VMVN which is UNDEFINED
2805 for such a cmode. */
2806 {ARM_FEATURE_COPROC (FPU_MVE),
2807 MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
2808
2809 /* Vector VMOV immediate to vector. */
2810 {ARM_FEATURE_COPROC (FPU_MVE),
2811 MVE_VMOV_IMM_TO_VEC,
2812 0xef800050, 0xefb810d0,
2813 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2814
2815 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2816 {ARM_FEATURE_COPROC (FPU_MVE),
2817 MVE_VMOV2_VEC_LANE_TO_GP,
2818 0xec000f00, 0xffb01ff0,
2819 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2820
2821 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2822 {ARM_FEATURE_COPROC (FPU_MVE),
2823 MVE_VMOV2_VEC_LANE_TO_GP,
2824 0xec000f10, 0xffb01ff0,
2825 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2826
2827 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2828 {ARM_FEATURE_COPROC (FPU_MVE),
2829 MVE_VMOV2_GP_TO_VEC_LANE,
2830 0xec100f00, 0xffb01ff0,
2831 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2832
2833 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2834 {ARM_FEATURE_COPROC (FPU_MVE),
2835 MVE_VMOV2_GP_TO_VEC_LANE,
2836 0xec100f10, 0xffb01ff0,
2837 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2838
2839 /* Vector VMOV Vector lane to gpr. */
2840 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2841 MVE_VMOV_VEC_LANE_TO_GP,
2842 0xee100b10, 0xff100f1f,
2843 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2844
ed63aa17
AV		 2845 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2846 to instruction opcode aliasing. */
2847 {ARM_FEATURE_COPROC (FPU_MVE),
2848 MVE_VSHLL_T1,
2849 0xeea00f40, 0xefa00fd1,
2850 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2851
14925797
AV		 2852 /* Vector VMOVL long. */
2853 {ARM_FEATURE_COPROC (FPU_MVE),
2854 MVE_VMOVL,
2855 0xeea00f40, 0xefa70fd1,
2856 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2857
2858 /* Vector VMOV and narrow. */
2859 {ARM_FEATURE_COPROC (FPU_MVE),
2860 MVE_VMOVN,
2861 0xfe310e81, 0xffb30fd1,
2862 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2863
c507f10b
AV		 2864 /* Floating point move extract. */
2865 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2866 MVE_VMOVX,
2867 0xfeb00a40, 0xffbf0fd0,
2868 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2869
f49bb598
AV		 2870 /* Vector VMUL floating-point T1 variant. */
2871 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2872 MVE_VMUL_FP_T1,
2873 0xff000d50, 0xffa11f51,
2874 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2875
2876 /* Vector VMUL floating-point T2 variant. */
2877 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2878 MVE_VMUL_FP_T2,
2879 0xee310e60, 0xefb11f70,
2880 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2881
2882 /* Vector VMUL T1 variant. */
2883 {ARM_FEATURE_COPROC (FPU_MVE),
2884 MVE_VMUL_VEC_T1,
2885 0xef000950, 0xff811f51,
2886 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2887
2888 /* Vector VMUL T2 variant. */
2889 {ARM_FEATURE_COPROC (FPU_MVE),
2890 MVE_VMUL_VEC_T2,
2891 0xee011e60, 0xff811f70,
2892 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2893
2894 /* Vector VMULH. */
2895 {ARM_FEATURE_COPROC (FPU_MVE),
2896 MVE_VMULH,
2897 0xee010e01, 0xef811f51,
2898 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2899
2900 /* Vector VRMULH. */
2901 {ARM_FEATURE_COPROC (FPU_MVE),
2902 MVE_VRMULH,
2903 0xee011e01, 0xef811f51,
2904 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2905
14925797
AV		 2906 /* Vector VMULL integer. */
2907 {ARM_FEATURE_COPROC (FPU_MVE),
2908 MVE_VMULL_INT,
2909 0xee010e00, 0xef810f51,
2910 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2911
2912 /* Vector VMULL polynomial. */
2913 {ARM_FEATURE_COPROC (FPU_MVE),
2914 MVE_VMULL_POLY,
2915 0xee310e00, 0xefb10f51,
2916 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2917
c507f10b
AV		 2918 /* Vector VMVN immediate to vector. */
2919 {ARM_FEATURE_COPROC (FPU_MVE),
2920 MVE_VMVN_IMM,
2921 0xef800070, 0xefb810f0,
2922 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2923
2924 /* Vector VMVN register. */
2925 {ARM_FEATURE_COPROC (FPU_MVE),
2926 MVE_VMVN_REG,
2927 0xffb005c0, 0xffbf1fd1,
2928 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2929
f49bb598
AV		 2930 /* Vector VNEG floating point. */
2931 {ARM_FEATURE_COPROC (FPU_MVE_FP),
2932 MVE_VNEG_FP,
2933 0xffb107c0, 0xffb31fd1,
2934 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2935
2936 /* Vector VNEG. */
2937 {ARM_FEATURE_COPROC (FPU_MVE),
2938 MVE_VNEG_VEC,
2939 0xffb103c0, 0xffb31fd1,
2940 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2941
c507f10b
AV		 2942 /* Vector VORN, vector bitwise or not. */
2943 {ARM_FEATURE_COPROC (FPU_MVE),
2944 MVE_VORN,
2945 0xef300150, 0xffb11f51,
2946 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2947
2948 /* Vector VORR register. */
2949 {ARM_FEATURE_COPROC (FPU_MVE),
2950 MVE_VORR_REG,
2951 0xef200150, 0xffb11f51,
2952 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2953
c4a23bf8
SP		 2954 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2955 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2956 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2957 array. */
2958
2959 {ARM_FEATURE_COPROC (FPU_MVE),
2960 MVE_VMOV_VEC_TO_VEC,
2961 0xef200150, 0xffb11f51,
2962 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2963
14925797
AV		 2964 /* Vector VQDMULL T1 variant. */
2965 {ARM_FEATURE_COPROC (FPU_MVE),
2966 MVE_VQDMULL_T1,
2967 0xee300f01, 0xefb10f51,
2968 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2969
14b456f2
AV		 2970 /* Vector VPNOT. */
2971 {ARM_FEATURE_COPROC (FPU_MVE),
2972 MVE_VPNOT,
2973 0xfe310f4d, 0xffffffff,
2974 "vpnot%v"},
2975
2976 /* Vector VPSEL. */
2977 {ARM_FEATURE_COPROC (FPU_MVE),
2978 MVE_VPSEL,
2979 0xfe310f01, 0xffb11f51,
2980 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2981
2982 /* Vector VQABS. */
2983 {ARM_FEATURE_COPROC (FPU_MVE),
2984 MVE_VQABS,
2985 0xffb00740, 0xffb31fd1,
2986 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2987
2988 /* Vector VQADD T1 variant. */
2989 {ARM_FEATURE_COPROC (FPU_MVE),
2990 MVE_VQADD_T1,
2991 0xef000050, 0xef811f51,
2992 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2993
2994 /* Vector VQADD T2 variant. */
2995 {ARM_FEATURE_COPROC (FPU_MVE),
2996 MVE_VQADD_T2,
2997 0xee000f60, 0xef811f70,
2998 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2999
14925797
AV		 3000 /* Vector VQDMULL T2 variant. */
3001 {ARM_FEATURE_COPROC (FPU_MVE),
3002 MVE_VQDMULL_T2,
3003 0xee300f60, 0xefb10f70,
3004 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3005
3006 /* Vector VQMOVN. */
3007 {ARM_FEATURE_COPROC (FPU_MVE),
3008 MVE_VQMOVN,
3009 0xee330e01, 0xefb30fd1,
3010 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3011
3012 /* Vector VQMOVUN. */
3013 {ARM_FEATURE_COPROC (FPU_MVE),
3014 MVE_VQMOVUN,
3015 0xee310e81, 0xffb30fd1,
3016 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3017
d3b63143
AV		 3018 /* Vector VQDMLADH. */
3019 {ARM_FEATURE_COPROC (FPU_MVE),
3020 MVE_VQDMLADH,
3021 0xee000e00, 0xff810f51,
3022 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3023
3024 /* Vector VQRDMLADH. */
3025 {ARM_FEATURE_COPROC (FPU_MVE),
3026 MVE_VQRDMLADH,
3027 0xee000e01, 0xff810f51,
3028 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3029
3030 /* Vector VQDMLAH. */
3031 {ARM_FEATURE_COPROC (FPU_MVE),
3032 MVE_VQDMLAH,
23d188c7 3033 0xee000e60, 0xff811f70,
d3b63143
AV		 3034 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3035
3036 /* Vector VQRDMLAH. */
3037 {ARM_FEATURE_COPROC (FPU_MVE),
3038 MVE_VQRDMLAH,
23d188c7 3039 0xee000e40, 0xff811f70,
d3b63143
AV		 3040 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3041
3042 /* Vector VQDMLASH. */
3043 {ARM_FEATURE_COPROC (FPU_MVE),
3044 MVE_VQDMLASH,
23d188c7 3045 0xee001e60, 0xff811f70,
d3b63143
AV		 3046 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3047
3048 /* Vector VQRDMLASH. */
3049 {ARM_FEATURE_COPROC (FPU_MVE),
3050 MVE_VQRDMLASH,
23d188c7 3051 0xee001e40, 0xff811f70,
d3b63143
AV		 3052 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3053
3054 /* Vector VQDMLSDH. */
3055 {ARM_FEATURE_COPROC (FPU_MVE),
3056 MVE_VQDMLSDH,
3057 0xfe000e00, 0xff810f51,
3058 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3059
3060 /* Vector VQRDMLSDH. */
3061 {ARM_FEATURE_COPROC (FPU_MVE),
3062 MVE_VQRDMLSDH,
3063 0xfe000e01, 0xff810f51,
3064 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3065
3066 /* Vector VQDMULH T1 variant. */
3067 {ARM_FEATURE_COPROC (FPU_MVE),
3068 MVE_VQDMULH_T1,
3069 0xef000b40, 0xff811f51,
3070 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3071
3072 /* Vector VQRDMULH T2 variant. */
3073 {ARM_FEATURE_COPROC (FPU_MVE),
3074 MVE_VQRDMULH_T2,
3075 0xff000b40, 0xff811f51,
3076 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3077
3078 /* Vector VQDMULH T3 variant. */
3079 {ARM_FEATURE_COPROC (FPU_MVE),
3080 MVE_VQDMULH_T3,
3081 0xee010e60, 0xff811f70,
3082 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3083
3084 /* Vector VQRDMULH T4 variant. */
3085 {ARM_FEATURE_COPROC (FPU_MVE),
3086 MVE_VQRDMULH_T4,
3087 0xfe010e60, 0xff811f70,
3088 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3089
14b456f2
AV		 3090 /* Vector VQNEG. */
3091 {ARM_FEATURE_COPROC (FPU_MVE),
3092 MVE_VQNEG,
3093 0xffb007c0, 0xffb31fd1,
3094 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3095
ed63aa17
AV		 3096 /* Vector VQRSHL T1 variant. */
3097 {ARM_FEATURE_COPROC (FPU_MVE),
3098 MVE_VQRSHL_T1,
3099 0xef000550, 0xef811f51,
3100 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3101
3102 /* Vector VQRSHL T2 variant. */
3103 {ARM_FEATURE_COPROC (FPU_MVE),
3104 MVE_VQRSHL_T2,
3105 0xee331ee0, 0xefb31ff0,
3106 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3107
3108 /* Vector VQRSHRN. */
3109 {ARM_FEATURE_COPROC (FPU_MVE),
3110 MVE_VQRSHRN,
3111 0xee800f41, 0xefa00fd1,
3112 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3113
3114 /* Vector VQRSHRUN. */
3115 {ARM_FEATURE_COPROC (FPU_MVE),
3116 MVE_VQRSHRUN,
3117 0xfe800fc0, 0xffa00fd1,
3118 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3119
3120 /* Vector VQSHL T1 Variant. */
3121 {ARM_FEATURE_COPROC (FPU_MVE),
3122 MVE_VQSHL_T1,
3123 0xee311ee0, 0xefb31ff0,
3124 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3125
3126 /* Vector VQSHL T4 Variant. */
3127 {ARM_FEATURE_COPROC (FPU_MVE),
3128 MVE_VQSHL_T4,
3129 0xef000450, 0xef811f51,
3130 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3131
3132 /* Vector VQSHRN. */
3133 {ARM_FEATURE_COPROC (FPU_MVE),
3134 MVE_VQSHRN,
3135 0xee800f40, 0xefa00fd1,
3136 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3137
3138 /* Vector VQSHRUN. */
3139 {ARM_FEATURE_COPROC (FPU_MVE),
3140 MVE_VQSHRUN,
3141 0xee800fc0, 0xffa00fd1,
3142 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3143
14b456f2
AV		 3144 /* Vector VQSUB T1 Variant. */
3145 {ARM_FEATURE_COPROC (FPU_MVE),
3146 MVE_VQSUB_T1,
3147 0xef000250, 0xef811f51,
3148 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150 /* Vector VQSUB T2 Variant. */
3151 {ARM_FEATURE_COPROC (FPU_MVE),
3152 MVE_VQSUB_T2,
3153 0xee001f60, 0xef811f70,
3154 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156 /* Vector VREV16. */
3157 {ARM_FEATURE_COPROC (FPU_MVE),
3158 MVE_VREV16,
3159 0xffb00140, 0xffb31fd1,
3160 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3161
3162 /* Vector VREV32. */
3163 {ARM_FEATURE_COPROC (FPU_MVE),
3164 MVE_VREV32,
3165 0xffb000c0, 0xffb31fd1,
3166 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3167
3168 /* Vector VREV64. */
3169 {ARM_FEATURE_COPROC (FPU_MVE),
3170 MVE_VREV64,
3171 0xffb00040, 0xffb31fd1,
3172 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3173
bf0b396d
AV		 3174 /* Vector VRINT floating point. */
3175 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3176 MVE_VRINT_FP,
3177 0xffb20440, 0xffb31c51,
3178 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3179
d3b63143
AV		 3180 /* Vector VRMLALDAVH. */
3181 {ARM_FEATURE_COPROC (FPU_MVE),
3182 MVE_VRMLALDAVH,
3183 0xee800f00, 0xef811f51,
3184 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3185
3186 /* Vector VRMLALDAVH. */
3187 {ARM_FEATURE_COPROC (FPU_MVE),
3188 MVE_VRMLALDAVH,
3189 0xee801f00, 0xef811f51,
3190 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3191
ed63aa17
AV		 3192 /* Vector VRSHL T1 Variant. */
3193 {ARM_FEATURE_COPROC (FPU_MVE),
3194 MVE_VRSHL_T1,
3195 0xef000540, 0xef811f51,
3196 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3197
3198 /* Vector VRSHL T2 Variant. */
3199 {ARM_FEATURE_COPROC (FPU_MVE),
3200 MVE_VRSHL_T2,
3201 0xee331e60, 0xefb31ff0,
3202 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3203
3204 /* Vector VRSHRN. */
3205 {ARM_FEATURE_COPROC (FPU_MVE),
3206 MVE_VRSHRN,
3207 0xfe800fc1, 0xffa00fd1,
3208 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3209
66dcaa5d
AV		 3210 /* Vector VSBC. */
3211 {ARM_FEATURE_COPROC (FPU_MVE),
3212 MVE_VSBC,
3213 0xfe300f00, 0xffb10f51,
3214 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3215
ed63aa17
AV		 3216 /* Vector VSHL T2 Variant. */
3217 {ARM_FEATURE_COPROC (FPU_MVE),
3218 MVE_VSHL_T2,
3219 0xee311e60, 0xefb31ff0,
3220 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3221
3222 /* Vector VSHL T3 Variant. */
3223 {ARM_FEATURE_COPROC (FPU_MVE),
3224 MVE_VSHL_T3,
3225 0xef000440, 0xef811f51,
3226 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3227
3228 /* Vector VSHLC. */
3229 {ARM_FEATURE_COPROC (FPU_MVE),
3230 MVE_VSHLC,
3231 0xeea00fc0, 0xffa01ff0,
3232 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3233
3234 /* Vector VSHLL T2 Variant. */
3235 {ARM_FEATURE_COPROC (FPU_MVE),
3236 MVE_VSHLL_T2,
3237 0xee310e01, 0xefb30fd1,
3238 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3239
3240 /* Vector VSHRN. */
3241 {ARM_FEATURE_COPROC (FPU_MVE),
3242 MVE_VSHRN,
3243 0xee800fc1, 0xffa00fd1,
3244 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3245
04d54ace
AV		 3246 /* Vector VST2 no writeback. */
3247 {ARM_FEATURE_COPROC (FPU_MVE),
3248 MVE_VST2,
3249 0xfc801e00, 0xffb01e5f,
3250 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3251
3252 /* Vector VST2 writeback. */
3253 {ARM_FEATURE_COPROC (FPU_MVE),
3254 MVE_VST2,
3255 0xfca01e00, 0xffb01e5f,
3256 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3257
3258 /* Vector VST4 no writeback. */
3259 {ARM_FEATURE_COPROC (FPU_MVE),
3260 MVE_VST4,
3261 0xfc801e01, 0xffb01e1f,
3262 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3263
3264 /* Vector VST4 writeback. */
3265 {ARM_FEATURE_COPROC (FPU_MVE),
3266 MVE_VST4,
3267 0xfca01e01, 0xffb01e1f,
3268 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3269
ef1576a1
AV		 3270 /* Vector VSTRB scatter store, T1 variant. */
3271 {ARM_FEATURE_COPROC (FPU_MVE),
3272 MVE_VSTRB_SCATTER_T1,
3273 0xec800e00, 0xffb01e50,
3274 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3275
3276 /* Vector VSTRH scatter store, T2 variant. */
3277 {ARM_FEATURE_COPROC (FPU_MVE),
3278 MVE_VSTRH_SCATTER_T2,
3279 0xec800e10, 0xffb01e50,
3280 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3281
3282 /* Vector VSTRW scatter store, T3 variant. */
3283 {ARM_FEATURE_COPROC (FPU_MVE),
3284 MVE_VSTRW_SCATTER_T3,
3285 0xec800e40, 0xffb01e50,
3286 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3287
3288 /* Vector VSTRD scatter store, T4 variant. */
3289 {ARM_FEATURE_COPROC (FPU_MVE),
3290 MVE_VSTRD_SCATTER_T4,
3291 0xec800fd0, 0xffb01fd0,
3292 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3293
3294 /* Vector VSTRW scatter store, T5 variant. */
3295 {ARM_FEATURE_COPROC (FPU_MVE),
3296 MVE_VSTRW_SCATTER_T5,
3297 0xfd001e00, 0xff111f00,
3298 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3299
3300 /* Vector VSTRD scatter store, T6 variant. */
3301 {ARM_FEATURE_COPROC (FPU_MVE),
3302 MVE_VSTRD_SCATTER_T6,
3303 0xfd001f00, 0xff111f00,
3304 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3305
aef6d006
AV		 3306 /* Vector VSTRB. */
3307 {ARM_FEATURE_COPROC (FPU_MVE),
3308 MVE_VSTRB_T1,
3309 0xec000e00, 0xfe581e00,
3310 "vstrb%v.%7-8s\t%13-15Q, %d"},
3311
3312 /* Vector VSTRH. */
3313 {ARM_FEATURE_COPROC (FPU_MVE),
3314 MVE_VSTRH_T2,
3315 0xec080e00, 0xfe581e00,
3316 "vstrh%v.%7-8s\t%13-15Q, %d"},
3317
3318 /* Vector VSTRB variant T5. */
3319 {ARM_FEATURE_COPROC (FPU_MVE),
3320 MVE_VSTRB_T5,
3321 0xec001e00, 0xfe101f80,
3322 "vstrb%v.8\t%13-15,22Q, %d"},
3323
3324 /* Vector VSTRH variant T6. */
3325 {ARM_FEATURE_COPROC (FPU_MVE),
3326 MVE_VSTRH_T6,
3327 0xec001e80, 0xfe101f80,
3328 "vstrh%v.16\t%13-15,22Q, %d"},
3329
3330 /* Vector VSTRW variant T7. */
3331 {ARM_FEATURE_COPROC (FPU_MVE),
3332 MVE_VSTRW_T7,
3333 0xec001f00, 0xfe101f80,
3334 "vstrw%v.32\t%13-15,22Q, %d"},
3335
66dcaa5d
AV		 3336 /* Vector VSUB floating point T1 variant. */
3337 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3338 MVE_VSUB_FP_T1,
3339 0xef200d40, 0xffa11f51,
3340 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3341
3342 /* Vector VSUB floating point T2 variant. */
3343 {ARM_FEATURE_COPROC (FPU_MVE_FP),
3344 MVE_VSUB_FP_T2,
3345 0xee301f40, 0xefb11f70,
3346 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3347
3348 /* Vector VSUB T1 variant. */
3349 {ARM_FEATURE_COPROC (FPU_MVE),
3350 MVE_VSUB_VEC_T1,
3351 0xff000840, 0xff811f51,
3352 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3353
3354 /* Vector VSUB T2 variant. */
3355 {ARM_FEATURE_COPROC (FPU_MVE),
3356 MVE_VSUB_VEC_T2,
3357 0xee011f40, 0xff811f70,
3358 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3359
23d00a41
SD		 3360 {ARM_FEATURE_COPROC (FPU_MVE),
3361 MVE_ASRLI,
3362 0xea50012f, 0xfff1813f,
3363 "asrl%c\t%17-19l, %9-11h, %j"},
3364
3365 {ARM_FEATURE_COPROC (FPU_MVE),
3366 MVE_ASRL,
3367 0xea50012d, 0xfff101ff,
3368 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3369
3370 {ARM_FEATURE_COPROC (FPU_MVE),
3371 MVE_LSLLI,
3372 0xea50010f, 0xfff1813f,
3373 "lsll%c\t%17-19l, %9-11h, %j"},
3374
3375 {ARM_FEATURE_COPROC (FPU_MVE),
3376 MVE_LSLL,
3377 0xea50010d, 0xfff101ff,
3378 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3379
3380 {ARM_FEATURE_COPROC (FPU_MVE),
3381 MVE_LSRL,
3382 0xea50011f, 0xfff1813f,
3383 "lsrl%c\t%17-19l, %9-11h, %j"},
3384
3385 {ARM_FEATURE_COPROC (FPU_MVE),
3386 MVE_SQRSHRL,
08132bdd
SP		 3387 0xea51012d, 0xfff1017f,
3388 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3389
3390 {ARM_FEATURE_COPROC (FPU_MVE),
3391 MVE_SQRSHR,
3392 0xea500f2d, 0xfff00fff,
3393 "sqrshr%c\t%16-19S, %12-15S"},
3394
3395 {ARM_FEATURE_COPROC (FPU_MVE),
3396 MVE_SQSHLL,
3397 0xea51013f, 0xfff1813f,
3398 "sqshll%c\t%17-19l, %9-11h, %j"},
3399
3400 {ARM_FEATURE_COPROC (FPU_MVE),
3401 MVE_SQSHL,
3402 0xea500f3f, 0xfff08f3f,
3403 "sqshl%c\t%16-19S, %j"},
3404
3405 {ARM_FEATURE_COPROC (FPU_MVE),
3406 MVE_SRSHRL,
3407 0xea51012f, 0xfff1813f,
3408 "srshrl%c\t%17-19l, %9-11h, %j"},
3409
3410 {ARM_FEATURE_COPROC (FPU_MVE),
3411 MVE_SRSHR,
3412 0xea500f2f, 0xfff08f3f,
3413 "srshr%c\t%16-19S, %j"},
3414
3415 {ARM_FEATURE_COPROC (FPU_MVE),
3416 MVE_UQRSHLL,
08132bdd
SP		 3417 0xea51010d, 0xfff1017f,
3418 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41
SD		 3419
3420 {ARM_FEATURE_COPROC (FPU_MVE),
3421 MVE_UQRSHL,
3422 0xea500f0d, 0xfff00fff,
3423 "uqrshl%c\t%16-19S, %12-15S"},
3424
3425 {ARM_FEATURE_COPROC (FPU_MVE),
3426 MVE_UQSHLL,
3427 0xea51010f, 0xfff1813f,
3428 "uqshll%c\t%17-19l, %9-11h, %j"},
3429
3430 {ARM_FEATURE_COPROC (FPU_MVE),
3431 MVE_UQSHL,
3432 0xea500f0f, 0xfff08f3f,
3433 "uqshl%c\t%16-19S, %j"},
3434
3435 {ARM_FEATURE_COPROC (FPU_MVE),
3436 MVE_URSHRL,
3437 0xea51011f, 0xfff1813f,
3438 "urshrl%c\t%17-19l, %9-11h, %j"},
3439
3440 {ARM_FEATURE_COPROC (FPU_MVE),
3441 MVE_URSHR,
3442 0xea500f1f, 0xfff08f3f,
3443 "urshr%c\t%16-19S, %j"},
3444
e39c1607
SD		 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3446 MVE_CSINC,
3447 0xea509000, 0xfff0f000,
3448 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3449
3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3451 MVE_CSINV,
3452 0xea50a000, 0xfff0f000,
3453 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3454
3455 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3456 MVE_CSET,
3457 0xea5f900f, 0xfffff00f,
3458 "cset\t%8-11S, %4-7C"},
3459
3460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3461 MVE_CSETM,
3462 0xea5fa00f, 0xfffff00f,
3463 "csetm\t%8-11S, %4-7C"},
3464
3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3466 MVE_CSEL,
3467 0xea508000, 0xfff0f000,
3468 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3469
3470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3471 MVE_CSNEG,
3472 0xea50b000, 0xfff0f000,
3473 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3474
3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3476 MVE_CINC,
3477 0xea509000, 0xfff0f000,
3478 "cinc\t%8-11S, %16-19Z, %4-7C"},
3479
3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3481 MVE_CINV,
3482 0xea50a000, 0xfff0f000,
3483 "cinv\t%8-11S, %16-19Z, %4-7C"},
3484
3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3486 MVE_CNEG,
3487 0xea50b000, 0xfff0f000,
3488 "cneg\t%8-11S, %16-19Z, %4-7C"},
3489
143275ea
AV		 3490 {ARM_FEATURE_CORE_LOW (0),
3491 MVE_NONE,
3492 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3493};
3494
8f06b2d8
PB		 3495/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3496 ordered: they must be searched linearly from the top to obtain a correct
3497 match. */
3498
3499/* print_insn_arm recognizes the following format control codes:
3500
3501 %% %
3502
3503 %a print address for ldr/str instruction
3504 %s print address for ldr/str halfword/signextend instruction
c1e26897 3505 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3506 %b print branch destination
3507 %c print condition code (always bits 28-31)
3508 %m print register mask for ldm/stm instruction
3509 %o print operand2 (immediate or register + shift)
3510 %p print 'p' iff bits 12-15 are 15
3511 %t print 't' iff bit 21 set and bit 24 clear
3512 %B print arm BLX(1) destination
3513 %C print the PSR sub type.
62b3e311
PB		 3514 %U print barrier type.
3515 %P print address for pli instruction.
8f06b2d8
PB		 3516
3517 %<bitfield>r print as an ARM register
9eb6c0f1 3518 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3519 %<bitfield>R as %r but r15 is UNPREDICTABLE
3520 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3521 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3522 %<bitfield>d print the bitfield in decimal
43e65147 3523 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3524 %<bitfield>x print the bitfield in hex
3525 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3526
16980d0b
JB		 3527 %<bitfield>'c print specified char iff bitfield is all ones
3528 %<bitfield>`c print specified char iff bitfield is all zeroes
3529 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3530
8f06b2d8
PB		 3531 %e print arm SMI operand (bits 0..7,8..19).
3532 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3533 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3534 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3535
8f06b2d8
PB		 3536static const struct opcode32 arm_opcodes[] =
3537{
3538 /* ARM instructions. */
823d2571
TG		 3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3540 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3542 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3543
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3545 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3547 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3549 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3551 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3553 0x00800090, 0x0fa000f0,
3554 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3556 0x00a00090, 0x0fa000f0,
3557 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3558
105bde57 3559 /* V8.2 RAS extension instructions. */
4d1464f2 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3561 0xe320f010, 0xffffffff, "esb"},
3562
53c4b28b 3563 /* V8 instructions. */
823d2571
TG		 3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3565 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3566 /* Defined in V8 but is in NOP space so available to all arch. */
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3568 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3570 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3571 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3572 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3574 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3576 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3577 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3578 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3579 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3580 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3581 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3582 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3583 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3584 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3585 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3586 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3587 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3588 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3589 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3590 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3591 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3592 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3593 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3594 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3595 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3596 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3597 /* CRC32 instructions. */
823d2571
TG		 3598 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3599 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3600 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3601 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3602 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3603 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3604 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3605 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3606 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3607 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3608 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
3609 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3610
ddfded2f
MW		 3611 /* Privileged Access Never extension instructions. */
3612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3613 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3614
90ec0d68 3615 /* Virtualization Extension instructions. */
823d2571
TG		 3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3618
eea54501 3619 /* Integer Divide Extension instructions. */
823d2571
TG		 3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3621 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3623 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3624
60e5ef9f 3625 /* MP Extension instructions. */
823d2571 3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3627
c597cc3d
SD		 3628 /* Speculation Barriers. */
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3632
62b3e311 3633 /* V7 instructions. */
823d2571
TG		 3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3642 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3643
c19d1205 3644 /* ARM V6T2 instructions. */
823d2571
TG		 3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3646 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3648 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3650 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3652 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3653
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3655 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3657 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3658
ff8646ee 3659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3660 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3662 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3664 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3666 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3667
f4c65163 3668 /* ARM Security extension instructions. */
823d2571
TG		 3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3670 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3671
8f06b2d8 3672 /* ARM V6K instructions. */
823d2571
TG		 3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3674 0xf57ff01f, 0xffffffff, "clrex"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3676 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3678 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3680 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3682 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3684 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3686 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3687
7fadb25d
SD		 3688 /* ARMv8.5-A instructions. */
3689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3690
8f06b2d8 3691 /* ARM V6K NOP hints. */
823d2571
TG		 3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3693 0x0320f001, 0x0fffffff, "yield%c"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3695 0x0320f002, 0x0fffffff, "wfe%c"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3697 0x0320f003, 0x0fffffff, "wfi%c"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3699 0x0320f004, 0x0fffffff, "sev%c"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3701 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3702
fe56b6ce 3703 /* ARM V6 instructions. */
823d2571
TG		 3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3705 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3707 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3709 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3711 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3713 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3715 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3717 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3719 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3721 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3723 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3725 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3727 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3729 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3731 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3733 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3735 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3737 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3739 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3741 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3743 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3745 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3747 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3749 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3751 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3753 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3755 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3757 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3759 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3761 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3763 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3765 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3767 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3769 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3771 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3773 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3775 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3777 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3779 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3781 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3783 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3785 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3787 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3789 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3791 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3793 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3795 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3797 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3799 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3801 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3803 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3805 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3807 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3809 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3811 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3813 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3815 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3817 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3819 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3821 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3823 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3825 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3827 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 3948
8f06b2d8 3949 /* V5J instruction. */
823d2571
TG		 3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
3951 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 3952
8f06b2d8 3953 /* V5 Instructions. */
823d2571
TG		 3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3955 0xe1200070, 0xfff000f0,
3956 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3958 0xfa000000, 0xfe000000, "blx\t%B"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3960 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
3962 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3963
3964 /* V5E "El Segundo" Instructions. */
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3966 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3968 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
3970 0xf450f000, 0xfc70f000, "pld\t%a"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3972 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3974 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3976 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3978 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3979
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3981 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3983 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3984
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3986 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3988 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3990 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3992 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3993
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3995 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3997 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
3999 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4001 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4002
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4004 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4006 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4007
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4009 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4011 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4013 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4015 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4016
8f06b2d8 4017 /* ARM Instructions. */
823d2571
TG		 4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4019 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4020
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4022 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4024 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4026 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4028 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4030 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4032 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4033
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4035 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4037 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4039 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4041 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4042
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4044 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4046 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4048 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4050 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4051
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4053 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4055 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4057 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4058
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4060 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4062 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4064 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4065
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4067 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4069 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4071 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4072
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4074 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4076 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4078 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4079
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4081 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4083 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4085 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4086
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4088 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4090 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4092 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4093
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4095 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4097 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4099 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4100
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4102 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4104 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4106 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4107
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4109 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4111 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4113 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4114
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4116 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4118 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4120 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4121
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4123 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4125 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4127 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4128
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4130 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4132 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4134 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4135
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4137 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4139 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4141 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4142
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4144 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4149
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4164
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4171
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4178
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4183
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4186
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4190 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4191
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4197 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4199 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4211 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4213 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4225 0x092d0000, 0x0fff0000, "push%c\t%m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4227 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4230
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4232 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4234 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4236 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4238 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4246 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4248 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4250 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4252 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4260 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4262 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4264 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4266 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4269
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4271 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4274
4275 /* The rest. */
4ab90a7a
AV		 4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4277 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4280 {ARM_FEATURE_CORE_LOW (0),
4281 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4282};
4283
4284/* print_insn_thumb16 recognizes the following format control codes:
4285
4286 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4287 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4288 %<bitfield>I print bitfield as a signed decimal
4289 (top bit of range being the sign bit)
4290 %N print Thumb register mask (with LR)
4291 %O print Thumb register mask (with PC)
4292 %M print Thumb register mask
4293 %b print CZB's 6-bit unsigned branch destination
4294 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4295 %c print the condition code
4296 %C print the condition code, or "s" if not conditional
4297 %x print warning if conditional an not at end of IT block"
4298 %X print "\t; unpredictable <IT:code>" if conditional
4299 %I print IT instruction suffix and operands
4547cb56 4300 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4301 %<bitfield>r print bitfield as an ARM register
4302 %<bitfield>d print bitfield as a decimal
4303 %<bitfield>H print (bitfield * 2) as a decimal
4304 %<bitfield>W print (bitfield * 4) as a decimal
4305 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4306 %<bitfield>B print Thumb branch destination (signed displacement)
4307 %<bitfield>c print bitfield as a condition code
4308 %<bitnum>'c print specified char iff bit is one
4309 %<bitnum>?ab print a if bit is one else print b. */
4310
4311static const struct opcode16 thumb_opcodes[] =
4312{
4313 /* Thumb instructions. */
4314
16a1fa25
TP		 4315 /* ARMv8-M Security Extensions instructions. */
4316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4318
53c4b28b 4319 /* ARM V8 instructions. */
823d2571
TG		 4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4323
8f06b2d8 4324 /* ARM V6K no-argument instructions. */
823d2571
TG		 4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4331
4332 /* ARM V6T2 instructions. */
ff8646ee
TP		 4333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4334 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4335 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4336 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4338
4339 /* ARM V6. */
823d2571
TG		 4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4351
4352 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4354 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4355 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4357 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4358 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4360 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4361 /* Format 4. */
823d2571
TG		 4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4378 /* format 13 */
823d2571
TG		 4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4381 /* format 5 */
823d2571
TG		 4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4386 /* format 14 */
823d2571
TG		 4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4389 /* format 2 */
823d2571
TG		 4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4391 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4393 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4395 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4397 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4398 /* format 8 */
823d2571
TG		 4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4400 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4402 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4404 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4405 /* format 7 */
823d2571
TG		 4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4407 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4409 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4410 /* format 1 */
823d2571
TG		 4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4413 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4416 /* format 3 */
823d2571
TG		 4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4421 /* format 6 */
823d2571
TG		 4422 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4424 0x4800, 0xF800,
4425 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4426 /* format 9 */
823d2571
TG		 4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4428 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4430 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4432 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4434 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4435 /* format 10 */
823d2571
TG		 4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4437 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4439 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4440 /* format 11 */
823d2571
TG		 4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4442 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4444 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4445 /* format 12 */
823d2571
TG		 4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4447 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4449 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4450 /* format 15 */
823d2571
TG		 4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4453 /* format 17 */
823d2571 4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4455 /* format 16 */
823d2571
TG		 4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4459 /* format 18 */
823d2571 4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4461
4462 /* The E800 .. FFFF range is unconditionally redirected to the
4463 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4464 are processed via that table. Thus, we can never encounter a
4465 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4467 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4468};
4469
4470/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4471 We adopt the convention that hw1 is the high 16 bits of .value and
4472 .mask, hw2 the low 16 bits.
4473
4474 print_insn_thumb32 recognizes the following format control codes:
4475
4476 %% %
4477
4478 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4479 %M print a modified 12-bit immediate (same location)
4480 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4481 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4482 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4483 %S print a possibly-shifted Rm
4484
32a94698 4485 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4486 %a print the address of a plain load/store
4487 %w print the width and signedness of a core load/store
4488 %m print register mask for ldm/stm
4b5a202f 4489 %n print register mask for clrm
8f06b2d8
PB		 4490
4491 %E print the lsb and width fields of a bfc/bfi instruction
4492 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4493 %G print a fallback offset for Branch Future instructions
e5d6e09e 4494 %W print an offset for BF instruction
1caf72a5 4495 %Y print an offset for BFL instruction
1889da70 4496 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4497 %Q print an offset for Low Overhead Loop instructions
4498 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4499 %b print a conditional branch offset
4500 %B print an unconditional branch offset
4501 %s print the shift field of an SSAT instruction
4502 %R print the rotation field of an SXT instruction
62b3e311
PB		 4503 %U print barrier type.
4504 %P print address for pli instruction.
c22aaad1
PB		 4505 %c print the condition code
4506 %x print warning if conditional an not at end of IT block"
4507 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4508
4509 %<bitfield>d print bitfield in decimal
f0fba320 4510 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4511 %<bitfield>W print bitfield*4 in decimal
4512 %<bitfield>r print bitfield as an ARM register
dd5181d5 4513 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4514 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4515 %<bitfield>c print bitfield as a condition code
4516
16980d0b
JB		 4517 %<bitfield>'c print specified char iff bitfield is all ones
4518 %<bitfield>`c print specified char iff bitfield is all zeroes
4519 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4520
4521 With one exception at the bottom (done because BL and BLX(1) need
4522 to come dead last), this table was machine-sorted first in
4523 decreasing order of number of bits set in the mask, then in
4524 increasing numeric order of mask, then in increasing numeric order
4525 of opcode. This order is not the clearest for a human reader, but
4526 is guaranteed never to catch a special-case bit pattern with a more
4527 general mask, which is important, because this instruction encoding
4528 makes heavy use of special-case bit patterns. */
4529static const struct opcode32 thumb32_opcodes[] =
4530{
4b5a202f
AV		 4531 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4532 instructions. */
60f993ce 4533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4534 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4536 0xf02fc001, 0xfffff001, "le\t%P"},
4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4538 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4540 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4542 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4544 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4546 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4548 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4549
4389b29a
AV		 4550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4551 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4553 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4555 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4557 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4559 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4560
4b5a202f
AV		 4561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4562 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4563
16a1fa25
TP		 4564 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4567 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4569 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4571 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4573 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4574
105bde57 4575 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4577 0xf3af8010, 0xffffffff, "esb"},
4578
53c4b28b 4579 /* V8 instructions. */
823d2571
TG		 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4581 0xf3af8005, 0xffffffff, "sevl%c.w"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4583 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4585 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4587 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4589 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4591 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4593 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4595 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4597 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4599 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4601 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4603 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4605 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4607 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4609 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4611 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4612
dd5181d5 4613 /* CRC32 instructions. */
823d2571 4614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4615 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
823d2571 4616 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4617 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
823d2571 4618 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4619 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
823d2571 4620 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4621 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
823d2571 4622 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4623 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
823d2571 4624 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
cc4a945a 4625 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4626
c597cc3d
SD		 4627 /* Speculation Barriers. */
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4631
62b3e311 4632 /* V7 instructions. */
823d2571
TG		 4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4641 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4643 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4644
90ec0d68 4645 /* Virtualization Extension instructions. */
823d2571 4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4647 /* We skip ERET as that is SUBS pc, lr, #0. */
4648
60e5ef9f 4649 /* MP Extension instructions. */
823d2571 4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4651
f4c65163 4652 /* Security extension instructions. */
823d2571 4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4654
7fadb25d
SD		 4655 /* ARMv8.5-A instructions. */
4656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4657
8f06b2d8 4658 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4665 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4667
ff8646ee 4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4669 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4671 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4673 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4675 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4677 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4679 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4681 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4683 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4685 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4687 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4689 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4691 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4693 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4695 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4697 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4699 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4701 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4703 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4705 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4707 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4709 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4711 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4713 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4715 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4717 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4719 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4721 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4723 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4725 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4727 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4729 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4731 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4733 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4735 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4737 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4739 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4741 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4743 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4745 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4747 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4749 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4751 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4753 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4755 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4757 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4759 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4761 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4763 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4765 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4767 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4769 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4771 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4773 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4775 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4777 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4779 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4781 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4783 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4785 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4787 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4789 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4791 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4795 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4797 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4825 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4827 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4845 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 4892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4893 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xf810f000, 0xff70f000, "pld%c\t%a"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xfb100000, 0xfff000c0,
4926 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfbc00080, 0xfff000c0,
4929 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4931 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4935 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4940 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4941 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 4944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4945 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4953 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4955 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 4966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4967 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xe9400000, 0xff500000,
5002 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xe9500000, 0xff500000,
5005 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xe8600000, 0xff700000,
5008 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xe8700000, 0xff700000,
5011 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5013 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5016
5017 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5019 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5021 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5025 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5026
8f06b2d8 5027 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5029 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5031 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5032
5033 /* Fallback. */
823d2571
TG		 5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5035 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5036 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5037};
ff4a8d2b 5038
8f06b2d8
PB		 5039static const char *const arm_conditional[] =
5040{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5041 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5042
5043static const char *const arm_fp_const[] =
5044{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5045
5046static const char *const arm_shift[] =
5047{"lsl", "lsr", "asr", "ror"};
5048
5049typedef struct
5050{
5051 const char *name;
5052 const char *description;
5053 const char *reg_names[16];
5054}
5055arm_regname;
5056
5057static const arm_regname regnames[] =
5058{
65b48a81 5059 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5060 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5061 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5062 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5063 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5064 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5065 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5066 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5067 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5068 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5069 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5070 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81
PB		 5071 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5072 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
8f06b2d8
PB		 5073};
5074
5075static const char *const iwmmxt_wwnames[] =
5076{"b", "h", "w", "d"};
5077
5078static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5079{"b", "bus", "bc", "bss",
5080 "h", "hus", "hc", "hss",
5081 "w", "wus", "wc", "wss",
5082 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5083};
5084
5085static const char *const iwmmxt_regnames[] =
5086{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5087 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5088};
5089
5090static const char *const iwmmxt_cregnames[] =
5091{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5092 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5093};
5094
143275ea
AV		 5095static const char *const vec_condnames[] =
5096{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5097};
5098
5099static const char *const mve_predicatenames[] =
5100{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5101 "eee", "ee", "eet", "e", "ett", "et", "ete"
5102};
5103
5104/* Names for 2-bit size field for mve vector isntructions. */
5105static const char *const mve_vec_sizename[] =
5106 { "8", "16", "32", "64"};
5107
5108/* Indicates whether we are processing a then predicate,
5109 else predicate or none at all. */
5110enum vpt_pred_state
5111{
5112 PRED_NONE,
5113 PRED_THEN,
5114 PRED_ELSE
5115};
5116
5117/* Information used to process a vpt block and subsequent instructions. */
5118struct vpt_block
5119{
5120 /* Are we in a vpt block. */
5121 bfd_boolean in_vpt_block;
5122
5123 /* Next predicate state if in vpt block. */
5124 enum vpt_pred_state next_pred_state;
5125
5126 /* Mask from vpt/vpst instruction. */
5127 long predicate_mask;
5128
5129 /* Instruction number in vpt block. */
5130 long current_insn_num;
5131
5132 /* Number of instructions in vpt block.. */
5133 long num_pred_insn;
5134};
5135
5136static struct vpt_block vpt_block_state =
5137{
5138 FALSE,
5139 PRED_NONE,
5140 0,
5141 0,
5142 0
5143};
5144
8f06b2d8
PB		 5145/* Default to GCC register name set. */
5146static unsigned int regname_selected = 1;
5147
65b48a81 5148#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5149#define arm_regnames regnames[regname_selected].reg_names
5150
5151static bfd_boolean force_thumb = FALSE;
5152
c22aaad1
PB		 5153/* Current IT instruction state. This contains the same state as the IT
5154 bits in the CPSR. */
5155static unsigned int ifthen_state;
5156/* IT state for the next instruction. */
5157static unsigned int ifthen_next_state;
5158/* The address of the insn for which the IT state is valid. */
5159static bfd_vma ifthen_address;
5160#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5161/* Indicates that the current Conditional state is unconditional or outside
5162 an IT block. */
5163#define COND_UNCOND 16
c22aaad1 5164
8f06b2d8
PB		 5165\f
5166/* Functions. */
143275ea
AV		 5167/* Extract the predicate mask for a VPT or VPST instruction.
5168 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5169
5170static long
5171mve_extract_pred_mask (long given)
5172{
5173 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5174}
5175
5176/* Return the number of instructions in a MVE predicate block. */
5177static long
5178num_instructions_vpt_block (long given)
5179{
5180 long mask = mve_extract_pred_mask (given);
5181 if (mask == 0)
5182 return 0;
5183
5184 if (mask == 8)
5185 return 1;
5186
5187 if ((mask & 7) == 4)
5188 return 2;
5189
5190 if ((mask & 3) == 2)
5191 return 3;
5192
5193 if ((mask & 1) == 1)
5194 return 4;
5195
5196 return 0;
5197}
5198
5199static void
5200mark_outside_vpt_block (void)
5201{
5202 vpt_block_state.in_vpt_block = FALSE;
5203 vpt_block_state.next_pred_state = PRED_NONE;
5204 vpt_block_state.predicate_mask = 0;
5205 vpt_block_state.current_insn_num = 0;
5206 vpt_block_state.num_pred_insn = 0;
5207}
5208
5209static void
5210mark_inside_vpt_block (long given)
5211{
5212 vpt_block_state.in_vpt_block = TRUE;
5213 vpt_block_state.next_pred_state = PRED_THEN;
5214 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5215 vpt_block_state.current_insn_num = 0;
5216 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5217 assert (vpt_block_state.num_pred_insn >= 1);
5218}
5219
5220static enum vpt_pred_state
5221invert_next_predicate_state (enum vpt_pred_state astate)
5222{
5223 if (astate == PRED_THEN)
5224 return PRED_ELSE;
5225 else if (astate == PRED_ELSE)
5226 return PRED_THEN;
5227 else
5228 return PRED_NONE;
5229}
5230
5231static enum vpt_pred_state
5232update_next_predicate_state (void)
5233{
5234 long pred_mask = vpt_block_state.predicate_mask;
5235 long mask_for_insn = 0;
5236
5237 switch (vpt_block_state.current_insn_num)
5238 {
5239 case 1:
5240 mask_for_insn = 8;
5241 break;
5242
5243 case 2:
5244 mask_for_insn = 4;
5245 break;
5246
5247 case 3:
5248 mask_for_insn = 2;
5249 break;
5250
5251 case 4:
5252 return PRED_NONE;
5253 }
5254
5255 if (pred_mask & mask_for_insn)
5256 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5257 else
5258 return vpt_block_state.next_pred_state;
5259}
5260
5261static void
5262update_vpt_block_state (void)
5263{
5264 vpt_block_state.current_insn_num++;
5265 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5266 {
5267 /* No more instructions to process in vpt block. */
5268 mark_outside_vpt_block ();
5269 return;
5270 }
5271
5272 vpt_block_state.next_pred_state = update_next_predicate_state ();
5273}
8f06b2d8 5274
16980d0b
JB		 5275/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5276 Returns pointer to following character of the format string and
5277 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5278 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5279
5280static const char *
fe56b6ce
NC		 5281arm_decode_bitfield (const char *ptr,
5282 unsigned long insn,
5283 unsigned long *valuep,
5284 int *widthp)
16980d0b
JB		 5285{
5286 unsigned long value = 0;
5287 int width = 0;
43e65147
L		 5288
5289 do
16980d0b
JB		 5290 {
5291 int start, end;
5292 int bits;
5293
5294 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5295 start = start * 10 + *ptr - '0';
5296 if (*ptr == '-')
5297 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5298 end = end * 10 + *ptr - '0';
5299 else
5300 end = start;
5301 bits = end - start;
5302 if (bits < 0)
5303 abort ();
5304 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5305 width += bits + 1;
5306 }
5307 while (*ptr++ == ',');
5308 *valuep = value;
5309 if (widthp)
5310 *widthp = width;
5311 return ptr - 1;
5312}
5313
8f06b2d8 5314static void
37b37b2d 5315arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5316 bfd_boolean print_shift)
8f06b2d8
PB		 5317{
5318 func (stream, "%s", arm_regnames[given & 0xf]);
5319
5320 if ((given & 0xff0) != 0)
5321 {
5322 if ((given & 0x10) == 0)
5323 {
5324 int amount = (given & 0xf80) >> 7;
5325 int shift = (given & 0x60) >> 5;
5326
5327 if (amount == 0)
5328 {
5329 if (shift == 3)
5330 {
5331 func (stream, ", rrx");
5332 return;
5333 }
5334
5335 amount = 32;
5336 }
5337
37b37b2d
RE		 5338 if (print_shift)
5339 func (stream, ", %s #%d", arm_shift[shift], amount);
5340 else
5341 func (stream, ", #%d", amount);
8f06b2d8 5342 }
74bdfecf 5343 else if ((given & 0x80) == 0x80)
aefd8a40 5344 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5345 else if (print_shift)
8f06b2d8
PB		 5346 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5347 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5348 else
5349 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5350 }
5351}
5352
73cd51e5
AV		 5353/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5354
5355static bfd_boolean
5356is_mve_okay_in_it (enum mve_instructions matched_insn)
5357{
c507f10b
AV		 5358 switch (matched_insn)
5359 {
5360 case MVE_VMOV_GP_TO_VEC_LANE:
5361 case MVE_VMOV2_VEC_LANE_TO_GP:
5362 case MVE_VMOV2_GP_TO_VEC_LANE:
5363 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5364 case MVE_LSLL:
5365 case MVE_LSLLI:
5366 case MVE_LSRL:
5367 case MVE_ASRL:
5368 case MVE_ASRLI:
5369 case MVE_SQRSHRL:
5370 case MVE_SQRSHR:
5371 case MVE_UQRSHL:
5372 case MVE_UQRSHLL:
5373 case MVE_UQSHL:
5374 case MVE_UQSHLL:
5375 case MVE_URSHRL:
5376 case MVE_URSHR:
5377 case MVE_SRSHRL:
5378 case MVE_SRSHR:
5379 case MVE_SQSHLL:
5380 case MVE_SQSHL:
c507f10b
AV		 5381 return TRUE;
5382 default:
5383 return FALSE;
5384 }
73cd51e5
AV		 5385}
5386
5387static bfd_boolean
5388is_mve_architecture (struct disassemble_info *info)
5389{
5390 struct arm_private_data *private_data = info->private_data;
5391 arm_feature_set allowed_arches = private_data->features;
5392
5393 arm_feature_set arm_ext_v8_1m_main
5394 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5395
5396 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5397 && !ARM_CPU_IS_ANY (allowed_arches))
5398 return TRUE;
5399 else
5400 return FALSE;
5401}
5402
143275ea
AV		 5403static bfd_boolean
5404is_vpt_instruction (long given)
5405{
5406
5407 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5408 if ((given & 0x0040e000) == 0)
5409 return FALSE;
5410
5411 /* VPT floating point T1 variant. */
5412 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5413 /* VPT floating point T2 variant. */
5414 || ((given & 0xefb10f50) == 0xee310f40)
5415 /* VPT vector T1 variant. */
5416 || ((given & 0xff811f51) == 0xfe010f00)
5417 /* VPT vector T2 variant. */
5418 || ((given & 0xff811f51) == 0xfe010f01
5419 && ((given & 0x300000) != 0x300000))
5420 /* VPT vector T3 variant. */
5421 || ((given & 0xff811f50) == 0xfe011f00)
5422 /* VPT vector T4 variant. */
5423 || ((given & 0xff811f70) == 0xfe010f40)
5424 /* VPT vector T5 variant. */
5425 || ((given & 0xff811f70) == 0xfe010f60)
5426 /* VPT vector T6 variant. */
5427 || ((given & 0xff811f50) == 0xfe011f40)
5428 /* VPST vector T variant. */
5429 || ((given & 0xffbf1fff) == 0xfe310f4d))
5430 return TRUE;
5431 else
5432 return FALSE;
5433}
5434
73cd51e5
AV		 5435/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5436 and ending bitfield = END. END must be greater than START. */
5437
5438static unsigned long
5439arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5440{
5441 int bits = end - start;
5442
5443 if (bits < 0)
5444 abort ();
5445
5446 return ((given >> start) & ((2ul << bits) - 1));
5447}
5448
5449/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5450 START:END and START2:END2. END/END2 must be greater than
5451 START/START2. */
5452
5453static unsigned long
5454arm_decode_field_multiple (unsigned long given, unsigned int start,
5455 unsigned int end, unsigned int start2,
5456 unsigned int end2)
5457{
5458 int bits = end - start;
5459 int bits2 = end2 - start2;
5460 unsigned long value = 0;
5461 int width = 0;
5462
5463 if (bits2 < 0)
5464 abort ();
5465
5466 value = arm_decode_field (given, start, end);
5467 width += bits + 1;
5468
5469 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5470 return value;
5471}
5472
5473/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5474 This helps us decode instructions that change mnemonic depending on specific
5475 operand values/encodings. */
5476
5477static bfd_boolean
5478is_mve_encoding_conflict (unsigned long given,
5479 enum mve_instructions matched_insn)
5480{
143275ea
AV		 5481 switch (matched_insn)
5482 {
5483 case MVE_VPST:
5484 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5485 return TRUE;
5486 else
5487 return FALSE;
5488
5489 case MVE_VPT_FP_T1:
5490 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5491 return TRUE;
5492 if ((arm_decode_field (given, 12, 12) == 0)
5493 && (arm_decode_field (given, 0, 0) == 1))
5494 return TRUE;
5495 return FALSE;
5496
5497 case MVE_VPT_FP_T2:
5498 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5499 return TRUE;
5500 if (arm_decode_field (given, 0, 3) == 0xd)
5501 return TRUE;
5502 return FALSE;
5503
5504 case MVE_VPT_VEC_T1:
5505 case MVE_VPT_VEC_T2:
5506 case MVE_VPT_VEC_T3:
5507 case MVE_VPT_VEC_T4:
5508 case MVE_VPT_VEC_T5:
5509 case MVE_VPT_VEC_T6:
5510 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5511 return TRUE;
5512 if (arm_decode_field (given, 20, 21) == 3)
5513 return TRUE;
5514 return FALSE;
5515
5516 case MVE_VCMP_FP_T1:
5517 if ((arm_decode_field (given, 12, 12) == 0)
5518 && (arm_decode_field (given, 0, 0) == 1))
5519 return TRUE;
5520 else
5521 return FALSE;
5522
5523 case MVE_VCMP_FP_T2:
5524 if (arm_decode_field (given, 0, 3) == 0xd)
5525 return TRUE;
5526 else
5527 return FALSE;
5528
14b456f2
AV		 5529 case MVE_VQADD_T2:
5530 case MVE_VQSUB_T2:
f49bb598
AV		 5531 case MVE_VMUL_VEC_T2:
5532 case MVE_VMULH:
5533 case MVE_VRMULH:
56858bea
AV		 5534 case MVE_VMLA:
5535 case MVE_VMAX:
5536 case MVE_VMIN:
e523f101 5537 case MVE_VBRSR:
66dcaa5d
AV		 5538 case MVE_VADD_VEC_T2:
5539 case MVE_VSUB_VEC_T2:
5540 case MVE_VABAV:
ed63aa17
AV		 5541 case MVE_VQRSHL_T1:
5542 case MVE_VQSHL_T4:
5543 case MVE_VRSHL_T1:
5544 case MVE_VSHL_T3:
897b9bbc
AV		 5545 case MVE_VCADD_VEC:
5546 case MVE_VHCADD:
1c8f2df8
AV		 5547 case MVE_VDDUP:
5548 case MVE_VIDUP:
d3b63143
AV		 5549 case MVE_VQRDMLADH:
5550 case MVE_VQDMLAH:
5551 case MVE_VQRDMLAH:
5552 case MVE_VQDMLASH:
5553 case MVE_VQRDMLASH:
5554 case MVE_VQDMLSDH:
5555 case MVE_VQRDMLSDH:
5556 case MVE_VQDMULH_T3:
5557 case MVE_VQRDMULH_T4:
5558 case MVE_VQDMLADH:
5559 case MVE_VMLAS:
14925797 5560 case MVE_VMULL_INT:
9743db03
AV		 5561 case MVE_VHADD_T2:
5562 case MVE_VHSUB_T2:
143275ea
AV		 5563 case MVE_VCMP_VEC_T1:
5564 case MVE_VCMP_VEC_T2:
5565 case MVE_VCMP_VEC_T3:
5566 case MVE_VCMP_VEC_T4:
5567 case MVE_VCMP_VEC_T5:
5568 case MVE_VCMP_VEC_T6:
5569 if (arm_decode_field (given, 20, 21) == 3)
5570 return TRUE;
5571 else
5572 return FALSE;
5573
04d54ace
AV		 5574 case MVE_VLD2:
5575 case MVE_VLD4:
5576 case MVE_VST2:
5577 case MVE_VST4:
5578 if (arm_decode_field (given, 7, 8) == 3)
5579 return TRUE;
5580 else
5581 return FALSE;
5582
aef6d006
AV		 5583 case MVE_VSTRB_T1:
5584 case MVE_VSTRH_T2:
5585 if ((arm_decode_field (given, 24, 24) == 0)
5586 && (arm_decode_field (given, 21, 21) == 0))
5587 {
5588 return TRUE;
5589 }
5590 else if ((arm_decode_field (given, 7, 8) == 3))
5591 return TRUE;
5592 else
5593 return FALSE;
5594
5595 case MVE_VSTRB_T5:
5596 case MVE_VSTRH_T6:
5597 case MVE_VSTRW_T7:
5598 if ((arm_decode_field (given, 24, 24) == 0)
5599 && (arm_decode_field (given, 21, 21) == 0))
5600 {
5601 return TRUE;
5602 }
5603 else
5604 return FALSE;
5605
bf0b396d
AV		 5606 case MVE_VCVT_FP_FIX_VEC:
5607 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5608
c507f10b
AV		 5609 case MVE_VBIC_IMM:
5610 case MVE_VORR_IMM:
5611 {
5612 unsigned long cmode = arm_decode_field (given, 8, 11);
5613
5614 if ((cmode & 1) == 0)
5615 return TRUE;
5616 else if ((cmode & 0xc) == 0xc)
5617 return TRUE;
5618 else
5619 return FALSE;
5620 }
5621
5622 case MVE_VMVN_IMM:
5623 {
5624 unsigned long cmode = arm_decode_field (given, 8, 11);
5625
5626 if ((cmode & 9) == 1)
5627 return TRUE;
5628 else if ((cmode & 5) == 1)
5629 return TRUE;
5630 else if ((cmode & 0xe) == 0xe)
5631 return TRUE;
5632 else
5633 return FALSE;
5634 }
5635
5636 case MVE_VMOV_IMM_TO_VEC:
5637 if ((arm_decode_field (given, 5, 5) == 1)
5638 && (arm_decode_field (given, 8, 11) != 0xe))
5639 return TRUE;
5640 else
5641 return FALSE;
5642
14925797
AV		 5643 case MVE_VMOVL:
5644 {
5645 unsigned long size = arm_decode_field (given, 19, 20);
5646 if ((size == 0) || (size == 3))
5647 return TRUE;
5648 else
5649 return FALSE;
5650 }
5651
56858bea
AV		 5652 case MVE_VMAXA:
5653 case MVE_VMINA:
5654 case MVE_VMAXV:
5655 case MVE_VMAXAV:
5656 case MVE_VMINV:
5657 case MVE_VMINAV:
ed63aa17
AV		 5658 case MVE_VQRSHL_T2:
5659 case MVE_VQSHL_T1:
5660 case MVE_VRSHL_T2:
5661 case MVE_VSHL_T2:
5662 case MVE_VSHLL_T2:
d3b63143 5663 case MVE_VADDV:
14925797
AV		 5664 case MVE_VMOVN:
5665 case MVE_VQMOVUN:
5666 case MVE_VQMOVN:
5667 if (arm_decode_field (given, 18, 19) == 3)
5668 return TRUE;
5669 else
5670 return FALSE;
5671
d3b63143
AV		 5672 case MVE_VMLSLDAV:
5673 case MVE_VRMLSLDAVH:
5674 case MVE_VMLALDAV:
5675 case MVE_VADDLV:
5676 if (arm_decode_field (given, 20, 22) == 7)
5677 return TRUE;
5678 else
5679 return FALSE;
5680
5681 case MVE_VRMLALDAVH:
5682 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5683 return TRUE;
5684 else
5685 return FALSE;
5686
1c8f2df8
AV		 5687 case MVE_VDWDUP:
5688 case MVE_VIWDUP:
5689 if ((arm_decode_field (given, 20, 21) == 3)
5690 || (arm_decode_field (given, 1, 3) == 7))
5691 return TRUE;
5692 else
5693 return FALSE;
5694
ed63aa17
AV		 5695
5696 case MVE_VSHLL_T1:
5697 if (arm_decode_field (given, 16, 18) == 0)
5698 {
5699 unsigned long sz = arm_decode_field (given, 19, 20);
5700
5701 if ((sz == 1) || (sz == 2))
5702 return TRUE;
5703 else
5704 return FALSE;
5705 }
5706 else
5707 return FALSE;
5708
5709 case MVE_VQSHL_T2:
5710 case MVE_VQSHLU_T3:
5711 case MVE_VRSHR:
5712 case MVE_VSHL_T1:
5713 case MVE_VSHR:
5714 case MVE_VSLI:
5715 case MVE_VSRI:
5716 if (arm_decode_field (given, 19, 21) == 0)
5717 return TRUE;
5718 else
5719 return FALSE;
5720
e523f101
AV		 5721 case MVE_VCTP:
5722 if (arm_decode_field (given, 16, 19) == 0xf)
5723 return TRUE;
5724 else
5725 return FALSE;
5726
23d00a41
SD		 5727 case MVE_ASRLI:
5728 case MVE_ASRL:
5729 case MVE_LSLLI:
5730 case MVE_LSLL:
5731 case MVE_LSRL:
5732 case MVE_SQRSHRL:
5733 case MVE_SQSHLL:
5734 case MVE_SRSHRL:
5735 case MVE_UQRSHLL:
5736 case MVE_UQSHLL:
5737 case MVE_URSHRL:
5738 if (arm_decode_field (given, 9, 11) == 0x7)
5739 return TRUE;
5740 else
5741 return FALSE;
5742
e39c1607
SD		 5743 case MVE_CSINC:
5744 case MVE_CSINV:
5745 {
5746 unsigned long rm, rn;
5747 rm = arm_decode_field (given, 0, 3);
5748 rn = arm_decode_field (given, 16, 19);
5749 /* CSET/CSETM. */
5750 if (rm == 0xf && rn == 0xf)
5751 return TRUE;
5752 /* CINC/CINV. */
5753 else if (rn == rm && rn != 0xf)
5754 return TRUE;
5755 }
5756 /* Fall through. */
5757 case MVE_CSEL:
5758 case MVE_CSNEG:
5759 if (arm_decode_field (given, 0, 3) == 0xd)
5760 return TRUE;
5761 /* CNEG. */
5762 else if (matched_insn == MVE_CSNEG)
5763 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5764 return TRUE;
5765 return FALSE;
5766
143275ea 5767 default:
66dcaa5d
AV		 5768 case MVE_VADD_FP_T1:
5769 case MVE_VADD_FP_T2:
5770 case MVE_VADD_VEC_T1:
143275ea
AV		 5771 return FALSE;
5772
5773 }
73cd51e5
AV		 5774}
5775
aef6d006
AV		 5776static void
5777print_mve_vld_str_addr (struct disassemble_info *info,
5778 unsigned long given,
5779 enum mve_instructions matched_insn)
5780{
5781 void *stream = info->stream;
5782 fprintf_ftype func = info->fprintf_func;
5783
5784 unsigned long p, w, gpr, imm, add, mod_imm;
5785
5786 imm = arm_decode_field (given, 0, 6);
5787 mod_imm = imm;
5788
5789 switch (matched_insn)
5790 {
5791 case MVE_VLDRB_T1:
5792 case MVE_VSTRB_T1:
5793 gpr = arm_decode_field (given, 16, 18);
5794 break;
5795
5796 case MVE_VLDRH_T2:
5797 case MVE_VSTRH_T2:
5798 gpr = arm_decode_field (given, 16, 18);
5799 mod_imm = imm << 1;
5800 break;
5801
5802 case MVE_VLDRH_T6:
5803 case MVE_VSTRH_T6:
5804 gpr = arm_decode_field (given, 16, 19);
5805 mod_imm = imm << 1;
5806 break;
5807
5808 case MVE_VLDRW_T7:
5809 case MVE_VSTRW_T7:
5810 gpr = arm_decode_field (given, 16, 19);
5811 mod_imm = imm << 2;
5812 break;
5813
5814 case MVE_VLDRB_T5:
5815 case MVE_VSTRB_T5:
5816 gpr = arm_decode_field (given, 16, 19);
5817 break;
5818
5819 default:
5820 return;
5821 }
5822
5823 p = arm_decode_field (given, 24, 24);
5824 w = arm_decode_field (given, 21, 21);
5825
5826 add = arm_decode_field (given, 23, 23);
5827
5828 char * add_sub;
5829
5830 /* Don't print anything for '+' as it is implied. */
5831 if (add == 1)
5832 add_sub = "";
5833 else
5834 add_sub = "-";
5835
5836 if (p == 1)
5837 {
5838 /* Offset mode. */
5839 if (w == 0)
5840 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5841 /* Pre-indexed mode. */
5842 else
5843 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5844 }
5845 else if ((p == 0) && (w == 1))
5846 /* Post-index mode. */
5847 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5848}
5849
73cd51e5
AV		 5850/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5851 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5852 this encoding is undefined. */
5853
5854static bfd_boolean
5855is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5856 enum mve_undefined *undefined_code)
5857{
5858 *undefined_code = UNDEF_NONE;
5859
9743db03
AV		 5860 switch (matched_insn)
5861 {
5862 case MVE_VDUP:
5863 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5864 {
5865 *undefined_code = UNDEF_SIZE_3;
5866 return TRUE;
5867 }
5868 else
5869 return FALSE;
5870
14b456f2
AV		 5871 case MVE_VQADD_T1:
5872 case MVE_VQSUB_T1:
f49bb598 5873 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 5874 case MVE_VABD_VEC:
5875 case MVE_VADD_VEC_T1:
5876 case MVE_VSUB_VEC_T1:
d3b63143
AV		 5877 case MVE_VQDMULH_T1:
5878 case MVE_VQRDMULH_T2:
9743db03
AV		 5879 case MVE_VRHADD:
5880 case MVE_VHADD_T1:
5881 case MVE_VHSUB_T1:
5882 if (arm_decode_field (given, 20, 21) == 3)
5883 {
5884 *undefined_code = UNDEF_SIZE_3;
5885 return TRUE;
5886 }
5887 else
5888 return FALSE;
5889
aef6d006
AV		 5890 case MVE_VLDRB_T1:
5891 if (arm_decode_field (given, 7, 8) == 3)
5892 {
5893 *undefined_code = UNDEF_SIZE_3;
5894 return TRUE;
5895 }
5896 else
5897 return FALSE;
5898
5899 case MVE_VLDRH_T2:
5900 if (arm_decode_field (given, 7, 8) <= 1)
5901 {
5902 *undefined_code = UNDEF_SIZE_LE_1;
5903 return TRUE;
5904 }
5905 else
5906 return FALSE;
5907
5908 case MVE_VSTRB_T1:
5909 if ((arm_decode_field (given, 7, 8) == 0))
5910 {
5911 *undefined_code = UNDEF_SIZE_0;
5912 return TRUE;
5913 }
5914 else
5915 return FALSE;
5916
5917 case MVE_VSTRH_T2:
5918 if ((arm_decode_field (given, 7, 8) <= 1))
5919 {
5920 *undefined_code = UNDEF_SIZE_LE_1;
5921 return TRUE;
5922 }
5923 else
5924 return FALSE;
5925
ef1576a1
AV		 5926 case MVE_VLDRB_GATHER_T1:
5927 if (arm_decode_field (given, 7, 8) == 3)
5928 {
5929 *undefined_code = UNDEF_SIZE_3;
5930 return TRUE;
5931 }
5932 else if ((arm_decode_field (given, 28, 28) == 0)
5933 && (arm_decode_field (given, 7, 8) == 0))
5934 {
5935 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
5936 return TRUE;
5937 }
5938 else
5939 return FALSE;
5940
5941 case MVE_VLDRH_GATHER_T2:
5942 if (arm_decode_field (given, 7, 8) == 3)
5943 {
5944 *undefined_code = UNDEF_SIZE_3;
5945 return TRUE;
5946 }
5947 else if ((arm_decode_field (given, 28, 28) == 0)
5948 && (arm_decode_field (given, 7, 8) == 1))
5949 {
5950 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
5951 return TRUE;
5952 }
5953 else if (arm_decode_field (given, 7, 8) == 0)
5954 {
5955 *undefined_code = UNDEF_SIZE_0;
5956 return TRUE;
5957 }
5958 else
5959 return FALSE;
5960
5961 case MVE_VLDRW_GATHER_T3:
5962 if (arm_decode_field (given, 7, 8) != 2)
5963 {
5964 *undefined_code = UNDEF_SIZE_NOT_2;
5965 return TRUE;
5966 }
5967 else if (arm_decode_field (given, 28, 28) == 0)
5968 {
5969 *undefined_code = UNDEF_NOT_UNSIGNED;
5970 return TRUE;
5971 }
5972 else
5973 return FALSE;
5974
5975 case MVE_VLDRD_GATHER_T4:
5976 if (arm_decode_field (given, 7, 8) != 3)
5977 {
5978 *undefined_code = UNDEF_SIZE_NOT_3;
5979 return TRUE;
5980 }
5981 else if (arm_decode_field (given, 28, 28) == 0)
5982 {
5983 *undefined_code = UNDEF_NOT_UNSIGNED;
5984 return TRUE;
5985 }
5986 else
5987 return FALSE;
5988
5989 case MVE_VSTRB_SCATTER_T1:
5990 if (arm_decode_field (given, 7, 8) == 3)
5991 {
5992 *undefined_code = UNDEF_SIZE_3;
5993 return TRUE;
5994 }
5995 else
5996 return FALSE;
5997
5998 case MVE_VSTRH_SCATTER_T2:
5999 {
6000 unsigned long size = arm_decode_field (given, 7, 8);
6001 if (size == 3)
6002 {
6003 *undefined_code = UNDEF_SIZE_3;
6004 return TRUE;
6005 }
6006 else if (size == 0)
6007 {
6008 *undefined_code = UNDEF_SIZE_0;
6009 return TRUE;
6010 }
6011 else
6012 return FALSE;
6013 }
6014
6015 case MVE_VSTRW_SCATTER_T3:
6016 if (arm_decode_field (given, 7, 8) != 2)
6017 {
6018 *undefined_code = UNDEF_SIZE_NOT_2;
6019 return TRUE;
6020 }
6021 else
6022 return FALSE;
6023
6024 case MVE_VSTRD_SCATTER_T4:
6025 if (arm_decode_field (given, 7, 8) != 3)
6026 {
6027 *undefined_code = UNDEF_SIZE_NOT_3;
6028 return TRUE;
6029 }
6030 else
6031 return FALSE;
6032
bf0b396d
AV		 6033 case MVE_VCVT_FP_FIX_VEC:
6034 {
6035 unsigned long imm6 = arm_decode_field (given, 16, 21);
6036 if ((imm6 & 0x20) == 0)
6037 {
6038 *undefined_code = UNDEF_VCVT_IMM6;
6039 return TRUE;
6040 }
6041
6042 if ((arm_decode_field (given, 9, 9) == 0)
6043 && ((imm6 & 0x30) == 0x20))
6044 {
6045 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6046 return TRUE;
6047 }
6048
6049 return FALSE;
6050 }
6051
f49bb598 6052 case MVE_VNEG_FP:
66dcaa5d 6053 case MVE_VABS_FP:
bf0b396d
AV		 6054 case MVE_VCVT_BETWEEN_FP_INT:
6055 case MVE_VCVT_FROM_FP_TO_INT:
6056 {
6057 unsigned long size = arm_decode_field (given, 18, 19);
6058 if (size == 0)
6059 {
6060 *undefined_code = UNDEF_SIZE_0;
6061 return TRUE;
6062 }
6063 else if (size == 3)
6064 {
6065 *undefined_code = UNDEF_SIZE_3;
6066 return TRUE;
6067 }
6068 else
6069 return FALSE;
6070 }
6071
c507f10b
AV		 6072 case MVE_VMOV_VEC_LANE_TO_GP:
6073 {
6074 unsigned long op1 = arm_decode_field (given, 21, 22);
6075 unsigned long op2 = arm_decode_field (given, 5, 6);
6076 unsigned long u = arm_decode_field (given, 23, 23);
6077
6078 if ((op2 == 0) && (u == 1))
6079 {
6080 if ((op1 == 0) || (op1 == 1))
6081 {
6082 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6083 return TRUE;
6084 }
6085 else
6086 return FALSE;
6087 }
6088 else if (op2 == 2)
6089 {
6090 if ((op1 == 0) || (op1 == 1))
6091 {
6092 *undefined_code = UNDEF_BAD_OP1_OP2;
6093 return TRUE;
6094 }
6095 else
6096 return FALSE;
6097 }
6098
6099 return FALSE;
6100 }
6101
6102 case MVE_VMOV_GP_TO_VEC_LANE:
6103 if (arm_decode_field (given, 5, 6) == 2)
6104 {
6105 unsigned long op1 = arm_decode_field (given, 21, 22);
6106 if ((op1 == 0) || (op1 == 1))
6107 {
6108 *undefined_code = UNDEF_BAD_OP1_OP2;
6109 return TRUE;
6110 }
6111 else
6112 return FALSE;
6113 }
6114 else
6115 return FALSE;
6116
c4a23bf8
SP		 6117 case MVE_VMOV_VEC_TO_VEC:
6118 if ((arm_decode_field (given, 5, 5) == 1)
6119 || (arm_decode_field (given, 22, 22) == 1))
6120 return TRUE;
6121 return FALSE;
6122
c507f10b
AV		 6123 case MVE_VMOV_IMM_TO_VEC:
6124 if (arm_decode_field (given, 5, 5) == 0)
6125 {
6126 unsigned long cmode = arm_decode_field (given, 8, 11);
6127
6128 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6129 {
6130 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6131 return TRUE;
6132 }
6133 else
6134 return FALSE;
6135 }
6136 else
6137 return FALSE;
6138
ed63aa17 6139 case MVE_VSHLL_T2:
14925797
AV		 6140 case MVE_VMOVN:
6141 if (arm_decode_field (given, 18, 19) == 2)
6142 {
6143 *undefined_code = UNDEF_SIZE_2;
6144 return TRUE;
6145 }
6146 else
6147 return FALSE;
6148
d3b63143
AV		 6149 case MVE_VRMLALDAVH:
6150 case MVE_VMLADAV_T1:
6151 case MVE_VMLADAV_T2:
6152 case MVE_VMLALDAV:
6153 if ((arm_decode_field (given, 28, 28) == 1)
6154 && (arm_decode_field (given, 12, 12) == 1))
6155 {
6156 *undefined_code = UNDEF_XCHG_UNS;
6157 return TRUE;
6158 }
6159 else
6160 return FALSE;
6161
ed63aa17
AV		 6162 case MVE_VQSHRN:
6163 case MVE_VQSHRUN:
6164 case MVE_VSHLL_T1:
6165 case MVE_VSHRN:
6166 {
6167 unsigned long sz = arm_decode_field (given, 19, 20);
6168 if (sz == 1)
6169 return FALSE;
6170 else if ((sz & 2) == 2)
6171 return FALSE;
6172 else
6173 {
6174 *undefined_code = UNDEF_SIZE;
6175 return TRUE;
6176 }
6177 }
6178 break;
6179
6180 case MVE_VQSHL_T2:
6181 case MVE_VQSHLU_T3:
6182 case MVE_VRSHR:
6183 case MVE_VSHL_T1:
6184 case MVE_VSHR:
6185 case MVE_VSLI:
6186 case MVE_VSRI:
6187 {
6188 unsigned long sz = arm_decode_field (given, 19, 21);
6189 if ((sz & 7) == 1)
6190 return FALSE;
6191 else if ((sz & 6) == 2)
6192 return FALSE;
6193 else if ((sz & 4) == 4)
6194 return FALSE;
6195 else
6196 {
6197 *undefined_code = UNDEF_SIZE;
6198 return TRUE;
6199 }
6200 }
6201
6202 case MVE_VQRSHRN:
6203 case MVE_VQRSHRUN:
6204 if (arm_decode_field (given, 19, 20) == 0)
6205 {
6206 *undefined_code = UNDEF_SIZE_0;
6207 return TRUE;
6208 }
6209 else
6210 return FALSE;
6211
66dcaa5d
AV		 6212 case MVE_VABS_VEC:
6213 if (arm_decode_field (given, 18, 19) == 3)
6214 {
6215 *undefined_code = UNDEF_SIZE_3;
6216 return TRUE;
6217 }
6218 else
6219 return FALSE;
6220
14b456f2
AV		 6221 case MVE_VQNEG:
6222 case MVE_VQABS:
f49bb598 6223 case MVE_VNEG_VEC:
e523f101
AV		 6224 case MVE_VCLS:
6225 case MVE_VCLZ:
6226 if (arm_decode_field (given, 18, 19) == 3)
6227 {
6228 *undefined_code = UNDEF_SIZE_3;
6229 return TRUE;
6230 }
6231 else
6232 return FALSE;
6233
14b456f2
AV		 6234 case MVE_VREV16:
6235 if (arm_decode_field (given, 18, 19) == 0)
6236 return FALSE;
6237 else
6238 {
6239 *undefined_code = UNDEF_SIZE_NOT_0;
6240 return TRUE;
6241 }
6242
6243 case MVE_VREV32:
6244 {
6245 unsigned long size = arm_decode_field (given, 18, 19);
6246 if ((size & 2) == 2)
6247 {
6248 *undefined_code = UNDEF_SIZE_2;
6249 return TRUE;
6250 }
6251 else
6252 return FALSE;
6253 }
6254
6255 case MVE_VREV64:
6256 if (arm_decode_field (given, 18, 19) != 3)
6257 return FALSE;
6258 else
6259 {
6260 *undefined_code = UNDEF_SIZE_3;
6261 return TRUE;
6262 }
6263
9743db03
AV		 6264 default:
6265 return FALSE;
6266 }
73cd51e5
AV		 6267}
6268
6269/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6270 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6271 why this encoding is unpredictable. */
6272
6273static bfd_boolean
6274is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6275 enum mve_unpredictable *unpredictable_code)
6276{
6277 *unpredictable_code = UNPRED_NONE;
6278
143275ea
AV		 6279 switch (matched_insn)
6280 {
6281 case MVE_VCMP_FP_T2:
6282 case MVE_VPT_FP_T2:
6283 if ((arm_decode_field (given, 12, 12) == 0)
6284 && (arm_decode_field (given, 5, 5) == 1))
6285 {
6286 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6287 return TRUE;
6288 }
6289 else
6290 return FALSE;
73cd51e5 6291
143275ea
AV		 6292 case MVE_VPT_VEC_T4:
6293 case MVE_VPT_VEC_T5:
6294 case MVE_VPT_VEC_T6:
6295 case MVE_VCMP_VEC_T4:
6296 case MVE_VCMP_VEC_T5:
6297 case MVE_VCMP_VEC_T6:
6298 if (arm_decode_field (given, 0, 3) == 0xd)
6299 {
6300 *unpredictable_code = UNPRED_R13;
6301 return TRUE;
6302 }
6303 else
6304 return FALSE;
c1e26897 6305
9743db03
AV		 6306 case MVE_VDUP:
6307 {
6308 unsigned long gpr = arm_decode_field (given, 12, 15);
6309 if (gpr == 0xd)
6310 {
6311 *unpredictable_code = UNPRED_R13;
6312 return TRUE;
6313 }
6314 else if (gpr == 0xf)
6315 {
6316 *unpredictable_code = UNPRED_R15;
6317 return TRUE;
6318 }
6319
6320 return FALSE;
6321 }
6322
14b456f2
AV		 6323 case MVE_VQADD_T2:
6324 case MVE_VQSUB_T2:
f49bb598
AV		 6325 case MVE_VMUL_FP_T2:
6326 case MVE_VMUL_VEC_T2:
56858bea 6327 case MVE_VMLA:
e523f101 6328 case MVE_VBRSR:
66dcaa5d
AV		 6329 case MVE_VADD_FP_T2:
6330 case MVE_VSUB_FP_T2:
6331 case MVE_VADD_VEC_T2:
6332 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6333 case MVE_VQRSHL_T2:
6334 case MVE_VQSHL_T1:
6335 case MVE_VRSHL_T2:
6336 case MVE_VSHL_T2:
6337 case MVE_VSHLC:
d3b63143
AV		 6338 case MVE_VQDMLAH:
6339 case MVE_VQRDMLAH:
6340 case MVE_VQDMLASH:
6341 case MVE_VQRDMLASH:
6342 case MVE_VQDMULH_T3:
6343 case MVE_VQRDMULH_T4:
6344 case MVE_VMLAS:
9743db03
AV		 6345 case MVE_VFMA_FP_SCALAR:
6346 case MVE_VFMAS_FP_SCALAR:
6347 case MVE_VHADD_T2:
6348 case MVE_VHSUB_T2:
6349 {
6350 unsigned long gpr = arm_decode_field (given, 0, 3);
6351 if (gpr == 0xd)
6352 {
6353 *unpredictable_code = UNPRED_R13;
6354 return TRUE;
6355 }
6356 else if (gpr == 0xf)
6357 {
6358 *unpredictable_code = UNPRED_R15;
6359 return TRUE;
6360 }
6361
6362 return FALSE;
6363 }
6364
04d54ace
AV		 6365 case MVE_VLD2:
6366 case MVE_VST2:
6367 {
6368 unsigned long rn = arm_decode_field (given, 16, 19);
6369
6370 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6371 {
6372 *unpredictable_code = UNPRED_R13_AND_WB;
6373 return TRUE;
6374 }
6375
6376 if (rn == 0xf)
6377 {
6378 *unpredictable_code = UNPRED_R15;
6379 return TRUE;
6380 }
6381
6382 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6383 {
6384 *unpredictable_code = UNPRED_Q_GT_6;
6385 return TRUE;
6386 }
6387 else
6388 return FALSE;
6389 }
6390
6391 case MVE_VLD4:
6392 case MVE_VST4:
6393 {
6394 unsigned long rn = arm_decode_field (given, 16, 19);
6395
6396 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6397 {
6398 *unpredictable_code = UNPRED_R13_AND_WB;
6399 return TRUE;
6400 }
6401
6402 if (rn == 0xf)
6403 {
6404 *unpredictable_code = UNPRED_R15;
6405 return TRUE;
6406 }
6407
6408 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6409 {
6410 *unpredictable_code = UNPRED_Q_GT_4;
6411 return TRUE;
6412 }
6413 else
6414 return FALSE;
6415 }
6416
aef6d006
AV		 6417 case MVE_VLDRB_T5:
6418 case MVE_VLDRH_T6:
6419 case MVE_VLDRW_T7:
6420 case MVE_VSTRB_T5:
6421 case MVE_VSTRH_T6:
6422 case MVE_VSTRW_T7:
6423 {
6424 unsigned long rn = arm_decode_field (given, 16, 19);
6425
6426 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6427 {
6428 *unpredictable_code = UNPRED_R13_AND_WB;
6429 return TRUE;
6430 }
6431 else if (rn == 0xf)
6432 {
6433 *unpredictable_code = UNPRED_R15;
6434 return TRUE;
6435 }
6436 else
6437 return FALSE;
6438 }
6439
ef1576a1
AV		 6440 case MVE_VLDRB_GATHER_T1:
6441 if (arm_decode_field (given, 0, 0) == 1)
6442 {
6443 *unpredictable_code = UNPRED_OS;
6444 return TRUE;
6445 }
6446
6447 /* fall through. */
6448 /* To handle common code with T2-T4 variants. */
6449 case MVE_VLDRH_GATHER_T2:
6450 case MVE_VLDRW_GATHER_T3:
6451 case MVE_VLDRD_GATHER_T4:
6452 {
6453 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6454 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6455
6456 if (qd == qm)
6457 {
6458 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6459 return TRUE;
6460 }
6461
6462 if (arm_decode_field (given, 16, 19) == 0xf)
6463 {
6464 *unpredictable_code = UNPRED_R15;
6465 return TRUE;
6466 }
6467
6468 return FALSE;
6469 }
6470
6471 case MVE_VLDRW_GATHER_T5:
6472 case MVE_VLDRD_GATHER_T6:
6473 {
6474 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6475 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6476
6477 if (qd == qm)
6478 {
6479 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6480 return TRUE;
6481 }
6482 else
6483 return FALSE;
6484 }
6485
6486 case MVE_VSTRB_SCATTER_T1:
6487 if (arm_decode_field (given, 16, 19) == 0xf)
6488 {
6489 *unpredictable_code = UNPRED_R15;
6490 return TRUE;
6491 }
6492 else if (arm_decode_field (given, 0, 0) == 1)
6493 {
6494 *unpredictable_code = UNPRED_OS;
6495 return TRUE;
6496 }
6497 else
6498 return FALSE;
6499
6500 case MVE_VSTRH_SCATTER_T2:
6501 case MVE_VSTRW_SCATTER_T3:
6502 case MVE_VSTRD_SCATTER_T4:
6503 if (arm_decode_field (given, 16, 19) == 0xf)
6504 {
6505 *unpredictable_code = UNPRED_R15;
6506 return TRUE;
6507 }
6508 else
6509 return FALSE;
6510
c507f10b
AV		 6511 case MVE_VMOV2_VEC_LANE_TO_GP:
6512 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6513 case MVE_VCVT_BETWEEN_FP_INT:
6514 case MVE_VCVT_FROM_FP_TO_INT:
6515 {
6516 unsigned long rt = arm_decode_field (given, 0, 3);
6517 unsigned long rt2 = arm_decode_field (given, 16, 19);
6518
6519 if ((rt == 0xd) || (rt2 == 0xd))
6520 {
6521 *unpredictable_code = UNPRED_R13;
6522 return TRUE;
6523 }
6524 else if ((rt == 0xf) || (rt2 == 0xf))
6525 {
6526 *unpredictable_code = UNPRED_R15;
6527 return TRUE;
6528 }
6529 else if (rt == rt2)
6530 {
6531 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6532 return TRUE;
6533 }
6534
6535 return FALSE;
6536 }
6537
56858bea
AV		 6538 case MVE_VMAXV:
6539 case MVE_VMAXAV:
6540 case MVE_VMAXNMV_FP:
6541 case MVE_VMAXNMAV_FP:
6542 case MVE_VMINNMV_FP:
6543 case MVE_VMINNMAV_FP:
6544 case MVE_VMINV:
6545 case MVE_VMINAV:
66dcaa5d 6546 case MVE_VABAV:
c507f10b
AV		 6547 case MVE_VMOV_HFP_TO_GP:
6548 case MVE_VMOV_GP_TO_VEC_LANE:
6549 case MVE_VMOV_VEC_LANE_TO_GP:
6550 {
6551 unsigned long rda = arm_decode_field (given, 12, 15);
6552 if (rda == 0xd)
6553 {
6554 *unpredictable_code = UNPRED_R13;
6555 return TRUE;
6556 }
6557 else if (rda == 0xf)
6558 {
6559 *unpredictable_code = UNPRED_R15;
6560 return TRUE;
6561 }
6562
6563 return FALSE;
6564 }
6565
14925797
AV		 6566 case MVE_VMULL_INT:
6567 {
6568 unsigned long Qd;
6569 unsigned long Qm;
6570 unsigned long Qn;
6571
6572 if (arm_decode_field (given, 20, 21) == 2)
6573 {
6574 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6575 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6576 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6577
6578 if ((Qd == Qn) || (Qd == Qm))
6579 {
6580 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6581 return TRUE;
6582 }
6583 else
6584 return FALSE;
6585 }
6586 else
6587 return FALSE;
6588 }
6589
897b9bbc 6590 case MVE_VCMUL_FP:
14925797
AV		 6591 case MVE_VQDMULL_T1:
6592 {
6593 unsigned long Qd;
6594 unsigned long Qm;
6595 unsigned long Qn;
6596
6597 if (arm_decode_field (given, 28, 28) == 1)
6598 {
6599 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6600 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6601 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6602
6603 if ((Qd == Qn) || (Qd == Qm))
6604 {
6605 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6606 return TRUE;
6607 }
6608 else
6609 return FALSE;
6610 }
6611 else
6612 return FALSE;
6613 }
6614
6615 case MVE_VQDMULL_T2:
6616 {
6617 unsigned long gpr = arm_decode_field (given, 0, 3);
6618 if (gpr == 0xd)
6619 {
6620 *unpredictable_code = UNPRED_R13;
6621 return TRUE;
6622 }
6623 else if (gpr == 0xf)
6624 {
6625 *unpredictable_code = UNPRED_R15;
6626 return TRUE;
6627 }
6628
6629 if (arm_decode_field (given, 28, 28) == 1)
6630 {
6631 unsigned long Qd
6632 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6633 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6634
a9d96ab9 6635 if (Qd == Qn)
14925797
AV		 6636 {
6637 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6638 return TRUE;
6639 }
6640 else
6641 return FALSE;
6642 }
6643
6644 return FALSE;
6645 }
6646
d3b63143
AV		 6647 case MVE_VMLSLDAV:
6648 case MVE_VRMLSLDAVH:
6649 case MVE_VMLALDAV:
6650 case MVE_VADDLV:
6651 if (arm_decode_field (given, 20, 22) == 6)
6652 {
6653 *unpredictable_code = UNPRED_R13;
6654 return TRUE;
6655 }
6656 else
6657 return FALSE;
6658
1c8f2df8
AV		 6659 case MVE_VDWDUP:
6660 case MVE_VIWDUP:
6661 if (arm_decode_field (given, 1, 3) == 6)
6662 {
6663 *unpredictable_code = UNPRED_R13;
6664 return TRUE;
6665 }
6666 else
6667 return FALSE;
6668
897b9bbc
AV		 6669 case MVE_VCADD_VEC:
6670 case MVE_VHCADD:
6671 {
6672 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6673 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6674 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6675 {
6676 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6677 return TRUE;
6678 }
6679 else
6680 return FALSE;
6681 }
6682
6683 case MVE_VCADD_FP:
6684 {
6685 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6686 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6687 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6688 {
6689 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6690 return TRUE;
6691 }
6692 else
6693 return FALSE;
6694 }
6695
6696 case MVE_VCMLA_FP:
6697 {
6698 unsigned long Qda;
6699 unsigned long Qm;
6700 unsigned long Qn;
6701
6702 if (arm_decode_field (given, 20, 20) == 1)
6703 {
6704 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6705 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6706 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6707
6708 if ((Qda == Qn) || (Qda == Qm))
6709 {
6710 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6711 return TRUE;
6712 }
6713 else
6714 return FALSE;
6715 }
6716 else
6717 return FALSE;
6718
6719 }
6720
e523f101
AV		 6721 case MVE_VCTP:
6722 if (arm_decode_field (given, 16, 19) == 0xd)
6723 {
6724 *unpredictable_code = UNPRED_R13;
6725 return TRUE;
6726 }
6727 else
6728 return FALSE;
6729
14b456f2
AV		 6730 case MVE_VREV64:
6731 {
6732 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6733 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6734
6735 if (qd == qm)
6736 {
6737 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6738 return TRUE;
6739 }
6740 else
6741 return FALSE;
6742 }
6743
23d00a41
SD		 6744 case MVE_LSLL:
6745 case MVE_LSLLI:
6746 case MVE_LSRL:
6747 case MVE_ASRL:
6748 case MVE_ASRLI:
6749 case MVE_UQSHLL:
6750 case MVE_UQRSHLL:
6751 case MVE_URSHRL:
6752 case MVE_SRSHRL:
6753 case MVE_SQSHLL:
6754 case MVE_SQRSHRL:
6755 {
6756 unsigned long gpr = arm_decode_field (given, 9, 11);
6757 gpr = ((gpr << 1) | 1);
6758 if (gpr == 0xd)
6759 {
6760 *unpredictable_code = UNPRED_R13;
6761 return TRUE;
6762 }
6763 else if (gpr == 0xf)
6764 {
6765 *unpredictable_code = UNPRED_R15;
6766 return TRUE;
6767 }
6768
6769 return FALSE;
6770 }
6771
143275ea
AV		 6772 default:
6773 return FALSE;
6774 }
6775}
c1e26897 6776
c507f10b
AV		 6777static void
6778print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6779{
6780 unsigned long op1 = arm_decode_field (given, 21, 22);
6781 unsigned long op2 = arm_decode_field (given, 5, 6);
6782 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6783 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6784 void *stream = info->stream;
6785 fprintf_ftype func = info->fprintf_func;
6786
6787 if ((op1 & 0x2) == 0x2)
6788 {
43dd7626 6789 index_operand = op2;
c507f10b
AV		 6790 esize = 8;
6791 }
6792 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6793 {
43dd7626 6794 index_operand = op2 >> 1;
c507f10b
AV		 6795 esize = 16;
6796 }
6797 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6798 {
43dd7626 6799 index_operand = 0;
c507f10b
AV		 6800 esize = 32;
6801 }
6802 else
6803 {
6804 func (stream, "<undefined index>");
6805 return;
6806 }
6807
6808 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6809 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6810
6811 func (stream, "%lu", idx);
6812}
6813
6814/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6815 in length and integer of floating-point type. */
6816static void
6817print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6818 unsigned int ibit_loc, const struct mopcode32 *insn)
6819{
6820 int bits = 0;
6821 int cmode = (given >> 8) & 0xf;
6822 int op = (given >> 5) & 0x1;
6823 unsigned long value = 0, hival = 0;
6824 unsigned shift;
6825 int size = 0;
6826 int isfloat = 0;
6827 void *stream = info->stream;
6828 fprintf_ftype func = info->fprintf_func;
6829
6830 /* On Neon the 'i' bit is at bit 24, on mve it is
6831 at bit 28. */
6832 bits |= ((given >> ibit_loc) & 1) << 7;
6833 bits |= ((given >> 16) & 7) << 4;
6834 bits |= ((given >> 0) & 15) << 0;
6835
6836 if (cmode < 8)
6837 {
6838 shift = (cmode >> 1) & 3;
6839 value = (unsigned long) bits << (8 * shift);
6840 size = 32;
6841 }
6842 else if (cmode < 12)
6843 {
6844 shift = (cmode >> 1) & 1;
6845 value = (unsigned long) bits << (8 * shift);
6846 size = 16;
6847 }
6848 else if (cmode < 14)
6849 {
6850 shift = (cmode & 1) + 1;
6851 value = (unsigned long) bits << (8 * shift);
6852 value |= (1ul << (8 * shift)) - 1;
6853 size = 32;
6854 }
6855 else if (cmode == 14)
6856 {
6857 if (op)
6858 {
6859 /* Bit replication into bytes. */
6860 int ix;
6861 unsigned long mask;
6862
6863 value = 0;
6864 hival = 0;
6865 for (ix = 7; ix >= 0; ix--)
6866 {
6867 mask = ((bits >> ix) & 1) ? 0xff : 0;
6868 if (ix <= 3)
6869 value = (value << 8) | mask;
6870 else
6871 hival = (hival << 8) | mask;
6872 }
6873 size = 64;
6874 }
6875 else
6876 {
6877 /* Byte replication. */
6878 value = (unsigned long) bits;
6879 size = 8;
6880 }
6881 }
6882 else if (!op)
6883 {
6884 /* Floating point encoding. */
6885 int tmp;
6886
6887 value = (unsigned long) (bits & 0x7f) << 19;
6888 value |= (unsigned long) (bits & 0x80) << 24;
6889 tmp = bits & 0x40 ? 0x3c : 0x40;
6890 value |= (unsigned long) tmp << 24;
6891 size = 32;
6892 isfloat = 1;
6893 }
6894 else
6895 {
6896 func (stream, "<illegal constant %.8x:%x:%x>",
6897 bits, cmode, op);
6898 size = 32;
6899 return;
6900 }
6901
6902 // printU determines whether the immediate value should be printed as
6903 // unsigned.
6904 unsigned printU = 0;
6905 switch (insn->mve_op)
6906 {
6907 default:
6908 break;
6909 // We want this for instructions that don't have a 'signed' type
6910 case MVE_VBIC_IMM:
6911 case MVE_VORR_IMM:
6912 case MVE_VMVN_IMM:
6913 case MVE_VMOV_IMM_TO_VEC:
6914 printU = 1;
6915 break;
6916 }
6917 switch (size)
6918 {
6919 case 8:
6920 func (stream, "#%ld\t; 0x%.2lx", value, value);
6921 break;
6922
6923 case 16:
6924 func (stream,
6925 printU
6926 ? "#%lu\t; 0x%.4lx"
6927 : "#%ld\t; 0x%.4lx", value, value);
6928 break;
6929
6930 case 32:
6931 if (isfloat)
6932 {
6933 unsigned char valbytes[4];
6934 double fvalue;
6935
6936 /* Do this a byte at a time so we don't have to
6937 worry about the host's endianness. */
6938 valbytes[0] = value & 0xff;
6939 valbytes[1] = (value >> 8) & 0xff;
6940 valbytes[2] = (value >> 16) & 0xff;
6941 valbytes[3] = (value >> 24) & 0xff;
6942
6943 floatformat_to_double
6944 (& floatformat_ieee_single_little, valbytes,
6945 & fvalue);
6946
6947 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
6948 value);
6949 }
6950 else
6951 func (stream,
6952 printU
6953 ? "#%lu\t; 0x%.8lx"
6954 : "#%ld\t; 0x%.8lx",
6955 (long) (((value & 0x80000000L) != 0)
6956 && !printU
6957 ? value | ~0xffffffffL : value),
6958 value);
6959 break;
6960
6961 case 64:
6962 func (stream, "#0x%.8lx%.8lx", hival, value);
6963 break;
6964
6965 default:
6966 abort ();
6967 }
6968
6969}
6970
73cd51e5
AV		 6971static void
6972print_mve_undefined (struct disassemble_info *info,
6973 enum mve_undefined undefined_code)
6974{
6975 void *stream = info->stream;
6976 fprintf_ftype func = info->fprintf_func;
6977
6978 func (stream, "\t\tundefined instruction: ");
6979
6980 switch (undefined_code)
6981 {
ed63aa17
AV		 6982 case UNDEF_SIZE:
6983 func (stream, "illegal size");
6984 break;
6985
aef6d006
AV		 6986 case UNDEF_SIZE_0:
6987 func (stream, "size equals zero");
6988 break;
6989
c507f10b
AV		 6990 case UNDEF_SIZE_2:
6991 func (stream, "size equals two");
6992 break;
6993
9743db03
AV		 6994 case UNDEF_SIZE_3:
6995 func (stream, "size equals three");
6996 break;
6997
aef6d006
AV		 6998 case UNDEF_SIZE_LE_1:
6999 func (stream, "size <= 1");
7000 break;
7001
14b456f2
AV		 7002 case UNDEF_SIZE_NOT_0:
7003 func (stream, "size not equal to 0");
7004 break;
7005
ef1576a1
AV		 7006 case UNDEF_SIZE_NOT_2:
7007 func (stream, "size not equal to 2");
7008 break;
7009
7010 case UNDEF_SIZE_NOT_3:
7011 func (stream, "size not equal to 3");
7012 break;
7013
7014 case UNDEF_NOT_UNS_SIZE_0:
7015 func (stream, "not unsigned and size = zero");
7016 break;
7017
7018 case UNDEF_NOT_UNS_SIZE_1:
7019 func (stream, "not unsigned and size = one");
7020 break;
7021
7022 case UNDEF_NOT_UNSIGNED:
7023 func (stream, "not unsigned");
7024 break;
7025
bf0b396d
AV		 7026 case UNDEF_VCVT_IMM6:
7027 func (stream, "invalid imm6");
7028 break;
7029
7030 case UNDEF_VCVT_FSI_IMM6:
7031 func (stream, "fsi = 0 and invalid imm6");
7032 break;
7033
c507f10b
AV		 7034 case UNDEF_BAD_OP1_OP2:
7035 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7036 break;
7037
7038 case UNDEF_BAD_U_OP1_OP2:
7039 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7040 break;
7041
7042 case UNDEF_OP_0_BAD_CMODE:
7043 func (stream, "op field equal 0 and bad cmode");
7044 break;
7045
d3b63143
AV		 7046 case UNDEF_XCHG_UNS:
7047 func (stream, "exchange and unsigned together");
7048 break;
7049
73cd51e5
AV		 7050 case UNDEF_NONE:
7051 break;
7052 }
7053
7054}
7055
7056static void
7057print_mve_unpredictable (struct disassemble_info *info,
7058 enum mve_unpredictable unpredict_code)
7059{
7060 void *stream = info->stream;
7061 fprintf_ftype func = info->fprintf_func;
7062
7063 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7064
7065 switch (unpredict_code)
7066 {
7067 case UNPRED_IT_BLOCK:
7068 func (stream, "mve instruction in it block");
7069 break;
7070
143275ea
AV		 7071 case UNPRED_FCA_0_FCB_1:
7072 func (stream, "condition bits, fca = 0 and fcb = 1");
7073 break;
7074
7075 case UNPRED_R13:
7076 func (stream, "use of r13 (sp)");
7077 break;
7078
9743db03
AV		 7079 case UNPRED_R15:
7080 func (stream, "use of r15 (pc)");
7081 break;
7082
04d54ace
AV		 7083 case UNPRED_Q_GT_4:
7084 func (stream, "start register block > r4");
7085 break;
7086
7087 case UNPRED_Q_GT_6:
7088 func (stream, "start register block > r6");
7089 break;
7090
7091 case UNPRED_R13_AND_WB:
7092 func (stream, "use of r13 and write back");
7093 break;
7094
ef1576a1
AV		 7095 case UNPRED_Q_REGS_EQUAL:
7096 func (stream,
7097 "same vector register used for destination and other operand");
7098 break;
7099
7100 case UNPRED_OS:
7101 func (stream, "use of offset scaled");
7102 break;
7103
bf0b396d
AV		 7104 case UNPRED_GP_REGS_EQUAL:
7105 func (stream, "same general-purpose register used for both operands");
7106 break;
7107
c507f10b
AV		 7108 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7109 func (stream, "use of identical q registers and size = 1");
7110 break;
7111
7112 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7113 func (stream, "use of identical q registers and size = 1");
7114 break;
7115
73cd51e5
AV		 7116 case UNPRED_NONE:
7117 break;
7118 }
7119}
7120
04d54ace
AV		 7121/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7122
7123static void
7124print_mve_register_blocks (struct disassemble_info *info,
7125 unsigned long given,
7126 enum mve_instructions matched_insn)
7127{
7128 void *stream = info->stream;
7129 fprintf_ftype func = info->fprintf_func;
7130
7131 unsigned long q_reg_start = arm_decode_field_multiple (given,
7132 13, 15,
7133 22, 22);
7134 switch (matched_insn)
7135 {
7136 case MVE_VLD2:
7137 case MVE_VST2:
7138 if (q_reg_start <= 6)
7139 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7140 else
7141 func (stream, "<illegal reg q%ld>", q_reg_start);
7142 break;
7143
7144 case MVE_VLD4:
7145 case MVE_VST4:
7146 if (q_reg_start <= 4)
7147 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7148 q_reg_start + 1, q_reg_start + 2,
7149 q_reg_start + 3);
7150 else
7151 func (stream, "<illegal reg q%ld>", q_reg_start);
7152 break;
7153
7154 default:
7155 break;
7156 }
7157}
7158
bf0b396d
AV		 7159static void
7160print_mve_rounding_mode (struct disassemble_info *info,
7161 unsigned long given,
7162 enum mve_instructions matched_insn)
7163{
7164 void *stream = info->stream;
7165 fprintf_ftype func = info->fprintf_func;
7166
7167 switch (matched_insn)
7168 {
7169 case MVE_VCVT_FROM_FP_TO_INT:
7170 {
7171 switch (arm_decode_field (given, 8, 9))
7172 {
7173 case 0:
7174 func (stream, "a");
7175 break;
7176
7177 case 1:
7178 func (stream, "n");
7179 break;
7180
7181 case 2:
7182 func (stream, "p");
7183 break;
7184
7185 case 3:
7186 func (stream, "m");
7187 break;
7188
7189 default:
7190 break;
7191 }
7192 }
7193 break;
7194
7195 case MVE_VRINT_FP:
7196 {
7197 switch (arm_decode_field (given, 7, 9))
7198 {
7199 case 0:
7200 func (stream, "n");
7201 break;
7202
7203 case 1:
7204 func (stream, "x");
7205 break;
7206
7207 case 2:
7208 func (stream, "a");
7209 break;
7210
7211 case 3:
7212 func (stream, "z");
7213 break;
7214
7215 case 5:
7216 func (stream, "m");
7217 break;
7218
7219 case 7:
7220 func (stream, "p");
7221
7222 case 4:
7223 case 6:
7224 default:
7225 break;
7226 }
7227 }
7228 break;
7229
7230 default:
7231 break;
7232 }
7233}
7234
7235static void
7236print_mve_vcvt_size (struct disassemble_info *info,
7237 unsigned long given,
7238 enum mve_instructions matched_insn)
7239{
7240 unsigned long mode = 0;
7241 void *stream = info->stream;
7242 fprintf_ftype func = info->fprintf_func;
7243
7244 switch (matched_insn)
7245 {
7246 case MVE_VCVT_FP_FIX_VEC:
7247 {
7248 mode = (((given & 0x200) >> 7)
7249 | ((given & 0x10000000) >> 27)
7250 | ((given & 0x100) >> 8));
7251
7252 switch (mode)
7253 {
7254 case 0:
7255 func (stream, "f16.s16");
7256 break;
7257
7258 case 1:
7259 func (stream, "s16.f16");
7260 break;
7261
7262 case 2:
7263 func (stream, "f16.u16");
7264 break;
7265
7266 case 3:
7267 func (stream, "u16.f16");
7268 break;
7269
7270 case 4:
7271 func (stream, "f32.s32");
7272 break;
7273
7274 case 5:
7275 func (stream, "s32.f32");
7276 break;
7277
7278 case 6:
7279 func (stream, "f32.u32");
7280 break;
7281
7282 case 7:
7283 func (stream, "u32.f32");
7284 break;
7285
7286 default:
7287 break;
7288 }
7289 break;
7290 }
7291 case MVE_VCVT_BETWEEN_FP_INT:
7292 {
7293 unsigned long size = arm_decode_field (given, 18, 19);
7294 unsigned long op = arm_decode_field (given, 7, 8);
7295
7296 if (size == 1)
7297 {
7298 switch (op)
7299 {
7300 case 0:
7301 func (stream, "f16.s16");
7302 break;
7303
7304 case 1:
7305 func (stream, "f16.u16");
7306 break;
7307
7308 case 2:
7309 func (stream, "s16.f16");
7310 break;
7311
7312 case 3:
7313 func (stream, "u16.f16");
7314 break;
7315
7316 default:
7317 break;
7318 }
7319 }
7320 else if (size == 2)
7321 {
7322 switch (op)
7323 {
7324 case 0:
7325 func (stream, "f32.s32");
7326 break;
7327
7328 case 1:
7329 func (stream, "f32.u32");
7330 break;
7331
7332 case 2:
7333 func (stream, "s32.f32");
7334 break;
7335
7336 case 3:
7337 func (stream, "u32.f32");
7338 break;
7339 }
7340 }
7341 }
7342 break;
7343
7344 case MVE_VCVT_FP_HALF_FP:
7345 {
7346 unsigned long op = arm_decode_field (given, 28, 28);
7347 if (op == 0)
7348 func (stream, "f16.f32");
7349 else if (op == 1)
7350 func (stream, "f32.f16");
7351 }
7352 break;
7353
7354 case MVE_VCVT_FROM_FP_TO_INT:
7355 {
7356 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7357
7358 switch (size)
7359 {
7360 case 2:
7361 func (stream, "s16.f16");
7362 break;
7363
7364 case 3:
7365 func (stream, "u16.f16");
7366 break;
7367
7368 case 4:
7369 func (stream, "s32.f32");
7370 break;
7371
7372 case 5:
7373 func (stream, "u32.f32");
7374 break;
7375
7376 default:
7377 break;
7378 }
7379 }
7380 break;
7381
7382 default:
7383 break;
7384 }
7385}
7386
897b9bbc
AV		 7387static void
7388print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7389 unsigned long rot_width)
7390{
7391 void *stream = info->stream;
7392 fprintf_ftype func = info->fprintf_func;
7393
7394 if (rot_width == 1)
7395 {
7396 switch (rot)
7397 {
7398 case 0:
7399 func (stream, "90");
7400 break;
7401 case 1:
7402 func (stream, "270");
7403 break;
7404 default:
7405 break;
7406 }
7407 }
7408 else if (rot_width == 2)
7409 {
7410 switch (rot)
7411 {
7412 case 0:
7413 func (stream, "0");
7414 break;
7415 case 1:
7416 func (stream, "90");
7417 break;
7418 case 2:
7419 func (stream, "180");
7420 break;
7421 case 3:
7422 func (stream, "270");
7423 break;
7424 default:
7425 break;
7426 }
7427 }
7428}
7429
143275ea
AV		 7430static void
7431print_instruction_predicate (struct disassemble_info *info)
7432{
7433 void *stream = info->stream;
7434 fprintf_ftype func = info->fprintf_func;
7435
7436 if (vpt_block_state.next_pred_state == PRED_THEN)
7437 func (stream, "t");
7438 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7439 func (stream, "e");
7440}
7441
7442static void
7443print_mve_size (struct disassemble_info *info,
7444 unsigned long size,
7445 enum mve_instructions matched_insn)
7446{
7447 void *stream = info->stream;
7448 fprintf_ftype func = info->fprintf_func;
7449
7450 switch (matched_insn)
7451 {
66dcaa5d
AV		 7452 case MVE_VABAV:
7453 case MVE_VABD_VEC:
7454 case MVE_VABS_FP:
7455 case MVE_VABS_VEC:
7456 case MVE_VADD_VEC_T1:
7457 case MVE_VADD_VEC_T2:
d3b63143 7458 case MVE_VADDV:
e523f101 7459 case MVE_VBRSR:
897b9bbc 7460 case MVE_VCADD_VEC:
e523f101
AV		 7461 case MVE_VCLS:
7462 case MVE_VCLZ:
143275ea
AV		 7463 case MVE_VCMP_VEC_T1:
7464 case MVE_VCMP_VEC_T2:
7465 case MVE_VCMP_VEC_T3:
7466 case MVE_VCMP_VEC_T4:
7467 case MVE_VCMP_VEC_T5:
7468 case MVE_VCMP_VEC_T6:
e523f101 7469 case MVE_VCTP:
1c8f2df8
AV		 7470 case MVE_VDDUP:
7471 case MVE_VDWDUP:
9743db03
AV		 7472 case MVE_VHADD_T1:
7473 case MVE_VHADD_T2:
897b9bbc 7474 case MVE_VHCADD:
9743db03
AV		 7475 case MVE_VHSUB_T1:
7476 case MVE_VHSUB_T2:
1c8f2df8
AV		 7477 case MVE_VIDUP:
7478 case MVE_VIWDUP:
04d54ace
AV		 7479 case MVE_VLD2:
7480 case MVE_VLD4:
ef1576a1
AV		 7481 case MVE_VLDRB_GATHER_T1:
7482 case MVE_VLDRH_GATHER_T2:
7483 case MVE_VLDRW_GATHER_T3:
7484 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7485 case MVE_VLDRB_T1:
7486 case MVE_VLDRH_T2:
56858bea
AV		 7487 case MVE_VMAX:
7488 case MVE_VMAXA:
7489 case MVE_VMAXV:
7490 case MVE_VMAXAV:
7491 case MVE_VMIN:
7492 case MVE_VMINA:
7493 case MVE_VMINV:
7494 case MVE_VMINAV:
7495 case MVE_VMLA:
d3b63143 7496 case MVE_VMLAS:
f49bb598
AV		 7497 case MVE_VMUL_VEC_T1:
7498 case MVE_VMUL_VEC_T2:
7499 case MVE_VMULH:
7500 case MVE_VRMULH:
7501 case MVE_VMULL_INT:
7502 case MVE_VNEG_FP:
7503 case MVE_VNEG_VEC:
143275ea
AV		 7504 case MVE_VPT_VEC_T1:
7505 case MVE_VPT_VEC_T2:
7506 case MVE_VPT_VEC_T3:
7507 case MVE_VPT_VEC_T4:
7508 case MVE_VPT_VEC_T5:
7509 case MVE_VPT_VEC_T6:
14b456f2
AV		 7510 case MVE_VQABS:
7511 case MVE_VQADD_T1:
7512 case MVE_VQADD_T2:
d3b63143
AV		 7513 case MVE_VQDMLADH:
7514 case MVE_VQRDMLADH:
7515 case MVE_VQDMLAH:
7516 case MVE_VQRDMLAH:
7517 case MVE_VQDMLASH:
7518 case MVE_VQRDMLASH:
7519 case MVE_VQDMLSDH:
7520 case MVE_VQRDMLSDH:
7521 case MVE_VQDMULH_T1:
7522 case MVE_VQRDMULH_T2:
7523 case MVE_VQDMULH_T3:
7524 case MVE_VQRDMULH_T4:
14b456f2 7525 case MVE_VQNEG:
ed63aa17
AV		 7526 case MVE_VQRSHL_T1:
7527 case MVE_VQRSHL_T2:
7528 case MVE_VQSHL_T1:
7529 case MVE_VQSHL_T4:
14b456f2
AV		 7530 case MVE_VQSUB_T1:
7531 case MVE_VQSUB_T2:
7532 case MVE_VREV32:
7533 case MVE_VREV64:
9743db03 7534 case MVE_VRHADD:
bf0b396d 7535 case MVE_VRINT_FP:
ed63aa17
AV		 7536 case MVE_VRSHL_T1:
7537 case MVE_VRSHL_T2:
7538 case MVE_VSHL_T2:
7539 case MVE_VSHL_T3:
7540 case MVE_VSHLL_T2:
04d54ace
AV		 7541 case MVE_VST2:
7542 case MVE_VST4:
ef1576a1
AV		 7543 case MVE_VSTRB_SCATTER_T1:
7544 case MVE_VSTRH_SCATTER_T2:
7545 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7546 case MVE_VSTRB_T1:
7547 case MVE_VSTRH_T2:
66dcaa5d
AV		 7548 case MVE_VSUB_VEC_T1:
7549 case MVE_VSUB_VEC_T2:
143275ea
AV		 7550 if (size <= 3)
7551 func (stream, "%s", mve_vec_sizename[size]);
7552 else
7553 func (stream, "<undef size>");
7554 break;
7555
66dcaa5d
AV		 7556 case MVE_VABD_FP:
7557 case MVE_VADD_FP_T1:
7558 case MVE_VADD_FP_T2:
7559 case MVE_VSUB_FP_T1:
7560 case MVE_VSUB_FP_T2:
143275ea
AV		 7561 case MVE_VCMP_FP_T1:
7562 case MVE_VCMP_FP_T2:
9743db03
AV		 7563 case MVE_VFMA_FP_SCALAR:
7564 case MVE_VFMA_FP:
7565 case MVE_VFMS_FP:
7566 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7567 case MVE_VMAXNM_FP:
7568 case MVE_VMAXNMA_FP:
7569 case MVE_VMAXNMV_FP:
7570 case MVE_VMAXNMAV_FP:
7571 case MVE_VMINNM_FP:
7572 case MVE_VMINNMA_FP:
7573 case MVE_VMINNMV_FP:
7574 case MVE_VMINNMAV_FP:
f49bb598
AV		 7575 case MVE_VMUL_FP_T1:
7576 case MVE_VMUL_FP_T2:
143275ea
AV		 7577 case MVE_VPT_FP_T1:
7578 case MVE_VPT_FP_T2:
7579 if (size == 0)
7580 func (stream, "32");
7581 else if (size == 1)
7582 func (stream, "16");
7583 break;
7584
897b9bbc
AV		 7585 case MVE_VCADD_FP:
7586 case MVE_VCMLA_FP:
7587 case MVE_VCMUL_FP:
d3b63143
AV		 7588 case MVE_VMLADAV_T1:
7589 case MVE_VMLALDAV:
7590 case MVE_VMLSDAV_T1:
7591 case MVE_VMLSLDAV:
14925797
AV		 7592 case MVE_VMOVN:
7593 case MVE_VQDMULL_T1:
7594 case MVE_VQDMULL_T2:
7595 case MVE_VQMOVN:
7596 case MVE_VQMOVUN:
7597 if (size == 0)
7598 func (stream, "16");
7599 else if (size == 1)
7600 func (stream, "32");
7601 break;
7602
7603 case MVE_VMOVL:
7604 if (size == 1)
7605 func (stream, "8");
7606 else if (size == 2)
7607 func (stream, "16");
7608 break;
7609
9743db03
AV		 7610 case MVE_VDUP:
7611 switch (size)
7612 {
7613 case 0:
7614 func (stream, "32");
7615 break;
7616 case 1:
7617 func (stream, "16");
7618 break;
7619 case 2:
7620 func (stream, "8");
7621 break;
7622 default:
7623 break;
7624 }
7625 break;
7626
c507f10b
AV		 7627 case MVE_VMOV_GP_TO_VEC_LANE:
7628 case MVE_VMOV_VEC_LANE_TO_GP:
7629 switch (size)
7630 {
7631 case 0: case 4:
7632 func (stream, "32");
7633 break;
7634
7635 case 1: case 3:
7636 case 5: case 7:
7637 func (stream, "16");
7638 break;
7639
7640 case 8: case 9: case 10: case 11:
7641 case 12: case 13: case 14: case 15:
7642 func (stream, "8");
7643 break;
7644
7645 default:
7646 break;
7647 }
7648 break;
7649
7650 case MVE_VMOV_IMM_TO_VEC:
7651 switch (size)
7652 {
7653 case 0: case 4: case 8:
7654 case 12: case 24: case 26:
7655 func (stream, "i32");
7656 break;
7657 case 16: case 20:
7658 func (stream, "i16");
7659 break;
7660 case 28:
7661 func (stream, "i8");
7662 break;
7663 case 29:
7664 func (stream, "i64");
7665 break;
7666 case 30:
7667 func (stream, "f32");
7668 break;
7669 default:
7670 break;
7671 }
7672 break;
7673
14925797
AV		 7674 case MVE_VMULL_POLY:
7675 if (size == 0)
7676 func (stream, "p8");
7677 else if (size == 1)
7678 func (stream, "p16");
7679 break;
7680
c507f10b
AV		 7681 case MVE_VMVN_IMM:
7682 switch (size)
7683 {
7684 case 0: case 2: case 4:
7685 case 6: case 12: case 13:
7686 func (stream, "32");
7687 break;
7688
7689 case 8: case 10:
7690 func (stream, "16");
7691 break;
7692
7693 default:
7694 break;
7695 }
7696 break;
7697
7698 case MVE_VBIC_IMM:
7699 case MVE_VORR_IMM:
7700 switch (size)
7701 {
7702 case 1: case 3:
7703 case 5: case 7:
7704 func (stream, "32");
7705 break;
7706
7707 case 9: case 11:
7708 func (stream, "16");
7709 break;
7710
7711 default:
7712 break;
7713 }
7714 break;
7715
ed63aa17
AV		 7716 case MVE_VQSHRN:
7717 case MVE_VQSHRUN:
7718 case MVE_VQRSHRN:
7719 case MVE_VQRSHRUN:
7720 case MVE_VRSHRN:
7721 case MVE_VSHRN:
7722 {
7723 switch (size)
7724 {
7725 case 1:
7726 func (stream, "16");
7727 break;
7728
7729 case 2: case 3:
7730 func (stream, "32");
7731 break;
7732
7733 default:
7734 break;
7735 }
7736 }
7737 break;
7738
7739 case MVE_VQSHL_T2:
7740 case MVE_VQSHLU_T3:
7741 case MVE_VRSHR:
7742 case MVE_VSHL_T1:
7743 case MVE_VSHLL_T1:
7744 case MVE_VSHR:
7745 case MVE_VSLI:
7746 case MVE_VSRI:
7747 {
7748 switch (size)
7749 {
7750 case 1:
7751 func (stream, "8");
7752 break;
7753
7754 case 2: case 3:
7755 func (stream, "16");
7756 break;
7757
7758 case 4: case 5: case 6: case 7:
7759 func (stream, "32");
7760 break;
7761
7762 default:
7763 break;
7764 }
7765 }
7766 break;
7767
143275ea
AV		 7768 default:
7769 break;
7770 }
7771}
7772
ed63aa17
AV		 7773static void
7774print_mve_shift_n (struct disassemble_info *info, long given,
7775 enum mve_instructions matched_insn)
7776{
7777 void *stream = info->stream;
7778 fprintf_ftype func = info->fprintf_func;
7779
7780 int startAt0
7781 = matched_insn == MVE_VQSHL_T2
7782 || matched_insn == MVE_VQSHLU_T3
7783 || matched_insn == MVE_VSHL_T1
7784 || matched_insn == MVE_VSHLL_T1
7785 || matched_insn == MVE_VSLI;
7786
7787 unsigned imm6 = (given & 0x3f0000) >> 16;
7788
7789 if (matched_insn == MVE_VSHLL_T1)
7790 imm6 &= 0x1f;
7791
7792 unsigned shiftAmount = 0;
7793 if ((imm6 & 0x20) != 0)
7794 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7795 else if ((imm6 & 0x10) != 0)
7796 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7797 else if ((imm6 & 0x08) != 0)
7798 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7799 else
7800 print_mve_undefined (info, UNDEF_SIZE_0);
7801
7802 func (stream, "%u", shiftAmount);
7803}
7804
143275ea
AV		 7805static void
7806print_vec_condition (struct disassemble_info *info, long given,
7807 enum mve_instructions matched_insn)
7808{
7809 void *stream = info->stream;
7810 fprintf_ftype func = info->fprintf_func;
7811 long vec_cond = 0;
7812
7813 switch (matched_insn)
7814 {
7815 case MVE_VPT_FP_T1:
7816 case MVE_VCMP_FP_T1:
7817 vec_cond = (((given & 0x1000) >> 10)
7818 | ((given & 1) << 1)
7819 | ((given & 0x0080) >> 7));
7820 func (stream, "%s",vec_condnames[vec_cond]);
7821 break;
7822
7823 case MVE_VPT_FP_T2:
7824 case MVE_VCMP_FP_T2:
7825 vec_cond = (((given & 0x1000) >> 10)
7826 | ((given & 0x0020) >> 4)
7827 | ((given & 0x0080) >> 7));
7828 func (stream, "%s",vec_condnames[vec_cond]);
7829 break;
7830
7831 case MVE_VPT_VEC_T1:
7832 case MVE_VCMP_VEC_T1:
7833 vec_cond = (given & 0x0080) >> 7;
7834 func (stream, "%s",vec_condnames[vec_cond]);
7835 break;
7836
7837 case MVE_VPT_VEC_T2:
7838 case MVE_VCMP_VEC_T2:
7839 vec_cond = 2 | ((given & 0x0080) >> 7);
7840 func (stream, "%s",vec_condnames[vec_cond]);
7841 break;
7842
7843 case MVE_VPT_VEC_T3:
7844 case MVE_VCMP_VEC_T3:
7845 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7846 func (stream, "%s",vec_condnames[vec_cond]);
7847 break;
7848
7849 case MVE_VPT_VEC_T4:
7850 case MVE_VCMP_VEC_T4:
7851 vec_cond = (given & 0x0080) >> 7;
7852 func (stream, "%s",vec_condnames[vec_cond]);
7853 break;
7854
7855 case MVE_VPT_VEC_T5:
7856 case MVE_VCMP_VEC_T5:
7857 vec_cond = 2 | ((given & 0x0080) >> 7);
7858 func (stream, "%s",vec_condnames[vec_cond]);
7859 break;
7860
7861 case MVE_VPT_VEC_T6:
7862 case MVE_VCMP_VEC_T6:
7863 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7864 func (stream, "%s",vec_condnames[vec_cond]);
7865 break;
7866
7867 case MVE_NONE:
7868 case MVE_VPST:
7869 default:
7870 break;
7871 }
7872}
7873
7874#define W_BIT 21
7875#define I_BIT 22
7876#define U_BIT 23
7877#define P_BIT 24
7878
7879#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7880#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7881#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7882#define PRE_BIT_SET (given & (1 << P_BIT))
7883
7884
8f06b2d8
PB		 7885/* Print one coprocessor instruction on INFO->STREAM.
7886 Return TRUE if the instuction matched, FALSE if this is not a
7887 recognised coprocessor instruction. */
7888
7889static bfd_boolean
fe56b6ce
NC		 7890print_insn_coprocessor (bfd_vma pc,
7891 struct disassemble_info *info,
7892 long given,
8f06b2d8
PB		 7893 bfd_boolean thumb)
7894{
6b0dd094 7895 const struct sopcode32 *insn;
8f06b2d8
PB		 7896 void *stream = info->stream;
7897 fprintf_ftype func = info->fprintf_func;
7898 unsigned long mask;
2edcd244 7899 unsigned long value = 0;
c22aaad1 7900 int cond;
8afc7bea 7901 int cp_num;
823d2571
TG		 7902 struct arm_private_data *private_data = info->private_data;
7903 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 7904 arm_feature_set arm_ext_v8_1m_main =
7905 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 7906
5b616bef 7907 allowed_arches = private_data->features;
8f06b2d8
PB		 7908
7909 for (insn = coprocessor_opcodes; insn->assembler; insn++)
7910 {
ff4a8d2b
NC		 7911 unsigned long u_reg = 16;
7912 bfd_boolean is_unpredictable = FALSE;
05413229 7913 signed long value_in_comment = 0;
0313a2b8
NC		 7914 const char *c;
7915
823d2571 7916 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 7917 switch (insn->value)
7918 {
7919 case SENTINEL_IWMMXT_START:
7920 if (info->mach != bfd_mach_arm_XScale
7921 && info->mach != bfd_mach_arm_iWMMXt
7922 && info->mach != bfd_mach_arm_iWMMXt2)
7923 do
7924 insn++;
823d2571
TG		 7925 while ((! ARM_FEATURE_ZERO (insn->arch))
7926 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 7927 continue;
7928
7929 case SENTINEL_IWMMXT_END:
7930 continue;
7931
7932 case SENTINEL_GENERIC_START:
5b616bef 7933 allowed_arches = private_data->features;
05413229
NC		 7934 continue;
7935
7936 default:
7937 abort ();
7938 }
8f06b2d8
PB		 7939
7940 mask = insn->mask;
7941 value = insn->value;
8afc7bea
RL		 7942 cp_num = (given >> 8) & 0xf;
7943
8f06b2d8
PB		 7944 if (thumb)
7945 {
7946 /* The high 4 bits are 0xe for Arm conditional instructions, and
7947 0xe for arm unconditional instructions. The rest of the
7948 encoding is the same. */
7949 mask |= 0xf0000000;
7950 value |= 0xe0000000;
c22aaad1
PB		 7951 if (ifthen_state)
7952 cond = IFTHEN_COND;
7953 else
e2efe87d 7954 cond = COND_UNCOND;
8f06b2d8
PB		 7955 }
7956 else
7957 {
7958 /* Only match unconditional instuctions against unconditional
7959 patterns. */
7960 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 7961 {
7962 mask |= 0xf0000000;
e2efe87d 7963 cond = COND_UNCOND;
c22aaad1
PB		 7964 }
7965 else
7966 {
7967 cond = (given >> 28) & 0xf;
7968 if (cond == 0xe)
e2efe87d 7969 cond = COND_UNCOND;
c22aaad1 7970 }
8f06b2d8 7971 }
823d2571 7972
6b0dd094
AV		 7973 if ((insn->isa == T32 && !thumb)
7974 || (insn->isa == ARM && thumb))
7975 continue;
7976
0313a2b8
NC		 7977 if ((given & mask) != value)
7978 continue;
8f06b2d8 7979
823d2571 7980 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 7981 continue;
7982
8afc7bea
RL		 7983 if (insn->value == 0xfe000010 /* mcr2 */
7984 || insn->value == 0xfe100010 /* mrc2 */
7985 || insn->value == 0xfc100000 /* ldc2 */
7986 || insn->value == 0xfc000000) /* stc2 */
7987 {
b0c11777 7988 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 7989 is_unpredictable = TRUE;
f08d8ce3
AV		 7990
7991 /* Armv8.1-M Mainline FP & MVE instructions. */
7992 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
7993 && !ARM_CPU_IS_ANY (allowed_arches)
7994 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
7995 continue;
7996
8afc7bea
RL		 7997 }
7998 else if (insn->value == 0x0e000000 /* cdp */
7999 || insn->value == 0xfe000000 /* cdp2 */
8000 || insn->value == 0x0e000010 /* mcr */
8001 || insn->value == 0x0e100010 /* mrc */
8002 || insn->value == 0x0c100000 /* ldc */
8003 || insn->value == 0x0c000000) /* stc */
8004 {
8005 /* Floating-point instructions. */
b0c11777 8006 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8007 continue;
32c36c3c
AV		 8008
8009 /* Armv8.1-M Mainline FP & MVE instructions. */
8010 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8011 && !ARM_CPU_IS_ANY (allowed_arches)
8012 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8013 continue;
8afc7bea 8014 }
aef6d006
AV		 8015 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8016 || insn->value == 0xec000f80) /* vstr (system register) */
8017 && arm_decode_field (given, 24, 24) == 0
8018 && arm_decode_field (given, 21, 21) == 0)
8019 /* If the P and W bits are both 0 then these encodings match the MVE
8020 VLDR and VSTR instructions, these are in a different table, so we
8021 don't let it match here. */
8022 continue;
8023
0313a2b8
NC		 8024 for (c = insn->assembler; *c; c++)
8025 {
8026 if (*c == '%')
8f06b2d8 8027 {
32c36c3c
AV		 8028 const char mod = *++c;
8029 switch (mod)
8f06b2d8 8030 {
0313a2b8
NC		 8031 case '%':
8032 func (stream, "%%");
8033 break;
8034
8035 case 'A':
32c36c3c 8036 case 'K':
05413229 8037 {
79862e45 8038 int rn = (given >> 16) & 0xf;
b0c11777 8039 bfd_vma offset = given & 0xff;
0313a2b8 8040
32c36c3c
AV		 8041 if (mod == 'K')
8042 offset = given & 0x7f;
8043
05413229 8044 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8045
79862e45
DJ		 8046 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8047 {
8048 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8049 if (cp_num == 9)
8050 /* vldr.16/vstr.16 will shift the address
8051 left by 1 bit only. */
8052 offset = offset * 2;
8053 else
8054 offset = offset * 4;
8055
79862e45
DJ		 8056 if (NEGATIVE_BIT_SET)
8057 offset = - offset;
8058 if (rn != 15)
8059 value_in_comment = offset;
8060 }
8061
c1e26897 8062 if (PRE_BIT_SET)
05413229
NC		 8063 {
8064 if (offset)
fe56b6ce 8065 func (stream, ", #%d]%s",
d908c8af 8066 (int) offset,
c1e26897 8067 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8068 else if (NEGATIVE_BIT_SET)
8069 func (stream, ", #-0]");
05413229
NC		 8070 else
8071 func (stream, "]");
8072 }
8073 else
8074 {
0313a2b8 8075 func (stream, "]");
8f06b2d8 8076
c1e26897 8077 if (WRITEBACK_BIT_SET)
05413229
NC		 8078 {
8079 if (offset)
d908c8af 8080 func (stream, ", #%d", (int) offset);
26d97720
NS		 8081 else if (NEGATIVE_BIT_SET)
8082 func (stream, ", #-0");
05413229
NC		 8083 }
8084 else
fe56b6ce 8085 {
26d97720
NS		 8086 func (stream, ", {%s%d}",
8087 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8088 (int) offset);
fe56b6ce
NC		 8089 value_in_comment = offset;
8090 }
05413229 8091 }
79862e45
DJ		 8092 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8093 {
8094 func (stream, "\t; ");
6844b2c2
MGD		 8095 /* For unaligned PCs, apply off-by-alignment
8096 correction. */
43e65147 8097 info->print_address_func (offset + pc
6844b2c2
MGD		 8098 + info->bytes_per_chunk * 2
8099 - (pc & 3),
dffaa15c 8100 info);
79862e45 8101 }
05413229 8102 }
0313a2b8 8103 break;
8f06b2d8 8104
0313a2b8
NC		 8105 case 'B':
8106 {
8107 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8108 int offset = (given >> 1) & 0x3f;
8109
8110 if (offset == 1)
8111 func (stream, "{d%d}", regno);
8112 else if (regno + offset > 32)
8113 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8114 else
8115 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8116 }
8117 break;
8f06b2d8 8118
efd6b359
AV		 8119 case 'C':
8120 {
8121 bfd_boolean single = ((given >> 8) & 1) == 0;
8122 char reg_prefix = single ? 's' : 'd';
8123 int Dreg = (given >> 22) & 0x1;
8124 int Vdreg = (given >> 12) & 0xf;
8125 int reg = single ? ((Vdreg << 1) | Dreg)
8126 : ((Dreg << 4) | Vdreg);
8127 int num = (given >> (single ? 0 : 1)) & 0x7f;
8128 int maxreg = single ? 31 : 15;
8129 int topreg = reg + num - 1;
8130
8131 if (!num)
8132 func (stream, "{VPR}");
8133 else if (num == 1)
8134 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8135 else if (topreg > maxreg)
8136 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8137 reg_prefix, reg, single ? topreg >> 1 : topreg);
8138 else
8139 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8140 reg_prefix, topreg);
8141 }
8142 break;
8143
e2efe87d
MGD		 8144 case 'u':
8145 if (cond != COND_UNCOND)
8146 is_unpredictable = TRUE;
8147
8148 /* Fall through. */
0313a2b8 8149 case 'c':
b0c11777
RL		 8150 if (cond != COND_UNCOND && cp_num == 9)
8151 is_unpredictable = TRUE;
8152
0313a2b8
NC		 8153 func (stream, "%s", arm_conditional[cond]);
8154 break;
8f06b2d8 8155
0313a2b8
NC		 8156 case 'I':
8157 /* Print a Cirrus/DSP shift immediate. */
8158 /* Immediates are 7bit signed ints with bits 0..3 in
8159 bits 0..3 of opcode and bits 4..6 in bits 5..7
8160 of opcode. */
8161 {
8162 int imm;
8f06b2d8 8163
0313a2b8 8164 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8165
0313a2b8
NC		 8166 /* Is ``imm'' a negative number? */
8167 if (imm & 0x40)
24b4cf66 8168 imm -= 0x80;
8f06b2d8 8169
0313a2b8
NC		 8170 func (stream, "%d", imm);
8171 }
8172
8173 break;
8f06b2d8 8174
32c36c3c
AV		 8175 case 'J':
8176 {
73cd51e5
AV		 8177 unsigned long regno
8178 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8179
8180 switch (regno)
8181 {
8182 case 0x1:
8183 func (stream, "FPSCR");
8184 break;
8185 case 0x2:
8186 func (stream, "FPSCR_nzcvqc");
8187 break;
8188 case 0xc:
8189 func (stream, "VPR");
8190 break;
8191 case 0xd:
8192 func (stream, "P0");
8193 break;
8194 case 0xe:
8195 func (stream, "FPCXTNS");
8196 break;
8197 case 0xf:
8198 func (stream, "FPCXTS");
8199 break;
8200 default:
73cd51e5 8201 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8202 break;
8203 }
8204 }
8205 break;
8206
0313a2b8
NC		 8207 case 'F':
8208 switch (given & 0x00408000)
8209 {
8210 case 0:
8211 func (stream, "4");
8212 break;
8213 case 0x8000:
8214 func (stream, "1");
8215 break;
8216 case 0x00400000:
8217 func (stream, "2");
8f06b2d8 8218 break;
0313a2b8
NC		 8219 default:
8220 func (stream, "3");
8221 }
8222 break;
8f06b2d8 8223
0313a2b8
NC		 8224 case 'P':
8225 switch (given & 0x00080080)
8226 {
8227 case 0:
8228 func (stream, "s");
8229 break;
8230 case 0x80:
8231 func (stream, "d");
8232 break;
8233 case 0x00080000:
8234 func (stream, "e");
8235 break;
8236 default:
8237 func (stream, _("<illegal precision>"));
8f06b2d8 8238 break;
0313a2b8
NC		 8239 }
8240 break;
8f06b2d8 8241
0313a2b8
NC		 8242 case 'Q':
8243 switch (given & 0x00408000)
8244 {
8245 case 0:
8246 func (stream, "s");
8f06b2d8 8247 break;
0313a2b8
NC		 8248 case 0x8000:
8249 func (stream, "d");
8f06b2d8 8250 break;
0313a2b8
NC		 8251 case 0x00400000:
8252 func (stream, "e");
8253 break;
8254 default:
8255 func (stream, "p");
8f06b2d8 8256 break;
0313a2b8
NC		 8257 }
8258 break;
8f06b2d8 8259
0313a2b8
NC		 8260 case 'R':
8261 switch (given & 0x60)
8262 {
8263 case 0:
8264 break;
8265 case 0x20:
8266 func (stream, "p");
8267 break;
8268 case 0x40:
8269 func (stream, "m");
8270 break;
8271 default:
8272 func (stream, "z");
8273 break;
8274 }
8275 break;
16980d0b 8276
0313a2b8
NC		 8277 case '0': case '1': case '2': case '3': case '4':
8278 case '5': case '6': case '7': case '8': case '9':
8279 {
8280 int width;
8f06b2d8 8281
0313a2b8 8282 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8283
0313a2b8
NC		 8284 switch (*c)
8285 {
ff4a8d2b
NC		 8286 case 'R':
8287 if (value == 15)
8288 is_unpredictable = TRUE;
8289 /* Fall through. */
0313a2b8 8290 case 'r':
ff4a8d2b
NC		 8291 if (c[1] == 'u')
8292 {
8293 /* Eat the 'u' character. */
8294 ++ c;
8295
8296 if (u_reg == value)
8297 is_unpredictable = TRUE;
8298 u_reg = value;
8299 }
0313a2b8
NC		 8300 func (stream, "%s", arm_regnames[value]);
8301 break;
c28eeff2
SN		 8302 case 'V':
8303 if (given & (1 << 6))
8304 goto Q;
8305 /* FALLTHROUGH */
0313a2b8
NC		 8306 case 'D':
8307 func (stream, "d%ld", value);
8308 break;
8309 case 'Q':
c28eeff2 8310 Q:
0313a2b8
NC		 8311 if (value & 1)
8312 func (stream, "<illegal reg q%ld.5>", value >> 1);
8313 else
8314 func (stream, "q%ld", value >> 1);
8315 break;
8316 case 'd':
8317 func (stream, "%ld", value);
05413229 8318 value_in_comment = value;
0313a2b8 8319 break;
6f1c2142
AM		 8320 case 'E':
8321 {
8322 /* Converts immediate 8 bit back to float value. */
8323 unsigned floatVal = (value & 0x80) << 24
8324 | (value & 0x3F) << 19
8325 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8326
8327 /* Quarter float have a maximum value of 31.0.
8328 Get floating point value multiplied by 1e7.
8329 The maximum value stays in limit of a 32-bit int. */
8330 unsigned decVal =
8331 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8332 (16 + (value & 0xF));
8333
8334 if (!(decVal % 1000000))
8335 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8336 floatVal, value & 0x80 ? '-' : ' ',
8337 decVal / 10000000,
8338 decVal % 10000000 / 1000000);
8339 else if (!(decVal % 10000))
8340 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8341 floatVal, value & 0x80 ? '-' : ' ',
8342 decVal / 10000000,
8343 decVal % 10000000 / 10000);
8344 else
8345 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8346 floatVal, value & 0x80 ? '-' : ' ',
8347 decVal / 10000000, decVal % 10000000);
8348 break;
8349 }
0313a2b8
NC		 8350 case 'k':
8351 {
8352 int from = (given & (1 << 7)) ? 32 : 16;
8353 func (stream, "%ld", from - value);
8354 }
8355 break;
8f06b2d8 8356
0313a2b8
NC		 8357 case 'f':
8358 if (value > 7)
8359 func (stream, "#%s", arm_fp_const[value & 7]);
8360 else
8361 func (stream, "f%ld", value);
8362 break;
4146fd53 8363
0313a2b8
NC		 8364 case 'w':
8365 if (width == 2)
8366 func (stream, "%s", iwmmxt_wwnames[value]);
8367 else
8368 func (stream, "%s", iwmmxt_wwssnames[value]);
8369 break;
4146fd53 8370
0313a2b8
NC		 8371 case 'g':
8372 func (stream, "%s", iwmmxt_regnames[value]);
8373 break;
8374 case 'G':
8375 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8376 break;
8f06b2d8 8377
0313a2b8 8378 case 'x':
d1aaab3c 8379 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8380 break;
8f06b2d8 8381
33399f07
MGD		 8382 case 'c':
8383 switch (value)
8384 {
8385 case 0:
8386 func (stream, "eq");
8387 break;
8388
8389 case 1:
8390 func (stream, "vs");
8391 break;
8392
8393 case 2:
8394 func (stream, "ge");
8395 break;
8396
8397 case 3:
8398 func (stream, "gt");
8399 break;
8400
8401 default:
8402 func (stream, "??");
8403 break;
8404 }
8405 break;
8406
0313a2b8
NC		 8407 case '`':
8408 c++;
8409 if (value == 0)
8410 func (stream, "%c", *c);
8411 break;
8412 case '\'':
8413 c++;
8414 if (value == ((1ul << width) - 1))
8415 func (stream, "%c", *c);
8416 break;
8417 case '?':
fe56b6ce 8418 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8419 c += 1 << width;
8420 break;
8421 default:
8422 abort ();
8423 }
dffaa15c
AM		 8424 }
8425 break;
0313a2b8 8426
dffaa15c
AM		 8427 case 'y':
8428 case 'z':
8429 {
8430 int single = *c++ == 'y';
8431 int regno;
8f06b2d8 8432
dffaa15c
AM		 8433 switch (*c)
8434 {
8435 case '4': /* Sm pair */
8436 case '0': /* Sm, Dm */
8437 regno = given & 0x0000000f;
8438 if (single)
8439 {
8440 regno <<= 1;
8441 regno += (given >> 5) & 1;
8442 }
8443 else
8444 regno += ((given >> 5) & 1) << 4;
8445 break;
8f06b2d8 8446
dffaa15c
AM		 8447 case '1': /* Sd, Dd */
8448 regno = (given >> 12) & 0x0000000f;
8449 if (single)
8450 {
8451 regno <<= 1;
8452 regno += (given >> 22) & 1;
8453 }
8454 else
8455 regno += ((given >> 22) & 1) << 4;
8456 break;
7df76b80 8457
dffaa15c
AM		 8458 case '2': /* Sn, Dn */
8459 regno = (given >> 16) & 0x0000000f;
8460 if (single)
8461 {
8462 regno <<= 1;
8463 regno += (given >> 7) & 1;
8464 }
8465 else
8466 regno += ((given >> 7) & 1) << 4;
8467 break;
a7f8487e 8468
dffaa15c
AM		 8469 case '3': /* List */
8470 func (stream, "{");
8471 regno = (given >> 12) & 0x0000000f;
8472 if (single)
8473 {
8474 regno <<= 1;
8475 regno += (given >> 22) & 1;
8476 }
8477 else
8478 regno += ((given >> 22) & 1) << 4;
8479 break;
a7f8487e 8480
dffaa15c
AM		 8481 default:
8482 abort ();
8483 }
0313a2b8 8484
dffaa15c 8485 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8486
dffaa15c
AM		 8487 if (*c == '3')
8488 {
8489 int count = given & 0xff;
b34976b6 8490
dffaa15c
AM		 8491 if (single == 0)
8492 count >>= 1;
0313a2b8 8493
dffaa15c
AM		 8494 if (--count)
8495 {
8496 func (stream, "-%c%d",
8497 single ? 's' : 'd',
8498 regno + count);
8499 }
0313a2b8 8500
dffaa15c 8501 func (stream, "}");
0313a2b8 8502 }
dffaa15c
AM		 8503 else if (*c == '4')
8504 func (stream, ", %c%d", single ? 's' : 'd',
8505 regno + 1);
8506 }
8507 break;
b34976b6 8508
dffaa15c
AM		 8509 case 'L':
8510 switch (given & 0x00400100)
0313a2b8 8511 {
dffaa15c
AM		 8512 case 0x00000000: func (stream, "b"); break;
8513 case 0x00400000: func (stream, "h"); break;
8514 case 0x00000100: func (stream, "w"); break;
8515 case 0x00400100: func (stream, "d"); break;
8516 default:
8517 break;
0313a2b8 8518 }
dffaa15c 8519 break;
2d447fca 8520
dffaa15c
AM		 8521 case 'Z':
8522 {
8523 /* given (20, 23) | given (0, 3) */
8524 value = ((given >> 16) & 0xf0) | (given & 0xf);
8525 func (stream, "%d", (int) value);
8526 }
8527 break;
0313a2b8 8528
dffaa15c
AM		 8529 case 'l':
8530 /* This is like the 'A' operator, except that if
8531 the width field "M" is zero, then the offset is
8532 *not* multiplied by four. */
8533 {
8534 int offset = given & 0xff;
8535 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8536
dffaa15c 8537 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8538
dffaa15c
AM		 8539 if (multiplier > 1)
8540 {
8541 value_in_comment = offset * multiplier;
8542 if (NEGATIVE_BIT_SET)
8543 value_in_comment = - value_in_comment;
8544 }
0313a2b8 8545
dffaa15c
AM		 8546 if (offset)
8547 {
8548 if (PRE_BIT_SET)
8549 func (stream, ", #%s%d]%s",
8550 NEGATIVE_BIT_SET ? "-" : "",
8551 offset * multiplier,
8552 WRITEBACK_BIT_SET ? "!" : "");
8553 else
8554 func (stream, "], #%s%d",
8555 NEGATIVE_BIT_SET ? "-" : "",
8556 offset * multiplier);
8557 }
8558 else
8559 func (stream, "]");
8560 }
8561 break;
2d447fca 8562
dffaa15c
AM		 8563 case 'r':
8564 {
8565 int imm4 = (given >> 4) & 0xf;
8566 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8567 int ubit = ! NEGATIVE_BIT_SET;
8568 const char *rm = arm_regnames [given & 0xf];
8569 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8570
dffaa15c
AM		 8571 switch (puw_bits)
8572 {
8573 case 1:
8574 case 3:
8575 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8576 if (imm4)
8577 func (stream, ", lsl #%d", imm4);
8578 break;
0313a2b8 8579
dffaa15c
AM		 8580 case 4:
8581 case 5:
8582 case 6:
8583 case 7:
8584 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8585 if (imm4 > 0)
8586 func (stream, ", lsl #%d", imm4);
8587 func (stream, "]");
8588 if (puw_bits == 5 || puw_bits == 7)
8589 func (stream, "!");
8590 break;
2d447fca 8591
dffaa15c
AM		 8592 default:
8593 func (stream, "INVALID");
8594 }
8595 }
8596 break;
0313a2b8 8597
dffaa15c
AM		 8598 case 'i':
8599 {
8600 long imm5;
8601 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8602 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8603 }
dffaa15c
AM		 8604 break;
8605
8606 default:
8607 abort ();
252b5132 8608 }
252b5132 8609 }
0313a2b8
NC		 8610 else
8611 func (stream, "%c", *c);
252b5132 8612 }
05413229
NC		 8613
8614 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8615 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8616
ff4a8d2b
NC		 8617 if (is_unpredictable)
8618 func (stream, UNPREDICTABLE_INSTRUCTION);
8619
0313a2b8 8620 return TRUE;
252b5132 8621 }
8f06b2d8 8622 return FALSE;
252b5132
RH		 8623}
8624
05413229
NC		 8625/* Decodes and prints ARM addressing modes. Returns the offset
8626 used in the address, if any, if it is worthwhile printing the
8627 offset as a hexadecimal value in a comment at the end of the
8628 line of disassembly. */
8629
8630static signed long
62b3e311
PB		 8631print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8632{
8633 void *stream = info->stream;
8634 fprintf_ftype func = info->fprintf_func;
f8b960bc 8635 bfd_vma offset = 0;
62b3e311
PB		 8636
8637 if (((given & 0x000f0000) == 0x000f0000)
8638 && ((given & 0x02000000) == 0))
8639 {
05413229 8640 offset = given & 0xfff;
62b3e311
PB		 8641
8642 func (stream, "[pc");
8643
c1e26897 8644 if (PRE_BIT_SET)
62b3e311 8645 {
26d97720
NS		 8646 /* Pre-indexed. Elide offset of positive zero when
8647 non-writeback. */
8648 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8649 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8650
8651 if (NEGATIVE_BIT_SET)
8652 offset = -offset;
62b3e311
PB		 8653
8654 offset += pc + 8;
8655
8656 /* Cope with the possibility of write-back
8657 being used. Probably a very dangerous thing
8658 for the programmer to do, but who are we to
8659 argue ? */
26d97720 8660 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8661 }
c1e26897 8662 else /* Post indexed. */
62b3e311 8663 {
d908c8af 8664 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8665
c1e26897 8666 /* Ie ignore the offset. */
62b3e311
PB		 8667 offset = pc + 8;
8668 }
8669
8670 func (stream, "\t; ");
8671 info->print_address_func (offset, info);
05413229 8672 offset = 0;
62b3e311
PB		 8673 }
8674 else
8675 {
8676 func (stream, "[%s",
8677 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8678
8679 if (PRE_BIT_SET)
62b3e311
PB		 8680 {
8681 if ((given & 0x02000000) == 0)
8682 {
26d97720 8683 /* Elide offset of positive zero when non-writeback. */
05413229 8684 offset = given & 0xfff;
26d97720 8685 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8686 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8687 }
8688 else
8689 {
26d97720 8690 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8691 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8692 }
8693
8694 func (stream, "]%s",
c1e26897 8695 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8696 }
8697 else
8698 {
8699 if ((given & 0x02000000) == 0)
8700 {
26d97720 8701 /* Always show offset. */
05413229 8702 offset = given & 0xfff;
26d97720 8703 func (stream, "], #%s%d",
d908c8af 8704 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8705 }
8706 else
8707 {
8708 func (stream, "], %s",
c1e26897 8709 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8710 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8711 }
8712 }
84919466
MR		 8713 if (NEGATIVE_BIT_SET)
8714 offset = -offset;
62b3e311 8715 }
05413229
NC		 8716
8717 return (signed long) offset;
62b3e311
PB		 8718}
8719
16980d0b
JB		 8720/* Print one neon instruction on INFO->STREAM.
8721 Return TRUE if the instuction matched, FALSE if this is not a
8722 recognised neon instruction. */
8723
8724static bfd_boolean
8725print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
8726{
8727 const struct opcode32 *insn;
8728 void *stream = info->stream;
8729 fprintf_ftype func = info->fprintf_func;
8730
8731 if (thumb)
8732 {
8733 if ((given & 0xef000000) == 0xef000000)
8734 {
0313a2b8 8735 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 8736 unsigned long bit28 = given & (1 << 28);
8737
8738 given &= 0x00ffffff;
8739 if (bit28)
8740 given |= 0xf3000000;
8741 else
8742 given |= 0xf2000000;
8743 }
8744 else if ((given & 0xff000000) == 0xf9000000)
8745 given ^= 0xf9000000 ^ 0xf4000000;
9743db03
AV		 8746 /* vdup is also a valid neon instruction. */
8747 else if ((given & 0xff910f5f) != 0xee800b10)
16980d0b
JB		 8748 return FALSE;
8749 }
43e65147 8750
16980d0b
JB		 8751 for (insn = neon_opcodes; insn->assembler; insn++)
8752 {
8753 if ((given & insn->mask) == insn->value)
8754 {
05413229 8755 signed long value_in_comment = 0;
e2efe87d 8756 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 8757 const char *c;
8758
8759 for (c = insn->assembler; *c; c++)
8760 {
8761 if (*c == '%')
8762 {
8763 switch (*++c)
8764 {
8765 case '%':
8766 func (stream, "%%");
8767 break;
8768
e2efe87d
MGD		 8769 case 'u':
8770 if (thumb && ifthen_state)
8771 is_unpredictable = TRUE;
8772
8773 /* Fall through. */
c22aaad1
PB		 8774 case 'c':
8775 if (thumb && ifthen_state)
8776 func (stream, "%s", arm_conditional[IFTHEN_COND]);
8777 break;
8778
16980d0b
JB		 8779 case 'A':
8780 {
43e65147 8781 static const unsigned char enc[16] =
16980d0b
JB		 8782 {
8783 0x4, 0x14, /* st4 0,1 */
8784 0x4, /* st1 2 */
8785 0x4, /* st2 3 */
8786 0x3, /* st3 4 */
8787 0x13, /* st3 5 */
8788 0x3, /* st1 6 */
8789 0x1, /* st1 7 */
8790 0x2, /* st2 8 */
8791 0x12, /* st2 9 */
8792 0x2, /* st1 10 */
8793 0, 0, 0, 0, 0
8794 };
8795 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8796 int rn = ((given >> 16) & 0xf);
8797 int rm = ((given >> 0) & 0xf);
8798 int align = ((given >> 4) & 0x3);
8799 int type = ((given >> 8) & 0xf);
8800 int n = enc[type] & 0xf;
8801 int stride = (enc[type] >> 4) + 1;
8802 int ix;
43e65147 8803
16980d0b
JB		 8804 func (stream, "{");
8805 if (stride > 1)
8806 for (ix = 0; ix != n; ix++)
8807 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
8808 else if (n == 1)
8809 func (stream, "d%d", rd);
8810 else
8811 func (stream, "d%d-d%d", rd, rd + n - 1);
8812 func (stream, "}, [%s", arm_regnames[rn]);
8813 if (align)
8e560766 8814 func (stream, " :%d", 32 << align);
16980d0b
JB		 8815 func (stream, "]");
8816 if (rm == 0xd)
8817 func (stream, "!");
8818 else if (rm != 0xf)
8819 func (stream, ", %s", arm_regnames[rm]);
8820 }
8821 break;
43e65147 8822
16980d0b
JB		 8823 case 'B':
8824 {
8825 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8826 int rn = ((given >> 16) & 0xf);
8827 int rm = ((given >> 0) & 0xf);
8828 int idx_align = ((given >> 4) & 0xf);
8829 int align = 0;
8830 int size = ((given >> 10) & 0x3);
8831 int idx = idx_align >> (size + 1);
8832 int length = ((given >> 8) & 3) + 1;
8833 int stride = 1;
8834 int i;
8835
8836 if (length > 1 && size > 0)
8837 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 8838
16980d0b
JB		 8839 switch (length)
8840 {
8841 case 1:
8842 {
8843 int amask = (1 << size) - 1;
8844 if ((idx_align & (1 << size)) != 0)
8845 return FALSE;
8846 if (size > 0)
8847 {
8848 if ((idx_align & amask) == amask)
8849 align = 8 << size;
8850 else if ((idx_align & amask) != 0)
8851 return FALSE;
8852 }
8853 }
8854 break;
43e65147 8855
16980d0b
JB		 8856 case 2:
8857 if (size == 2 && (idx_align & 2) != 0)
8858 return FALSE;
8859 align = (idx_align & 1) ? 16 << size : 0;
8860 break;
43e65147 8861
16980d0b
JB		 8862 case 3:
8863 if ((size == 2 && (idx_align & 3) != 0)
8864 || (idx_align & 1) != 0)
8865 return FALSE;
8866 break;
43e65147 8867
16980d0b
JB		 8868 case 4:
8869 if (size == 2)
8870 {
8871 if ((idx_align & 3) == 3)
8872 return FALSE;
8873 align = (idx_align & 3) * 64;
8874 }
8875 else
8876 align = (idx_align & 1) ? 32 << size : 0;
8877 break;
43e65147 8878
16980d0b
JB		 8879 default:
8880 abort ();
8881 }
43e65147 8882
16980d0b
JB		 8883 func (stream, "{");
8884 for (i = 0; i < length; i++)
8885 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
8886 rd + i * stride, idx);
8887 func (stream, "}, [%s", arm_regnames[rn]);
8888 if (align)
8e560766 8889 func (stream, " :%d", align);
16980d0b
JB		 8890 func (stream, "]");
8891 if (rm == 0xd)
8892 func (stream, "!");
8893 else if (rm != 0xf)
8894 func (stream, ", %s", arm_regnames[rm]);
8895 }
8896 break;
43e65147 8897
16980d0b
JB		 8898 case 'C':
8899 {
8900 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
8901 int rn = ((given >> 16) & 0xf);
8902 int rm = ((given >> 0) & 0xf);
8903 int align = ((given >> 4) & 0x1);
8904 int size = ((given >> 6) & 0x3);
8905 int type = ((given >> 8) & 0x3);
8906 int n = type + 1;
8907 int stride = ((given >> 5) & 0x1);
8908 int ix;
43e65147 8909
16980d0b
JB		 8910 if (stride && (n == 1))
8911 n++;
8912 else
8913 stride++;
43e65147 8914
16980d0b
JB		 8915 func (stream, "{");
8916 if (stride > 1)
8917 for (ix = 0; ix != n; ix++)
8918 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
8919 else if (n == 1)
8920 func (stream, "d%d[]", rd);
8921 else
8922 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
8923 func (stream, "}, [%s", arm_regnames[rn]);
8924 if (align)
8925 {
91d6fa6a 8926 align = (8 * (type + 1)) << size;
16980d0b
JB		 8927 if (type == 3)
8928 align = (size > 1) ? align >> 1 : align;
8929 if (type == 2 || (type == 0 && !size))
8e560766 8930 func (stream, " :<bad align %d>", align);
16980d0b 8931 else
8e560766 8932 func (stream, " :%d", align);
16980d0b
JB		 8933 }
8934 func (stream, "]");
8935 if (rm == 0xd)
8936 func (stream, "!");
8937 else if (rm != 0xf)
8938 func (stream, ", %s", arm_regnames[rm]);
8939 }
8940 break;
43e65147 8941
16980d0b
JB		 8942 case 'D':
8943 {
8944 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
8945 int size = (given >> 20) & 3;
8946 int reg = raw_reg & ((4 << size) - 1);
8947 int ix = raw_reg >> size >> 2;
43e65147 8948
16980d0b
JB		 8949 func (stream, "d%d[%d]", reg, ix);
8950 }
8951 break;
43e65147 8952
16980d0b 8953 case 'E':
fe56b6ce 8954 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 8955 {
8956 int bits = 0;
8957 int cmode = (given >> 8) & 0xf;
8958 int op = (given >> 5) & 0x1;
8959 unsigned long value = 0, hival = 0;
8960 unsigned shift;
8961 int size = 0;
0dbde4cf 8962 int isfloat = 0;
43e65147 8963
16980d0b
JB		 8964 bits |= ((given >> 24) & 1) << 7;
8965 bits |= ((given >> 16) & 7) << 4;
8966 bits |= ((given >> 0) & 15) << 0;
43e65147 8967
16980d0b
JB		 8968 if (cmode < 8)
8969 {
8970 shift = (cmode >> 1) & 3;
fe56b6ce 8971 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8972 size = 32;
8973 }
8974 else if (cmode < 12)
8975 {
8976 shift = (cmode >> 1) & 1;
fe56b6ce 8977 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8978 size = 16;
8979 }
8980 else if (cmode < 14)
8981 {
8982 shift = (cmode & 1) + 1;
fe56b6ce 8983 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 8984 value |= (1ul << (8 * shift)) - 1;
8985 size = 32;
8986 }
8987 else if (cmode == 14)
8988 {
8989 if (op)
8990 {
fe56b6ce 8991 /* Bit replication into bytes. */
16980d0b
JB		 8992 int ix;
8993 unsigned long mask;
43e65147 8994
16980d0b
JB		 8995 value = 0;
8996 hival = 0;
8997 for (ix = 7; ix >= 0; ix--)
8998 {
8999 mask = ((bits >> ix) & 1) ? 0xff : 0;
9000 if (ix <= 3)
9001 value = (value << 8) | mask;
9002 else
9003 hival = (hival << 8) | mask;
9004 }
9005 size = 64;
9006 }
9007 else
9008 {
fe56b6ce
NC		 9009 /* Byte replication. */
9010 value = (unsigned long) bits;
16980d0b
JB		 9011 size = 8;
9012 }
9013 }
9014 else if (!op)
9015 {
fe56b6ce 9016 /* Floating point encoding. */
16980d0b 9017 int tmp;
43e65147 9018
fe56b6ce
NC		 9019 value = (unsigned long) (bits & 0x7f) << 19;
9020 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9021 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9022 value |= (unsigned long) tmp << 24;
16980d0b 9023 size = 32;
0dbde4cf 9024 isfloat = 1;
16980d0b
JB		 9025 }
9026 else
9027 {
9028 func (stream, "<illegal constant %.8x:%x:%x>",
9029 bits, cmode, op);
9030 size = 32;
9031 break;
9032 }
9033 switch (size)
9034 {
9035 case 8:
9036 func (stream, "#%ld\t; 0x%.2lx", value, value);
9037 break;
43e65147 9038
16980d0b
JB		 9039 case 16:
9040 func (stream, "#%ld\t; 0x%.4lx", value, value);
9041 break;
9042
9043 case 32:
0dbde4cf
JB		 9044 if (isfloat)
9045 {
9046 unsigned char valbytes[4];
9047 double fvalue;
43e65147 9048
0dbde4cf
JB		 9049 /* Do this a byte at a time so we don't have to
9050 worry about the host's endianness. */
9051 valbytes[0] = value & 0xff;
9052 valbytes[1] = (value >> 8) & 0xff;
9053 valbytes[2] = (value >> 16) & 0xff;
9054 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9055
9056 floatformat_to_double
c1e26897
NC		 9057 (& floatformat_ieee_single_little, valbytes,
9058 & fvalue);
43e65147 9059
0dbde4cf
JB		 9060 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9061 value);
9062 }
9063 else
4e9d3b81 9064 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9065 (long) (((value & 0x80000000L) != 0)
9d82ec38 9066 ? value | ~0xffffffffL : value),
c1e26897 9067 value);
16980d0b
JB		 9068 break;
9069
9070 case 64:
9071 func (stream, "#0x%.8lx%.8lx", hival, value);
9072 break;
43e65147 9073
16980d0b
JB		 9074 default:
9075 abort ();
9076 }
9077 }
9078 break;
43e65147 9079
16980d0b
JB		 9080 case 'F':
9081 {
9082 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9083 int num = (given >> 8) & 0x3;
43e65147 9084
16980d0b
JB		 9085 if (!num)
9086 func (stream, "{d%d}", regno);
9087 else if (num + regno >= 32)
9088 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9089 else
9090 func (stream, "{d%d-d%d}", regno, regno + num);
9091 }
9092 break;
7e8e6784 9093
16980d0b
JB		 9094
9095 case '0': case '1': case '2': case '3': case '4':
9096 case '5': case '6': case '7': case '8': case '9':
9097 {
9098 int width;
9099 unsigned long value;
9100
9101 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9102
16980d0b
JB		 9103 switch (*c)
9104 {
9105 case 'r':
9106 func (stream, "%s", arm_regnames[value]);
9107 break;
9108 case 'd':
9109 func (stream, "%ld", value);
05413229 9110 value_in_comment = value;
16980d0b
JB		 9111 break;
9112 case 'e':
9113 func (stream, "%ld", (1ul << width) - value);
9114 break;
43e65147 9115
16980d0b
JB		 9116 case 'S':
9117 case 'T':
9118 case 'U':
05413229 9119 /* Various width encodings. */
16980d0b
JB		 9120 {
9121 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9122 int limit;
9123 unsigned low, high;
9124
9125 c++;
9126 if (*c >= '0' && *c <= '9')
9127 limit = *c - '0';
9128 else if (*c >= 'a' && *c <= 'f')
9129 limit = *c - 'a' + 10;
9130 else
9131 abort ();
9132 low = limit >> 2;
9133 high = limit & 3;
9134
9135 if (value < low || value > high)
9136 func (stream, "<illegal width %d>", base << value);
9137 else
9138 func (stream, "%d", base << value);
9139 }
9140 break;
9141 case 'R':
9142 if (given & (1 << 6))
9143 goto Q;
9144 /* FALLTHROUGH */
9145 case 'D':
9146 func (stream, "d%ld", value);
9147 break;
9148 case 'Q':
9149 Q:
9150 if (value & 1)
9151 func (stream, "<illegal reg q%ld.5>", value >> 1);
9152 else
9153 func (stream, "q%ld", value >> 1);
9154 break;
43e65147 9155
16980d0b
JB		 9156 case '`':
9157 c++;
9158 if (value == 0)
9159 func (stream, "%c", *c);
9160 break;
9161 case '\'':
9162 c++;
9163 if (value == ((1ul << width) - 1))
9164 func (stream, "%c", *c);
9165 break;
9166 case '?':
fe56b6ce 9167 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9168 c += 1 << width;
9169 break;
9170 default:
9171 abort ();
9172 }
16980d0b 9173 }
dffaa15c
AM		 9174 break;
9175
9176 default:
9177 abort ();
16980d0b
JB		 9178 }
9179 }
9180 else
9181 func (stream, "%c", *c);
9182 }
05413229
NC		 9183
9184 if (value_in_comment > 32 || value_in_comment < -16)
9185 func (stream, "\t; 0x%lx", value_in_comment);
9186
e2efe87d
MGD		 9187 if (is_unpredictable)
9188 func (stream, UNPREDICTABLE_INSTRUCTION);
9189
16980d0b
JB		 9190 return TRUE;
9191 }
9192 }
9193 return FALSE;
9194}
9195
73cd51e5
AV		 9196/* Print one mve instruction on INFO->STREAM.
9197 Return TRUE if the instuction matched, FALSE if this is not a
9198 recognised mve instruction. */
9199
9200static bfd_boolean
9201print_insn_mve (struct disassemble_info *info, long given)
9202{
9203 const struct mopcode32 *insn;
9204 void *stream = info->stream;
9205 fprintf_ftype func = info->fprintf_func;
9206
9207 for (insn = mve_opcodes; insn->assembler; insn++)
9208 {
9209 if (((given & insn->mask) == insn->value)
9210 && !is_mve_encoding_conflict (given, insn->mve_op))
9211 {
9212 signed long value_in_comment = 0;
9213 bfd_boolean is_unpredictable = FALSE;
9214 bfd_boolean is_undefined = FALSE;
9215 const char *c;
9216 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9217 enum mve_undefined undefined_cond = UNDEF_NONE;
9218
9219 /* Most vector mve instruction are illegal in a it block.
9220 There are a few exceptions; check for them. */
9221 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9222 {
9223 is_unpredictable = TRUE;
9224 unpredictable_cond = UNPRED_IT_BLOCK;
9225 }
9226 else if (is_mve_unpredictable (given, insn->mve_op,
9227 &unpredictable_cond))
9228 is_unpredictable = TRUE;
9229
9230 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9231 is_undefined = TRUE;
9232
c4a23bf8
SP		 9233 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9234 i.e "VMOV Qd, Qm". */
9235 if ((insn->mve_op == MVE_VORR_REG)
9236 && (arm_decode_field (given, 1, 3)
9237 == arm_decode_field (given, 17, 19)))
9238 continue;
9239
73cd51e5
AV		 9240 for (c = insn->assembler; *c; c++)
9241 {
9242 if (*c == '%')
9243 {
9244 switch (*++c)
9245 {
9246 case '%':
9247 func (stream, "%%");
9248 break;
9249
ef1576a1
AV		 9250 case 'a':
9251 /* Don't print anything for '+' as it is implied. */
9252 if (arm_decode_field (given, 23, 23) == 0)
9253 func (stream, "-");
9254 break;
9255
143275ea
AV		 9256 case 'c':
9257 if (ifthen_state)
9258 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9259 break;
9260
aef6d006
AV		 9261 case 'd':
9262 print_mve_vld_str_addr (info, given, insn->mve_op);
9263 break;
9264
143275ea
AV		 9265 case 'i':
9266 {
9267 long mve_mask = mve_extract_pred_mask (given);
9268 func (stream, "%s", mve_predicatenames[mve_mask]);
9269 }
9270 break;
9271
23d00a41
SD		 9272 case 'j':
9273 {
9274 unsigned int imm5 = 0;
9275 imm5 |= arm_decode_field (given, 6, 7);
9276 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9277 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9278 }
9279 break;
9280
08132bdd
SP		 9281 case 'k':
9282 func (stream, "#%u",
9283 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9284 break;
9285
143275ea
AV		 9286 case 'n':
9287 print_vec_condition (info, given, insn->mve_op);
9288 break;
9289
ef1576a1
AV		 9290 case 'o':
9291 if (arm_decode_field (given, 0, 0) == 1)
9292 {
9293 unsigned long size
9294 = arm_decode_field (given, 4, 4)
9295 | (arm_decode_field (given, 6, 6) << 1);
9296
9297 func (stream, ", uxtw #%lu", size);
9298 }
9299 break;
9300
bf0b396d
AV		 9301 case 'm':
9302 print_mve_rounding_mode (info, given, insn->mve_op);
9303 break;
9304
9305 case 's':
9306 print_mve_vcvt_size (info, given, insn->mve_op);
9307 break;
9308
aef6d006
AV		 9309 case 'u':
9310 {
c507f10b
AV		 9311 unsigned long op1 = arm_decode_field (given, 21, 22);
9312
9313 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9314 {
9315 /* Check for signed. */
9316 if (arm_decode_field (given, 23, 23) == 0)
9317 {
9318 /* We don't print 's' for S32. */
9319 if ((arm_decode_field (given, 5, 6) == 0)
9320 && ((op1 == 0) || (op1 == 1)))
9321 ;
9322 else
9323 func (stream, "s");
9324 }
9325 else
9326 func (stream, "u");
9327 }
aef6d006 9328 else
c507f10b
AV		 9329 {
9330 if (arm_decode_field (given, 28, 28) == 0)
9331 func (stream, "s");
9332 else
9333 func (stream, "u");
9334 }
aef6d006 9335 }
ef1576a1 9336 break;
aef6d006 9337
143275ea
AV		 9338 case 'v':
9339 print_instruction_predicate (info);
9340 break;
9341
04d54ace
AV		 9342 case 'w':
9343 if (arm_decode_field (given, 21, 21) == 1)
9344 func (stream, "!");
9345 break;
9346
9347 case 'B':
9348 print_mve_register_blocks (info, given, insn->mve_op);
9349 break;
9350
c507f10b
AV		 9351 case 'E':
9352 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9353
9354 print_simd_imm8 (info, given, 28, insn);
9355 break;
9356
9357 case 'N':
9358 print_mve_vmov_index (info, given);
9359 break;
9360
14925797
AV		 9361 case 'T':
9362 if (arm_decode_field (given, 12, 12) == 0)
9363 func (stream, "b");
9364 else
9365 func (stream, "t");
9366 break;
9367
d3b63143
AV		 9368 case 'X':
9369 if (arm_decode_field (given, 12, 12) == 1)
9370 func (stream, "x");
9371 break;
9372
143275ea
AV		 9373 case '0': case '1': case '2': case '3': case '4':
9374 case '5': case '6': case '7': case '8': case '9':
9375 {
9376 int width;
9377 unsigned long value;
9378
9379 c = arm_decode_bitfield (c, given, &value, &width);
9380
9381 switch (*c)
9382 {
9383 case 'Z':
9384 if (value == 13)
9385 is_unpredictable = TRUE;
9386 else if (value == 15)
9387 func (stream, "zr");
9388 else
9389 func (stream, "%s", arm_regnames[value]);
9390 break;
23d00a41 9391
e39c1607
SD		 9392 case 'c':
9393 func (stream, "%s", arm_conditional[value]);
9394 break;
9395
9396 case 'C':
9397 value ^= 1;
9398 func (stream, "%s", arm_conditional[value]);
9399 break;
9400
23d00a41
SD		 9401 case 'S':
9402 if (value == 13 || value == 15)
9403 is_unpredictable = TRUE;
9404 else
9405 func (stream, "%s", arm_regnames[value]);
9406 break;
9407
143275ea
AV		 9408 case 's':
9409 print_mve_size (info,
9410 value,
9411 insn->mve_op);
9412 break;
66dcaa5d
AV		 9413 case 'I':
9414 if (value == 1)
9415 func (stream, "i");
9416 break;
d3b63143
AV		 9417 case 'A':
9418 if (value == 1)
9419 func (stream, "a");
9420 break;
1c8f2df8
AV		 9421 case 'h':
9422 {
9423 unsigned int odd_reg = (value << 1) | 1;
9424 func (stream, "%s", arm_regnames[odd_reg]);
9425 }
9426 break;
ef1576a1
AV		 9427 case 'i':
9428 {
9429 unsigned long imm
9430 = arm_decode_field (given, 0, 6);
9431 unsigned long mod_imm = imm;
9432
9433 switch (insn->mve_op)
9434 {
9435 case MVE_VLDRW_GATHER_T5:
9436 case MVE_VSTRW_SCATTER_T5:
9437 mod_imm = mod_imm << 2;
9438 break;
9439 case MVE_VSTRD_SCATTER_T6:
9440 case MVE_VLDRD_GATHER_T6:
9441 mod_imm = mod_imm << 3;
9442 break;
9443
9444 default:
9445 break;
9446 }
9447
9448 func (stream, "%lu", mod_imm);
9449 }
9450 break;
bf0b396d
AV		 9451 case 'k':
9452 func (stream, "%lu", 64 - value);
9453 break;
1c8f2df8
AV		 9454 case 'l':
9455 {
9456 unsigned int even_reg = value << 1;
9457 func (stream, "%s", arm_regnames[even_reg]);
9458 }
9459 break;
9460 case 'u':
9461 switch (value)
9462 {
9463 case 0:
9464 func (stream, "1");
9465 break;
9466 case 1:
9467 func (stream, "2");
9468 break;
9469 case 2:
9470 func (stream, "4");
9471 break;
9472 case 3:
9473 func (stream, "8");
9474 break;
9475 default:
9476 break;
9477 }
9478 break;
897b9bbc
AV		 9479 case 'o':
9480 print_mve_rotate (info, value, width);
9481 break;
9743db03
AV		 9482 case 'r':
9483 func (stream, "%s", arm_regnames[value]);
9484 break;
04d54ace 9485 case 'd':
ed63aa17
AV		 9486 if (insn->mve_op == MVE_VQSHL_T2
9487 || insn->mve_op == MVE_VQSHLU_T3
9488 || insn->mve_op == MVE_VRSHR
9489 || insn->mve_op == MVE_VRSHRN
9490 || insn->mve_op == MVE_VSHL_T1
9491 || insn->mve_op == MVE_VSHLL_T1
9492 || insn->mve_op == MVE_VSHR
9493 || insn->mve_op == MVE_VSHRN
9494 || insn->mve_op == MVE_VSLI
9495 || insn->mve_op == MVE_VSRI)
9496 print_mve_shift_n (info, given, insn->mve_op);
9497 else if (insn->mve_op == MVE_VSHLL_T2)
9498 {
9499 switch (value)
9500 {
9501 case 0x00:
9502 func (stream, "8");
9503 break;
9504 case 0x01:
9505 func (stream, "16");
9506 break;
9507 case 0x10:
9508 print_mve_undefined (info, UNDEF_SIZE_0);
9509 break;
9510 default:
9511 assert (0);
9512 break;
9513 }
9514 }
9515 else
9516 {
9517 if (insn->mve_op == MVE_VSHLC && value == 0)
9518 value = 32;
9519 func (stream, "%ld", value);
9520 value_in_comment = value;
9521 }
04d54ace 9522 break;
c507f10b
AV		 9523 case 'F':
9524 func (stream, "s%ld", value);
9525 break;
143275ea
AV		 9526 case 'Q':
9527 if (value & 0x8)
9528 func (stream, "<illegal reg q%ld.5>", value);
9529 else
9530 func (stream, "q%ld", value);
9531 break;
c507f10b
AV		 9532 case 'x':
9533 func (stream, "0x%08lx", value);
9534 break;
143275ea
AV		 9535 default:
9536 abort ();
9537 }
9538 break;
9539 default:
9540 abort ();
9541 }
73cd51e5
AV		 9542 }
9543 }
9544 else
9545 func (stream, "%c", *c);
9546 }
9547
9548 if (value_in_comment > 32 || value_in_comment < -16)
9549 func (stream, "\t; 0x%lx", value_in_comment);
9550
9551 if (is_unpredictable)
9552 print_mve_unpredictable (info, unpredictable_cond);
9553
9554 if (is_undefined)
9555 print_mve_undefined (info, undefined_cond);
9556
143275ea
AV		 9557 if ((vpt_block_state.in_vpt_block == FALSE)
9558 && !ifthen_state
9559 && (is_vpt_instruction (given) == TRUE))
9560 mark_inside_vpt_block (given);
9561 else if (vpt_block_state.in_vpt_block == TRUE)
9562 update_vpt_block_state ();
9563
73cd51e5
AV		 9564 return TRUE;
9565 }
9566 }
9567 return FALSE;
9568}
9569
9570
90ec0d68
MGD		 9571/* Return the name of a v7A special register. */
9572
43e65147 9573static const char *
90ec0d68
MGD		 9574banked_regname (unsigned reg)
9575{
9576 switch (reg)
9577 {
9578 case 15: return "CPSR";
43e65147 9579 case 32: return "R8_usr";
90ec0d68
MGD		 9580 case 33: return "R9_usr";
9581 case 34: return "R10_usr";
9582 case 35: return "R11_usr";
9583 case 36: return "R12_usr";
9584 case 37: return "SP_usr";
9585 case 38: return "LR_usr";
43e65147 9586 case 40: return "R8_fiq";
90ec0d68
MGD		 9587 case 41: return "R9_fiq";
9588 case 42: return "R10_fiq";
9589 case 43: return "R11_fiq";
9590 case 44: return "R12_fiq";
9591 case 45: return "SP_fiq";
9592 case 46: return "LR_fiq";
9593 case 48: return "LR_irq";
9594 case 49: return "SP_irq";
9595 case 50: return "LR_svc";
9596 case 51: return "SP_svc";
9597 case 52: return "LR_abt";
9598 case 53: return "SP_abt";
9599 case 54: return "LR_und";
9600 case 55: return "SP_und";
9601 case 60: return "LR_mon";
9602 case 61: return "SP_mon";
9603 case 62: return "ELR_hyp";
9604 case 63: return "SP_hyp";
9605 case 79: return "SPSR";
9606 case 110: return "SPSR_fiq";
9607 case 112: return "SPSR_irq";
9608 case 114: return "SPSR_svc";
9609 case 116: return "SPSR_abt";
9610 case 118: return "SPSR_und";
9611 case 124: return "SPSR_mon";
9612 case 126: return "SPSR_hyp";
9613 default: return NULL;
9614 }
9615}
9616
e797f7e0
MGD		 9617/* Return the name of the DMB/DSB option. */
9618static const char *
9619data_barrier_option (unsigned option)
9620{
9621 switch (option & 0xf)
9622 {
9623 case 0xf: return "sy";
9624 case 0xe: return "st";
9625 case 0xd: return "ld";
9626 case 0xb: return "ish";
9627 case 0xa: return "ishst";
9628 case 0x9: return "ishld";
9629 case 0x7: return "un";
9630 case 0x6: return "unst";
9631 case 0x5: return "nshld";
9632 case 0x3: return "osh";
9633 case 0x2: return "oshst";
9634 case 0x1: return "oshld";
9635 default: return NULL;
9636 }
9637}
9638
4a5329c6
ZW		 9639/* Print one ARM instruction from PC on INFO->STREAM. */
9640
9641static void
9642print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9643{
6b5d3a4d 9644 const struct opcode32 *insn;
6a51a8a8 9645 void *stream = info->stream;
6b5d3a4d 9646 fprintf_ftype func = info->fprintf_func;
b0e28b39 9647 struct arm_private_data *private_data = info->private_data;
252b5132 9648
16980d0b
JB		 9649 if (print_insn_coprocessor (pc, info, given, FALSE))
9650 return;
9651
9652 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9653 return;
9654
252b5132
RH		 9655 for (insn = arm_opcodes; insn->assembler; insn++)
9656 {
0313a2b8
NC		 9657 if ((given & insn->mask) != insn->value)
9658 continue;
823d2571
TG		 9659
9660 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9661 continue;
9662
9663 /* Special case: an instruction with all bits set in the condition field
9664 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9665 or by the catchall at the end of the table. */
9666 if ((given & 0xF0000000) != 0xF0000000
9667 || (insn->mask & 0xF0000000) == 0xF0000000
9668 || (insn->mask == 0 && insn->value == 0))
252b5132 9669 {
ff4a8d2b
NC		 9670 unsigned long u_reg = 16;
9671 unsigned long U_reg = 16;
ab8e2090 9672 bfd_boolean is_unpredictable = FALSE;
05413229 9673 signed long value_in_comment = 0;
6b5d3a4d 9674 const char *c;
b34976b6 9675
252b5132
RH		 9676 for (c = insn->assembler; *c; c++)
9677 {
9678 if (*c == '%')
9679 {
c1e26897
NC		 9680 bfd_boolean allow_unpredictable = FALSE;
9681
252b5132
RH		 9682 switch (*++c)
9683 {
9684 case '%':
9685 func (stream, "%%");
9686 break;
9687
9688 case 'a':
05413229 9689 value_in_comment = print_arm_address (pc, info, given);
62b3e311 9690 break;
252b5132 9691
62b3e311
PB		 9692 case 'P':
9693 /* Set P address bit and use normal address
9694 printing routine. */
c1e26897 9695 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 9696 break;
9697
c1e26897
NC		 9698 case 'S':
9699 allow_unpredictable = TRUE;
1a0670f3 9700 /* Fall through. */
252b5132
RH		 9701 case 's':
9702 if ((given & 0x004f0000) == 0x004f0000)
9703 {
58efb6c0 9704 /* PC relative with immediate offset. */
f8b960bc 9705 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 9706
aefd8a40
NC		 9707 if (PRE_BIT_SET)
9708 {
26d97720
NS		 9709 /* Elide positive zero offset. */
9710 if (offset || NEGATIVE_BIT_SET)
9711 func (stream, "[pc, #%s%d]\t; ",
d908c8af 9712 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 9713 else
26d97720
NS		 9714 func (stream, "[pc]\t; ");
9715 if (NEGATIVE_BIT_SET)
9716 offset = -offset;
aefd8a40
NC		 9717 info->print_address_func (offset + pc + 8, info);
9718 }
9719 else
9720 {
26d97720
NS		 9721 /* Always show the offset. */
9722 func (stream, "[pc], #%s%d",
d908c8af 9723 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 9724 if (! allow_unpredictable)
9725 is_unpredictable = TRUE;
aefd8a40 9726 }
252b5132
RH		 9727 }
9728 else
9729 {
fe56b6ce
NC		 9730 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
9731
b34976b6 9732 func (stream, "[%s",
252b5132 9733 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 9734
c1e26897 9735 if (PRE_BIT_SET)
252b5132 9736 {
c1e26897 9737 if (IMMEDIATE_BIT_SET)
252b5132 9738 {
26d97720
NS		 9739 /* Elide offset for non-writeback
9740 positive zero. */
9741 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
9742 || offset)
9743 func (stream, ", #%s%d",
9744 NEGATIVE_BIT_SET ? "-" : "", offset);
9745
9746 if (NEGATIVE_BIT_SET)
9747 offset = -offset;
945ee430 9748
fe56b6ce 9749 value_in_comment = offset;
252b5132 9750 }
945ee430 9751 else
ff4a8d2b
NC		 9752 {
9753 /* Register Offset or Register Pre-Indexed. */
9754 func (stream, ", %s%s",
9755 NEGATIVE_BIT_SET ? "-" : "",
9756 arm_regnames[given & 0xf]);
9757
9758 /* Writing back to the register that is the source/
9759 destination of the load/store is unpredictable. */
9760 if (! allow_unpredictable
9761 && WRITEBACK_BIT_SET
9762 && ((given & 0xf) == ((given >> 12) & 0xf)))
9763 is_unpredictable = TRUE;
9764 }
252b5132 9765
b34976b6 9766 func (stream, "]%s",
c1e26897 9767 WRITEBACK_BIT_SET ? "!" : "");
252b5132 9768 }
945ee430 9769 else
252b5132 9770 {
c1e26897 9771 if (IMMEDIATE_BIT_SET)
252b5132 9772 {
945ee430 9773 /* Immediate Post-indexed. */
aefd8a40 9774 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 9775 func (stream, "], #%s%d",
9776 NEGATIVE_BIT_SET ? "-" : "", offset);
9777 if (NEGATIVE_BIT_SET)
9778 offset = -offset;
fe56b6ce 9779 value_in_comment = offset;
252b5132 9780 }
945ee430 9781 else
ff4a8d2b
NC		 9782 {
9783 /* Register Post-indexed. */
9784 func (stream, "], %s%s",
9785 NEGATIVE_BIT_SET ? "-" : "",
9786 arm_regnames[given & 0xf]);
9787
9788 /* Writing back to the register that is the source/
9789 destination of the load/store is unpredictable. */
9790 if (! allow_unpredictable
9791 && (given & 0xf) == ((given >> 12) & 0xf))
9792 is_unpredictable = TRUE;
9793 }
c1e26897 9794
07a28fab
NC		 9795 if (! allow_unpredictable)
9796 {
9797 /* Writeback is automatically implied by post- addressing.
9798 Setting the W bit is unnecessary and ARM specify it as
9799 being unpredictable. */
9800 if (WRITEBACK_BIT_SET
9801 /* Specifying the PC register as the post-indexed
9802 registers is also unpredictable. */
ab8e2090
NC		 9803 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
9804 is_unpredictable = TRUE;
07a28fab 9805 }
252b5132
RH		 9806 }
9807 }
9808 break;
b34976b6 9809
252b5132 9810 case 'b':
6b5d3a4d 9811 {
f8b960bc 9812 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
05413229 9813 info->print_address_func (disp * 4 + pc + 8, info);
6b5d3a4d 9814 }
252b5132
RH		 9815 break;
9816
9817 case 'c':
c22aaad1
PB		 9818 if (((given >> 28) & 0xf) != 0xe)
9819 func (stream, "%s",
9820 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 9821 break;
9822
9823 case 'm':
9824 {
9825 int started = 0;
9826 int reg;
9827
9828 func (stream, "{");
9829 for (reg = 0; reg < 16; reg++)
9830 if ((given & (1 << reg)) != 0)
9831 {
9832 if (started)
9833 func (stream, ", ");
9834 started = 1;
9835 func (stream, "%s", arm_regnames[reg]);
9836 }
9837 func (stream, "}");
ab8e2090
NC		 9838 if (! started)
9839 is_unpredictable = TRUE;
252b5132
RH		 9840 }
9841 break;
9842
37b37b2d 9843 case 'q':
78c66db8 9844 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 9845 break;
9846
252b5132
RH		 9847 case 'o':
9848 if ((given & 0x02000000) != 0)
9849 {
a415b1cd
JB		 9850 unsigned int rotate = (given & 0xf00) >> 7;
9851 unsigned int immed = (given & 0xff);
9852 unsigned int a, i;
9853
9854 a = (((immed << (32 - rotate))
9855 | (immed >> rotate)) & 0xffffffff);
9856 /* If there is another encoding with smaller rotate,
9857 the rotate should be specified directly. */
9858 for (i = 0; i < 32; i += 2)
9859 if ((a << i | a >> (32 - i)) <= 0xff)
9860 break;
9861
9862 if (i != rotate)
9863 func (stream, "#%d, %d", immed, rotate);
9864 else
9865 func (stream, "#%d", a);
9866 value_in_comment = a;
252b5132
RH		 9867 }
9868 else
78c66db8 9869 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 9870 break;
9871
9872 case 'p':
9873 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 9874 {
823d2571
TG		 9875 arm_feature_set arm_ext_v6 =
9876 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
9877
aefd8a40
NC		 9878 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9879 mechanism for setting PSR flag bits. They are
9880 obsolete in V6 onwards. */
823d2571
TG		 9881 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
9882 arm_ext_v6))
aefd8a40 9883 func (stream, "p");
4ab90a7a
AV		 9884 else
9885 is_unpredictable = TRUE;
aefd8a40 9886 }
252b5132
RH		 9887 break;
9888
9889 case 't':
9890 if ((given & 0x01200000) == 0x00200000)
9891 func (stream, "t");
9892 break;
9893
252b5132 9894 case 'A':
05413229
NC		 9895 {
9896 int offset = given & 0xff;
f02232aa 9897
05413229 9898 value_in_comment = offset * 4;
c1e26897 9899 if (NEGATIVE_BIT_SET)
05413229 9900 value_in_comment = - value_in_comment;
f02232aa 9901
05413229 9902 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 9903
c1e26897 9904 if (PRE_BIT_SET)
05413229
NC		 9905 {
9906 if (offset)
fe56b6ce 9907 func (stream, ", #%d]%s",
d908c8af 9908 (int) value_in_comment,
c1e26897 9909 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 9910 else
9911 func (stream, "]");
9912 }
9913 else
9914 {
9915 func (stream, "]");
f02232aa 9916
c1e26897 9917 if (WRITEBACK_BIT_SET)
05413229
NC		 9918 {
9919 if (offset)
d908c8af 9920 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 9921 }
9922 else
fe56b6ce 9923 {
d908c8af 9924 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 9925 value_in_comment = offset;
9926 }
05413229
NC		 9927 }
9928 }
252b5132
RH		 9929 break;
9930
077b8428
NC		 9931 case 'B':
9932 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9933 {
9934 bfd_vma address;
9935 bfd_vma offset = 0;
b34976b6 9936
c1e26897 9937 if (! NEGATIVE_BIT_SET)
077b8428
NC		 9938 /* Is signed, hi bits should be ones. */
9939 offset = (-1) ^ 0x00ffffff;
9940
9941 /* Offset is (SignExtend(offset field)<<2). */
9942 offset += given & 0x00ffffff;
9943 offset <<= 2;
9944 address = offset + pc + 8;
b34976b6 9945
8f06b2d8
PB		 9946 if (given & 0x01000000)
9947 /* H bit allows addressing to 2-byte boundaries. */
9948 address += 2;
b1ee46c5 9949
8f06b2d8 9950 info->print_address_func (address, info);
b1ee46c5 9951 }
b1ee46c5
AH		 9952 break;
9953
252b5132 9954 case 'C':
90ec0d68
MGD		 9955 if ((given & 0x02000200) == 0x200)
9956 {
9957 const char * name;
9958 unsigned sysm = (given & 0x004f0000) >> 16;
9959
9960 sysm |= (given & 0x300) >> 4;
9961 name = banked_regname (sysm);
9962
9963 if (name != NULL)
9964 func (stream, "%s", name);
9965 else
d908c8af 9966 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 9967 }
9968 else
9969 {
43e65147 9970 func (stream, "%cPSR_",
90ec0d68
MGD		 9971 (given & 0x00400000) ? 'S' : 'C');
9972 if (given & 0x80000)
9973 func (stream, "f");
9974 if (given & 0x40000)
9975 func (stream, "s");
9976 if (given & 0x20000)
9977 func (stream, "x");
9978 if (given & 0x10000)
9979 func (stream, "c");
9980 }
252b5132
RH		 9981 break;
9982
62b3e311 9983 case 'U':
43e65147 9984 if ((given & 0xf0) == 0x60)
62b3e311 9985 {
52e7f43d
RE		 9986 switch (given & 0xf)
9987 {
9988 case 0xf: func (stream, "sy"); break;
9989 default:
9990 func (stream, "#%d", (int) given & 0xf);
9991 break;
9992 }
43e65147
L		 9993 }
9994 else
52e7f43d 9995 {
e797f7e0
MGD		 9996 const char * opt = data_barrier_option (given & 0xf);
9997 if (opt != NULL)
9998 func (stream, "%s", opt);
9999 else
52e7f43d 10000 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10001 }
10002 break;
10003
b34976b6 10004 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10005 case '5': case '6': case '7': case '8': case '9':
10006 {
16980d0b
JB		 10007 int width;
10008 unsigned long value;
252b5132 10009
16980d0b 10010 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10011
252b5132
RH		 10012 switch (*c)
10013 {
ab8e2090
NC		 10014 case 'R':
10015 if (value == 15)
10016 is_unpredictable = TRUE;
10017 /* Fall through. */
16980d0b 10018 case 'r':
9eb6c0f1
MGD		 10019 case 'T':
10020 /* We want register + 1 when decoding T. */
10021 if (*c == 'T')
10022 ++value;
10023
ff4a8d2b
NC		 10024 if (c[1] == 'u')
10025 {
10026 /* Eat the 'u' character. */
10027 ++ c;
10028
10029 if (u_reg == value)
10030 is_unpredictable = TRUE;
10031 u_reg = value;
10032 }
10033 if (c[1] == 'U')
10034 {
10035 /* Eat the 'U' character. */
10036 ++ c;
10037
10038 if (U_reg == value)
10039 is_unpredictable = TRUE;
10040 U_reg = value;
10041 }
16980d0b
JB		 10042 func (stream, "%s", arm_regnames[value]);
10043 break;
10044 case 'd':
10045 func (stream, "%ld", value);
05413229 10046 value_in_comment = value;
16980d0b
JB		 10047 break;
10048 case 'b':
10049 func (stream, "%ld", value * 8);
05413229 10050 value_in_comment = value * 8;
16980d0b
JB		 10051 break;
10052 case 'W':
10053 func (stream, "%ld", value + 1);
05413229 10054 value_in_comment = value + 1;
16980d0b
JB		 10055 break;
10056 case 'x':
10057 func (stream, "0x%08lx", value);
10058
10059 /* Some SWI instructions have special
10060 meanings. */
10061 if ((given & 0x0fffffff) == 0x0FF00000)
10062 func (stream, "\t; IMB");
10063 else if ((given & 0x0fffffff) == 0x0FF00001)
10064 func (stream, "\t; IMBRange");
10065 break;
10066 case 'X':
10067 func (stream, "%01lx", value & 0xf);
05413229 10068 value_in_comment = value;
252b5132
RH		 10069 break;
10070 case '`':
10071 c++;
16980d0b 10072 if (value == 0)
252b5132
RH		 10073 func (stream, "%c", *c);
10074 break;
10075 case '\'':
10076 c++;
16980d0b 10077 if (value == ((1ul << width) - 1))
252b5132
RH		 10078 func (stream, "%c", *c);
10079 break;
10080 case '?':
fe56b6ce 10081 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10082 c += 1 << width;
252b5132
RH		 10083 break;
10084 default:
10085 abort ();
10086 }
dffaa15c
AM		 10087 }
10088 break;
0dd132b6 10089
dffaa15c
AM		 10090 case 'e':
10091 {
10092 int imm;
0dd132b6 10093
dffaa15c
AM		 10094 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10095 func (stream, "%d", imm);
10096 value_in_comment = imm;
10097 }
10098 break;
fe56b6ce 10099
dffaa15c
AM		 10100 case 'E':
10101 /* LSB and WIDTH fields of BFI or BFC. The machine-
10102 language instruction encodes LSB and MSB. */
10103 {
10104 long msb = (given & 0x001f0000) >> 16;
10105 long lsb = (given & 0x00000f80) >> 7;
10106 long w = msb - lsb + 1;
0a003adc 10107
dffaa15c
AM		 10108 if (w > 0)
10109 func (stream, "#%lu, #%lu", lsb, w);
10110 else
10111 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10112 }
10113 break;
90ec0d68 10114
dffaa15c
AM		 10115 case 'R':
10116 /* Get the PSR/banked register name. */
10117 {
10118 const char * name;
10119 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10120
dffaa15c
AM		 10121 sysm |= (given & 0x300) >> 4;
10122 name = banked_regname (sysm);
90ec0d68 10123
dffaa15c
AM		 10124 if (name != NULL)
10125 func (stream, "%s", name);
10126 else
10127 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10128 }
10129 break;
fe56b6ce 10130
dffaa15c
AM		 10131 case 'V':
10132 /* 16-bit unsigned immediate from a MOVT or MOVW
10133 instruction, encoded in bits 0:11 and 15:19. */
10134 {
10135 long hi = (given & 0x000f0000) >> 4;
10136 long lo = (given & 0x00000fff);
10137 long imm16 = hi | lo;
0a003adc 10138
dffaa15c
AM		 10139 func (stream, "#%lu", imm16);
10140 value_in_comment = imm16;
252b5132 10141 }
dffaa15c
AM		 10142 break;
10143
10144 default:
10145 abort ();
252b5132
RH		 10146 }
10147 }
10148 else
10149 func (stream, "%c", *c);
10150 }
05413229
NC		 10151
10152 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10153 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10154
10155 if (is_unpredictable)
10156 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10157
4a5329c6 10158 return;
252b5132
RH		 10159 }
10160 }
0b347048
TC		 10161 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10162 return;
252b5132
RH		 10163}
10164
4a5329c6 10165/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10166
4a5329c6
ZW		 10167static void
10168print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10169{
6b5d3a4d 10170 const struct opcode16 *insn;
6a51a8a8
AM		 10171 void *stream = info->stream;
10172 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10173
10174 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10175 if ((given & insn->mask) == insn->value)
10176 {
05413229 10177 signed long value_in_comment = 0;
6b5d3a4d 10178 const char *c = insn->assembler;
05413229 10179
c19d1205
ZW		 10180 for (; *c; c++)
10181 {
10182 int domaskpc = 0;
10183 int domasklr = 0;
10184
10185 if (*c != '%')
10186 {
10187 func (stream, "%c", *c);
10188 continue;
10189 }
252b5132 10190
c19d1205
ZW		 10191 switch (*++c)
10192 {
10193 case '%':
10194 func (stream, "%%");
10195 break;
b34976b6 10196
c22aaad1
PB		 10197 case 'c':
10198 if (ifthen_state)
10199 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10200 break;
10201
10202 case 'C':
10203 if (ifthen_state)
10204 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10205 else
10206 func (stream, "s");
10207 break;
10208
10209 case 'I':
10210 {
10211 unsigned int tmp;
10212
10213 ifthen_next_state = given & 0xff;
10214 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10215 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10216 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10217 }
10218 break;
10219
10220 case 'x':
10221 if (ifthen_next_state)
10222 func (stream, "\t; unpredictable branch in IT block\n");
10223 break;
10224
10225 case 'X':
10226 if (ifthen_state)
10227 func (stream, "\t; unpredictable <IT:%s>",
10228 arm_conditional[IFTHEN_COND]);
10229 break;
10230
c19d1205
ZW		 10231 case 'S':
10232 {
10233 long reg;
10234
10235 reg = (given >> 3) & 0x7;
10236 if (given & (1 << 6))
10237 reg += 8;
4f3c3dbb 10238
c19d1205
ZW		 10239 func (stream, "%s", arm_regnames[reg]);
10240 }
10241 break;
baf0cc5e 10242
c19d1205 10243 case 'D':
4f3c3dbb 10244 {
c19d1205
ZW		 10245 long reg;
10246
10247 reg = given & 0x7;
10248 if (given & (1 << 7))
10249 reg += 8;
10250
10251 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10252 }
c19d1205
ZW		 10253 break;
10254
10255 case 'N':
10256 if (given & (1 << 8))
10257 domasklr = 1;
10258 /* Fall through. */
10259 case 'O':
10260 if (*c == 'O' && (given & (1 << 8)))
10261 domaskpc = 1;
10262 /* Fall through. */
10263 case 'M':
10264 {
10265 int started = 0;
10266 int reg;
10267
10268 func (stream, "{");
10269
10270 /* It would be nice if we could spot
10271 ranges, and generate the rS-rE format: */
10272 for (reg = 0; (reg < 8); reg++)
10273 if ((given & (1 << reg)) != 0)
10274 {
10275 if (started)
10276 func (stream, ", ");
10277 started = 1;
10278 func (stream, "%s", arm_regnames[reg]);
10279 }
10280
10281 if (domasklr)
10282 {
10283 if (started)
10284 func (stream, ", ");
10285 started = 1;
d908c8af 10286 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10287 }
10288
10289 if (domaskpc)
10290 {
10291 if (started)
10292 func (stream, ", ");
d908c8af 10293 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10294 }
10295
10296 func (stream, "}");
10297 }
10298 break;
10299
4547cb56
NC		 10300 case 'W':
10301 /* Print writeback indicator for a LDMIA. We are doing a
10302 writeback if the base register is not in the register
10303 mask. */
10304 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10305 func (stream, "!");
dffaa15c 10306 break;
4547cb56 10307
c19d1205
ZW		 10308 case 'b':
10309 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10310 {
10311 bfd_vma address = (pc + 4
10312 + ((given & 0x00f8) >> 2)
10313 + ((given & 0x0200) >> 3));
10314 info->print_address_func (address, info);
10315 }
10316 break;
10317
10318 case 's':
10319 /* Right shift immediate -- bits 6..10; 1-31 print
10320 as themselves, 0 prints as 32. */
10321 {
10322 long imm = (given & 0x07c0) >> 6;
10323 if (imm == 0)
10324 imm = 32;
0fd3a477 10325 func (stream, "#%ld", imm);
c19d1205
ZW		 10326 }
10327 break;
10328
10329 case '0': case '1': case '2': case '3': case '4':
10330 case '5': case '6': case '7': case '8': case '9':
10331 {
10332 int bitstart = *c++ - '0';
10333 int bitend = 0;
10334
10335 while (*c >= '0' && *c <= '9')
10336 bitstart = (bitstart * 10) + *c++ - '0';
10337
10338 switch (*c)
10339 {
10340 case '-':
10341 {
f8b960bc 10342 bfd_vma reg;
c19d1205
ZW		 10343
10344 c++;
10345 while (*c >= '0' && *c <= '9')
10346 bitend = (bitend * 10) + *c++ - '0';
10347 if (!bitend)
10348 abort ();
10349 reg = given >> bitstart;
10350 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10351
c19d1205
ZW		 10352 switch (*c)
10353 {
10354 case 'r':
10355 func (stream, "%s", arm_regnames[reg]);
10356 break;
10357
10358 case 'd':
d908c8af 10359 func (stream, "%ld", (long) reg);
05413229 10360 value_in_comment = reg;
c19d1205
ZW		 10361 break;
10362
10363 case 'H':
d908c8af 10364 func (stream, "%ld", (long) (reg << 1));
05413229 10365 value_in_comment = reg << 1;
c19d1205
ZW		 10366 break;
10367
10368 case 'W':
d908c8af 10369 func (stream, "%ld", (long) (reg << 2));
05413229 10370 value_in_comment = reg << 2;
c19d1205
ZW		 10371 break;
10372
10373 case 'a':
10374 /* PC-relative address -- the bottom two
10375 bits of the address are dropped
10376 before the calculation. */
10377 info->print_address_func
10378 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10379 value_in_comment = 0;
c19d1205
ZW		 10380 break;
10381
10382 case 'x':
d908c8af 10383 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10384 break;
10385
c19d1205
ZW		 10386 case 'B':
10387 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
6b5d3a4d 10388 info->print_address_func (reg * 2 + pc + 4, info);
05413229 10389 value_in_comment = 0;
c19d1205
ZW		 10390 break;
10391
10392 case 'c':
c22aaad1 10393 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10394 break;
10395
10396 default:
10397 abort ();
10398 }
10399 }
10400 break;
10401
10402 case '\'':
10403 c++;
10404 if ((given & (1 << bitstart)) != 0)
10405 func (stream, "%c", *c);
10406 break;
10407
10408 case '?':
10409 ++c;
10410 if ((given & (1 << bitstart)) != 0)
10411 func (stream, "%c", *c++);
10412 else
10413 func (stream, "%c", *++c);
10414 break;
10415
10416 default:
10417 abort ();
10418 }
10419 }
10420 break;
10421
10422 default:
10423 abort ();
10424 }
10425 }
05413229
NC		 10426
10427 if (value_in_comment > 32 || value_in_comment < -16)
10428 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10429 return;
c19d1205
ZW		 10430 }
10431
10432 /* No match. */
0b347048
TC		 10433 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10434 return;
c19d1205
ZW		 10435}
10436
62b3e311 10437/* Return the name of an V7M special register. */
fe56b6ce 10438
62b3e311
PB		 10439static const char *
10440psr_name (int regno)
10441{
10442 switch (regno)
10443 {
1a336194
TP		 10444 case 0x0: return "APSR";
10445 case 0x1: return "IAPSR";
10446 case 0x2: return "EAPSR";
10447 case 0x3: return "PSR";
10448 case 0x5: return "IPSR";
10449 case 0x6: return "EPSR";
10450 case 0x7: return "IEPSR";
10451 case 0x8: return "MSP";
10452 case 0x9: return "PSP";
10453 case 0xa: return "MSPLIM";
10454 case 0xb: return "PSPLIM";
10455 case 0x10: return "PRIMASK";
10456 case 0x11: return "BASEPRI";
10457 case 0x12: return "BASEPRI_MAX";
10458 case 0x13: return "FAULTMASK";
10459 case 0x14: return "CONTROL";
16a1fa25
TP		 10460 case 0x88: return "MSP_NS";
10461 case 0x89: return "PSP_NS";
1a336194
TP		 10462 case 0x8a: return "MSPLIM_NS";
10463 case 0x8b: return "PSPLIM_NS";
10464 case 0x90: return "PRIMASK_NS";
10465 case 0x91: return "BASEPRI_NS";
10466 case 0x93: return "FAULTMASK_NS";
10467 case 0x94: return "CONTROL_NS";
10468 case 0x98: return "SP_NS";
62b3e311
PB		 10469 default: return "<unknown>";
10470 }
10471}
10472
4a5329c6
ZW		 10473/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10474
10475static void
10476print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10477{
6b5d3a4d 10478 const struct opcode32 *insn;
c19d1205
ZW		 10479 void *stream = info->stream;
10480 fprintf_ftype func = info->fprintf_func;
73cd51e5 10481 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10482
16980d0b
JB		 10483 if (print_insn_coprocessor (pc, info, given, TRUE))
10484 return;
10485
73cd51e5
AV		 10486 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10487 return;
10488
10489 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10490 return;
10491
c19d1205
ZW		 10492 for (insn = thumb32_opcodes; insn->assembler; insn++)
10493 if ((given & insn->mask) == insn->value)
10494 {
4b5a202f 10495 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10496 bfd_boolean is_unpredictable = FALSE;
05413229 10497 signed long value_in_comment = 0;
6b5d3a4d 10498 const char *c = insn->assembler;
05413229 10499
c19d1205
ZW		 10500 for (; *c; c++)
10501 {
10502 if (*c != '%')
10503 {
10504 func (stream, "%c", *c);
10505 continue;
10506 }
10507
10508 switch (*++c)
10509 {
10510 case '%':
10511 func (stream, "%%");
10512 break;
10513
c22aaad1
PB		 10514 case 'c':
10515 if (ifthen_state)
10516 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10517 break;
10518
10519 case 'x':
10520 if (ifthen_next_state)
10521 func (stream, "\t; unpredictable branch in IT block\n");
10522 break;
10523
10524 case 'X':
10525 if (ifthen_state)
10526 func (stream, "\t; unpredictable <IT:%s>",
10527 arm_conditional[IFTHEN_COND]);
10528 break;
10529
c19d1205
ZW		 10530 case 'I':
10531 {
10532 unsigned int imm12 = 0;
fe56b6ce 10533
c19d1205
ZW		 10534 imm12 |= (given & 0x000000ffu);
10535 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10536 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10537 func (stream, "#%u", imm12);
10538 value_in_comment = imm12;
c19d1205
ZW		 10539 }
10540 break;
10541
10542 case 'M':
10543 {
10544 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10545
c19d1205
ZW		 10546 bits |= (given & 0x000000ffu);
10547 bits |= (given & 0x00007000u) >> 4;
10548 bits |= (given & 0x04000000u) >> 15;
10549 imm8 = (bits & 0x0ff);
10550 mod = (bits & 0xf00) >> 8;
10551 switch (mod)
10552 {
10553 case 0: imm = imm8; break;
c1e26897
NC		 10554 case 1: imm = ((imm8 << 16) | imm8); break;
10555 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10556 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10557 default:
10558 mod = (bits & 0xf80) >> 7;
10559 imm8 = (bits & 0x07f) | 0x80;
10560 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10561 }
fe56b6ce
NC		 10562 func (stream, "#%u", imm);
10563 value_in_comment = imm;
c19d1205
ZW		 10564 }
10565 break;
43e65147 10566
c19d1205
ZW		 10567 case 'J':
10568 {
10569 unsigned int imm = 0;
fe56b6ce 10570
c19d1205
ZW		 10571 imm |= (given & 0x000000ffu);
10572 imm |= (given & 0x00007000u) >> 4;
10573 imm |= (given & 0x04000000u) >> 15;
10574 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10575 func (stream, "#%u", imm);
10576 value_in_comment = imm;
c19d1205
ZW		 10577 }
10578 break;
10579
10580 case 'K':
10581 {
10582 unsigned int imm = 0;
fe56b6ce 10583
c19d1205
ZW		 10584 imm |= (given & 0x000f0000u) >> 16;
10585 imm |= (given & 0x00000ff0u) >> 0;
10586 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10587 func (stream, "#%u", imm);
10588 value_in_comment = imm;
c19d1205
ZW		 10589 }
10590 break;
10591
74db7efb
NC		 10592 case 'H':
10593 {
10594 unsigned int imm = 0;
10595
10596 imm |= (given & 0x000f0000u) >> 4;
10597 imm |= (given & 0x00000fffu) >> 0;
10598 func (stream, "#%u", imm);
10599 value_in_comment = imm;
10600 }
10601 break;
10602
90ec0d68
MGD		 10603 case 'V':
10604 {
10605 unsigned int imm = 0;
10606
10607 imm |= (given & 0x00000fffu);
10608 imm |= (given & 0x000f0000u) >> 4;
10609 func (stream, "#%u", imm);
10610 value_in_comment = imm;
10611 }
10612 break;
10613
c19d1205
ZW		 10614 case 'S':
10615 {
10616 unsigned int reg = (given & 0x0000000fu);
10617 unsigned int stp = (given & 0x00000030u) >> 4;
10618 unsigned int imm = 0;
10619 imm |= (given & 0x000000c0u) >> 6;
10620 imm |= (given & 0x00007000u) >> 10;
10621
10622 func (stream, "%s", arm_regnames[reg]);
10623 switch (stp)
10624 {
10625 case 0:
10626 if (imm > 0)
10627 func (stream, ", lsl #%u", imm);
10628 break;
10629
10630 case 1:
10631 if (imm == 0)
10632 imm = 32;
10633 func (stream, ", lsr #%u", imm);
10634 break;
10635
10636 case 2:
10637 if (imm == 0)
10638 imm = 32;
10639 func (stream, ", asr #%u", imm);
10640 break;
10641
10642 case 3:
10643 if (imm == 0)
10644 func (stream, ", rrx");
10645 else
10646 func (stream, ", ror #%u", imm);
10647 }
10648 }
10649 break;
10650
10651 case 'a':
10652 {
10653 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 10654 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 10655 unsigned int op = (given & 0x00000f00) >> 8;
10656 unsigned int i12 = (given & 0x00000fff);
10657 unsigned int i8 = (given & 0x000000ff);
10658 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 10659 bfd_vma offset = 0;
c19d1205
ZW		 10660
10661 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 10662 if (U) /* 12-bit positive immediate offset. */
10663 {
10664 offset = i12;
10665 if (Rn != 15)
10666 value_in_comment = offset;
10667 }
10668 else if (Rn == 15) /* 12-bit negative immediate offset. */
10669 offset = - (int) i12;
10670 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 10671 {
10672 unsigned int Rm = (i8 & 0x0f);
10673 unsigned int sh = (i8 & 0x30) >> 4;
05413229 10674
c19d1205
ZW		 10675 func (stream, ", %s", arm_regnames[Rm]);
10676 if (sh)
10677 func (stream, ", lsl #%u", sh);
10678 func (stream, "]");
10679 break;
10680 }
10681 else switch (op)
10682 {
05413229 10683 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 10684 offset = i8;
10685 break;
10686
05413229 10687 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 10688 offset = -i8;
10689 break;
10690
05413229 10691 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 10692 offset = i8;
10693 writeback = TRUE;
10694 break;
10695
05413229 10696 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 10697 offset = -i8;
10698 writeback = TRUE;
10699 break;
10700
05413229 10701 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 10702 offset = i8;
10703 postind = TRUE;
10704 break;
10705
05413229 10706 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 10707 offset = -i8;
10708 postind = TRUE;
10709 break;
10710
10711 default:
10712 func (stream, ", <undefined>]");
10713 goto skip;
10714 }
10715
10716 if (postind)
d908c8af 10717 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 10718 else
10719 {
10720 if (offset)
d908c8af 10721 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 10722 func (stream, writeback ? "]!" : "]");
10723 }
10724
10725 if (Rn == 15)
10726 {
10727 func (stream, "\t; ");
10728 info->print_address_func (((pc + 4) & ~3) + offset, info);
10729 }
10730 }
10731 skip:
10732 break;
10733
10734 case 'A':
10735 {
c1e26897
NC		 10736 unsigned int U = ! NEGATIVE_BIT_SET;
10737 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 10738 unsigned int Rn = (given & 0x000f0000) >> 16;
10739 unsigned int off = (given & 0x000000ff);
10740
10741 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 10742
10743 if (PRE_BIT_SET)
c19d1205
ZW		 10744 {
10745 if (off || !U)
05413229
NC		 10746 {
10747 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 10748 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10749 }
c19d1205
ZW		 10750 func (stream, "]");
10751 if (W)
10752 func (stream, "!");
10753 }
10754 else
10755 {
10756 func (stream, "], ");
10757 if (W)
05413229
NC		 10758 {
10759 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 10760 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 10761 }
c19d1205 10762 else
fe56b6ce
NC		 10763 {
10764 func (stream, "{%u}", off);
10765 value_in_comment = off;
10766 }
c19d1205
ZW		 10767 }
10768 }
10769 break;
10770
10771 case 'w':
10772 {
10773 unsigned int Sbit = (given & 0x01000000) >> 24;
10774 unsigned int type = (given & 0x00600000) >> 21;
05413229 10775
c19d1205
ZW		 10776 switch (type)
10777 {
10778 case 0: func (stream, Sbit ? "sb" : "b"); break;
10779 case 1: func (stream, Sbit ? "sh" : "h"); break;
10780 case 2:
10781 if (Sbit)
10782 func (stream, "??");
10783 break;
10784 case 3:
10785 func (stream, "??");
10786 break;
10787 }
10788 }
10789 break;
10790
4b5a202f
AV		 10791 case 'n':
10792 is_clrm = TRUE;
10793 /* Fall through. */
c19d1205
ZW		 10794 case 'm':
10795 {
10796 int started = 0;
10797 int reg;
10798
10799 func (stream, "{");
10800 for (reg = 0; reg < 16; reg++)
10801 if ((given & (1 << reg)) != 0)
10802 {
10803 if (started)
10804 func (stream, ", ");
10805 started = 1;
4b5a202f
AV		 10806 if (is_clrm && reg == 13)
10807 func (stream, "(invalid: %s)", arm_regnames[reg]);
10808 else if (is_clrm && reg == 15)
10809 func (stream, "%s", "APSR");
10810 else
10811 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 10812 }
10813 func (stream, "}");
10814 }
10815 break;
10816
10817 case 'E':
10818 {
10819 unsigned int msb = (given & 0x0000001f);
10820 unsigned int lsb = 0;
fe56b6ce 10821
c19d1205
ZW		 10822 lsb |= (given & 0x000000c0u) >> 6;
10823 lsb |= (given & 0x00007000u) >> 10;
10824 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
10825 }
10826 break;
10827
10828 case 'F':
10829 {
10830 unsigned int width = (given & 0x0000001f) + 1;
10831 unsigned int lsb = 0;
fe56b6ce 10832
c19d1205
ZW		 10833 lsb |= (given & 0x000000c0u) >> 6;
10834 lsb |= (given & 0x00007000u) >> 10;
10835 func (stream, "#%u, #%u", lsb, width);
10836 }
10837 break;
10838
e12437dc
AV		 10839 case 'G':
10840 {
10841 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
10842 func (stream, "%x", boff);
10843 }
10844 break;
10845
e5d6e09e
AV		 10846 case 'W':
10847 {
10848 unsigned int immA = (given & 0x001f0000u) >> 16;
10849 unsigned int immB = (given & 0x000007feu) >> 1;
10850 unsigned int immC = (given & 0x00000800u) >> 11;
10851 bfd_vma offset = 0;
10852
10853 offset |= immA << 12;
10854 offset |= immB << 2;
10855 offset |= immC << 1;
10856 /* Sign extend. */
10857 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
10858
10859 info->print_address_func (pc + 4 + offset, info);
10860 }
10861 break;
10862
1caf72a5
AV		 10863 case 'Y':
10864 {
10865 unsigned int immA = (given & 0x007f0000u) >> 16;
10866 unsigned int immB = (given & 0x000007feu) >> 1;
10867 unsigned int immC = (given & 0x00000800u) >> 11;
10868 bfd_vma offset = 0;
10869
10870 offset |= immA << 12;
10871 offset |= immB << 2;
10872 offset |= immC << 1;
10873 /* Sign extend. */
10874 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
10875
10876 info->print_address_func (pc + 4 + offset, info);
10877 }
10878 break;
10879
1889da70
AV		 10880 case 'Z':
10881 {
10882 unsigned int immA = (given & 0x00010000u) >> 16;
10883 unsigned int immB = (given & 0x000007feu) >> 1;
10884 unsigned int immC = (given & 0x00000800u) >> 11;
10885 bfd_vma offset = 0;
10886
10887 offset |= immA << 12;
10888 offset |= immB << 2;
10889 offset |= immC << 1;
10890 /* Sign extend. */
10891 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
10892
10893 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 10894
10895 unsigned int T = (given & 0x00020000u) >> 17;
10896 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
10897 unsigned int boffset = (T == 1) ? 4 : 2;
10898 func (stream, ", ");
10899 func (stream, "%x", endoffset + boffset);
1889da70
AV		 10900 }
10901 break;
10902
60f993ce
AV		 10903 case 'Q':
10904 {
10905 unsigned int immh = (given & 0x000007feu) >> 1;
10906 unsigned int imml = (given & 0x00000800u) >> 11;
10907 bfd_vma imm32 = 0;
10908
10909 imm32 |= immh << 2;
10910 imm32 |= imml << 1;
10911
10912 info->print_address_func (pc + 4 + imm32, info);
10913 }
10914 break;
10915
10916 case 'P':
10917 {
10918 unsigned int immh = (given & 0x000007feu) >> 1;
10919 unsigned int imml = (given & 0x00000800u) >> 11;
10920 bfd_vma imm32 = 0;
10921
10922 imm32 |= immh << 2;
10923 imm32 |= imml << 1;
10924
10925 info->print_address_func (pc + 4 - imm32, info);
10926 }
10927 break;
10928
c19d1205
ZW		 10929 case 'b':
10930 {
10931 unsigned int S = (given & 0x04000000u) >> 26;
10932 unsigned int J1 = (given & 0x00002000u) >> 13;
10933 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 10934 bfd_vma offset = 0;
c19d1205
ZW		 10935
10936 offset |= !S << 20;
10937 offset |= J2 << 19;
10938 offset |= J1 << 18;
10939 offset |= (given & 0x003f0000) >> 4;
10940 offset |= (given & 0x000007ff) << 1;
10941 offset -= (1 << 20);
10942
10943 info->print_address_func (pc + 4 + offset, info);
10944 }
10945 break;
10946
10947 case 'B':
10948 {
10949 unsigned int S = (given & 0x04000000u) >> 26;
10950 unsigned int I1 = (given & 0x00002000u) >> 13;
10951 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 10952 bfd_vma offset = 0;
c19d1205
ZW		 10953
10954 offset |= !S << 24;
10955 offset |= !(I1 ^ S) << 23;
10956 offset |= !(I2 ^ S) << 22;
10957 offset |= (given & 0x03ff0000u) >> 4;
10958 offset |= (given & 0x000007ffu) << 1;
10959 offset -= (1 << 24);
36b0c57d 10960 offset += pc + 4;
c19d1205 10961
36b0c57d
PB		 10962 /* BLX target addresses are always word aligned. */
10963 if ((given & 0x00001000u) == 0)
10964 offset &= ~2u;
10965
10966 info->print_address_func (offset, info);
c19d1205
ZW		 10967 }
10968 break;
10969
10970 case 's':
10971 {
10972 unsigned int shift = 0;
fe56b6ce 10973
c19d1205
ZW		 10974 shift |= (given & 0x000000c0u) >> 6;
10975 shift |= (given & 0x00007000u) >> 10;
c1e26897 10976 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 10977 func (stream, ", asr #%u", shift);
10978 else if (shift)
10979 func (stream, ", lsl #%u", shift);
10980 /* else print nothing - lsl #0 */
10981 }
10982 break;
10983
10984 case 'R':
10985 {
10986 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 10987
c19d1205
ZW		 10988 if (rot)
10989 func (stream, ", ror #%u", rot * 8);
10990 }
10991 break;
10992
62b3e311 10993 case 'U':
43e65147 10994 if ((given & 0xf0) == 0x60)
62b3e311 10995 {
52e7f43d
RE		 10996 switch (given & 0xf)
10997 {
10998 case 0xf: func (stream, "sy"); break;
10999 default:
11000 func (stream, "#%d", (int) given & 0xf);
11001 break;
11002 }
62b3e311 11003 }
43e65147 11004 else
52e7f43d 11005 {
e797f7e0
MGD		 11006 const char * opt = data_barrier_option (given & 0xf);
11007 if (opt != NULL)
11008 func (stream, "%s", opt);
11009 else
11010 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11011 }
62b3e311
PB		 11012 break;
11013
11014 case 'C':
11015 if ((given & 0xff) == 0)
11016 {
11017 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11018 if (given & 0x800)
11019 func (stream, "f");
11020 if (given & 0x400)
11021 func (stream, "s");
11022 if (given & 0x200)
11023 func (stream, "x");
11024 if (given & 0x100)
11025 func (stream, "c");
11026 }
90ec0d68
MGD		 11027 else if ((given & 0x20) == 0x20)
11028 {
11029 char const* name;
11030 unsigned sysm = (given & 0xf00) >> 8;
11031
11032 sysm |= (given & 0x30);
11033 sysm |= (given & 0x00100000) >> 14;
11034 name = banked_regname (sysm);
43e65147 11035
90ec0d68
MGD		 11036 if (name != NULL)
11037 func (stream, "%s", name);
11038 else
d908c8af 11039 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11040 }
62b3e311
PB		 11041 else
11042 {
d908c8af 11043 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11044 }
11045 break;
11046
11047 case 'D':
90ec0d68
MGD		 11048 if (((given & 0xff) == 0)
11049 || ((given & 0x20) == 0x20))
11050 {
11051 char const* name;
11052 unsigned sm = (given & 0xf0000) >> 16;
11053
11054 sm |= (given & 0x30);
11055 sm |= (given & 0x00100000) >> 14;
11056 name = banked_regname (sm);
11057
11058 if (name != NULL)
11059 func (stream, "%s", name);
11060 else
d908c8af 11061 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11062 }
62b3e311 11063 else
d908c8af 11064 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11065 break;
11066
c19d1205
ZW		 11067 case '0': case '1': case '2': case '3': case '4':
11068 case '5': case '6': case '7': case '8': case '9':
11069 {
16980d0b
JB		 11070 int width;
11071 unsigned long val;
c19d1205 11072
16980d0b 11073 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11074
c19d1205
ZW		 11075 switch (*c)
11076 {
d052b9b7
AV		 11077 case 's':
11078 if (val <= 3)
11079 func (stream, "%s", mve_vec_sizename[val]);
11080 else
11081 func (stream, "<undef size>");
11082 break;
11083
05413229
NC		 11084 case 'd':
11085 func (stream, "%lu", val);
11086 value_in_comment = val;
11087 break;
ff4a8d2b 11088
f0fba320
RL		 11089 case 'D':
11090 func (stream, "%lu", val + 1);
11091 value_in_comment = val + 1;
11092 break;
11093
05413229
NC		 11094 case 'W':
11095 func (stream, "%lu", val * 4);
11096 value_in_comment = val * 4;
11097 break;
ff4a8d2b 11098
f1c7f421
AV		 11099 case 'S':
11100 if (val == 13)
11101 is_unpredictable = TRUE;
11102 /* Fall through. */
ff4a8d2b
NC		 11103 case 'R':
11104 if (val == 15)
11105 is_unpredictable = TRUE;
11106 /* Fall through. */
11107 case 'r':
11108 func (stream, "%s", arm_regnames[val]);
11109 break;
c19d1205
ZW		 11110
11111 case 'c':
c22aaad1 11112 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11113 break;
11114
11115 case '\'':
c19d1205 11116 c++;
16980d0b
JB		 11117 if (val == ((1ul << width) - 1))
11118 func (stream, "%c", *c);
c19d1205 11119 break;
43e65147 11120
c19d1205 11121 case '`':
c19d1205 11122 c++;
16980d0b
JB		 11123 if (val == 0)
11124 func (stream, "%c", *c);
c19d1205
ZW		 11125 break;
11126
11127 case '?':
fe56b6ce 11128 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11129 c += 1 << width;
c19d1205 11130 break;
43e65147 11131
0bb027fd
RR		 11132 case 'x':
11133 func (stream, "0x%lx", val & 0xffffffffUL);
11134 break;
c19d1205
ZW		 11135
11136 default:
11137 abort ();
11138 }
11139 }
11140 break;
11141
32a94698
NC		 11142 case 'L':
11143 /* PR binutils/12534
11144 If we have a PC relative offset in an LDRD or STRD
11145 instructions then display the decoded address. */
11146 if (((given >> 16) & 0xf) == 0xf)
11147 {
11148 bfd_vma offset = (given & 0xff) * 4;
11149
11150 if ((given & (1 << 23)) == 0)
11151 offset = - offset;
11152 func (stream, "\t; ");
11153 info->print_address_func ((pc & ~3) + 4 + offset, info);
11154 }
11155 break;
11156
c19d1205
ZW		 11157 default:
11158 abort ();
11159 }
11160 }
05413229
NC		 11161
11162 if (value_in_comment > 32 || value_in_comment < -16)
11163 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11164
11165 if (is_unpredictable)
11166 func (stream, UNPREDICTABLE_INSTRUCTION);
11167
4a5329c6 11168 return;
c19d1205 11169 }
252b5132 11170
58efb6c0 11171 /* No match. */
0b347048
TC		 11172 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11173 return;
252b5132
RH		 11174}
11175
e821645d
DJ		 11176/* Print data bytes on INFO->STREAM. */
11177
11178static void
fe56b6ce
NC		 11179print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11180 struct disassemble_info *info,
e821645d
DJ		 11181 long given)
11182{
11183 switch (info->bytes_per_chunk)
11184 {
11185 case 1:
11186 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11187 break;
11188 case 2:
11189 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11190 break;
11191 case 4:
11192 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11193 break;
11194 default:
11195 abort ();
11196 }
11197}
11198
22a398e1 11199/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11200 being displayed in symbol relative addresses.
11201
11202 Also disallow private symbol, with __tagsym$$ prefix,
11203 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11204
11205bfd_boolean
11206arm_symbol_is_valid (asymbol * sym,
11207 struct disassemble_info * info ATTRIBUTE_UNUSED)
11208{
11209 const char * name;
43e65147 11210
22a398e1
NC		 11211 if (sym == NULL)
11212 return FALSE;
11213
11214 name = bfd_asymbol_name (sym);
11215
d8282f0e 11216 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11217}
11218
65b48a81 11219/* Parse the string of disassembler options. */
baf0cc5e 11220
65b48a81 11221static void
f995bbe8 11222parse_arm_disassembler_options (const char *options)
dd92f639 11223{
f995bbe8 11224 const char *opt;
b34976b6 11225
65b48a81 11226 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11227 {
65b48a81
PB		 11228 if (CONST_STRNEQ (opt, "reg-names-"))
11229 {
11230 unsigned int i;
11231 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11232 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11233 {
11234 regname_selected = i;
11235 break;
11236 }
b34976b6 11237
65b48a81 11238 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11239 /* xgettext: c-format */
11240 opcodes_error_handler (_("unrecognised register name set: %s"),
11241 opt);
65b48a81
PB		 11242 }
11243 else if (CONST_STRNEQ (opt, "force-thumb"))
11244 force_thumb = 1;
11245 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11246 force_thumb = 0;
11247 else
a6743a54
AM		 11248 /* xgettext: c-format */
11249 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11250 }
b34976b6 11251
dd92f639
NC		 11252 return;
11253}
11254
5bc5ae88
RL		 11255static bfd_boolean
11256mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11257 enum map_type *map_symbol);
11258
c22aaad1
PB		 11259/* Search back through the insn stream to determine if this instruction is
11260 conditionally executed. */
fe56b6ce 11261
c22aaad1 11262static void
fe56b6ce
NC		 11263find_ifthen_state (bfd_vma pc,
11264 struct disassemble_info *info,
c22aaad1
PB		 11265 bfd_boolean little)
11266{
11267 unsigned char b[2];
11268 unsigned int insn;
11269 int status;
11270 /* COUNT is twice the number of instructions seen. It will be odd if we
11271 just crossed an instruction boundary. */
11272 int count;
11273 int it_count;
11274 unsigned int seen_it;
11275 bfd_vma addr;
11276
11277 ifthen_address = pc;
11278 ifthen_state = 0;
11279
11280 addr = pc;
11281 count = 1;
11282 it_count = 0;
11283 seen_it = 0;
11284 /* Scan backwards looking for IT instructions, keeping track of where
11285 instruction boundaries are. We don't know if something is actually an
11286 IT instruction until we find a definite instruction boundary. */
11287 for (;;)
11288 {
fe56b6ce 11289 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11290 {
11291 /* A symbol must be on an instruction boundary, and will not
11292 be within an IT block. */
11293 if (seen_it && (count & 1))
11294 break;
11295
11296 return;
11297 }
11298 addr -= 2;
fe56b6ce 11299 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11300 if (status)
11301 return;
11302
11303 if (little)
11304 insn = (b[0]) | (b[1] << 8);
11305 else
11306 insn = (b[1]) | (b[0] << 8);
11307 if (seen_it)
11308 {
11309 if ((insn & 0xf800) < 0xe800)
11310 {
11311 /* Addr + 2 is an instruction boundary. See if this matches
11312 the expected boundary based on the position of the last
11313 IT candidate. */
11314 if (count & 1)
11315 break;
11316 seen_it = 0;
11317 }
11318 }
11319 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11320 {
5bc5ae88
RL		 11321 enum map_type type = MAP_ARM;
11322 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11323
11324 if (!found || (found && type == MAP_THUMB))
11325 {
11326 /* This could be an IT instruction. */
11327 seen_it = insn;
11328 it_count = count >> 1;
11329 }
c22aaad1
PB		 11330 }
11331 if ((insn & 0xf800) >= 0xe800)
11332 count++;
11333 else
11334 count = (count + 2) | 1;
11335 /* IT blocks contain at most 4 instructions. */
11336 if (count >= 8 && !seen_it)
11337 return;
11338 }
11339 /* We found an IT instruction. */
11340 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11341 if ((ifthen_state & 0xf) == 0)
11342 ifthen_state = 0;
11343}
11344
b0e28b39
DJ		 11345/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11346 mapping symbol. */
11347
11348static int
11349is_mapping_symbol (struct disassemble_info *info, int n,
11350 enum map_type *map_type)
11351{
11352 const char *name;
11353
11354 name = bfd_asymbol_name (info->symtab[n]);
11355 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11356 && (name[2] == 0 || name[2] == '.'))
11357 {
11358 *map_type = ((name[1] == 'a') ? MAP_ARM
11359 : (name[1] == 't') ? MAP_THUMB
11360 : MAP_DATA);
11361 return TRUE;
11362 }
11363
11364 return FALSE;
11365}
11366
11367/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11368 Returns nonzero if *MAP_TYPE was set. */
11369
11370static int
11371get_map_sym_type (struct disassemble_info *info,
11372 int n,
11373 enum map_type *map_type)
11374{
11375 /* If the symbol is in a different section, ignore it. */
11376 if (info->section != NULL && info->section != info->symtab[n]->section)
11377 return FALSE;
11378
11379 return is_mapping_symbol (info, n, map_type);
11380}
11381
11382/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11383 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11384
11385static int
fe56b6ce
NC		 11386get_sym_code_type (struct disassemble_info *info,
11387 int n,
e821645d 11388 enum map_type *map_type)
2087ad84
PB		 11389{
11390 elf_symbol_type *es;
11391 unsigned int type;
b0e28b39
DJ		 11392
11393 /* If the symbol is in a different section, ignore it. */
11394 if (info->section != NULL && info->section != info->symtab[n]->section)
11395 return FALSE;
2087ad84 11396
e821645d 11397 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11398 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11399
11400 /* If the symbol has function type then use that. */
34e77a92 11401 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11402 {
39d911fc
TP		 11403 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11404 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11405 *map_type = MAP_THUMB;
11406 else
11407 *map_type = MAP_ARM;
2087ad84
PB		 11408 return TRUE;
11409 }
11410
2087ad84
PB		 11411 return FALSE;
11412}
11413
5bc5ae88
RL		 11414/* Search the mapping symbol state for instruction at pc. This is only
11415 applicable for elf target.
11416
11417 There is an assumption Here, info->private_data contains the correct AND
11418 up-to-date information about current scan process. The information will be
11419 used to speed this search process.
11420
11421 Return TRUE if the mapping state can be determined, and map_symbol
11422 will be updated accordingly. Otherwise, return FALSE. */
11423
11424static bfd_boolean
11425mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11426 enum map_type *map_symbol)
11427{
796d6298
TC		 11428 bfd_vma addr, section_vma = 0;
11429 int n, last_sym = -1;
5bc5ae88 11430 bfd_boolean found = FALSE;
796d6298
TC		 11431 bfd_boolean can_use_search_opt_p = FALSE;
11432
11433 /* Default to DATA. A text section is required by the ABI to contain an
11434 INSN mapping symbol at the start. A data section has no such
11435 requirement, hence if no mapping symbol is found the section must
11436 contain only data. This however isn't very useful if the user has
11437 fully stripped the binaries. If this is the case use the section
11438 attributes to determine the default. If we have no section default to
11439 INSN as well, as we may be disassembling some raw bytes on a baremetal
11440 HEX file or similar. */
11441 enum map_type type = MAP_DATA;
11442 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11443 type = MAP_ARM;
5bc5ae88
RL		 11444 struct arm_private_data *private_data;
11445
796d6298 11446 if (info->private_data == NULL
5bc5ae88
RL		 11447 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11448 return FALSE;
11449
11450 private_data = info->private_data;
5bc5ae88 11451
796d6298
TC		 11452 /* First, look for mapping symbols. */
11453 if (info->symtab_size != 0)
11454 {
11455 if (pc <= private_data->last_mapping_addr)
11456 private_data->last_mapping_sym = -1;
11457
11458 /* Start scanning at the start of the function, or wherever
11459 we finished last time. */
11460 n = info->symtab_pos + 1;
11461
11462 /* If the last stop offset is different from the current one it means we
11463 are disassembling a different glob of bytes. As such the optimization
11464 would not be safe and we should start over. */
11465 can_use_search_opt_p
11466 = private_data->last_mapping_sym >= 0
11467 && info->stop_offset == private_data->last_stop_offset;
11468
11469 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11470 n = private_data->last_mapping_sym;
11471
11472 /* Look down while we haven't passed the location being disassembled.
11473 The reason for this is that there's no defined order between a symbol
11474 and an mapping symbol that may be at the same address. We may have to
11475 look at least one position ahead. */
11476 for (; n < info->symtab_size; n++)
11477 {
11478 addr = bfd_asymbol_value (info->symtab[n]);
11479 if (addr > pc)
11480 break;
11481 if (get_map_sym_type (info, n, &type))
11482 {
11483 last_sym = n;
11484 found = TRUE;
11485 }
11486 }
5bc5ae88 11487
796d6298
TC		 11488 if (!found)
11489 {
11490 n = info->symtab_pos;
11491 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11492 n = private_data->last_mapping_sym;
11493
11494 /* No mapping symbol found at this address. Look backwards
11495 for a preceeding one, but don't go pass the section start
11496 otherwise a data section with no mapping symbol can pick up
11497 a text mapping symbol of a preceeding section. The documentation
11498 says section can be NULL, in which case we will seek up all the
11499 way to the top. */
11500 if (info->section)
11501 section_vma = info->section->vma;
11502
11503 for (; n >= 0; n--)
11504 {
11505 addr = bfd_asymbol_value (info->symtab[n]);
11506 if (addr < section_vma)
11507 break;
11508
11509 if (get_map_sym_type (info, n, &type))
11510 {
11511 last_sym = n;
11512 found = TRUE;
11513 break;
11514 }
11515 }
11516 }
11517 }
11518
11519 /* If no mapping symbol was found, try looking up without a mapping
11520 symbol. This is done by walking up from the current PC to the nearest
11521 symbol. We don't actually have to loop here since symtab_pos will
11522 contain the nearest symbol already. */
11523 if (!found)
5bc5ae88 11524 {
796d6298
TC		 11525 n = info->symtab_pos;
11526 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11527 {
796d6298
TC		 11528 last_sym = n;
11529 found = TRUE;
5bc5ae88
RL		 11530 }
11531 }
11532
796d6298
TC		 11533 private_data->last_mapping_sym = last_sym;
11534 private_data->last_type = type;
11535 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11536
11537 *map_symbol = type;
11538 return found;
11539}
11540
0313a2b8
NC		 11541/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11542 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11543 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11544
11545 FIXME: This could more efficiently implemented as a constant array,
11546 although it would also be less robust. */
11547
11548static void
11549select_arm_features (unsigned long mach,
11550 arm_feature_set * features)
11551{
c0c468d5
TP		 11552 arm_feature_set arch_fset;
11553 const arm_feature_set fpu_any = FPU_ANY;
11554
1af1dd51
MW		 11555#undef ARM_SET_FEATURES
11556#define ARM_SET_FEATURES(FSET) \
11557 { \
11558 const arm_feature_set fset = FSET; \
c0c468d5 11559 arch_fset = fset; \
1af1dd51 11560 }
823d2571 11561
c0c468d5
TP		 11562 /* When several architecture versions share the same bfd_mach_arm_XXX value
11563 the most featureful is chosen. */
0313a2b8
NC		 11564 switch (mach)
11565 {
c0c468d5
TP		 11566 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11567 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11568 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11569 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11570 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11571 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11572 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11573 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11574 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11575 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11576 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11577 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11578 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11579 break;
c0c468d5
TP		 11580 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11581 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11582 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11583 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11584 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11585 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11586 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11587 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11588 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11589 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11590 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11591 case bfd_mach_arm_8:
11592 {
0632eeea
SD		 11593 /* Add bits for extensions that Armv8.5-A recognizes. */
11594 arm_feature_set armv8_5_ext_fset
11595 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
11596 ARM_SET_FEATURES (ARM_ARCH_V8_5A);
11597 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_5_ext_fset);
c0c468d5
TP		 11598 break;
11599 }
11600 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11601 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11602 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 11603 case bfd_mach_arm_8_1M_MAIN:
11604 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
11605 force_thumb = 1;
11606 break;
c0c468d5
TP		 11607 /* If the machine type is unknown allow all architecture types and all
11608 extensions. */
11609 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
0313a2b8
NC		 11610 default:
11611 abort ();
11612 }
1af1dd51 11613#undef ARM_SET_FEATURES
c0c468d5
TP		 11614
11615 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11616 and thus on bfd_mach_arm_XXX value. Therefore for a given
11617 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11618 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 11619}
11620
11621
58efb6c0
NC		 11622/* NOTE: There are no checks in these routines that
11623 the relevant number of data bytes exist. */
baf0cc5e 11624
58efb6c0 11625static int
4a5329c6 11626print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 11627{
c19d1205
ZW		 11628 unsigned char b[4];
11629 long given;
11630 int status;
e821645d 11631 int is_thumb = FALSE;
b0e28b39 11632 int is_data = FALSE;
bd2e2557 11633 int little_code;
e821645d 11634 unsigned int size = 4;
4a5329c6 11635 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 11636 bfd_boolean found = FALSE;
b0e28b39 11637 struct arm_private_data *private_data;
58efb6c0 11638
dd92f639
NC		 11639 if (info->disassembler_options)
11640 {
65b48a81 11641 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 11642
58efb6c0 11643 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 11644 info->disassembler_options = NULL;
11645 }
b34976b6 11646
0313a2b8
NC		 11647 /* PR 10288: Control which instructions will be disassembled. */
11648 if (info->private_data == NULL)
11649 {
b0e28b39 11650 static struct arm_private_data private;
0313a2b8
NC		 11651
11652 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
11653 /* If the user did not use the -m command line switch then default to
11654 disassembling all types of ARM instruction.
43e65147 11655
0313a2b8
NC		 11656 The info->mach value has to be ignored as this will be based on
11657 the default archictecture for the target and/or hints in the notes
11658 section, but it will never be greater than the current largest arm
11659 machine value (iWMMXt2), which is only equivalent to the V5TE
11660 architecture. ARM architectures have advanced beyond the machine
11661 value encoding, and these newer architectures would be ignored if
11662 the machine value was used.
11663
11664 Ie the -m switch is used to restrict which instructions will be
11665 disassembled. If it is necessary to use the -m switch to tell
11666 objdump that an ARM binary is being disassembled, eg because the
11667 input is a raw binary file, but it is also desired to disassemble
11668 all ARM instructions then use "-marm". This will select the
11669 "unknown" arm architecture which is compatible with any ARM
11670 instruction. */
11671 info->mach = bfd_mach_arm_unknown;
11672
11673 /* Compute the architecture bitmask from the machine number.
11674 Note: This assumes that the machine number will not change
11675 during disassembly.... */
b0e28b39 11676 select_arm_features (info->mach, & private.features);
0313a2b8 11677
1fbaefec
PB		 11678 private.last_mapping_sym = -1;
11679 private.last_mapping_addr = 0;
796d6298 11680 private.last_stop_offset = 0;
b0e28b39
DJ		 11681
11682 info->private_data = & private;
0313a2b8 11683 }
b0e28b39
DJ		 11684
11685 private_data = info->private_data;
11686
bd2e2557
SS		 11687 /* Decide if our code is going to be little-endian, despite what the
11688 function argument might say. */
11689 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
11690
b0e28b39
DJ		 11691 /* For ELF, consult the symbol table to determine what kind of code
11692 or data we have. */
8977d4b2 11693 if (info->symtab_size != 0
e821645d
DJ		 11694 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
11695 {
11696 bfd_vma addr;
796d6298 11697 int n;
e821645d 11698 int last_sym = -1;
b0e28b39 11699 enum map_type type = MAP_ARM;
e821645d 11700
796d6298
TC		 11701 found = mapping_symbol_for_insn (pc, info, &type);
11702 last_sym = private_data->last_mapping_sym;
e821645d 11703
1fbaefec
PB		 11704 is_thumb = (private_data->last_type == MAP_THUMB);
11705 is_data = (private_data->last_type == MAP_DATA);
b34976b6 11706
e821645d
DJ		 11707 /* Look a little bit ahead to see if we should print out
11708 two or four bytes of data. If there's a symbol,
11709 mapping or otherwise, after two bytes then don't
11710 print more. */
11711 if (is_data)
11712 {
11713 size = 4 - (pc & 3);
11714 for (n = last_sym + 1; n < info->symtab_size; n++)
11715 {
11716 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 11717 if (addr > pc
11718 && (info->section == NULL
11719 || info->section == info->symtab[n]->section))
e821645d
DJ		 11720 {
11721 if (addr - pc < size)
11722 size = addr - pc;
11723 break;
11724 }
11725 }
11726 /* If the next symbol is after three bytes, we need to
11727 print only part of the data, so that we can use either
11728 .byte or .short. */
11729 if (size == 3)
11730 size = (pc & 1) ? 1 : 2;
11731 }
11732 }
11733
11734 if (info->symbols != NULL)
252b5132 11735 {
5876e06d
NC		 11736 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
11737 {
2f0ca46a 11738 coff_symbol_type * cs;
b34976b6 11739
5876e06d
NC		 11740 cs = coffsymbol (*info->symbols);
11741 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
11742 || cs->native->u.syment.n_sclass == C_THUMBSTAT
11743 || cs->native->u.syment.n_sclass == C_THUMBLABEL
11744 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
11745 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
11746 }
e821645d
DJ		 11747 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
11748 && !found)
5876e06d 11749 {
2087ad84
PB		 11750 /* If no mapping symbol has been found then fall back to the type
11751 of the function symbol. */
e821645d
DJ		 11752 elf_symbol_type * es;
11753 unsigned int type;
2087ad84 11754
e821645d
DJ		 11755 es = *(elf_symbol_type **)(info->symbols);
11756 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 11757
39d911fc
TP		 11758 is_thumb =
11759 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11760 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 11761 }
e49d43ff
TG		 11762 else if (bfd_asymbol_flavour (*info->symbols)
11763 == bfd_target_mach_o_flavour)
11764 {
11765 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
11766
11767 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
11768 }
5876e06d 11769 }
b34976b6 11770
e821645d
DJ		 11771 if (force_thumb)
11772 is_thumb = TRUE;
11773
b8f9ee44
CL		 11774 if (is_data)
11775 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11776 else
11777 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
11778
c19d1205 11779 info->bytes_per_line = 4;
252b5132 11780
1316c8b3
NC		 11781 /* PR 10263: Disassemble data if requested to do so by the user. */
11782 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 11783 {
11784 int i;
11785
1316c8b3 11786 /* Size was already set above. */
e821645d
DJ		 11787 info->bytes_per_chunk = size;
11788 printer = print_insn_data;
11789
fe56b6ce 11790 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 11791 given = 0;
11792 if (little)
11793 for (i = size - 1; i >= 0; i--)
11794 given = b[i] | (given << 8);
11795 else
11796 for (i = 0; i < (int) size; i++)
11797 given = b[i] | (given << 8);
11798 }
11799 else if (!is_thumb)
252b5132 11800 {
c19d1205
ZW		 11801 /* In ARM mode endianness is a straightforward issue: the instruction
11802 is four bytes long and is either ordered 0123 or 3210. */
11803 printer = print_insn_arm;
11804 info->bytes_per_chunk = 4;
4a5329c6 11805 size = 4;
c19d1205 11806
0313a2b8 11807 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 11808 if (little_code)
c19d1205
ZW		 11809 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
11810 else
11811 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
252b5132 11812 }
58efb6c0 11813 else
252b5132 11814 {
c19d1205
ZW		 11815 /* In Thumb mode we have the additional wrinkle of two
11816 instruction lengths. Fortunately, the bits that determine
11817 the length of the current instruction are always to be found
11818 in the first two bytes. */
4a5329c6 11819 printer = print_insn_thumb16;
c19d1205 11820 info->bytes_per_chunk = 2;
4a5329c6
ZW		 11821 size = 2;
11822
fe56b6ce 11823 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 11824 if (little_code)
9a2ff3f5
AM		 11825 given = (b[0]) | (b[1] << 8);
11826 else
11827 given = (b[1]) | (b[0] << 8);
11828
c19d1205 11829 if (!status)
252b5132 11830 {
c19d1205
ZW		 11831 /* These bit patterns signal a four-byte Thumb
11832 instruction. */
11833 if ((given & 0xF800) == 0xF800
11834 || (given & 0xF800) == 0xF000
11835 || (given & 0xF800) == 0xE800)
252b5132 11836 {
0313a2b8 11837 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 11838 if (little_code)
c19d1205 11839 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 11840 else
c19d1205
ZW		 11841 given = (b[1]) | (b[0] << 8) | (given << 16);
11842
11843 printer = print_insn_thumb32;
4a5329c6 11844 size = 4;
252b5132 11845 }
252b5132 11846 }
c22aaad1
PB		 11847
11848 if (ifthen_address != pc)
0313a2b8 11849 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 11850
11851 if (ifthen_state)
11852 {
11853 if ((ifthen_state & 0xf) == 0x8)
11854 ifthen_next_state = 0;
11855 else
11856 ifthen_next_state = (ifthen_state & 0xe0)
11857 | ((ifthen_state & 0xf) << 1);
11858 }
252b5132 11859 }
b34976b6 11860
c19d1205
ZW		 11861 if (status)
11862 {
11863 info->memory_error_func (status, pc, info);
11864 return -1;
11865 }
6a56ec7e
NC		 11866 if (info->flags & INSN_HAS_RELOC)
11867 /* If the instruction has a reloc associated with it, then
11868 the offset field in the instruction will actually be the
11869 addend for the reloc. (We are using REL type relocs).
11870 In such cases, we can ignore the pc when computing
11871 addresses, since the addend is not currently pc-relative. */
11872 pc = 0;
b34976b6 11873
4a5329c6 11874 printer (pc, info, given);
c22aaad1
PB		 11875
11876 if (is_thumb)
11877 {
11878 ifthen_state = ifthen_next_state;
11879 ifthen_address += size;
11880 }
4a5329c6 11881 return size;
252b5132
RH		 11882}
11883
11884int
4a5329c6 11885print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 11886{
bd2e2557
SS		 11887 /* Detect BE8-ness and record it in the disassembler info. */
11888 if (info->flavour == bfd_target_elf_flavour
11889 && info->section != NULL
11890 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
11891 info->endian_code = BFD_ENDIAN_LITTLE;
11892
b34976b6 11893 return print_insn (pc, info, FALSE);
58efb6c0 11894}
01c7f630 11895
58efb6c0 11896int
4a5329c6 11897print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 11898{
b34976b6 11899 return print_insn (pc, info, TRUE);
58efb6c0 11900}
252b5132 11901
471b9d15 11902const disasm_options_and_args_t *
65b48a81
PB		 11903disassembler_options_arm (void)
11904{
471b9d15 11905 static disasm_options_and_args_t *opts_and_args;
65b48a81 11906
471b9d15 11907 if (opts_and_args == NULL)
65b48a81 11908 {
471b9d15 11909 disasm_options_t *opts;
65b48a81 11910 unsigned int i;
471b9d15
MR		 11911
11912 opts_and_args = XNEW (disasm_options_and_args_t);
11913 opts_and_args->args = NULL;
11914
11915 opts = &opts_and_args->options;
65b48a81
PB		 11916 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
11917 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 11918 opts->arg = NULL;
65b48a81
PB		 11919 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11920 {
11921 opts->name[i] = regnames[i].name;
11922 if (regnames[i].description != NULL)
11923 opts->description[i] = _(regnames[i].description);
11924 else
11925 opts->description[i] = NULL;
11926 }
11927 /* The array we return must be NULL terminated. */
11928 opts->name[i] = NULL;
11929 opts->description[i] = NULL;
11930 }
11931
471b9d15 11932 return opts_and_args;
65b48a81
PB		 11933}
11934
58efb6c0 11935void
4a5329c6 11936print_arm_disassembler_options (FILE *stream)
58efb6c0 11937{
65b48a81 11938 unsigned int i, max_len = 0;
58efb6c0
NC		 11939 fprintf (stream, _("\n\
11940The following ARM specific disassembler options are supported for use with\n\
11941the -M switch:\n"));
b34976b6 11942
65b48a81
PB		 11943 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11944 {
11945 unsigned int len = strlen (regnames[i].name);
11946 if (max_len < len)
11947 max_len = len;
11948 }
58efb6c0 11949
65b48a81
PB		 11950 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
11951 fprintf (stream, " %s%*c %s\n",
11952 regnames[i].name,
11953 (int)(max_len - strlen (regnames[i].name)), ' ',
11954 _(regnames[i].description));
252b5132 11955}
GDB Binutils - Deliverables
This page took 1.605989 seconds and 4 git commands to generate.