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[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
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252b5132 1/* Instruction printing code for the ARM
250d07de 2 Copyright (C) 1994-2021 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
1fbaefec
PB		 42/* Cached mapping symbol state. */
43enum map_type
44{
45 MAP_ARM,
46 MAP_THUMB,
47 MAP_DATA
48};
49
b0e28b39
DJ		 50struct arm_private_data
51{
52 /* The features to use when disassembling optional instructions. */
53 arm_feature_set features;
54
1fbaefec
PB		 55 /* Track the last type (although this doesn't seem to be useful) */
56 enum map_type last_type;
57
58 /* Tracking symbol table information */
59 int last_mapping_sym;
796d6298
TC		 60
61 /* The end range of the current range being disassembled. */
62 bfd_vma last_stop_offset;
1fbaefec 63 bfd_vma last_mapping_addr;
b0e28b39
DJ		 64};
65
73cd51e5
AV		 66enum mve_instructions
67{
143275ea
AV		 68 MVE_VPST,
69 MVE_VPT_FP_T1,
70 MVE_VPT_FP_T2,
71 MVE_VPT_VEC_T1,
72 MVE_VPT_VEC_T2,
73 MVE_VPT_VEC_T3,
74 MVE_VPT_VEC_T4,
75 MVE_VPT_VEC_T5,
76 MVE_VPT_VEC_T6,
77 MVE_VCMP_FP_T1,
78 MVE_VCMP_FP_T2,
79 MVE_VCMP_VEC_T1,
80 MVE_VCMP_VEC_T2,
81 MVE_VCMP_VEC_T3,
82 MVE_VCMP_VEC_T4,
83 MVE_VCMP_VEC_T5,
84 MVE_VCMP_VEC_T6,
9743db03
AV		 85 MVE_VDUP,
86 MVE_VEOR,
87 MVE_VFMAS_FP_SCALAR,
88 MVE_VFMA_FP_SCALAR,
89 MVE_VFMA_FP,
90 MVE_VFMS_FP,
91 MVE_VHADD_T1,
92 MVE_VHADD_T2,
93 MVE_VHSUB_T1,
94 MVE_VHSUB_T2,
95 MVE_VRHADD,
04d54ace
AV		 96 MVE_VLD2,
97 MVE_VLD4,
98 MVE_VST2,
99 MVE_VST4,
aef6d006
AV		 100 MVE_VLDRB_T1,
101 MVE_VLDRH_T2,
102 MVE_VLDRB_T5,
103 MVE_VLDRH_T6,
104 MVE_VLDRW_T7,
105 MVE_VSTRB_T1,
106 MVE_VSTRH_T2,
107 MVE_VSTRB_T5,
108 MVE_VSTRH_T6,
109 MVE_VSTRW_T7,
ef1576a1
AV		 110 MVE_VLDRB_GATHER_T1,
111 MVE_VLDRH_GATHER_T2,
112 MVE_VLDRW_GATHER_T3,
113 MVE_VLDRD_GATHER_T4,
114 MVE_VLDRW_GATHER_T5,
115 MVE_VLDRD_GATHER_T6,
116 MVE_VSTRB_SCATTER_T1,
117 MVE_VSTRH_SCATTER_T2,
118 MVE_VSTRW_SCATTER_T3,
119 MVE_VSTRD_SCATTER_T4,
120 MVE_VSTRW_SCATTER_T5,
121 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 122 MVE_VCVT_FP_FIX_VEC,
123 MVE_VCVT_BETWEEN_FP_INT,
124 MVE_VCVT_FP_HALF_FP,
125 MVE_VCVT_FROM_FP_TO_INT,
126 MVE_VRINT_FP,
c507f10b
AV		 127 MVE_VMOV_HFP_TO_GP,
128 MVE_VMOV_GP_TO_VEC_LANE,
129 MVE_VMOV_IMM_TO_VEC,
130 MVE_VMOV_VEC_TO_VEC,
131 MVE_VMOV2_VEC_LANE_TO_GP,
132 MVE_VMOV2_GP_TO_VEC_LANE,
133 MVE_VMOV_VEC_LANE_TO_GP,
134 MVE_VMVN_IMM,
135 MVE_VMVN_REG,
136 MVE_VORR_IMM,
137 MVE_VORR_REG,
138 MVE_VORN,
139 MVE_VBIC_IMM,
140 MVE_VBIC_REG,
141 MVE_VMOVX,
14925797
AV		 142 MVE_VMOVL,
143 MVE_VMOVN,
144 MVE_VMULL_INT,
145 MVE_VMULL_POLY,
146 MVE_VQDMULL_T1,
147 MVE_VQDMULL_T2,
148 MVE_VQMOVN,
149 MVE_VQMOVUN,
d3b63143
AV		 150 MVE_VADDV,
151 MVE_VMLADAV_T1,
152 MVE_VMLADAV_T2,
153 MVE_VMLALDAV,
154 MVE_VMLAS,
155 MVE_VADDLV,
156 MVE_VMLSDAV_T1,
157 MVE_VMLSDAV_T2,
158 MVE_VMLSLDAV,
159 MVE_VRMLALDAVH,
160 MVE_VRMLSLDAVH,
161 MVE_VQDMLADH,
162 MVE_VQRDMLADH,
163 MVE_VQDMLAH,
164 MVE_VQRDMLAH,
165 MVE_VQDMLASH,
166 MVE_VQRDMLASH,
167 MVE_VQDMLSDH,
168 MVE_VQRDMLSDH,
169 MVE_VQDMULH_T1,
170 MVE_VQRDMULH_T2,
171 MVE_VQDMULH_T3,
172 MVE_VQRDMULH_T4,
1c8f2df8
AV		 173 MVE_VDDUP,
174 MVE_VDWDUP,
175 MVE_VIWDUP,
176 MVE_VIDUP,
897b9bbc
AV		 177 MVE_VCADD_FP,
178 MVE_VCADD_VEC,
179 MVE_VHCADD,
180 MVE_VCMLA_FP,
181 MVE_VCMUL_FP,
ed63aa17
AV		 182 MVE_VQRSHL_T1,
183 MVE_VQRSHL_T2,
184 MVE_VQRSHRN,
185 MVE_VQRSHRUN,
186 MVE_VQSHL_T1,
187 MVE_VQSHL_T2,
188 MVE_VQSHLU_T3,
189 MVE_VQSHL_T4,
190 MVE_VQSHRN,
191 MVE_VQSHRUN,
192 MVE_VRSHL_T1,
193 MVE_VRSHL_T2,
194 MVE_VRSHR,
195 MVE_VRSHRN,
196 MVE_VSHL_T1,
197 MVE_VSHL_T2,
198 MVE_VSHL_T3,
199 MVE_VSHLC,
200 MVE_VSHLL_T1,
201 MVE_VSHLL_T2,
202 MVE_VSHR,
203 MVE_VSHRN,
204 MVE_VSLI,
205 MVE_VSRI,
66dcaa5d
AV		 206 MVE_VADC,
207 MVE_VABAV,
208 MVE_VABD_FP,
209 MVE_VABD_VEC,
210 MVE_VABS_FP,
211 MVE_VABS_VEC,
212 MVE_VADD_FP_T1,
213 MVE_VADD_FP_T2,
214 MVE_VADD_VEC_T1,
215 MVE_VADD_VEC_T2,
216 MVE_VSBC,
217 MVE_VSUB_FP_T1,
218 MVE_VSUB_FP_T2,
219 MVE_VSUB_VEC_T1,
220 MVE_VSUB_VEC_T2,
e523f101
AV		 221 MVE_VAND,
222 MVE_VBRSR,
223 MVE_VCLS,
224 MVE_VCLZ,
225 MVE_VCTP,
56858bea
AV		 226 MVE_VMAX,
227 MVE_VMAXA,
228 MVE_VMAXNM_FP,
229 MVE_VMAXNMA_FP,
230 MVE_VMAXNMV_FP,
231 MVE_VMAXNMAV_FP,
232 MVE_VMAXV,
233 MVE_VMAXAV,
234 MVE_VMIN,
235 MVE_VMINA,
236 MVE_VMINNM_FP,
237 MVE_VMINNMA_FP,
238 MVE_VMINNMV_FP,
239 MVE_VMINNMAV_FP,
240 MVE_VMINV,
241 MVE_VMINAV,
242 MVE_VMLA,
f49bb598
AV		 243 MVE_VMUL_FP_T1,
244 MVE_VMUL_FP_T2,
245 MVE_VMUL_VEC_T1,
246 MVE_VMUL_VEC_T2,
247 MVE_VMULH,
248 MVE_VRMULH,
249 MVE_VNEG_FP,
250 MVE_VNEG_VEC,
14b456f2
AV		 251 MVE_VPNOT,
252 MVE_VPSEL,
253 MVE_VQABS,
254 MVE_VQADD_T1,
255 MVE_VQADD_T2,
256 MVE_VQSUB_T1,
257 MVE_VQSUB_T2,
258 MVE_VQNEG,
259 MVE_VREV16,
260 MVE_VREV32,
261 MVE_VREV64,
23d00a41
SD		 262 MVE_LSLL,
263 MVE_LSLLI,
264 MVE_LSRL,
265 MVE_ASRL,
266 MVE_ASRLI,
267 MVE_SQRSHRL,
268 MVE_SQRSHR,
269 MVE_UQRSHL,
270 MVE_UQRSHLL,
271 MVE_UQSHL,
272 MVE_UQSHLL,
273 MVE_URSHRL,
274 MVE_URSHR,
275 MVE_SRSHRL,
276 MVE_SRSHR,
277 MVE_SQSHLL,
278 MVE_SQSHL,
e39c1607
SD		 279 MVE_CINC,
280 MVE_CINV,
281 MVE_CNEG,
282 MVE_CSINC,
283 MVE_CSINV,
284 MVE_CSET,
285 MVE_CSETM,
286 MVE_CSNEG,
287 MVE_CSEL,
73cd51e5
AV		 288 MVE_NONE
289};
290
291enum mve_unpredictable
292{
293 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
294 */
143275ea
AV		 295 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
296 fcB = 1 (vpt). */
297 UNPRED_R13, /* Unpredictable because r13 (sp) or
298 r15 (sp) used. */
9743db03 299 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 300 UNPRED_Q_GT_4, /* Unpredictable because
301 vec reg start > 4 (vld4/st4). */
302 UNPRED_Q_GT_6, /* Unpredictable because
303 vec reg start > 6 (vld2/st2). */
304 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
305 and WB bit = 1. */
ef1576a1
AV		 306 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
307 equal. */
308 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 309 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
310 same. */
c507f10b
AV		 311 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
312 size = 1. */
313 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
314 size = 2. */
73cd51e5
AV		 315 UNPRED_NONE /* No unpredictable behavior. */
316};
317
318enum mve_undefined
319{
ed63aa17 320 UNDEF_SIZE, /* undefined size. */
bf0b396d 321 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 322 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 323 UNDEF_SIZE_3, /* undefined because size == 3. */
324 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 325 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 326 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
327 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
328 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
329 size == 0. */
330 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
331 size == 1. */
332 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 333 UNDEF_VCVT_IMM6, /* imm6 < 32. */
334 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 335 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
336 op1 == (0 or 1). */
337 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
338 op2 == 0 and op1 == (0 or 1). */
339 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
340 in {0xx1, x0x1}. */
d3b63143 341 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 342 UNDEF_NONE /* no undefined behavior. */
343};
344
6b5d3a4d
ZW		 345struct opcode32
346{
823d2571
TG		 347 arm_feature_set arch; /* Architecture defining this insn. */
348 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 349 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 350 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 351};
352
4934a27c
MM		 353struct cdeopcode32
354{
355 arm_feature_set arch; /* Architecture defining this insn. */
356 uint8_t coproc_shift; /* coproc is this far into op. */
357 uint16_t coproc_mask; /* Length of coproc field in op. */
358 unsigned long value; /* If arch is 0 then value is a sentinel. */
359 unsigned long mask; /* Recognise insn if (op & mask) == value. */
360 const char * assembler; /* How to disassemble this insn. */
361};
362
73cd51e5
AV		 363/* MVE opcodes. */
364
365struct mopcode32
366{
367 arm_feature_set arch; /* Architecture defining this insn. */
368 enum mve_instructions mve_op; /* Specific mve instruction for faster
369 decoding. */
370 unsigned long value; /* If arch is 0 then value is a sentinel. */
371 unsigned long mask; /* Recognise insn if (op & mask) == value. */
372 const char * assembler; /* How to disassemble this insn. */
373};
374
6b0dd094
AV		 375enum isa {
376 ANY,
377 T32,
378 ARM
379};
380
381
382/* Shared (between Arm and Thumb mode) opcode. */
383struct sopcode32
384{
385 enum isa isa; /* Execution mode instruction availability. */
386 arm_feature_set arch; /* Architecture defining this insn. */
387 unsigned long value; /* If arch is 0 then value is a sentinel. */
388 unsigned long mask; /* Recognise insn if (op & mask) == value. */
389 const char * assembler; /* How to disassemble this insn. */
390};
391
6b5d3a4d
ZW		 392struct opcode16
393{
823d2571 394 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 395 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 396 const char *assembler; /* How to disassemble this insn. */
397};
b7693d02 398
8f06b2d8 399/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 400
2fbad815 401 %% %
4a5329c6 402
c22aaad1 403 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 404 %b print condition code allowing cp_num == 9
37b37b2d 405 %q print shifter argument
e2efe87d
MGD		 406 %u print condition code (unconditional in ARM mode,
407 UNPREDICTABLE if not AL in Thumb)
4a5329c6 408 %A print address for ldc/stc/ldf/stf instruction
16980d0b 409 %B print vstm/vldm register list
efd6b359 410 %C print vscclrm register list
4a5329c6 411 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 412 %J print register for VLDR instruction
413 %K print address for VLDR instruction
4a5329c6
ZW		 414 %F print the COUNT field of a LFM/SFM instruction.
415 %P print floating point precision in arithmetic insn
416 %Q print floating point precision in ldf/stf insn
417 %R print floating point rounding mode
418
33399f07 419 %<bitfield>c print as a condition code (for vsel)
4a5329c6 420 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 421 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
422 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 423 %<bitfield>d print the bitfield in decimal
16980d0b 424 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 425 %<bitfield>x print the bitfield in hex
426 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 427 %<bitfield>f print a floating point constant if >7 else a
428 floating point register
4a5329c6
ZW		 429 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
430 %<bitfield>g print as an iWMMXt 64-bit register
431 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 432 %<bitfield>D print as a NEON D register
433 %<bitfield>Q print as a NEON Q register
c28eeff2 434 %<bitfield>V print as a NEON D or Q register
6f1c2142 435 %<bitfield>E print a quarter-float immediate value
4a5329c6 436
16980d0b 437 %y<code> print a single precision VFP reg.
2fbad815 438 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 439 %z<code> print a double precision VFP reg
2fbad815 440 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 441
16980d0b
JB		 442 %<bitfield>'c print specified char iff bitfield is all ones
443 %<bitfield>`c print specified char iff bitfield is all zeroes
444 %<bitfield>?ab... select from array of values in big endian order
43e65147 445
2fbad815 446 %L print as an iWMMXt N/M width field.
4a5329c6 447 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 448 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 449 versions.
450 %i print 5-bit immediate in bits 8,3..0
451 (print "32" when 0)
fe56b6ce 452 %r print register offset address for wldt/wstr instruction. */
2fbad815 453
21d799b5 454enum opcode_sentinel_enum
05413229
NC		 455{
456 SENTINEL_IWMMXT_START = 1,
457 SENTINEL_IWMMXT_END,
458 SENTINEL_GENERIC_START
459} opcode_sentinels;
460
aefd8a40 461#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 462#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
463#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 464#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 465
8f06b2d8 466/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 467
4934a27c
MM		 468/* print_insn_cde recognizes the following format control codes:
469
470 %% %
471
472 %a print 'a' iff bit 28 is 1
473 %p print bits 8-10 as coprocessor
474 %<bitfield>d print as decimal
475 %<bitfield>r print as an ARM register
476 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
477 %<bitfield>T print as an ARM register + 1
478 %<bitfield>R as %r but r13 is UNPREDICTABLE
479 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
480 %j print immediate taken from bits (16..21,7,0..5)
481 %k print immediate taken from bits (20..21,7,0..5).
482 %l print immediate taken from bits (20..22,7,4..5). */
483
484/* At the moment there is only one valid position for the coprocessor number,
485 and hence that's encoded in the macro below. */
486#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
487 { ARCH, 8, 7, VALUE, MASK, ASM }
488static const struct cdeopcode32 cde_opcodes[] =
489{
490 /* Custom Datapath Extension instructions. */
491 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
492 0xee000000, 0xefc00840,
493 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
494 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
495 0xee000040, 0xefc00840,
496 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
497
498 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
499 0xee400000, 0xefc00840,
500 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
501 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
502 0xee400040, 0xefc00840,
503 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
504
505 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
506 0xee800000, 0xef800840,
507 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
508 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
509 0xee800040, 0xef800840,
510 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
511
5aae9ae9
MM		 512 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
513 0xec200000, 0xeeb00840,
514 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
515 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
516 0xec200040, 0xeeb00840,
517 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
518
519 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
520 0xec300000, 0xeeb00840,
521 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
522 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
523 0xec300040, 0xeeb00840,
524 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
525
526 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
527 0xec800000, 0xee800840,
528 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
529 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
530 0xec800040, 0xee800840,
531 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
532
4934a27c
MM		 533 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
534
535};
536
6b0dd094 537static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 538{
2fbad815 539 /* XScale instructions. */
6b0dd094 540 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 541 0x0e200010, 0x0fff0ff0,
542 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 543 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 544 0x0e280010, 0x0fff0ff0,
545 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 546 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 547 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 549 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 550 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 551 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 552
2fbad815 553 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 554 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 556 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 557 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 558 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 559 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 560 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 561 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 562 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 563 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 564 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 565 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 566 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 567 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 568 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 569 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 570 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 571 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 572 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 573 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 574 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 575 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 576 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 577 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 578 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 579 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 580 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 581 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 582 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 583 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 584 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 585 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 586 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 587 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 588 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 589 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 590 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 591 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 592 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 593 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 594 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 595 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 596 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 597 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 598 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 599 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 600 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 601 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 602 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 603 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 604 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 605 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 606 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 607 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 608 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 609 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 610 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 611 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 612 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 613 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 614 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 615 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 616 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 617 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 618 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 619 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 620 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 621 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 622 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 623 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 624 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 625 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 626 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 627 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 628 0x0e800120, 0x0f800ff0,
629 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 633 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 634 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 635 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 636 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 637 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 638 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 639 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 640 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 641 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 642 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 643 0x0e8000a0, 0x0f800ff0,
644 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 648 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 649 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 650 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 651 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 652 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 653 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 654 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 655 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 656 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 657 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 658 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 659 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 660 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 661 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 662 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 663 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 664 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 665 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 666 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 667 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 668 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 669 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 670 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 671 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 672 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 673 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 674 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 675 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 676 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 677 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 678 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 679 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 680 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 681 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 682 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 683 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 684 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 685 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 686 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 687 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 688 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 689 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 690 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 691 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 692 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 693 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 694 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 695 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 696 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 697 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 698 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 699 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 700 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 701 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 702 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 703 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 704 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 705 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 706 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 707 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 708 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 709
fe56b6ce 710 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 711 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 712 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 713 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 714 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 715 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 716 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 717 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 718 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 719 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 720 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 721 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 722 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 723 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 724 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 725 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 726 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 727 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 728 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 729 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 730 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 731 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 732 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 733 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 734 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 735 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 736 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 737 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 738 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 739 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 740 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 741 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 742 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 743 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 744 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 745 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 746 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 747 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 748 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 749 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 750 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 751 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 752 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 753 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 754 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 755 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 756 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 757 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 758 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 759 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 760 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 761 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 762 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 763 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 764 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 765 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 766 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 767 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 768 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 769 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 770 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 771 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 772 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 773 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 774 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 775 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 776 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 777 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 778 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 779 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 780 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 781 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 782 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 783 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 784 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 785 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 786 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 787 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 788 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 789 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 790 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 791 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 792 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 793 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 794 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 795 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 796 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 797
efd6b359
AV		 798 /* Armv8.1-M Mainline instructions. */
799 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
800 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
801 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
802 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
803
16a1fa25 804 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 805 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 806 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 807 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 808 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
809
fe56b6ce 810 /* Register load/store. */
6b0dd094 811 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 812 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 813 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 814 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 815 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 816 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 817 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 818 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 819 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 820 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 821 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 822 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 823 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 824 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 825 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 826 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 827 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 828 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 829 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 830 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 831 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 832 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 833 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 834 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 835 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 836 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 837 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 838 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 839 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 840 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 841 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 842 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 843 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
844 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
845 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
846 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 847
6b0dd094 848 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 849 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 850 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 851 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 852 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 853 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 854 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 855 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 856
fe56b6ce 857 /* Data transfer between ARM and NEON registers. */
6b0dd094 858 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 859 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 860 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 861 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 862 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 863 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 864 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 865 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 866 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 867 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 868 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 869 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 870 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 871 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 872 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 873 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 874 /* Half-precision conversion instructions. */
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 876 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 878 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 879 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 880 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 881 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 882 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 883
fe56b6ce 884 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 885 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 886 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
2da2eaf4 887 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 888 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 889 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
890 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 891 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 892 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 893 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 894 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 895 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 896 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 897 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 898 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 899 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 900 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 901 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 902 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
2da2eaf4 903 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 904 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
2da2eaf4 905 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 906 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
907 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
908 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
909 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
910 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 911 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 912 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 913 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 914 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
2da2eaf4 915 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 916 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 917 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
918 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 919 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 920 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 921 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 922 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 923 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 924 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 925 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 926 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 927 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 928 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 929 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 930 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
2da2eaf4 931 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 932 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
2da2eaf4 933 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 934 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
935 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
936 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
937 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
938 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 939 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 940 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 941 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 942 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 943 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 944 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 945 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 946 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 947 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 948 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 949 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 950 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 951 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 952 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 953 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 954 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 955 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 956 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 957 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 958 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 959 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 960 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 961 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 962 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 963 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 964 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 965 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 966 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 967 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 968 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 969 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 970 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 971 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 972 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 973 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 974 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 975 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 976 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 977 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 978 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 979 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 980 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 981 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 982 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 983 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 984 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 985 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 986 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 987 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 988 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 989 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 990 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 991 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 992 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 993 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 994 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 995 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 996 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 997 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 998 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 999 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 1000 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 1001 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1002 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1003 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1004 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1005 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1006 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1007 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1008 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1009 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1010 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1011 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1012 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1013 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1014 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1015 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1016 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1017 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1018 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1019 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1020 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1021 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1022 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1023 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1024 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1025 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1026 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1027 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1028 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1029 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1030 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1031 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1032 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1033 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1034 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1035 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1036 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1037 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1038 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1039 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1040 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1041 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1042 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1043
1044 /* Cirrus coprocessor instructions. */
6b0dd094 1045 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1046 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1047 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1048 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1049 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1050 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1051 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1052 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1053 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1054 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1055 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1056 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1057 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1058 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1059 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1060 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1061 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1062 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1063 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1064 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1065 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1066 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1067 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1068 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1069 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1070 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1071 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1072 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1073 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1074 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1075 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1076 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1077 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1078 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1079 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1080 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1081 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1082 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1083 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1084 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1085 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1086 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1087 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1088 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1089 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1090 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1091 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1092 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1093 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1094 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1095 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1096 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1097 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1098 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1099 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1100 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1101 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1102 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1103 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1104 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1105 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1106 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1107 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1108 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1109 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1110 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1111 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1112 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1113 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1114 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1115 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1116 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1117 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1118 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1119 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1120 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1121 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1122 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1123 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1124 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1125 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1126 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1127 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1128 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1129 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1130 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1131 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1132 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1133 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1134 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1135 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1136 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1137 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1138 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1139 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1140 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1141 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1142 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1143 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1144 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1145 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1146 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1147 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1148 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1149 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1150 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1151 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1152 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1153 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1154 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1155 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1156 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1157 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1158 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1159 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1160 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1161 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1162 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1163 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1164 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1165 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1166 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1167 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1168 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1169 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1170 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1171 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1172 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1173 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1174 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1175 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1176 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1177 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1178 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1179 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1180 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1181 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1182 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1183 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1184 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1185 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1186 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1187 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1188 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1189 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1190 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1191 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1192 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1193 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1194 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1195 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1196 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1197 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1198 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1199 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1200 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1201 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1202 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1203 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1204 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1205 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1206 0x0e000600, 0x0ff00f10,
1207 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1209 0x0e100600, 0x0ff00f10,
1210 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1211 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1212 0x0e200600, 0x0ff00f10,
1213 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1214 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1215 0x0e300600, 0x0ff00f10,
1216 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1217
62f3b8c8 1218 /* VFP Fused multiply add instructions. */
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1220 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1221 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1222 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1223 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1224 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1225 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1226 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1227 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1228 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1229 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1230 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1231 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1232 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1233 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1234 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1235
33399f07 1236 /* FP v5. */
6b0dd094 1237 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1238 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1239 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1240 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1241 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1242 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1243 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1244 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1245 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1246 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1247 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1248 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1249 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1250 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1251 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1252 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1253 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1254 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1255 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1256 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1257 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1258 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1259 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1260 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1261
6b0dd094 1262 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1263 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1264 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1265 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1266 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1267 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1268 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1269 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1270 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1271 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1272 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1273 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1274 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1275 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1276 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1277 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1278 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1279 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1280 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1281 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1282 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1283 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1284
aab2c27d
MM		 1285 /* BFloat16 instructions. */
1286 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1287 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1288
c604a79a 1289 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1290 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1291 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1292 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1293 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1294
dec41383 1295 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1296 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1297 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1298 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1299 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1300 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1301 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1302 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1303 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1304 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1305 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1306 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1307 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1308 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1309 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1310 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1311 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1312
b0c11777
RL		 1313 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1314 cp_num: bit <11:8> == 0b1001.
1315 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1316 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1317 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1318 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1319 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1320 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1321 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1322 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1323 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1324 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1325 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1326 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1327 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1328 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1329 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1330 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1331 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1332 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1333 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1334 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1335 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1336 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1337 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1338 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1339 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1340 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1341 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1342 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1343 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1344 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1345 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1346 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1347 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1348 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1349 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1350 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1351 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1352 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1353 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1354 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1355 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1356 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1357 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1358 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1359 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1360 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1361 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1362 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1363 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1364 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1365 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1366 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1367 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1368 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1369 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1370 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1371 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1372 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1373 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1374 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1375 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1376 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1377 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1378 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1379 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1380 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1381 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1382 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1383 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1384 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1385 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1386
49e8a725 1387 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1388 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1389 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1390
6b0dd094 1391 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1392};
1393
33593eaf
MM		 1394/* Generic coprocessor instructions. These are only matched if a more specific
1395 SIMD or co-processor instruction does not match first. */
1396
1397static const struct sopcode32 generic_coprocessor_opcodes[] =
1398{
1399 /* Generic coprocessor instructions. */
1400 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1401 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1402 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1403 0x0c500000, 0x0ff00000,
1404 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1406 0x0e000000, 0x0f000010,
1407 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1408 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1409 0x0e10f010, 0x0f10f010,
1410 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1411 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1412 0x0e100010, 0x0f100010,
1413 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1414 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1415 0x0e000010, 0x0f100010,
1416 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1417 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1418 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1421
1422 /* V6 coprocessor instructions. */
1423 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1424 0xfc500000, 0xfff00000,
1425 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1426 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1427 0xfc400000, 0xfff00000,
1428 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1429
1430 /* V5 coprocessor instructions. */
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1432 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1433 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1434 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1435 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1436 0xfe000000, 0xff000010,
1437 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfe000010, 0xff100010,
1440 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1441 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1442 0xfe100010, 0xff100010,
1443 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1444
1445 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1446};
1447
16980d0b
JB		 1448/* Neon opcode table: This does not encode the top byte -- that is
1449 checked by the print_insn_neon routine, as it depends on whether we are
1450 doing thumb32 or arm32 disassembly. */
1451
1452/* print_insn_neon recognizes the following format control codes:
1453
1454 %% %
1455
c22aaad1 1456 %c print condition code
e2efe87d
MGD		 1457 %u print condition code (unconditional in ARM mode,
1458 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1459 %A print v{st,ld}[1234] operands
1460 %B print v{st,ld}[1234] any one operands
1461 %C print v{st,ld}[1234] single->all operands
1462 %D print scalar
1463 %E print vmov, vmvn, vorr, vbic encoded constant
1464 %F print vtbl,vtbx register list
1465
1466 %<bitfield>r print as an ARM register
1467 %<bitfield>d print the bitfield in decimal
1468 %<bitfield>e print the 2^N - bitfield in decimal
1469 %<bitfield>D print as a NEON D register
1470 %<bitfield>Q print as a NEON Q register
1471 %<bitfield>R print as a NEON D or Q register
1472 %<bitfield>Sn print byte scaled width limited by n
1473 %<bitfield>Tn print short scaled width limited by n
1474 %<bitfield>Un print long scaled width limited by n
43e65147 1475
16980d0b
JB		 1476 %<bitfield>'c print specified char iff bitfield is all ones
1477 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1478 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1479
1480static const struct opcode32 neon_opcodes[] =
1481{
fe56b6ce 1482 /* Extract. */
823d2571
TG		 1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484 0xf2b00840, 0xffb00850,
1485 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1487 0xf2b00000, 0xffb00810,
1488 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1489
9743db03
AV		 1490 /* Data transfer between ARM and NEON registers. */
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1492 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1494 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1496 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1498 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1500 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1502 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1503
fe56b6ce 1504 /* Move data element to all lanes. */
823d2571
TG		 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1511
fe56b6ce 1512 /* Table lookup. */
823d2571
TG		 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1517
8e79c3df 1518 /* Half-precision conversions. */
823d2571
TG		 1519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1520 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1522 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1523
1524 /* NEON fused multiply add instructions. */
823d2571 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1526 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1527 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1528 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1530 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1531 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1532 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1533
aab2c27d
MM		 1534 /* BFloat16 instructions. */
1535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1536 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1538 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1540 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1542 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1544 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1546 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1547
616ce08e
MM		 1548 /* Matrix Multiply instructions. */
1549 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1550 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1552 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1554 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1556 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1558 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1560 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1561
fe56b6ce 1562 /* Two registers, miscellaneous. */
823d2571
TG		 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1564 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1566 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1567 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1568 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1570 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1571 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1572 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1573 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1574 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1576 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1577 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1578 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1579 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1580 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1581 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1582 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1583 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1584 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1591 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1592 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1600 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606 0xf3b20300, 0xffb30fd0,
1607 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1611 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1613 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1614 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1615 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1616 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1617 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1619 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1621 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1623 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1624 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1625 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1627 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1629 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1631 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1635 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1636 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1637 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1639 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1641 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1642 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1643 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1645 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1647 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1649 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1651 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1653 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1655 0xf3bb0600, 0xffbf0e10,
823d2571 1656 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1658 0xf3b70600, 0xffbf0e10,
1659 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1660
fe56b6ce 1661 /* Three registers of the same length. */
823d2571
TG		 1662 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1663 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1664 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1665 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1666 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1667 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1668 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1669 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1670 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1671 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1672 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1673 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1674 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1675 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1676 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1677 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1679 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1681 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1683 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1685 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1687 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1689 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1691 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1693 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1695 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1697 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1699 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1701 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1703 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1705 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1706 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1707 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1709 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1711 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1713 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1715 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1717 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1718 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1719 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1721 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1723 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1725 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1727 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1729 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1731 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1733 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1735 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1737 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1739 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1741 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1743 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1745 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1747 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1749 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1751 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1753 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1754 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1755 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1757 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1758 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1759 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1761 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1763 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1765 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1766 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1767 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1769 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1771 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1773 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1775 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1777 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1779 0xf2000b00, 0xff800f10,
1780 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000b10, 0xff800f10,
1783 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1785 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1788 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1789 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1791 0xf3000b00, 0xff800f10,
1792 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf2000000, 0xfe800f10,
1795 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1797 0xf2000010, 0xfe800f10,
1798 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1800 0xf2000100, 0xfe800f10,
1801 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1803 0xf2000200, 0xfe800f10,
1804 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1806 0xf2000210, 0xfe800f10,
1807 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1809 0xf2000300, 0xfe800f10,
1810 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1811 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1812 0xf2000310, 0xfe800f10,
1813 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1815 0xf2000400, 0xfe800f10,
1816 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1817 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1818 0xf2000410, 0xfe800f10,
1819 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1821 0xf2000500, 0xfe800f10,
1822 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1823 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1824 0xf2000510, 0xfe800f10,
1825 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1827 0xf2000600, 0xfe800f10,
1828 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1829 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1830 0xf2000610, 0xfe800f10,
1831 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1833 0xf2000700, 0xfe800f10,
1834 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1835 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1836 0xf2000710, 0xfe800f10,
1837 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1839 0xf2000910, 0xfe800f10,
1840 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1841 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1842 0xf2000a00, 0xfe800f10,
1843 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1845 0xf2000a10, 0xfe800f10,
1846 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1847 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1848 0xf3000b10, 0xff800f10,
1849 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1851 0xf3000c10, 0xff800f10,
1852 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1853
fe56b6ce 1854 /* One register and an immediate value. */
823d2571
TG		 1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1856 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1858 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1860 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1862 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1864 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1866 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1868 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1870 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1872 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1874 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1876 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1878 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1880 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1881
fe56b6ce 1882 /* Two registers and a shift amount. */
823d2571
TG		 1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1884 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1886 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1887 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1888 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1889 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1890 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1891 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1892 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1893 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1894 0xf2880950, 0xfeb80fd0,
1895 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1901 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1903 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1905 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1907 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1909 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1911 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1913 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1915 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1917 0xf2900950, 0xfeb00fd0,
1918 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1923 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1924 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1925 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1926 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1928 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1929 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1930 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1931 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1932 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1934 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1935 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1936 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1937 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1938 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1940 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1941 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1942 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1943 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1944 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1945 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1946 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1948 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1950 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1951 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1952 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1954 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1956 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1958 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1959 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1960 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1962 0xf2a00950, 0xfea00fd0,
1963 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1968 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1969 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1970 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1971 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1972 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1973 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1974 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1975 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1976 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1977 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1978 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1979 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1980 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1981 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1982 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1983 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1984 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1985 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1986 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1987 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1988 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1989 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1990 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1991 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1992 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1993 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1994 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1995 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1996 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1997 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1998 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1999 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2001 0xf2a00e10, 0xfea00e90,
2002 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 2003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2004 0xf2a00c10, 0xfea00e90,
2005 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 2006
fe56b6ce 2007 /* Three registers of different lengths. */
823d2571
TG		 2008 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2009 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2010 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2011 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2013 0xf2800400, 0xff800f50,
2014 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800600, 0xff800f50,
2017 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2018 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2019 0xf2800900, 0xff800f50,
2020 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2022 0xf2800b00, 0xff800f50,
2023 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2024 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2025 0xf2800d00, 0xff800f50,
2026 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2028 0xf3800400, 0xff800f50,
2029 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2030 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2031 0xf3800600, 0xff800f50,
2032 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2034 0xf2800000, 0xfe800f50,
2035 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2036 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2037 0xf2800100, 0xfe800f50,
2038 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2040 0xf2800200, 0xfe800f50,
2041 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2042 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2043 0xf2800300, 0xfe800f50,
2044 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2046 0xf2800500, 0xfe800f50,
2047 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2048 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2049 0xf2800700, 0xfe800f50,
2050 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2052 0xf2800800, 0xfe800f50,
2053 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2054 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2055 0xf2800a00, 0xfe800f50,
2056 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2058 0xf2800c00, 0xfe800f50,
2059 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2060
fe56b6ce 2061 /* Two registers and a scalar. */
823d2571
TG		 2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2065 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2066 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2067 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2068 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2069 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2071 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2073 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2074 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2075 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2077 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2078 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2079 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2081 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2082 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2083 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2084 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2085 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2086 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2087 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2088 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2089 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2090 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2091 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2093 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2094 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2095 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2097 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2098 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2099 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2100 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2101 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2103 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2104 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2105 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2106 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2107 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2108 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2109 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2110 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2111 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2112 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2113 0xf2800240, 0xfe800f50,
2114 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf2800640, 0xfe800f50,
2117 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2118 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2119 0xf2800a40, 0xfe800f50,
2120 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2121 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2122 0xf2800e40, 0xff800f50,
2123 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2125 0xf2800f40, 0xff800f50,
2126 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2128 0xf3800e40, 0xff800f50,
2129 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2131 0xf3800f40, 0xff800f50,
2132 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2133 },
16980d0b 2134
fe56b6ce 2135 /* Element and structure load/store. */
823d2571
TG		 2136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2137 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2139 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2141 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2143 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2145 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2146 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2147 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2148 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2149 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2151 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2152 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2153 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2155 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2156 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2157 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2159 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2161 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2163 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2165 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2167 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2169 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2171 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2173 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2174
2175 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2176};
2177
73cd51e5
AV		 2178/* mve opcode table. */
2179
2180/* print_insn_mve recognizes the following format control codes:
2181
2182 %% %
2183
ef1576a1
AV		 2184 %a print '+' or '-' or imm offset in vldr[bhwd] and
2185 vstr[bhwd]
9743db03 2186 %c print condition code
aef6d006
AV		 2187 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2188 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2189 %i print MVE predicate(s) for vpt and vpst
23d00a41 2190 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2191 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2192 %m print rounding mode for vcvt and vrint
143275ea 2193 %n print vector comparison code for predicated instruction
bf0b396d 2194 %s print size for various vcvt instructions
143275ea
AV		 2195 %v print vector predicate for instruction in predicated
2196 block
ef1576a1 2197 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2198 %w print writeback mode for MVE v{st,ld}[24]
2199 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2200 %E print vmov, vmvn, vorr, vbic encoded constant
2201 %N print generic index for vmov
14925797 2202 %T print bottom ('b') or top ('t') of source register
d3b63143 2203 %X print exchange field in vmla* instructions
04d54ace 2204
9743db03 2205 %<bitfield>r print as an ARM register
04d54ace 2206 %<bitfield>d print the bitfield in decimal
d3b63143 2207 %<bitfield>A print accumulate or not
e39c1607
SD		 2208 %<bitfield>c print bitfield as a condition code
2209 %<bitfield>C print bitfield as an inverted condition code
143275ea 2210 %<bitfield>Q print as a MVE Q register
c507f10b 2211 %<bitfield>F print as a MVE S register
143275ea
AV		 2212 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2213 UNPREDICTABLE
23d00a41
SD		 2214
2215 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2216 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2217 %<bitfield>I print carry flag or not
ef1576a1 2218 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2219 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2220 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2221 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2222 %<bitfield>o print rotate value for vcmul
1c8f2df8 2223 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2224 %<bitfield>x print the bitfield in hex.
1c8f2df8 2225 */
73cd51e5
AV		 2226
2227static const struct mopcode32 mve_opcodes[] =
2228{
143275ea
AV		 2229 /* MVE. */
2230
2da2eaf4 2231 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2232 MVE_VPST,
2233 0xfe310f4d, 0xffbf1fff,
2234 "vpst%i"
2235 },
2236
2237 /* Floating point VPT T1. */
2da2eaf4 2238 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2239 MVE_VPT_FP_T1,
2240 0xee310f00, 0xefb10f50,
2241 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2242 /* Floating point VPT T2. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T2,
2245 0xee310f40, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2247
2248 /* Vector VPT T1. */
2da2eaf4 2249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2250 MVE_VPT_VEC_T1,
2251 0xfe010f00, 0xff811f51,
2252 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2253 /* Vector VPT T2. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T2,
2256 0xfe010f01, 0xff811f51,
2257 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T3. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T3,
2261 0xfe011f00, 0xff811f50,
2262 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T4. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T4,
2266 0xfe010f40, 0xff811f70,
2267 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2268 /* Vector VPT T5. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T5,
2271 0xfe010f60, 0xff811f70,
2272 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T6. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T6,
2276 0xfe011f40, 0xff811f50,
2277 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2278
c507f10b 2279 /* Vector VBIC immediate. */
2da2eaf4 2280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2281 MVE_VBIC_IMM,
2282 0xef800070, 0xefb81070,
2283 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2284
2285 /* Vector VBIC register. */
2da2eaf4 2286 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2287 MVE_VBIC_REG,
2288 0xef100150, 0xffb11f51,
2289 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2290
66dcaa5d 2291 /* Vector VABAV. */
2da2eaf4 2292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2293 MVE_VABAV,
2294 0xee800f01, 0xefc10f51,
2295 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2296
2297 /* Vector VABD floating point. */
2da2eaf4 2298 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2299 MVE_VABD_FP,
2300 0xff200d40, 0xffa11f51,
2301 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2302
2303 /* Vector VABD. */
2da2eaf4 2304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2305 MVE_VABD_VEC,
2306 0xef000740, 0xef811f51,
2307 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2308
2309 /* Vector VABS floating point. */
2da2eaf4 2310 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2311 MVE_VABS_FP,
2312 0xFFB10740, 0xFFB31FD1,
2313 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2314 /* Vector VABS. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2316 MVE_VABS_VEC,
2317 0xffb10340, 0xffb31fd1,
2318 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2319
2320 /* Vector VADD floating point T1. */
2da2eaf4 2321 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2322 MVE_VADD_FP_T1,
2323 0xef000d40, 0xffa11f51,
2324 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2325 /* Vector VADD floating point T2. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T2,
2328 0xee300f40, 0xefb11f70,
2329 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2330 /* Vector VADD T1. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2332 MVE_VADD_VEC_T1,
2333 0xef000840, 0xff811f51,
2334 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2335 /* Vector VADD T2. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T2,
2338 0xee010f40, 0xff811f70,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2340
d3b63143 2341 /* Vector VADDLV. */
2da2eaf4 2342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2343 MVE_VADDLV,
2344 0xee890f00, 0xef8f1fd1,
2345 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2346
2347 /* Vector VADDV. */
2da2eaf4 2348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2349 MVE_VADDV,
2350 0xeef10f00, 0xeff31fd1,
2351 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2352
66dcaa5d 2353 /* Vector VADC. */
2da2eaf4 2354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2355 MVE_VADC,
2356 0xee300f00, 0xffb10f51,
2357 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2358
e523f101 2359 /* Vector VAND. */
2da2eaf4 2360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2361 MVE_VAND,
2362 0xef000150, 0xffb11f51,
2363 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2364
2365 /* Vector VBRSR register. */
2da2eaf4 2366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2367 MVE_VBRSR,
2368 0xfe011e60, 0xff811f70,
2369 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2370
897b9bbc 2371 /* Vector VCADD floating point. */
2da2eaf4 2372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2373 MVE_VCADD_FP,
2374 0xfc800840, 0xfea11f51,
2375 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2376
2377 /* Vector VCADD. */
2da2eaf4 2378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2379 MVE_VCADD_VEC,
2380 0xfe000f00, 0xff810f51,
2381 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2382
e523f101 2383 /* Vector VCLS. */
2da2eaf4 2384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2385 MVE_VCLS,
2386 0xffb00440, 0xffb31fd1,
2387 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2388
2389 /* Vector VCLZ. */
2da2eaf4 2390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2391 MVE_VCLZ,
2392 0xffb004c0, 0xffb31fd1,
2393 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2394
897b9bbc 2395 /* Vector VCMLA. */
2da2eaf4 2396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2397 MVE_VCMLA_FP,
2398 0xfc200840, 0xfe211f51,
2399 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2400
143275ea 2401 /* Vector VCMP floating point T1. */
2da2eaf4 2402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2403 MVE_VCMP_FP_T1,
2404 0xee310f00, 0xeff1ef50,
2405 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2406
2407 /* Vector VCMP floating point T2. */
2da2eaf4 2408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2409 MVE_VCMP_FP_T2,
2410 0xee310f40, 0xeff1ef50,
2411 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2412
2413 /* Vector VCMP T1. */
2da2eaf4 2414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2415 MVE_VCMP_VEC_T1,
2416 0xfe010f00, 0xffc1ff51,
2417 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2418 /* Vector VCMP T2. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T2,
2421 0xfe010f01, 0xffc1ff51,
2422 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T3. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T3,
2426 0xfe011f00, 0xffc1ff50,
2427 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T4. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T4,
2431 0xfe010f40, 0xffc1ff70,
2432 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2433 /* Vector VCMP T5. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T5,
2436 0xfe010f60, 0xffc1ff70,
2437 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T6. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T6,
2441 0xfe011f40, 0xffc1ff50,
2442 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2443
9743db03 2444 /* Vector VDUP. */
2da2eaf4 2445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2446 MVE_VDUP,
2447 0xeea00b10, 0xffb10f5f,
2448 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2449
2450 /* Vector VEOR. */
2da2eaf4 2451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2452 MVE_VEOR,
2453 0xff000150, 0xffd11f51,
2454 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2455
2456 /* Vector VFMA, vector * scalar. */
2da2eaf4 2457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2458 MVE_VFMA_FP_SCALAR,
2459 0xee310e40, 0xefb11f70,
2460 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2461
2462 /* Vector VFMA floating point. */
2da2eaf4 2463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2464 MVE_VFMA_FP,
2465 0xef000c50, 0xffa11f51,
2466 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2467
2468 /* Vector VFMS floating point. */
2da2eaf4 2469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2470 MVE_VFMS_FP,
2471 0xef200c50, 0xffa11f51,
2472 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473
2474 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2476 MVE_VFMAS_FP_SCALAR,
2477 0xee311e40, 0xefb11f70,
2478 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2479
2480 /* Vector VHADD T1. */
2da2eaf4 2481 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2482 MVE_VHADD_T1,
2483 0xef000040, 0xef811f51,
2484 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2485
2486 /* Vector VHADD T2. */
2da2eaf4 2487 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2488 MVE_VHADD_T2,
2489 0xee000f40, 0xef811f70,
2490 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2491
2492 /* Vector VHSUB T1. */
2da2eaf4 2493 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2494 MVE_VHSUB_T1,
2495 0xef000240, 0xef811f51,
2496 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2497
2498 /* Vector VHSUB T2. */
2da2eaf4 2499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2500 MVE_VHSUB_T2,
2501 0xee001f40, 0xef811f70,
2502 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2503
897b9bbc 2504 /* Vector VCMUL. */
2da2eaf4 2505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2506 MVE_VCMUL_FP,
2507 0xee300e00, 0xefb10f50,
2508 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2509
e523f101 2510 /* Vector VCTP. */
2da2eaf4 2511 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2512 MVE_VCTP,
2513 0xf000e801, 0xffc0ffff,
2514 "vctp%v.%20-21s\t%16-19r"},
2515
9743db03 2516 /* Vector VDUP. */
2da2eaf4 2517 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2518 MVE_VDUP,
2519 0xeea00b10, 0xffb10f5f,
2520 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2521
2522 /* Vector VRHADD. */
2da2eaf4 2523 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2524 MVE_VRHADD,
2525 0xef000140, 0xef811f51,
2526 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2527
bf0b396d 2528 /* Vector VCVT. */
2da2eaf4 2529 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2530 MVE_VCVT_FP_FIX_VEC,
2531 0xef800c50, 0xef801cd1,
2532 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2533
2534 /* Vector VCVT. */
2da2eaf4 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2536 MVE_VCVT_BETWEEN_FP_INT,
2537 0xffb30640, 0xffb31e51,
2538 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2539
2540 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2542 MVE_VCVT_FP_HALF_FP,
2543 0xee3f0e01, 0xefbf1fd1,
2544 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2545
2546 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2548 MVE_VCVT_FP_HALF_FP,
2549 0xee3f1e01, 0xefbf1fd1,
2550 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2551
2552 /* Vector VCVT. */
2da2eaf4 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2554 MVE_VCVT_FROM_FP_TO_INT,
2555 0xffb30040, 0xffb31c51,
2556 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2557
1c8f2df8 2558 /* Vector VDDUP. */
2da2eaf4 2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2560 MVE_VDDUP,
2561 0xee011f6e, 0xff811f7e,
2562 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2563
2564 /* Vector VDWDUP. */
2da2eaf4 2565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2566 MVE_VDWDUP,
2567 0xee011f60, 0xff811f70,
2568 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2569
897b9bbc 2570 /* Vector VHCADD. */
2da2eaf4 2571 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2572 MVE_VHCADD,
2573 0xee000f00, 0xff810f51,
2574 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2575
1c8f2df8 2576 /* Vector VIWDUP. */
2da2eaf4 2577 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2578 MVE_VIWDUP,
2579 0xee010f60, 0xff811f70,
2580 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2581
2582 /* Vector VIDUP. */
2da2eaf4 2583 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2584 MVE_VIDUP,
2585 0xee010f6e, 0xff811f7e,
2586 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2587
04d54ace 2588 /* Vector VLD2. */
2da2eaf4 2589 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2590 MVE_VLD2,
2591 0xfc901e00, 0xff901e5f,
2592 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2593
2594 /* Vector VLD4. */
2da2eaf4 2595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2596 MVE_VLD4,
2597 0xfc901e01, 0xff901e1f,
2598 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2599
ef1576a1 2600 /* Vector VLDRB gather load. */
2da2eaf4 2601 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2602 MVE_VLDRB_GATHER_T1,
2603 0xec900e00, 0xefb01e50,
2604 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2605
2606 /* Vector VLDRH gather load. */
2da2eaf4 2607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2608 MVE_VLDRH_GATHER_T2,
2609 0xec900e10, 0xefb01e50,
2610 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2611
2612 /* Vector VLDRW gather load. */
2da2eaf4 2613 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2614 MVE_VLDRW_GATHER_T3,
2615 0xfc900f40, 0xffb01fd0,
2616 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617
2618 /* Vector VLDRD gather load. */
2da2eaf4 2619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2620 MVE_VLDRD_GATHER_T4,
2621 0xec900fd0, 0xefb01fd0,
2622 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623
2624 /* Vector VLDRW gather load. */
2da2eaf4 2625 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2626 MVE_VLDRW_GATHER_T5,
2627 0xfd101e00, 0xff111f00,
2628 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2629
2630 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2632 MVE_VLDRD_GATHER_T6,
2633 0xfd101f00, 0xff111f00,
2634 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2635
aef6d006 2636 /* Vector VLDRB. */
2da2eaf4 2637 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2638 MVE_VLDRB_T1,
2639 0xec100e00, 0xee581e00,
2640 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2641
2642 /* Vector VLDRH. */
2da2eaf4 2643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2644 MVE_VLDRH_T2,
2645 0xec180e00, 0xee581e00,
2646 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2647
2648 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2649 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2650 MVE_VLDRB_T5,
2651 0xec101e00, 0xfe101f80,
2652 "vldrb%v.u8\t%13-15,22Q, %d"},
2653
2654 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2656 MVE_VLDRH_T6,
2657 0xec101e80, 0xfe101f80,
2658 "vldrh%v.u16\t%13-15,22Q, %d"},
2659
2660 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2662 MVE_VLDRW_T7,
2663 0xec101f00, 0xfe101f80,
2664 "vldrw%v.u32\t%13-15,22Q, %d"},
2665
56858bea 2666 /* Vector VMAX. */
2da2eaf4 2667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2668 MVE_VMAX,
2669 0xef000640, 0xef811f51,
2670 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2671
2672 /* Vector VMAXA. */
2da2eaf4 2673 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2674 MVE_VMAXA,
2675 0xee330e81, 0xffb31fd1,
2676 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2677
2678 /* Vector VMAXNM floating point. */
2da2eaf4 2679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2680 MVE_VMAXNM_FP,
2681 0xff000f50, 0xffa11f51,
2682 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2683
2684 /* Vector VMAXNMA floating point. */
2da2eaf4 2685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2686 MVE_VMAXNMA_FP,
2687 0xee3f0e81, 0xefbf1fd1,
2688 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2689
2690 /* Vector VMAXNMV floating point. */
2da2eaf4 2691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2692 MVE_VMAXNMV_FP,
2693 0xeeee0f00, 0xefff0fd1,
2694 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2695
2696 /* Vector VMAXNMAV floating point. */
2da2eaf4 2697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2698 MVE_VMAXNMAV_FP,
2699 0xeeec0f00, 0xefff0fd1,
2700 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2701
2702 /* Vector VMAXV. */
2da2eaf4 2703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2704 MVE_VMAXV,
2705 0xeee20f00, 0xeff30fd1,
2706 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2707
2708 /* Vector VMAXAV. */
2da2eaf4 2709 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2710 MVE_VMAXAV,
2711 0xeee00f00, 0xfff30fd1,
2712 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2713
2714 /* Vector VMIN. */
2da2eaf4 2715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2716 MVE_VMIN,
2717 0xef000650, 0xef811f51,
2718 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2719
2720 /* Vector VMINA. */
2da2eaf4 2721 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2722 MVE_VMINA,
2723 0xee331e81, 0xffb31fd1,
2724 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2725
2726 /* Vector VMINNM floating point. */
2da2eaf4 2727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2728 MVE_VMINNM_FP,
2729 0xff200f50, 0xffa11f51,
2730 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2731
2732 /* Vector VMINNMA floating point. */
2da2eaf4 2733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2734 MVE_VMINNMA_FP,
2735 0xee3f1e81, 0xefbf1fd1,
2736 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2737
2738 /* Vector VMINNMV floating point. */
2da2eaf4 2739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2740 MVE_VMINNMV_FP,
2741 0xeeee0f80, 0xefff0fd1,
2742 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2743
2744 /* Vector VMINNMAV floating point. */
2da2eaf4 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2746 MVE_VMINNMAV_FP,
2747 0xeeec0f80, 0xefff0fd1,
2748 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2749
2750 /* Vector VMINV. */
2da2eaf4 2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2752 MVE_VMINV,
2753 0xeee20f80, 0xeff30fd1,
2754 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2755
2756 /* Vector VMINAV. */
2da2eaf4 2757 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2758 MVE_VMINAV,
2759 0xeee00f80, 0xfff30fd1,
2760 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2761
2762 /* Vector VMLA. */
2da2eaf4 2763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2764 MVE_VMLA,
2765 0xee010e40, 0xef811f70,
2766 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2767
d3b63143
AV		 2768 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2769 opcode aliasing. */
2da2eaf4 2770 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2771 MVE_VMLALDAV,
2772 0xee801e00, 0xef801f51,
2773 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2774
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee800e00, 0xef801f51,
2778 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2780 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2782 MVE_VMLADAV_T1,
2783 0xeef00e00, 0xeff01f51,
2784 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2785
2786 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2787 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2788 MVE_VMLADAV_T2,
2789 0xeef00f00, 0xeff11f51,
2790 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2791
2792 /* Vector VMLADAV T1 variant. */
2da2eaf4 2793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2794 MVE_VMLADAV_T1,
2795 0xeef01e00, 0xeff01f51,
2796 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2797
2798 /* Vector VMLADAV T2 variant. */
2da2eaf4 2799 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2800 MVE_VMLADAV_T2,
2801 0xeef01f00, 0xeff11f51,
2802 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2803
2804 /* Vector VMLAS. */
2da2eaf4 2805 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2806 MVE_VMLAS,
2807 0xee011e40, 0xef811f70,
2808 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2809
2810 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2811 opcode aliasing. */
2da2eaf4 2812 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2813 MVE_VRMLSLDAVH,
2814 0xfe800e01, 0xff810f51,
2815 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2816
2817 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2818 opcdoe aliasing. */
2da2eaf4 2819 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2820 MVE_VMLSLDAV,
2821 0xee800e01, 0xff800f51,
2822 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2823
2824 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2826 MVE_VMLSDAV_T1,
2827 0xeef00e01, 0xfff00f51,
2828 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2829
2830 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2831 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2832 MVE_VMLSDAV_T2,
2833 0xfef00e01, 0xfff10f51,
2834 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2835
c507f10b 2836 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2837 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2838 MVE_VMOV_HFP_TO_GP,
2839 0xee000910, 0xfff00f7f,
2840 "vmov.f16\t%7,16-19F, %12-15r"},
2841
2842 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2843 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2844 MVE_VMOV_HFP_TO_GP,
2845 0xee100910, 0xfff00f7f,
2846 "vmov.f16\t%12-15r, %7,16-19F"},
2847
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_GP_TO_VEC_LANE,
2850 0xee000b10, 0xff900f1f,
2851 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2852
2853 /* Vector VORR immediate to vector.
2854 NOTE: MVE_VORR_IMM must appear in the table
2855 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2857 MVE_VORR_IMM,
2858 0xef800050, 0xefb810f0,
2859 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2860
ed63aa17
AV		 2861 /* Vector VQSHL T2 Variant.
2862 NOTE: MVE_VQSHL_T2 must appear in the table before
2863 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2864 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2865 MVE_VQSHL_T2,
2866 0xef800750, 0xef801fd1,
2867 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2868
2869 /* Vector VQSHLU T3 Variant
2870 NOTE: MVE_VQSHL_T2 must appear in the table before
2871 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2872
2da2eaf4 2873 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2874 MVE_VQSHLU_T3,
2875 0xff800650, 0xff801fd1,
2876 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2877
2878 /* Vector VRSHR
2879 NOTE: MVE_VRSHR must appear in the table before
2880 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2882 MVE_VRSHR,
2883 0xef800250, 0xef801fd1,
2884 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2885
2886 /* Vector VSHL.
2887 NOTE: MVE_VSHL must appear in the table before
2888 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2889 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2890 MVE_VSHL_T1,
2891 0xef800550, 0xff801fd1,
2892 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2893
2894 /* Vector VSHR
2895 NOTE: MVE_VSHR must appear in the table before
2896 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2898 MVE_VSHR,
2899 0xef800050, 0xef801fd1,
2900 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2901
2902 /* Vector VSLI
2903 NOTE: MVE_VSLI must appear in the table before
2904 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2906 MVE_VSLI,
2907 0xff800550, 0xff801fd1,
2908 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2909
2910 /* Vector VSRI
2911 NOTE: MVE_VSRI must appear in the table before
2912 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2914 MVE_VSRI,
2915 0xff800450, 0xff801fd1,
2916 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2917
c507f10b 2918 /* Vector VMOV immediate to vector,
ce760a76 2919 undefinded for cmode == 1111 */
2da2eaf4 2920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2921 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2922
2923 /* Vector VMOV immediate to vector,
2924 cmode == 1101 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2927 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2928
2929 /* Vector VMOV immediate to vector. */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2931 MVE_VMOV_IMM_TO_VEC,
2932 0xef800050, 0xefb810d0,
2933 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934
2935 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2936 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2937 MVE_VMOV2_VEC_LANE_TO_GP,
2938 0xec000f00, 0xffb01ff0,
2939 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2940
2941 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2942 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2943 MVE_VMOV2_VEC_LANE_TO_GP,
2944 0xec000f10, 0xffb01ff0,
2945 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2946
2947 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2948 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2949 MVE_VMOV2_GP_TO_VEC_LANE,
2950 0xec100f00, 0xffb01ff0,
2951 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2952
2953 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2955 MVE_VMOV2_GP_TO_VEC_LANE,
2956 0xec100f10, 0xffb01ff0,
e683cb41 2957 "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
c507f10b
AV		 2958
2959 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2961 MVE_VMOV_VEC_LANE_TO_GP,
2962 0xee100b10, 0xff100f1f,
2963 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2964
ed63aa17
AV		 2965 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2966 to instruction opcode aliasing. */
2da2eaf4 2967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2968 MVE_VSHLL_T1,
2969 0xeea00f40, 0xefa00fd1,
2970 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2971
14925797 2972 /* Vector VMOVL long. */
2da2eaf4 2973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2974 MVE_VMOVL,
2975 0xeea00f40, 0xefa70fd1,
2976 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2977
2978 /* Vector VMOV and narrow. */
2da2eaf4 2979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2980 MVE_VMOVN,
2981 0xfe310e81, 0xffb30fd1,
2982 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2983
c507f10b 2984 /* Floating point move extract. */
2da2eaf4 2985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2986 MVE_VMOVX,
2987 0xfeb00a40, 0xffbf0fd0,
2988 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2989
f49bb598 2990 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2992 MVE_VMUL_FP_T1,
2993 0xff000d50, 0xffa11f51,
2994 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2995
2996 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 2997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2998 MVE_VMUL_FP_T2,
2999 0xee310e60, 0xefb11f70,
3000 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3001
3002 /* Vector VMUL T1 variant. */
2da2eaf4 3003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3004 MVE_VMUL_VEC_T1,
3005 0xef000950, 0xff811f51,
3006 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3007
3008 /* Vector VMUL T2 variant. */
2da2eaf4 3009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3010 MVE_VMUL_VEC_T2,
3011 0xee011e60, 0xff811f70,
3012 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3013
3014 /* Vector VMULH. */
2da2eaf4 3015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3016 MVE_VMULH,
3017 0xee010e01, 0xef811f51,
3018 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3019
3020 /* Vector VRMULH. */
2da2eaf4 3021 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3022 MVE_VRMULH,
3023 0xee011e01, 0xef811f51,
3024 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025
14925797 3026 /* Vector VMULL integer. */
2da2eaf4 3027 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3028 MVE_VMULL_INT,
3029 0xee010e00, 0xef810f51,
3030 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031
3032 /* Vector VMULL polynomial. */
2da2eaf4 3033 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3034 MVE_VMULL_POLY,
3035 0xee310e00, 0xefb10f51,
3036 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037
c507f10b 3038 /* Vector VMVN immediate to vector. */
2da2eaf4 3039 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3040 MVE_VMVN_IMM,
3041 0xef800070, 0xefb810f0,
3042 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3043
3044 /* Vector VMVN register. */
2da2eaf4 3045 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3046 MVE_VMVN_REG,
3047 0xffb005c0, 0xffbf1fd1,
3048 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3049
f49bb598 3050 /* Vector VNEG floating point. */
2da2eaf4 3051 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3052 MVE_VNEG_FP,
3053 0xffb107c0, 0xffb31fd1,
3054 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3055
3056 /* Vector VNEG. */
2da2eaf4 3057 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3058 MVE_VNEG_VEC,
3059 0xffb103c0, 0xffb31fd1,
3060 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3061
c507f10b 3062 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3063 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3064 MVE_VORN,
3065 0xef300150, 0xffb11f51,
3066 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3067
3068 /* Vector VORR register. */
2da2eaf4 3069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3070 MVE_VORR_REG,
3071 0xef200150, 0xffb11f51,
3072 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073
c4a23bf8
SP		 3074 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3075 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3076 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3077 array. */
3078
2da2eaf4 3079 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3080 MVE_VMOV_VEC_TO_VEC,
3081 0xef200150, 0xffb11f51,
3082 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3083
14925797 3084 /* Vector VQDMULL T1 variant. */
2da2eaf4 3085 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3086 MVE_VQDMULL_T1,
3087 0xee300f01, 0xefb10f51,
3088 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3089
14b456f2 3090 /* Vector VPNOT. */
2da2eaf4 3091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3092 MVE_VPNOT,
3093 0xfe310f4d, 0xffffffff,
3094 "vpnot%v"},
3095
3096 /* Vector VPSEL. */
2da2eaf4 3097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3098 MVE_VPSEL,
3099 0xfe310f01, 0xffb11f51,
3100 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3101
3102 /* Vector VQABS. */
2da2eaf4 3103 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3104 MVE_VQABS,
3105 0xffb00740, 0xffb31fd1,
3106 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3107
3108 /* Vector VQADD T1 variant. */
2da2eaf4 3109 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3110 MVE_VQADD_T1,
3111 0xef000050, 0xef811f51,
3112 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113
3114 /* Vector VQADD T2 variant. */
2da2eaf4 3115 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3116 MVE_VQADD_T2,
3117 0xee000f60, 0xef811f70,
3118 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3119
14925797 3120 /* Vector VQDMULL T2 variant. */
2da2eaf4 3121 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3122 MVE_VQDMULL_T2,
3123 0xee300f60, 0xefb10f70,
3124 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125
3126 /* Vector VQMOVN. */
2da2eaf4 3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3128 MVE_VQMOVN,
3129 0xee330e01, 0xefb30fd1,
3130 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3131
3132 /* Vector VQMOVUN. */
2da2eaf4 3133 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3134 MVE_VQMOVUN,
3135 0xee310e81, 0xffb30fd1,
3136 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3137
d3b63143 3138 /* Vector VQDMLADH. */
2da2eaf4 3139 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3140 MVE_VQDMLADH,
3141 0xee000e00, 0xff810f51,
3142 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3143
3144 /* Vector VQRDMLADH. */
2da2eaf4 3145 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3146 MVE_VQRDMLADH,
3147 0xee000e01, 0xff810f51,
3148 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149
3150 /* Vector VQDMLAH. */
2da2eaf4 3151 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3152 MVE_VQDMLAH,
23d188c7 3153 0xee000e60, 0xff811f70,
d3b63143
AV		 3154 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3155
3156 /* Vector VQRDMLAH. */
2da2eaf4 3157 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3158 MVE_VQRDMLAH,
23d188c7 3159 0xee000e40, 0xff811f70,
d3b63143
AV		 3160 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161
3162 /* Vector VQDMLASH. */
2da2eaf4 3163 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3164 MVE_VQDMLASH,
23d188c7 3165 0xee001e60, 0xff811f70,
d3b63143
AV		 3166 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167
3168 /* Vector VQRDMLASH. */
2da2eaf4 3169 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3170 MVE_VQRDMLASH,
23d188c7 3171 0xee001e40, 0xff811f70,
d3b63143
AV		 3172 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173
3174 /* Vector VQDMLSDH. */
2da2eaf4 3175 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3176 MVE_VQDMLSDH,
3177 0xfe000e00, 0xff810f51,
3178 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3179
3180 /* Vector VQRDMLSDH. */
2da2eaf4 3181 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3182 MVE_VQRDMLSDH,
3183 0xfe000e01, 0xff810f51,
3184 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185
3186 /* Vector VQDMULH T1 variant. */
2da2eaf4 3187 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3188 MVE_VQDMULH_T1,
3189 0xef000b40, 0xff811f51,
3190 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191
3192 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3193 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3194 MVE_VQRDMULH_T2,
3195 0xff000b40, 0xff811f51,
3196 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197
3198 /* Vector VQDMULH T3 variant. */
2da2eaf4 3199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3200 MVE_VQDMULH_T3,
3201 0xee010e60, 0xff811f70,
3202 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3203
3204 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3205 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3206 MVE_VQRDMULH_T4,
3207 0xfe010e60, 0xff811f70,
3208 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209
14b456f2 3210 /* Vector VQNEG. */
2da2eaf4 3211 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3212 MVE_VQNEG,
3213 0xffb007c0, 0xffb31fd1,
3214 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3215
ed63aa17 3216 /* Vector VQRSHL T1 variant. */
2da2eaf4 3217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3218 MVE_VQRSHL_T1,
3219 0xef000550, 0xef811f51,
3220 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3221
3222 /* Vector VQRSHL T2 variant. */
2da2eaf4 3223 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3224 MVE_VQRSHL_T2,
3225 0xee331ee0, 0xefb31ff0,
3226 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3227
3228 /* Vector VQRSHRN. */
2da2eaf4 3229 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3230 MVE_VQRSHRN,
3231 0xee800f41, 0xefa00fd1,
3232 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3233
3234 /* Vector VQRSHRUN. */
2da2eaf4 3235 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3236 MVE_VQRSHRUN,
3237 0xfe800fc0, 0xffa00fd1,
3238 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3239
3240 /* Vector VQSHL T1 Variant. */
2da2eaf4 3241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3242 MVE_VQSHL_T1,
3243 0xee311ee0, 0xefb31ff0,
3244 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3245
3246 /* Vector VQSHL T4 Variant. */
2da2eaf4 3247 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3248 MVE_VQSHL_T4,
3249 0xef000450, 0xef811f51,
3250 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3251
3252 /* Vector VQSHRN. */
2da2eaf4 3253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3254 MVE_VQSHRN,
3255 0xee800f40, 0xefa00fd1,
3256 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3257
3258 /* Vector VQSHRUN. */
2da2eaf4 3259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3260 MVE_VQSHRUN,
3261 0xee800fc0, 0xffa00fd1,
3262 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3263
14b456f2 3264 /* Vector VQSUB T1 Variant. */
2da2eaf4 3265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3266 MVE_VQSUB_T1,
3267 0xef000250, 0xef811f51,
3268 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3269
3270 /* Vector VQSUB T2 Variant. */
2da2eaf4 3271 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3272 MVE_VQSUB_T2,
3273 0xee001f60, 0xef811f70,
3274 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3275
3276 /* Vector VREV16. */
2da2eaf4 3277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3278 MVE_VREV16,
3279 0xffb00140, 0xffb31fd1,
3280 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3281
3282 /* Vector VREV32. */
2da2eaf4 3283 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3284 MVE_VREV32,
3285 0xffb000c0, 0xffb31fd1,
3286 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3287
3288 /* Vector VREV64. */
2da2eaf4 3289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3290 MVE_VREV64,
3291 0xffb00040, 0xffb31fd1,
3292 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293
bf0b396d 3294 /* Vector VRINT floating point. */
2da2eaf4 3295 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3296 MVE_VRINT_FP,
3297 0xffb20440, 0xffb31c51,
3298 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3299
d3b63143 3300 /* Vector VRMLALDAVH. */
2da2eaf4 3301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3302 MVE_VRMLALDAVH,
3303 0xee800f00, 0xef811f51,
3304 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3305
3306 /* Vector VRMLALDAVH. */
2da2eaf4 3307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3308 MVE_VRMLALDAVH,
3309 0xee801f00, 0xef811f51,
3310 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311
ed63aa17 3312 /* Vector VRSHL T1 Variant. */
2da2eaf4 3313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3314 MVE_VRSHL_T1,
3315 0xef000540, 0xef811f51,
3316 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3317
3318 /* Vector VRSHL T2 Variant. */
2da2eaf4 3319 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3320 MVE_VRSHL_T2,
3321 0xee331e60, 0xefb31ff0,
3322 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3323
3324 /* Vector VRSHRN. */
2da2eaf4 3325 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3326 MVE_VRSHRN,
3327 0xfe800fc1, 0xffa00fd1,
3328 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3329
66dcaa5d 3330 /* Vector VSBC. */
2da2eaf4 3331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3332 MVE_VSBC,
3333 0xfe300f00, 0xffb10f51,
3334 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3335
ed63aa17 3336 /* Vector VSHL T2 Variant. */
2da2eaf4 3337 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3338 MVE_VSHL_T2,
3339 0xee311e60, 0xefb31ff0,
3340 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3341
3342 /* Vector VSHL T3 Variant. */
2da2eaf4 3343 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3344 MVE_VSHL_T3,
3345 0xef000440, 0xef811f51,
3346 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3347
3348 /* Vector VSHLC. */
2da2eaf4 3349 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3350 MVE_VSHLC,
3351 0xeea00fc0, 0xffa01ff0,
3352 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3353
3354 /* Vector VSHLL T2 Variant. */
2da2eaf4 3355 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3356 MVE_VSHLL_T2,
3357 0xee310e01, 0xefb30fd1,
3358 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3359
3360 /* Vector VSHRN. */
2da2eaf4 3361 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3362 MVE_VSHRN,
3363 0xee800fc1, 0xffa00fd1,
3364 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3365
04d54ace 3366 /* Vector VST2 no writeback. */
2da2eaf4 3367 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3368 MVE_VST2,
3369 0xfc801e00, 0xffb01e5f,
3370 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3371
3372 /* Vector VST2 writeback. */
2da2eaf4 3373 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3374 MVE_VST2,
3375 0xfca01e00, 0xffb01e5f,
3376 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3377
3378 /* Vector VST4 no writeback. */
2da2eaf4 3379 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3380 MVE_VST4,
3381 0xfc801e01, 0xffb01e1f,
3382 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3383
3384 /* Vector VST4 writeback. */
2da2eaf4 3385 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3386 MVE_VST4,
3387 0xfca01e01, 0xffb01e1f,
3388 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3389
ef1576a1 3390 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3391 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3392 MVE_VSTRB_SCATTER_T1,
3393 0xec800e00, 0xffb01e50,
3394 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3395
3396 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3397 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3398 MVE_VSTRH_SCATTER_T2,
3399 0xec800e10, 0xffb01e50,
3400 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3401
3402 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3403 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3404 MVE_VSTRW_SCATTER_T3,
3405 0xec800e40, 0xffb01e50,
3406 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407
3408 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3409 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3410 MVE_VSTRD_SCATTER_T4,
3411 0xec800fd0, 0xffb01fd0,
3412 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413
3414 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3416 MVE_VSTRW_SCATTER_T5,
3417 0xfd001e00, 0xff111f00,
3418 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3419
3420 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3421 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3422 MVE_VSTRD_SCATTER_T6,
3423 0xfd001f00, 0xff111f00,
3424 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3425
aef6d006 3426 /* Vector VSTRB. */
2da2eaf4 3427 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3428 MVE_VSTRB_T1,
3429 0xec000e00, 0xfe581e00,
3430 "vstrb%v.%7-8s\t%13-15Q, %d"},
3431
3432 /* Vector VSTRH. */
2da2eaf4 3433 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3434 MVE_VSTRH_T2,
3435 0xec080e00, 0xfe581e00,
3436 "vstrh%v.%7-8s\t%13-15Q, %d"},
3437
3438 /* Vector VSTRB variant T5. */
2da2eaf4 3439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3440 MVE_VSTRB_T5,
3441 0xec001e00, 0xfe101f80,
3442 "vstrb%v.8\t%13-15,22Q, %d"},
3443
3444 /* Vector VSTRH variant T6. */
2da2eaf4 3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3446 MVE_VSTRH_T6,
3447 0xec001e80, 0xfe101f80,
3448 "vstrh%v.16\t%13-15,22Q, %d"},
3449
3450 /* Vector VSTRW variant T7. */
2da2eaf4 3451 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3452 MVE_VSTRW_T7,
3453 0xec001f00, 0xfe101f80,
3454 "vstrw%v.32\t%13-15,22Q, %d"},
3455
66dcaa5d 3456 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3458 MVE_VSUB_FP_T1,
3459 0xef200d40, 0xffa11f51,
3460 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3461
3462 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3463 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3464 MVE_VSUB_FP_T2,
3465 0xee301f40, 0xefb11f70,
3466 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3467
3468 /* Vector VSUB T1 variant. */
2da2eaf4 3469 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3470 MVE_VSUB_VEC_T1,
3471 0xff000840, 0xff811f51,
3472 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3473
3474 /* Vector VSUB T2 variant. */
2da2eaf4 3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3476 MVE_VSUB_VEC_T2,
3477 0xee011f40, 0xff811f70,
3478 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3479
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3481 MVE_ASRLI,
3482 0xea50012f, 0xfff1813f,
3483 "asrl%c\t%17-19l, %9-11h, %j"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRL,
3487 0xea50012d, 0xfff101ff,
3488 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_LSLLI,
3492 0xea50010f, 0xfff1813f,
3493 "lsll%c\t%17-19l, %9-11h, %j"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLL,
3497 0xea50010d, 0xfff101ff,
3498 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSRL,
3502 0xea50011f, 0xfff1813f,
3503 "lsrl%c\t%17-19l, %9-11h, %j"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3506 MVE_SQRSHRL,
08132bdd
SP		 3507 0xea51012d, 0xfff1017f,
3508 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3511 MVE_SQRSHR,
3512 0xea500f2d, 0xfff00fff,
3513 "sqrshr%c\t%16-19S, %12-15S"},
3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQSHLL,
3517 0xea51013f, 0xfff1813f,
3518 "sqshll%c\t%17-19l, %9-11h, %j"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHL,
3522 0xea500f3f, 0xfff08f3f,
3523 "sqshl%c\t%16-19S, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SRSHRL,
3527 0xea51012f, 0xfff1813f,
3528 "srshrl%c\t%17-19l, %9-11h, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHR,
3532 0xea500f2f, 0xfff08f3f,
3533 "srshr%c\t%16-19S, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3536 MVE_UQRSHLL,
08132bdd
SP		 3537 0xea51010d, 0xfff1017f,
3538 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3541 MVE_UQRSHL,
3542 0xea500f0d, 0xfff00fff,
3543 "uqrshl%c\t%16-19S, %12-15S"},
3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQSHLL,
3547 0xea51010f, 0xfff1813f,
3548 "uqshll%c\t%17-19l, %9-11h, %j"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHL,
3552 0xea500f0f, 0xfff08f3f,
3553 "uqshl%c\t%16-19S, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_URSHRL,
3557 0xea51011f, 0xfff1813f,
3558 "urshrl%c\t%17-19l, %9-11h, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHR,
3562 0xea500f1f, 0xfff08f3f,
3563 "urshr%c\t%16-19S, %j"},
3564
e39c1607
SD		 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3566 MVE_CSINC,
3567 0xea509000, 0xfff0f000,
3568 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3569
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINV,
3572 0xea50a000, 0xfff0f000,
3573 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSET,
3577 0xea5f900f, 0xfffff00f,
3578 "cset\t%8-11S, %4-7C"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSETM,
3582 0xea5fa00f, 0xfffff00f,
3583 "csetm\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSEL,
3587 0xea508000, 0xfff0f000,
3588 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSNEG,
3592 0xea50b000, 0xfff0f000,
3593 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CINC,
3597 0xea509000, 0xfff0f000,
3598 "cinc\t%8-11S, %16-19Z, %4-7C"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINV,
3602 0xea50a000, 0xfff0f000,
3603 "cinv\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CNEG,
3607 0xea50b000, 0xfff0f000,
3608 "cneg\t%8-11S, %16-19Z, %4-7C"},
3609
143275ea
AV		 3610 {ARM_FEATURE_CORE_LOW (0),
3611 MVE_NONE,
3612 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3613};
3614
8f06b2d8
PB		 3615/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3616 ordered: they must be searched linearly from the top to obtain a correct
3617 match. */
3618
3619/* print_insn_arm recognizes the following format control codes:
3620
3621 %% %
3622
3623 %a print address for ldr/str instruction
3624 %s print address for ldr/str halfword/signextend instruction
c1e26897 3625 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3626 %b print branch destination
3627 %c print condition code (always bits 28-31)
3628 %m print register mask for ldm/stm instruction
3629 %o print operand2 (immediate or register + shift)
3630 %p print 'p' iff bits 12-15 are 15
3631 %t print 't' iff bit 21 set and bit 24 clear
3632 %B print arm BLX(1) destination
3633 %C print the PSR sub type.
62b3e311
PB		 3634 %U print barrier type.
3635 %P print address for pli instruction.
8f06b2d8
PB		 3636
3637 %<bitfield>r print as an ARM register
9eb6c0f1 3638 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3639 %<bitfield>R as %r but r15 is UNPREDICTABLE
3640 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3641 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3642 %<bitfield>d print the bitfield in decimal
43e65147 3643 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3644 %<bitfield>x print the bitfield in hex
3645 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3646
16980d0b
JB		 3647 %<bitfield>'c print specified char iff bitfield is all ones
3648 %<bitfield>`c print specified char iff bitfield is all zeroes
3649 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3650
8f06b2d8
PB		 3651 %e print arm SMI operand (bits 0..7,8..19).
3652 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3653 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3654 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3655
8f06b2d8
PB		 3656static const struct opcode32 arm_opcodes[] =
3657{
3658 /* ARM instructions. */
823d2571
TG		 3659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3660 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3662 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3663
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3665 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3667 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3668 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3669 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3671 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3673 0x00800090, 0x0fa000f0,
3674 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3676 0x00a00090, 0x0fa000f0,
3677 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3678
105bde57 3679 /* V8.2 RAS extension instructions. */
4d1464f2 3680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3681 0xe320f010, 0xffffffff, "esb"},
3682
26417f19
AC		 3683 /* V8-R instructions. */
3684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
3685 0xf57ff04c, 0xffffffff, "dfb"},
3686
53c4b28b 3687 /* V8 instructions. */
823d2571
TG		 3688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3689 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3690 /* Defined in V8 but is in NOP space so available to all arch. */
3691 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3692 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3694 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3695 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3696 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3697 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3698 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3699 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3700 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3701 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3702 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3703 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3704 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3705 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3706 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3707 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3708 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3709 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3710 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3711 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3712 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3713 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3714 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3715 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3716 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3717 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3718 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3719 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3720 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3721 /* CRC32 instructions. */
8b301fbb 3722 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3723 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3725 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3727 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3729 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3731 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3733 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3734
ddfded2f
MW		 3735 /* Privileged Access Never extension instructions. */
3736 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3737 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3738
90ec0d68 3739 /* Virtualization Extension instructions. */
823d2571
TG		 3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3742
eea54501 3743 /* Integer Divide Extension instructions. */
823d2571
TG		 3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3745 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3747 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3748
60e5ef9f 3749 /* MP Extension instructions. */
823d2571 3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3751
c597cc3d
SD		 3752 /* Speculation Barriers. */
3753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3756
62b3e311 3757 /* V7 instructions. */
823d2571
TG		 3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3766 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3767
c19d1205 3768 /* ARM V6T2 instructions. */
823d2571
TG		 3769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3770 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3772 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3774 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3776 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3777
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3779 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3781 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3782
ff8646ee 3783 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3784 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3786 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3788 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3790 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3791
f4c65163 3792 /* ARM Security extension instructions. */
823d2571
TG		 3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3794 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3795
8f06b2d8 3796 /* ARM V6K instructions. */
823d2571
TG		 3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3798 0xf57ff01f, 0xffffffff, "clrex"},
3799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3800 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3802 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3804 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3806 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3808 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3810 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3811
7fadb25d
SD		 3812 /* ARMv8.5-A instructions. */
3813 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3814
8f06b2d8 3815 /* ARM V6K NOP hints. */
823d2571
TG		 3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3817 0x0320f001, 0x0fffffff, "yield%c"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3819 0x0320f002, 0x0fffffff, "wfe%c"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3821 0x0320f003, 0x0fffffff, "wfi%c"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3823 0x0320f004, 0x0fffffff, "sev%c"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3825 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3826
fe56b6ce 3827 /* ARM V6 instructions. */
823d2571
TG		 3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3829 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3831 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3833 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3835 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3837 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3839 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3841 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3843 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3845 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3847 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3849 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3851 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3853 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3855 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3857 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3859 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3861 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3863 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3865 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3867 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3869 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3871 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3873 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3875 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3877 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3879 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3881 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3883 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3885 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3887 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3889 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3891 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3893 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3895 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3897 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3899 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3901 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3903 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3905 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3907 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3909 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3911 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3913 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3915 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3917 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3919 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3921 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3923 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3925 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3927 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3929 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3931 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3933 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3935 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3937 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3939 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3941 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3943 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3945 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3947 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3949 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3951 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3953 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3955 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3957 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3959 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3961 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3963 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3965 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3967 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3969 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3971 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3973 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3975 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3977 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3979 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3981 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3983 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3985 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3987 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3989 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3991 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3993 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3995 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3997 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3999 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4001 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4003 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4005 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4007 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4009 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4011 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4013 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4015 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4017 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4019 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4021 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4023 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4025 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4027 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4029 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4031 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4033 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4035 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4037 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4039 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4041 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4043 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4045 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4047 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4049 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4051 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4053 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4055 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4057 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4059 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4061 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4063 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4065 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4067 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4069 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4071 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 4072
8f06b2d8 4073 /* V5J instruction. */
823d2571
TG		 4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4075 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4076
8f06b2d8 4077 /* V5 Instructions. */
823d2571
TG		 4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4079 0xe1200070, 0xfff000f0,
4080 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4082 0xfa000000, 0xfe000000, "blx\t%B"},
4083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4084 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4086 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4087
4088 /* V5E "El Segundo" Instructions. */
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4090 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4092 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4094 0xf450f000, 0xfc70f000, "pld\t%a"},
4095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4096 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4098 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4100 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4102 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4103
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4105 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4107 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4108
4109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4110 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4112 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4114 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4116 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4117
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4119 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4121 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4123 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4125 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4126
4127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4128 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4130 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4131
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4133 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4135 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4137 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4139 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4140
8f06b2d8 4141 /* ARM Instructions. */
823d2571
TG		 4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4143 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4144
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4146 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4148 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4150 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4152 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4154 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4156 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4157
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4159 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4161 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4163 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4165 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4166
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4168 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4170 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4172 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4174 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4175
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4177 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4179 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4181 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4182
4183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4184 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4186 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4188 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4189
4190 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4191 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4193 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4195 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4196
4197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4198 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4200 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4202 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4203
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4205 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4207 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4209 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4210
4211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4212 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4214 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4216 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4217
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4219 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4221 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4223 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4224
4225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4226 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4228 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4230 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4231
4232 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4233 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4235 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4237 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4238
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4240 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4242 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4244 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4245
4246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4247 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4249 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4251 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4252
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4254 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4256 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4258 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4259
4260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4261 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4263 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4265 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4266
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4268 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4270 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4272 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4273
4274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4275 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4277 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4279 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4281 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4282 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4283 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4285 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4287 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4288
4289 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4290 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4292 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4294 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4295
4296 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4297 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4299 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4301 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4302
4303 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4304 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4306 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4307
4308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4309 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4310
4311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4312 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4314 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4315
4316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4317 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4319 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4321 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4323 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4325 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4327 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4329 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4331 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4332 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4333 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4335 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4337 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4339 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4341 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4343 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4345 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4347 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4349 0x092d0000, 0x0fff0000, "push%c\t%m"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4351 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4352 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4353 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4354
4355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4356 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4358 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4360 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4362 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4364 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4366 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4368 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4370 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4372 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4374 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4376 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4378 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4380 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4381 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4382 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4384 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4386 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4388 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4390 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4392 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4393
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4395 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4397 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4398
4399 /* The rest. */
4ab90a7a
AV		 4400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4401 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4403 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4404 {ARM_FEATURE_CORE_LOW (0),
4405 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4406};
4407
4408/* print_insn_thumb16 recognizes the following format control codes:
4409
4410 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4411 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4412 %<bitfield>I print bitfield as a signed decimal
4413 (top bit of range being the sign bit)
4414 %N print Thumb register mask (with LR)
4415 %O print Thumb register mask (with PC)
4416 %M print Thumb register mask
4417 %b print CZB's 6-bit unsigned branch destination
4418 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4419 %c print the condition code
4420 %C print the condition code, or "s" if not conditional
4421 %x print warning if conditional an not at end of IT block"
4422 %X print "\t; unpredictable <IT:code>" if conditional
4423 %I print IT instruction suffix and operands
4547cb56 4424 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4425 %<bitfield>r print bitfield as an ARM register
4426 %<bitfield>d print bitfield as a decimal
4427 %<bitfield>H print (bitfield * 2) as a decimal
4428 %<bitfield>W print (bitfield * 4) as a decimal
4429 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4430 %<bitfield>B print Thumb branch destination (signed displacement)
4431 %<bitfield>c print bitfield as a condition code
4432 %<bitnum>'c print specified char iff bit is one
4433 %<bitnum>?ab print a if bit is one else print b. */
4434
4435static const struct opcode16 thumb_opcodes[] =
4436{
4437 /* Thumb instructions. */
4438
16a1fa25
TP		 4439 /* ARMv8-M Security Extensions instructions. */
4440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4442
53c4b28b 4443 /* ARM V8 instructions. */
823d2571
TG		 4444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4446 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4447
8f06b2d8 4448 /* ARM V6K no-argument instructions. */
823d2571
TG		 4449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4455
4456 /* ARM V6T2 instructions. */
ff8646ee
TP		 4457 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4458 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4459 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4460 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4462
4463 /* ARM V6. */
823d2571
TG		 4464 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4475
4476 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4478 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4479 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4480 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4481 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4482 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4484 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4485 /* Format 4. */
823d2571
TG		 4486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4502 /* format 13 */
823d2571
TG		 4503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4505 /* format 5 */
823d2571
TG		 4506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4510 /* format 14 */
823d2571
TG		 4511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4513 /* format 2 */
823d2571
TG		 4514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4515 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4517 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4518 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4519 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4520 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4521 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4522 /* format 8 */
823d2571
TG		 4523 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4524 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4526 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4527 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4528 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4529 /* format 7 */
823d2571
TG		 4530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4531 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4533 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4534 /* format 1 */
823d2571
TG		 4535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4537 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4540 /* format 3 */
823d2571
TG		 4541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4545 /* format 6 */
823d2571
TG		 4546 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4548 0x4800, 0xF800,
4549 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4550 /* format 9 */
823d2571
TG		 4551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4552 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4554 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4556 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4557 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4558 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4559 /* format 10 */
823d2571
TG		 4560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4561 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4563 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4564 /* format 11 */
823d2571
TG		 4565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4566 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4568 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4569 /* format 12 */
823d2571
TG		 4570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4571 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4573 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4574 /* format 15 */
823d2571
TG		 4575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4577 /* format 17 */
823d2571 4578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4579 /* format 16 */
823d2571
TG		 4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4583 /* format 18 */
823d2571 4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4585
4586 /* The E800 .. FFFF range is unconditionally redirected to the
4587 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4588 are processed via that table. Thus, we can never encounter a
4589 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4591 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4592};
4593
4594/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4595 We adopt the convention that hw1 is the high 16 bits of .value and
4596 .mask, hw2 the low 16 bits.
4597
4598 print_insn_thumb32 recognizes the following format control codes:
4599
4600 %% %
4601
4602 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4603 %M print a modified 12-bit immediate (same location)
4604 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4605 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4606 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4607 %S print a possibly-shifted Rm
4608
32a94698 4609 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4610 %a print the address of a plain load/store
4611 %w print the width and signedness of a core load/store
4612 %m print register mask for ldm/stm
4b5a202f 4613 %n print register mask for clrm
8f06b2d8
PB		 4614
4615 %E print the lsb and width fields of a bfc/bfi instruction
4616 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4617 %G print a fallback offset for Branch Future instructions
e5d6e09e 4618 %W print an offset for BF instruction
1caf72a5 4619 %Y print an offset for BFL instruction
1889da70 4620 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4621 %Q print an offset for Low Overhead Loop instructions
4622 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4623 %b print a conditional branch offset
4624 %B print an unconditional branch offset
4625 %s print the shift field of an SSAT instruction
4626 %R print the rotation field of an SXT instruction
62b3e311
PB		 4627 %U print barrier type.
4628 %P print address for pli instruction.
c22aaad1
PB		 4629 %c print the condition code
4630 %x print warning if conditional an not at end of IT block"
4631 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4632
4633 %<bitfield>d print bitfield in decimal
f0fba320 4634 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4635 %<bitfield>W print bitfield*4 in decimal
4636 %<bitfield>r print bitfield as an ARM register
dd5181d5 4637 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4638 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4639 %<bitfield>c print bitfield as a condition code
4640
16980d0b
JB		 4641 %<bitfield>'c print specified char iff bitfield is all ones
4642 %<bitfield>`c print specified char iff bitfield is all zeroes
4643 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4644
4645 With one exception at the bottom (done because BL and BLX(1) need
4646 to come dead last), this table was machine-sorted first in
4647 decreasing order of number of bits set in the mask, then in
4648 increasing numeric order of mask, then in increasing numeric order
4649 of opcode. This order is not the clearest for a human reader, but
4650 is guaranteed never to catch a special-case bit pattern with a more
4651 general mask, which is important, because this instruction encoding
4652 makes heavy use of special-case bit patterns. */
4653static const struct opcode32 thumb32_opcodes[] =
4654{
4b5a202f
AV		 4655 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4656 instructions. */
60f993ce 4657 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4658 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4660 0xf02fc001, 0xfffff001, "le\t%P"},
4661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4662 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4663 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4664 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4665 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4666 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4667 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4668 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4669 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4670 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4671 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4672 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4673
4389b29a
AV		 4674 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4675 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4676 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4677 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4679 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4680 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4681 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4682 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4683 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4684
4b5a202f
AV		 4685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4686 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4687
16a1fa25
TP		 4688 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4691 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4692 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4693 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4695 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4697 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4698
105bde57 4699 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4700 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4701 0xf3af8010, 0xffffffff, "esb"},
4702
53c4b28b 4703 /* V8 instructions. */
823d2571
TG		 4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4705 0xf3af8005, 0xffffffff, "sevl%c.w"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4707 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4709 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4711 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4713 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4715 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4717 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4719 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4721 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4723 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4725 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4727 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4729 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4731 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4733 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4735 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4736
26417f19
AC		 4737 /* V8-R instructions. */
4738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
4739 0xf3bf8f4c, 0xffffffff, "dfb%c"},
4740
dd5181d5 4741 /* CRC32 instructions. */
8b301fbb 4742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4743 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4745 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4746 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4747 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4749 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4751 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4752 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4753 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4754
c597cc3d
SD		 4755 /* Speculation Barriers. */
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4759
62b3e311 4760 /* V7 instructions. */
823d2571
TG		 4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4769 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4771 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4772
90ec0d68 4773 /* Virtualization Extension instructions. */
823d2571 4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4775 /* We skip ERET as that is SUBS pc, lr, #0. */
4776
60e5ef9f 4777 /* MP Extension instructions. */
823d2571 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4779
f4c65163 4780 /* Security extension instructions. */
823d2571 4781 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4782
7fadb25d
SD		 4783 /* ARMv8.5-A instructions. */
4784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4785
8f06b2d8 4786 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4793 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4795
ff8646ee 4796 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4797 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4799 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4801 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4803 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4805 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4807 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4809 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4811 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4813 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4815 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4817 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4819 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4821 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4823 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4825 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4826 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4827 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4829 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4831 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4833 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4835 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4837 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4839 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4841 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4843 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4844 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4845 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4847 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4849 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4851 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4853 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4855 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4857 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4859 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4861 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4863 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4865 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4867 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4869 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4871 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4873 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4875 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4877 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4879 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4881 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4883 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4885 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4887 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4889 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4891 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4893 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4895 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4897 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4899 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4901 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4903 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4905 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4907 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4909 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4911 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4913 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4915 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4917 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4919 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4921 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4923 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4925 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4927 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4929 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4931 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4933 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4935 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4937 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4939 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4941 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4943 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4945 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4947 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4949 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4951 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4952 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4953 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4955 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4957 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4959 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4961 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4963 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4965 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4967 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4969 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4971 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4973 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4975 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4977 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4979 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4981 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4983 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4985 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4987 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4989 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4991 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4993 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4995 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4997 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4999 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5001 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
5002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5003 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5005 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5007 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5009 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5011 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5013 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5015 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5017 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5019 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5021 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5023 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5025 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5027 0xf810f000, 0xff70f000, "pld%c\t%a"},
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5029 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5031 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5033 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5035 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5037 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5039 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5041 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5043 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5045 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5047 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5049 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5051 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5053 0xfb100000, 0xfff000c0,
5054 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xfbc00080, 0xfff000c0,
5057 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5059 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5061 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 5063 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 5064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5065 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5067 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5069 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5071 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5072 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5073 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5075 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5077 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5079 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5081 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5083 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5085 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5087 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5089 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5091 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5093 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5095 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5097 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5099 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5101 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5103 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5105 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5107 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5109 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5111 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5113 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5115 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5117 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5119 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5121 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5123 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5125 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5127 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5129 0xe9400000, 0xff500000,
5130 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xe9500000, 0xff500000,
5133 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5135 0xe8600000, 0xff700000,
5136 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138 0xe8700000, 0xff700000,
5139 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5141 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5143 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5144
5145 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5147 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5149 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5151 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5153 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5154
8f06b2d8 5155 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5157 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5159 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5160
5161 /* Fallback. */
823d2571
TG		 5162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5163 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5164 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5165};
ff4a8d2b 5166
8f06b2d8
PB		 5167static const char *const arm_conditional[] =
5168{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5169 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5170
5171static const char *const arm_fp_const[] =
5172{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5173
5174static const char *const arm_shift[] =
5175{"lsl", "lsr", "asr", "ror"};
5176
5177typedef struct
5178{
5179 const char *name;
5180 const char *description;
5181 const char *reg_names[16];
5182}
5183arm_regname;
5184
5185static const arm_regname regnames[] =
5186{
65b48a81 5187 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5188 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5189 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5190 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5191 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5192 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5193 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5194 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5195 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5196 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5197 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5198 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5199 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5200 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5201 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5202};
5203
5204static const char *const iwmmxt_wwnames[] =
5205{"b", "h", "w", "d"};
5206
5207static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5208{"b", "bus", "bc", "bss",
5209 "h", "hus", "hc", "hss",
5210 "w", "wus", "wc", "wss",
5211 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5212};
5213
5214static const char *const iwmmxt_regnames[] =
5215{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5216 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5217};
5218
5219static const char *const iwmmxt_cregnames[] =
5220{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5221 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5222};
5223
143275ea
AV		 5224static const char *const vec_condnames[] =
5225{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5226};
5227
5228static const char *const mve_predicatenames[] =
5229{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5230 "eee", "ee", "eet", "e", "ett", "et", "ete"
5231};
5232
5233/* Names for 2-bit size field for mve vector isntructions. */
5234static const char *const mve_vec_sizename[] =
5235 { "8", "16", "32", "64"};
5236
5237/* Indicates whether we are processing a then predicate,
5238 else predicate or none at all. */
5239enum vpt_pred_state
5240{
5241 PRED_NONE,
5242 PRED_THEN,
5243 PRED_ELSE
5244};
5245
5246/* Information used to process a vpt block and subsequent instructions. */
5247struct vpt_block
5248{
5249 /* Are we in a vpt block. */
78933a4a 5250 bool in_vpt_block;
143275ea
AV		 5251
5252 /* Next predicate state if in vpt block. */
5253 enum vpt_pred_state next_pred_state;
5254
5255 /* Mask from vpt/vpst instruction. */
5256 long predicate_mask;
5257
5258 /* Instruction number in vpt block. */
5259 long current_insn_num;
5260
5261 /* Number of instructions in vpt block.. */
5262 long num_pred_insn;
5263};
5264
5265static struct vpt_block vpt_block_state =
5266{
78933a4a 5267 false,
143275ea
AV		 5268 PRED_NONE,
5269 0,
5270 0,
5271 0
5272};
5273
8f06b2d8
PB		 5274/* Default to GCC register name set. */
5275static unsigned int regname_selected = 1;
5276
65b48a81 5277#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5278#define arm_regnames regnames[regname_selected].reg_names
5279
78933a4a 5280static bool force_thumb = false;
4934a27c 5281static uint16_t cde_coprocs = 0;
8f06b2d8 5282
c22aaad1
PB		 5283/* Current IT instruction state. This contains the same state as the IT
5284 bits in the CPSR. */
5285static unsigned int ifthen_state;
5286/* IT state for the next instruction. */
5287static unsigned int ifthen_next_state;
5288/* The address of the insn for which the IT state is valid. */
5289static bfd_vma ifthen_address;
5290#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5291/* Indicates that the current Conditional state is unconditional or outside
5292 an IT block. */
5293#define COND_UNCOND 16
c22aaad1 5294
8f06b2d8
PB		 5295\f
5296/* Functions. */
143275ea
AV		 5297/* Extract the predicate mask for a VPT or VPST instruction.
5298 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5299
5300static long
5301mve_extract_pred_mask (long given)
5302{
5303 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5304}
5305
5306/* Return the number of instructions in a MVE predicate block. */
5307static long
5308num_instructions_vpt_block (long given)
5309{
5310 long mask = mve_extract_pred_mask (given);
5311 if (mask == 0)
5312 return 0;
5313
5314 if (mask == 8)
5315 return 1;
5316
5317 if ((mask & 7) == 4)
5318 return 2;
5319
5320 if ((mask & 3) == 2)
5321 return 3;
5322
5323 if ((mask & 1) == 1)
5324 return 4;
5325
5326 return 0;
5327}
5328
5329static void
5330mark_outside_vpt_block (void)
5331{
78933a4a 5332 vpt_block_state.in_vpt_block = false;
143275ea
AV		 5333 vpt_block_state.next_pred_state = PRED_NONE;
5334 vpt_block_state.predicate_mask = 0;
5335 vpt_block_state.current_insn_num = 0;
5336 vpt_block_state.num_pred_insn = 0;
5337}
5338
5339static void
5340mark_inside_vpt_block (long given)
5341{
78933a4a 5342 vpt_block_state.in_vpt_block = true;
143275ea
AV		 5343 vpt_block_state.next_pred_state = PRED_THEN;
5344 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5345 vpt_block_state.current_insn_num = 0;
5346 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5347 assert (vpt_block_state.num_pred_insn >= 1);
5348}
5349
5350static enum vpt_pred_state
5351invert_next_predicate_state (enum vpt_pred_state astate)
5352{
5353 if (astate == PRED_THEN)
5354 return PRED_ELSE;
5355 else if (astate == PRED_ELSE)
5356 return PRED_THEN;
5357 else
5358 return PRED_NONE;
5359}
5360
5361static enum vpt_pred_state
5362update_next_predicate_state (void)
5363{
5364 long pred_mask = vpt_block_state.predicate_mask;
5365 long mask_for_insn = 0;
5366
5367 switch (vpt_block_state.current_insn_num)
5368 {
5369 case 1:
5370 mask_for_insn = 8;
5371 break;
5372
5373 case 2:
5374 mask_for_insn = 4;
5375 break;
5376
5377 case 3:
5378 mask_for_insn = 2;
5379 break;
5380
5381 case 4:
5382 return PRED_NONE;
5383 }
5384
5385 if (pred_mask & mask_for_insn)
5386 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5387 else
5388 return vpt_block_state.next_pred_state;
5389}
5390
5391static void
5392update_vpt_block_state (void)
5393{
5394 vpt_block_state.current_insn_num++;
5395 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5396 {
5397 /* No more instructions to process in vpt block. */
5398 mark_outside_vpt_block ();
5399 return;
5400 }
5401
5402 vpt_block_state.next_pred_state = update_next_predicate_state ();
5403}
8f06b2d8 5404
16980d0b
JB		 5405/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5406 Returns pointer to following character of the format string and
5407 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5408 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5409
5410static const char *
fe56b6ce
NC		 5411arm_decode_bitfield (const char *ptr,
5412 unsigned long insn,
5413 unsigned long *valuep,
5414 int *widthp)
16980d0b
JB		 5415{
5416 unsigned long value = 0;
5417 int width = 0;
43e65147
L		 5418
5419 do
16980d0b
JB		 5420 {
5421 int start, end;
5422 int bits;
5423
5424 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5425 start = start * 10 + *ptr - '0';
5426 if (*ptr == '-')
5427 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5428 end = end * 10 + *ptr - '0';
5429 else
5430 end = start;
5431 bits = end - start;
5432 if (bits < 0)
5433 abort ();
5434 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5435 width += bits + 1;
5436 }
5437 while (*ptr++ == ',');
5438 *valuep = value;
5439 if (widthp)
5440 *widthp = width;
5441 return ptr - 1;
5442}
5443
8f06b2d8 5444static void
37b37b2d 5445arm_decode_shift (long given, fprintf_ftype func, void *stream,
78933a4a 5446 bool print_shift)
8f06b2d8
PB		 5447{
5448 func (stream, "%s", arm_regnames[given & 0xf]);
5449
5450 if ((given & 0xff0) != 0)
5451 {
5452 if ((given & 0x10) == 0)
5453 {
5454 int amount = (given & 0xf80) >> 7;
5455 int shift = (given & 0x60) >> 5;
5456
5457 if (amount == 0)
5458 {
5459 if (shift == 3)
5460 {
5461 func (stream, ", rrx");
5462 return;
5463 }
5464
5465 amount = 32;
5466 }
5467
37b37b2d
RE		 5468 if (print_shift)
5469 func (stream, ", %s #%d", arm_shift[shift], amount);
5470 else
5471 func (stream, ", #%d", amount);
8f06b2d8 5472 }
74bdfecf 5473 else if ((given & 0x80) == 0x80)
aefd8a40 5474 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5475 else if (print_shift)
8f06b2d8
PB		 5476 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5477 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5478 else
5479 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5480 }
5481}
5482
73cd51e5
AV		 5483/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5484
78933a4a 5485static bool
73cd51e5
AV		 5486is_mve_okay_in_it (enum mve_instructions matched_insn)
5487{
c507f10b
AV		 5488 switch (matched_insn)
5489 {
5490 case MVE_VMOV_GP_TO_VEC_LANE:
5491 case MVE_VMOV2_VEC_LANE_TO_GP:
5492 case MVE_VMOV2_GP_TO_VEC_LANE:
5493 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5494 case MVE_LSLL:
5495 case MVE_LSLLI:
5496 case MVE_LSRL:
5497 case MVE_ASRL:
5498 case MVE_ASRLI:
5499 case MVE_SQRSHRL:
5500 case MVE_SQRSHR:
5501 case MVE_UQRSHL:
5502 case MVE_UQRSHLL:
5503 case MVE_UQSHL:
5504 case MVE_UQSHLL:
5505 case MVE_URSHRL:
5506 case MVE_URSHR:
5507 case MVE_SRSHRL:
5508 case MVE_SRSHR:
5509 case MVE_SQSHLL:
5510 case MVE_SQSHL:
78933a4a 5511 return true;
c507f10b 5512 default:
78933a4a 5513 return false;
c507f10b 5514 }
73cd51e5
AV		 5515}
5516
78933a4a 5517static bool
73cd51e5
AV		 5518is_mve_architecture (struct disassemble_info *info)
5519{
5520 struct arm_private_data *private_data = info->private_data;
5521 arm_feature_set allowed_arches = private_data->features;
5522
5523 arm_feature_set arm_ext_v8_1m_main
5524 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5525
5526 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5527 && !ARM_CPU_IS_ANY (allowed_arches))
78933a4a 5528 return true;
73cd51e5 5529 else
78933a4a 5530 return false;
73cd51e5
AV		 5531}
5532
78933a4a 5533static bool
143275ea
AV		 5534is_vpt_instruction (long given)
5535{
5536
5537 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5538 if ((given & 0x0040e000) == 0)
78933a4a 5539 return false;
143275ea
AV		 5540
5541 /* VPT floating point T1 variant. */
5542 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5543 /* VPT floating point T2 variant. */
5544 || ((given & 0xefb10f50) == 0xee310f40)
5545 /* VPT vector T1 variant. */
5546 || ((given & 0xff811f51) == 0xfe010f00)
5547 /* VPT vector T2 variant. */
5548 || ((given & 0xff811f51) == 0xfe010f01
5549 && ((given & 0x300000) != 0x300000))
5550 /* VPT vector T3 variant. */
5551 || ((given & 0xff811f50) == 0xfe011f00)
5552 /* VPT vector T4 variant. */
5553 || ((given & 0xff811f70) == 0xfe010f40)
5554 /* VPT vector T5 variant. */
5555 || ((given & 0xff811f70) == 0xfe010f60)
5556 /* VPT vector T6 variant. */
5557 || ((given & 0xff811f50) == 0xfe011f40)
5558 /* VPST vector T variant. */
5559 || ((given & 0xffbf1fff) == 0xfe310f4d))
78933a4a 5560 return true;
143275ea 5561 else
78933a4a 5562 return false;
143275ea
AV		 5563}
5564
73cd51e5
AV		 5565/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5566 and ending bitfield = END. END must be greater than START. */
5567
5568static unsigned long
5569arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5570{
5571 int bits = end - start;
5572
5573 if (bits < 0)
5574 abort ();
5575
5576 return ((given >> start) & ((2ul << bits) - 1));
5577}
5578
5579/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5580 START:END and START2:END2. END/END2 must be greater than
5581 START/START2. */
5582
5583static unsigned long
5584arm_decode_field_multiple (unsigned long given, unsigned int start,
5585 unsigned int end, unsigned int start2,
5586 unsigned int end2)
5587{
5588 int bits = end - start;
5589 int bits2 = end2 - start2;
5590 unsigned long value = 0;
5591 int width = 0;
5592
5593 if (bits2 < 0)
5594 abort ();
5595
5596 value = arm_decode_field (given, start, end);
5597 width += bits + 1;
5598
5599 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5600 return value;
5601}
5602
5603/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5604 This helps us decode instructions that change mnemonic depending on specific
5605 operand values/encodings. */
5606
78933a4a 5607static bool
73cd51e5
AV		 5608is_mve_encoding_conflict (unsigned long given,
5609 enum mve_instructions matched_insn)
5610{
143275ea
AV		 5611 switch (matched_insn)
5612 {
5613 case MVE_VPST:
5614 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5615 return true;
143275ea 5616 else
78933a4a 5617 return false;
143275ea
AV		 5618
5619 case MVE_VPT_FP_T1:
5620 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5621 return true;
143275ea
AV		 5622 if ((arm_decode_field (given, 12, 12) == 0)
5623 && (arm_decode_field (given, 0, 0) == 1))
78933a4a
AM		 5624 return true;
5625 return false;
143275ea
AV		 5626
5627 case MVE_VPT_FP_T2:
5628 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5629 return true;
143275ea 5630 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a
AM		 5631 return true;
5632 return false;
143275ea
AV		 5633
5634 case MVE_VPT_VEC_T1:
5635 case MVE_VPT_VEC_T2:
5636 case MVE_VPT_VEC_T3:
5637 case MVE_VPT_VEC_T4:
5638 case MVE_VPT_VEC_T5:
5639 case MVE_VPT_VEC_T6:
5640 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
78933a4a 5641 return true;
143275ea 5642 if (arm_decode_field (given, 20, 21) == 3)
78933a4a
AM		 5643 return true;
5644 return false;
143275ea
AV		 5645
5646 case MVE_VCMP_FP_T1:
5647 if ((arm_decode_field (given, 12, 12) == 0)
5648 && (arm_decode_field (given, 0, 0) == 1))
78933a4a 5649 return true;
143275ea 5650 else
78933a4a 5651 return false;
143275ea
AV		 5652
5653 case MVE_VCMP_FP_T2:
5654 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5655 return true;
143275ea 5656 else
78933a4a 5657 return false;
143275ea 5658
14b456f2
AV		 5659 case MVE_VQADD_T2:
5660 case MVE_VQSUB_T2:
f49bb598
AV		 5661 case MVE_VMUL_VEC_T2:
5662 case MVE_VMULH:
5663 case MVE_VRMULH:
56858bea
AV		 5664 case MVE_VMLA:
5665 case MVE_VMAX:
5666 case MVE_VMIN:
e523f101 5667 case MVE_VBRSR:
66dcaa5d
AV		 5668 case MVE_VADD_VEC_T2:
5669 case MVE_VSUB_VEC_T2:
5670 case MVE_VABAV:
ed63aa17
AV		 5671 case MVE_VQRSHL_T1:
5672 case MVE_VQSHL_T4:
5673 case MVE_VRSHL_T1:
5674 case MVE_VSHL_T3:
897b9bbc
AV		 5675 case MVE_VCADD_VEC:
5676 case MVE_VHCADD:
1c8f2df8
AV		 5677 case MVE_VDDUP:
5678 case MVE_VIDUP:
d3b63143
AV		 5679 case MVE_VQRDMLADH:
5680 case MVE_VQDMLAH:
5681 case MVE_VQRDMLAH:
5682 case MVE_VQDMLASH:
5683 case MVE_VQRDMLASH:
5684 case MVE_VQDMLSDH:
5685 case MVE_VQRDMLSDH:
5686 case MVE_VQDMULH_T3:
5687 case MVE_VQRDMULH_T4:
5688 case MVE_VQDMLADH:
5689 case MVE_VMLAS:
14925797 5690 case MVE_VMULL_INT:
9743db03
AV		 5691 case MVE_VHADD_T2:
5692 case MVE_VHSUB_T2:
143275ea
AV		 5693 case MVE_VCMP_VEC_T1:
5694 case MVE_VCMP_VEC_T2:
5695 case MVE_VCMP_VEC_T3:
5696 case MVE_VCMP_VEC_T4:
5697 case MVE_VCMP_VEC_T5:
5698 case MVE_VCMP_VEC_T6:
5699 if (arm_decode_field (given, 20, 21) == 3)
78933a4a 5700 return true;
143275ea 5701 else
78933a4a 5702 return false;
143275ea 5703
04d54ace
AV		 5704 case MVE_VLD2:
5705 case MVE_VLD4:
5706 case MVE_VST2:
5707 case MVE_VST4:
5708 if (arm_decode_field (given, 7, 8) == 3)
78933a4a 5709 return true;
04d54ace 5710 else
78933a4a 5711 return false;
04d54ace 5712
aef6d006
AV		 5713 case MVE_VSTRB_T1:
5714 case MVE_VSTRH_T2:
5715 if ((arm_decode_field (given, 24, 24) == 0)
5716 && (arm_decode_field (given, 21, 21) == 0))
5717 {
78933a4a 5718 return true;
aef6d006
AV		 5719 }
5720 else if ((arm_decode_field (given, 7, 8) == 3))
78933a4a 5721 return true;
aef6d006 5722 else
78933a4a 5723 return false;
aef6d006 5724
e683cb41
AC		 5725 case MVE_VLDRB_T1:
5726 case MVE_VLDRH_T2:
5727 case MVE_VLDRW_T7:
aef6d006
AV		 5728 case MVE_VSTRB_T5:
5729 case MVE_VSTRH_T6:
5730 case MVE_VSTRW_T7:
5731 if ((arm_decode_field (given, 24, 24) == 0)
5732 && (arm_decode_field (given, 21, 21) == 0))
5733 {
78933a4a 5734 return true;
aef6d006
AV		 5735 }
5736 else
78933a4a 5737 return false;
aef6d006 5738
bf0b396d
AV		 5739 case MVE_VCVT_FP_FIX_VEC:
5740 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5741
c507f10b
AV		 5742 case MVE_VBIC_IMM:
5743 case MVE_VORR_IMM:
5744 {
5745 unsigned long cmode = arm_decode_field (given, 8, 11);
5746
5747 if ((cmode & 1) == 0)
78933a4a 5748 return true;
c507f10b 5749 else if ((cmode & 0xc) == 0xc)
78933a4a 5750 return true;
c507f10b 5751 else
78933a4a 5752 return false;
c507f10b
AV		 5753 }
5754
5755 case MVE_VMVN_IMM:
5756 {
5757 unsigned long cmode = arm_decode_field (given, 8, 11);
5758
ce760a76 5759 if (cmode == 0xe)
78933a4a 5760 return true;
ce760a76 5761 else if ((cmode & 0x9) == 1)
78933a4a 5762 return true;
ce760a76 5763 else if ((cmode & 0xd) == 9)
78933a4a 5764 return true;
c507f10b 5765 else
78933a4a 5766 return false;
c507f10b
AV		 5767 }
5768
5769 case MVE_VMOV_IMM_TO_VEC:
5770 if ((arm_decode_field (given, 5, 5) == 1)
5771 && (arm_decode_field (given, 8, 11) != 0xe))
78933a4a 5772 return true;
c507f10b 5773 else
78933a4a 5774 return false;
c507f10b 5775
14925797
AV		 5776 case MVE_VMOVL:
5777 {
5778 unsigned long size = arm_decode_field (given, 19, 20);
5779 if ((size == 0) || (size == 3))
78933a4a 5780 return true;
14925797 5781 else
78933a4a 5782 return false;
14925797
AV		 5783 }
5784
56858bea
AV		 5785 case MVE_VMAXA:
5786 case MVE_VMINA:
5787 case MVE_VMAXV:
5788 case MVE_VMAXAV:
5789 case MVE_VMINV:
5790 case MVE_VMINAV:
ed63aa17
AV		 5791 case MVE_VQRSHL_T2:
5792 case MVE_VQSHL_T1:
5793 case MVE_VRSHL_T2:
5794 case MVE_VSHL_T2:
5795 case MVE_VSHLL_T2:
d3b63143 5796 case MVE_VADDV:
14925797
AV		 5797 case MVE_VMOVN:
5798 case MVE_VQMOVUN:
5799 case MVE_VQMOVN:
5800 if (arm_decode_field (given, 18, 19) == 3)
78933a4a 5801 return true;
14925797 5802 else
78933a4a 5803 return false;
14925797 5804
d3b63143
AV		 5805 case MVE_VMLSLDAV:
5806 case MVE_VRMLSLDAVH:
5807 case MVE_VMLALDAV:
5808 case MVE_VADDLV:
5809 if (arm_decode_field (given, 20, 22) == 7)
78933a4a 5810 return true;
d3b63143 5811 else
78933a4a 5812 return false;
d3b63143
AV		 5813
5814 case MVE_VRMLALDAVH:
5815 if ((arm_decode_field (given, 20, 22) & 6) == 6)
78933a4a 5816 return true;
d3b63143 5817 else
78933a4a 5818 return false;
d3b63143 5819
1c8f2df8
AV		 5820 case MVE_VDWDUP:
5821 case MVE_VIWDUP:
5822 if ((arm_decode_field (given, 20, 21) == 3)
5823 || (arm_decode_field (given, 1, 3) == 7))
78933a4a 5824 return true;
1c8f2df8 5825 else
78933a4a 5826 return false;
1c8f2df8 5827
ed63aa17
AV		 5828
5829 case MVE_VSHLL_T1:
5830 if (arm_decode_field (given, 16, 18) == 0)
5831 {
5832 unsigned long sz = arm_decode_field (given, 19, 20);
5833
5834 if ((sz == 1) || (sz == 2))
78933a4a 5835 return true;
ed63aa17 5836 else
78933a4a 5837 return false;
ed63aa17
AV		 5838 }
5839 else
78933a4a 5840 return false;
ed63aa17
AV		 5841
5842 case MVE_VQSHL_T2:
5843 case MVE_VQSHLU_T3:
5844 case MVE_VRSHR:
5845 case MVE_VSHL_T1:
5846 case MVE_VSHR:
5847 case MVE_VSLI:
5848 case MVE_VSRI:
5849 if (arm_decode_field (given, 19, 21) == 0)
78933a4a 5850 return true;
ed63aa17 5851 else
78933a4a 5852 return false;
ed63aa17 5853
e523f101
AV		 5854 case MVE_VCTP:
5855 if (arm_decode_field (given, 16, 19) == 0xf)
78933a4a 5856 return true;
e523f101 5857 else
78933a4a 5858 return false;
e523f101 5859
23d00a41
SD		 5860 case MVE_ASRLI:
5861 case MVE_ASRL:
5862 case MVE_LSLLI:
5863 case MVE_LSLL:
5864 case MVE_LSRL:
5865 case MVE_SQRSHRL:
5866 case MVE_SQSHLL:
5867 case MVE_SRSHRL:
5868 case MVE_UQRSHLL:
5869 case MVE_UQSHLL:
5870 case MVE_URSHRL:
5871 if (arm_decode_field (given, 9, 11) == 0x7)
78933a4a 5872 return true;
23d00a41 5873 else
78933a4a 5874 return false;
23d00a41 5875
e39c1607
SD		 5876 case MVE_CSINC:
5877 case MVE_CSINV:
5878 {
5879 unsigned long rm, rn;
5880 rm = arm_decode_field (given, 0, 3);
5881 rn = arm_decode_field (given, 16, 19);
5882 /* CSET/CSETM. */
5883 if (rm == 0xf && rn == 0xf)
78933a4a 5884 return true;
e39c1607
SD		 5885 /* CINC/CINV. */
5886 else if (rn == rm && rn != 0xf)
78933a4a 5887 return true;
e39c1607
SD		 5888 }
5889 /* Fall through. */
5890 case MVE_CSEL:
5891 case MVE_CSNEG:
5892 if (arm_decode_field (given, 0, 3) == 0xd)
78933a4a 5893 return true;
e39c1607
SD		 5894 /* CNEG. */
5895 else if (matched_insn == MVE_CSNEG)
5896 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
78933a4a
AM		 5897 return true;
5898 return false;
e39c1607 5899
143275ea 5900 default:
66dcaa5d
AV		 5901 case MVE_VADD_FP_T1:
5902 case MVE_VADD_FP_T2:
5903 case MVE_VADD_VEC_T1:
78933a4a 5904 return false;
143275ea
AV		 5905
5906 }
73cd51e5
AV		 5907}
5908
aef6d006
AV		 5909static void
5910print_mve_vld_str_addr (struct disassemble_info *info,
5911 unsigned long given,
5912 enum mve_instructions matched_insn)
5913{
5914 void *stream = info->stream;
5915 fprintf_ftype func = info->fprintf_func;
5916
5917 unsigned long p, w, gpr, imm, add, mod_imm;
5918
5919 imm = arm_decode_field (given, 0, 6);
5920 mod_imm = imm;
5921
5922 switch (matched_insn)
5923 {
5924 case MVE_VLDRB_T1:
5925 case MVE_VSTRB_T1:
5926 gpr = arm_decode_field (given, 16, 18);
5927 break;
5928
5929 case MVE_VLDRH_T2:
5930 case MVE_VSTRH_T2:
5931 gpr = arm_decode_field (given, 16, 18);
5932 mod_imm = imm << 1;
5933 break;
5934
5935 case MVE_VLDRH_T6:
5936 case MVE_VSTRH_T6:
5937 gpr = arm_decode_field (given, 16, 19);
5938 mod_imm = imm << 1;
5939 break;
5940
5941 case MVE_VLDRW_T7:
5942 case MVE_VSTRW_T7:
5943 gpr = arm_decode_field (given, 16, 19);
5944 mod_imm = imm << 2;
5945 break;
5946
5947 case MVE_VLDRB_T5:
5948 case MVE_VSTRB_T5:
5949 gpr = arm_decode_field (given, 16, 19);
5950 break;
5951
5952 default:
5953 return;
5954 }
5955
5956 p = arm_decode_field (given, 24, 24);
5957 w = arm_decode_field (given, 21, 21);
5958
5959 add = arm_decode_field (given, 23, 23);
5960
5961 char * add_sub;
5962
5963 /* Don't print anything for '+' as it is implied. */
5964 if (add == 1)
5965 add_sub = "";
5966 else
5967 add_sub = "-";
5968
5969 if (p == 1)
5970 {
5971 /* Offset mode. */
5972 if (w == 0)
5973 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5974 /* Pre-indexed mode. */
5975 else
5976 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5977 }
5978 else if ((p == 0) && (w == 1))
5979 /* Post-index mode. */
5980 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5981}
5982
73cd51e5
AV		 5983/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5984 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5985 this encoding is undefined. */
5986
78933a4a 5987static bool
73cd51e5
AV		 5988is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5989 enum mve_undefined *undefined_code)
5990{
5991 *undefined_code = UNDEF_NONE;
5992
9743db03
AV		 5993 switch (matched_insn)
5994 {
5995 case MVE_VDUP:
5996 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5997 {
5998 *undefined_code = UNDEF_SIZE_3;
78933a4a 5999 return true;
9743db03
AV		 6000 }
6001 else
78933a4a 6002 return false;
9743db03 6003
14b456f2
AV		 6004 case MVE_VQADD_T1:
6005 case MVE_VQSUB_T1:
f49bb598 6006 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6007 case MVE_VABD_VEC:
6008 case MVE_VADD_VEC_T1:
6009 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6010 case MVE_VQDMULH_T1:
6011 case MVE_VQRDMULH_T2:
9743db03
AV		 6012 case MVE_VRHADD:
6013 case MVE_VHADD_T1:
6014 case MVE_VHSUB_T1:
6015 if (arm_decode_field (given, 20, 21) == 3)
6016 {
6017 *undefined_code = UNDEF_SIZE_3;
78933a4a 6018 return true;
9743db03
AV		 6019 }
6020 else
78933a4a 6021 return false;
9743db03 6022
aef6d006
AV		 6023 case MVE_VLDRB_T1:
6024 if (arm_decode_field (given, 7, 8) == 3)
6025 {
6026 *undefined_code = UNDEF_SIZE_3;
78933a4a 6027 return true;
aef6d006
AV		 6028 }
6029 else
78933a4a 6030 return false;
aef6d006
AV		 6031
6032 case MVE_VLDRH_T2:
6033 if (arm_decode_field (given, 7, 8) <= 1)
6034 {
6035 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6036 return true;
aef6d006
AV		 6037 }
6038 else
78933a4a 6039 return false;
aef6d006
AV		 6040
6041 case MVE_VSTRB_T1:
6042 if ((arm_decode_field (given, 7, 8) == 0))
6043 {
6044 *undefined_code = UNDEF_SIZE_0;
78933a4a 6045 return true;
aef6d006
AV		 6046 }
6047 else
78933a4a 6048 return false;
aef6d006
AV		 6049
6050 case MVE_VSTRH_T2:
6051 if ((arm_decode_field (given, 7, 8) <= 1))
6052 {
6053 *undefined_code = UNDEF_SIZE_LE_1;
78933a4a 6054 return true;
aef6d006
AV		 6055 }
6056 else
78933a4a 6057 return false;
aef6d006 6058
ef1576a1
AV		 6059 case MVE_VLDRB_GATHER_T1:
6060 if (arm_decode_field (given, 7, 8) == 3)
6061 {
6062 *undefined_code = UNDEF_SIZE_3;
78933a4a 6063 return true;
ef1576a1
AV		 6064 }
6065 else if ((arm_decode_field (given, 28, 28) == 0)
6066 && (arm_decode_field (given, 7, 8) == 0))
6067 {
6068 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
78933a4a 6069 return true;
ef1576a1
AV		 6070 }
6071 else
78933a4a 6072 return false;
ef1576a1
AV		 6073
6074 case MVE_VLDRH_GATHER_T2:
6075 if (arm_decode_field (given, 7, 8) == 3)
6076 {
6077 *undefined_code = UNDEF_SIZE_3;
78933a4a 6078 return true;
ef1576a1
AV		 6079 }
6080 else if ((arm_decode_field (given, 28, 28) == 0)
6081 && (arm_decode_field (given, 7, 8) == 1))
6082 {
6083 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
78933a4a 6084 return true;
ef1576a1
AV		 6085 }
6086 else if (arm_decode_field (given, 7, 8) == 0)
6087 {
6088 *undefined_code = UNDEF_SIZE_0;
78933a4a 6089 return true;
ef1576a1
AV		 6090 }
6091 else
78933a4a 6092 return false;
ef1576a1
AV		 6093
6094 case MVE_VLDRW_GATHER_T3:
6095 if (arm_decode_field (given, 7, 8) != 2)
6096 {
6097 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6098 return true;
ef1576a1
AV		 6099 }
6100 else if (arm_decode_field (given, 28, 28) == 0)
6101 {
6102 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6103 return true;
ef1576a1
AV		 6104 }
6105 else
78933a4a 6106 return false;
ef1576a1
AV		 6107
6108 case MVE_VLDRD_GATHER_T4:
6109 if (arm_decode_field (given, 7, 8) != 3)
6110 {
6111 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6112 return true;
ef1576a1
AV		 6113 }
6114 else if (arm_decode_field (given, 28, 28) == 0)
6115 {
6116 *undefined_code = UNDEF_NOT_UNSIGNED;
78933a4a 6117 return true;
ef1576a1
AV		 6118 }
6119 else
78933a4a 6120 return false;
ef1576a1
AV		 6121
6122 case MVE_VSTRB_SCATTER_T1:
6123 if (arm_decode_field (given, 7, 8) == 3)
6124 {
6125 *undefined_code = UNDEF_SIZE_3;
78933a4a 6126 return true;
ef1576a1
AV		 6127 }
6128 else
78933a4a 6129 return false;
ef1576a1
AV		 6130
6131 case MVE_VSTRH_SCATTER_T2:
6132 {
6133 unsigned long size = arm_decode_field (given, 7, 8);
6134 if (size == 3)
6135 {
6136 *undefined_code = UNDEF_SIZE_3;
78933a4a 6137 return true;
ef1576a1
AV		 6138 }
6139 else if (size == 0)
6140 {
6141 *undefined_code = UNDEF_SIZE_0;
78933a4a 6142 return true;
ef1576a1
AV		 6143 }
6144 else
78933a4a 6145 return false;
ef1576a1
AV		 6146 }
6147
6148 case MVE_VSTRW_SCATTER_T3:
6149 if (arm_decode_field (given, 7, 8) != 2)
6150 {
6151 *undefined_code = UNDEF_SIZE_NOT_2;
78933a4a 6152 return true;
ef1576a1
AV		 6153 }
6154 else
78933a4a 6155 return false;
ef1576a1
AV		 6156
6157 case MVE_VSTRD_SCATTER_T4:
6158 if (arm_decode_field (given, 7, 8) != 3)
6159 {
6160 *undefined_code = UNDEF_SIZE_NOT_3;
78933a4a 6161 return true;
ef1576a1
AV		 6162 }
6163 else
78933a4a 6164 return false;
ef1576a1 6165
bf0b396d
AV		 6166 case MVE_VCVT_FP_FIX_VEC:
6167 {
6168 unsigned long imm6 = arm_decode_field (given, 16, 21);
6169 if ((imm6 & 0x20) == 0)
6170 {
6171 *undefined_code = UNDEF_VCVT_IMM6;
78933a4a 6172 return true;
bf0b396d
AV		 6173 }
6174
6175 if ((arm_decode_field (given, 9, 9) == 0)
6176 && ((imm6 & 0x30) == 0x20))
6177 {
6178 *undefined_code = UNDEF_VCVT_FSI_IMM6;
78933a4a 6179 return true;
bf0b396d
AV		 6180 }
6181
78933a4a 6182 return false;
bf0b396d
AV		 6183 }
6184
f49bb598 6185 case MVE_VNEG_FP:
66dcaa5d 6186 case MVE_VABS_FP:
bf0b396d
AV		 6187 case MVE_VCVT_BETWEEN_FP_INT:
6188 case MVE_VCVT_FROM_FP_TO_INT:
6189 {
6190 unsigned long size = arm_decode_field (given, 18, 19);
6191 if (size == 0)
6192 {
6193 *undefined_code = UNDEF_SIZE_0;
78933a4a 6194 return true;
bf0b396d
AV		 6195 }
6196 else if (size == 3)
6197 {
6198 *undefined_code = UNDEF_SIZE_3;
78933a4a 6199 return true;
bf0b396d
AV		 6200 }
6201 else
78933a4a 6202 return false;
bf0b396d
AV		 6203 }
6204
c507f10b
AV		 6205 case MVE_VMOV_VEC_LANE_TO_GP:
6206 {
6207 unsigned long op1 = arm_decode_field (given, 21, 22);
6208 unsigned long op2 = arm_decode_field (given, 5, 6);
6209 unsigned long u = arm_decode_field (given, 23, 23);
6210
6211 if ((op2 == 0) && (u == 1))
6212 {
6213 if ((op1 == 0) || (op1 == 1))
6214 {
6215 *undefined_code = UNDEF_BAD_U_OP1_OP2;
78933a4a 6216 return true;
c507f10b
AV		 6217 }
6218 else
78933a4a 6219 return false;
c507f10b
AV		 6220 }
6221 else if (op2 == 2)
6222 {
6223 if ((op1 == 0) || (op1 == 1))
6224 {
6225 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6226 return true;
c507f10b
AV		 6227 }
6228 else
78933a4a 6229 return false;
c507f10b
AV		 6230 }
6231
78933a4a 6232 return false;
c507f10b
AV		 6233 }
6234
6235 case MVE_VMOV_GP_TO_VEC_LANE:
6236 if (arm_decode_field (given, 5, 6) == 2)
6237 {
6238 unsigned long op1 = arm_decode_field (given, 21, 22);
6239 if ((op1 == 0) || (op1 == 1))
6240 {
6241 *undefined_code = UNDEF_BAD_OP1_OP2;
78933a4a 6242 return true;
c507f10b
AV		 6243 }
6244 else
78933a4a 6245 return false;
c507f10b
AV		 6246 }
6247 else
78933a4a 6248 return false;
c507f10b 6249
c4a23bf8
SP		 6250 case MVE_VMOV_VEC_TO_VEC:
6251 if ((arm_decode_field (given, 5, 5) == 1)
6252 || (arm_decode_field (given, 22, 22) == 1))
78933a4a
AM		 6253 return true;
6254 return false;
c4a23bf8 6255
c507f10b
AV		 6256 case MVE_VMOV_IMM_TO_VEC:
6257 if (arm_decode_field (given, 5, 5) == 0)
6258 {
6259 unsigned long cmode = arm_decode_field (given, 8, 11);
6260
6261 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6262 {
6263 *undefined_code = UNDEF_OP_0_BAD_CMODE;
78933a4a 6264 return true;
c507f10b
AV		 6265 }
6266 else
78933a4a 6267 return false;
c507f10b
AV		 6268 }
6269 else
78933a4a 6270 return false;
c507f10b 6271
ed63aa17 6272 case MVE_VSHLL_T2:
14925797
AV		 6273 case MVE_VMOVN:
6274 if (arm_decode_field (given, 18, 19) == 2)
6275 {
6276 *undefined_code = UNDEF_SIZE_2;
78933a4a 6277 return true;
14925797
AV		 6278 }
6279 else
78933a4a 6280 return false;
14925797 6281
d3b63143
AV		 6282 case MVE_VRMLALDAVH:
6283 case MVE_VMLADAV_T1:
6284 case MVE_VMLADAV_T2:
6285 case MVE_VMLALDAV:
6286 if ((arm_decode_field (given, 28, 28) == 1)
6287 && (arm_decode_field (given, 12, 12) == 1))
6288 {
6289 *undefined_code = UNDEF_XCHG_UNS;
78933a4a 6290 return true;
d3b63143
AV		 6291 }
6292 else
78933a4a 6293 return false;
d3b63143 6294
ed63aa17
AV		 6295 case MVE_VQSHRN:
6296 case MVE_VQSHRUN:
6297 case MVE_VSHLL_T1:
6298 case MVE_VSHRN:
6299 {
6300 unsigned long sz = arm_decode_field (given, 19, 20);
6301 if (sz == 1)
78933a4a 6302 return false;
ed63aa17 6303 else if ((sz & 2) == 2)
78933a4a 6304 return false;
ed63aa17
AV		 6305 else
6306 {
6307 *undefined_code = UNDEF_SIZE;
78933a4a 6308 return true;
ed63aa17
AV		 6309 }
6310 }
6311 break;
6312
6313 case MVE_VQSHL_T2:
6314 case MVE_VQSHLU_T3:
6315 case MVE_VRSHR:
6316 case MVE_VSHL_T1:
6317 case MVE_VSHR:
6318 case MVE_VSLI:
6319 case MVE_VSRI:
6320 {
6321 unsigned long sz = arm_decode_field (given, 19, 21);
6322 if ((sz & 7) == 1)
78933a4a 6323 return false;
ed63aa17 6324 else if ((sz & 6) == 2)
78933a4a 6325 return false;
ed63aa17 6326 else if ((sz & 4) == 4)
78933a4a 6327 return false;
ed63aa17
AV		 6328 else
6329 {
6330 *undefined_code = UNDEF_SIZE;
78933a4a 6331 return true;
ed63aa17
AV		 6332 }
6333 }
6334
6335 case MVE_VQRSHRN:
6336 case MVE_VQRSHRUN:
6337 if (arm_decode_field (given, 19, 20) == 0)
6338 {
6339 *undefined_code = UNDEF_SIZE_0;
78933a4a 6340 return true;
ed63aa17
AV		 6341 }
6342 else
78933a4a 6343 return false;
ed63aa17 6344
66dcaa5d
AV		 6345 case MVE_VABS_VEC:
6346 if (arm_decode_field (given, 18, 19) == 3)
6347 {
6348 *undefined_code = UNDEF_SIZE_3;
78933a4a 6349 return true;
66dcaa5d
AV		 6350 }
6351 else
78933a4a 6352 return false;
66dcaa5d 6353
14b456f2
AV		 6354 case MVE_VQNEG:
6355 case MVE_VQABS:
f49bb598 6356 case MVE_VNEG_VEC:
e523f101
AV		 6357 case MVE_VCLS:
6358 case MVE_VCLZ:
6359 if (arm_decode_field (given, 18, 19) == 3)
6360 {
6361 *undefined_code = UNDEF_SIZE_3;
78933a4a 6362 return true;
e523f101
AV		 6363 }
6364 else
78933a4a 6365 return false;
e523f101 6366
14b456f2
AV		 6367 case MVE_VREV16:
6368 if (arm_decode_field (given, 18, 19) == 0)
78933a4a 6369 return false;
14b456f2
AV		 6370 else
6371 {
6372 *undefined_code = UNDEF_SIZE_NOT_0;
78933a4a 6373 return true;
14b456f2
AV		 6374 }
6375
6376 case MVE_VREV32:
6377 {
6378 unsigned long size = arm_decode_field (given, 18, 19);
6379 if ((size & 2) == 2)
6380 {
6381 *undefined_code = UNDEF_SIZE_2;
78933a4a 6382 return true;
14b456f2
AV		 6383 }
6384 else
78933a4a 6385 return false;
14b456f2
AV		 6386 }
6387
6388 case MVE_VREV64:
6389 if (arm_decode_field (given, 18, 19) != 3)
78933a4a 6390 return false;
14b456f2
AV		 6391 else
6392 {
6393 *undefined_code = UNDEF_SIZE_3;
78933a4a 6394 return true;
14b456f2
AV		 6395 }
6396
9743db03 6397 default:
78933a4a 6398 return false;
9743db03 6399 }
73cd51e5
AV		 6400}
6401
6402/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6403 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6404 why this encoding is unpredictable. */
6405
78933a4a 6406static bool
73cd51e5
AV		 6407is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6408 enum mve_unpredictable *unpredictable_code)
6409{
6410 *unpredictable_code = UNPRED_NONE;
6411
143275ea
AV		 6412 switch (matched_insn)
6413 {
6414 case MVE_VCMP_FP_T2:
6415 case MVE_VPT_FP_T2:
6416 if ((arm_decode_field (given, 12, 12) == 0)
6417 && (arm_decode_field (given, 5, 5) == 1))
6418 {
6419 *unpredictable_code = UNPRED_FCA_0_FCB_1;
78933a4a 6420 return true;
143275ea
AV		 6421 }
6422 else
78933a4a 6423 return false;
73cd51e5 6424
143275ea
AV		 6425 case MVE_VPT_VEC_T4:
6426 case MVE_VPT_VEC_T5:
6427 case MVE_VPT_VEC_T6:
6428 case MVE_VCMP_VEC_T4:
6429 case MVE_VCMP_VEC_T5:
6430 case MVE_VCMP_VEC_T6:
6431 if (arm_decode_field (given, 0, 3) == 0xd)
6432 {
6433 *unpredictable_code = UNPRED_R13;
78933a4a 6434 return true;
143275ea
AV		 6435 }
6436 else
78933a4a 6437 return false;
c1e26897 6438
9743db03
AV		 6439 case MVE_VDUP:
6440 {
6441 unsigned long gpr = arm_decode_field (given, 12, 15);
6442 if (gpr == 0xd)
6443 {
6444 *unpredictable_code = UNPRED_R13;
78933a4a 6445 return true;
9743db03
AV		 6446 }
6447 else if (gpr == 0xf)
6448 {
6449 *unpredictable_code = UNPRED_R15;
78933a4a 6450 return true;
9743db03
AV		 6451 }
6452
78933a4a 6453 return false;
9743db03
AV		 6454 }
6455
14b456f2
AV		 6456 case MVE_VQADD_T2:
6457 case MVE_VQSUB_T2:
f49bb598
AV		 6458 case MVE_VMUL_FP_T2:
6459 case MVE_VMUL_VEC_T2:
56858bea 6460 case MVE_VMLA:
e523f101 6461 case MVE_VBRSR:
66dcaa5d
AV		 6462 case MVE_VADD_FP_T2:
6463 case MVE_VSUB_FP_T2:
6464 case MVE_VADD_VEC_T2:
6465 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6466 case MVE_VQRSHL_T2:
6467 case MVE_VQSHL_T1:
6468 case MVE_VRSHL_T2:
6469 case MVE_VSHL_T2:
6470 case MVE_VSHLC:
d3b63143
AV		 6471 case MVE_VQDMLAH:
6472 case MVE_VQRDMLAH:
6473 case MVE_VQDMLASH:
6474 case MVE_VQRDMLASH:
6475 case MVE_VQDMULH_T3:
6476 case MVE_VQRDMULH_T4:
6477 case MVE_VMLAS:
9743db03
AV		 6478 case MVE_VFMA_FP_SCALAR:
6479 case MVE_VFMAS_FP_SCALAR:
6480 case MVE_VHADD_T2:
6481 case MVE_VHSUB_T2:
6482 {
6483 unsigned long gpr = arm_decode_field (given, 0, 3);
6484 if (gpr == 0xd)
6485 {
6486 *unpredictable_code = UNPRED_R13;
78933a4a 6487 return true;
9743db03
AV		 6488 }
6489 else if (gpr == 0xf)
6490 {
6491 *unpredictable_code = UNPRED_R15;
78933a4a 6492 return true;
9743db03
AV		 6493 }
6494
78933a4a 6495 return false;
9743db03
AV		 6496 }
6497
04d54ace
AV		 6498 case MVE_VLD2:
6499 case MVE_VST2:
6500 {
6501 unsigned long rn = arm_decode_field (given, 16, 19);
6502
6503 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6504 {
6505 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6506 return true;
04d54ace
AV		 6507 }
6508
6509 if (rn == 0xf)
6510 {
6511 *unpredictable_code = UNPRED_R15;
78933a4a 6512 return true;
04d54ace
AV		 6513 }
6514
6515 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6516 {
6517 *unpredictable_code = UNPRED_Q_GT_6;
78933a4a 6518 return true;
04d54ace
AV		 6519 }
6520 else
78933a4a 6521 return false;
04d54ace
AV		 6522 }
6523
6524 case MVE_VLD4:
6525 case MVE_VST4:
6526 {
6527 unsigned long rn = arm_decode_field (given, 16, 19);
6528
6529 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6530 {
6531 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6532 return true;
04d54ace
AV		 6533 }
6534
6535 if (rn == 0xf)
6536 {
6537 *unpredictable_code = UNPRED_R15;
78933a4a 6538 return true;
04d54ace
AV		 6539 }
6540
6541 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6542 {
6543 *unpredictable_code = UNPRED_Q_GT_4;
78933a4a 6544 return true;
04d54ace
AV		 6545 }
6546 else
78933a4a 6547 return false;
04d54ace
AV		 6548 }
6549
aef6d006
AV		 6550 case MVE_VLDRB_T5:
6551 case MVE_VLDRH_T6:
6552 case MVE_VLDRW_T7:
6553 case MVE_VSTRB_T5:
6554 case MVE_VSTRH_T6:
6555 case MVE_VSTRW_T7:
6556 {
6557 unsigned long rn = arm_decode_field (given, 16, 19);
6558
6559 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6560 {
6561 *unpredictable_code = UNPRED_R13_AND_WB;
78933a4a 6562 return true;
aef6d006
AV		 6563 }
6564 else if (rn == 0xf)
6565 {
6566 *unpredictable_code = UNPRED_R15;
78933a4a 6567 return true;
aef6d006
AV		 6568 }
6569 else
78933a4a 6570 return false;
aef6d006
AV		 6571 }
6572
ef1576a1
AV		 6573 case MVE_VLDRB_GATHER_T1:
6574 if (arm_decode_field (given, 0, 0) == 1)
6575 {
6576 *unpredictable_code = UNPRED_OS;
78933a4a 6577 return true;
ef1576a1
AV		 6578 }
6579
6580 /* fall through. */
6581 /* To handle common code with T2-T4 variants. */
6582 case MVE_VLDRH_GATHER_T2:
6583 case MVE_VLDRW_GATHER_T3:
6584 case MVE_VLDRD_GATHER_T4:
6585 {
6586 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6587 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6588
6589 if (qd == qm)
6590 {
6591 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6592 return true;
ef1576a1
AV		 6593 }
6594
6595 if (arm_decode_field (given, 16, 19) == 0xf)
6596 {
6597 *unpredictable_code = UNPRED_R15;
78933a4a 6598 return true;
ef1576a1
AV		 6599 }
6600
78933a4a 6601 return false;
ef1576a1
AV		 6602 }
6603
6604 case MVE_VLDRW_GATHER_T5:
6605 case MVE_VLDRD_GATHER_T6:
6606 {
6607 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6608 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6609
6610 if (qd == qm)
6611 {
6612 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6613 return true;
ef1576a1
AV		 6614 }
6615 else
78933a4a 6616 return false;
ef1576a1
AV		 6617 }
6618
6619 case MVE_VSTRB_SCATTER_T1:
6620 if (arm_decode_field (given, 16, 19) == 0xf)
6621 {
6622 *unpredictable_code = UNPRED_R15;
78933a4a 6623 return true;
ef1576a1
AV		 6624 }
6625 else if (arm_decode_field (given, 0, 0) == 1)
6626 {
6627 *unpredictable_code = UNPRED_OS;
78933a4a 6628 return true;
ef1576a1
AV		 6629 }
6630 else
78933a4a 6631 return false;
ef1576a1
AV		 6632
6633 case MVE_VSTRH_SCATTER_T2:
6634 case MVE_VSTRW_SCATTER_T3:
6635 case MVE_VSTRD_SCATTER_T4:
6636 if (arm_decode_field (given, 16, 19) == 0xf)
6637 {
6638 *unpredictable_code = UNPRED_R15;
78933a4a 6639 return true;
ef1576a1
AV		 6640 }
6641 else
78933a4a 6642 return false;
ef1576a1 6643
c507f10b
AV		 6644 case MVE_VMOV2_VEC_LANE_TO_GP:
6645 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6646 case MVE_VCVT_BETWEEN_FP_INT:
6647 case MVE_VCVT_FROM_FP_TO_INT:
6648 {
6649 unsigned long rt = arm_decode_field (given, 0, 3);
6650 unsigned long rt2 = arm_decode_field (given, 16, 19);
6651
6652 if ((rt == 0xd) || (rt2 == 0xd))
6653 {
6654 *unpredictable_code = UNPRED_R13;
78933a4a 6655 return true;
bf0b396d
AV		 6656 }
6657 else if ((rt == 0xf) || (rt2 == 0xf))
6658 {
6659 *unpredictable_code = UNPRED_R15;
78933a4a 6660 return true;
bf0b396d 6661 }
e683cb41 6662 else if (rt == rt2 && matched_insn != MVE_VMOV2_GP_TO_VEC_LANE)
bf0b396d
AV		 6663 {
6664 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
78933a4a 6665 return true;
bf0b396d
AV		 6666 }
6667
78933a4a 6668 return false;
bf0b396d
AV		 6669 }
6670
56858bea
AV		 6671 case MVE_VMAXV:
6672 case MVE_VMAXAV:
6673 case MVE_VMAXNMV_FP:
6674 case MVE_VMAXNMAV_FP:
6675 case MVE_VMINNMV_FP:
6676 case MVE_VMINNMAV_FP:
6677 case MVE_VMINV:
6678 case MVE_VMINAV:
66dcaa5d 6679 case MVE_VABAV:
c507f10b
AV		 6680 case MVE_VMOV_HFP_TO_GP:
6681 case MVE_VMOV_GP_TO_VEC_LANE:
6682 case MVE_VMOV_VEC_LANE_TO_GP:
6683 {
6684 unsigned long rda = arm_decode_field (given, 12, 15);
6685 if (rda == 0xd)
6686 {
6687 *unpredictable_code = UNPRED_R13;
78933a4a 6688 return true;
c507f10b
AV		 6689 }
6690 else if (rda == 0xf)
6691 {
6692 *unpredictable_code = UNPRED_R15;
78933a4a 6693 return true;
c507f10b
AV		 6694 }
6695
78933a4a 6696 return false;
c507f10b
AV		 6697 }
6698
14925797
AV		 6699 case MVE_VMULL_INT:
6700 {
6701 unsigned long Qd;
6702 unsigned long Qm;
6703 unsigned long Qn;
6704
6705 if (arm_decode_field (given, 20, 21) == 2)
6706 {
6707 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6708 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6709 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6710
6711 if ((Qd == Qn) || (Qd == Qm))
6712 {
6713 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6714 return true;
14925797
AV		 6715 }
6716 else
78933a4a 6717 return false;
14925797
AV		 6718 }
6719 else
78933a4a 6720 return false;
14925797
AV		 6721 }
6722
897b9bbc 6723 case MVE_VCMUL_FP:
14925797
AV		 6724 case MVE_VQDMULL_T1:
6725 {
6726 unsigned long Qd;
6727 unsigned long Qm;
6728 unsigned long Qn;
6729
6730 if (arm_decode_field (given, 28, 28) == 1)
6731 {
6732 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6733 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6734 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6735
6736 if ((Qd == Qn) || (Qd == Qm))
6737 {
6738 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6739 return true;
14925797
AV		 6740 }
6741 else
78933a4a 6742 return false;
14925797
AV		 6743 }
6744 else
78933a4a 6745 return false;
14925797
AV		 6746 }
6747
6748 case MVE_VQDMULL_T2:
6749 {
6750 unsigned long gpr = arm_decode_field (given, 0, 3);
6751 if (gpr == 0xd)
6752 {
6753 *unpredictable_code = UNPRED_R13;
78933a4a 6754 return true;
14925797
AV		 6755 }
6756 else if (gpr == 0xf)
6757 {
6758 *unpredictable_code = UNPRED_R15;
78933a4a 6759 return true;
14925797
AV		 6760 }
6761
6762 if (arm_decode_field (given, 28, 28) == 1)
6763 {
6764 unsigned long Qd
6765 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6766 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6767
a9d96ab9 6768 if (Qd == Qn)
14925797
AV		 6769 {
6770 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6771 return true;
14925797
AV		 6772 }
6773 else
78933a4a 6774 return false;
14925797
AV		 6775 }
6776
78933a4a 6777 return false;
14925797
AV		 6778 }
6779
d3b63143
AV		 6780 case MVE_VMLSLDAV:
6781 case MVE_VRMLSLDAVH:
6782 case MVE_VMLALDAV:
6783 case MVE_VADDLV:
6784 if (arm_decode_field (given, 20, 22) == 6)
6785 {
6786 *unpredictable_code = UNPRED_R13;
78933a4a 6787 return true;
d3b63143
AV		 6788 }
6789 else
78933a4a 6790 return false;
d3b63143 6791
1c8f2df8
AV		 6792 case MVE_VDWDUP:
6793 case MVE_VIWDUP:
6794 if (arm_decode_field (given, 1, 3) == 6)
6795 {
6796 *unpredictable_code = UNPRED_R13;
78933a4a 6797 return true;
1c8f2df8
AV		 6798 }
6799 else
78933a4a 6800 return false;
1c8f2df8 6801
897b9bbc
AV		 6802 case MVE_VCADD_VEC:
6803 case MVE_VHCADD:
6804 {
6805 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6806 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6807 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6808 {
6809 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
78933a4a 6810 return true;
897b9bbc
AV		 6811 }
6812 else
78933a4a 6813 return false;
897b9bbc
AV		 6814 }
6815
6816 case MVE_VCADD_FP:
6817 {
6818 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6819 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6820 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6821 {
6822 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6823 return true;
897b9bbc
AV		 6824 }
6825 else
78933a4a 6826 return false;
897b9bbc
AV		 6827 }
6828
6829 case MVE_VCMLA_FP:
6830 {
6831 unsigned long Qda;
6832 unsigned long Qm;
6833 unsigned long Qn;
6834
6835 if (arm_decode_field (given, 20, 20) == 1)
6836 {
6837 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6838 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6839 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6840
6841 if ((Qda == Qn) || (Qda == Qm))
6842 {
6843 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
78933a4a 6844 return true;
897b9bbc
AV		 6845 }
6846 else
78933a4a 6847 return false;
897b9bbc
AV		 6848 }
6849 else
78933a4a 6850 return false;
897b9bbc
AV		 6851
6852 }
6853
e523f101
AV		 6854 case MVE_VCTP:
6855 if (arm_decode_field (given, 16, 19) == 0xd)
6856 {
6857 *unpredictable_code = UNPRED_R13;
78933a4a 6858 return true;
e523f101
AV		 6859 }
6860 else
78933a4a 6861 return false;
e523f101 6862
14b456f2
AV		 6863 case MVE_VREV64:
6864 {
6865 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6866 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6867
6868 if (qd == qm)
6869 {
6870 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
78933a4a 6871 return true;
14b456f2
AV		 6872 }
6873 else
78933a4a 6874 return false;
14b456f2
AV		 6875 }
6876
23d00a41
SD		 6877 case MVE_LSLL:
6878 case MVE_LSLLI:
6879 case MVE_LSRL:
6880 case MVE_ASRL:
6881 case MVE_ASRLI:
6882 case MVE_UQSHLL:
6883 case MVE_UQRSHLL:
6884 case MVE_URSHRL:
6885 case MVE_SRSHRL:
6886 case MVE_SQSHLL:
6887 case MVE_SQRSHRL:
6888 {
6889 unsigned long gpr = arm_decode_field (given, 9, 11);
6890 gpr = ((gpr << 1) | 1);
6891 if (gpr == 0xd)
6892 {
6893 *unpredictable_code = UNPRED_R13;
78933a4a 6894 return true;
23d00a41
SD		 6895 }
6896 else if (gpr == 0xf)
6897 {
6898 *unpredictable_code = UNPRED_R15;
78933a4a 6899 return true;
23d00a41
SD		 6900 }
6901
78933a4a 6902 return false;
23d00a41
SD		 6903 }
6904
143275ea 6905 default:
78933a4a 6906 return false;
143275ea
AV		 6907 }
6908}
c1e26897 6909
c507f10b
AV		 6910static void
6911print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6912{
6913 unsigned long op1 = arm_decode_field (given, 21, 22);
6914 unsigned long op2 = arm_decode_field (given, 5, 6);
6915 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6916 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6917 void *stream = info->stream;
6918 fprintf_ftype func = info->fprintf_func;
6919
6920 if ((op1 & 0x2) == 0x2)
6921 {
43dd7626 6922 index_operand = op2;
c507f10b
AV		 6923 esize = 8;
6924 }
6925 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6926 {
43dd7626 6927 index_operand = op2 >> 1;
c507f10b
AV		 6928 esize = 16;
6929 }
6930 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6931 {
43dd7626 6932 index_operand = 0;
c507f10b
AV		 6933 esize = 32;
6934 }
6935 else
6936 {
6937 func (stream, "<undefined index>");
6938 return;
6939 }
6940
6941 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6942 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6943
6944 func (stream, "%lu", idx);
6945}
6946
6947/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6948 in length and integer of floating-point type. */
6949static void
6950print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6951 unsigned int ibit_loc, const struct mopcode32 *insn)
6952{
6953 int bits = 0;
6954 int cmode = (given >> 8) & 0xf;
6955 int op = (given >> 5) & 0x1;
6956 unsigned long value = 0, hival = 0;
6957 unsigned shift;
6958 int size = 0;
6959 int isfloat = 0;
6960 void *stream = info->stream;
6961 fprintf_ftype func = info->fprintf_func;
6962
6963 /* On Neon the 'i' bit is at bit 24, on mve it is
6964 at bit 28. */
6965 bits |= ((given >> ibit_loc) & 1) << 7;
6966 bits |= ((given >> 16) & 7) << 4;
6967 bits |= ((given >> 0) & 15) << 0;
6968
6969 if (cmode < 8)
6970 {
6971 shift = (cmode >> 1) & 3;
6972 value = (unsigned long) bits << (8 * shift);
6973 size = 32;
6974 }
6975 else if (cmode < 12)
6976 {
6977 shift = (cmode >> 1) & 1;
6978 value = (unsigned long) bits << (8 * shift);
6979 size = 16;
6980 }
6981 else if (cmode < 14)
6982 {
6983 shift = (cmode & 1) + 1;
6984 value = (unsigned long) bits << (8 * shift);
6985 value |= (1ul << (8 * shift)) - 1;
6986 size = 32;
6987 }
6988 else if (cmode == 14)
6989 {
6990 if (op)
6991 {
6992 /* Bit replication into bytes. */
6993 int ix;
6994 unsigned long mask;
6995
6996 value = 0;
6997 hival = 0;
6998 for (ix = 7; ix >= 0; ix--)
6999 {
7000 mask = ((bits >> ix) & 1) ? 0xff : 0;
7001 if (ix <= 3)
7002 value = (value << 8) | mask;
7003 else
7004 hival = (hival << 8) | mask;
7005 }
7006 size = 64;
7007 }
7008 else
7009 {
7010 /* Byte replication. */
7011 value = (unsigned long) bits;
7012 size = 8;
7013 }
7014 }
7015 else if (!op)
7016 {
7017 /* Floating point encoding. */
7018 int tmp;
7019
7020 value = (unsigned long) (bits & 0x7f) << 19;
7021 value |= (unsigned long) (bits & 0x80) << 24;
7022 tmp = bits & 0x40 ? 0x3c : 0x40;
7023 value |= (unsigned long) tmp << 24;
7024 size = 32;
7025 isfloat = 1;
7026 }
7027 else
7028 {
7029 func (stream, "<illegal constant %.8x:%x:%x>",
7030 bits, cmode, op);
7031 size = 32;
7032 return;
7033 }
7034
279edac5
AM		 7035 /* printU determines whether the immediate value should be printed as
7036 unsigned. */
c507f10b
AV		 7037 unsigned printU = 0;
7038 switch (insn->mve_op)
7039 {
7040 default:
7041 break;
279edac5 7042 /* We want this for instructions that don't have a 'signed' type. */
c507f10b
AV		 7043 case MVE_VBIC_IMM:
7044 case MVE_VORR_IMM:
7045 case MVE_VMVN_IMM:
7046 case MVE_VMOV_IMM_TO_VEC:
7047 printU = 1;
7048 break;
7049 }
7050 switch (size)
7051 {
7052 case 8:
7053 func (stream, "#%ld\t; 0x%.2lx", value, value);
7054 break;
7055
7056 case 16:
7057 func (stream,
7058 printU
7059 ? "#%lu\t; 0x%.4lx"
7060 : "#%ld\t; 0x%.4lx", value, value);
7061 break;
7062
7063 case 32:
7064 if (isfloat)
7065 {
7066 unsigned char valbytes[4];
7067 double fvalue;
7068
7069 /* Do this a byte at a time so we don't have to
7070 worry about the host's endianness. */
7071 valbytes[0] = value & 0xff;
7072 valbytes[1] = (value >> 8) & 0xff;
7073 valbytes[2] = (value >> 16) & 0xff;
7074 valbytes[3] = (value >> 24) & 0xff;
7075
7076 floatformat_to_double
7077 (& floatformat_ieee_single_little, valbytes,
7078 & fvalue);
7079
7080 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7081 value);
7082 }
7083 else
7084 func (stream,
7085 printU
7086 ? "#%lu\t; 0x%.8lx"
7087 : "#%ld\t; 0x%.8lx",
7088 (long) (((value & 0x80000000L) != 0)
7089 && !printU
7090 ? value | ~0xffffffffL : value),
7091 value);
7092 break;
7093
7094 case 64:
7095 func (stream, "#0x%.8lx%.8lx", hival, value);
7096 break;
7097
7098 default:
7099 abort ();
7100 }
7101
7102}
7103
73cd51e5
AV		 7104static void
7105print_mve_undefined (struct disassemble_info *info,
7106 enum mve_undefined undefined_code)
7107{
7108 void *stream = info->stream;
7109 fprintf_ftype func = info->fprintf_func;
7110
7111 func (stream, "\t\tundefined instruction: ");
7112
7113 switch (undefined_code)
7114 {
ed63aa17
AV		 7115 case UNDEF_SIZE:
7116 func (stream, "illegal size");
7117 break;
7118
aef6d006
AV		 7119 case UNDEF_SIZE_0:
7120 func (stream, "size equals zero");
7121 break;
7122
c507f10b
AV		 7123 case UNDEF_SIZE_2:
7124 func (stream, "size equals two");
7125 break;
7126
9743db03
AV		 7127 case UNDEF_SIZE_3:
7128 func (stream, "size equals three");
7129 break;
7130
aef6d006
AV		 7131 case UNDEF_SIZE_LE_1:
7132 func (stream, "size <= 1");
7133 break;
7134
14b456f2
AV		 7135 case UNDEF_SIZE_NOT_0:
7136 func (stream, "size not equal to 0");
7137 break;
7138
ef1576a1
AV		 7139 case UNDEF_SIZE_NOT_2:
7140 func (stream, "size not equal to 2");
7141 break;
7142
7143 case UNDEF_SIZE_NOT_3:
7144 func (stream, "size not equal to 3");
7145 break;
7146
7147 case UNDEF_NOT_UNS_SIZE_0:
7148 func (stream, "not unsigned and size = zero");
7149 break;
7150
7151 case UNDEF_NOT_UNS_SIZE_1:
7152 func (stream, "not unsigned and size = one");
7153 break;
7154
7155 case UNDEF_NOT_UNSIGNED:
7156 func (stream, "not unsigned");
7157 break;
7158
bf0b396d
AV		 7159 case UNDEF_VCVT_IMM6:
7160 func (stream, "invalid imm6");
7161 break;
7162
7163 case UNDEF_VCVT_FSI_IMM6:
7164 func (stream, "fsi = 0 and invalid imm6");
7165 break;
7166
c507f10b
AV		 7167 case UNDEF_BAD_OP1_OP2:
7168 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7169 break;
7170
7171 case UNDEF_BAD_U_OP1_OP2:
7172 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7173 break;
7174
7175 case UNDEF_OP_0_BAD_CMODE:
7176 func (stream, "op field equal 0 and bad cmode");
7177 break;
7178
d3b63143
AV		 7179 case UNDEF_XCHG_UNS:
7180 func (stream, "exchange and unsigned together");
7181 break;
7182
73cd51e5
AV		 7183 case UNDEF_NONE:
7184 break;
7185 }
7186
7187}
7188
7189static void
7190print_mve_unpredictable (struct disassemble_info *info,
7191 enum mve_unpredictable unpredict_code)
7192{
7193 void *stream = info->stream;
7194 fprintf_ftype func = info->fprintf_func;
7195
7196 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7197
7198 switch (unpredict_code)
7199 {
7200 case UNPRED_IT_BLOCK:
7201 func (stream, "mve instruction in it block");
7202 break;
7203
143275ea
AV		 7204 case UNPRED_FCA_0_FCB_1:
7205 func (stream, "condition bits, fca = 0 and fcb = 1");
7206 break;
7207
7208 case UNPRED_R13:
7209 func (stream, "use of r13 (sp)");
7210 break;
7211
9743db03
AV		 7212 case UNPRED_R15:
7213 func (stream, "use of r15 (pc)");
7214 break;
7215
04d54ace
AV		 7216 case UNPRED_Q_GT_4:
7217 func (stream, "start register block > r4");
7218 break;
7219
7220 case UNPRED_Q_GT_6:
7221 func (stream, "start register block > r6");
7222 break;
7223
7224 case UNPRED_R13_AND_WB:
7225 func (stream, "use of r13 and write back");
7226 break;
7227
ef1576a1
AV		 7228 case UNPRED_Q_REGS_EQUAL:
7229 func (stream,
7230 "same vector register used for destination and other operand");
7231 break;
7232
7233 case UNPRED_OS:
7234 func (stream, "use of offset scaled");
7235 break;
7236
bf0b396d
AV		 7237 case UNPRED_GP_REGS_EQUAL:
7238 func (stream, "same general-purpose register used for both operands");
7239 break;
7240
c507f10b
AV		 7241 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7242 func (stream, "use of identical q registers and size = 1");
7243 break;
7244
7245 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7246 func (stream, "use of identical q registers and size = 1");
7247 break;
7248
73cd51e5
AV		 7249 case UNPRED_NONE:
7250 break;
7251 }
7252}
7253
04d54ace
AV		 7254/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7255
7256static void
7257print_mve_register_blocks (struct disassemble_info *info,
7258 unsigned long given,
7259 enum mve_instructions matched_insn)
7260{
7261 void *stream = info->stream;
7262 fprintf_ftype func = info->fprintf_func;
7263
7264 unsigned long q_reg_start = arm_decode_field_multiple (given,
7265 13, 15,
7266 22, 22);
7267 switch (matched_insn)
7268 {
7269 case MVE_VLD2:
7270 case MVE_VST2:
7271 if (q_reg_start <= 6)
7272 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7273 else
7274 func (stream, "<illegal reg q%ld>", q_reg_start);
7275 break;
7276
7277 case MVE_VLD4:
7278 case MVE_VST4:
7279 if (q_reg_start <= 4)
7280 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7281 q_reg_start + 1, q_reg_start + 2,
7282 q_reg_start + 3);
7283 else
7284 func (stream, "<illegal reg q%ld>", q_reg_start);
7285 break;
7286
7287 default:
7288 break;
7289 }
7290}
7291
bf0b396d
AV		 7292static void
7293print_mve_rounding_mode (struct disassemble_info *info,
7294 unsigned long given,
7295 enum mve_instructions matched_insn)
7296{
7297 void *stream = info->stream;
7298 fprintf_ftype func = info->fprintf_func;
7299
7300 switch (matched_insn)
7301 {
7302 case MVE_VCVT_FROM_FP_TO_INT:
7303 {
7304 switch (arm_decode_field (given, 8, 9))
7305 {
7306 case 0:
7307 func (stream, "a");
7308 break;
7309
7310 case 1:
7311 func (stream, "n");
7312 break;
7313
7314 case 2:
7315 func (stream, "p");
7316 break;
7317
7318 case 3:
7319 func (stream, "m");
7320 break;
7321
7322 default:
7323 break;
7324 }
7325 }
7326 break;
7327
7328 case MVE_VRINT_FP:
7329 {
7330 switch (arm_decode_field (given, 7, 9))
7331 {
7332 case 0:
7333 func (stream, "n");
7334 break;
7335
7336 case 1:
7337 func (stream, "x");
7338 break;
7339
7340 case 2:
7341 func (stream, "a");
7342 break;
7343
7344 case 3:
7345 func (stream, "z");
7346 break;
7347
7348 case 5:
7349 func (stream, "m");
7350 break;
7351
7352 case 7:
7353 func (stream, "p");
7354
7355 case 4:
7356 case 6:
7357 default:
7358 break;
7359 }
7360 }
7361 break;
7362
7363 default:
7364 break;
7365 }
7366}
7367
7368static void
7369print_mve_vcvt_size (struct disassemble_info *info,
7370 unsigned long given,
7371 enum mve_instructions matched_insn)
7372{
7373 unsigned long mode = 0;
7374 void *stream = info->stream;
7375 fprintf_ftype func = info->fprintf_func;
7376
7377 switch (matched_insn)
7378 {
7379 case MVE_VCVT_FP_FIX_VEC:
7380 {
7381 mode = (((given & 0x200) >> 7)
7382 | ((given & 0x10000000) >> 27)
7383 | ((given & 0x100) >> 8));
7384
7385 switch (mode)
7386 {
7387 case 0:
7388 func (stream, "f16.s16");
7389 break;
7390
7391 case 1:
7392 func (stream, "s16.f16");
7393 break;
7394
7395 case 2:
7396 func (stream, "f16.u16");
7397 break;
7398
7399 case 3:
7400 func (stream, "u16.f16");
7401 break;
7402
7403 case 4:
7404 func (stream, "f32.s32");
7405 break;
7406
7407 case 5:
7408 func (stream, "s32.f32");
7409 break;
7410
7411 case 6:
7412 func (stream, "f32.u32");
7413 break;
7414
7415 case 7:
7416 func (stream, "u32.f32");
7417 break;
7418
7419 default:
7420 break;
7421 }
7422 break;
7423 }
7424 case MVE_VCVT_BETWEEN_FP_INT:
7425 {
7426 unsigned long size = arm_decode_field (given, 18, 19);
7427 unsigned long op = arm_decode_field (given, 7, 8);
7428
7429 if (size == 1)
7430 {
7431 switch (op)
7432 {
7433 case 0:
7434 func (stream, "f16.s16");
7435 break;
7436
7437 case 1:
7438 func (stream, "f16.u16");
7439 break;
7440
7441 case 2:
7442 func (stream, "s16.f16");
7443 break;
7444
7445 case 3:
7446 func (stream, "u16.f16");
7447 break;
7448
7449 default:
7450 break;
7451 }
7452 }
7453 else if (size == 2)
7454 {
7455 switch (op)
7456 {
7457 case 0:
7458 func (stream, "f32.s32");
7459 break;
7460
7461 case 1:
7462 func (stream, "f32.u32");
7463 break;
7464
7465 case 2:
7466 func (stream, "s32.f32");
7467 break;
7468
7469 case 3:
7470 func (stream, "u32.f32");
7471 break;
7472 }
7473 }
7474 }
7475 break;
7476
7477 case MVE_VCVT_FP_HALF_FP:
7478 {
7479 unsigned long op = arm_decode_field (given, 28, 28);
7480 if (op == 0)
7481 func (stream, "f16.f32");
7482 else if (op == 1)
7483 func (stream, "f32.f16");
7484 }
7485 break;
7486
7487 case MVE_VCVT_FROM_FP_TO_INT:
7488 {
7489 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7490
7491 switch (size)
7492 {
7493 case 2:
7494 func (stream, "s16.f16");
7495 break;
7496
7497 case 3:
7498 func (stream, "u16.f16");
7499 break;
7500
7501 case 4:
7502 func (stream, "s32.f32");
7503 break;
7504
7505 case 5:
7506 func (stream, "u32.f32");
7507 break;
7508
7509 default:
7510 break;
7511 }
7512 }
7513 break;
7514
7515 default:
7516 break;
7517 }
7518}
7519
897b9bbc
AV		 7520static void
7521print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7522 unsigned long rot_width)
7523{
7524 void *stream = info->stream;
7525 fprintf_ftype func = info->fprintf_func;
7526
7527 if (rot_width == 1)
7528 {
7529 switch (rot)
7530 {
7531 case 0:
7532 func (stream, "90");
7533 break;
7534 case 1:
7535 func (stream, "270");
7536 break;
7537 default:
7538 break;
7539 }
7540 }
7541 else if (rot_width == 2)
7542 {
7543 switch (rot)
7544 {
7545 case 0:
7546 func (stream, "0");
7547 break;
7548 case 1:
7549 func (stream, "90");
7550 break;
7551 case 2:
7552 func (stream, "180");
7553 break;
7554 case 3:
7555 func (stream, "270");
7556 break;
7557 default:
7558 break;
7559 }
7560 }
7561}
7562
143275ea
AV		 7563static void
7564print_instruction_predicate (struct disassemble_info *info)
7565{
7566 void *stream = info->stream;
7567 fprintf_ftype func = info->fprintf_func;
7568
7569 if (vpt_block_state.next_pred_state == PRED_THEN)
7570 func (stream, "t");
7571 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7572 func (stream, "e");
7573}
7574
7575static void
7576print_mve_size (struct disassemble_info *info,
7577 unsigned long size,
7578 enum mve_instructions matched_insn)
7579{
7580 void *stream = info->stream;
7581 fprintf_ftype func = info->fprintf_func;
7582
7583 switch (matched_insn)
7584 {
66dcaa5d
AV		 7585 case MVE_VABAV:
7586 case MVE_VABD_VEC:
7587 case MVE_VABS_FP:
7588 case MVE_VABS_VEC:
7589 case MVE_VADD_VEC_T1:
7590 case MVE_VADD_VEC_T2:
d3b63143 7591 case MVE_VADDV:
e523f101 7592 case MVE_VBRSR:
897b9bbc 7593 case MVE_VCADD_VEC:
e523f101
AV		 7594 case MVE_VCLS:
7595 case MVE_VCLZ:
143275ea
AV		 7596 case MVE_VCMP_VEC_T1:
7597 case MVE_VCMP_VEC_T2:
7598 case MVE_VCMP_VEC_T3:
7599 case MVE_VCMP_VEC_T4:
7600 case MVE_VCMP_VEC_T5:
7601 case MVE_VCMP_VEC_T6:
e523f101 7602 case MVE_VCTP:
1c8f2df8
AV		 7603 case MVE_VDDUP:
7604 case MVE_VDWDUP:
9743db03
AV		 7605 case MVE_VHADD_T1:
7606 case MVE_VHADD_T2:
897b9bbc 7607 case MVE_VHCADD:
9743db03
AV		 7608 case MVE_VHSUB_T1:
7609 case MVE_VHSUB_T2:
1c8f2df8
AV		 7610 case MVE_VIDUP:
7611 case MVE_VIWDUP:
04d54ace
AV		 7612 case MVE_VLD2:
7613 case MVE_VLD4:
ef1576a1
AV		 7614 case MVE_VLDRB_GATHER_T1:
7615 case MVE_VLDRH_GATHER_T2:
7616 case MVE_VLDRW_GATHER_T3:
7617 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7618 case MVE_VLDRB_T1:
7619 case MVE_VLDRH_T2:
56858bea
AV		 7620 case MVE_VMAX:
7621 case MVE_VMAXA:
7622 case MVE_VMAXV:
7623 case MVE_VMAXAV:
7624 case MVE_VMIN:
7625 case MVE_VMINA:
7626 case MVE_VMINV:
7627 case MVE_VMINAV:
7628 case MVE_VMLA:
d3b63143 7629 case MVE_VMLAS:
f49bb598
AV		 7630 case MVE_VMUL_VEC_T1:
7631 case MVE_VMUL_VEC_T2:
7632 case MVE_VMULH:
7633 case MVE_VRMULH:
7634 case MVE_VMULL_INT:
7635 case MVE_VNEG_FP:
7636 case MVE_VNEG_VEC:
143275ea
AV		 7637 case MVE_VPT_VEC_T1:
7638 case MVE_VPT_VEC_T2:
7639 case MVE_VPT_VEC_T3:
7640 case MVE_VPT_VEC_T4:
7641 case MVE_VPT_VEC_T5:
7642 case MVE_VPT_VEC_T6:
14b456f2
AV		 7643 case MVE_VQABS:
7644 case MVE_VQADD_T1:
7645 case MVE_VQADD_T2:
d3b63143
AV		 7646 case MVE_VQDMLADH:
7647 case MVE_VQRDMLADH:
7648 case MVE_VQDMLAH:
7649 case MVE_VQRDMLAH:
7650 case MVE_VQDMLASH:
7651 case MVE_VQRDMLASH:
7652 case MVE_VQDMLSDH:
7653 case MVE_VQRDMLSDH:
7654 case MVE_VQDMULH_T1:
7655 case MVE_VQRDMULH_T2:
7656 case MVE_VQDMULH_T3:
7657 case MVE_VQRDMULH_T4:
14b456f2 7658 case MVE_VQNEG:
ed63aa17
AV		 7659 case MVE_VQRSHL_T1:
7660 case MVE_VQRSHL_T2:
7661 case MVE_VQSHL_T1:
7662 case MVE_VQSHL_T4:
14b456f2
AV		 7663 case MVE_VQSUB_T1:
7664 case MVE_VQSUB_T2:
7665 case MVE_VREV32:
7666 case MVE_VREV64:
9743db03 7667 case MVE_VRHADD:
bf0b396d 7668 case MVE_VRINT_FP:
ed63aa17
AV		 7669 case MVE_VRSHL_T1:
7670 case MVE_VRSHL_T2:
7671 case MVE_VSHL_T2:
7672 case MVE_VSHL_T3:
7673 case MVE_VSHLL_T2:
04d54ace
AV		 7674 case MVE_VST2:
7675 case MVE_VST4:
ef1576a1
AV		 7676 case MVE_VSTRB_SCATTER_T1:
7677 case MVE_VSTRH_SCATTER_T2:
7678 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7679 case MVE_VSTRB_T1:
7680 case MVE_VSTRH_T2:
66dcaa5d
AV		 7681 case MVE_VSUB_VEC_T1:
7682 case MVE_VSUB_VEC_T2:
143275ea
AV		 7683 if (size <= 3)
7684 func (stream, "%s", mve_vec_sizename[size]);
7685 else
7686 func (stream, "<undef size>");
7687 break;
7688
66dcaa5d
AV		 7689 case MVE_VABD_FP:
7690 case MVE_VADD_FP_T1:
7691 case MVE_VADD_FP_T2:
7692 case MVE_VSUB_FP_T1:
7693 case MVE_VSUB_FP_T2:
143275ea
AV		 7694 case MVE_VCMP_FP_T1:
7695 case MVE_VCMP_FP_T2:
9743db03
AV		 7696 case MVE_VFMA_FP_SCALAR:
7697 case MVE_VFMA_FP:
7698 case MVE_VFMS_FP:
7699 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7700 case MVE_VMAXNM_FP:
7701 case MVE_VMAXNMA_FP:
7702 case MVE_VMAXNMV_FP:
7703 case MVE_VMAXNMAV_FP:
7704 case MVE_VMINNM_FP:
7705 case MVE_VMINNMA_FP:
7706 case MVE_VMINNMV_FP:
7707 case MVE_VMINNMAV_FP:
f49bb598
AV		 7708 case MVE_VMUL_FP_T1:
7709 case MVE_VMUL_FP_T2:
143275ea
AV		 7710 case MVE_VPT_FP_T1:
7711 case MVE_VPT_FP_T2:
7712 if (size == 0)
7713 func (stream, "32");
7714 else if (size == 1)
7715 func (stream, "16");
7716 break;
7717
897b9bbc
AV		 7718 case MVE_VCADD_FP:
7719 case MVE_VCMLA_FP:
7720 case MVE_VCMUL_FP:
d3b63143
AV		 7721 case MVE_VMLADAV_T1:
7722 case MVE_VMLALDAV:
7723 case MVE_VMLSDAV_T1:
7724 case MVE_VMLSLDAV:
14925797
AV		 7725 case MVE_VMOVN:
7726 case MVE_VQDMULL_T1:
7727 case MVE_VQDMULL_T2:
7728 case MVE_VQMOVN:
7729 case MVE_VQMOVUN:
7730 if (size == 0)
7731 func (stream, "16");
7732 else if (size == 1)
7733 func (stream, "32");
7734 break;
7735
7736 case MVE_VMOVL:
7737 if (size == 1)
7738 func (stream, "8");
7739 else if (size == 2)
7740 func (stream, "16");
7741 break;
7742
9743db03
AV		 7743 case MVE_VDUP:
7744 switch (size)
7745 {
7746 case 0:
7747 func (stream, "32");
7748 break;
7749 case 1:
7750 func (stream, "16");
7751 break;
7752 case 2:
7753 func (stream, "8");
7754 break;
7755 default:
7756 break;
7757 }
7758 break;
7759
c507f10b
AV		 7760 case MVE_VMOV_GP_TO_VEC_LANE:
7761 case MVE_VMOV_VEC_LANE_TO_GP:
7762 switch (size)
7763 {
7764 case 0: case 4:
7765 func (stream, "32");
7766 break;
7767
7768 case 1: case 3:
7769 case 5: case 7:
7770 func (stream, "16");
7771 break;
7772
7773 case 8: case 9: case 10: case 11:
7774 case 12: case 13: case 14: case 15:
7775 func (stream, "8");
7776 break;
7777
7778 default:
7779 break;
7780 }
7781 break;
7782
7783 case MVE_VMOV_IMM_TO_VEC:
7784 switch (size)
7785 {
7786 case 0: case 4: case 8:
7787 case 12: case 24: case 26:
7788 func (stream, "i32");
7789 break;
7790 case 16: case 20:
7791 func (stream, "i16");
7792 break;
7793 case 28:
7794 func (stream, "i8");
7795 break;
7796 case 29:
7797 func (stream, "i64");
7798 break;
7799 case 30:
7800 func (stream, "f32");
7801 break;
7802 default:
7803 break;
7804 }
7805 break;
7806
14925797
AV		 7807 case MVE_VMULL_POLY:
7808 if (size == 0)
7809 func (stream, "p8");
7810 else if (size == 1)
7811 func (stream, "p16");
7812 break;
7813
c507f10b
AV		 7814 case MVE_VMVN_IMM:
7815 switch (size)
7816 {
7817 case 0: case 2: case 4:
7818 case 6: case 12: case 13:
7819 func (stream, "32");
7820 break;
7821
7822 case 8: case 10:
7823 func (stream, "16");
7824 break;
7825
7826 default:
7827 break;
7828 }
7829 break;
7830
7831 case MVE_VBIC_IMM:
7832 case MVE_VORR_IMM:
7833 switch (size)
7834 {
7835 case 1: case 3:
7836 case 5: case 7:
7837 func (stream, "32");
7838 break;
7839
7840 case 9: case 11:
7841 func (stream, "16");
7842 break;
7843
7844 default:
7845 break;
7846 }
7847 break;
7848
ed63aa17
AV		 7849 case MVE_VQSHRN:
7850 case MVE_VQSHRUN:
7851 case MVE_VQRSHRN:
7852 case MVE_VQRSHRUN:
7853 case MVE_VRSHRN:
7854 case MVE_VSHRN:
7855 {
7856 switch (size)
7857 {
7858 case 1:
7859 func (stream, "16");
7860 break;
7861
7862 case 2: case 3:
7863 func (stream, "32");
7864 break;
7865
7866 default:
7867 break;
7868 }
7869 }
7870 break;
7871
7872 case MVE_VQSHL_T2:
7873 case MVE_VQSHLU_T3:
7874 case MVE_VRSHR:
7875 case MVE_VSHL_T1:
7876 case MVE_VSHLL_T1:
7877 case MVE_VSHR:
7878 case MVE_VSLI:
7879 case MVE_VSRI:
7880 {
7881 switch (size)
7882 {
7883 case 1:
7884 func (stream, "8");
7885 break;
7886
7887 case 2: case 3:
7888 func (stream, "16");
7889 break;
7890
7891 case 4: case 5: case 6: case 7:
7892 func (stream, "32");
7893 break;
7894
7895 default:
7896 break;
7897 }
7898 }
7899 break;
7900
143275ea
AV		 7901 default:
7902 break;
7903 }
7904}
7905
ed63aa17
AV		 7906static void
7907print_mve_shift_n (struct disassemble_info *info, long given,
7908 enum mve_instructions matched_insn)
7909{
7910 void *stream = info->stream;
7911 fprintf_ftype func = info->fprintf_func;
7912
7913 int startAt0
7914 = matched_insn == MVE_VQSHL_T2
7915 || matched_insn == MVE_VQSHLU_T3
7916 || matched_insn == MVE_VSHL_T1
7917 || matched_insn == MVE_VSHLL_T1
7918 || matched_insn == MVE_VSLI;
7919
7920 unsigned imm6 = (given & 0x3f0000) >> 16;
7921
7922 if (matched_insn == MVE_VSHLL_T1)
7923 imm6 &= 0x1f;
7924
7925 unsigned shiftAmount = 0;
7926 if ((imm6 & 0x20) != 0)
7927 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7928 else if ((imm6 & 0x10) != 0)
7929 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7930 else if ((imm6 & 0x08) != 0)
7931 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7932 else
7933 print_mve_undefined (info, UNDEF_SIZE_0);
7934
7935 func (stream, "%u", shiftAmount);
7936}
7937
143275ea
AV		 7938static void
7939print_vec_condition (struct disassemble_info *info, long given,
7940 enum mve_instructions matched_insn)
7941{
7942 void *stream = info->stream;
7943 fprintf_ftype func = info->fprintf_func;
7944 long vec_cond = 0;
7945
7946 switch (matched_insn)
7947 {
7948 case MVE_VPT_FP_T1:
7949 case MVE_VCMP_FP_T1:
7950 vec_cond = (((given & 0x1000) >> 10)
7951 | ((given & 1) << 1)
7952 | ((given & 0x0080) >> 7));
7953 func (stream, "%s",vec_condnames[vec_cond]);
7954 break;
7955
7956 case MVE_VPT_FP_T2:
7957 case MVE_VCMP_FP_T2:
7958 vec_cond = (((given & 0x1000) >> 10)
7959 | ((given & 0x0020) >> 4)
7960 | ((given & 0x0080) >> 7));
7961 func (stream, "%s",vec_condnames[vec_cond]);
7962 break;
7963
7964 case MVE_VPT_VEC_T1:
7965 case MVE_VCMP_VEC_T1:
7966 vec_cond = (given & 0x0080) >> 7;
7967 func (stream, "%s",vec_condnames[vec_cond]);
7968 break;
7969
7970 case MVE_VPT_VEC_T2:
7971 case MVE_VCMP_VEC_T2:
7972 vec_cond = 2 | ((given & 0x0080) >> 7);
7973 func (stream, "%s",vec_condnames[vec_cond]);
7974 break;
7975
7976 case MVE_VPT_VEC_T3:
7977 case MVE_VCMP_VEC_T3:
7978 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7979 func (stream, "%s",vec_condnames[vec_cond]);
7980 break;
7981
7982 case MVE_VPT_VEC_T4:
7983 case MVE_VCMP_VEC_T4:
7984 vec_cond = (given & 0x0080) >> 7;
7985 func (stream, "%s",vec_condnames[vec_cond]);
7986 break;
7987
7988 case MVE_VPT_VEC_T5:
7989 case MVE_VCMP_VEC_T5:
7990 vec_cond = 2 | ((given & 0x0080) >> 7);
7991 func (stream, "%s",vec_condnames[vec_cond]);
7992 break;
7993
7994 case MVE_VPT_VEC_T6:
7995 case MVE_VCMP_VEC_T6:
7996 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7997 func (stream, "%s",vec_condnames[vec_cond]);
7998 break;
7999
8000 case MVE_NONE:
8001 case MVE_VPST:
8002 default:
8003 break;
8004 }
8005}
8006
8007#define W_BIT 21
8008#define I_BIT 22
8009#define U_BIT 23
8010#define P_BIT 24
8011
8012#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8013#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8014#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8015#define PRE_BIT_SET (given & (1 << P_BIT))
8016
8017
8f06b2d8
PB		 8018/* Print one coprocessor instruction on INFO->STREAM.
8019 Return TRUE if the instuction matched, FALSE if this is not a
8020 recognised coprocessor instruction. */
8021
78933a4a 8022static bool
33593eaf
MM		 8023print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8024 bfd_vma pc,
8025 struct disassemble_info *info,
8026 long given,
78933a4a 8027 bool thumb)
8f06b2d8 8028{
6b0dd094 8029 const struct sopcode32 *insn;
8f06b2d8
PB		 8030 void *stream = info->stream;
8031 fprintf_ftype func = info->fprintf_func;
8032 unsigned long mask;
2edcd244 8033 unsigned long value = 0;
c22aaad1 8034 int cond;
8afc7bea 8035 int cp_num;
823d2571
TG		 8036 struct arm_private_data *private_data = info->private_data;
8037 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8038 arm_feature_set arm_ext_v8_1m_main =
8039 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 8040
5b616bef 8041 allowed_arches = private_data->features;
8f06b2d8 8042
33593eaf 8043 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8044 {
ff4a8d2b 8045 unsigned long u_reg = 16;
78933a4a 8046 bool is_unpredictable = false;
05413229 8047 signed long value_in_comment = 0;
0313a2b8
NC		 8048 const char *c;
8049
823d2571 8050 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8051 switch (insn->value)
8052 {
8053 case SENTINEL_IWMMXT_START:
8054 if (info->mach != bfd_mach_arm_XScale
8055 && info->mach != bfd_mach_arm_iWMMXt
8056 && info->mach != bfd_mach_arm_iWMMXt2)
8057 do
8058 insn++;
823d2571
TG		 8059 while ((! ARM_FEATURE_ZERO (insn->arch))
8060 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8061 continue;
8062
8063 case SENTINEL_IWMMXT_END:
8064 continue;
8065
8066 case SENTINEL_GENERIC_START:
5b616bef 8067 allowed_arches = private_data->features;
05413229
NC		 8068 continue;
8069
8070 default:
8071 abort ();
8072 }
8f06b2d8
PB		 8073
8074 mask = insn->mask;
8075 value = insn->value;
8afc7bea
RL		 8076 cp_num = (given >> 8) & 0xf;
8077
8f06b2d8
PB		 8078 if (thumb)
8079 {
8080 /* The high 4 bits are 0xe for Arm conditional instructions, and
8081 0xe for arm unconditional instructions. The rest of the
8082 encoding is the same. */
8083 mask |= 0xf0000000;
8084 value |= 0xe0000000;
c22aaad1
PB		 8085 if (ifthen_state)
8086 cond = IFTHEN_COND;
8087 else
e2efe87d 8088 cond = COND_UNCOND;
8f06b2d8
PB		 8089 }
8090 else
8091 {
8092 /* Only match unconditional instuctions against unconditional
8093 patterns. */
8094 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8095 {
8096 mask |= 0xf0000000;
e2efe87d 8097 cond = COND_UNCOND;
c22aaad1
PB		 8098 }
8099 else
8100 {
8101 cond = (given >> 28) & 0xf;
8102 if (cond == 0xe)
e2efe87d 8103 cond = COND_UNCOND;
c22aaad1 8104 }
8f06b2d8 8105 }
823d2571 8106
6b0dd094
AV		 8107 if ((insn->isa == T32 && !thumb)
8108 || (insn->isa == ARM && thumb))
8109 continue;
8110
0313a2b8
NC		 8111 if ((given & mask) != value)
8112 continue;
8f06b2d8 8113
823d2571 8114 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8115 continue;
8116
8afc7bea
RL		 8117 if (insn->value == 0xfe000010 /* mcr2 */
8118 || insn->value == 0xfe100010 /* mrc2 */
8119 || insn->value == 0xfc100000 /* ldc2 */
8120 || insn->value == 0xfc000000) /* stc2 */
8121 {
b0c11777 8122 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
78933a4a 8123 is_unpredictable = true;
f08d8ce3
AV		 8124
8125 /* Armv8.1-M Mainline FP & MVE instructions. */
8126 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8127 && !ARM_CPU_IS_ANY (allowed_arches)
8128 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8129 continue;
8130
8afc7bea
RL		 8131 }
8132 else if (insn->value == 0x0e000000 /* cdp */
8133 || insn->value == 0xfe000000 /* cdp2 */
8134 || insn->value == 0x0e000010 /* mcr */
8135 || insn->value == 0x0e100010 /* mrc */
8136 || insn->value == 0x0c100000 /* ldc */
8137 || insn->value == 0x0c000000) /* stc */
8138 {
8139 /* Floating-point instructions. */
b0c11777 8140 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8141 continue;
32c36c3c
AV		 8142
8143 /* Armv8.1-M Mainline FP & MVE instructions. */
8144 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8145 && !ARM_CPU_IS_ANY (allowed_arches)
8146 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8147 continue;
8afc7bea 8148 }
aef6d006
AV		 8149 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8150 || insn->value == 0xec000f80) /* vstr (system register) */
8151 && arm_decode_field (given, 24, 24) == 0
8152 && arm_decode_field (given, 21, 21) == 0)
8153 /* If the P and W bits are both 0 then these encodings match the MVE
8154 VLDR and VSTR instructions, these are in a different table, so we
8155 don't let it match here. */
8156 continue;
8157
0313a2b8
NC		 8158 for (c = insn->assembler; *c; c++)
8159 {
8160 if (*c == '%')
8f06b2d8 8161 {
32c36c3c
AV		 8162 const char mod = *++c;
8163 switch (mod)
8f06b2d8 8164 {
0313a2b8
NC		 8165 case '%':
8166 func (stream, "%%");
8167 break;
8168
8169 case 'A':
32c36c3c 8170 case 'K':
05413229 8171 {
79862e45 8172 int rn = (given >> 16) & 0xf;
b0c11777 8173 bfd_vma offset = given & 0xff;
0313a2b8 8174
32c36c3c
AV		 8175 if (mod == 'K')
8176 offset = given & 0x7f;
8177
05413229 8178 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8179
79862e45
DJ		 8180 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8181 {
8182 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8183 if (cp_num == 9)
8184 /* vldr.16/vstr.16 will shift the address
8185 left by 1 bit only. */
8186 offset = offset * 2;
8187 else
8188 offset = offset * 4;
8189
79862e45
DJ		 8190 if (NEGATIVE_BIT_SET)
8191 offset = - offset;
8192 if (rn != 15)
8193 value_in_comment = offset;
8194 }
8195
c1e26897 8196 if (PRE_BIT_SET)
05413229
NC		 8197 {
8198 if (offset)
fe56b6ce 8199 func (stream, ", #%d]%s",
d908c8af 8200 (int) offset,
c1e26897 8201 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8202 else if (NEGATIVE_BIT_SET)
8203 func (stream, ", #-0]");
05413229
NC		 8204 else
8205 func (stream, "]");
8206 }
8207 else
8208 {
0313a2b8 8209 func (stream, "]");
8f06b2d8 8210
c1e26897 8211 if (WRITEBACK_BIT_SET)
05413229
NC		 8212 {
8213 if (offset)
d908c8af 8214 func (stream, ", #%d", (int) offset);
26d97720
NS		 8215 else if (NEGATIVE_BIT_SET)
8216 func (stream, ", #-0");
05413229
NC		 8217 }
8218 else
fe56b6ce 8219 {
26d97720
NS		 8220 func (stream, ", {%s%d}",
8221 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8222 (int) offset);
fe56b6ce
NC		 8223 value_in_comment = offset;
8224 }
05413229 8225 }
79862e45
DJ		 8226 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8227 {
8228 func (stream, "\t; ");
6844b2c2
MGD		 8229 /* For unaligned PCs, apply off-by-alignment
8230 correction. */
43e65147 8231 info->print_address_func (offset + pc
6844b2c2
MGD		 8232 + info->bytes_per_chunk * 2
8233 - (pc & 3),
dffaa15c 8234 info);
79862e45 8235 }
05413229 8236 }
0313a2b8 8237 break;
8f06b2d8 8238
0313a2b8
NC		 8239 case 'B':
8240 {
8241 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8242 int offset = (given >> 1) & 0x3f;
8243
8244 if (offset == 1)
8245 func (stream, "{d%d}", regno);
8246 else if (regno + offset > 32)
8247 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8248 else
8249 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8250 }
8251 break;
8f06b2d8 8252
efd6b359
AV		 8253 case 'C':
8254 {
78933a4a 8255 bool single = ((given >> 8) & 1) == 0;
efd6b359
AV		 8256 char reg_prefix = single ? 's' : 'd';
8257 int Dreg = (given >> 22) & 0x1;
8258 int Vdreg = (given >> 12) & 0xf;
8259 int reg = single ? ((Vdreg << 1) | Dreg)
8260 : ((Dreg << 4) | Vdreg);
8261 int num = (given >> (single ? 0 : 1)) & 0x7f;
8262 int maxreg = single ? 31 : 15;
8263 int topreg = reg + num - 1;
8264
8265 if (!num)
8266 func (stream, "{VPR}");
8267 else if (num == 1)
8268 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8269 else if (topreg > maxreg)
8270 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8271 reg_prefix, reg, single ? topreg >> 1 : topreg);
8272 else
8273 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8274 reg_prefix, topreg);
8275 }
8276 break;
8277
e2efe87d
MGD		 8278 case 'u':
8279 if (cond != COND_UNCOND)
78933a4a 8280 is_unpredictable = true;
e2efe87d
MGD		 8281
8282 /* Fall through. */
0313a2b8 8283 case 'c':
b0c11777 8284 if (cond != COND_UNCOND && cp_num == 9)
78933a4a 8285 is_unpredictable = true;
b0c11777 8286
aab2c27d
MM		 8287 /* Fall through. */
8288 case 'b':
0313a2b8
NC		 8289 func (stream, "%s", arm_conditional[cond]);
8290 break;
8f06b2d8 8291
0313a2b8
NC		 8292 case 'I':
8293 /* Print a Cirrus/DSP shift immediate. */
8294 /* Immediates are 7bit signed ints with bits 0..3 in
8295 bits 0..3 of opcode and bits 4..6 in bits 5..7
8296 of opcode. */
8297 {
8298 int imm;
8f06b2d8 8299
0313a2b8 8300 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8301
0313a2b8
NC		 8302 /* Is ``imm'' a negative number? */
8303 if (imm & 0x40)
24b4cf66 8304 imm -= 0x80;
8f06b2d8 8305
0313a2b8
NC		 8306 func (stream, "%d", imm);
8307 }
8308
8309 break;
8f06b2d8 8310
32c36c3c
AV		 8311 case 'J':
8312 {
73cd51e5
AV		 8313 unsigned long regno
8314 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8315
8316 switch (regno)
8317 {
8318 case 0x1:
8319 func (stream, "FPSCR");
8320 break;
8321 case 0x2:
8322 func (stream, "FPSCR_nzcvqc");
8323 break;
8324 case 0xc:
8325 func (stream, "VPR");
8326 break;
8327 case 0xd:
8328 func (stream, "P0");
8329 break;
8330 case 0xe:
8331 func (stream, "FPCXTNS");
8332 break;
8333 case 0xf:
8334 func (stream, "FPCXTS");
8335 break;
8336 default:
73cd51e5 8337 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8338 break;
8339 }
8340 }
8341 break;
8342
0313a2b8
NC		 8343 case 'F':
8344 switch (given & 0x00408000)
8345 {
8346 case 0:
8347 func (stream, "4");
8348 break;
8349 case 0x8000:
8350 func (stream, "1");
8351 break;
8352 case 0x00400000:
8353 func (stream, "2");
8f06b2d8 8354 break;
0313a2b8
NC		 8355 default:
8356 func (stream, "3");
8357 }
8358 break;
8f06b2d8 8359
0313a2b8
NC		 8360 case 'P':
8361 switch (given & 0x00080080)
8362 {
8363 case 0:
8364 func (stream, "s");
8365 break;
8366 case 0x80:
8367 func (stream, "d");
8368 break;
8369 case 0x00080000:
8370 func (stream, "e");
8371 break;
8372 default:
8373 func (stream, _("<illegal precision>"));
8f06b2d8 8374 break;
0313a2b8
NC		 8375 }
8376 break;
8f06b2d8 8377
0313a2b8
NC		 8378 case 'Q':
8379 switch (given & 0x00408000)
8380 {
8381 case 0:
8382 func (stream, "s");
8f06b2d8 8383 break;
0313a2b8
NC		 8384 case 0x8000:
8385 func (stream, "d");
8f06b2d8 8386 break;
0313a2b8
NC		 8387 case 0x00400000:
8388 func (stream, "e");
8389 break;
8390 default:
8391 func (stream, "p");
8f06b2d8 8392 break;
0313a2b8
NC		 8393 }
8394 break;
8f06b2d8 8395
0313a2b8
NC		 8396 case 'R':
8397 switch (given & 0x60)
8398 {
8399 case 0:
8400 break;
8401 case 0x20:
8402 func (stream, "p");
8403 break;
8404 case 0x40:
8405 func (stream, "m");
8406 break;
8407 default:
8408 func (stream, "z");
8409 break;
8410 }
8411 break;
16980d0b 8412
0313a2b8
NC		 8413 case '0': case '1': case '2': case '3': case '4':
8414 case '5': case '6': case '7': case '8': case '9':
8415 {
8416 int width;
8f06b2d8 8417
0313a2b8 8418 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8419
0313a2b8
NC		 8420 switch (*c)
8421 {
ff4a8d2b
NC		 8422 case 'R':
8423 if (value == 15)
78933a4a 8424 is_unpredictable = true;
ff4a8d2b 8425 /* Fall through. */
0313a2b8 8426 case 'r':
ff4a8d2b
NC		 8427 if (c[1] == 'u')
8428 {
8429 /* Eat the 'u' character. */
8430 ++ c;
8431
8432 if (u_reg == value)
78933a4a 8433 is_unpredictable = true;
ff4a8d2b
NC		 8434 u_reg = value;
8435 }
0313a2b8
NC		 8436 func (stream, "%s", arm_regnames[value]);
8437 break;
c28eeff2
SN		 8438 case 'V':
8439 if (given & (1 << 6))
8440 goto Q;
8441 /* FALLTHROUGH */
0313a2b8
NC		 8442 case 'D':
8443 func (stream, "d%ld", value);
8444 break;
8445 case 'Q':
c28eeff2 8446 Q:
0313a2b8
NC		 8447 if (value & 1)
8448 func (stream, "<illegal reg q%ld.5>", value >> 1);
8449 else
8450 func (stream, "q%ld", value >> 1);
8451 break;
8452 case 'd':
8453 func (stream, "%ld", value);
05413229 8454 value_in_comment = value;
0313a2b8 8455 break;
6f1c2142
AM		 8456 case 'E':
8457 {
8458 /* Converts immediate 8 bit back to float value. */
8459 unsigned floatVal = (value & 0x80) << 24
8460 | (value & 0x3F) << 19
8461 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8462
8463 /* Quarter float have a maximum value of 31.0.
8464 Get floating point value multiplied by 1e7.
8465 The maximum value stays in limit of a 32-bit int. */
8466 unsigned decVal =
8467 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8468 (16 + (value & 0xF));
8469
8470 if (!(decVal % 1000000))
8471 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8472 floatVal, value & 0x80 ? '-' : ' ',
8473 decVal / 10000000,
8474 decVal % 10000000 / 1000000);
8475 else if (!(decVal % 10000))
8476 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8477 floatVal, value & 0x80 ? '-' : ' ',
8478 decVal / 10000000,
8479 decVal % 10000000 / 10000);
8480 else
8481 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8482 floatVal, value & 0x80 ? '-' : ' ',
8483 decVal / 10000000, decVal % 10000000);
8484 break;
8485 }
0313a2b8
NC		 8486 case 'k':
8487 {
8488 int from = (given & (1 << 7)) ? 32 : 16;
8489 func (stream, "%ld", from - value);
8490 }
8491 break;
8f06b2d8 8492
0313a2b8
NC		 8493 case 'f':
8494 if (value > 7)
8495 func (stream, "#%s", arm_fp_const[value & 7]);
8496 else
8497 func (stream, "f%ld", value);
8498 break;
4146fd53 8499
0313a2b8
NC		 8500 case 'w':
8501 if (width == 2)
8502 func (stream, "%s", iwmmxt_wwnames[value]);
8503 else
8504 func (stream, "%s", iwmmxt_wwssnames[value]);
8505 break;
4146fd53 8506
0313a2b8
NC		 8507 case 'g':
8508 func (stream, "%s", iwmmxt_regnames[value]);
8509 break;
8510 case 'G':
8511 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8512 break;
8f06b2d8 8513
0313a2b8 8514 case 'x':
d1aaab3c 8515 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8516 break;
8f06b2d8 8517
33399f07
MGD		 8518 case 'c':
8519 switch (value)
8520 {
8521 case 0:
8522 func (stream, "eq");
8523 break;
8524
8525 case 1:
8526 func (stream, "vs");
8527 break;
8528
8529 case 2:
8530 func (stream, "ge");
8531 break;
8532
8533 case 3:
8534 func (stream, "gt");
8535 break;
8536
8537 default:
8538 func (stream, "??");
8539 break;
8540 }
8541 break;
8542
0313a2b8
NC		 8543 case '`':
8544 c++;
8545 if (value == 0)
8546 func (stream, "%c", *c);
8547 break;
8548 case '\'':
8549 c++;
8550 if (value == ((1ul << width) - 1))
8551 func (stream, "%c", *c);
8552 break;
8553 case '?':
fe56b6ce 8554 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8555 c += 1 << width;
8556 break;
8557 default:
8558 abort ();
8559 }
dffaa15c
AM		 8560 }
8561 break;
0313a2b8 8562
dffaa15c
AM		 8563 case 'y':
8564 case 'z':
8565 {
8566 int single = *c++ == 'y';
8567 int regno;
8f06b2d8 8568
dffaa15c
AM		 8569 switch (*c)
8570 {
8571 case '4': /* Sm pair */
8572 case '0': /* Sm, Dm */
8573 regno = given & 0x0000000f;
8574 if (single)
8575 {
8576 regno <<= 1;
8577 regno += (given >> 5) & 1;
8578 }
8579 else
8580 regno += ((given >> 5) & 1) << 4;
8581 break;
8f06b2d8 8582
dffaa15c
AM		 8583 case '1': /* Sd, Dd */
8584 regno = (given >> 12) & 0x0000000f;
8585 if (single)
8586 {
8587 regno <<= 1;
8588 regno += (given >> 22) & 1;
8589 }
8590 else
8591 regno += ((given >> 22) & 1) << 4;
8592 break;
7df76b80 8593
dffaa15c
AM		 8594 case '2': /* Sn, Dn */
8595 regno = (given >> 16) & 0x0000000f;
8596 if (single)
8597 {
8598 regno <<= 1;
8599 regno += (given >> 7) & 1;
8600 }
8601 else
8602 regno += ((given >> 7) & 1) << 4;
8603 break;
a7f8487e 8604
dffaa15c
AM		 8605 case '3': /* List */
8606 func (stream, "{");
8607 regno = (given >> 12) & 0x0000000f;
8608 if (single)
8609 {
8610 regno <<= 1;
8611 regno += (given >> 22) & 1;
8612 }
8613 else
8614 regno += ((given >> 22) & 1) << 4;
8615 break;
a7f8487e 8616
dffaa15c
AM		 8617 default:
8618 abort ();
8619 }
0313a2b8 8620
dffaa15c 8621 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8622
dffaa15c
AM		 8623 if (*c == '3')
8624 {
8625 int count = given & 0xff;
b34976b6 8626
dffaa15c
AM		 8627 if (single == 0)
8628 count >>= 1;
0313a2b8 8629
dffaa15c
AM		 8630 if (--count)
8631 {
8632 func (stream, "-%c%d",
8633 single ? 's' : 'd',
8634 regno + count);
8635 }
0313a2b8 8636
dffaa15c 8637 func (stream, "}");
0313a2b8 8638 }
dffaa15c
AM		 8639 else if (*c == '4')
8640 func (stream, ", %c%d", single ? 's' : 'd',
8641 regno + 1);
8642 }
8643 break;
b34976b6 8644
dffaa15c
AM		 8645 case 'L':
8646 switch (given & 0x00400100)
0313a2b8 8647 {
dffaa15c
AM		 8648 case 0x00000000: func (stream, "b"); break;
8649 case 0x00400000: func (stream, "h"); break;
8650 case 0x00000100: func (stream, "w"); break;
8651 case 0x00400100: func (stream, "d"); break;
8652 default:
8653 break;
0313a2b8 8654 }
dffaa15c 8655 break;
2d447fca 8656
dffaa15c
AM		 8657 case 'Z':
8658 {
8659 /* given (20, 23) | given (0, 3) */
8660 value = ((given >> 16) & 0xf0) | (given & 0xf);
8661 func (stream, "%d", (int) value);
8662 }
8663 break;
0313a2b8 8664
dffaa15c
AM		 8665 case 'l':
8666 /* This is like the 'A' operator, except that if
8667 the width field "M" is zero, then the offset is
8668 *not* multiplied by four. */
8669 {
8670 int offset = given & 0xff;
8671 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8672
dffaa15c 8673 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8674
dffaa15c
AM		 8675 if (multiplier > 1)
8676 {
8677 value_in_comment = offset * multiplier;
8678 if (NEGATIVE_BIT_SET)
8679 value_in_comment = - value_in_comment;
8680 }
0313a2b8 8681
dffaa15c
AM		 8682 if (offset)
8683 {
8684 if (PRE_BIT_SET)
8685 func (stream, ", #%s%d]%s",
8686 NEGATIVE_BIT_SET ? "-" : "",
8687 offset * multiplier,
8688 WRITEBACK_BIT_SET ? "!" : "");
8689 else
8690 func (stream, "], #%s%d",
8691 NEGATIVE_BIT_SET ? "-" : "",
8692 offset * multiplier);
8693 }
8694 else
8695 func (stream, "]");
8696 }
8697 break;
2d447fca 8698
dffaa15c
AM		 8699 case 'r':
8700 {
8701 int imm4 = (given >> 4) & 0xf;
8702 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8703 int ubit = ! NEGATIVE_BIT_SET;
8704 const char *rm = arm_regnames [given & 0xf];
8705 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8706
dffaa15c
AM		 8707 switch (puw_bits)
8708 {
8709 case 1:
8710 case 3:
8711 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8712 if (imm4)
8713 func (stream, ", lsl #%d", imm4);
8714 break;
0313a2b8 8715
dffaa15c
AM		 8716 case 4:
8717 case 5:
8718 case 6:
8719 case 7:
8720 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8721 if (imm4 > 0)
8722 func (stream, ", lsl #%d", imm4);
8723 func (stream, "]");
8724 if (puw_bits == 5 || puw_bits == 7)
8725 func (stream, "!");
8726 break;
2d447fca 8727
dffaa15c
AM		 8728 default:
8729 func (stream, "INVALID");
8730 }
8731 }
8732 break;
0313a2b8 8733
dffaa15c
AM		 8734 case 'i':
8735 {
8736 long imm5;
8737 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8738 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8739 }
dffaa15c
AM		 8740 break;
8741
8742 default:
8743 abort ();
252b5132 8744 }
252b5132 8745 }
0313a2b8
NC		 8746 else
8747 func (stream, "%c", *c);
252b5132 8748 }
05413229
NC		 8749
8750 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8751 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8752
ff4a8d2b
NC		 8753 if (is_unpredictable)
8754 func (stream, UNPREDICTABLE_INSTRUCTION);
8755
78933a4a 8756 return true;
252b5132 8757 }
78933a4a 8758 return false;
252b5132
RH		 8759}
8760
78933a4a 8761static bool
33593eaf
MM		 8762print_insn_coprocessor (bfd_vma pc,
8763 struct disassemble_info *info,
8764 long given,
78933a4a 8765 bool thumb)
33593eaf
MM		 8766{
8767 return print_insn_coprocessor_1 (coprocessor_opcodes,
8768 pc, info, given, thumb);
8769}
8770
78933a4a 8771static bool
33593eaf
MM		 8772print_insn_generic_coprocessor (bfd_vma pc,
8773 struct disassemble_info *info,
8774 long given,
78933a4a 8775 bool thumb)
33593eaf
MM		 8776{
8777 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8778 pc, info, given, thumb);
8779}
8780
05413229
NC		 8781/* Decodes and prints ARM addressing modes. Returns the offset
8782 used in the address, if any, if it is worthwhile printing the
8783 offset as a hexadecimal value in a comment at the end of the
8784 line of disassembly. */
8785
8786static signed long
62b3e311
PB		 8787print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8788{
8789 void *stream = info->stream;
8790 fprintf_ftype func = info->fprintf_func;
f8b960bc 8791 bfd_vma offset = 0;
62b3e311
PB		 8792
8793 if (((given & 0x000f0000) == 0x000f0000)
8794 && ((given & 0x02000000) == 0))
8795 {
05413229 8796 offset = given & 0xfff;
62b3e311
PB		 8797
8798 func (stream, "[pc");
8799
c1e26897 8800 if (PRE_BIT_SET)
62b3e311 8801 {
26d97720
NS		 8802 /* Pre-indexed. Elide offset of positive zero when
8803 non-writeback. */
8804 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8805 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8806
8807 if (NEGATIVE_BIT_SET)
8808 offset = -offset;
62b3e311
PB		 8809
8810 offset += pc + 8;
8811
8812 /* Cope with the possibility of write-back
8813 being used. Probably a very dangerous thing
8814 for the programmer to do, but who are we to
8815 argue ? */
26d97720 8816 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8817 }
c1e26897 8818 else /* Post indexed. */
62b3e311 8819 {
d908c8af 8820 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8821
c1e26897 8822 /* Ie ignore the offset. */
62b3e311
PB		 8823 offset = pc + 8;
8824 }
8825
8826 func (stream, "\t; ");
8827 info->print_address_func (offset, info);
05413229 8828 offset = 0;
62b3e311
PB		 8829 }
8830 else
8831 {
8832 func (stream, "[%s",
8833 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8834
8835 if (PRE_BIT_SET)
62b3e311
PB		 8836 {
8837 if ((given & 0x02000000) == 0)
8838 {
26d97720 8839 /* Elide offset of positive zero when non-writeback. */
05413229 8840 offset = given & 0xfff;
26d97720 8841 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8842 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8843 }
8844 else
8845 {
26d97720 8846 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8847 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8848 }
8849
8850 func (stream, "]%s",
c1e26897 8851 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8852 }
8853 else
8854 {
8855 if ((given & 0x02000000) == 0)
8856 {
26d97720 8857 /* Always show offset. */
05413229 8858 offset = given & 0xfff;
26d97720 8859 func (stream, "], #%s%d",
d908c8af 8860 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8861 }
8862 else
8863 {
8864 func (stream, "], %s",
c1e26897 8865 NEGATIVE_BIT_SET ? "-" : "");
78933a4a 8866 arm_decode_shift (given, func, stream, true);
62b3e311
PB		 8867 }
8868 }
84919466
MR		 8869 if (NEGATIVE_BIT_SET)
8870 offset = -offset;
62b3e311 8871 }
05413229
NC		 8872
8873 return (signed long) offset;
62b3e311
PB		 8874}
8875
4934a27c
MM		 8876
8877/* Print one cde instruction on INFO->STREAM.
8878 Return TRUE if the instuction matched, FALSE if this is not a
8879 recognised cde instruction. */
78933a4a
AM		 8880static bool
8881print_insn_cde (struct disassemble_info *info, long given, bool thumb)
4934a27c
MM		 8882{
8883 const struct cdeopcode32 *insn;
8884 void *stream = info->stream;
8885 fprintf_ftype func = info->fprintf_func;
8886
8887 if (thumb)
8888 {
8889 /* Manually extract the coprocessor code from a known point.
8890 This position is the same across all CDE instructions. */
8891 for (insn = cde_opcodes; insn->assembler; insn++)
8892 {
8893 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8894 uint16_t coproc_mask = 1 << coproc;
8895 if (! (coproc_mask & cde_coprocs))
8896 continue;
8897
8898 if ((given & insn->mask) == insn->value)
8899 {
78933a4a 8900 bool is_unpredictable = false;
4934a27c
MM		 8901 const char *c;
8902
8903 for (c = insn->assembler; *c; c++)
8904 {
8905 if (*c == '%')
8906 {
8907 switch (*++c)
8908 {
8909 case '%':
8910 func (stream, "%%");
8911 break;
8912
8913 case '0': case '1': case '2': case '3': case '4':
8914 case '5': case '6': case '7': case '8': case '9':
8915 {
8916 int width;
8917 unsigned long value;
8918
8919 c = arm_decode_bitfield (c, given, &value, &width);
8920
8921 switch (*c)
8922 {
8923 case 'S':
8924 if (value > 10)
78933a4a 8925 is_unpredictable = true;
4934a27c
MM		 8926 /* Fall through. */
8927 case 'R':
8928 if (value == 13)
78933a4a 8929 is_unpredictable = true;
4934a27c
MM		 8930 /* Fall through. */
8931 case 'r':
8932 func (stream, "%s", arm_regnames[value]);
8933 break;
8934
8935 case 'n':
8936 if (value == 15)
8937 func (stream, "%s", "APSR_nzcv");
8938 else
8939 func (stream, "%s", arm_regnames[value]);
8940 break;
8941
8942 case 'T':
8943 func (stream, "%s", arm_regnames[value + 1]);
8944 break;
8945
8946 case 'd':
8947 func (stream, "%ld", value);
8948 break;
8949
5aae9ae9
MM		 8950 case 'V':
8951 if (given & (1 << 6))
8952 func (stream, "q%ld", value >> 1);
8953 else if (given & (1 << 24))
8954 func (stream, "d%ld", value);
8955 else
8956 {
8957 /* Encoding for S register is different than for D and
8958 Q registers. S registers are encoded using the top
8959 single bit in position 22 as the lowest bit of the
8960 register number, while for Q and D it represents the
8961 highest bit of the register number. */
8962 uint8_t top_bit = (value >> 4) & 1;
8963 uint8_t tmp = (value << 1) & 0x1e;
8964 uint8_t res = tmp | top_bit;
8965 func (stream, "s%u", res);
8966 }
8967 break;
8968
4934a27c
MM		 8969 default:
8970 abort ();
8971 }
8972 }
8973 break;
8974
8975 case 'p':
8976 {
8977 uint8_t proc_number = (given >> 8) & 0x7;
8978 func (stream, "p%u", proc_number);
8979 break;
8980 }
8981
8982 case 'a':
8983 {
8984 uint8_t a_offset = 28;
8985 if (given & (1 << a_offset))
8986 func (stream, "a");
8987 break;
8988 }
8989 default:
8990 abort ();
8991 }
8992 }
8993 else
8994 func (stream, "%c", *c);
8995 }
8996
8997 if (is_unpredictable)
8998 func (stream, UNPREDICTABLE_INSTRUCTION);
8999
78933a4a 9000 return true;
4934a27c
MM		 9001 }
9002 }
78933a4a 9003 return false;
4934a27c
MM		 9004 }
9005 else
78933a4a 9006 return false;
4934a27c
MM		 9007}
9008
9009
16980d0b
JB		 9010/* Print one neon instruction on INFO->STREAM.
9011 Return TRUE if the instuction matched, FALSE if this is not a
9012 recognised neon instruction. */
9013
78933a4a
AM		 9014static bool
9015print_insn_neon (struct disassemble_info *info, long given, bool thumb)
16980d0b
JB		 9016{
9017 const struct opcode32 *insn;
9018 void *stream = info->stream;
9019 fprintf_ftype func = info->fprintf_func;
9020
9021 if (thumb)
9022 {
9023 if ((given & 0xef000000) == 0xef000000)
9024 {
0313a2b8 9025 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9026 unsigned long bit28 = given & (1 << 28);
9027
9028 given &= 0x00ffffff;
9029 if (bit28)
9030 given |= 0xf3000000;
9031 else
9032 given |= 0xf2000000;
9033 }
9034 else if ((given & 0xff000000) == 0xf9000000)
9035 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9036 /* BFloat16 neon instructions without special top byte handling. */
9037 else if ((given & 0xff000000) == 0xfe000000
9038 || (given & 0xff000000) == 0xfc000000)
9039 ;
9743db03 9040 /* vdup is also a valid neon instruction. */
e409955d 9041 else if ((given & 0xff900f5f) != 0xee800b10)
78933a4a 9042 return false;
16980d0b 9043 }
43e65147 9044
16980d0b
JB		 9045 for (insn = neon_opcodes; insn->assembler; insn++)
9046 {
e409955d
FS		 9047 unsigned long cond_mask = insn->mask;
9048 unsigned long cond_value = insn->value;
9049 int cond;
9050
9051 if (thumb)
9052 {
9053 if ((cond_mask & 0xf0000000) == 0) {
9054 /* For the entries in neon_opcodes, an opcode mask/value with
9055 the high 4 bits equal to 0 indicates a conditional
9056 instruction. For thumb however, we need to include those
9057 bits in the instruction matching. */
9058 cond_mask |= 0xf0000000;
9059 /* Furthermore, the thumb encoding of a conditional instruction
9060 will have the high 4 bits equal to 0xe. */
9061 cond_value |= 0xe0000000;
9062 }
9063 if (ifthen_state)
9064 cond = IFTHEN_COND;
9065 else
9066 cond = COND_UNCOND;
9067 }
9068 else
9069 {
9070 if ((given & 0xf0000000) == 0xf0000000)
9071 {
9072 /* If the instruction is unconditional, update the mask to only
9073 match against unconditional opcode values. */
9074 cond_mask |= 0xf0000000;
9075 cond = COND_UNCOND;
9076 }
9077 else
9078 {
9079 cond = (given >> 28) & 0xf;
9080 if (cond == 0xe)
9081 cond = COND_UNCOND;
9082 }
9083 }
9084
9085 if ((given & cond_mask) == cond_value)
16980d0b 9086 {
05413229 9087 signed long value_in_comment = 0;
78933a4a 9088 bool is_unpredictable = false;
16980d0b
JB		 9089 const char *c;
9090
9091 for (c = insn->assembler; *c; c++)
9092 {
9093 if (*c == '%')
9094 {
9095 switch (*++c)
9096 {
9097 case '%':
9098 func (stream, "%%");
9099 break;
9100
e2efe87d
MGD		 9101 case 'u':
9102 if (thumb && ifthen_state)
78933a4a 9103 is_unpredictable = true;
e2efe87d
MGD		 9104
9105 /* Fall through. */
c22aaad1 9106 case 'c':
e409955d 9107 func (stream, "%s", arm_conditional[cond]);
c22aaad1
PB		 9108 break;
9109
16980d0b
JB		 9110 case 'A':
9111 {
43e65147 9112 static const unsigned char enc[16] =
16980d0b
JB		 9113 {
9114 0x4, 0x14, /* st4 0,1 */
9115 0x4, /* st1 2 */
9116 0x4, /* st2 3 */
9117 0x3, /* st3 4 */
9118 0x13, /* st3 5 */
9119 0x3, /* st1 6 */
9120 0x1, /* st1 7 */
9121 0x2, /* st2 8 */
9122 0x12, /* st2 9 */
9123 0x2, /* st1 10 */
9124 0, 0, 0, 0, 0
9125 };
9126 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9127 int rn = ((given >> 16) & 0xf);
9128 int rm = ((given >> 0) & 0xf);
9129 int align = ((given >> 4) & 0x3);
9130 int type = ((given >> 8) & 0xf);
9131 int n = enc[type] & 0xf;
9132 int stride = (enc[type] >> 4) + 1;
9133 int ix;
43e65147 9134
16980d0b
JB		 9135 func (stream, "{");
9136 if (stride > 1)
9137 for (ix = 0; ix != n; ix++)
9138 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9139 else if (n == 1)
9140 func (stream, "d%d", rd);
9141 else
9142 func (stream, "d%d-d%d", rd, rd + n - 1);
9143 func (stream, "}, [%s", arm_regnames[rn]);
9144 if (align)
8e560766 9145 func (stream, " :%d", 32 << align);
16980d0b
JB		 9146 func (stream, "]");
9147 if (rm == 0xd)
9148 func (stream, "!");
9149 else if (rm != 0xf)
9150 func (stream, ", %s", arm_regnames[rm]);
9151 }
9152 break;
43e65147 9153
16980d0b
JB		 9154 case 'B':
9155 {
9156 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9157 int rn = ((given >> 16) & 0xf);
9158 int rm = ((given >> 0) & 0xf);
9159 int idx_align = ((given >> 4) & 0xf);
9160 int align = 0;
9161 int size = ((given >> 10) & 0x3);
9162 int idx = idx_align >> (size + 1);
9163 int length = ((given >> 8) & 3) + 1;
9164 int stride = 1;
9165 int i;
9166
9167 if (length > 1 && size > 0)
9168 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9169
16980d0b
JB		 9170 switch (length)
9171 {
9172 case 1:
9173 {
9174 int amask = (1 << size) - 1;
9175 if ((idx_align & (1 << size)) != 0)
78933a4a 9176 return false;
16980d0b
JB		 9177 if (size > 0)
9178 {
9179 if ((idx_align & amask) == amask)
9180 align = 8 << size;
9181 else if ((idx_align & amask) != 0)
78933a4a 9182 return false;
16980d0b
JB		 9183 }
9184 }
9185 break;
43e65147 9186
16980d0b
JB		 9187 case 2:
9188 if (size == 2 && (idx_align & 2) != 0)
78933a4a 9189 return false;
16980d0b
JB		 9190 align = (idx_align & 1) ? 16 << size : 0;
9191 break;
43e65147 9192
16980d0b
JB		 9193 case 3:
9194 if ((size == 2 && (idx_align & 3) != 0)
9195 || (idx_align & 1) != 0)
78933a4a 9196 return false;
16980d0b 9197 break;
43e65147 9198
16980d0b
JB		 9199 case 4:
9200 if (size == 2)
9201 {
9202 if ((idx_align & 3) == 3)
78933a4a 9203 return false;
16980d0b
JB		 9204 align = (idx_align & 3) * 64;
9205 }
9206 else
9207 align = (idx_align & 1) ? 32 << size : 0;
9208 break;
43e65147 9209
16980d0b
JB		 9210 default:
9211 abort ();
9212 }
43e65147 9213
16980d0b
JB		 9214 func (stream, "{");
9215 for (i = 0; i < length; i++)
9216 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9217 rd + i * stride, idx);
9218 func (stream, "}, [%s", arm_regnames[rn]);
9219 if (align)
8e560766 9220 func (stream, " :%d", align);
16980d0b
JB		 9221 func (stream, "]");
9222 if (rm == 0xd)
9223 func (stream, "!");
9224 else if (rm != 0xf)
9225 func (stream, ", %s", arm_regnames[rm]);
9226 }
9227 break;
43e65147 9228
16980d0b
JB		 9229 case 'C':
9230 {
9231 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9232 int rn = ((given >> 16) & 0xf);
9233 int rm = ((given >> 0) & 0xf);
9234 int align = ((given >> 4) & 0x1);
9235 int size = ((given >> 6) & 0x3);
9236 int type = ((given >> 8) & 0x3);
9237 int n = type + 1;
9238 int stride = ((given >> 5) & 0x1);
9239 int ix;
43e65147 9240
16980d0b
JB		 9241 if (stride && (n == 1))
9242 n++;
9243 else
9244 stride++;
43e65147 9245
16980d0b
JB		 9246 func (stream, "{");
9247 if (stride > 1)
9248 for (ix = 0; ix != n; ix++)
9249 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9250 else if (n == 1)
9251 func (stream, "d%d[]", rd);
9252 else
9253 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9254 func (stream, "}, [%s", arm_regnames[rn]);
9255 if (align)
9256 {
91d6fa6a 9257 align = (8 * (type + 1)) << size;
16980d0b
JB		 9258 if (type == 3)
9259 align = (size > 1) ? align >> 1 : align;
9260 if (type == 2 || (type == 0 && !size))
8e560766 9261 func (stream, " :<bad align %d>", align);
16980d0b 9262 else
8e560766 9263 func (stream, " :%d", align);
16980d0b
JB		 9264 }
9265 func (stream, "]");
9266 if (rm == 0xd)
9267 func (stream, "!");
9268 else if (rm != 0xf)
9269 func (stream, ", %s", arm_regnames[rm]);
9270 }
9271 break;
43e65147 9272
16980d0b
JB		 9273 case 'D':
9274 {
9275 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9276 int size = (given >> 20) & 3;
9277 int reg = raw_reg & ((4 << size) - 1);
9278 int ix = raw_reg >> size >> 2;
43e65147 9279
16980d0b
JB		 9280 func (stream, "d%d[%d]", reg, ix);
9281 }
9282 break;
43e65147 9283
16980d0b 9284 case 'E':
fe56b6ce 9285 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9286 {
9287 int bits = 0;
9288 int cmode = (given >> 8) & 0xf;
9289 int op = (given >> 5) & 0x1;
9290 unsigned long value = 0, hival = 0;
9291 unsigned shift;
9292 int size = 0;
0dbde4cf 9293 int isfloat = 0;
43e65147 9294
16980d0b
JB		 9295 bits |= ((given >> 24) & 1) << 7;
9296 bits |= ((given >> 16) & 7) << 4;
9297 bits |= ((given >> 0) & 15) << 0;
43e65147 9298
16980d0b
JB		 9299 if (cmode < 8)
9300 {
9301 shift = (cmode >> 1) & 3;
fe56b6ce 9302 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9303 size = 32;
9304 }
9305 else if (cmode < 12)
9306 {
9307 shift = (cmode >> 1) & 1;
fe56b6ce 9308 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9309 size = 16;
9310 }
9311 else if (cmode < 14)
9312 {
9313 shift = (cmode & 1) + 1;
fe56b6ce 9314 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9315 value |= (1ul << (8 * shift)) - 1;
9316 size = 32;
9317 }
9318 else if (cmode == 14)
9319 {
9320 if (op)
9321 {
fe56b6ce 9322 /* Bit replication into bytes. */
16980d0b
JB		 9323 int ix;
9324 unsigned long mask;
43e65147 9325
16980d0b
JB		 9326 value = 0;
9327 hival = 0;
9328 for (ix = 7; ix >= 0; ix--)
9329 {
9330 mask = ((bits >> ix) & 1) ? 0xff : 0;
9331 if (ix <= 3)
9332 value = (value << 8) | mask;
9333 else
9334 hival = (hival << 8) | mask;
9335 }
9336 size = 64;
9337 }
9338 else
9339 {
fe56b6ce
NC		 9340 /* Byte replication. */
9341 value = (unsigned long) bits;
16980d0b
JB		 9342 size = 8;
9343 }
9344 }
9345 else if (!op)
9346 {
fe56b6ce 9347 /* Floating point encoding. */
16980d0b 9348 int tmp;
43e65147 9349
fe56b6ce
NC		 9350 value = (unsigned long) (bits & 0x7f) << 19;
9351 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9352 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9353 value |= (unsigned long) tmp << 24;
16980d0b 9354 size = 32;
0dbde4cf 9355 isfloat = 1;
16980d0b
JB		 9356 }
9357 else
9358 {
9359 func (stream, "<illegal constant %.8x:%x:%x>",
9360 bits, cmode, op);
9361 size = 32;
9362 break;
9363 }
9364 switch (size)
9365 {
9366 case 8:
9367 func (stream, "#%ld\t; 0x%.2lx", value, value);
9368 break;
43e65147 9369
16980d0b
JB		 9370 case 16:
9371 func (stream, "#%ld\t; 0x%.4lx", value, value);
9372 break;
9373
9374 case 32:
0dbde4cf
JB		 9375 if (isfloat)
9376 {
9377 unsigned char valbytes[4];
9378 double fvalue;
43e65147 9379
0dbde4cf
JB		 9380 /* Do this a byte at a time so we don't have to
9381 worry about the host's endianness. */
9382 valbytes[0] = value & 0xff;
9383 valbytes[1] = (value >> 8) & 0xff;
9384 valbytes[2] = (value >> 16) & 0xff;
9385 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9386
9387 floatformat_to_double
c1e26897
NC		 9388 (& floatformat_ieee_single_little, valbytes,
9389 & fvalue);
43e65147 9390
0dbde4cf
JB		 9391 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9392 value);
9393 }
9394 else
4e9d3b81 9395 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9396 (long) (((value & 0x80000000L) != 0)
9d82ec38 9397 ? value | ~0xffffffffL : value),
c1e26897 9398 value);
16980d0b
JB		 9399 break;
9400
9401 case 64:
9402 func (stream, "#0x%.8lx%.8lx", hival, value);
9403 break;
43e65147 9404
16980d0b
JB		 9405 default:
9406 abort ();
9407 }
9408 }
9409 break;
43e65147 9410
16980d0b
JB		 9411 case 'F':
9412 {
9413 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9414 int num = (given >> 8) & 0x3;
43e65147 9415
16980d0b
JB		 9416 if (!num)
9417 func (stream, "{d%d}", regno);
9418 else if (num + regno >= 32)
9419 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9420 else
9421 func (stream, "{d%d-d%d}", regno, regno + num);
9422 }
9423 break;
7e8e6784 9424
16980d0b
JB		 9425
9426 case '0': case '1': case '2': case '3': case '4':
9427 case '5': case '6': case '7': case '8': case '9':
9428 {
9429 int width;
9430 unsigned long value;
9431
9432 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9433
16980d0b
JB		 9434 switch (*c)
9435 {
9436 case 'r':
9437 func (stream, "%s", arm_regnames[value]);
9438 break;
9439 case 'd':
9440 func (stream, "%ld", value);
05413229 9441 value_in_comment = value;
16980d0b
JB		 9442 break;
9443 case 'e':
9444 func (stream, "%ld", (1ul << width) - value);
9445 break;
43e65147 9446
16980d0b
JB		 9447 case 'S':
9448 case 'T':
9449 case 'U':
05413229 9450 /* Various width encodings. */
16980d0b
JB		 9451 {
9452 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9453 int limit;
9454 unsigned low, high;
9455
9456 c++;
9457 if (*c >= '0' && *c <= '9')
9458 limit = *c - '0';
9459 else if (*c >= 'a' && *c <= 'f')
9460 limit = *c - 'a' + 10;
9461 else
9462 abort ();
9463 low = limit >> 2;
9464 high = limit & 3;
9465
9466 if (value < low || value > high)
9467 func (stream, "<illegal width %d>", base << value);
9468 else
9469 func (stream, "%d", base << value);
9470 }
9471 break;
9472 case 'R':
9473 if (given & (1 << 6))
9474 goto Q;
9475 /* FALLTHROUGH */
9476 case 'D':
9477 func (stream, "d%ld", value);
9478 break;
9479 case 'Q':
9480 Q:
9481 if (value & 1)
9482 func (stream, "<illegal reg q%ld.5>", value >> 1);
9483 else
9484 func (stream, "q%ld", value >> 1);
9485 break;
43e65147 9486
16980d0b
JB		 9487 case '`':
9488 c++;
9489 if (value == 0)
9490 func (stream, "%c", *c);
9491 break;
9492 case '\'':
9493 c++;
9494 if (value == ((1ul << width) - 1))
9495 func (stream, "%c", *c);
9496 break;
9497 case '?':
fe56b6ce 9498 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9499 c += 1 << width;
9500 break;
9501 default:
9502 abort ();
9503 }
16980d0b 9504 }
dffaa15c
AM		 9505 break;
9506
9507 default:
9508 abort ();
16980d0b
JB		 9509 }
9510 }
9511 else
9512 func (stream, "%c", *c);
9513 }
05413229
NC		 9514
9515 if (value_in_comment > 32 || value_in_comment < -16)
9516 func (stream, "\t; 0x%lx", value_in_comment);
9517
e2efe87d
MGD		 9518 if (is_unpredictable)
9519 func (stream, UNPREDICTABLE_INSTRUCTION);
9520
78933a4a 9521 return true;
16980d0b
JB		 9522 }
9523 }
78933a4a 9524 return false;
16980d0b
JB		 9525}
9526
73cd51e5
AV		 9527/* Print one mve instruction on INFO->STREAM.
9528 Return TRUE if the instuction matched, FALSE if this is not a
9529 recognised mve instruction. */
9530
78933a4a 9531static bool
73cd51e5
AV		 9532print_insn_mve (struct disassemble_info *info, long given)
9533{
9534 const struct mopcode32 *insn;
9535 void *stream = info->stream;
9536 fprintf_ftype func = info->fprintf_func;
9537
9538 for (insn = mve_opcodes; insn->assembler; insn++)
9539 {
9540 if (((given & insn->mask) == insn->value)
9541 && !is_mve_encoding_conflict (given, insn->mve_op))
9542 {
9543 signed long value_in_comment = 0;
78933a4a
AM		 9544 bool is_unpredictable = false;
9545 bool is_undefined = false;
73cd51e5
AV		 9546 const char *c;
9547 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9548 enum mve_undefined undefined_cond = UNDEF_NONE;
9549
9550 /* Most vector mve instruction are illegal in a it block.
9551 There are a few exceptions; check for them. */
9552 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9553 {
78933a4a 9554 is_unpredictable = true;
73cd51e5
AV		 9555 unpredictable_cond = UNPRED_IT_BLOCK;
9556 }
9557 else if (is_mve_unpredictable (given, insn->mve_op,
9558 &unpredictable_cond))
78933a4a 9559 is_unpredictable = true;
73cd51e5
AV		 9560
9561 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
78933a4a 9562 is_undefined = true;
73cd51e5 9563
c4a23bf8
SP		 9564 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9565 i.e "VMOV Qd, Qm". */
9566 if ((insn->mve_op == MVE_VORR_REG)
9567 && (arm_decode_field (given, 1, 3)
9568 == arm_decode_field (given, 17, 19)))
9569 continue;
9570
73cd51e5
AV		 9571 for (c = insn->assembler; *c; c++)
9572 {
9573 if (*c == '%')
9574 {
9575 switch (*++c)
9576 {
9577 case '%':
9578 func (stream, "%%");
9579 break;
9580
ef1576a1
AV		 9581 case 'a':
9582 /* Don't print anything for '+' as it is implied. */
9583 if (arm_decode_field (given, 23, 23) == 0)
9584 func (stream, "-");
9585 break;
9586
143275ea
AV		 9587 case 'c':
9588 if (ifthen_state)
9589 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9590 break;
9591
aef6d006
AV		 9592 case 'd':
9593 print_mve_vld_str_addr (info, given, insn->mve_op);
9594 break;
9595
143275ea
AV		 9596 case 'i':
9597 {
9598 long mve_mask = mve_extract_pred_mask (given);
9599 func (stream, "%s", mve_predicatenames[mve_mask]);
9600 }
9601 break;
9602
23d00a41
SD		 9603 case 'j':
9604 {
9605 unsigned int imm5 = 0;
9606 imm5 |= arm_decode_field (given, 6, 7);
9607 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9608 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9609 }
9610 break;
9611
08132bdd
SP		 9612 case 'k':
9613 func (stream, "#%u",
9614 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9615 break;
9616
143275ea
AV		 9617 case 'n':
9618 print_vec_condition (info, given, insn->mve_op);
9619 break;
9620
ef1576a1
AV		 9621 case 'o':
9622 if (arm_decode_field (given, 0, 0) == 1)
9623 {
9624 unsigned long size
9625 = arm_decode_field (given, 4, 4)
9626 | (arm_decode_field (given, 6, 6) << 1);
9627
9628 func (stream, ", uxtw #%lu", size);
9629 }
9630 break;
9631
bf0b396d
AV		 9632 case 'm':
9633 print_mve_rounding_mode (info, given, insn->mve_op);
9634 break;
9635
9636 case 's':
9637 print_mve_vcvt_size (info, given, insn->mve_op);
9638 break;
9639
aef6d006
AV		 9640 case 'u':
9641 {
c507f10b
AV		 9642 unsigned long op1 = arm_decode_field (given, 21, 22);
9643
9644 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9645 {
9646 /* Check for signed. */
9647 if (arm_decode_field (given, 23, 23) == 0)
9648 {
9649 /* We don't print 's' for S32. */
9650 if ((arm_decode_field (given, 5, 6) == 0)
9651 && ((op1 == 0) || (op1 == 1)))
9652 ;
9653 else
9654 func (stream, "s");
9655 }
9656 else
9657 func (stream, "u");
9658 }
aef6d006 9659 else
c507f10b
AV		 9660 {
9661 if (arm_decode_field (given, 28, 28) == 0)
9662 func (stream, "s");
9663 else
9664 func (stream, "u");
9665 }
aef6d006 9666 }
ef1576a1 9667 break;
aef6d006 9668
143275ea
AV		 9669 case 'v':
9670 print_instruction_predicate (info);
9671 break;
9672
04d54ace
AV		 9673 case 'w':
9674 if (arm_decode_field (given, 21, 21) == 1)
9675 func (stream, "!");
9676 break;
9677
9678 case 'B':
9679 print_mve_register_blocks (info, given, insn->mve_op);
9680 break;
9681
c507f10b
AV		 9682 case 'E':
9683 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9684
9685 print_simd_imm8 (info, given, 28, insn);
9686 break;
9687
9688 case 'N':
9689 print_mve_vmov_index (info, given);
9690 break;
9691
14925797
AV		 9692 case 'T':
9693 if (arm_decode_field (given, 12, 12) == 0)
9694 func (stream, "b");
9695 else
9696 func (stream, "t");
9697 break;
9698
d3b63143
AV		 9699 case 'X':
9700 if (arm_decode_field (given, 12, 12) == 1)
9701 func (stream, "x");
9702 break;
9703
143275ea
AV		 9704 case '0': case '1': case '2': case '3': case '4':
9705 case '5': case '6': case '7': case '8': case '9':
9706 {
9707 int width;
9708 unsigned long value;
9709
9710 c = arm_decode_bitfield (c, given, &value, &width);
9711
9712 switch (*c)
9713 {
9714 case 'Z':
9715 if (value == 13)
78933a4a 9716 is_unpredictable = true;
143275ea
AV		 9717 else if (value == 15)
9718 func (stream, "zr");
9719 else
9720 func (stream, "%s", arm_regnames[value]);
9721 break;
23d00a41 9722
e39c1607
SD		 9723 case 'c':
9724 func (stream, "%s", arm_conditional[value]);
9725 break;
9726
9727 case 'C':
9728 value ^= 1;
9729 func (stream, "%s", arm_conditional[value]);
9730 break;
9731
23d00a41
SD		 9732 case 'S':
9733 if (value == 13 || value == 15)
78933a4a 9734 is_unpredictable = true;
23d00a41
SD		 9735 else
9736 func (stream, "%s", arm_regnames[value]);
9737 break;
9738
143275ea
AV		 9739 case 's':
9740 print_mve_size (info,
9741 value,
9742 insn->mve_op);
9743 break;
66dcaa5d
AV		 9744 case 'I':
9745 if (value == 1)
9746 func (stream, "i");
9747 break;
d3b63143
AV		 9748 case 'A':
9749 if (value == 1)
9750 func (stream, "a");
9751 break;
1c8f2df8
AV		 9752 case 'h':
9753 {
9754 unsigned int odd_reg = (value << 1) | 1;
9755 func (stream, "%s", arm_regnames[odd_reg]);
9756 }
9757 break;
ef1576a1
AV		 9758 case 'i':
9759 {
9760 unsigned long imm
9761 = arm_decode_field (given, 0, 6);
9762 unsigned long mod_imm = imm;
9763
9764 switch (insn->mve_op)
9765 {
9766 case MVE_VLDRW_GATHER_T5:
9767 case MVE_VSTRW_SCATTER_T5:
9768 mod_imm = mod_imm << 2;
9769 break;
9770 case MVE_VSTRD_SCATTER_T6:
9771 case MVE_VLDRD_GATHER_T6:
9772 mod_imm = mod_imm << 3;
9773 break;
9774
9775 default:
9776 break;
9777 }
9778
9779 func (stream, "%lu", mod_imm);
9780 }
9781 break;
bf0b396d
AV		 9782 case 'k':
9783 func (stream, "%lu", 64 - value);
9784 break;
1c8f2df8
AV		 9785 case 'l':
9786 {
9787 unsigned int even_reg = value << 1;
9788 func (stream, "%s", arm_regnames[even_reg]);
9789 }
9790 break;
9791 case 'u':
9792 switch (value)
9793 {
9794 case 0:
9795 func (stream, "1");
9796 break;
9797 case 1:
9798 func (stream, "2");
9799 break;
9800 case 2:
9801 func (stream, "4");
9802 break;
9803 case 3:
9804 func (stream, "8");
9805 break;
9806 default:
9807 break;
9808 }
9809 break;
897b9bbc
AV		 9810 case 'o':
9811 print_mve_rotate (info, value, width);
9812 break;
9743db03
AV		 9813 case 'r':
9814 func (stream, "%s", arm_regnames[value]);
9815 break;
04d54ace 9816 case 'd':
ed63aa17
AV		 9817 if (insn->mve_op == MVE_VQSHL_T2
9818 || insn->mve_op == MVE_VQSHLU_T3
9819 || insn->mve_op == MVE_VRSHR
9820 || insn->mve_op == MVE_VRSHRN
9821 || insn->mve_op == MVE_VSHL_T1
9822 || insn->mve_op == MVE_VSHLL_T1
9823 || insn->mve_op == MVE_VSHR
9824 || insn->mve_op == MVE_VSHRN
9825 || insn->mve_op == MVE_VSLI
9826 || insn->mve_op == MVE_VSRI)
9827 print_mve_shift_n (info, given, insn->mve_op);
9828 else if (insn->mve_op == MVE_VSHLL_T2)
9829 {
9830 switch (value)
9831 {
9832 case 0x00:
9833 func (stream, "8");
9834 break;
9835 case 0x01:
9836 func (stream, "16");
9837 break;
9838 case 0x10:
9839 print_mve_undefined (info, UNDEF_SIZE_0);
9840 break;
9841 default:
9842 assert (0);
9843 break;
9844 }
9845 }
9846 else
9847 {
9848 if (insn->mve_op == MVE_VSHLC && value == 0)
9849 value = 32;
9850 func (stream, "%ld", value);
9851 value_in_comment = value;
9852 }
04d54ace 9853 break;
c507f10b
AV		 9854 case 'F':
9855 func (stream, "s%ld", value);
9856 break;
143275ea
AV		 9857 case 'Q':
9858 if (value & 0x8)
9859 func (stream, "<illegal reg q%ld.5>", value);
9860 else
9861 func (stream, "q%ld", value);
9862 break;
c507f10b
AV		 9863 case 'x':
9864 func (stream, "0x%08lx", value);
9865 break;
143275ea
AV		 9866 default:
9867 abort ();
9868 }
9869 break;
9870 default:
9871 abort ();
9872 }
73cd51e5
AV		 9873 }
9874 }
9875 else
9876 func (stream, "%c", *c);
9877 }
9878
9879 if (value_in_comment > 32 || value_in_comment < -16)
9880 func (stream, "\t; 0x%lx", value_in_comment);
9881
9882 if (is_unpredictable)
9883 print_mve_unpredictable (info, unpredictable_cond);
9884
9885 if (is_undefined)
9886 print_mve_undefined (info, undefined_cond);
9887
63b4cc53 9888 if (!vpt_block_state.in_vpt_block
143275ea 9889 && !ifthen_state
63b4cc53 9890 && is_vpt_instruction (given))
143275ea 9891 mark_inside_vpt_block (given);
63b4cc53 9892 else if (vpt_block_state.in_vpt_block)
143275ea
AV		 9893 update_vpt_block_state ();
9894
78933a4a 9895 return true;
73cd51e5
AV		 9896 }
9897 }
78933a4a 9898 return false;
73cd51e5
AV		 9899}
9900
9901
90ec0d68
MGD		 9902/* Return the name of a v7A special register. */
9903
43e65147 9904static const char *
90ec0d68
MGD		 9905banked_regname (unsigned reg)
9906{
9907 switch (reg)
9908 {
9909 case 15: return "CPSR";
43e65147 9910 case 32: return "R8_usr";
90ec0d68
MGD		 9911 case 33: return "R9_usr";
9912 case 34: return "R10_usr";
9913 case 35: return "R11_usr";
9914 case 36: return "R12_usr";
9915 case 37: return "SP_usr";
9916 case 38: return "LR_usr";
43e65147 9917 case 40: return "R8_fiq";
90ec0d68
MGD		 9918 case 41: return "R9_fiq";
9919 case 42: return "R10_fiq";
9920 case 43: return "R11_fiq";
9921 case 44: return "R12_fiq";
9922 case 45: return "SP_fiq";
9923 case 46: return "LR_fiq";
9924 case 48: return "LR_irq";
9925 case 49: return "SP_irq";
9926 case 50: return "LR_svc";
9927 case 51: return "SP_svc";
9928 case 52: return "LR_abt";
9929 case 53: return "SP_abt";
9930 case 54: return "LR_und";
9931 case 55: return "SP_und";
9932 case 60: return "LR_mon";
9933 case 61: return "SP_mon";
9934 case 62: return "ELR_hyp";
9935 case 63: return "SP_hyp";
9936 case 79: return "SPSR";
9937 case 110: return "SPSR_fiq";
9938 case 112: return "SPSR_irq";
9939 case 114: return "SPSR_svc";
9940 case 116: return "SPSR_abt";
9941 case 118: return "SPSR_und";
9942 case 124: return "SPSR_mon";
9943 case 126: return "SPSR_hyp";
9944 default: return NULL;
9945 }
9946}
9947
e797f7e0
MGD		 9948/* Return the name of the DMB/DSB option. */
9949static const char *
9950data_barrier_option (unsigned option)
9951{
9952 switch (option & 0xf)
9953 {
9954 case 0xf: return "sy";
9955 case 0xe: return "st";
9956 case 0xd: return "ld";
9957 case 0xb: return "ish";
9958 case 0xa: return "ishst";
9959 case 0x9: return "ishld";
9960 case 0x7: return "un";
9961 case 0x6: return "unst";
9962 case 0x5: return "nshld";
9963 case 0x3: return "osh";
9964 case 0x2: return "oshst";
9965 case 0x1: return "oshld";
9966 default: return NULL;
9967 }
9968}
9969
4a5329c6
ZW		 9970/* Print one ARM instruction from PC on INFO->STREAM. */
9971
9972static void
9973print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9974{
6b5d3a4d 9975 const struct opcode32 *insn;
6a51a8a8 9976 void *stream = info->stream;
6b5d3a4d 9977 fprintf_ftype func = info->fprintf_func;
b0e28b39 9978 struct arm_private_data *private_data = info->private_data;
252b5132 9979
78933a4a 9980 if (print_insn_coprocessor (pc, info, given, false))
16980d0b
JB		 9981 return;
9982
78933a4a 9983 if (print_insn_neon (info, given, false))
8f06b2d8
PB		 9984 return;
9985
78933a4a 9986 if (print_insn_generic_coprocessor (pc, info, given, false))
33593eaf
MM		 9987 return;
9988
252b5132
RH		 9989 for (insn = arm_opcodes; insn->assembler; insn++)
9990 {
0313a2b8
NC		 9991 if ((given & insn->mask) != insn->value)
9992 continue;
823d2571
TG		 9993
9994 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9995 continue;
9996
9997 /* Special case: an instruction with all bits set in the condition field
9998 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9999 or by the catchall at the end of the table. */
10000 if ((given & 0xF0000000) != 0xF0000000
10001 || (insn->mask & 0xF0000000) == 0xF0000000
10002 || (insn->mask == 0 && insn->value == 0))
252b5132 10003 {
ff4a8d2b
NC		 10004 unsigned long u_reg = 16;
10005 unsigned long U_reg = 16;
78933a4a 10006 bool is_unpredictable = false;
05413229 10007 signed long value_in_comment = 0;
6b5d3a4d 10008 const char *c;
b34976b6 10009
252b5132
RH		 10010 for (c = insn->assembler; *c; c++)
10011 {
10012 if (*c == '%')
10013 {
78933a4a 10014 bool allow_unpredictable = false;
c1e26897 10015
252b5132
RH		 10016 switch (*++c)
10017 {
10018 case '%':
10019 func (stream, "%%");
10020 break;
10021
10022 case 'a':
05413229 10023 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10024 break;
252b5132 10025
62b3e311
PB		 10026 case 'P':
10027 /* Set P address bit and use normal address
10028 printing routine. */
c1e26897 10029 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10030 break;
10031
c1e26897 10032 case 'S':
78933a4a 10033 allow_unpredictable = true;
1a0670f3 10034 /* Fall through. */
252b5132
RH		 10035 case 's':
10036 if ((given & 0x004f0000) == 0x004f0000)
10037 {
58efb6c0 10038 /* PC relative with immediate offset. */
f8b960bc 10039 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10040
aefd8a40
NC		 10041 if (PRE_BIT_SET)
10042 {
26d97720
NS		 10043 /* Elide positive zero offset. */
10044 if (offset || NEGATIVE_BIT_SET)
10045 func (stream, "[pc, #%s%d]\t; ",
d908c8af 10046 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 10047 else
26d97720
NS		 10048 func (stream, "[pc]\t; ");
10049 if (NEGATIVE_BIT_SET)
10050 offset = -offset;
aefd8a40
NC		 10051 info->print_address_func (offset + pc + 8, info);
10052 }
10053 else
10054 {
26d97720
NS		 10055 /* Always show the offset. */
10056 func (stream, "[pc], #%s%d",
d908c8af 10057 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b 10058 if (! allow_unpredictable)
78933a4a 10059 is_unpredictable = true;
aefd8a40 10060 }
252b5132
RH		 10061 }
10062 else
10063 {
fe56b6ce
NC		 10064 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10065
b34976b6 10066 func (stream, "[%s",
252b5132 10067 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10068
c1e26897 10069 if (PRE_BIT_SET)
252b5132 10070 {
c1e26897 10071 if (IMMEDIATE_BIT_SET)
252b5132 10072 {
26d97720
NS		 10073 /* Elide offset for non-writeback
10074 positive zero. */
10075 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10076 || offset)
10077 func (stream, ", #%s%d",
10078 NEGATIVE_BIT_SET ? "-" : "", offset);
10079
10080 if (NEGATIVE_BIT_SET)
10081 offset = -offset;
945ee430 10082
fe56b6ce 10083 value_in_comment = offset;
252b5132 10084 }
945ee430 10085 else
ff4a8d2b
NC		 10086 {
10087 /* Register Offset or Register Pre-Indexed. */
10088 func (stream, ", %s%s",
10089 NEGATIVE_BIT_SET ? "-" : "",
10090 arm_regnames[given & 0xf]);
10091
10092 /* Writing back to the register that is the source/
10093 destination of the load/store is unpredictable. */
10094 if (! allow_unpredictable
10095 && WRITEBACK_BIT_SET
10096 && ((given & 0xf) == ((given >> 12) & 0xf)))
78933a4a 10097 is_unpredictable = true;
ff4a8d2b 10098 }
252b5132 10099
b34976b6 10100 func (stream, "]%s",
c1e26897 10101 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10102 }
945ee430 10103 else
252b5132 10104 {
c1e26897 10105 if (IMMEDIATE_BIT_SET)
252b5132 10106 {
945ee430 10107 /* Immediate Post-indexed. */
aefd8a40 10108 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 10109 func (stream, "], #%s%d",
10110 NEGATIVE_BIT_SET ? "-" : "", offset);
10111 if (NEGATIVE_BIT_SET)
10112 offset = -offset;
fe56b6ce 10113 value_in_comment = offset;
252b5132 10114 }
945ee430 10115 else
ff4a8d2b
NC		 10116 {
10117 /* Register Post-indexed. */
10118 func (stream, "], %s%s",
10119 NEGATIVE_BIT_SET ? "-" : "",
10120 arm_regnames[given & 0xf]);
10121
10122 /* Writing back to the register that is the source/
10123 destination of the load/store is unpredictable. */
10124 if (! allow_unpredictable
10125 && (given & 0xf) == ((given >> 12) & 0xf))
78933a4a 10126 is_unpredictable = true;
ff4a8d2b 10127 }
c1e26897 10128
07a28fab
NC		 10129 if (! allow_unpredictable)
10130 {
10131 /* Writeback is automatically implied by post- addressing.
10132 Setting the W bit is unnecessary and ARM specify it as
10133 being unpredictable. */
10134 if (WRITEBACK_BIT_SET
10135 /* Specifying the PC register as the post-indexed
10136 registers is also unpredictable. */
ab8e2090 10137 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
78933a4a 10138 is_unpredictable = true;
07a28fab 10139 }
252b5132
RH		 10140 }
10141 }
10142 break;
b34976b6 10143
252b5132 10144 case 'b':
6b5d3a4d 10145 {
f8b960bc 10146 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10147 bfd_vma target = disp * 4 + pc + 8;
10148 info->print_address_func (target, info);
10149
10150 /* Fill in instruction information. */
10151 info->insn_info_valid = 1;
10152 info->insn_type = dis_branch;
10153 info->target = target;
6b5d3a4d 10154 }
252b5132
RH		 10155 break;
10156
10157 case 'c':
c22aaad1
PB		 10158 if (((given >> 28) & 0xf) != 0xe)
10159 func (stream, "%s",
10160 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10161 break;
10162
10163 case 'm':
10164 {
10165 int started = 0;
10166 int reg;
10167
10168 func (stream, "{");
10169 for (reg = 0; reg < 16; reg++)
10170 if ((given & (1 << reg)) != 0)
10171 {
10172 if (started)
10173 func (stream, ", ");
10174 started = 1;
10175 func (stream, "%s", arm_regnames[reg]);
10176 }
10177 func (stream, "}");
ab8e2090 10178 if (! started)
78933a4a 10179 is_unpredictable = true;
252b5132
RH		 10180 }
10181 break;
10182
37b37b2d 10183 case 'q':
78933a4a 10184 arm_decode_shift (given, func, stream, false);
37b37b2d
RE		 10185 break;
10186
252b5132
RH		 10187 case 'o':
10188 if ((given & 0x02000000) != 0)
10189 {
a415b1cd
JB		 10190 unsigned int rotate = (given & 0xf00) >> 7;
10191 unsigned int immed = (given & 0xff);
10192 unsigned int a, i;
10193
ebd1c6d1
AM		 10194 a = (immed << ((32 - rotate) & 31)
10195 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10196 /* If there is another encoding with smaller rotate,
10197 the rotate should be specified directly. */
10198 for (i = 0; i < 32; i += 2)
ebd1c6d1 10199 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10200 break;
10201
10202 if (i != rotate)
10203 func (stream, "#%d, %d", immed, rotate);
10204 else
10205 func (stream, "#%d", a);
10206 value_in_comment = a;
252b5132
RH		 10207 }
10208 else
78933a4a 10209 arm_decode_shift (given, func, stream, true);
252b5132
RH		 10210 break;
10211
10212 case 'p':
10213 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10214 {
823d2571
TG		 10215 arm_feature_set arm_ext_v6 =
10216 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10217
aefd8a40
NC		 10218 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10219 mechanism for setting PSR flag bits. They are
10220 obsolete in V6 onwards. */
823d2571
TG		 10221 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10222 arm_ext_v6))
aefd8a40 10223 func (stream, "p");
4ab90a7a 10224 else
78933a4a 10225 is_unpredictable = true;
aefd8a40 10226 }
252b5132
RH		 10227 break;
10228
10229 case 't':
10230 if ((given & 0x01200000) == 0x00200000)
10231 func (stream, "t");
10232 break;
10233
252b5132 10234 case 'A':
05413229
NC		 10235 {
10236 int offset = given & 0xff;
f02232aa 10237
05413229 10238 value_in_comment = offset * 4;
c1e26897 10239 if (NEGATIVE_BIT_SET)
05413229 10240 value_in_comment = - value_in_comment;
f02232aa 10241
05413229 10242 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 10243
c1e26897 10244 if (PRE_BIT_SET)
05413229
NC		 10245 {
10246 if (offset)
fe56b6ce 10247 func (stream, ", #%d]%s",
d908c8af 10248 (int) value_in_comment,
c1e26897 10249 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 10250 else
10251 func (stream, "]");
10252 }
10253 else
10254 {
10255 func (stream, "]");
f02232aa 10256
c1e26897 10257 if (WRITEBACK_BIT_SET)
05413229
NC		 10258 {
10259 if (offset)
d908c8af 10260 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 10261 }
10262 else
fe56b6ce 10263 {
d908c8af 10264 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10265 value_in_comment = offset;
10266 }
05413229
NC		 10267 }
10268 }
252b5132
RH		 10269 break;
10270
077b8428
NC		 10271 case 'B':
10272 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10273 {
10274 bfd_vma address;
10275 bfd_vma offset = 0;
b34976b6 10276
c1e26897 10277 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10278 /* Is signed, hi bits should be ones. */
10279 offset = (-1) ^ 0x00ffffff;
10280
10281 /* Offset is (SignExtend(offset field)<<2). */
10282 offset += given & 0x00ffffff;
10283 offset <<= 2;
10284 address = offset + pc + 8;
b34976b6 10285
8f06b2d8
PB		 10286 if (given & 0x01000000)
10287 /* H bit allows addressing to 2-byte boundaries. */
10288 address += 2;
b1ee46c5 10289
8f06b2d8 10290 info->print_address_func (address, info);
1d67fe3b
TT		 10291
10292 /* Fill in instruction information. */
10293 info->insn_info_valid = 1;
10294 info->insn_type = dis_branch;
10295 info->target = address;
b1ee46c5 10296 }
b1ee46c5
AH		 10297 break;
10298
252b5132 10299 case 'C':
90ec0d68
MGD		 10300 if ((given & 0x02000200) == 0x200)
10301 {
10302 const char * name;
10303 unsigned sysm = (given & 0x004f0000) >> 16;
10304
10305 sysm |= (given & 0x300) >> 4;
10306 name = banked_regname (sysm);
10307
10308 if (name != NULL)
10309 func (stream, "%s", name);
10310 else
d908c8af 10311 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10312 }
10313 else
10314 {
43e65147 10315 func (stream, "%cPSR_",
90ec0d68
MGD		 10316 (given & 0x00400000) ? 'S' : 'C');
10317 if (given & 0x80000)
10318 func (stream, "f");
10319 if (given & 0x40000)
10320 func (stream, "s");
10321 if (given & 0x20000)
10322 func (stream, "x");
10323 if (given & 0x10000)
10324 func (stream, "c");
10325 }
252b5132
RH		 10326 break;
10327
62b3e311 10328 case 'U':
43e65147 10329 if ((given & 0xf0) == 0x60)
62b3e311 10330 {
52e7f43d
RE		 10331 switch (given & 0xf)
10332 {
10333 case 0xf: func (stream, "sy"); break;
10334 default:
10335 func (stream, "#%d", (int) given & 0xf);
10336 break;
10337 }
43e65147
L		 10338 }
10339 else
52e7f43d 10340 {
e797f7e0
MGD		 10341 const char * opt = data_barrier_option (given & 0xf);
10342 if (opt != NULL)
10343 func (stream, "%s", opt);
10344 else
52e7f43d 10345 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10346 }
10347 break;
10348
b34976b6 10349 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10350 case '5': case '6': case '7': case '8': case '9':
10351 {
16980d0b
JB		 10352 int width;
10353 unsigned long value;
252b5132 10354
16980d0b 10355 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10356
252b5132
RH		 10357 switch (*c)
10358 {
ab8e2090
NC		 10359 case 'R':
10360 if (value == 15)
78933a4a 10361 is_unpredictable = true;
ab8e2090 10362 /* Fall through. */
16980d0b 10363 case 'r':
9eb6c0f1
MGD		 10364 case 'T':
10365 /* We want register + 1 when decoding T. */
10366 if (*c == 'T')
2bddb71a 10367 value = (value + 1) & 0xf;
9eb6c0f1 10368
ff4a8d2b
NC		 10369 if (c[1] == 'u')
10370 {
10371 /* Eat the 'u' character. */
10372 ++ c;
10373
10374 if (u_reg == value)
78933a4a 10375 is_unpredictable = true;
ff4a8d2b
NC		 10376 u_reg = value;
10377 }
10378 if (c[1] == 'U')
10379 {
10380 /* Eat the 'U' character. */
10381 ++ c;
10382
10383 if (U_reg == value)
78933a4a 10384 is_unpredictable = true;
ff4a8d2b
NC		 10385 U_reg = value;
10386 }
16980d0b
JB		 10387 func (stream, "%s", arm_regnames[value]);
10388 break;
10389 case 'd':
10390 func (stream, "%ld", value);
05413229 10391 value_in_comment = value;
16980d0b
JB		 10392 break;
10393 case 'b':
10394 func (stream, "%ld", value * 8);
05413229 10395 value_in_comment = value * 8;
16980d0b
JB		 10396 break;
10397 case 'W':
10398 func (stream, "%ld", value + 1);
05413229 10399 value_in_comment = value + 1;
16980d0b
JB		 10400 break;
10401 case 'x':
10402 func (stream, "0x%08lx", value);
10403
10404 /* Some SWI instructions have special
10405 meanings. */
10406 if ((given & 0x0fffffff) == 0x0FF00000)
10407 func (stream, "\t; IMB");
10408 else if ((given & 0x0fffffff) == 0x0FF00001)
10409 func (stream, "\t; IMBRange");
10410 break;
10411 case 'X':
10412 func (stream, "%01lx", value & 0xf);
05413229 10413 value_in_comment = value;
252b5132
RH		 10414 break;
10415 case '`':
10416 c++;
16980d0b 10417 if (value == 0)
252b5132
RH		 10418 func (stream, "%c", *c);
10419 break;
10420 case '\'':
10421 c++;
16980d0b 10422 if (value == ((1ul << width) - 1))
252b5132
RH		 10423 func (stream, "%c", *c);
10424 break;
10425 case '?':
fe56b6ce 10426 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10427 c += 1 << width;
252b5132
RH		 10428 break;
10429 default:
10430 abort ();
10431 }
dffaa15c
AM		 10432 }
10433 break;
0dd132b6 10434
dffaa15c
AM		 10435 case 'e':
10436 {
10437 int imm;
0dd132b6 10438
dffaa15c
AM		 10439 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10440 func (stream, "%d", imm);
10441 value_in_comment = imm;
10442 }
10443 break;
fe56b6ce 10444
dffaa15c
AM		 10445 case 'E':
10446 /* LSB and WIDTH fields of BFI or BFC. The machine-
10447 language instruction encodes LSB and MSB. */
10448 {
10449 long msb = (given & 0x001f0000) >> 16;
10450 long lsb = (given & 0x00000f80) >> 7;
10451 long w = msb - lsb + 1;
0a003adc 10452
dffaa15c
AM		 10453 if (w > 0)
10454 func (stream, "#%lu, #%lu", lsb, w);
10455 else
10456 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10457 }
10458 break;
90ec0d68 10459
dffaa15c
AM		 10460 case 'R':
10461 /* Get the PSR/banked register name. */
10462 {
10463 const char * name;
10464 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10465
dffaa15c
AM		 10466 sysm |= (given & 0x300) >> 4;
10467 name = banked_regname (sysm);
90ec0d68 10468
dffaa15c
AM		 10469 if (name != NULL)
10470 func (stream, "%s", name);
10471 else
10472 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10473 }
10474 break;
fe56b6ce 10475
dffaa15c
AM		 10476 case 'V':
10477 /* 16-bit unsigned immediate from a MOVT or MOVW
10478 instruction, encoded in bits 0:11 and 15:19. */
10479 {
10480 long hi = (given & 0x000f0000) >> 4;
10481 long lo = (given & 0x00000fff);
10482 long imm16 = hi | lo;
0a003adc 10483
dffaa15c
AM		 10484 func (stream, "#%lu", imm16);
10485 value_in_comment = imm16;
252b5132 10486 }
dffaa15c
AM		 10487 break;
10488
10489 default:
10490 abort ();
252b5132
RH		 10491 }
10492 }
10493 else
10494 func (stream, "%c", *c);
10495 }
05413229
NC		 10496
10497 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10498 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10499
10500 if (is_unpredictable)
10501 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10502
4a5329c6 10503 return;
252b5132
RH		 10504 }
10505 }
0b347048
TC		 10506 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10507 return;
252b5132
RH		 10508}
10509
4a5329c6 10510/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10511
4a5329c6
ZW		 10512static void
10513print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10514{
6b5d3a4d 10515 const struct opcode16 *insn;
6a51a8a8
AM		 10516 void *stream = info->stream;
10517 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10518
10519 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10520 if ((given & insn->mask) == insn->value)
10521 {
05413229 10522 signed long value_in_comment = 0;
6b5d3a4d 10523 const char *c = insn->assembler;
05413229 10524
c19d1205
ZW		 10525 for (; *c; c++)
10526 {
10527 int domaskpc = 0;
10528 int domasklr = 0;
10529
10530 if (*c != '%')
10531 {
10532 func (stream, "%c", *c);
10533 continue;
10534 }
252b5132 10535
c19d1205
ZW		 10536 switch (*++c)
10537 {
10538 case '%':
10539 func (stream, "%%");
10540 break;
b34976b6 10541
c22aaad1
PB		 10542 case 'c':
10543 if (ifthen_state)
10544 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10545 break;
10546
10547 case 'C':
10548 if (ifthen_state)
10549 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10550 else
10551 func (stream, "s");
10552 break;
10553
10554 case 'I':
10555 {
10556 unsigned int tmp;
10557
10558 ifthen_next_state = given & 0xff;
10559 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10560 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10561 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10562 }
10563 break;
10564
10565 case 'x':
10566 if (ifthen_next_state)
10567 func (stream, "\t; unpredictable branch in IT block\n");
10568 break;
10569
10570 case 'X':
10571 if (ifthen_state)
10572 func (stream, "\t; unpredictable <IT:%s>",
10573 arm_conditional[IFTHEN_COND]);
10574 break;
10575
c19d1205
ZW		 10576 case 'S':
10577 {
10578 long reg;
10579
10580 reg = (given >> 3) & 0x7;
10581 if (given & (1 << 6))
10582 reg += 8;
4f3c3dbb 10583
c19d1205
ZW		 10584 func (stream, "%s", arm_regnames[reg]);
10585 }
10586 break;
baf0cc5e 10587
c19d1205 10588 case 'D':
4f3c3dbb 10589 {
c19d1205
ZW		 10590 long reg;
10591
10592 reg = given & 0x7;
10593 if (given & (1 << 7))
10594 reg += 8;
10595
10596 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10597 }
c19d1205
ZW		 10598 break;
10599
10600 case 'N':
10601 if (given & (1 << 8))
10602 domasklr = 1;
10603 /* Fall through. */
10604 case 'O':
10605 if (*c == 'O' && (given & (1 << 8)))
10606 domaskpc = 1;
10607 /* Fall through. */
10608 case 'M':
10609 {
10610 int started = 0;
10611 int reg;
10612
10613 func (stream, "{");
10614
10615 /* It would be nice if we could spot
10616 ranges, and generate the rS-rE format: */
10617 for (reg = 0; (reg < 8); reg++)
10618 if ((given & (1 << reg)) != 0)
10619 {
10620 if (started)
10621 func (stream, ", ");
10622 started = 1;
10623 func (stream, "%s", arm_regnames[reg]);
10624 }
10625
10626 if (domasklr)
10627 {
10628 if (started)
10629 func (stream, ", ");
10630 started = 1;
d908c8af 10631 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10632 }
10633
10634 if (domaskpc)
10635 {
10636 if (started)
10637 func (stream, ", ");
d908c8af 10638 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10639 }
10640
10641 func (stream, "}");
10642 }
10643 break;
10644
4547cb56
NC		 10645 case 'W':
10646 /* Print writeback indicator for a LDMIA. We are doing a
10647 writeback if the base register is not in the register
10648 mask. */
10649 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10650 func (stream, "!");
dffaa15c 10651 break;
4547cb56 10652
c19d1205
ZW		 10653 case 'b':
10654 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10655 {
10656 bfd_vma address = (pc + 4
10657 + ((given & 0x00f8) >> 2)
10658 + ((given & 0x0200) >> 3));
10659 info->print_address_func (address, info);
1d67fe3b
TT		 10660
10661 /* Fill in instruction information. */
10662 info->insn_info_valid = 1;
10663 info->insn_type = dis_branch;
10664 info->target = address;
c19d1205
ZW		 10665 }
10666 break;
10667
10668 case 's':
10669 /* Right shift immediate -- bits 6..10; 1-31 print
10670 as themselves, 0 prints as 32. */
10671 {
10672 long imm = (given & 0x07c0) >> 6;
10673 if (imm == 0)
10674 imm = 32;
0fd3a477 10675 func (stream, "#%ld", imm);
c19d1205
ZW		 10676 }
10677 break;
10678
10679 case '0': case '1': case '2': case '3': case '4':
10680 case '5': case '6': case '7': case '8': case '9':
10681 {
10682 int bitstart = *c++ - '0';
10683 int bitend = 0;
10684
10685 while (*c >= '0' && *c <= '9')
10686 bitstart = (bitstart * 10) + *c++ - '0';
10687
10688 switch (*c)
10689 {
10690 case '-':
10691 {
f8b960bc 10692 bfd_vma reg;
c19d1205
ZW		 10693
10694 c++;
10695 while (*c >= '0' && *c <= '9')
10696 bitend = (bitend * 10) + *c++ - '0';
10697 if (!bitend)
10698 abort ();
10699 reg = given >> bitstart;
10700 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10701
c19d1205
ZW		 10702 switch (*c)
10703 {
10704 case 'r':
10705 func (stream, "%s", arm_regnames[reg]);
10706 break;
10707
10708 case 'd':
d908c8af 10709 func (stream, "%ld", (long) reg);
05413229 10710 value_in_comment = reg;
c19d1205
ZW		 10711 break;
10712
10713 case 'H':
d908c8af 10714 func (stream, "%ld", (long) (reg << 1));
05413229 10715 value_in_comment = reg << 1;
c19d1205
ZW		 10716 break;
10717
10718 case 'W':
d908c8af 10719 func (stream, "%ld", (long) (reg << 2));
05413229 10720 value_in_comment = reg << 2;
c19d1205
ZW		 10721 break;
10722
10723 case 'a':
10724 /* PC-relative address -- the bottom two
10725 bits of the address are dropped
10726 before the calculation. */
10727 info->print_address_func
10728 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10729 value_in_comment = 0;
c19d1205
ZW		 10730 break;
10731
10732 case 'x':
d908c8af 10733 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10734 break;
10735
c19d1205
ZW		 10736 case 'B':
10737 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10738 bfd_vma target = reg * 2 + pc + 4;
10739 info->print_address_func (target, info);
05413229 10740 value_in_comment = 0;
1d67fe3b
TT		 10741
10742 /* Fill in instruction information. */
10743 info->insn_info_valid = 1;
10744 info->insn_type = dis_branch;
10745 info->target = target;
c19d1205
ZW		 10746 break;
10747
10748 case 'c':
c22aaad1 10749 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10750 break;
10751
10752 default:
10753 abort ();
10754 }
10755 }
10756 break;
10757
10758 case '\'':
10759 c++;
10760 if ((given & (1 << bitstart)) != 0)
10761 func (stream, "%c", *c);
10762 break;
10763
10764 case '?':
10765 ++c;
10766 if ((given & (1 << bitstart)) != 0)
10767 func (stream, "%c", *c++);
10768 else
10769 func (stream, "%c", *++c);
10770 break;
10771
10772 default:
10773 abort ();
10774 }
10775 }
10776 break;
10777
10778 default:
10779 abort ();
10780 }
10781 }
05413229
NC		 10782
10783 if (value_in_comment > 32 || value_in_comment < -16)
10784 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10785 return;
c19d1205
ZW		 10786 }
10787
10788 /* No match. */
0b347048
TC		 10789 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10790 return;
c19d1205
ZW		 10791}
10792
62b3e311 10793/* Return the name of an V7M special register. */
fe56b6ce 10794
62b3e311
PB		 10795static const char *
10796psr_name (int regno)
10797{
10798 switch (regno)
10799 {
1a336194
TP		 10800 case 0x0: return "APSR";
10801 case 0x1: return "IAPSR";
10802 case 0x2: return "EAPSR";
10803 case 0x3: return "PSR";
10804 case 0x5: return "IPSR";
10805 case 0x6: return "EPSR";
10806 case 0x7: return "IEPSR";
10807 case 0x8: return "MSP";
10808 case 0x9: return "PSP";
10809 case 0xa: return "MSPLIM";
10810 case 0xb: return "PSPLIM";
10811 case 0x10: return "PRIMASK";
10812 case 0x11: return "BASEPRI";
10813 case 0x12: return "BASEPRI_MAX";
10814 case 0x13: return "FAULTMASK";
10815 case 0x14: return "CONTROL";
16a1fa25
TP		 10816 case 0x88: return "MSP_NS";
10817 case 0x89: return "PSP_NS";
1a336194
TP		 10818 case 0x8a: return "MSPLIM_NS";
10819 case 0x8b: return "PSPLIM_NS";
10820 case 0x90: return "PRIMASK_NS";
10821 case 0x91: return "BASEPRI_NS";
10822 case 0x93: return "FAULTMASK_NS";
10823 case 0x94: return "CONTROL_NS";
10824 case 0x98: return "SP_NS";
62b3e311
PB		 10825 default: return "<unknown>";
10826 }
10827}
10828
4a5329c6
ZW		 10829/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10830
10831static void
10832print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10833{
6b5d3a4d 10834 const struct opcode32 *insn;
c19d1205
ZW		 10835 void *stream = info->stream;
10836 fprintf_ftype func = info->fprintf_func;
78933a4a 10837 bool is_mve = is_mve_architecture (info);
c19d1205 10838
78933a4a 10839 if (print_insn_coprocessor (pc, info, given, true))
16980d0b
JB		 10840 return;
10841
78933a4a 10842 if (!is_mve && print_insn_neon (info, given, true))
73cd51e5
AV		 10843 return;
10844
10845 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10846 return;
10847
78933a4a 10848 if (print_insn_cde (info, given, true))
4934a27c
MM		 10849 return;
10850
78933a4a 10851 if (print_insn_generic_coprocessor (pc, info, given, true))
33593eaf
MM		 10852 return;
10853
c19d1205
ZW		 10854 for (insn = thumb32_opcodes; insn->assembler; insn++)
10855 if ((given & insn->mask) == insn->value)
10856 {
78933a4a
AM		 10857 bool is_clrm = false;
10858 bool is_unpredictable = false;
05413229 10859 signed long value_in_comment = 0;
6b5d3a4d 10860 const char *c = insn->assembler;
05413229 10861
c19d1205
ZW		 10862 for (; *c; c++)
10863 {
10864 if (*c != '%')
10865 {
10866 func (stream, "%c", *c);
10867 continue;
10868 }
10869
10870 switch (*++c)
10871 {
10872 case '%':
10873 func (stream, "%%");
10874 break;
10875
c22aaad1
PB		 10876 case 'c':
10877 if (ifthen_state)
10878 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10879 break;
10880
10881 case 'x':
10882 if (ifthen_next_state)
10883 func (stream, "\t; unpredictable branch in IT block\n");
10884 break;
10885
10886 case 'X':
10887 if (ifthen_state)
10888 func (stream, "\t; unpredictable <IT:%s>",
10889 arm_conditional[IFTHEN_COND]);
10890 break;
10891
c19d1205
ZW		 10892 case 'I':
10893 {
10894 unsigned int imm12 = 0;
fe56b6ce 10895
c19d1205
ZW		 10896 imm12 |= (given & 0x000000ffu);
10897 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10898 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10899 func (stream, "#%u", imm12);
10900 value_in_comment = imm12;
c19d1205
ZW		 10901 }
10902 break;
10903
10904 case 'M':
10905 {
10906 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10907
c19d1205
ZW		 10908 bits |= (given & 0x000000ffu);
10909 bits |= (given & 0x00007000u) >> 4;
10910 bits |= (given & 0x04000000u) >> 15;
10911 imm8 = (bits & 0x0ff);
10912 mod = (bits & 0xf00) >> 8;
10913 switch (mod)
10914 {
10915 case 0: imm = imm8; break;
c1e26897
NC		 10916 case 1: imm = ((imm8 << 16) | imm8); break;
10917 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10918 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10919 default:
10920 mod = (bits & 0xf80) >> 7;
10921 imm8 = (bits & 0x07f) | 0x80;
10922 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10923 }
fe56b6ce
NC		 10924 func (stream, "#%u", imm);
10925 value_in_comment = imm;
c19d1205
ZW		 10926 }
10927 break;
43e65147 10928
c19d1205
ZW		 10929 case 'J':
10930 {
10931 unsigned int imm = 0;
fe56b6ce 10932
c19d1205
ZW		 10933 imm |= (given & 0x000000ffu);
10934 imm |= (given & 0x00007000u) >> 4;
10935 imm |= (given & 0x04000000u) >> 15;
10936 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10937 func (stream, "#%u", imm);
10938 value_in_comment = imm;
c19d1205
ZW		 10939 }
10940 break;
10941
10942 case 'K':
10943 {
10944 unsigned int imm = 0;
fe56b6ce 10945
c19d1205
ZW		 10946 imm |= (given & 0x000f0000u) >> 16;
10947 imm |= (given & 0x00000ff0u) >> 0;
10948 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10949 func (stream, "#%u", imm);
10950 value_in_comment = imm;
c19d1205
ZW		 10951 }
10952 break;
10953
74db7efb
NC		 10954 case 'H':
10955 {
10956 unsigned int imm = 0;
10957
10958 imm |= (given & 0x000f0000u) >> 4;
10959 imm |= (given & 0x00000fffu) >> 0;
10960 func (stream, "#%u", imm);
10961 value_in_comment = imm;
10962 }
10963 break;
10964
90ec0d68
MGD		 10965 case 'V':
10966 {
10967 unsigned int imm = 0;
10968
10969 imm |= (given & 0x00000fffu);
10970 imm |= (given & 0x000f0000u) >> 4;
10971 func (stream, "#%u", imm);
10972 value_in_comment = imm;
10973 }
10974 break;
10975
c19d1205
ZW		 10976 case 'S':
10977 {
10978 unsigned int reg = (given & 0x0000000fu);
10979 unsigned int stp = (given & 0x00000030u) >> 4;
10980 unsigned int imm = 0;
10981 imm |= (given & 0x000000c0u) >> 6;
10982 imm |= (given & 0x00007000u) >> 10;
10983
10984 func (stream, "%s", arm_regnames[reg]);
10985 switch (stp)
10986 {
10987 case 0:
10988 if (imm > 0)
10989 func (stream, ", lsl #%u", imm);
10990 break;
10991
10992 case 1:
10993 if (imm == 0)
10994 imm = 32;
10995 func (stream, ", lsr #%u", imm);
10996 break;
10997
10998 case 2:
10999 if (imm == 0)
11000 imm = 32;
11001 func (stream, ", asr #%u", imm);
11002 break;
11003
11004 case 3:
11005 if (imm == 0)
11006 func (stream, ", rrx");
11007 else
11008 func (stream, ", ror #%u", imm);
11009 }
11010 }
11011 break;
11012
11013 case 'a':
11014 {
11015 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11016 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11017 unsigned int op = (given & 0x00000f00) >> 8;
11018 unsigned int i12 = (given & 0x00000fff);
11019 unsigned int i8 = (given & 0x000000ff);
78933a4a 11020 bool writeback = false, postind = false;
f8b960bc 11021 bfd_vma offset = 0;
c19d1205
ZW		 11022
11023 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 11024 if (U) /* 12-bit positive immediate offset. */
11025 {
11026 offset = i12;
11027 if (Rn != 15)
11028 value_in_comment = offset;
11029 }
11030 else if (Rn == 15) /* 12-bit negative immediate offset. */
11031 offset = - (int) i12;
11032 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11033 {
11034 unsigned int Rm = (i8 & 0x0f);
11035 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11036
c19d1205
ZW		 11037 func (stream, ", %s", arm_regnames[Rm]);
11038 if (sh)
11039 func (stream, ", lsl #%u", sh);
11040 func (stream, "]");
11041 break;
11042 }
11043 else switch (op)
11044 {
05413229 11045 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11046 offset = i8;
11047 break;
11048
05413229 11049 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11050 offset = -i8;
11051 break;
11052
05413229 11053 case 0xF: /* 8-bit + preindex with wb. */
c19d1205 11054 offset = i8;
78933a4a 11055 writeback = true;
c19d1205
ZW		 11056 break;
11057
05413229 11058 case 0xD: /* 8-bit - preindex with wb. */
c19d1205 11059 offset = -i8;
78933a4a 11060 writeback = true;
c19d1205
ZW		 11061 break;
11062
05413229 11063 case 0xB: /* 8-bit + postindex. */
c19d1205 11064 offset = i8;
78933a4a 11065 postind = true;
c19d1205
ZW		 11066 break;
11067
05413229 11068 case 0x9: /* 8-bit - postindex. */
c19d1205 11069 offset = -i8;
78933a4a 11070 postind = true;
c19d1205
ZW		 11071 break;
11072
11073 default:
11074 func (stream, ", <undefined>]");
11075 goto skip;
11076 }
11077
11078 if (postind)
d908c8af 11079 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 11080 else
11081 {
11082 if (offset)
d908c8af 11083 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 11084 func (stream, writeback ? "]!" : "]");
11085 }
11086
11087 if (Rn == 15)
11088 {
11089 func (stream, "\t; ");
11090 info->print_address_func (((pc + 4) & ~3) + offset, info);
11091 }
11092 }
11093 skip:
11094 break;
11095
11096 case 'A':
11097 {
c1e26897
NC		 11098 unsigned int U = ! NEGATIVE_BIT_SET;
11099 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11100 unsigned int Rn = (given & 0x000f0000) >> 16;
11101 unsigned int off = (given & 0x000000ff);
11102
11103 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 11104
11105 if (PRE_BIT_SET)
c19d1205
ZW		 11106 {
11107 if (off || !U)
05413229
NC		 11108 {
11109 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 11110 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11111 }
c19d1205
ZW		 11112 func (stream, "]");
11113 if (W)
11114 func (stream, "!");
11115 }
11116 else
11117 {
11118 func (stream, "], ");
11119 if (W)
05413229
NC		 11120 {
11121 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 11122 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11123 }
c19d1205 11124 else
fe56b6ce
NC		 11125 {
11126 func (stream, "{%u}", off);
11127 value_in_comment = off;
11128 }
c19d1205
ZW		 11129 }
11130 }
11131 break;
11132
11133 case 'w':
11134 {
11135 unsigned int Sbit = (given & 0x01000000) >> 24;
11136 unsigned int type = (given & 0x00600000) >> 21;
05413229 11137
c19d1205
ZW		 11138 switch (type)
11139 {
11140 case 0: func (stream, Sbit ? "sb" : "b"); break;
11141 case 1: func (stream, Sbit ? "sh" : "h"); break;
11142 case 2:
11143 if (Sbit)
11144 func (stream, "??");
11145 break;
11146 case 3:
11147 func (stream, "??");
11148 break;
11149 }
11150 }
11151 break;
11152
4b5a202f 11153 case 'n':
78933a4a 11154 is_clrm = true;
4b5a202f 11155 /* Fall through. */
c19d1205
ZW		 11156 case 'm':
11157 {
11158 int started = 0;
11159 int reg;
11160
11161 func (stream, "{");
11162 for (reg = 0; reg < 16; reg++)
11163 if ((given & (1 << reg)) != 0)
11164 {
11165 if (started)
11166 func (stream, ", ");
11167 started = 1;
4b5a202f
AV		 11168 if (is_clrm && reg == 13)
11169 func (stream, "(invalid: %s)", arm_regnames[reg]);
11170 else if (is_clrm && reg == 15)
11171 func (stream, "%s", "APSR");
11172 else
11173 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 11174 }
11175 func (stream, "}");
11176 }
11177 break;
11178
11179 case 'E':
11180 {
11181 unsigned int msb = (given & 0x0000001f);
11182 unsigned int lsb = 0;
fe56b6ce 11183
c19d1205
ZW		 11184 lsb |= (given & 0x000000c0u) >> 6;
11185 lsb |= (given & 0x00007000u) >> 10;
11186 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11187 }
11188 break;
11189
11190 case 'F':
11191 {
11192 unsigned int width = (given & 0x0000001f) + 1;
11193 unsigned int lsb = 0;
fe56b6ce 11194
c19d1205
ZW		 11195 lsb |= (given & 0x000000c0u) >> 6;
11196 lsb |= (given & 0x00007000u) >> 10;
11197 func (stream, "#%u, #%u", lsb, width);
11198 }
11199 break;
11200
e12437dc
AV		 11201 case 'G':
11202 {
11203 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11204 func (stream, "%x", boff);
11205 }
11206 break;
11207
e5d6e09e
AV		 11208 case 'W':
11209 {
11210 unsigned int immA = (given & 0x001f0000u) >> 16;
11211 unsigned int immB = (given & 0x000007feu) >> 1;
11212 unsigned int immC = (given & 0x00000800u) >> 11;
11213 bfd_vma offset = 0;
11214
11215 offset |= immA << 12;
11216 offset |= immB << 2;
11217 offset |= immC << 1;
11218 /* Sign extend. */
11219 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11220
11221 info->print_address_func (pc + 4 + offset, info);
11222 }
11223 break;
11224
1caf72a5
AV		 11225 case 'Y':
11226 {
11227 unsigned int immA = (given & 0x007f0000u) >> 16;
11228 unsigned int immB = (given & 0x000007feu) >> 1;
11229 unsigned int immC = (given & 0x00000800u) >> 11;
11230 bfd_vma offset = 0;
11231
11232 offset |= immA << 12;
11233 offset |= immB << 2;
11234 offset |= immC << 1;
11235 /* Sign extend. */
11236 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11237
11238 info->print_address_func (pc + 4 + offset, info);
11239 }
11240 break;
11241
1889da70
AV		 11242 case 'Z':
11243 {
11244 unsigned int immA = (given & 0x00010000u) >> 16;
11245 unsigned int immB = (given & 0x000007feu) >> 1;
11246 unsigned int immC = (given & 0x00000800u) >> 11;
11247 bfd_vma offset = 0;
11248
11249 offset |= immA << 12;
11250 offset |= immB << 2;
11251 offset |= immC << 1;
11252 /* Sign extend. */
11253 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11254
11255 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11256
11257 unsigned int T = (given & 0x00020000u) >> 17;
11258 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11259 unsigned int boffset = (T == 1) ? 4 : 2;
11260 func (stream, ", ");
11261 func (stream, "%x", endoffset + boffset);
1889da70
AV		 11262 }
11263 break;
11264
60f993ce
AV		 11265 case 'Q':
11266 {
11267 unsigned int immh = (given & 0x000007feu) >> 1;
11268 unsigned int imml = (given & 0x00000800u) >> 11;
11269 bfd_vma imm32 = 0;
11270
11271 imm32 |= immh << 2;
11272 imm32 |= imml << 1;
11273
11274 info->print_address_func (pc + 4 + imm32, info);
11275 }
11276 break;
11277
11278 case 'P':
11279 {
11280 unsigned int immh = (given & 0x000007feu) >> 1;
11281 unsigned int imml = (given & 0x00000800u) >> 11;
11282 bfd_vma imm32 = 0;
11283
11284 imm32 |= immh << 2;
11285 imm32 |= imml << 1;
11286
11287 info->print_address_func (pc + 4 - imm32, info);
11288 }
11289 break;
11290
c19d1205
ZW		 11291 case 'b':
11292 {
11293 unsigned int S = (given & 0x04000000u) >> 26;
11294 unsigned int J1 = (given & 0x00002000u) >> 13;
11295 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11296 bfd_vma offset = 0;
c19d1205
ZW		 11297
11298 offset |= !S << 20;
11299 offset |= J2 << 19;
11300 offset |= J1 << 18;
11301 offset |= (given & 0x003f0000) >> 4;
11302 offset |= (given & 0x000007ff) << 1;
11303 offset -= (1 << 20);
11304
1d67fe3b
TT		 11305 bfd_vma target = pc + 4 + offset;
11306 info->print_address_func (target, info);
11307
11308 /* Fill in instruction information. */
11309 info->insn_info_valid = 1;
11310 info->insn_type = dis_branch;
11311 info->target = target;
c19d1205
ZW		 11312 }
11313 break;
11314
11315 case 'B':
11316 {
11317 unsigned int S = (given & 0x04000000u) >> 26;
11318 unsigned int I1 = (given & 0x00002000u) >> 13;
11319 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11320 bfd_vma offset = 0;
c19d1205
ZW		 11321
11322 offset |= !S << 24;
11323 offset |= !(I1 ^ S) << 23;
11324 offset |= !(I2 ^ S) << 22;
11325 offset |= (given & 0x03ff0000u) >> 4;
11326 offset |= (given & 0x000007ffu) << 1;
11327 offset -= (1 << 24);
36b0c57d 11328 offset += pc + 4;
c19d1205 11329
36b0c57d
PB		 11330 /* BLX target addresses are always word aligned. */
11331 if ((given & 0x00001000u) == 0)
11332 offset &= ~2u;
11333
11334 info->print_address_func (offset, info);
1d67fe3b
TT		 11335
11336 /* Fill in instruction information. */
11337 info->insn_info_valid = 1;
11338 info->insn_type = dis_branch;
11339 info->target = offset;
c19d1205
ZW		 11340 }
11341 break;
11342
11343 case 's':
11344 {
11345 unsigned int shift = 0;
fe56b6ce 11346
c19d1205
ZW		 11347 shift |= (given & 0x000000c0u) >> 6;
11348 shift |= (given & 0x00007000u) >> 10;
c1e26897 11349 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11350 func (stream, ", asr #%u", shift);
11351 else if (shift)
11352 func (stream, ", lsl #%u", shift);
11353 /* else print nothing - lsl #0 */
11354 }
11355 break;
11356
11357 case 'R':
11358 {
11359 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11360
c19d1205
ZW		 11361 if (rot)
11362 func (stream, ", ror #%u", rot * 8);
11363 }
11364 break;
11365
62b3e311 11366 case 'U':
43e65147 11367 if ((given & 0xf0) == 0x60)
62b3e311 11368 {
52e7f43d
RE		 11369 switch (given & 0xf)
11370 {
11371 case 0xf: func (stream, "sy"); break;
11372 default:
11373 func (stream, "#%d", (int) given & 0xf);
11374 break;
11375 }
62b3e311 11376 }
43e65147 11377 else
52e7f43d 11378 {
e797f7e0
MGD		 11379 const char * opt = data_barrier_option (given & 0xf);
11380 if (opt != NULL)
11381 func (stream, "%s", opt);
11382 else
11383 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11384 }
62b3e311
PB		 11385 break;
11386
11387 case 'C':
11388 if ((given & 0xff) == 0)
11389 {
11390 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11391 if (given & 0x800)
11392 func (stream, "f");
11393 if (given & 0x400)
11394 func (stream, "s");
11395 if (given & 0x200)
11396 func (stream, "x");
11397 if (given & 0x100)
11398 func (stream, "c");
11399 }
90ec0d68
MGD		 11400 else if ((given & 0x20) == 0x20)
11401 {
11402 char const* name;
11403 unsigned sysm = (given & 0xf00) >> 8;
11404
11405 sysm |= (given & 0x30);
11406 sysm |= (given & 0x00100000) >> 14;
11407 name = banked_regname (sysm);
43e65147 11408
90ec0d68
MGD		 11409 if (name != NULL)
11410 func (stream, "%s", name);
11411 else
d908c8af 11412 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11413 }
62b3e311
PB		 11414 else
11415 {
d908c8af 11416 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11417 }
11418 break;
11419
11420 case 'D':
90ec0d68
MGD		 11421 if (((given & 0xff) == 0)
11422 || ((given & 0x20) == 0x20))
11423 {
11424 char const* name;
11425 unsigned sm = (given & 0xf0000) >> 16;
11426
11427 sm |= (given & 0x30);
11428 sm |= (given & 0x00100000) >> 14;
11429 name = banked_regname (sm);
11430
11431 if (name != NULL)
11432 func (stream, "%s", name);
11433 else
d908c8af 11434 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11435 }
62b3e311 11436 else
d908c8af 11437 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11438 break;
11439
c19d1205
ZW		 11440 case '0': case '1': case '2': case '3': case '4':
11441 case '5': case '6': case '7': case '8': case '9':
11442 {
16980d0b
JB		 11443 int width;
11444 unsigned long val;
c19d1205 11445
16980d0b 11446 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11447
c19d1205
ZW		 11448 switch (*c)
11449 {
d052b9b7
AV		 11450 case 's':
11451 if (val <= 3)
11452 func (stream, "%s", mve_vec_sizename[val]);
11453 else
11454 func (stream, "<undef size>");
11455 break;
11456
05413229
NC		 11457 case 'd':
11458 func (stream, "%lu", val);
11459 value_in_comment = val;
11460 break;
ff4a8d2b 11461
f0fba320
RL		 11462 case 'D':
11463 func (stream, "%lu", val + 1);
11464 value_in_comment = val + 1;
11465 break;
11466
05413229
NC		 11467 case 'W':
11468 func (stream, "%lu", val * 4);
11469 value_in_comment = val * 4;
11470 break;
ff4a8d2b 11471
f1c7f421
AV		 11472 case 'S':
11473 if (val == 13)
78933a4a 11474 is_unpredictable = true;
f1c7f421 11475 /* Fall through. */
ff4a8d2b
NC		 11476 case 'R':
11477 if (val == 15)
78933a4a 11478 is_unpredictable = true;
ff4a8d2b
NC		 11479 /* Fall through. */
11480 case 'r':
11481 func (stream, "%s", arm_regnames[val]);
11482 break;
c19d1205
ZW		 11483
11484 case 'c':
c22aaad1 11485 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11486 break;
11487
11488 case '\'':
c19d1205 11489 c++;
16980d0b
JB		 11490 if (val == ((1ul << width) - 1))
11491 func (stream, "%c", *c);
c19d1205 11492 break;
43e65147 11493
c19d1205 11494 case '`':
c19d1205 11495 c++;
16980d0b
JB		 11496 if (val == 0)
11497 func (stream, "%c", *c);
c19d1205
ZW		 11498 break;
11499
11500 case '?':
fe56b6ce 11501 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11502 c += 1 << width;
c19d1205 11503 break;
43e65147 11504
0bb027fd
RR		 11505 case 'x':
11506 func (stream, "0x%lx", val & 0xffffffffUL);
11507 break;
c19d1205
ZW		 11508
11509 default:
11510 abort ();
11511 }
11512 }
11513 break;
11514
32a94698
NC		 11515 case 'L':
11516 /* PR binutils/12534
11517 If we have a PC relative offset in an LDRD or STRD
11518 instructions then display the decoded address. */
11519 if (((given >> 16) & 0xf) == 0xf)
11520 {
11521 bfd_vma offset = (given & 0xff) * 4;
11522
11523 if ((given & (1 << 23)) == 0)
11524 offset = - offset;
11525 func (stream, "\t; ");
11526 info->print_address_func ((pc & ~3) + 4 + offset, info);
11527 }
11528 break;
11529
c19d1205
ZW		 11530 default:
11531 abort ();
11532 }
11533 }
05413229
NC		 11534
11535 if (value_in_comment > 32 || value_in_comment < -16)
11536 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11537
11538 if (is_unpredictable)
11539 func (stream, UNPREDICTABLE_INSTRUCTION);
11540
4a5329c6 11541 return;
c19d1205 11542 }
252b5132 11543
58efb6c0 11544 /* No match. */
0b347048
TC		 11545 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11546 return;
252b5132
RH		 11547}
11548
e821645d
DJ		 11549/* Print data bytes on INFO->STREAM. */
11550
11551static void
fe56b6ce
NC		 11552print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11553 struct disassemble_info *info,
e821645d
DJ		 11554 long given)
11555{
11556 switch (info->bytes_per_chunk)
11557 {
11558 case 1:
11559 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11560 break;
11561 case 2:
11562 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11563 break;
11564 case 4:
11565 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11566 break;
11567 default:
11568 abort ();
11569 }
11570}
11571
22a398e1 11572/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11573 being displayed in symbol relative addresses.
11574
11575 Also disallow private symbol, with __tagsym$$ prefix,
11576 from ARM RVCT toolchain being displayed. */
22a398e1 11577
78933a4a 11578bool
22a398e1
NC		 11579arm_symbol_is_valid (asymbol * sym,
11580 struct disassemble_info * info ATTRIBUTE_UNUSED)
11581{
11582 const char * name;
43e65147 11583
22a398e1 11584 if (sym == NULL)
78933a4a 11585 return false;
22a398e1
NC		 11586
11587 name = bfd_asymbol_name (sym);
11588
d8282f0e 11589 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11590}
11591
65b48a81 11592/* Parse the string of disassembler options. */
baf0cc5e 11593
65b48a81 11594static void
f995bbe8 11595parse_arm_disassembler_options (const char *options)
dd92f639 11596{
f995bbe8 11597 const char *opt;
b34976b6 11598
65b48a81 11599 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11600 {
08dedd66 11601 if (startswith (opt, "reg-names-"))
65b48a81
PB		 11602 {
11603 unsigned int i;
11604 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11605 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11606 {
11607 regname_selected = i;
11608 break;
11609 }
b34976b6 11610
65b48a81 11611 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11612 /* xgettext: c-format */
11613 opcodes_error_handler (_("unrecognised register name set: %s"),
11614 opt);
65b48a81 11615 }
08dedd66 11616 else if (startswith (opt, "force-thumb"))
65b48a81 11617 force_thumb = 1;
08dedd66 11618 else if (startswith (opt, "no-force-thumb"))
65b48a81 11619 force_thumb = 0;
08dedd66 11620 else if (startswith (opt, "coproc"))
4934a27c
MM		 11621 {
11622 const char *procptr = opt + sizeof ("coproc") - 1;
11623 char *endptr;
11624 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11625 if (endptr != procptr + 1 || coproc_number > 7)
11626 {
11627 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11628 opt);
11629 continue;
11630 }
11631 if (*endptr != '=')
11632 {
11633 opcodes_error_handler (_("coproc must have an argument: %s"),
11634 opt);
11635 continue;
11636 }
11637 endptr += 1;
08dedd66 11638 if (startswith (endptr, "generic"))
4934a27c 11639 cde_coprocs &= ~(1 << coproc_number);
08dedd66
ML		 11640 else if (startswith (endptr, "cde")
11641 || startswith (endptr, "CDE"))
4934a27c
MM		 11642 cde_coprocs |= (1 << coproc_number);
11643 else
11644 {
11645 opcodes_error_handler (
11646 _("coprocN argument takes options \"generic\","
11647 " \"cde\", or \"CDE\": %s"), opt);
11648 }
11649 }
65b48a81 11650 else
a6743a54
AM		 11651 /* xgettext: c-format */
11652 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11653 }
b34976b6 11654
dd92f639
NC		 11655 return;
11656}
11657
78933a4a 11658static bool
5bc5ae88
RL		 11659mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11660 enum map_type *map_symbol);
11661
c22aaad1
PB		 11662/* Search back through the insn stream to determine if this instruction is
11663 conditionally executed. */
fe56b6ce 11664
c22aaad1 11665static void
fe56b6ce
NC		 11666find_ifthen_state (bfd_vma pc,
11667 struct disassemble_info *info,
78933a4a 11668 bool little)
c22aaad1
PB		 11669{
11670 unsigned char b[2];
11671 unsigned int insn;
11672 int status;
11673 /* COUNT is twice the number of instructions seen. It will be odd if we
11674 just crossed an instruction boundary. */
11675 int count;
11676 int it_count;
11677 unsigned int seen_it;
11678 bfd_vma addr;
11679
11680 ifthen_address = pc;
11681 ifthen_state = 0;
11682
11683 addr = pc;
11684 count = 1;
11685 it_count = 0;
11686 seen_it = 0;
11687 /* Scan backwards looking for IT instructions, keeping track of where
11688 instruction boundaries are. We don't know if something is actually an
11689 IT instruction until we find a definite instruction boundary. */
11690 for (;;)
11691 {
fe56b6ce 11692 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11693 {
11694 /* A symbol must be on an instruction boundary, and will not
11695 be within an IT block. */
11696 if (seen_it && (count & 1))
11697 break;
11698
11699 return;
11700 }
11701 addr -= 2;
fe56b6ce 11702 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11703 if (status)
11704 return;
11705
11706 if (little)
11707 insn = (b[0]) | (b[1] << 8);
11708 else
11709 insn = (b[1]) | (b[0] << 8);
11710 if (seen_it)
11711 {
11712 if ((insn & 0xf800) < 0xe800)
11713 {
11714 /* Addr + 2 is an instruction boundary. See if this matches
11715 the expected boundary based on the position of the last
11716 IT candidate. */
11717 if (count & 1)
11718 break;
11719 seen_it = 0;
11720 }
11721 }
11722 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11723 {
5bc5ae88 11724 enum map_type type = MAP_ARM;
78933a4a 11725 bool found = mapping_symbol_for_insn (addr, info, &type);
5bc5ae88
RL		 11726
11727 if (!found || (found && type == MAP_THUMB))
11728 {
11729 /* This could be an IT instruction. */
11730 seen_it = insn;
11731 it_count = count >> 1;
11732 }
c22aaad1
PB		 11733 }
11734 if ((insn & 0xf800) >= 0xe800)
11735 count++;
11736 else
11737 count = (count + 2) | 1;
11738 /* IT blocks contain at most 4 instructions. */
11739 if (count >= 8 && !seen_it)
11740 return;
11741 }
11742 /* We found an IT instruction. */
11743 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11744 if ((ifthen_state & 0xf) == 0)
11745 ifthen_state = 0;
11746}
11747
b0e28b39
DJ		 11748/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11749 mapping symbol. */
11750
11751static int
11752is_mapping_symbol (struct disassemble_info *info, int n,
11753 enum map_type *map_type)
11754{
11755 const char *name;
11756
11757 name = bfd_asymbol_name (info->symtab[n]);
11758 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11759 && (name[2] == 0 || name[2] == '.'))
11760 {
11761 *map_type = ((name[1] == 'a') ? MAP_ARM
11762 : (name[1] == 't') ? MAP_THUMB
11763 : MAP_DATA);
78933a4a 11764 return true;
b0e28b39
DJ		 11765 }
11766
78933a4a 11767 return false;
b0e28b39
DJ		 11768}
11769
11770/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11771 Returns nonzero if *MAP_TYPE was set. */
11772
11773static int
11774get_map_sym_type (struct disassemble_info *info,
11775 int n,
11776 enum map_type *map_type)
11777{
11778 /* If the symbol is in a different section, ignore it. */
11779 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 11780 return false;
b0e28b39
DJ		 11781
11782 return is_mapping_symbol (info, n, map_type);
11783}
11784
11785/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11786 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11787
11788static int
fe56b6ce
NC		 11789get_sym_code_type (struct disassemble_info *info,
11790 int n,
e821645d 11791 enum map_type *map_type)
2087ad84
PB		 11792{
11793 elf_symbol_type *es;
11794 unsigned int type;
b0e28b39
DJ		 11795
11796 /* If the symbol is in a different section, ignore it. */
11797 if (info->section != NULL && info->section != info->symtab[n]->section)
78933a4a 11798 return false;
2087ad84 11799
e821645d 11800 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11801 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11802
11803 /* If the symbol has function type then use that. */
34e77a92 11804 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11805 {
39d911fc
TP		 11806 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11807 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11808 *map_type = MAP_THUMB;
11809 else
11810 *map_type = MAP_ARM;
78933a4a 11811 return true;
2087ad84
PB		 11812 }
11813
78933a4a 11814 return false;
2087ad84
PB		 11815}
11816
5bc5ae88
RL		 11817/* Search the mapping symbol state for instruction at pc. This is only
11818 applicable for elf target.
11819
11820 There is an assumption Here, info->private_data contains the correct AND
11821 up-to-date information about current scan process. The information will be
11822 used to speed this search process.
11823
11824 Return TRUE if the mapping state can be determined, and map_symbol
11825 will be updated accordingly. Otherwise, return FALSE. */
11826
78933a4a 11827static bool
5bc5ae88
RL		 11828mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11829 enum map_type *map_symbol)
11830{
796d6298
TC		 11831 bfd_vma addr, section_vma = 0;
11832 int n, last_sym = -1;
78933a4a
AM		 11833 bool found = false;
11834 bool can_use_search_opt_p = false;
796d6298
TC		 11835
11836 /* Default to DATA. A text section is required by the ABI to contain an
11837 INSN mapping symbol at the start. A data section has no such
11838 requirement, hence if no mapping symbol is found the section must
11839 contain only data. This however isn't very useful if the user has
11840 fully stripped the binaries. If this is the case use the section
11841 attributes to determine the default. If we have no section default to
11842 INSN as well, as we may be disassembling some raw bytes on a baremetal
11843 HEX file or similar. */
11844 enum map_type type = MAP_DATA;
11845 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11846 type = MAP_ARM;
5bc5ae88
RL		 11847 struct arm_private_data *private_data;
11848
796d6298 11849 if (info->private_data == NULL
5bc5ae88 11850 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
78933a4a 11851 return false;
5bc5ae88
RL		 11852
11853 private_data = info->private_data;
5bc5ae88 11854
796d6298
TC		 11855 /* First, look for mapping symbols. */
11856 if (info->symtab_size != 0)
11857 {
11858 if (pc <= private_data->last_mapping_addr)
11859 private_data->last_mapping_sym = -1;
11860
11861 /* Start scanning at the start of the function, or wherever
11862 we finished last time. */
11863 n = info->symtab_pos + 1;
11864
11865 /* If the last stop offset is different from the current one it means we
11866 are disassembling a different glob of bytes. As such the optimization
11867 would not be safe and we should start over. */
11868 can_use_search_opt_p
11869 = private_data->last_mapping_sym >= 0
11870 && info->stop_offset == private_data->last_stop_offset;
11871
11872 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11873 n = private_data->last_mapping_sym;
11874
11875 /* Look down while we haven't passed the location being disassembled.
11876 The reason for this is that there's no defined order between a symbol
11877 and an mapping symbol that may be at the same address. We may have to
11878 look at least one position ahead. */
11879 for (; n < info->symtab_size; n++)
11880 {
11881 addr = bfd_asymbol_value (info->symtab[n]);
11882 if (addr > pc)
11883 break;
11884 if (get_map_sym_type (info, n, &type))
11885 {
11886 last_sym = n;
78933a4a 11887 found = true;
796d6298
TC		 11888 }
11889 }
5bc5ae88 11890
796d6298
TC		 11891 if (!found)
11892 {
11893 n = info->symtab_pos;
11894 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11895 n = private_data->last_mapping_sym;
11896
11897 /* No mapping symbol found at this address. Look backwards
11898 for a preceeding one, but don't go pass the section start
11899 otherwise a data section with no mapping symbol can pick up
11900 a text mapping symbol of a preceeding section. The documentation
11901 says section can be NULL, in which case we will seek up all the
11902 way to the top. */
11903 if (info->section)
11904 section_vma = info->section->vma;
11905
11906 for (; n >= 0; n--)
11907 {
11908 addr = bfd_asymbol_value (info->symtab[n]);
11909 if (addr < section_vma)
11910 break;
11911
11912 if (get_map_sym_type (info, n, &type))
11913 {
11914 last_sym = n;
78933a4a 11915 found = true;
796d6298
TC		 11916 break;
11917 }
11918 }
11919 }
11920 }
11921
11922 /* If no mapping symbol was found, try looking up without a mapping
11923 symbol. This is done by walking up from the current PC to the nearest
11924 symbol. We don't actually have to loop here since symtab_pos will
11925 contain the nearest symbol already. */
11926 if (!found)
5bc5ae88 11927 {
796d6298
TC		 11928 n = info->symtab_pos;
11929 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11930 {
796d6298 11931 last_sym = n;
78933a4a 11932 found = true;
5bc5ae88
RL		 11933 }
11934 }
11935
796d6298
TC		 11936 private_data->last_mapping_sym = last_sym;
11937 private_data->last_type = type;
11938 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11939
11940 *map_symbol = type;
11941 return found;
11942}
11943
0313a2b8
NC		 11944/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11945 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11946 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11947
11948 FIXME: This could more efficiently implemented as a constant array,
11949 although it would also be less robust. */
11950
11951static void
11952select_arm_features (unsigned long mach,
11953 arm_feature_set * features)
11954{
c0c468d5
TP		 11955 arm_feature_set arch_fset;
11956 const arm_feature_set fpu_any = FPU_ANY;
11957
1af1dd51
MW		 11958#undef ARM_SET_FEATURES
11959#define ARM_SET_FEATURES(FSET) \
11960 { \
11961 const arm_feature_set fset = FSET; \
c0c468d5 11962 arch_fset = fset; \
1af1dd51 11963 }
823d2571 11964
c0c468d5
TP		 11965 /* When several architecture versions share the same bfd_mach_arm_XXX value
11966 the most featureful is chosen. */
0313a2b8
NC		 11967 switch (mach)
11968 {
c0c468d5
TP		 11969 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11970 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11971 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11972 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11973 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11974 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11975 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11976 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11977 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11978 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11979 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11980 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11981 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11982 break;
c0c468d5
TP		 11983 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11984 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11985 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11986 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11987 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11988 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11989 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11990 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11991 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11992 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11993 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11994 case bfd_mach_arm_8:
11995 {
aab2c27d
MM		 11996 /* Add bits for extensions that Armv8.6-A recognizes. */
11997 arm_feature_set armv8_6_ext_fset
0632eeea 11998 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11999 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
12000 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 12001 break;
12002 }
12003 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
12004 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
12005 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12006 case bfd_mach_arm_8_1M_MAIN:
12007 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12008 arm_feature_set mve_all
12009 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12010 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12011 force_thumb = 1;
12012 break;
c0c468d5 12013 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12014 extensions, with the exception of MVE as that clashes with NEON. */
12015 case bfd_mach_arm_unknown:
12016 ARM_SET_FEATURES (ARM_FEATURE (-1,
12017 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12018 -1));
12019 break;
0313a2b8
NC		 12020 default:
12021 abort ();
12022 }
1af1dd51 12023#undef ARM_SET_FEATURES
c0c468d5
TP		 12024
12025 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12026 and thus on bfd_mach_arm_XXX value. Therefore for a given
12027 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12028 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12029}
12030
12031
58efb6c0
NC		 12032/* NOTE: There are no checks in these routines that
12033 the relevant number of data bytes exist. */
baf0cc5e 12034
58efb6c0 12035static int
78933a4a 12036print_insn (bfd_vma pc, struct disassemble_info *info, bool little)
252b5132 12037{
c19d1205 12038 unsigned char b[4];
2480b6fa 12039 unsigned long given;
78933a4a
AM		 12040 int status;
12041 int is_thumb = false;
12042 int is_data = false;
12043 int little_code;
e821645d 12044 unsigned int size = 4;
78933a4a
AM		 12045 void (*printer) (bfd_vma, struct disassemble_info *, long);
12046 bool found = false;
b0e28b39 12047 struct arm_private_data *private_data;
58efb6c0 12048
1d67fe3b
TT		 12049 /* Clear instruction information field. */
12050 info->insn_info_valid = 0;
12051 info->branch_delay_insns = 0;
12052 info->data_size = 0;
12053 info->insn_type = dis_noninsn;
12054 info->target = 0;
12055 info->target2 = 0;
12056
dd92f639
NC		 12057 if (info->disassembler_options)
12058 {
65b48a81 12059 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12060
58efb6c0 12061 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12062 info->disassembler_options = NULL;
12063 }
b34976b6 12064
0313a2b8
NC		 12065 /* PR 10288: Control which instructions will be disassembled. */
12066 if (info->private_data == NULL)
12067 {
b0e28b39 12068 static struct arm_private_data private;
0313a2b8
NC		 12069
12070 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12071 /* If the user did not use the -m command line switch then default to
12072 disassembling all types of ARM instruction.
43e65147 12073
0313a2b8
NC		 12074 The info->mach value has to be ignored as this will be based on
12075 the default archictecture for the target and/or hints in the notes
12076 section, but it will never be greater than the current largest arm
12077 machine value (iWMMXt2), which is only equivalent to the V5TE
12078 architecture. ARM architectures have advanced beyond the machine
12079 value encoding, and these newer architectures would be ignored if
12080 the machine value was used.
12081
12082 Ie the -m switch is used to restrict which instructions will be
12083 disassembled. If it is necessary to use the -m switch to tell
12084 objdump that an ARM binary is being disassembled, eg because the
12085 input is a raw binary file, but it is also desired to disassemble
12086 all ARM instructions then use "-marm". This will select the
12087 "unknown" arm architecture which is compatible with any ARM
12088 instruction. */
12089 info->mach = bfd_mach_arm_unknown;
12090
12091 /* Compute the architecture bitmask from the machine number.
12092 Note: This assumes that the machine number will not change
12093 during disassembly.... */
b0e28b39 12094 select_arm_features (info->mach, & private.features);
0313a2b8 12095
1fbaefec
PB		 12096 private.last_mapping_sym = -1;
12097 private.last_mapping_addr = 0;
796d6298 12098 private.last_stop_offset = 0;
b0e28b39
DJ		 12099
12100 info->private_data = & private;
0313a2b8 12101 }
b0e28b39
DJ		 12102
12103 private_data = info->private_data;
12104
bd2e2557
SS		 12105 /* Decide if our code is going to be little-endian, despite what the
12106 function argument might say. */
12107 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12108
b0e28b39
DJ		 12109 /* For ELF, consult the symbol table to determine what kind of code
12110 or data we have. */
8977d4b2 12111 if (info->symtab_size != 0
e821645d
DJ		 12112 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12113 {
12114 bfd_vma addr;
796d6298 12115 int n;
e821645d 12116 int last_sym = -1;
b0e28b39 12117 enum map_type type = MAP_ARM;
e821645d 12118
796d6298
TC		 12119 found = mapping_symbol_for_insn (pc, info, &type);
12120 last_sym = private_data->last_mapping_sym;
e821645d 12121
1fbaefec
PB		 12122 is_thumb = (private_data->last_type == MAP_THUMB);
12123 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12124
e821645d
DJ		 12125 /* Look a little bit ahead to see if we should print out
12126 two or four bytes of data. If there's a symbol,
12127 mapping or otherwise, after two bytes then don't
12128 print more. */
12129 if (is_data)
12130 {
12131 size = 4 - (pc & 3);
12132 for (n = last_sym + 1; n < info->symtab_size; n++)
12133 {
12134 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12135 if (addr > pc
12136 && (info->section == NULL
12137 || info->section == info->symtab[n]->section))
e821645d
DJ		 12138 {
12139 if (addr - pc < size)
12140 size = addr - pc;
12141 break;
12142 }
12143 }
12144 /* If the next symbol is after three bytes, we need to
12145 print only part of the data, so that we can use either
12146 .byte or .short. */
12147 if (size == 3)
12148 size = (pc & 1) ? 1 : 2;
12149 }
12150 }
12151
12152 if (info->symbols != NULL)
252b5132 12153 {
5876e06d
NC		 12154 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12155 {
2f0ca46a 12156 coff_symbol_type * cs;
b34976b6 12157
5876e06d
NC		 12158 cs = coffsymbol (*info->symbols);
12159 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12160 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12161 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12162 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12163 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12164 }
e821645d
DJ		 12165 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12166 && !found)
5876e06d 12167 {
2087ad84
PB		 12168 /* If no mapping symbol has been found then fall back to the type
12169 of the function symbol. */
e821645d
DJ		 12170 elf_symbol_type * es;
12171 unsigned int type;
2087ad84 12172
e821645d
DJ		 12173 es = *(elf_symbol_type **)(info->symbols);
12174 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12175
39d911fc
TP		 12176 is_thumb =
12177 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12178 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12179 }
e49d43ff
TG		 12180 else if (bfd_asymbol_flavour (*info->symbols)
12181 == bfd_target_mach_o_flavour)
12182 {
12183 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12184
12185 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12186 }
5876e06d 12187 }
b34976b6 12188
e821645d 12189 if (force_thumb)
78933a4a 12190 is_thumb = true;
e821645d 12191
b8f9ee44
CL		 12192 if (is_data)
12193 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12194 else
12195 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12196
c19d1205 12197 info->bytes_per_line = 4;
252b5132 12198
1316c8b3
NC		 12199 /* PR 10263: Disassemble data if requested to do so by the user. */
12200 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12201 {
12202 int i;
12203
1316c8b3 12204 /* Size was already set above. */
e821645d
DJ		 12205 info->bytes_per_chunk = size;
12206 printer = print_insn_data;
12207
fe56b6ce 12208 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12209 given = 0;
12210 if (little)
12211 for (i = size - 1; i >= 0; i--)
12212 given = b[i] | (given << 8);
12213 else
12214 for (i = 0; i < (int) size; i++)
12215 given = b[i] | (given << 8);
12216 }
12217 else if (!is_thumb)
252b5132 12218 {
c19d1205
ZW		 12219 /* In ARM mode endianness is a straightforward issue: the instruction
12220 is four bytes long and is either ordered 0123 or 3210. */
12221 printer = print_insn_arm;
12222 info->bytes_per_chunk = 4;
4a5329c6 12223 size = 4;
c19d1205 12224
0313a2b8 12225 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12226 if (little_code)
2480b6fa 12227 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12228 else
2480b6fa 12229 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12230 }
58efb6c0 12231 else
252b5132 12232 {
c19d1205
ZW		 12233 /* In Thumb mode we have the additional wrinkle of two
12234 instruction lengths. Fortunately, the bits that determine
12235 the length of the current instruction are always to be found
12236 in the first two bytes. */
4a5329c6 12237 printer = print_insn_thumb16;
c19d1205 12238 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12239 size = 2;
12240
fe56b6ce 12241 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12242 if (little_code)
9a2ff3f5
AM		 12243 given = (b[0]) | (b[1] << 8);
12244 else
12245 given = (b[1]) | (b[0] << 8);
12246
c19d1205 12247 if (!status)
252b5132 12248 {
c19d1205
ZW		 12249 /* These bit patterns signal a four-byte Thumb
12250 instruction. */
12251 if ((given & 0xF800) == 0xF800
12252 || (given & 0xF800) == 0xF000
12253 || (given & 0xF800) == 0xE800)
252b5132 12254 {
0313a2b8 12255 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12256 if (little_code)
c19d1205 12257 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12258 else
c19d1205
ZW		 12259 given = (b[1]) | (b[0] << 8) | (given << 16);
12260
12261 printer = print_insn_thumb32;
4a5329c6 12262 size = 4;
252b5132 12263 }
252b5132 12264 }
c22aaad1
PB		 12265
12266 if (ifthen_address != pc)
0313a2b8 12267 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12268
12269 if (ifthen_state)
12270 {
12271 if ((ifthen_state & 0xf) == 0x8)
12272 ifthen_next_state = 0;
12273 else
12274 ifthen_next_state = (ifthen_state & 0xe0)
12275 | ((ifthen_state & 0xf) << 1);
12276 }
252b5132 12277 }
b34976b6 12278
c19d1205
ZW		 12279 if (status)
12280 {
12281 info->memory_error_func (status, pc, info);
12282 return -1;
12283 }
6a56ec7e
NC		 12284 if (info->flags & INSN_HAS_RELOC)
12285 /* If the instruction has a reloc associated with it, then
12286 the offset field in the instruction will actually be the
12287 addend for the reloc. (We are using REL type relocs).
12288 In such cases, we can ignore the pc when computing
12289 addresses, since the addend is not currently pc-relative. */
12290 pc = 0;
b34976b6 12291
4a5329c6 12292 printer (pc, info, given);
c22aaad1
PB		 12293
12294 if (is_thumb)
12295 {
12296 ifthen_state = ifthen_next_state;
12297 ifthen_address += size;
12298 }
4a5329c6 12299 return size;
252b5132
RH		 12300}
12301
12302int
4a5329c6 12303print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12304{
bd2e2557
SS		 12305 /* Detect BE8-ness and record it in the disassembler info. */
12306 if (info->flavour == bfd_target_elf_flavour
12307 && info->section != NULL
12308 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12309 info->endian_code = BFD_ENDIAN_LITTLE;
12310
78933a4a 12311 return print_insn (pc, info, false);
58efb6c0 12312}
01c7f630 12313
58efb6c0 12314int
4a5329c6 12315print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12316{
78933a4a 12317 return print_insn (pc, info, true);
58efb6c0 12318}
252b5132 12319
471b9d15 12320const disasm_options_and_args_t *
65b48a81
PB		 12321disassembler_options_arm (void)
12322{
471b9d15 12323 static disasm_options_and_args_t *opts_and_args;
65b48a81 12324
471b9d15 12325 if (opts_and_args == NULL)
65b48a81 12326 {
471b9d15 12327 disasm_options_t *opts;
65b48a81 12328 unsigned int i;
471b9d15
MR		 12329
12330 opts_and_args = XNEW (disasm_options_and_args_t);
12331 opts_and_args->args = NULL;
12332
12333 opts = &opts_and_args->options;
65b48a81
PB		 12334 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12335 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12336 opts->arg = NULL;
65b48a81
PB		 12337 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12338 {
12339 opts->name[i] = regnames[i].name;
12340 if (regnames[i].description != NULL)
12341 opts->description[i] = _(regnames[i].description);
12342 else
12343 opts->description[i] = NULL;
12344 }
12345 /* The array we return must be NULL terminated. */
12346 opts->name[i] = NULL;
12347 opts->description[i] = NULL;
12348 }
12349
471b9d15 12350 return opts_and_args;
65b48a81
PB		 12351}
12352
58efb6c0 12353void
4a5329c6 12354print_arm_disassembler_options (FILE *stream)
58efb6c0 12355{
65b48a81 12356 unsigned int i, max_len = 0;
58efb6c0
NC		 12357 fprintf (stream, _("\n\
12358The following ARM specific disassembler options are supported for use with\n\
12359the -M switch:\n"));
b34976b6 12360
65b48a81
PB		 12361 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12362 {
12363 unsigned int len = strlen (regnames[i].name);
12364 if (max_len < len)
12365 max_len = len;
12366 }
58efb6c0 12367
65b48a81
PB		 12368 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12369 fprintf (stream, " %s%*c %s\n",
12370 regnames[i].name,
12371 (int)(max_len - strlen (regnames[i].name)), ' ',
12372 _(regnames[i].description));
252b5132 12373}
GDB Binutils - Deliverables
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