projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gas/opcodes: blackfin: punt BYTEOP2M insn support
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
69b8ea4a
MF		 2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4b7f6baa 4
9b201bb5
NC		 5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
4b7f6baa 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
4b7f6baa 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
4b7f6baa
CM		 16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22#include <stdio.h>
23#include <stdlib.h>
24#include <string.h>
25
26#include "opcode/bfin.h"
27
4b7f6baa
CM		 28#ifndef PRINTF
29#define PRINTF printf
30#endif
31
32#ifndef EXIT
33#define EXIT exit
34#endif
35
36typedef long TIword;
37
b7d48530
NC		 38#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
4b7f6baa
CM		 42
43#include "dis-asm.h"
b7d48530 44
b21c9cb4
BS		 45typedef unsigned int bu32;
46
528c6277
MF		 47static char comment = 0;
48static char parallel = 0;
49
4b7f6baa
CM		 50typedef enum
51{
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 57} const_forms_t;
58
528c6277 59static const struct
4b7f6baa 60{
528c6277
MF		 61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
4b7f6baa
CM		 73} constant_formats[] =
74{
086134ec
BS		 75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 118};
119
528c6277
MF		 120static const char *
121fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 122{
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
7a360e83
MF		 132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
134
086134ec
BS		 135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
137 outf->print_address_func (ea, outf);
138 return "";
139 }
140 else
141 {
0af1713e 142 sprintf (buf, "%lx", (unsigned long) x);
086134ec
BS		 143 return buf;
144 }
4b7f6baa
CM		 145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
b7d48530 151
4b7f6baa
CM		 152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
086134ec
BS		 164 if (constant_formats[cf].decimal)
165 {
166 if (constant_formats[cf].leading)
167 {
168 char ps[10];
169 sprintf (ps, "%%%ii", constant_formats[cf].leading);
170 sprintf (buf, ps, x);
171 }
172 else
173 sprintf (buf, "%li", x);
174 }
4b7f6baa 175 else
086134ec
BS		 176 {
177 if (constant_formats[cf].issigned && x < 0)
178 sprintf (buf, "-0x%x", abs (x));
179 else
0af1713e 180 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 181 }
4b7f6baa
CM		 182
183 return buf;
184}
185
b21c9cb4
BS		 186static bu32
187fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
188{
189 if (0 && constant_formats[cf].reloc)
190 {
191 bu32 ea = (((constant_formats[cf].pcrel
086134ec
BS		 192 ? SIGNEXTEND (x, constant_formats[cf].nbits)
193 : x) + constant_formats[cf].offset)
194 << constant_formats[cf].scale);
b21c9cb4 195 if (constant_formats[cf].pcrel)
086134ec 196 ea += pc;
b21c9cb4
BS		 197
198 return ea;
199 }
200
201 /* Negative constants have an implied sign bit. */
202 if (constant_formats[cf].negative)
203 {
204 int nb = constant_formats[cf].nbits + 1;
205 x = x | (1 << constant_formats[cf].nbits);
206 x = SIGNEXTEND (x, nb);
207 }
208 else if (constant_formats[cf].issigned)
209 x = SIGNEXTEND (x, constant_formats[cf].nbits);
210
211 x += constant_formats[cf].offset;
212 x <<= constant_formats[cf].scale;
213
214 return x;
215}
216
4b7f6baa
CM		 217enum machine_registers
218{
219 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
220 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
221 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
222 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
223 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
224 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
225 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
226 REG_L2, REG_L3,
227 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
228 REG_AQ, REG_V, REG_VS,
229 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
43a6aa65 230 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
4b7f6baa
CM		 231 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
232 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
233 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
234 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
235 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
236 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
237 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
238 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 239 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 240 REG_LASTREG,
241};
242
243enum reg_class
244{
245 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
246 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
247 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
248 rc_sysregs3, rc_allregs,
249 LIM_REG_CLASSES
250};
251
69b8ea4a 252static const char * const reg_names[] =
4b7f6baa
CM		 253{
254 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
255 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
256 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
257 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 258 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 259 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
260 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
261 "L2", "L3",
262 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
263 "AQ", "V", "VS",
264 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
43a6aa65 265 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
4b7f6baa
CM		 266 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
267 "RETE", "EMUDAT",
268 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
269 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
270 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
271 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
272 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
273 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
274 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 275 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 276 "LASTREG",
277 0
278};
279
280#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
281
282/* RL(0..7). */
69b8ea4a 283static const enum machine_registers decode_dregs_lo[] =
4b7f6baa
CM		 284{
285 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
286};
287
b7d48530 288#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 289
290/* RH(0..7). */
69b8ea4a 291static const enum machine_registers decode_dregs_hi[] =
4b7f6baa
CM		 292{
293 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
294};
295
b7d48530 296#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 297
298/* R(0..7). */
69b8ea4a 299static const enum machine_registers decode_dregs[] =
4b7f6baa
CM		 300{
301 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
302};
303
b7d48530 304#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 305
306/* R BYTE(0..7). */
69b8ea4a 307static const enum machine_registers decode_dregs_byte[] =
4b7f6baa
CM		 308{
309 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
310};
311
b7d48530 312#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 313
314/* P(0..5) SP FP. */
69b8ea4a 315static const enum machine_registers decode_pregs[] =
4b7f6baa
CM		 316{
317 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
318};
319
b7d48530
NC		 320#define pregs(x) REGNAME (decode_pregs[(x) & 7])
321#define spfp(x) REGNAME (decode_spfp[(x) & 1])
322#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
323#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
324#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
325#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 326
327/* I(0..3). */
69b8ea4a 328static const enum machine_registers decode_iregs[] =
4b7f6baa
CM		 329{
330 REG_I0, REG_I1, REG_I2, REG_I3,
331};
332
b7d48530 333#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 334
335/* M(0..3). */
69b8ea4a 336static const enum machine_registers decode_mregs[] =
4b7f6baa
CM		 337{
338 REG_M0, REG_M1, REG_M2, REG_M3,
339};
340
b7d48530
NC		 341#define mregs(x) REGNAME (decode_mregs[(x) & 3])
342#define bregs(x) REGNAME (decode_bregs[(x) & 3])
343#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 344
345/* dregs pregs. */
69b8ea4a 346static const enum machine_registers decode_dpregs[] =
4b7f6baa
CM		 347{
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350};
351
b7d48530 352#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 353
354/* [dregs pregs]. */
69b8ea4a 355static const enum machine_registers decode_gregs[] =
4b7f6baa
CM		 356{
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359};
360
b7d48530 361#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
4b7f6baa
CM		 362
363/* [dregs pregs (iregs mregs) (bregs lregs)]. */
69b8ea4a 364static const enum machine_registers decode_regs[] =
4b7f6baa
CM		 365{
366 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
369 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
370};
371
b7d48530 372#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
4b7f6baa
CM		 373
374/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
69b8ea4a 375static const enum machine_registers decode_regs_lo[] =
4b7f6baa
CM		 376{
377 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
378 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
379 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
380 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
381};
382
b7d48530 383#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
4b7f6baa 384/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
69b8ea4a 385static const enum machine_registers decode_regs_hi[] =
4b7f6baa
CM		 386{
387 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
388 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 389 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 390 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
391};
392
b7d48530 393#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
4b7f6baa 394
69b8ea4a 395static const enum machine_registers decode_statbits[] =
4b7f6baa 396{
22215ae0
MF		 397 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
398 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
399 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
400 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
401 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
402 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
403 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
404 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 405};
406
ad15c38e 407#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 408
409/* LC0 LC1. */
69b8ea4a 410static const enum machine_registers decode_counters[] =
4b7f6baa
CM		 411{
412 REG_LC0, REG_LC1,
413};
414
b7d48530
NC		 415#define counters(x) REGNAME (decode_counters[(x) & 1])
416#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 417
418/* [dregs pregs (iregs mregs) (bregs lregs)
419 dregs2_sysregs1 open sysregs2 sysregs3]. */
69b8ea4a 420static const enum machine_registers decode_allregs[] =
4b7f6baa
CM		 421{
422 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
423 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
424 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
425 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
43a6aa65 426 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
4b7f6baa
CM		 427 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
428 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 429 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
430 REG_LASTREG,
4b7f6baa
CM		 431};
432
50e2162a
MF		 433#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
434#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 435#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 436#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
437#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 438#define IS_SYSREG(g,r) \
439 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 440#define IS_RESERVEDREG(g,r) \
441 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
442
443#define allreg(r,g) (!IS_RESERVEDREG (g, r))
444#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 445
b7d48530
NC		 446#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
447#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 448#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 449#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
450#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
451#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
452#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
453#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
454#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
455#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
456#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
457#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 458#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 459#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
460#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
461#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
462#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
463#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
464#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
465#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
466#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
467#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
468#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 469#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 470#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
471#define imm3(x) fmtconst (c_imm3, x, 0, outf)
472#define imm4(x) fmtconst (c_imm4, x, 0, outf)
473#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
474#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 475#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 476#define imm6(x) fmtconst (c_imm6, x, 0, outf)
477#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 478#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 479#define imm8(x) fmtconst (c_imm8, x, 0, outf)
480#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
481#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 482#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 483#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 484#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 485#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
486#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 487#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
488#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 489
490/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 491#ifndef OUTS
4ca47a51 492#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
4b7f6baa
CM		 493#endif
494
4b7f6baa
CM		 495static void
496amod0 (int s0, int x0, disassemble_info *outf)
497{
b7d48530 498 if (s0 == 1 && x0 == 0)
086134ec 499 OUTS (outf, " (S)");
4b7f6baa 500 else if (s0 == 0 && x0 == 1)
086134ec 501 OUTS (outf, " (CO)");
4b7f6baa 502 else if (s0 == 1 && x0 == 1)
086134ec 503 OUTS (outf, " (SCO)");
4b7f6baa
CM		 504}
505
506static void
507amod1 (int s0, int x0, disassemble_info *outf)
508{
509 if (s0 == 0 && x0 == 0)
086134ec 510 OUTS (outf, " (NS)");
4b7f6baa 511 else if (s0 == 1 && x0 == 0)
086134ec 512 OUTS (outf, " (S)");
4b7f6baa
CM		 513}
514
515static void
516amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
517{
b7d48530 518 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 519 OUTS (outf, " (S)");
4b7f6baa 520 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 521 OUTS (outf, " (CO)");
4b7f6baa 522 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 523 OUTS (outf, " (SCO)");
4b7f6baa 524 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 525 OUTS (outf, " (ASR)");
4b7f6baa 526 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 527 OUTS (outf, " (S, ASR)");
4b7f6baa 528 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 529 OUTS (outf, " (CO, ASR)");
4b7f6baa 530 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 531 OUTS (outf, " (SCO, ASR)");
4b7f6baa 532 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 533 OUTS (outf, " (ASL)");
4b7f6baa 534 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 535 OUTS (outf, " (S, ASL)");
4b7f6baa 536 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 537 OUTS (outf, " (CO, ASL)");
4b7f6baa 538 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 539 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 540}
541
542static void
543searchmod (int r0, disassemble_info *outf)
544{
b7d48530
NC		 545 if (r0 == 0)
546 OUTS (outf, "GT");
547 else if (r0 == 1)
548 OUTS (outf, "GE");
549 else if (r0 == 2)
550 OUTS (outf, "LT");
551 else if (r0 == 3)
552 OUTS (outf, "LE");
4b7f6baa
CM		 553}
554
555static void
556aligndir (int r0, disassemble_info *outf)
557{
b7d48530 558 if (r0 == 1)
086134ec 559 OUTS (outf, " (R)");
4b7f6baa
CM		 560}
561
562static int
563decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
564{
528c6277 565 const char *s0, *s1;
4b7f6baa
CM		 566
567 if (h0)
568 s0 = dregs_hi (src0);
569 else
570 s0 = dregs_lo (src0);
571
572 if (h1)
573 s1 = dregs_hi (src1);
574 else
575 s1 = dregs_lo (src1);
576
577 OUTS (outf, s0);
578 OUTS (outf, " * ");
579 OUTS (outf, s1);
580 return 0;
581}
582
583static int
584decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
585{
528c6277
MF		 586 const char *a;
587 const char *sop = "<unknown op>";
4b7f6baa
CM		 588
589 if (which)
086134ec 590 a = "A1";
4b7f6baa 591 else
086134ec 592 a = "A0";
4b7f6baa
CM		 593
594 if (op == 3)
595 {
596 OUTS (outf, a);
597 return 0;
598 }
599
600 switch (op)
601 {
086134ec
BS		 602 case 0: sop = " = "; break;
603 case 1: sop = " += "; break;
604 case 2: sop = " -= "; break;
b7d48530 605 default: break;
4b7f6baa
CM		 606 }
607
608 OUTS (outf, a);
4b7f6baa 609 OUTS (outf, sop);
4b7f6baa
CM		 610 decode_multfunc (h0, h1, src0, src1, outf);
611
612 return 0;
613}
614
615static void
616decode_optmode (int mod, int MM, disassemble_info *outf)
617{
618 if (mod == 0 && MM == 0)
619 return;
620
621 OUTS (outf, " (");
622
623 if (MM && !mod)
624 {
625 OUTS (outf, "M)");
626 return;
627 }
628
629 if (MM)
630 OUTS (outf, "M, ");
b7d48530 631
4b7f6baa
CM		 632 if (mod == M_S2RND)
633 OUTS (outf, "S2RND");
634 else if (mod == M_T)
635 OUTS (outf, "T");
636 else if (mod == M_W32)
637 OUTS (outf, "W32");
638 else if (mod == M_FU)
639 OUTS (outf, "FU");
640 else if (mod == M_TFU)
641 OUTS (outf, "TFU");
642 else if (mod == M_IS)
643 OUTS (outf, "IS");
644 else if (mod == M_ISS2)
645 OUTS (outf, "ISS2");
646 else if (mod == M_IH)
647 OUTS (outf, "IH");
648 else if (mod == M_IU)
649 OUTS (outf, "IU");
650 else
651 abort ();
652
653 OUTS (outf, ")");
654}
b7d48530 655
b21c9cb4
BS		 656struct saved_state
657{
658 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
659 bu32 a0x, a0w, a1x, a1w;
660 bu32 lt[2], lc[2], lb[2];
661 int ac0, ac0_copy, ac1, an, aq;
662 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
663 int rnd_mod;
664 int v_internal;
665 bu32 pc, rets;
666
667 int ticks;
668 int insts;
669
670 int exception;
671
672 int end_of_registers;
673
674 int msize;
675 unsigned char *memory;
676 unsigned long bfd_mach;
677} saved_state;
678
679#define DREG(x) (saved_state.dpregs[x])
680#define GREG(x,i) DPREG ((x) | (i << 3))
681#define DPREG(x) (saved_state.dpregs[x])
682#define DREG(x) (saved_state.dpregs[x])
683#define PREG(x) (saved_state.dpregs[x + 8])
684#define SPREG PREG (6)
685#define FPREG PREG (7)
686#define IREG(x) (saved_state.iregs[x])
687#define MREG(x) (saved_state.mregs[x])
688#define BREG(x) (saved_state.bregs[x])
689#define LREG(x) (saved_state.lregs[x])
690#define A0XREG (saved_state.a0x)
691#define A0WREG (saved_state.a0w)
692#define A1XREG (saved_state.a1x)
693#define A1WREG (saved_state.a1w)
694#define CCREG (saved_state.cc)
695#define LC0REG (saved_state.lc[0])
696#define LT0REG (saved_state.lt[0])
697#define LB0REG (saved_state.lb[0])
698#define LC1REG (saved_state.lc[1])
699#define LT1REG (saved_state.lt[1])
700#define LB1REG (saved_state.lb[1])
701#define RETSREG (saved_state.rets)
702#define PCREG (saved_state.pc)
703
704static bu32 *
705get_allreg (int grp, int reg)
706{
707 int fullreg = (grp << 3) | reg;
708 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
709 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
710 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
711 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
712 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
713 , , , , , , , ,
714 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
715 REG_CYCLES2,
716 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
717 REG_LASTREG */
718 switch (fullreg >> 2)
719 {
720 case 0: case 1: return &DREG (reg); break;
721 case 2: case 3: return &PREG (reg); break;
722 case 4: return &IREG (reg & 3); break;
723 case 5: return &MREG (reg & 3); break;
724 case 6: return &BREG (reg & 3); break;
725 case 7: return &LREG (reg & 3); break;
726 default:
727 switch (fullreg)
086134ec
BS		 728 {
729 case 32: return &saved_state.a0x;
730 case 33: return &saved_state.a0w;
731 case 34: return &saved_state.a1x;
732 case 35: return &saved_state.a1w;
733 case 39: return &saved_state.rets;
734 case 48: return &LC0REG;
735 case 49: return &LT0REG;
736 case 50: return &LB0REG;
737 case 51: return &LC1REG;
738 case 52: return &LT1REG;
739 case 53: return &LB1REG;
740 }
b21c9cb4
BS		 741 return 0;
742 }
743}
744
4b7f6baa
CM		 745static int
746decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
747{
b7d48530
NC		 748 /* ProgCtrl
749 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
750 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
751 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 752 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
753 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
754
755 if (prgfunc == 0 && poprnd == 0)
b7d48530 756 OUTS (outf, "NOP");
219b747a
MF		 757 else if (parallel)
758 return 0;
4b7f6baa 759 else if (prgfunc == 1 && poprnd == 0)
b7d48530 760 OUTS (outf, "RTS");
4b7f6baa 761 else if (prgfunc == 1 && poprnd == 1)
b7d48530 762 OUTS (outf, "RTI");
4b7f6baa 763 else if (prgfunc == 1 && poprnd == 2)
b7d48530 764 OUTS (outf, "RTX");
4b7f6baa 765 else if (prgfunc == 1 && poprnd == 3)
b7d48530 766 OUTS (outf, "RTN");
4b7f6baa 767 else if (prgfunc == 1 && poprnd == 4)
b7d48530 768 OUTS (outf, "RTE");
4b7f6baa 769 else if (prgfunc == 2 && poprnd == 0)
b7d48530 770 OUTS (outf, "IDLE");
4b7f6baa 771 else if (prgfunc == 2 && poprnd == 3)
b7d48530 772 OUTS (outf, "CSYNC");
4b7f6baa 773 else if (prgfunc == 2 && poprnd == 4)
b7d48530 774 OUTS (outf, "SSYNC");
4b7f6baa 775 else if (prgfunc == 2 && poprnd == 5)
b7d48530 776 OUTS (outf, "EMUEXCPT");
50e2162a 777 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 778 {
086134ec 779 OUTS (outf, "CLI ");
4b7f6baa 780 OUTS (outf, dregs (poprnd));
4b7f6baa 781 }
50e2162a 782 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 783 {
086134ec 784 OUTS (outf, "STI ");
4b7f6baa 785 OUTS (outf, dregs (poprnd));
4b7f6baa 786 }
50e2162a 787 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 788 {
086134ec 789 OUTS (outf, "JUMP (");
4b7f6baa
CM		 790 OUTS (outf, pregs (poprnd));
791 OUTS (outf, ")");
4b7f6baa 792 }
50e2162a 793 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 794 {
086134ec 795 OUTS (outf, "CALL (");
4b7f6baa
CM		 796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
4b7f6baa 798 }
50e2162a 799 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 800 {
086134ec 801 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 802 OUTS (outf, pregs (poprnd));
803 OUTS (outf, ")");
4b7f6baa 804 }
50e2162a 805 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 806 {
086134ec 807 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 808 OUTS (outf, pregs (poprnd));
809 OUTS (outf, ")");
4b7f6baa
CM		 810 }
811 else if (prgfunc == 9)
812 {
086134ec 813 OUTS (outf, "RAISE ");
4b7f6baa 814 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 815 }
816 else if (prgfunc == 10)
817 {
086134ec 818 OUTS (outf, "EXCPT ");
4b7f6baa 819 OUTS (outf, uimm4 (poprnd));
4b7f6baa 820 }
219b747a 821 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 822 {
086134ec 823 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 824 OUTS (outf, pregs (poprnd));
825 OUTS (outf, ")");
4b7f6baa
CM		 826 }
827 else
b7d48530
NC		 828 return 0;
829 return 2;
4b7f6baa
CM		 830}
831
832static int
833decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
834{
b7d48530
NC		 835 /* CaCTRL
836 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
837 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 839 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
840 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
841 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
842
219b747a
MF		 843 if (parallel)
844 return 0;
845
4b7f6baa
CM		 846 if (a == 0 && op == 0)
847 {
4b7f6baa
CM		 848 OUTS (outf, "PREFETCH[");
849 OUTS (outf, pregs (reg));
850 OUTS (outf, "]");
4b7f6baa
CM		 851 }
852 else if (a == 0 && op == 1)
853 {
4b7f6baa
CM		 854 OUTS (outf, "FLUSHINV[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "]");
4b7f6baa
CM		 857 }
858 else if (a == 0 && op == 2)
859 {
4b7f6baa
CM		 860 OUTS (outf, "FLUSH[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "]");
4b7f6baa
CM		 863 }
864 else if (a == 0 && op == 3)
865 {
4b7f6baa
CM		 866 OUTS (outf, "IFLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "]");
4b7f6baa
CM		 869 }
870 else if (a == 1 && op == 0)
871 {
4b7f6baa
CM		 872 OUTS (outf, "PREFETCH[");
873 OUTS (outf, pregs (reg));
874 OUTS (outf, "++]");
4b7f6baa
CM		 875 }
876 else if (a == 1 && op == 1)
877 {
4b7f6baa
CM		 878 OUTS (outf, "FLUSHINV[");
879 OUTS (outf, pregs (reg));
880 OUTS (outf, "++]");
4b7f6baa
CM		 881 }
882 else if (a == 1 && op == 2)
883 {
4b7f6baa
CM		 884 OUTS (outf, "FLUSH[");
885 OUTS (outf, pregs (reg));
886 OUTS (outf, "++]");
4b7f6baa
CM		 887 }
888 else if (a == 1 && op == 3)
889 {
4b7f6baa
CM		 890 OUTS (outf, "IFLUSH[");
891 OUTS (outf, pregs (reg));
892 OUTS (outf, "++]");
4b7f6baa
CM		 893 }
894 else
b7d48530
NC		 895 return 0;
896 return 2;
4b7f6baa
CM		 897}
898
899static int
900decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
901{
b7d48530
NC		 902 /* PushPopReg
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
904 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 906 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
907 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
908 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
909
219b747a
MF		 910 if (parallel)
911 return 0;
912
50e2162a 913 if (W == 0 && mostreg (reg, grp))
4b7f6baa 914 {
4b7f6baa
CM		 915 OUTS (outf, allregs (reg, grp));
916 OUTS (outf, " = [SP++]");
4b7f6baa 917 }
219b747a 918 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 919 {
4b7f6baa
CM		 920 OUTS (outf, "[--SP] = ");
921 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 922 }
923 else
b7d48530
NC		 924 return 0;
925 return 2;
4b7f6baa
CM		 926}
927
928static int
929decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
930{
b7d48530
NC		 931 /* PushPopMultiple
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
933 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
934 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 935 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
936 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
937 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
938 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
939 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 940
219b747a
MF		 941 if (parallel)
942 return 0;
943
775f1cf0
MF		 944 if (pr > 5)
945 return 0;
946
4b7f6baa
CM		 947 if (W == 1 && d == 1 && p == 1)
948 {
4b7f6baa 949 OUTS (outf, "[--SP] = (R7:");
086134ec 950 OUTS (outf, imm5d (dr));
4b7f6baa 951 OUTS (outf, ", P5:");
086134ec 952 OUTS (outf, imm5d (pr));
4b7f6baa 953 OUTS (outf, ")");
4b7f6baa 954 }
219b747a 955 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 956 {
4b7f6baa 957 OUTS (outf, "[--SP] = (R7:");
086134ec 958 OUTS (outf, imm5d (dr));
4b7f6baa 959 OUTS (outf, ")");
4b7f6baa 960 }
219b747a 961 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 962 {
4b7f6baa 963 OUTS (outf, "[--SP] = (P5:");
086134ec 964 OUTS (outf, imm5d (pr));
4b7f6baa 965 OUTS (outf, ")");
4b7f6baa
CM		 966 }
967 else if (W == 0 && d == 1 && p == 1)
968 {
4b7f6baa 969 OUTS (outf, "(R7:");
086134ec 970 OUTS (outf, imm5d (dr));
4b7f6baa 971 OUTS (outf, ", P5:");
086134ec 972 OUTS (outf, imm5d (pr));
4b7f6baa 973 OUTS (outf, ") = [SP++]");
4b7f6baa 974 }
219b747a 975 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 976 {
4b7f6baa 977 OUTS (outf, "(R7:");
086134ec 978 OUTS (outf, imm5d (dr));
4b7f6baa 979 OUTS (outf, ") = [SP++]");
4b7f6baa 980 }
219b747a 981 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 982 {
4b7f6baa 983 OUTS (outf, "(P5:");
086134ec 984 OUTS (outf, imm5d (pr));
4b7f6baa 985 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 986 }
987 else
b7d48530
NC		 988 return 0;
989 return 2;
4b7f6baa
CM		 990}
991
992static int
993decode_ccMV_0 (TIword iw0, disassemble_info *outf)
994{
b7d48530
NC		 995 /* ccMV
996 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
997 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
998 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 999 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1000 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1001 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1002 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1003 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1004
219b747a
MF		 1005 if (parallel)
1006 return 0;
1007
4b7f6baa
CM		 1008 if (T == 1)
1009 {
4b7f6baa
CM		 1010 OUTS (outf, "IF CC ");
1011 OUTS (outf, gregs (dst, d));
1012 OUTS (outf, " = ");
1013 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1014 }
1015 else if (T == 0)
1016 {
086134ec 1017 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 1018 OUTS (outf, gregs (dst, d));
1019 OUTS (outf, " = ");
1020 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1021 }
1022 else
b7d48530
NC		 1023 return 0;
1024 return 2;
4b7f6baa
CM		 1025}
1026
1027static int
1028decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1029{
b7d48530
NC		 1030 /* CCflag
1031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1032 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1033 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1034 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1035 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1036 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1037 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1038 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1039
219b747a
MF		 1040 if (parallel)
1041 return 0;
1042
4b7f6baa
CM		 1043 if (opc == 0 && I == 0 && G == 0)
1044 {
086134ec 1045 OUTS (outf, "CC = ");
4b7f6baa 1046 OUTS (outf, dregs (x));
086134ec 1047 OUTS (outf, " == ");
4b7f6baa 1048 OUTS (outf, dregs (y));
4b7f6baa
CM		 1049 }
1050 else if (opc == 1 && I == 0 && G == 0)
1051 {
086134ec 1052 OUTS (outf, "CC = ");
4b7f6baa 1053 OUTS (outf, dregs (x));
086134ec 1054 OUTS (outf, " < ");
4b7f6baa 1055 OUTS (outf, dregs (y));
4b7f6baa
CM		 1056 }
1057 else if (opc == 2 && I == 0 && G == 0)
1058 {
086134ec 1059 OUTS (outf, "CC = ");
4b7f6baa 1060 OUTS (outf, dregs (x));
086134ec 1061 OUTS (outf, " <= ");
4b7f6baa 1062 OUTS (outf, dregs (y));
4b7f6baa
CM		 1063 }
1064 else if (opc == 3 && I == 0 && G == 0)
1065 {
086134ec 1066 OUTS (outf, "CC = ");
4b7f6baa 1067 OUTS (outf, dregs (x));
086134ec 1068 OUTS (outf, " < ");
4b7f6baa 1069 OUTS (outf, dregs (y));
086134ec 1070 OUTS (outf, " (IU)");
4b7f6baa
CM		 1071 }
1072 else if (opc == 4 && I == 0 && G == 0)
1073 {
086134ec 1074 OUTS (outf, "CC = ");
4b7f6baa 1075 OUTS (outf, dregs (x));
086134ec 1076 OUTS (outf, " <= ");
4b7f6baa 1077 OUTS (outf, dregs (y));
086134ec 1078 OUTS (outf, " (IU)");
4b7f6baa
CM		 1079 }
1080 else if (opc == 0 && I == 1 && G == 0)
1081 {
086134ec 1082 OUTS (outf, "CC = ");
4b7f6baa 1083 OUTS (outf, dregs (x));
086134ec 1084 OUTS (outf, " == ");
4b7f6baa 1085 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1086 }
1087 else if (opc == 1 && I == 1 && G == 0)
1088 {
086134ec 1089 OUTS (outf, "CC = ");
4b7f6baa 1090 OUTS (outf, dregs (x));
086134ec 1091 OUTS (outf, " < ");
4b7f6baa 1092 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1093 }
1094 else if (opc == 2 && I == 1 && G == 0)
1095 {
086134ec 1096 OUTS (outf, "CC = ");
4b7f6baa 1097 OUTS (outf, dregs (x));
086134ec 1098 OUTS (outf, " <= ");
4b7f6baa 1099 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1100 }
1101 else if (opc == 3 && I == 1 && G == 0)
1102 {
086134ec 1103 OUTS (outf, "CC = ");
4b7f6baa 1104 OUTS (outf, dregs (x));
086134ec 1105 OUTS (outf, " < ");
4b7f6baa 1106 OUTS (outf, uimm3 (y));
086134ec 1107 OUTS (outf, " (IU)");
4b7f6baa
CM		 1108 }
1109 else if (opc == 4 && I == 1 && G == 0)
1110 {
086134ec 1111 OUTS (outf, "CC = ");
4b7f6baa 1112 OUTS (outf, dregs (x));
086134ec 1113 OUTS (outf, " <= ");
4b7f6baa 1114 OUTS (outf, uimm3 (y));
086134ec 1115 OUTS (outf, " (IU)");
4b7f6baa
CM		 1116 }
1117 else if (opc == 0 && I == 0 && G == 1)
1118 {
086134ec 1119 OUTS (outf, "CC = ");
4b7f6baa 1120 OUTS (outf, pregs (x));
086134ec 1121 OUTS (outf, " == ");
4b7f6baa 1122 OUTS (outf, pregs (y));
4b7f6baa
CM		 1123 }
1124 else if (opc == 1 && I == 0 && G == 1)
1125 {
086134ec 1126 OUTS (outf, "CC = ");
4b7f6baa 1127 OUTS (outf, pregs (x));
086134ec 1128 OUTS (outf, " < ");
4b7f6baa 1129 OUTS (outf, pregs (y));
4b7f6baa
CM		 1130 }
1131 else if (opc == 2 && I == 0 && G == 1)
1132 {
086134ec 1133 OUTS (outf, "CC = ");
4b7f6baa 1134 OUTS (outf, pregs (x));
086134ec 1135 OUTS (outf, " <= ");
4b7f6baa 1136 OUTS (outf, pregs (y));
4b7f6baa
CM		 1137 }
1138 else if (opc == 3 && I == 0 && G == 1)
1139 {
086134ec 1140 OUTS (outf, "CC = ");
4b7f6baa 1141 OUTS (outf, pregs (x));
086134ec 1142 OUTS (outf, " < ");
4b7f6baa 1143 OUTS (outf, pregs (y));
086134ec 1144 OUTS (outf, " (IU)");
4b7f6baa
CM		 1145 }
1146 else if (opc == 4 && I == 0 && G == 1)
1147 {
086134ec 1148 OUTS (outf, "CC = ");
4b7f6baa 1149 OUTS (outf, pregs (x));
086134ec 1150 OUTS (outf, " <= ");
4b7f6baa 1151 OUTS (outf, pregs (y));
086134ec 1152 OUTS (outf, " (IU)");
4b7f6baa
CM		 1153 }
1154 else if (opc == 0 && I == 1 && G == 1)
1155 {
086134ec 1156 OUTS (outf, "CC = ");
4b7f6baa 1157 OUTS (outf, pregs (x));
086134ec 1158 OUTS (outf, " == ");
4b7f6baa 1159 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1160 }
1161 else if (opc == 1 && I == 1 && G == 1)
1162 {
086134ec 1163 OUTS (outf, "CC = ");
4b7f6baa 1164 OUTS (outf, pregs (x));
086134ec 1165 OUTS (outf, " < ");
4b7f6baa 1166 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1167 }
1168 else if (opc == 2 && I == 1 && G == 1)
1169 {
086134ec 1170 OUTS (outf, "CC = ");
4b7f6baa 1171 OUTS (outf, pregs (x));
086134ec 1172 OUTS (outf, " <= ");
4b7f6baa 1173 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1174 }
1175 else if (opc == 3 && I == 1 && G == 1)
1176 {
086134ec 1177 OUTS (outf, "CC = ");
4b7f6baa 1178 OUTS (outf, pregs (x));
086134ec 1179 OUTS (outf, " < ");
4b7f6baa 1180 OUTS (outf, uimm3 (y));
086134ec 1181 OUTS (outf, " (IU)");
4b7f6baa
CM		 1182 }
1183 else if (opc == 4 && I == 1 && G == 1)
1184 {
086134ec 1185 OUTS (outf, "CC = ");
4b7f6baa 1186 OUTS (outf, pregs (x));
086134ec 1187 OUTS (outf, " <= ");
4b7f6baa 1188 OUTS (outf, uimm3 (y));
086134ec 1189 OUTS (outf, " (IU)");
4b7f6baa 1190 }
219b747a 1191 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1192 OUTS (outf, "CC = A0 == A1");
b7d48530 1193
219b747a 1194 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1195 OUTS (outf, "CC = A0 < A1");
b7d48530 1196
219b747a 1197 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1198 OUTS (outf, "CC = A0 <= A1");
b7d48530 1199
4b7f6baa 1200 else
b7d48530
NC		 1201 return 0;
1202 return 2;
4b7f6baa
CM		 1203}
1204
1205static int
1206decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1207{
b7d48530
NC		 1208 /* CC2dreg
1209 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1211 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1212 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1213 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1214
219b747a
MF		 1215 if (parallel)
1216 return 0;
1217
4b7f6baa
CM		 1218 if (op == 0)
1219 {
4b7f6baa 1220 OUTS (outf, dregs (reg));
086134ec 1221 OUTS (outf, " = CC");
4b7f6baa
CM		 1222 }
1223 else if (op == 1)
1224 {
086134ec 1225 OUTS (outf, "CC = ");
4b7f6baa 1226 OUTS (outf, dregs (reg));
4b7f6baa 1227 }
50e2162a 1228 else if (op == 3 && reg == 0)
086134ec 1229 OUTS (outf, "CC = !CC");
4b7f6baa 1230 else
b7d48530
NC		 1231 return 0;
1232
1233 return 2;
4b7f6baa
CM		 1234}
1235
1236static int
1237decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1238{
b7d48530
NC		 1239 /* CC2stat
1240 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1241 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1242 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1243 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1244 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1245 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1246
b2459327 1247 const char *bitname = statbits (cbit);
219b747a
MF		 1248
1249 if (parallel)
1250 return 0;
1251
b2459327
MF		 1252 if (decode_statbits[cbit] == REG_LASTREG)
1253 {
1254 /* All ASTAT bits except CC may be operated on in hardware, but may
1255 not have a dedicated insn, so still decode "valid" insns. */
1256 static char bitnames[64];
1257 if (cbit != 5)
1258 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1259 else
219b747a
MF		 1260 return 0;
1261
b2459327
MF		 1262 bitname = bitnames;
1263 }
1264
4b7f6baa
CM		 1265 if (op == 0 && D == 0)
1266 {
4b7f6baa 1267 OUTS (outf, "CC = ");
b2459327 1268 OUTS (outf, bitname);
4b7f6baa
CM		 1269 }
1270 else if (op == 1 && D == 0)
1271 {
086134ec 1272 OUTS (outf, "CC |= ");
b2459327 1273 OUTS (outf, bitname);
4b7f6baa
CM		 1274 }
1275 else if (op == 2 && D == 0)
1276 {
086134ec 1277 OUTS (outf, "CC &= ");
b2459327 1278 OUTS (outf, bitname);
4b7f6baa
CM		 1279 }
1280 else if (op == 3 && D == 0)
1281 {
086134ec 1282 OUTS (outf, "CC ^= ");
b2459327 1283 OUTS (outf, bitname);
4b7f6baa
CM		 1284 }
1285 else if (op == 0 && D == 1)
1286 {
b2459327 1287 OUTS (outf, bitname);
086134ec 1288 OUTS (outf, " = CC");
4b7f6baa
CM		 1289 }
1290 else if (op == 1 && D == 1)
1291 {
b2459327 1292 OUTS (outf, bitname);
086134ec 1293 OUTS (outf, " |= CC");
4b7f6baa
CM		 1294 }
1295 else if (op == 2 && D == 1)
1296 {
b2459327 1297 OUTS (outf, bitname);
086134ec 1298 OUTS (outf, " &= CC");
4b7f6baa
CM		 1299 }
1300 else if (op == 3 && D == 1)
1301 {
b2459327 1302 OUTS (outf, bitname);
086134ec 1303 OUTS (outf, " ^= CC");
4b7f6baa
CM		 1304 }
1305 else
b7d48530
NC		 1306 return 0;
1307
1308 return 2;
4b7f6baa
CM		 1309}
1310
1311static int
1312decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1313{
b7d48530
NC		 1314 /* BRCC
1315 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1316 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1317 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1318 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1319 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1320 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1321
219b747a
MF		 1322 if (parallel)
1323 return 0;
1324
4b7f6baa
CM		 1325 if (T == 1 && B == 1)
1326 {
086134ec 1327 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1328 OUTS (outf, pcrel10 (offset));
086134ec 1329 OUTS (outf, " (BP)");
4b7f6baa
CM		 1330 }
1331 else if (T == 0 && B == 1)
1332 {
086134ec 1333 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1334 OUTS (outf, pcrel10 (offset));
086134ec 1335 OUTS (outf, " (BP)");
4b7f6baa
CM		 1336 }
1337 else if (T == 1)
1338 {
086134ec 1339 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1340 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1341 }
1342 else if (T == 0)
1343 {
086134ec 1344 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1345 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1346 }
1347 else
b7d48530
NC		 1348 return 0;
1349
1350 return 2;
4b7f6baa
CM		 1351}
1352
1353static int
1354decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1355{
b7d48530
NC		 1356 /* UJUMP
1357 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1358 | 0 | 0 | 1 | 0 |.offset........................................|
1359 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1360 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1361
219b747a
MF		 1362 if (parallel)
1363 return 0;
1364
086134ec 1365 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1366 OUTS (outf, pcrel12 (offset));
b7d48530 1367 return 2;
4b7f6baa
CM		 1368}
1369
1370static int
1371decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1372{
b7d48530
NC		 1373 /* REGMV
1374 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1375 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1376 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1377 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1378 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1379 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1380 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1381
35fc57f3
MF		 1382 /* Reserved slots cannot be a src/dst. */
1383 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1384 goto invalid_move;
1385
1386 /* Standard register moves */
1387 if ((gs < 2) || /* Dregs/Pregs as source */
1388 (gd < 2) || /* Dregs/Pregs as dest */
1389 (gs == 4 && src < 4) || /* Accumulators as source */
1390 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1391 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1392 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1393 goto valid_move;
1394
1395 /* dareg = dareg (IMBL) */
1396 if (gs < 4 && gd < 4)
1397 goto valid_move;
1398
1399 /* USP can be src to sysregs, but not dagregs. */
1400 if ((gs == 7 && src == 0) && (gd >= 4))
1401 goto valid_move;
1402
1403 /* USP can move between genregs (only check Accumulators). */
1404 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1405 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1406 goto valid_move;
1407
1408 /* Still here ? Invalid reg pair. */
1409 invalid_move:
1410 return 0;
c958a8a8 1411
35fc57f3 1412 valid_move:
4b7f6baa 1413 OUTS (outf, allregs (dst, gd));
086134ec 1414 OUTS (outf, " = ");
4b7f6baa 1415 OUTS (outf, allregs (src, gs));
b7d48530 1416 return 2;
4b7f6baa
CM		 1417}
1418
1419static int
1420decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1421{
b7d48530
NC		 1422 /* ALU2op
1423 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1424 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1426 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1427 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1428 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1429
1430 if (opc == 0)
1431 {
4b7f6baa 1432 OUTS (outf, dregs (dst));
086134ec 1433 OUTS (outf, " >>>= ");
4b7f6baa 1434 OUTS (outf, dregs (src));
4b7f6baa
CM		 1435 }
1436 else if (opc == 1)
1437 {
4b7f6baa 1438 OUTS (outf, dregs (dst));
086134ec 1439 OUTS (outf, " >>= ");
4b7f6baa 1440 OUTS (outf, dregs (src));
4b7f6baa
CM		 1441 }
1442 else if (opc == 2)
1443 {
4b7f6baa 1444 OUTS (outf, dregs (dst));
086134ec 1445 OUTS (outf, " <<= ");
4b7f6baa 1446 OUTS (outf, dregs (src));
4b7f6baa
CM		 1447 }
1448 else if (opc == 3)
1449 {
4b7f6baa 1450 OUTS (outf, dregs (dst));
086134ec 1451 OUTS (outf, " *= ");
4b7f6baa 1452 OUTS (outf, dregs (src));
4b7f6baa
CM		 1453 }
1454 else if (opc == 4)
1455 {
4b7f6baa 1456 OUTS (outf, dregs (dst));
086134ec 1457 OUTS (outf, " = (");
4b7f6baa 1458 OUTS (outf, dregs (dst));
086134ec 1459 OUTS (outf, " + ");
4b7f6baa 1460 OUTS (outf, dregs (src));
086134ec 1461 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1462 }
1463 else if (opc == 5)
1464 {
4b7f6baa 1465 OUTS (outf, dregs (dst));
086134ec 1466 OUTS (outf, " = (");
4b7f6baa 1467 OUTS (outf, dregs (dst));
086134ec 1468 OUTS (outf, " + ");
4b7f6baa 1469 OUTS (outf, dregs (src));
086134ec 1470 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1471 }
1472 else if (opc == 8)
1473 {
086134ec 1474 OUTS (outf, "DIVQ (");
4b7f6baa 1475 OUTS (outf, dregs (dst));
086134ec 1476 OUTS (outf, ", ");
4b7f6baa
CM		 1477 OUTS (outf, dregs (src));
1478 OUTS (outf, ")");
4b7f6baa
CM		 1479 }
1480 else if (opc == 9)
1481 {
086134ec 1482 OUTS (outf, "DIVS (");
4b7f6baa 1483 OUTS (outf, dregs (dst));
086134ec 1484 OUTS (outf, ", ");
4b7f6baa
CM		 1485 OUTS (outf, dregs (src));
1486 OUTS (outf, ")");
4b7f6baa
CM		 1487 }
1488 else if (opc == 10)
1489 {
4b7f6baa 1490 OUTS (outf, dregs (dst));
086134ec 1491 OUTS (outf, " = ");
4b7f6baa 1492 OUTS (outf, dregs_lo (src));
086134ec 1493 OUTS (outf, " (X)");
4b7f6baa
CM		 1494 }
1495 else if (opc == 11)
1496 {
4b7f6baa 1497 OUTS (outf, dregs (dst));
086134ec 1498 OUTS (outf, " = ");
4b7f6baa 1499 OUTS (outf, dregs_lo (src));
086134ec 1500 OUTS (outf, " (Z)");
4b7f6baa
CM		 1501 }
1502 else if (opc == 12)
1503 {
4b7f6baa 1504 OUTS (outf, dregs (dst));
086134ec 1505 OUTS (outf, " = ");
4b7f6baa 1506 OUTS (outf, dregs_byte (src));
086134ec 1507 OUTS (outf, " (X)");
4b7f6baa
CM		 1508 }
1509 else if (opc == 13)
1510 {
4b7f6baa 1511 OUTS (outf, dregs (dst));
086134ec 1512 OUTS (outf, " = ");
4b7f6baa 1513 OUTS (outf, dregs_byte (src));
086134ec 1514 OUTS (outf, " (Z)");
4b7f6baa
CM		 1515 }
1516 else if (opc == 14)
1517 {
4b7f6baa 1518 OUTS (outf, dregs (dst));
086134ec 1519 OUTS (outf, " = -");
4b7f6baa 1520 OUTS (outf, dregs (src));
4b7f6baa
CM		 1521 }
1522 else if (opc == 15)
1523 {
4b7f6baa 1524 OUTS (outf, dregs (dst));
086134ec 1525 OUTS (outf, " =~ ");
4b7f6baa 1526 OUTS (outf, dregs (src));
4b7f6baa
CM		 1527 }
1528 else
b7d48530
NC		 1529 return 0;
1530
1531 return 2;
4b7f6baa
CM		 1532}
1533
1534static int
1535decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1536{
b7d48530
NC		 1537 /* PTR2op
1538 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1539 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1541 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1542 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1543 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1544
1545 if (opc == 0)
1546 {
4b7f6baa 1547 OUTS (outf, pregs (dst));
086134ec 1548 OUTS (outf, " -= ");
4b7f6baa 1549 OUTS (outf, pregs (src));
4b7f6baa
CM		 1550 }
1551 else if (opc == 1)
1552 {
4b7f6baa 1553 OUTS (outf, pregs (dst));
086134ec 1554 OUTS (outf, " = ");
4b7f6baa 1555 OUTS (outf, pregs (src));
086134ec 1556 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1557 }
1558 else if (opc == 3)
1559 {
4b7f6baa 1560 OUTS (outf, pregs (dst));
086134ec 1561 OUTS (outf, " = ");
4b7f6baa 1562 OUTS (outf, pregs (src));
086134ec 1563 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1564 }
1565 else if (opc == 4)
1566 {
4b7f6baa 1567 OUTS (outf, pregs (dst));
086134ec 1568 OUTS (outf, " = ");
4b7f6baa 1569 OUTS (outf, pregs (src));
086134ec 1570 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1571 }
1572 else if (opc == 5)
1573 {
4b7f6baa 1574 OUTS (outf, pregs (dst));
086134ec 1575 OUTS (outf, " += ");
4b7f6baa 1576 OUTS (outf, pregs (src));
086134ec 1577 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1578 }
1579 else if (opc == 6)
1580 {
4b7f6baa 1581 OUTS (outf, pregs (dst));
086134ec 1582 OUTS (outf, " = (");
4b7f6baa 1583 OUTS (outf, pregs (dst));
086134ec 1584 OUTS (outf, " + ");
4b7f6baa 1585 OUTS (outf, pregs (src));
086134ec 1586 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1587 }
1588 else if (opc == 7)
1589 {
4b7f6baa 1590 OUTS (outf, pregs (dst));
086134ec 1591 OUTS (outf, " = (");
4b7f6baa 1592 OUTS (outf, pregs (dst));
086134ec 1593 OUTS (outf, " + ");
4b7f6baa 1594 OUTS (outf, pregs (src));
086134ec 1595 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1596 }
1597 else
b7d48530
NC		 1598 return 0;
1599
1600 return 2;
4b7f6baa
CM		 1601}
1602
1603static int
1604decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1605{
b7d48530
NC		 1606 /* LOGI2op
1607 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1608 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1609 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1610 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1611 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1612 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1613
219b747a
MF		 1614 if (parallel)
1615 return 0;
1616
4b7f6baa
CM		 1617 if (opc == 0)
1618 {
086134ec 1619 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1620 OUTS (outf, dregs (dst));
086134ec 1621 OUTS (outf, ", ");
4b7f6baa 1622 OUTS (outf, uimm5 (src));
086134ec
BS		 1623 OUTS (outf, ");\t\t/* bit");
1624 OUTS (outf, imm7d (src));
1625 OUTS (outf, " */");
1626 comment = 1;
4b7f6baa
CM		 1627 }
1628 else if (opc == 1)
1629 {
4b7f6baa
CM		 1630 OUTS (outf, "CC = BITTST (");
1631 OUTS (outf, dregs (dst));
086134ec 1632 OUTS (outf, ", ");
4b7f6baa 1633 OUTS (outf, uimm5 (src));
086134ec
BS		 1634 OUTS (outf, ");\t\t/* bit");
1635 OUTS (outf, imm7d (src));
1636 OUTS (outf, " */");
1637 comment = 1;
4b7f6baa
CM		 1638 }
1639 else if (opc == 2)
1640 {
4b7f6baa
CM		 1641 OUTS (outf, "BITSET (");
1642 OUTS (outf, dregs (dst));
086134ec 1643 OUTS (outf, ", ");
4b7f6baa 1644 OUTS (outf, uimm5 (src));
086134ec
BS		 1645 OUTS (outf, ");\t\t/* bit");
1646 OUTS (outf, imm7d (src));
1647 OUTS (outf, " */");
1648 comment = 1;
4b7f6baa
CM		 1649 }
1650 else if (opc == 3)
1651 {
4b7f6baa
CM		 1652 OUTS (outf, "BITTGL (");
1653 OUTS (outf, dregs (dst));
086134ec 1654 OUTS (outf, ", ");
4b7f6baa 1655 OUTS (outf, uimm5 (src));
086134ec
BS		 1656 OUTS (outf, ");\t\t/* bit");
1657 OUTS (outf, imm7d (src));
1658 OUTS (outf, " */");
1659 comment = 1;
4b7f6baa
CM		 1660 }
1661 else if (opc == 4)
1662 {
4b7f6baa
CM		 1663 OUTS (outf, "BITCLR (");
1664 OUTS (outf, dregs (dst));
086134ec 1665 OUTS (outf, ", ");
4b7f6baa 1666 OUTS (outf, uimm5 (src));
086134ec
BS		 1667 OUTS (outf, ");\t\t/* bit");
1668 OUTS (outf, imm7d (src));
1669 OUTS (outf, " */");
1670 comment = 1;
4b7f6baa
CM		 1671 }
1672 else if (opc == 5)
1673 {
4b7f6baa 1674 OUTS (outf, dregs (dst));
086134ec 1675 OUTS (outf, " >>>= ");
4b7f6baa 1676 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1677 }
1678 else if (opc == 6)
1679 {
4b7f6baa 1680 OUTS (outf, dregs (dst));
086134ec 1681 OUTS (outf, " >>= ");
4b7f6baa 1682 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1683 }
1684 else if (opc == 7)
1685 {
4b7f6baa 1686 OUTS (outf, dregs (dst));
086134ec 1687 OUTS (outf, " <<= ");
4b7f6baa 1688 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1689 }
1690 else
b7d48530
NC		 1691 return 0;
1692
1693 return 2;
4b7f6baa
CM		 1694}
1695
1696static int
1697decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1698{
b7d48530
NC		 1699 /* COMP3op
1700 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1701 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1702 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1703 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1704 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1705 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1706 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1707
1708 if (opc == 5 && src1 == src0)
1709 {
4b7f6baa 1710 OUTS (outf, pregs (dst));
086134ec 1711 OUTS (outf, " = ");
4b7f6baa 1712 OUTS (outf, pregs (src0));
086134ec 1713 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1714 }
1715 else if (opc == 1)
1716 {
4b7f6baa 1717 OUTS (outf, dregs (dst));
086134ec 1718 OUTS (outf, " = ");
4b7f6baa 1719 OUTS (outf, dregs (src0));
086134ec 1720 OUTS (outf, " - ");
4b7f6baa 1721 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1722 }
1723 else if (opc == 2)
1724 {
4b7f6baa 1725 OUTS (outf, dregs (dst));
086134ec 1726 OUTS (outf, " = ");
4b7f6baa 1727 OUTS (outf, dregs (src0));
086134ec 1728 OUTS (outf, " & ");
4b7f6baa 1729 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1730 }
1731 else if (opc == 3)
1732 {
4b7f6baa 1733 OUTS (outf, dregs (dst));
086134ec 1734 OUTS (outf, " = ");
4b7f6baa 1735 OUTS (outf, dregs (src0));
086134ec 1736 OUTS (outf, " | ");
4b7f6baa 1737 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1738 }
1739 else if (opc == 4)
1740 {
4b7f6baa 1741 OUTS (outf, dregs (dst));
086134ec 1742 OUTS (outf, " = ");
4b7f6baa 1743 OUTS (outf, dregs (src0));
086134ec 1744 OUTS (outf, " ^ ");
4b7f6baa 1745 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1746 }
1747 else if (opc == 5)
1748 {
4b7f6baa 1749 OUTS (outf, pregs (dst));
086134ec 1750 OUTS (outf, " = ");
4b7f6baa 1751 OUTS (outf, pregs (src0));
086134ec 1752 OUTS (outf, " + ");
4b7f6baa 1753 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1754 }
1755 else if (opc == 6)
1756 {
4b7f6baa 1757 OUTS (outf, pregs (dst));
086134ec 1758 OUTS (outf, " = ");
4b7f6baa 1759 OUTS (outf, pregs (src0));
086134ec 1760 OUTS (outf, " + (");
4b7f6baa 1761 OUTS (outf, pregs (src1));
086134ec 1762 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1763 }
1764 else if (opc == 7)
1765 {
4b7f6baa 1766 OUTS (outf, pregs (dst));
086134ec 1767 OUTS (outf, " = ");
4b7f6baa 1768 OUTS (outf, pregs (src0));
086134ec 1769 OUTS (outf, " + (");
4b7f6baa 1770 OUTS (outf, pregs (src1));
086134ec 1771 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1772 }
1773 else if (opc == 0)
1774 {
4b7f6baa 1775 OUTS (outf, dregs (dst));
086134ec 1776 OUTS (outf, " = ");
4b7f6baa 1777 OUTS (outf, dregs (src0));
086134ec 1778 OUTS (outf, " + ");
4b7f6baa 1779 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1780 }
1781 else
b7d48530
NC		 1782 return 0;
1783
1784 return 2;
4b7f6baa
CM		 1785}
1786
1787static int
1788decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1789{
b7d48530
NC		 1790 /* COMPI2opD
1791 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1792 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1793 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1794 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1795 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1796 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1797
086134ec
BS		 1798 bu32 *pval = get_allreg (0, dst);
1799
219b747a
MF		 1800 if (parallel)
1801 return 0;
1802
086134ec
BS		 1803 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1804 to combine them, so it prints out the right values.
1805 Here we keep track of the registers. */
1806 if (op == 0)
1807 {
1808 *pval = imm7_val (src);
1809 if (src & 0x40)
1810 *pval |= 0xFFFFFF80;
1811 else
1812 *pval &= 0x7F;
1813 }
1814
4b7f6baa
CM		 1815 if (op == 0)
1816 {
4b7f6baa 1817 OUTS (outf, dregs (dst));
086134ec 1818 OUTS (outf, " = ");
4b7f6baa 1819 OUTS (outf, imm7 (src));
086134ec
BS		 1820 OUTS (outf, " (X);\t\t/*\t\t");
1821 OUTS (outf, dregs (dst));
1822 OUTS (outf, "=");
1823 OUTS (outf, uimm32 (*pval));
1824 OUTS (outf, "(");
1825 OUTS (outf, imm32 (*pval));
1826 OUTS (outf, ") */");
1827 comment = 1;
4b7f6baa
CM		 1828 }
1829 else if (op == 1)
1830 {
4b7f6baa 1831 OUTS (outf, dregs (dst));
086134ec 1832 OUTS (outf, " += ");
4b7f6baa 1833 OUTS (outf, imm7 (src));
086134ec
BS		 1834 OUTS (outf, ";\t\t/* (");
1835 OUTS (outf, imm7d (src));
1836 OUTS (outf, ") */");
1837 comment = 1;
4b7f6baa
CM		 1838 }
1839 else
b7d48530
NC		 1840 return 0;
1841
1842 return 2;
4b7f6baa
CM		 1843}
1844
1845static int
1846decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1847{
b7d48530
NC		 1848 /* COMPI2opP
1849 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1850 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1851 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1852 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1853 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1854 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1855
086134ec
BS		 1856 bu32 *pval = get_allreg (1, dst);
1857
219b747a
MF		 1858 if (parallel)
1859 return 0;
1860
086134ec
BS		 1861 if (op == 0)
1862 {
1863 *pval = imm7_val (src);
1864 if (src & 0x40)
1865 *pval |= 0xFFFFFF80;
1866 else
1867 *pval &= 0x7F;
1868 }
1869
4b7f6baa
CM		 1870 if (op == 0)
1871 {
4b7f6baa 1872 OUTS (outf, pregs (dst));
086134ec 1873 OUTS (outf, " = ");
4b7f6baa 1874 OUTS (outf, imm7 (src));
086134ec
BS		 1875 OUTS (outf, " (X);\t\t/*\t\t");
1876 OUTS (outf, pregs (dst));
1877 OUTS (outf, "=");
1878 OUTS (outf, uimm32 (*pval));
1879 OUTS (outf, "(");
1880 OUTS (outf, imm32 (*pval));
1881 OUTS (outf, ") */");
1882 comment = 1;
4b7f6baa
CM		 1883 }
1884 else if (op == 1)
1885 {
4b7f6baa 1886 OUTS (outf, pregs (dst));
086134ec 1887 OUTS (outf, " += ");
4b7f6baa 1888 OUTS (outf, imm7 (src));
086134ec
BS		 1889 OUTS (outf, ";\t\t/* (");
1890 OUTS (outf, imm7d (src));
1891 OUTS (outf, ") */");
1892 comment = 1;
4b7f6baa
CM		 1893 }
1894 else
b7d48530
NC		 1895 return 0;
1896
1897 return 2;
4b7f6baa
CM		 1898}
1899
1900static int
1901decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1902{
b7d48530
NC		 1903 /* LDSTpmod
1904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1905 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1907 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1908 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1909 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1910 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1911 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1912
1913 if (aop == 1 && W == 0 && idx == ptr)
1914 {
4b7f6baa 1915 OUTS (outf, dregs_lo (reg));
086134ec 1916 OUTS (outf, " = W[");
4b7f6baa
CM		 1917 OUTS (outf, pregs (ptr));
1918 OUTS (outf, "]");
4b7f6baa
CM		 1919 }
1920 else if (aop == 2 && W == 0 && idx == ptr)
1921 {
4b7f6baa 1922 OUTS (outf, dregs_hi (reg));
086134ec 1923 OUTS (outf, " = W[");
4b7f6baa
CM		 1924 OUTS (outf, pregs (ptr));
1925 OUTS (outf, "]");
4b7f6baa
CM		 1926 }
1927 else if (aop == 1 && W == 1 && idx == ptr)
1928 {
4b7f6baa
CM		 1929 OUTS (outf, "W[");
1930 OUTS (outf, pregs (ptr));
086134ec 1931 OUTS (outf, "] = ");
4b7f6baa 1932 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1933 }
1934 else if (aop == 2 && W == 1 && idx == ptr)
1935 {
4b7f6baa
CM		 1936 OUTS (outf, "W[");
1937 OUTS (outf, pregs (ptr));
086134ec 1938 OUTS (outf, "] = ");
4b7f6baa 1939 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1940 }
1941 else if (aop == 0 && W == 0)
1942 {
4b7f6baa 1943 OUTS (outf, dregs (reg));
086134ec 1944 OUTS (outf, " = [");
4b7f6baa 1945 OUTS (outf, pregs (ptr));
086134ec 1946 OUTS (outf, " ++ ");
4b7f6baa
CM		 1947 OUTS (outf, pregs (idx));
1948 OUTS (outf, "]");
4b7f6baa
CM		 1949 }
1950 else if (aop == 1 && W == 0)
1951 {
4b7f6baa 1952 OUTS (outf, dregs_lo (reg));
086134ec 1953 OUTS (outf, " = W[");
4b7f6baa 1954 OUTS (outf, pregs (ptr));
086134ec 1955 OUTS (outf, " ++ ");
4b7f6baa
CM		 1956 OUTS (outf, pregs (idx));
1957 OUTS (outf, "]");
4b7f6baa
CM		 1958 }
1959 else if (aop == 2 && W == 0)
1960 {
4b7f6baa 1961 OUTS (outf, dregs_hi (reg));
086134ec 1962 OUTS (outf, " = W[");
4b7f6baa 1963 OUTS (outf, pregs (ptr));
086134ec 1964 OUTS (outf, " ++ ");
4b7f6baa
CM		 1965 OUTS (outf, pregs (idx));
1966 OUTS (outf, "]");
4b7f6baa
CM		 1967 }
1968 else if (aop == 3 && W == 0)
1969 {
4b7f6baa 1970 OUTS (outf, dregs (reg));
086134ec 1971 OUTS (outf, " = W[");
4b7f6baa 1972 OUTS (outf, pregs (ptr));
086134ec 1973 OUTS (outf, " ++ ");
4b7f6baa
CM		 1974 OUTS (outf, pregs (idx));
1975 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1976 }
1977 else if (aop == 3 && W == 1)
1978 {
4b7f6baa 1979 OUTS (outf, dregs (reg));
086134ec 1980 OUTS (outf, " = W[");
4b7f6baa 1981 OUTS (outf, pregs (ptr));
086134ec 1982 OUTS (outf, " ++ ");
4b7f6baa 1983 OUTS (outf, pregs (idx));
086134ec 1984 OUTS (outf, "] (X)");
4b7f6baa
CM		 1985 }
1986 else if (aop == 0 && W == 1)
1987 {
4b7f6baa
CM		 1988 OUTS (outf, "[");
1989 OUTS (outf, pregs (ptr));
086134ec 1990 OUTS (outf, " ++ ");
4b7f6baa 1991 OUTS (outf, pregs (idx));
086134ec 1992 OUTS (outf, "] = ");
4b7f6baa 1993 OUTS (outf, dregs (reg));
4b7f6baa
CM		 1994 }
1995 else if (aop == 1 && W == 1)
1996 {
4b7f6baa
CM		 1997 OUTS (outf, "W[");
1998 OUTS (outf, pregs (ptr));
086134ec 1999 OUTS (outf, " ++ ");
4b7f6baa 2000 OUTS (outf, pregs (idx));
086134ec 2001 OUTS (outf, "] = ");
4b7f6baa 2002 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2003 }
2004 else if (aop == 2 && W == 1)
2005 {
4b7f6baa
CM		 2006 OUTS (outf, "W[");
2007 OUTS (outf, pregs (ptr));
086134ec 2008 OUTS (outf, " ++ ");
4b7f6baa 2009 OUTS (outf, pregs (idx));
086134ec 2010 OUTS (outf, "] = ");
4b7f6baa 2011 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2012 }
2013 else
b7d48530
NC		 2014 return 0;
2015
2016 return 2;
4b7f6baa
CM		 2017}
2018
2019static int
2020decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2021{
b7d48530
NC		 2022 /* dagMODim
2023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2024 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2025 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2026 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2027 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2028 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2029 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2030
2031 if (op == 0 && br == 1)
2032 {
4b7f6baa 2033 OUTS (outf, iregs (i));
086134ec 2034 OUTS (outf, " += ");
4b7f6baa 2035 OUTS (outf, mregs (m));
086134ec 2036 OUTS (outf, " (BREV)");
4b7f6baa
CM		 2037 }
2038 else if (op == 0)
2039 {
4b7f6baa 2040 OUTS (outf, iregs (i));
086134ec 2041 OUTS (outf, " += ");
4b7f6baa 2042 OUTS (outf, mregs (m));
4b7f6baa 2043 }
219b747a 2044 else if (op == 1 && br == 0)
4b7f6baa 2045 {
4b7f6baa 2046 OUTS (outf, iregs (i));
086134ec 2047 OUTS (outf, " -= ");
4b7f6baa 2048 OUTS (outf, mregs (m));
4b7f6baa
CM		 2049 }
2050 else
b7d48530
NC		 2051 return 0;
2052
2053 return 2;
4b7f6baa
CM		 2054}
2055
2056static int
2057decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2058{
b7d48530
NC		 2059 /* dagMODik
2060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2061 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2063 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2064 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2065
2066 if (op == 0)
2067 {
4b7f6baa 2068 OUTS (outf, iregs (i));
086134ec 2069 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2070 }
2071 else if (op == 1)
2072 {
4b7f6baa 2073 OUTS (outf, iregs (i));
086134ec 2074 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2075 }
2076 else if (op == 2)
2077 {
4b7f6baa 2078 OUTS (outf, iregs (i));
086134ec 2079 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2080 }
2081 else if (op == 3)
2082 {
4b7f6baa 2083 OUTS (outf, iregs (i));
086134ec 2084 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2085 }
2086 else
b7d48530
NC		 2087 return 0;
2088
086134ec
BS		 2089 if (! parallel )
2090 {
2091 OUTS (outf, ";\t\t/* ( ");
2092 if (op == 0 || op == 1)
2093 OUTS (outf, "2");
2094 else if (op == 2 || op == 3)
2095 OUTS (outf, "4");
2096 OUTS (outf, ") */");
2097 comment = 1;
2098 }
2099
b7d48530 2100 return 2;
4b7f6baa
CM		 2101}
2102
2103static int
2104decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2105{
b7d48530
NC		 2106 /* dspLDST
2107 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2108 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2109 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2110 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2111 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2112 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2113 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2114 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2115
2116 if (aop == 0 && W == 0 && m == 0)
2117 {
4b7f6baa 2118 OUTS (outf, dregs (reg));
086134ec 2119 OUTS (outf, " = [");
4b7f6baa
CM		 2120 OUTS (outf, iregs (i));
2121 OUTS (outf, "++]");
4b7f6baa
CM		 2122 }
2123 else if (aop == 0 && W == 0 && m == 1)
2124 {
4b7f6baa 2125 OUTS (outf, dregs_lo (reg));
086134ec 2126 OUTS (outf, " = W[");
4b7f6baa
CM		 2127 OUTS (outf, iregs (i));
2128 OUTS (outf, "++]");
4b7f6baa
CM		 2129 }
2130 else if (aop == 0 && W == 0 && m == 2)
2131 {
4b7f6baa 2132 OUTS (outf, dregs_hi (reg));
086134ec 2133 OUTS (outf, " = W[");
4b7f6baa
CM		 2134 OUTS (outf, iregs (i));
2135 OUTS (outf, "++]");
4b7f6baa
CM		 2136 }
2137 else if (aop == 1 && W == 0 && m == 0)
2138 {
4b7f6baa 2139 OUTS (outf, dregs (reg));
086134ec 2140 OUTS (outf, " = [");
4b7f6baa
CM		 2141 OUTS (outf, iregs (i));
2142 OUTS (outf, "--]");
4b7f6baa
CM		 2143 }
2144 else if (aop == 1 && W == 0 && m == 1)
2145 {
4b7f6baa 2146 OUTS (outf, dregs_lo (reg));
086134ec 2147 OUTS (outf, " = W[");
4b7f6baa
CM		 2148 OUTS (outf, iregs (i));
2149 OUTS (outf, "--]");
4b7f6baa
CM		 2150 }
2151 else if (aop == 1 && W == 0 && m == 2)
2152 {
4b7f6baa 2153 OUTS (outf, dregs_hi (reg));
086134ec 2154 OUTS (outf, " = W[");
4b7f6baa
CM		 2155 OUTS (outf, iregs (i));
2156 OUTS (outf, "--]");
4b7f6baa
CM		 2157 }
2158 else if (aop == 2 && W == 0 && m == 0)
2159 {
4b7f6baa 2160 OUTS (outf, dregs (reg));
086134ec 2161 OUTS (outf, " = [");
4b7f6baa
CM		 2162 OUTS (outf, iregs (i));
2163 OUTS (outf, "]");
4b7f6baa
CM		 2164 }
2165 else if (aop == 2 && W == 0 && m == 1)
2166 {
4b7f6baa 2167 OUTS (outf, dregs_lo (reg));
086134ec 2168 OUTS (outf, " = W[");
4b7f6baa
CM		 2169 OUTS (outf, iregs (i));
2170 OUTS (outf, "]");
4b7f6baa
CM		 2171 }
2172 else if (aop == 2 && W == 0 && m == 2)
2173 {
4b7f6baa 2174 OUTS (outf, dregs_hi (reg));
086134ec 2175 OUTS (outf, " = W[");
4b7f6baa
CM		 2176 OUTS (outf, iregs (i));
2177 OUTS (outf, "]");
4b7f6baa
CM		 2178 }
2179 else if (aop == 0 && W == 1 && m == 0)
2180 {
4b7f6baa
CM		 2181 OUTS (outf, "[");
2182 OUTS (outf, iregs (i));
086134ec 2183 OUTS (outf, "++] = ");
4b7f6baa 2184 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2185 }
2186 else if (aop == 0 && W == 1 && m == 1)
2187 {
4b7f6baa
CM		 2188 OUTS (outf, "W[");
2189 OUTS (outf, iregs (i));
086134ec 2190 OUTS (outf, "++] = ");
4b7f6baa 2191 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2192 }
2193 else if (aop == 0 && W == 1 && m == 2)
2194 {
4b7f6baa
CM		 2195 OUTS (outf, "W[");
2196 OUTS (outf, iregs (i));
086134ec 2197 OUTS (outf, "++] = ");
4b7f6baa 2198 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2199 }
2200 else if (aop == 1 && W == 1 && m == 0)
2201 {
4b7f6baa
CM		 2202 OUTS (outf, "[");
2203 OUTS (outf, iregs (i));
086134ec 2204 OUTS (outf, "--] = ");
4b7f6baa 2205 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2206 }
2207 else if (aop == 1 && W == 1 && m == 1)
2208 {
4b7f6baa
CM		 2209 OUTS (outf, "W[");
2210 OUTS (outf, iregs (i));
086134ec 2211 OUTS (outf, "--] = ");
4b7f6baa 2212 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2213 }
2214 else if (aop == 1 && W == 1 && m == 2)
2215 {
4b7f6baa
CM		 2216 OUTS (outf, "W[");
2217 OUTS (outf, iregs (i));
086134ec 2218 OUTS (outf, "--] = ");
4b7f6baa 2219 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2220 }
2221 else if (aop == 2 && W == 1 && m == 0)
2222 {
4b7f6baa
CM		 2223 OUTS (outf, "[");
2224 OUTS (outf, iregs (i));
086134ec 2225 OUTS (outf, "] = ");
4b7f6baa 2226 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2227 }
2228 else if (aop == 2 && W == 1 && m == 1)
2229 {
4b7f6baa
CM		 2230 OUTS (outf, "W[");
2231 OUTS (outf, iregs (i));
086134ec 2232 OUTS (outf, "] = ");
4b7f6baa 2233 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2234 }
2235 else if (aop == 2 && W == 1 && m == 2)
2236 {
4b7f6baa
CM		 2237 OUTS (outf, "W[");
2238 OUTS (outf, iregs (i));
086134ec 2239 OUTS (outf, "] = ");
4b7f6baa 2240 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2241 }
2242 else if (aop == 3 && W == 0)
2243 {
4b7f6baa 2244 OUTS (outf, dregs (reg));
086134ec 2245 OUTS (outf, " = [");
4b7f6baa 2246 OUTS (outf, iregs (i));
086134ec 2247 OUTS (outf, " ++ ");
4b7f6baa
CM		 2248 OUTS (outf, mregs (m));
2249 OUTS (outf, "]");
4b7f6baa
CM		 2250 }
2251 else if (aop == 3 && W == 1)
2252 {
4b7f6baa
CM		 2253 OUTS (outf, "[");
2254 OUTS (outf, iregs (i));
086134ec 2255 OUTS (outf, " ++ ");
4b7f6baa 2256 OUTS (outf, mregs (m));
086134ec 2257 OUTS (outf, "] = ");
4b7f6baa 2258 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2259 }
2260 else
b7d48530
NC		 2261 return 0;
2262
2263 return 2;
4b7f6baa
CM		 2264}
2265
2266static int
2267decode_LDST_0 (TIword iw0, disassemble_info *outf)
2268{
b7d48530
NC		 2269 /* LDST
2270 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2271 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2272 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2273 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2274 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2275 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2276 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2277 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2278 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2279
2280 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2281 {
4b7f6baa 2282 OUTS (outf, dregs (reg));
086134ec 2283 OUTS (outf, " = [");
4b7f6baa
CM		 2284 OUTS (outf, pregs (ptr));
2285 OUTS (outf, "++]");
4b7f6baa 2286 }
219b747a 2287 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2288 {
4b7f6baa 2289 OUTS (outf, pregs (reg));
086134ec 2290 OUTS (outf, " = [");
4b7f6baa
CM		 2291 OUTS (outf, pregs (ptr));
2292 OUTS (outf, "++]");
4b7f6baa
CM		 2293 }
2294 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2295 {
4b7f6baa 2296 OUTS (outf, dregs (reg));
086134ec 2297 OUTS (outf, " = W[");
4b7f6baa
CM		 2298 OUTS (outf, pregs (ptr));
2299 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2300 }
2301 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2302 {
4b7f6baa 2303 OUTS (outf, dregs (reg));
086134ec 2304 OUTS (outf, " = W[");
4b7f6baa 2305 OUTS (outf, pregs (ptr));
086134ec 2306 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2307 }
2308 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2309 {
4b7f6baa 2310 OUTS (outf, dregs (reg));
086134ec 2311 OUTS (outf, " = B[");
4b7f6baa
CM		 2312 OUTS (outf, pregs (ptr));
2313 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2314 }
2315 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2316 {
4b7f6baa 2317 OUTS (outf, dregs (reg));
086134ec 2318 OUTS (outf, " = B[");
4b7f6baa 2319 OUTS (outf, pregs (ptr));
086134ec 2320 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2321 }
2322 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2323 {
4b7f6baa 2324 OUTS (outf, dregs (reg));
086134ec 2325 OUTS (outf, " = [");
4b7f6baa
CM		 2326 OUTS (outf, pregs (ptr));
2327 OUTS (outf, "--]");
4b7f6baa 2328 }
219b747a 2329 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2330 {
4b7f6baa 2331 OUTS (outf, pregs (reg));
086134ec 2332 OUTS (outf, " = [");
4b7f6baa
CM		 2333 OUTS (outf, pregs (ptr));
2334 OUTS (outf, "--]");
4b7f6baa
CM		 2335 }
2336 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2337 {
4b7f6baa 2338 OUTS (outf, dregs (reg));
086134ec 2339 OUTS (outf, " = W[");
4b7f6baa
CM		 2340 OUTS (outf, pregs (ptr));
2341 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2342 }
2343 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2344 {
4b7f6baa 2345 OUTS (outf, dregs (reg));
086134ec 2346 OUTS (outf, " = W[");
4b7f6baa 2347 OUTS (outf, pregs (ptr));
086134ec 2348 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2349 }
2350 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2351 {
4b7f6baa 2352 OUTS (outf, dregs (reg));
086134ec 2353 OUTS (outf, " = B[");
4b7f6baa
CM		 2354 OUTS (outf, pregs (ptr));
2355 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2356 }
2357 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2358 {
4b7f6baa 2359 OUTS (outf, dregs (reg));
086134ec 2360 OUTS (outf, " = B[");
4b7f6baa 2361 OUTS (outf, pregs (ptr));
086134ec 2362 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2363 }
2364 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2365 {
4b7f6baa 2366 OUTS (outf, dregs (reg));
086134ec 2367 OUTS (outf, " = [");
4b7f6baa
CM		 2368 OUTS (outf, pregs (ptr));
2369 OUTS (outf, "]");
4b7f6baa
CM		 2370 }
2371 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2372 {
4b7f6baa 2373 OUTS (outf, pregs (reg));
086134ec 2374 OUTS (outf, " = [");
4b7f6baa
CM		 2375 OUTS (outf, pregs (ptr));
2376 OUTS (outf, "]");
4b7f6baa
CM		 2377 }
2378 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2379 {
4b7f6baa 2380 OUTS (outf, dregs (reg));
086134ec 2381 OUTS (outf, " = W[");
4b7f6baa
CM		 2382 OUTS (outf, pregs (ptr));
2383 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2384 }
2385 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2386 {
4b7f6baa 2387 OUTS (outf, dregs (reg));
086134ec 2388 OUTS (outf, " = W[");
4b7f6baa 2389 OUTS (outf, pregs (ptr));
086134ec 2390 OUTS (outf, "] (X)");
4b7f6baa
CM		 2391 }
2392 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2393 {
4b7f6baa 2394 OUTS (outf, dregs (reg));
086134ec 2395 OUTS (outf, " = B[");
4b7f6baa
CM		 2396 OUTS (outf, pregs (ptr));
2397 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2398 }
2399 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2400 {
4b7f6baa 2401 OUTS (outf, dregs (reg));
086134ec 2402 OUTS (outf, " = B[");
4b7f6baa 2403 OUTS (outf, pregs (ptr));
086134ec 2404 OUTS (outf, "] (X)");
4b7f6baa
CM		 2405 }
2406 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2407 {
4b7f6baa
CM		 2408 OUTS (outf, "[");
2409 OUTS (outf, pregs (ptr));
086134ec 2410 OUTS (outf, "++] = ");
4b7f6baa 2411 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2412 }
2413 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2414 {
4b7f6baa
CM		 2415 OUTS (outf, "[");
2416 OUTS (outf, pregs (ptr));
086134ec 2417 OUTS (outf, "++] = ");
4b7f6baa 2418 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2419 }
2420 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2421 {
4b7f6baa
CM		 2422 OUTS (outf, "W[");
2423 OUTS (outf, pregs (ptr));
086134ec 2424 OUTS (outf, "++] = ");
4b7f6baa 2425 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2426 }
2427 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2428 {
4b7f6baa
CM		 2429 OUTS (outf, "B[");
2430 OUTS (outf, pregs (ptr));
086134ec 2431 OUTS (outf, "++] = ");
4b7f6baa 2432 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2433 }
2434 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2435 {
4b7f6baa
CM		 2436 OUTS (outf, "[");
2437 OUTS (outf, pregs (ptr));
086134ec 2438 OUTS (outf, "--] = ");
4b7f6baa 2439 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2440 }
2441 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2442 {
4b7f6baa
CM		 2443 OUTS (outf, "[");
2444 OUTS (outf, pregs (ptr));
086134ec 2445 OUTS (outf, "--] = ");
4b7f6baa 2446 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2447 }
2448 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2449 {
4b7f6baa
CM		 2450 OUTS (outf, "W[");
2451 OUTS (outf, pregs (ptr));
086134ec 2452 OUTS (outf, "--] = ");
4b7f6baa 2453 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2454 }
2455 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2456 {
4b7f6baa
CM		 2457 OUTS (outf, "B[");
2458 OUTS (outf, pregs (ptr));
086134ec 2459 OUTS (outf, "--] = ");
4b7f6baa 2460 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2461 }
2462 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2463 {
4b7f6baa
CM		 2464 OUTS (outf, "[");
2465 OUTS (outf, pregs (ptr));
086134ec 2466 OUTS (outf, "] = ");
4b7f6baa 2467 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2468 }
2469 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2470 {
4b7f6baa
CM		 2471 OUTS (outf, "[");
2472 OUTS (outf, pregs (ptr));
086134ec 2473 OUTS (outf, "] = ");
4b7f6baa 2474 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2475 }
2476 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2477 {
4b7f6baa
CM		 2478 OUTS (outf, "W[");
2479 OUTS (outf, pregs (ptr));
086134ec 2480 OUTS (outf, "] = ");
4b7f6baa 2481 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2482 }
2483 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2484 {
4b7f6baa
CM		 2485 OUTS (outf, "B[");
2486 OUTS (outf, pregs (ptr));
086134ec 2487 OUTS (outf, "] = ");
4b7f6baa 2488 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2489 }
2490 else
b7d48530
NC		 2491 return 0;
2492
2493 return 2;
4b7f6baa
CM		 2494}
2495
2496static int
2497decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2498{
b7d48530
NC		 2499 /* LDSTiiFP
2500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2501 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2503 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2504 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2505 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2506
2507 if (W == 0)
2508 {
4b7f6baa 2509 OUTS (outf, dpregs (reg));
086134ec 2510 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2511 OUTS (outf, negimm5s4 (offset));
2512 OUTS (outf, "]");
4b7f6baa
CM		 2513 }
2514 else if (W == 1)
2515 {
086134ec 2516 OUTS (outf, "[FP ");
4b7f6baa 2517 OUTS (outf, negimm5s4 (offset));
086134ec 2518 OUTS (outf, "] = ");
4b7f6baa 2519 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2520 }
2521 else
b7d48530
NC		 2522 return 0;
2523
2524 return 2;
4b7f6baa
CM		 2525}
2526
2527static int
2528decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2529{
b7d48530
NC		 2530 /* LDSTii
2531 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2532 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2533 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2534 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2535 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2536 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2537 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2538 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2539
2540 if (W == 0 && op == 0)
2541 {
4b7f6baa 2542 OUTS (outf, dregs (reg));
086134ec 2543 OUTS (outf, " = [");
4b7f6baa 2544 OUTS (outf, pregs (ptr));
086134ec 2545 OUTS (outf, " + ");
4b7f6baa
CM		 2546 OUTS (outf, uimm4s4 (offset));
2547 OUTS (outf, "]");
4b7f6baa
CM		 2548 }
2549 else if (W == 0 && op == 1)
2550 {
4b7f6baa 2551 OUTS (outf, dregs (reg));
086134ec 2552 OUTS (outf, " = W[");
4b7f6baa 2553 OUTS (outf, pregs (ptr));
086134ec 2554 OUTS (outf, " + ");
4b7f6baa
CM		 2555 OUTS (outf, uimm4s2 (offset));
2556 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2557 }
2558 else if (W == 0 && op == 2)
2559 {
4b7f6baa 2560 OUTS (outf, dregs (reg));
086134ec 2561 OUTS (outf, " = W[");
4b7f6baa 2562 OUTS (outf, pregs (ptr));
086134ec 2563 OUTS (outf, " + ");
4b7f6baa 2564 OUTS (outf, uimm4s2 (offset));
086134ec 2565 OUTS (outf, "] (X)");
4b7f6baa
CM		 2566 }
2567 else if (W == 0 && op == 3)
2568 {
4b7f6baa 2569 OUTS (outf, pregs (reg));
086134ec 2570 OUTS (outf, " = [");
4b7f6baa 2571 OUTS (outf, pregs (ptr));
086134ec 2572 OUTS (outf, " + ");
4b7f6baa
CM		 2573 OUTS (outf, uimm4s4 (offset));
2574 OUTS (outf, "]");
4b7f6baa
CM		 2575 }
2576 else if (W == 1 && op == 0)
2577 {
4b7f6baa
CM		 2578 OUTS (outf, "[");
2579 OUTS (outf, pregs (ptr));
086134ec 2580 OUTS (outf, " + ");
4b7f6baa 2581 OUTS (outf, uimm4s4 (offset));
086134ec 2582 OUTS (outf, "] = ");
4b7f6baa 2583 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2584 }
2585 else if (W == 1 && op == 1)
2586 {
086134ec 2587 OUTS (outf, "W[");
4b7f6baa 2588 OUTS (outf, pregs (ptr));
086134ec 2589 OUTS (outf, " + ");
4b7f6baa 2590 OUTS (outf, uimm4s2 (offset));
086134ec 2591 OUTS (outf, "] = ");
4b7f6baa 2592 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2593 }
2594 else if (W == 1 && op == 3)
2595 {
4b7f6baa
CM		 2596 OUTS (outf, "[");
2597 OUTS (outf, pregs (ptr));
086134ec 2598 OUTS (outf, " + ");
4b7f6baa 2599 OUTS (outf, uimm4s4 (offset));
086134ec 2600 OUTS (outf, "] = ");
4b7f6baa 2601 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2602 }
2603 else
b7d48530
NC		 2604 return 0;
2605
2606 return 2;
4b7f6baa
CM		 2607}
2608
2609static int
2610decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2611{
b7d48530
NC		 2612 /* LoopSetup
2613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2614 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2615 |.reg...........| - | - |.eoffset...............................|
2616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2617 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2618 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2619 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2620 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2621 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2622
219b747a
MF		 2623 if (parallel)
2624 return 0;
2625
4b7f6baa
CM		 2626 if (rop == 0)
2627 {
4b7f6baa 2628 OUTS (outf, "LSETUP");
086134ec 2629 OUTS (outf, "(0x");
4b7f6baa 2630 OUTS (outf, pcrel4 (soffset));
086134ec 2631 OUTS (outf, ", 0x");
4b7f6baa 2632 OUTS (outf, lppcrel10 (eoffset));
086134ec 2633 OUTS (outf, ") ");
4b7f6baa 2634 OUTS (outf, counters (c));
4b7f6baa
CM		 2635 }
2636 else if (rop == 1)
2637 {
4b7f6baa 2638 OUTS (outf, "LSETUP");
086134ec 2639 OUTS (outf, "(0x");
4b7f6baa 2640 OUTS (outf, pcrel4 (soffset));
086134ec 2641 OUTS (outf, ", 0x");
4b7f6baa 2642 OUTS (outf, lppcrel10 (eoffset));
086134ec 2643 OUTS (outf, ") ");
4b7f6baa 2644 OUTS (outf, counters (c));
086134ec 2645 OUTS (outf, " = ");
4b7f6baa 2646 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2647 }
2648 else if (rop == 3)
2649 {
4b7f6baa 2650 OUTS (outf, "LSETUP");
086134ec 2651 OUTS (outf, "(0x");
4b7f6baa 2652 OUTS (outf, pcrel4 (soffset));
086134ec 2653 OUTS (outf, ", 0x");
4b7f6baa 2654 OUTS (outf, lppcrel10 (eoffset));
086134ec 2655 OUTS (outf, ") ");
4b7f6baa 2656 OUTS (outf, counters (c));
086134ec 2657 OUTS (outf, " = ");
4b7f6baa 2658 OUTS (outf, pregs (reg));
086134ec 2659 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2660 }
2661 else
b7d48530
NC		 2662 return 0;
2663
2664 return 4;
4b7f6baa
CM		 2665}
2666
2667static int
2668decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2669{
b7d48530
NC		 2670 /* LDIMMhalf
2671 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2672 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2673 |.hword.........................................................|
2674 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2675 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2676 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2677 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2678 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2679 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2680 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2681
b21c9cb4
BS		 2682 bu32 *pval = get_allreg (grp, reg);
2683
219b747a
MF		 2684 if (parallel)
2685 return 0;
2686
b21c9cb4
BS		 2687 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2688 to combine them, so it prints out the right values.
2689 Here we keep track of the registers. */
2690 if (H == 0 && S == 1 && Z == 0)
2691 {
2692 /* regs = imm16 (x) */
2693 *pval = imm16_val (hword);
086134ec
BS		 2694 if (hword & 0x8000)
2695 *pval |= 0xFFFF0000;
2696 else
2697 *pval &= 0xFFFF;
b21c9cb4
BS		 2698 }
2699 else if (H == 0 && S == 0 && Z == 1)
2700 {
2701 /* regs = luimm16 (Z) */
2702 *pval = luimm16_val (hword);
086134ec 2703 *pval &= 0xFFFF;
b21c9cb4
BS		 2704 }
2705 else if (H == 0 && S == 0 && Z == 0)
2706 {
2707 /* regs_lo = luimm16 */
2708 *pval &= 0xFFFF0000;
2709 *pval |= luimm16_val (hword);
2710 }
2711 else if (H == 1 && S == 0 && Z == 0)
2712 {
2713 /* regs_hi = huimm16 */
2714 *pval &= 0xFFFF;
2715 *pval |= luimm16_val (hword) << 16;
2716 }
2717
2718 /* Here we do the disassembly */
4b7f6baa
CM		 2719 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2720 {
4b7f6baa 2721 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2722 OUTS (outf, " = ");
2723 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2724 }
2725 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2726 {
4b7f6baa 2727 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2728 OUTS (outf, " = ");
2729 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2730 }
2731 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2732 {
4b7f6baa 2733 OUTS (outf, dregs (reg));
086134ec 2734 OUTS (outf, " = ");
4b7f6baa
CM		 2735 OUTS (outf, imm16 (hword));
2736 OUTS (outf, " (X)");
4b7f6baa
CM		 2737 }
2738 else if (H == 0 && S == 1 && Z == 0)
086134ec 2739 {
4b7f6baa 2740 OUTS (outf, regs (reg, grp));
086134ec 2741 OUTS (outf, " = ");
4b7f6baa
CM		 2742 OUTS (outf, imm16 (hword));
2743 OUTS (outf, " (X)");
4b7f6baa
CM		 2744 }
2745 else if (H == 0 && S == 0 && Z == 1)
2746 {
4b7f6baa 2747 OUTS (outf, regs (reg, grp));
086134ec
BS		 2748 OUTS (outf, " = ");
2749 OUTS (outf, uimm16 (hword));
2750 OUTS (outf, " (Z)");
4b7f6baa
CM		 2751 }
2752 else if (H == 0 && S == 0 && Z == 0)
2753 {
4b7f6baa 2754 OUTS (outf, regs_lo (reg, grp));
086134ec 2755 OUTS (outf, " = ");
b21c9cb4 2756 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2757 }
2758 else if (H == 1 && S == 0 && Z == 0)
2759 {
4b7f6baa 2760 OUTS (outf, regs_hi (reg, grp));
086134ec 2761 OUTS (outf, " = ");
b21c9cb4 2762 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2763 }
2764 else
b7d48530
NC		 2765 return 0;
2766
b21c9cb4 2767 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2768 if (S == 0 && Z == 0)
b21c9cb4 2769 {
086134ec
BS		 2770 OUTS (outf, ";\t\t/* (");
2771 OUTS (outf, imm16d (hword));
2772 OUTS (outf, ")\t");
2773
b21c9cb4 2774 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2775 if (*pval < 0xFFC00000 && grp == 1)
2776 {
2777 OUTS (outf, regs (reg, grp));
2778 OUTS (outf, "=0x");
2779 OUTS (outf, huimm32e (*pval));
2780 }
b21c9cb4 2781 else
086134ec
BS		 2782 {
2783 OUTS (outf, regs (reg, grp));
2784 OUTS (outf, "=0x");
2785 OUTS (outf, huimm32e (*pval));
2786 OUTS (outf, "(");
2787 OUTS (outf, imm32 (*pval));
2788 OUTS (outf, ")");
2789 }
b21c9cb4
BS		 2790
2791 OUTS (outf, " */");
086134ec
BS		 2792 comment = 1;
2793 }
2794 if (S == 1 || Z == 1)
2795 {
2796 OUTS (outf, ";\t\t/*\t\t");
2797 OUTS (outf, regs (reg, grp));
2798 OUTS (outf, "=0x");
2799 OUTS (outf, huimm32e (*pval));
2800 OUTS (outf, "(");
2801 OUTS (outf, imm32 (*pval));
2802 OUTS (outf, ") */");
2803 comment = 1;
b21c9cb4 2804 }
b7d48530 2805 return 4;
4b7f6baa
CM		 2806}
2807
2808static int
2809decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2810{
b7d48530
NC		 2811 /* CALLa
2812 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2813 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2814 |.lsw...........................................................|
2815 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2816 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2817 int lsw = ((iw1 >> 0) & 0xffff);
2818 int msw = ((iw0 >> 0) & 0xff);
2819
219b747a
MF		 2820 if (parallel)
2821 return 0;
2822
4b7f6baa 2823 if (S == 1)
086134ec 2824 OUTS (outf, "CALL 0x");
4b7f6baa 2825 else if (S == 0)
086134ec 2826 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2827 else
b7d48530
NC		 2828 return 0;
2829
2830 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2831 return 4;
4b7f6baa
CM		 2832}
2833
2834static int
2835decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2836{
b7d48530
NC		 2837 /* LDSTidxI
2838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2839 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2840 |.offset........................................................|
2841 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2842 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2843 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2844 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2845 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2846 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2847 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2848
2849 if (W == 0 && sz == 0 && Z == 0)
2850 {
4b7f6baa 2851 OUTS (outf, dregs (reg));
086134ec 2852 OUTS (outf, " = [");
4b7f6baa 2853 OUTS (outf, pregs (ptr));
086134ec 2854 OUTS (outf, " + ");
4b7f6baa
CM		 2855 OUTS (outf, imm16s4 (offset));
2856 OUTS (outf, "]");
4b7f6baa
CM		 2857 }
2858 else if (W == 0 && sz == 0 && Z == 1)
2859 {
4b7f6baa 2860 OUTS (outf, pregs (reg));
086134ec 2861 OUTS (outf, " = [");
4b7f6baa 2862 OUTS (outf, pregs (ptr));
086134ec 2863 OUTS (outf, " + ");
4b7f6baa
CM		 2864 OUTS (outf, imm16s4 (offset));
2865 OUTS (outf, "]");
4b7f6baa
CM		 2866 }
2867 else if (W == 0 && sz == 1 && Z == 0)
2868 {
4b7f6baa 2869 OUTS (outf, dregs (reg));
086134ec 2870 OUTS (outf, " = W[");
4b7f6baa 2871 OUTS (outf, pregs (ptr));
086134ec 2872 OUTS (outf, " + ");
4b7f6baa
CM		 2873 OUTS (outf, imm16s2 (offset));
2874 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2875 }
2876 else if (W == 0 && sz == 1 && Z == 1)
2877 {
4b7f6baa 2878 OUTS (outf, dregs (reg));
086134ec 2879 OUTS (outf, " = W[");
4b7f6baa 2880 OUTS (outf, pregs (ptr));
086134ec 2881 OUTS (outf, " + ");
4b7f6baa 2882 OUTS (outf, imm16s2 (offset));
086134ec 2883 OUTS (outf, "] (X)");
4b7f6baa
CM		 2884 }
2885 else if (W == 0 && sz == 2 && Z == 0)
2886 {
4b7f6baa 2887 OUTS (outf, dregs (reg));
086134ec 2888 OUTS (outf, " = B[");
4b7f6baa 2889 OUTS (outf, pregs (ptr));
086134ec 2890 OUTS (outf, " + ");
4b7f6baa
CM		 2891 OUTS (outf, imm16 (offset));
2892 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2893 }
2894 else if (W == 0 && sz == 2 && Z == 1)
2895 {
4b7f6baa 2896 OUTS (outf, dregs (reg));
086134ec 2897 OUTS (outf, " = B[");
4b7f6baa 2898 OUTS (outf, pregs (ptr));
086134ec 2899 OUTS (outf, " + ");
4b7f6baa 2900 OUTS (outf, imm16 (offset));
086134ec 2901 OUTS (outf, "] (X)");
4b7f6baa
CM		 2902 }
2903 else if (W == 1 && sz == 0 && Z == 0)
2904 {
4b7f6baa
CM		 2905 OUTS (outf, "[");
2906 OUTS (outf, pregs (ptr));
086134ec 2907 OUTS (outf, " + ");
4b7f6baa 2908 OUTS (outf, imm16s4 (offset));
086134ec 2909 OUTS (outf, "] = ");
4b7f6baa 2910 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2911 }
2912 else if (W == 1 && sz == 0 && Z == 1)
2913 {
4b7f6baa
CM		 2914 OUTS (outf, "[");
2915 OUTS (outf, pregs (ptr));
086134ec 2916 OUTS (outf, " + ");
4b7f6baa 2917 OUTS (outf, imm16s4 (offset));
086134ec 2918 OUTS (outf, "] = ");
4b7f6baa 2919 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2920 }
2921 else if (W == 1 && sz == 1 && Z == 0)
2922 {
4b7f6baa
CM		 2923 OUTS (outf, "W[");
2924 OUTS (outf, pregs (ptr));
086134ec 2925 OUTS (outf, " + ");
4b7f6baa 2926 OUTS (outf, imm16s2 (offset));
086134ec 2927 OUTS (outf, "] = ");
4b7f6baa 2928 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2929 }
2930 else if (W == 1 && sz == 2 && Z == 0)
2931 {
4b7f6baa
CM		 2932 OUTS (outf, "B[");
2933 OUTS (outf, pregs (ptr));
086134ec 2934 OUTS (outf, " + ");
4b7f6baa 2935 OUTS (outf, imm16 (offset));
086134ec 2936 OUTS (outf, "] = ");
4b7f6baa 2937 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2938 }
2939 else
b7d48530
NC		 2940 return 0;
2941
2942 return 4;
4b7f6baa
CM		 2943}
2944
2945static int
2946decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2947{
b7d48530
NC		 2948 /* linkage
2949 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2950 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2951 |.framesize.....................................................|
2952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2953 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2954 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2955
219b747a
MF		 2956 if (parallel)
2957 return 0;
2958
4b7f6baa
CM		 2959 if (R == 0)
2960 {
4b7f6baa
CM		 2961 OUTS (outf, "LINK ");
2962 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2963 OUTS (outf, ";\t\t/* (");
2964 OUTS (outf, uimm16s4d (framesize));
2965 OUTS (outf, ") */");
2966 comment = 1;
4b7f6baa
CM		 2967 }
2968 else if (R == 1)
b7d48530 2969 OUTS (outf, "UNLINK");
4b7f6baa 2970 else
b7d48530
NC		 2971 return 0;
2972
2973 return 4;
4b7f6baa
CM		 2974}
2975
2976static int
2977decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2978{
b7d48530
NC		 2979 /* dsp32mac
2980 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2981 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2982 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2983 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2984 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2985 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2986 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2987 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2988 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2989 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2990 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2991 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 2992 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2993 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2994 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2995 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2996 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2997 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 2998
2999 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3000 return 0;
3001
3002 if (op1 == 3 && MM)
3003 return 0;
3004
3005 if ((w1 || w0) && mmod == M_W32)
3006 return 0;
3007
ee171c8f 3008 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 3009 return 0;
3010
3011 if (w1 == 1 || op1 != 3)
3012 {
3013 if (w1)
3014 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3015
3016 if (op1 == 3)
3017 OUTS (outf, " = A1");
3018 else
3019 {
3020 if (w1)
3021 OUTS (outf, " = (");
3022 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3023 if (w1)
3024 OUTS (outf, ")");
3025 }
3026
3027 if (w0 == 1 || op0 != 3)
3028 {
3029 if (MM)
3030 OUTS (outf, " (M)");
3031 MM = 0;
3032 OUTS (outf, ", ");
3033 }
3034 }
3035
3036 if (w0 == 1 || op0 != 3)
3037 {
3038 if (w0)
3039 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3040
3041 if (op0 == 3)
3042 OUTS (outf, " = A0");
3043 else
3044 {
3045 if (w0)
3046 OUTS (outf, " = (");
3047 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3048 if (w0)
3049 OUTS (outf, ")");
3050 }
3051 }
3052
3053 decode_optmode (mmod, MM, outf);
3054
3055 return 4;
3056}
3057
3058static int
3059decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3060{
b7d48530
NC		 3061 /* dsp32mult
3062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3063 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3064 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3065 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3066 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3067 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3068 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3069 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3070 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3071 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3072 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3073 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3074 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3075 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3076 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3077 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3078
3079 if (w1 == 0 && w0 == 0)
3080 return 0;
b7d48530 3081
4b7f6baa
CM		 3082 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3083 return 0;
b7d48530 3084
4b7f6baa
CM		 3085 if (w1)
3086 {
3087 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3088 OUTS (outf, " = ");
3089 decode_multfunc (h01, h11, src0, src1, outf);
3090
3091 if (w0)
3092 {
3093 if (MM)
3094 OUTS (outf, " (M)");
3095 MM = 0;
3096 OUTS (outf, ", ");
3097 }
3098 }
3099
3100 if (w0)
3101 {
3102 OUTS (outf, dregs (dst));
3103 OUTS (outf, " = ");
3104 decode_multfunc (h00, h10, src0, src1, outf);
3105 }
3106
3107 decode_optmode (mmod, MM, outf);
3108 return 4;
3109}
3110
3111static int
3112decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3113{
b7d48530
NC		 3114 /* dsp32alu
3115 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3116 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3117 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3118 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3119 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3120 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3121 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3122 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3123 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3124 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3125 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3126 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3127 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3128
3129 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3130 {
086134ec 3131 OUTS (outf, "A0.L = ");
4b7f6baa 3132 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3133 }
3134 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3135 {
086134ec 3136 OUTS (outf, "A1.H = ");
4b7f6baa 3137 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3138 }
3139 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3140 {
086134ec 3141 OUTS (outf, "A1.L = ");
4b7f6baa 3142 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3143 }
3144 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3145 {
086134ec 3146 OUTS (outf, "A0.H = ");
4b7f6baa 3147 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3148 }
3149 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3150 {
4b7f6baa 3151 OUTS (outf, dregs_hi (dst0));
086134ec 3152 OUTS (outf, " = ");
4b7f6baa 3153 OUTS (outf, dregs (src0));
086134ec 3154 OUTS (outf, " - ");
4b7f6baa 3155 OUTS (outf, dregs (src1));
086134ec 3156 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3157 }
3158 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3159 {
4b7f6baa 3160 OUTS (outf, dregs_hi (dst0));
086134ec 3161 OUTS (outf, " = ");
4b7f6baa 3162 OUTS (outf, dregs (src0));
086134ec 3163 OUTS (outf, " + ");
4b7f6baa 3164 OUTS (outf, dregs (src1));
086134ec 3165 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3166 }
3167 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3168 {
4b7f6baa 3169 OUTS (outf, dregs_lo (dst0));
086134ec 3170 OUTS (outf, " = ");
4b7f6baa 3171 OUTS (outf, dregs (src0));
086134ec 3172 OUTS (outf, " - ");
4b7f6baa 3173 OUTS (outf, dregs (src1));
086134ec 3174 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3175 }
3176 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3177 {
4b7f6baa 3178 OUTS (outf, dregs_lo (dst0));
086134ec 3179 OUTS (outf, " = ");
4b7f6baa 3180 OUTS (outf, dregs (src0));
086134ec 3181 OUTS (outf, " + ");
4b7f6baa 3182 OUTS (outf, dregs (src1));
086134ec 3183 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3184 }
3185 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3186 {
4b7f6baa 3187 OUTS (outf, dregs_lo (dst0));
086134ec 3188 OUTS (outf, " = ");
4b7f6baa 3189 OUTS (outf, dregs (src0));
086134ec 3190 OUTS (outf, " - ");
4b7f6baa 3191 OUTS (outf, dregs (src1));
086134ec 3192 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3193 }
3194 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3195 {
4b7f6baa 3196 OUTS (outf, dregs_hi (dst0));
086134ec 3197 OUTS (outf, " = ");
4b7f6baa 3198 OUTS (outf, dregs (src0));
086134ec 3199 OUTS (outf, " + ");
4b7f6baa 3200 OUTS (outf, dregs (src1));
086134ec 3201 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3202 }
3203 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3204 {
4b7f6baa 3205 OUTS (outf, dregs_lo (dst0));
086134ec 3206 OUTS (outf, " = ");
4b7f6baa 3207 OUTS (outf, dregs (src0));
086134ec 3208 OUTS (outf, " + ");
4b7f6baa 3209 OUTS (outf, dregs (src1));
086134ec 3210 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3211 }
3212 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3213 {
4b7f6baa 3214 OUTS (outf, dregs_hi (dst0));
086134ec 3215 OUTS (outf, " = ");
4b7f6baa 3216 OUTS (outf, dregs (src0));
086134ec 3217 OUTS (outf, " - ");
4b7f6baa 3218 OUTS (outf, dregs (src1));
086134ec 3219 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3220 }
3221 else if (HL == 1 && aop == 0 && aopcde == 2)
3222 {
4b7f6baa 3223 OUTS (outf, dregs_hi (dst0));
086134ec 3224 OUTS (outf, " = ");
4b7f6baa 3225 OUTS (outf, dregs_lo (src0));
086134ec 3226 OUTS (outf, " + ");
4b7f6baa 3227 OUTS (outf, dregs_lo (src1));
4b7f6baa 3228 amod1 (s, x, outf);
4b7f6baa
CM		 3229 }
3230 else if (HL == 1 && aop == 1 && aopcde == 2)
3231 {
4b7f6baa 3232 OUTS (outf, dregs_hi (dst0));
086134ec 3233 OUTS (outf, " = ");
4b7f6baa 3234 OUTS (outf, dregs_lo (src0));
086134ec 3235 OUTS (outf, " + ");
4b7f6baa 3236 OUTS (outf, dregs_hi (src1));
4b7f6baa 3237 amod1 (s, x, outf);
4b7f6baa
CM		 3238 }
3239 else if (HL == 1 && aop == 2 && aopcde == 2)
3240 {
4b7f6baa 3241 OUTS (outf, dregs_hi (dst0));
086134ec 3242 OUTS (outf, " = ");
4b7f6baa 3243 OUTS (outf, dregs_hi (src0));
086134ec 3244 OUTS (outf, " + ");
4b7f6baa 3245 OUTS (outf, dregs_lo (src1));
4b7f6baa 3246 amod1 (s, x, outf);
4b7f6baa
CM		 3247 }
3248 else if (HL == 1 && aop == 3 && aopcde == 2)
3249 {
4b7f6baa 3250 OUTS (outf, dregs_hi (dst0));
086134ec 3251 OUTS (outf, " = ");
4b7f6baa 3252 OUTS (outf, dregs_hi (src0));
086134ec 3253 OUTS (outf, " + ");
4b7f6baa 3254 OUTS (outf, dregs_hi (src1));
4b7f6baa 3255 amod1 (s, x, outf);
4b7f6baa
CM		 3256 }
3257 else if (HL == 0 && aop == 0 && aopcde == 3)
3258 {
4b7f6baa 3259 OUTS (outf, dregs_lo (dst0));
086134ec 3260 OUTS (outf, " = ");
4b7f6baa 3261 OUTS (outf, dregs_lo (src0));
086134ec 3262 OUTS (outf, " - ");
4b7f6baa 3263 OUTS (outf, dregs_lo (src1));
4b7f6baa 3264 amod1 (s, x, outf);
4b7f6baa
CM		 3265 }
3266 else if (HL == 0 && aop == 1 && aopcde == 3)
3267 {
4b7f6baa 3268 OUTS (outf, dregs_lo (dst0));
086134ec 3269 OUTS (outf, " = ");
4b7f6baa 3270 OUTS (outf, dregs_lo (src0));
086134ec 3271 OUTS (outf, " - ");
4b7f6baa 3272 OUTS (outf, dregs_hi (src1));
4b7f6baa 3273 amod1 (s, x, outf);
4b7f6baa
CM		 3274 }
3275 else if (HL == 0 && aop == 3 && aopcde == 2)
3276 {
4b7f6baa 3277 OUTS (outf, dregs_lo (dst0));
086134ec 3278 OUTS (outf, " = ");
4b7f6baa 3279 OUTS (outf, dregs_hi (src0));
086134ec 3280 OUTS (outf, " + ");
4b7f6baa 3281 OUTS (outf, dregs_hi (src1));
4b7f6baa 3282 amod1 (s, x, outf);
4b7f6baa
CM		 3283 }
3284 else if (HL == 1 && aop == 0 && aopcde == 3)
3285 {
4b7f6baa 3286 OUTS (outf, dregs_hi (dst0));
086134ec 3287 OUTS (outf, " = ");
4b7f6baa 3288 OUTS (outf, dregs_lo (src0));
086134ec 3289 OUTS (outf, " - ");
4b7f6baa 3290 OUTS (outf, dregs_lo (src1));
4b7f6baa 3291 amod1 (s, x, outf);
4b7f6baa
CM		 3292 }
3293 else if (HL == 1 && aop == 1 && aopcde == 3)
3294 {
4b7f6baa 3295 OUTS (outf, dregs_hi (dst0));
086134ec 3296 OUTS (outf, " = ");
4b7f6baa 3297 OUTS (outf, dregs_lo (src0));
086134ec 3298 OUTS (outf, " - ");
4b7f6baa 3299 OUTS (outf, dregs_hi (src1));
4b7f6baa 3300 amod1 (s, x, outf);
4b7f6baa
CM		 3301 }
3302 else if (HL == 1 && aop == 2 && aopcde == 3)
3303 {
4b7f6baa 3304 OUTS (outf, dregs_hi (dst0));
086134ec 3305 OUTS (outf, " = ");
4b7f6baa 3306 OUTS (outf, dregs_hi (src0));
086134ec 3307 OUTS (outf, " - ");
4b7f6baa 3308 OUTS (outf, dregs_lo (src1));
4b7f6baa 3309 amod1 (s, x, outf);
4b7f6baa
CM		 3310 }
3311 else if (HL == 1 && aop == 3 && aopcde == 3)
3312 {
4b7f6baa 3313 OUTS (outf, dregs_hi (dst0));
086134ec 3314 OUTS (outf, " = ");
4b7f6baa 3315 OUTS (outf, dregs_hi (src0));
086134ec 3316 OUTS (outf, " - ");
4b7f6baa 3317 OUTS (outf, dregs_hi (src1));
4b7f6baa 3318 amod1 (s, x, outf);
4b7f6baa
CM		 3319 }
3320 else if (HL == 0 && aop == 2 && aopcde == 2)
3321 {
4b7f6baa 3322 OUTS (outf, dregs_lo (dst0));
086134ec 3323 OUTS (outf, " = ");
4b7f6baa 3324 OUTS (outf, dregs_hi (src0));
086134ec 3325 OUTS (outf, " + ");
4b7f6baa 3326 OUTS (outf, dregs_lo (src1));
4b7f6baa 3327 amod1 (s, x, outf);
4b7f6baa
CM		 3328 }
3329 else if (HL == 0 && aop == 1 && aopcde == 2)
3330 {
4b7f6baa 3331 OUTS (outf, dregs_lo (dst0));
086134ec 3332 OUTS (outf, " = ");
4b7f6baa 3333 OUTS (outf, dregs_lo (src0));
086134ec 3334 OUTS (outf, " + ");
4b7f6baa 3335 OUTS (outf, dregs_hi (src1));
4b7f6baa 3336 amod1 (s, x, outf);
4b7f6baa
CM		 3337 }
3338 else if (HL == 0 && aop == 2 && aopcde == 3)
3339 {
4b7f6baa 3340 OUTS (outf, dregs_lo (dst0));
086134ec 3341 OUTS (outf, " = ");
4b7f6baa 3342 OUTS (outf, dregs_hi (src0));
086134ec 3343 OUTS (outf, " - ");
4b7f6baa 3344 OUTS (outf, dregs_lo (src1));
4b7f6baa 3345 amod1 (s, x, outf);
4b7f6baa
CM		 3346 }
3347 else if (HL == 0 && aop == 3 && aopcde == 3)
3348 {
4b7f6baa 3349 OUTS (outf, dregs_lo (dst0));
086134ec 3350 OUTS (outf, " = ");
4b7f6baa 3351 OUTS (outf, dregs_hi (src0));
086134ec 3352 OUTS (outf, " - ");
4b7f6baa 3353 OUTS (outf, dregs_hi (src1));
4b7f6baa 3354 amod1 (s, x, outf);
4b7f6baa
CM		 3355 }
3356 else if (HL == 0 && aop == 0 && aopcde == 2)
3357 {
4b7f6baa 3358 OUTS (outf, dregs_lo (dst0));
086134ec 3359 OUTS (outf, " = ");
4b7f6baa 3360 OUTS (outf, dregs_lo (src0));
086134ec 3361 OUTS (outf, " + ");
4b7f6baa 3362 OUTS (outf, dregs_lo (src1));
4b7f6baa 3363 amod1 (s, x, outf);
4b7f6baa
CM		 3364 }
3365 else if (aop == 0 && aopcde == 9 && s == 1)
3366 {
086134ec 3367 OUTS (outf, "A0 = ");
4b7f6baa 3368 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3369 }
3370 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3371 OUTS (outf, "A0 -= A1");
b7d48530 3372
4b7f6baa 3373 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3374 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3375
4b7f6baa
CM		 3376 else if (aop == 1 && aopcde == 22 && HL == 1)
3377 {
4b7f6baa 3378 OUTS (outf, dregs (dst0));
086134ec 3379 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3380 OUTS (outf, dregs (src0 + 1));
3381 OUTS (outf, ":");
086134ec
BS		 3382 OUTS (outf, imm5d (src0));
3383 OUTS (outf, ", ");
4b7f6baa
CM		 3384 OUTS (outf, dregs (src1 + 1));
3385 OUTS (outf, ":");
086134ec
BS		 3386 OUTS (outf, imm5d (src1));
3387 OUTS (outf, ") (TH");
4b7f6baa
CM		 3388 if (s == 1)
3389 OUTS (outf, ", R)");
3390 else
3391 OUTS (outf, ")");
4b7f6baa
CM		 3392 }
3393 else if (aop == 1 && aopcde == 22 && HL == 0)
3394 {
4b7f6baa 3395 OUTS (outf, dregs (dst0));
086134ec 3396 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3397 OUTS (outf, dregs (src0 + 1));
3398 OUTS (outf, ":");
086134ec
BS		 3399 OUTS (outf, imm5d (src0));
3400 OUTS (outf, ", ");
4b7f6baa
CM		 3401 OUTS (outf, dregs (src1 + 1));
3402 OUTS (outf, ":");
086134ec
BS		 3403 OUTS (outf, imm5d (src1));
3404 OUTS (outf, ") (TL");
4b7f6baa
CM		 3405 if (s == 1)
3406 OUTS (outf, ", R)");
3407 else
3408 OUTS (outf, ")");
4b7f6baa
CM		 3409 }
3410 else if (aop == 0 && aopcde == 22 && HL == 1)
3411 {
4b7f6baa 3412 OUTS (outf, dregs (dst0));
086134ec 3413 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3414 OUTS (outf, dregs (src0 + 1));
3415 OUTS (outf, ":");
086134ec
BS		 3416 OUTS (outf, imm5d (src0));
3417 OUTS (outf, ", ");
4b7f6baa
CM		 3418 OUTS (outf, dregs (src1 + 1));
3419 OUTS (outf, ":");
086134ec
BS		 3420 OUTS (outf, imm5d (src1));
3421 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3422 if (s == 1)
3423 OUTS (outf, ", R)");
3424 else
3425 OUTS (outf, ")");
4b7f6baa
CM		 3426 }
3427 else if (aop == 0 && aopcde == 22 && HL == 0)
3428 {
4b7f6baa 3429 OUTS (outf, dregs (dst0));
086134ec 3430 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3431 OUTS (outf, dregs (src0 + 1));
3432 OUTS (outf, ":");
086134ec
BS		 3433 OUTS (outf, imm5d (src0));
3434 OUTS (outf, ", ");
4b7f6baa
CM		 3435 OUTS (outf, dregs (src1 + 1));
3436 OUTS (outf, ":");
086134ec
BS		 3437 OUTS (outf, imm5d (src1));
3438 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3439 if (s == 1)
3440 OUTS (outf, ", R)");
3441 else
3442 OUTS (outf, ")");
4b7f6baa
CM		 3443 }
3444 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3445 OUTS (outf, "A0 = 0");
b7d48530 3446
4b7f6baa 3447 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3448 OUTS (outf, "A0 = A0 (S)");
b7d48530 3449
4b7f6baa 3450 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3451 OUTS (outf, "A1 = 0");
b7d48530 3452
4b7f6baa 3453 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3454 OUTS (outf, "A1 = A1 (S)");
b7d48530 3455
4b7f6baa 3456 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3457 OUTS (outf, "A1 = A0 = 0");
b7d48530 3458
4b7f6baa 3459 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3460 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3461
4b7f6baa 3462 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3463 OUTS (outf, "A0 = A1");
b7d48530 3464
4b7f6baa 3465 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3466 OUTS (outf, "A1 = A0");
b7d48530 3467
4b7f6baa
CM		 3468 else if (aop == 1 && aopcde == 9 && s == 0)
3469 {
086134ec 3470 OUTS (outf, "A0.X = ");
4b7f6baa 3471 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3472 }
3473 else if (aop == 1 && HL == 0 && aopcde == 11)
3474 {
4b7f6baa 3475 OUTS (outf, dregs_lo (dst0));
086134ec 3476 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3477 }
3478 else if (aop == 3 && HL == 0 && aopcde == 16)
086134ec 3479 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
b7d48530 3480
4b7f6baa
CM		 3481 else if (aop == 0 && aopcde == 23 && HL == 1)
3482 {
4b7f6baa 3483 OUTS (outf, dregs (dst0));
086134ec 3484 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3485 OUTS (outf, dregs (src0 + 1));
3486 OUTS (outf, ":");
086134ec
BS		 3487 OUTS (outf, imm5d (src0));
3488 OUTS (outf, ", ");
4b7f6baa
CM		 3489 OUTS (outf, dregs (src1 + 1));
3490 OUTS (outf, ":");
086134ec
BS		 3491 OUTS (outf, imm5d (src1));
3492 OUTS (outf, ") (HI");
4b7f6baa
CM		 3493 if (s == 1)
3494 OUTS (outf, ", R)");
3495 else
3496 OUTS (outf, ")");
4b7f6baa
CM		 3497 }
3498 else if (aop == 3 && aopcde == 9 && s == 0)
3499 {
086134ec 3500 OUTS (outf, "A1.X = ");
4b7f6baa 3501 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3502 }
3503 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3504 OUTS (outf, "A1 = ABS A1");
b7d48530 3505
4b7f6baa 3506 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3507 OUTS (outf, "A1 = ABS A0");
b7d48530 3508
4b7f6baa
CM		 3509 else if (aop == 2 && aopcde == 9 && s == 1)
3510 {
086134ec 3511 OUTS (outf, "A1 = ");
4b7f6baa 3512 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3513 }
3514 else if (HL == 0 && aop == 3 && aopcde == 12)
3515 {
4b7f6baa 3516 OUTS (outf, dregs_lo (dst0));
086134ec 3517 OUTS (outf, " = ");
4b7f6baa 3518 OUTS (outf, dregs (src0));
086134ec 3519 OUTS (outf, " (RND)");
4b7f6baa
CM		 3520 }
3521 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3522 OUTS (outf, "A0 = ABS A1");
b7d48530 3523
4b7f6baa 3524 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3525 OUTS (outf, "A0 = ABS A0");
b7d48530 3526
4b7f6baa
CM		 3527 else if (aop == 3 && HL == 0 && aopcde == 15)
3528 {
4b7f6baa 3529 OUTS (outf, dregs (dst0));
086134ec 3530 OUTS (outf, " = -");
4b7f6baa 3531 OUTS (outf, dregs (src0));
086134ec 3532 OUTS (outf, " (V)");
4b7f6baa
CM		 3533 }
3534 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3535 {
4b7f6baa 3536 OUTS (outf, dregs (dst0));
086134ec 3537 OUTS (outf, " = -");
4b7f6baa 3538 OUTS (outf, dregs (src0));
086134ec 3539 OUTS (outf, " (S)");
4b7f6baa
CM		 3540 }
3541 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3542 {
4b7f6baa 3543 OUTS (outf, dregs (dst0));
086134ec 3544 OUTS (outf, " = -");
4b7f6baa 3545 OUTS (outf, dregs (src0));
086134ec 3546 OUTS (outf, " (NS)");
4b7f6baa
CM		 3547 }
3548 else if (aop == 1 && HL == 1 && aopcde == 11)
3549 {
4b7f6baa 3550 OUTS (outf, dregs_hi (dst0));
086134ec 3551 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3552 }
3553 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3554 OUTS (outf, "A0 += A1");
b7d48530 3555
4b7f6baa 3556 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3557 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3558
4b7f6baa 3559 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3560 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3561
4b7f6baa
CM		 3562 else if (HL == 1 && aop == 3 && aopcde == 12)
3563 {
4b7f6baa 3564 OUTS (outf, dregs_hi (dst0));
086134ec 3565 OUTS (outf, " = ");
4b7f6baa 3566 OUTS (outf, dregs (src0));
086134ec 3567 OUTS (outf, " (RND)");
4b7f6baa
CM		 3568 }
3569 else if (aop == 0 && aopcde == 23 && HL == 0)
3570 {
4b7f6baa 3571 OUTS (outf, dregs (dst0));
086134ec 3572 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3573 OUTS (outf, dregs (src0 + 1));
3574 OUTS (outf, ":");
086134ec
BS		 3575 OUTS (outf, imm5d (src0));
3576 OUTS (outf, ", ");
4b7f6baa
CM		 3577 OUTS (outf, dregs (src1 + 1));
3578 OUTS (outf, ":");
086134ec
BS		 3579 OUTS (outf, imm5d (src1));
3580 OUTS (outf, ") (LO");
4b7f6baa
CM		 3581 if (s == 1)
3582 OUTS (outf, ", R)");
3583 else
3584 OUTS (outf, ")");
4b7f6baa
CM		 3585 }
3586 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3587 OUTS (outf, "A0 = -A0");
b7d48530 3588
4b7f6baa 3589 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3590 OUTS (outf, "A0 = -A1");
b7d48530 3591
4b7f6baa 3592 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3593 OUTS (outf, "A1 = -A0");
b7d48530 3594
4b7f6baa 3595 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3596 OUTS (outf, "A1 = -A1");
b7d48530 3597
4b7f6baa
CM		 3598 else if (aop == 0 && aopcde == 12)
3599 {
4b7f6baa 3600 OUTS (outf, dregs_hi (dst0));
086134ec 3601 OUTS (outf, " = ");
4b7f6baa 3602 OUTS (outf, dregs_lo (dst0));
086134ec 3603 OUTS (outf, " = SIGN (");
4b7f6baa 3604 OUTS (outf, dregs_hi (src0));
086134ec 3605 OUTS (outf, ") * ");
4b7f6baa 3606 OUTS (outf, dregs_hi (src1));
086134ec 3607 OUTS (outf, " + SIGN (");
4b7f6baa 3608 OUTS (outf, dregs_lo (src0));
086134ec 3609 OUTS (outf, ") * ");
4b7f6baa 3610 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3611 }
3612 else if (aop == 2 && aopcde == 0)
3613 {
4b7f6baa 3614 OUTS (outf, dregs (dst0));
086134ec 3615 OUTS (outf, " = ");
4b7f6baa 3616 OUTS (outf, dregs (src0));
086134ec 3617 OUTS (outf, " -|+ ");
4b7f6baa 3618 OUTS (outf, dregs (src1));
4b7f6baa 3619 amod0 (s, x, outf);
4b7f6baa
CM		 3620 }
3621 else if (aop == 1 && aopcde == 12)
3622 {
4b7f6baa 3623 OUTS (outf, dregs (dst1));
086134ec 3624 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3625 OUTS (outf, dregs (dst0));
086134ec 3626 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3627 }
3628 else if (aop == 2 && aopcde == 4)
3629 {
4b7f6baa 3630 OUTS (outf, dregs (dst1));
086134ec 3631 OUTS (outf, " = ");
4b7f6baa 3632 OUTS (outf, dregs (src0));
086134ec 3633 OUTS (outf, " + ");
4b7f6baa 3634 OUTS (outf, dregs (src1));
086134ec 3635 OUTS (outf, ", ");
4b7f6baa 3636 OUTS (outf, dregs (dst0));
086134ec 3637 OUTS (outf, " = ");
4b7f6baa 3638 OUTS (outf, dregs (src0));
086134ec 3639 OUTS (outf, " - ");
4b7f6baa 3640 OUTS (outf, dregs (src1));
4b7f6baa 3641 amod1 (s, x, outf);
4b7f6baa
CM		 3642 }
3643 else if (HL == 0 && aopcde == 1)
3644 {
4b7f6baa 3645 OUTS (outf, dregs (dst1));
086134ec 3646 OUTS (outf, " = ");
4b7f6baa 3647 OUTS (outf, dregs (src0));
086134ec 3648 OUTS (outf, " +|+ ");
4b7f6baa 3649 OUTS (outf, dregs (src1));
086134ec 3650 OUTS (outf, ", ");
4b7f6baa 3651 OUTS (outf, dregs (dst0));
086134ec 3652 OUTS (outf, " = ");
4b7f6baa 3653 OUTS (outf, dregs (src0));
086134ec 3654 OUTS (outf, " -|- ");
4b7f6baa
CM		 3655 OUTS (outf, dregs (src1));
3656 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3657 }
3658 else if (aop == 0 && aopcde == 11)
3659 {
4b7f6baa 3660 OUTS (outf, dregs (dst0));
086134ec 3661 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3662 }
3663 else if (aop == 0 && aopcde == 10)
3664 {
4b7f6baa 3665 OUTS (outf, dregs_lo (dst0));
086134ec 3666 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3667 }
3668 else if (aop == 1 && aopcde == 10)
3669 {
4b7f6baa 3670 OUTS (outf, dregs_lo (dst0));
086134ec 3671 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3672 }
3673 else if (aop == 1 && aopcde == 0)
3674 {
4b7f6baa 3675 OUTS (outf, dregs (dst0));
086134ec 3676 OUTS (outf, " = ");
4b7f6baa 3677 OUTS (outf, dregs (src0));
086134ec 3678 OUTS (outf, " +|- ");
4b7f6baa 3679 OUTS (outf, dregs (src1));
4b7f6baa 3680 amod0 (s, x, outf);
4b7f6baa
CM		 3681 }
3682 else if (aop == 3 && aopcde == 0)
3683 {
4b7f6baa 3684 OUTS (outf, dregs (dst0));
086134ec 3685 OUTS (outf, " = ");
4b7f6baa 3686 OUTS (outf, dregs (src0));
086134ec 3687 OUTS (outf, " -|- ");
4b7f6baa 3688 OUTS (outf, dregs (src1));
4b7f6baa 3689 amod0 (s, x, outf);
4b7f6baa
CM		 3690 }
3691 else if (aop == 1 && aopcde == 4)
3692 {
4b7f6baa 3693 OUTS (outf, dregs (dst0));
086134ec 3694 OUTS (outf, " = ");
4b7f6baa 3695 OUTS (outf, dregs (src0));
086134ec 3696 OUTS (outf, " - ");
4b7f6baa 3697 OUTS (outf, dregs (src1));
4b7f6baa 3698 amod1 (s, x, outf);
4b7f6baa
CM		 3699 }
3700 else if (aop == 0 && aopcde == 17)
3701 {
4b7f6baa 3702 OUTS (outf, dregs (dst1));
086134ec 3703 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3704 OUTS (outf, dregs (dst0));
086134ec 3705 OUTS (outf, " = A1 - A0");
4b7f6baa 3706 amod1 (s, x, outf);
4b7f6baa
CM		 3707 }
3708 else if (aop == 1 && aopcde == 17)
3709 {
4b7f6baa 3710 OUTS (outf, dregs (dst1));
086134ec 3711 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3712 OUTS (outf, dregs (dst0));
086134ec 3713 OUTS (outf, " = A0 - A1");
4b7f6baa 3714 amod1 (s, x, outf);
4b7f6baa
CM		 3715 }
3716 else if (aop == 0 && aopcde == 18)
3717 {
086134ec 3718 OUTS (outf, "SAA (");
4b7f6baa
CM		 3719 OUTS (outf, dregs (src0 + 1));
3720 OUTS (outf, ":");
086134ec
BS		 3721 OUTS (outf, imm5d (src0));
3722 OUTS (outf, ", ");
4b7f6baa
CM		 3723 OUTS (outf, dregs (src1 + 1));
3724 OUTS (outf, ":");
086134ec
BS		 3725 OUTS (outf, imm5d (src1));
3726 OUTS (outf, ")");
4b7f6baa 3727 aligndir (s, outf);
4b7f6baa
CM		 3728 }
3729 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3730 OUTS (outf, "DISALGNEXCPT");
3731
4b7f6baa
CM		 3732 else if (aop == 0 && aopcde == 20)
3733 {
4b7f6baa 3734 OUTS (outf, dregs (dst0));
086134ec 3735 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3736 OUTS (outf, dregs (src0 + 1));
3737 OUTS (outf, ":");
086134ec
BS		 3738 OUTS (outf, imm5d (src0));
3739 OUTS (outf, ", ");
4b7f6baa
CM		 3740 OUTS (outf, dregs (src1 + 1));
3741 OUTS (outf, ":");
086134ec 3742 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3743 OUTS (outf, ")");
3744 aligndir (s, outf);
4b7f6baa
CM		 3745 }
3746 else if (aop == 1 && aopcde == 20)
3747 {
4b7f6baa 3748 OUTS (outf, dregs (dst0));
086134ec 3749 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3750 OUTS (outf, dregs (src0 + 1));
3751 OUTS (outf, ":");
086134ec
BS		 3752 OUTS (outf, imm5d (src0));
3753 OUTS (outf, ", ");
4b7f6baa
CM		 3754 OUTS (outf, dregs (src1 + 1));
3755 OUTS (outf, ":");
086134ec
BS		 3756 OUTS (outf, imm5d (src1));
3757 OUTS (outf, ") (T");
4b7f6baa
CM		 3758 if (s == 1)
3759 OUTS (outf, ", R)");
3760 else
3761 OUTS (outf, ")");
4b7f6baa
CM		 3762 }
3763 else if (aop == 0 && aopcde == 21)
3764 {
4b7f6baa
CM		 3765 OUTS (outf, "(");
3766 OUTS (outf, dregs (dst1));
086134ec 3767 OUTS (outf, ", ");
4b7f6baa 3768 OUTS (outf, dregs (dst0));
086134ec 3769 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3770 OUTS (outf, dregs (src0 + 1));
3771 OUTS (outf, ":");
086134ec
BS		 3772 OUTS (outf, imm5d (src0));
3773 OUTS (outf, ", ");
4b7f6baa
CM		 3774 OUTS (outf, dregs (src1 + 1));
3775 OUTS (outf, ":");
086134ec
BS		 3776 OUTS (outf, imm5d (src1));
3777 OUTS (outf, ")");
4b7f6baa 3778 aligndir (s, outf);
4b7f6baa
CM		 3779 }
3780 else if (aop == 1 && aopcde == 21)
3781 {
4b7f6baa
CM		 3782 OUTS (outf, "(");
3783 OUTS (outf, dregs (dst1));
086134ec 3784 OUTS (outf, ", ");
4b7f6baa 3785 OUTS (outf, dregs (dst0));
086134ec 3786 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3787 OUTS (outf, dregs (src0 + 1));
3788 OUTS (outf, ":");
086134ec
BS		 3789 OUTS (outf, imm5d (src0));
3790 OUTS (outf, ", ");
4b7f6baa
CM		 3791 OUTS (outf, dregs (src1 + 1));
3792 OUTS (outf, ":");
086134ec
BS		 3793 OUTS (outf, imm5d (src1));
3794 OUTS (outf, ")");
4b7f6baa 3795 aligndir (s, outf);
4b7f6baa
CM		 3796 }
3797 else if (aop == 2 && aopcde == 7)
3798 {
4b7f6baa 3799 OUTS (outf, dregs (dst0));
086134ec 3800 OUTS (outf, " = ABS ");
4b7f6baa 3801 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3802 }
3803 else if (aop == 1 && aopcde == 7)
3804 {
4b7f6baa 3805 OUTS (outf, dregs (dst0));
086134ec 3806 OUTS (outf, " = MIN (");
4b7f6baa 3807 OUTS (outf, dregs (src0));
086134ec 3808 OUTS (outf, ", ");
4b7f6baa
CM		 3809 OUTS (outf, dregs (src1));
3810 OUTS (outf, ")");
4b7f6baa
CM		 3811 }
3812 else if (aop == 0 && aopcde == 7)
3813 {
4b7f6baa 3814 OUTS (outf, dregs (dst0));
086134ec 3815 OUTS (outf, " = MAX (");
4b7f6baa 3816 OUTS (outf, dregs (src0));
086134ec 3817 OUTS (outf, ", ");
4b7f6baa
CM		 3818 OUTS (outf, dregs (src1));
3819 OUTS (outf, ")");
4b7f6baa
CM		 3820 }
3821 else if (aop == 2 && aopcde == 6)
3822 {
4b7f6baa 3823 OUTS (outf, dregs (dst0));
086134ec 3824 OUTS (outf, " = ABS ");
4b7f6baa 3825 OUTS (outf, dregs (src0));
086134ec 3826 OUTS (outf, " (V)");
4b7f6baa
CM		 3827 }
3828 else if (aop == 1 && aopcde == 6)
3829 {
4b7f6baa 3830 OUTS (outf, dregs (dst0));
086134ec 3831 OUTS (outf, " = MIN (");
4b7f6baa 3832 OUTS (outf, dregs (src0));
086134ec 3833 OUTS (outf, ", ");
4b7f6baa 3834 OUTS (outf, dregs (src1));
086134ec 3835 OUTS (outf, ") (V)");
4b7f6baa
CM		 3836 }
3837 else if (aop == 0 && aopcde == 6)
3838 {
4b7f6baa 3839 OUTS (outf, dregs (dst0));
086134ec 3840 OUTS (outf, " = MAX (");
4b7f6baa 3841 OUTS (outf, dregs (src0));
086134ec 3842 OUTS (outf, ", ");
4b7f6baa 3843 OUTS (outf, dregs (src1));
086134ec 3844 OUTS (outf, ") (V)");
4b7f6baa
CM		 3845 }
3846 else if (HL == 1 && aopcde == 1)
3847 {
4b7f6baa 3848 OUTS (outf, dregs (dst1));
086134ec 3849 OUTS (outf, " = ");
4b7f6baa 3850 OUTS (outf, dregs (src0));
086134ec 3851 OUTS (outf, " +|- ");
4b7f6baa 3852 OUTS (outf, dregs (src1));
086134ec 3853 OUTS (outf, ", ");
4b7f6baa 3854 OUTS (outf, dregs (dst0));
086134ec 3855 OUTS (outf, " = ");
4b7f6baa 3856 OUTS (outf, dregs (src0));
086134ec 3857 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3858 OUTS (outf, dregs (src1));
3859 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3860 }
3861 else if (aop == 0 && aopcde == 4)
3862 {
4b7f6baa 3863 OUTS (outf, dregs (dst0));
086134ec 3864 OUTS (outf, " = ");
4b7f6baa 3865 OUTS (outf, dregs (src0));
086134ec 3866 OUTS (outf, " + ");
4b7f6baa 3867 OUTS (outf, dregs (src1));
4b7f6baa 3868 amod1 (s, x, outf);
4b7f6baa
CM		 3869 }
3870 else if (aop == 0 && aopcde == 0)
3871 {
4b7f6baa 3872 OUTS (outf, dregs (dst0));
086134ec 3873 OUTS (outf, " = ");
4b7f6baa 3874 OUTS (outf, dregs (src0));
086134ec 3875 OUTS (outf, " +|+ ");
4b7f6baa 3876 OUTS (outf, dregs (src1));
4b7f6baa 3877 amod0 (s, x, outf);
4b7f6baa
CM		 3878 }
3879 else if (aop == 0 && aopcde == 24)
3880 {
4b7f6baa 3881 OUTS (outf, dregs (dst0));
086134ec 3882 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3883 OUTS (outf, dregs (src0));
086134ec 3884 OUTS (outf, ", ");
4b7f6baa
CM		 3885 OUTS (outf, dregs (src1));
3886 OUTS (outf, ")");
4b7f6baa
CM		 3887 }
3888 else if (aop == 1 && aopcde == 24)
3889 {
4b7f6baa
CM		 3890 OUTS (outf, "(");
3891 OUTS (outf, dregs (dst1));
086134ec 3892 OUTS (outf, ", ");
4b7f6baa
CM		 3893 OUTS (outf, dregs (dst0));
3894 OUTS (outf, ") = BYTEUNPACK ");
3895 OUTS (outf, dregs (src0 + 1));
3896 OUTS (outf, ":");
086134ec 3897 OUTS (outf, imm5d (src0));
4b7f6baa 3898 aligndir (s, outf);
4b7f6baa
CM		 3899 }
3900 else if (aopcde == 13)
3901 {
4b7f6baa
CM		 3902 OUTS (outf, "(");
3903 OUTS (outf, dregs (dst1));
086134ec 3904 OUTS (outf, ", ");
4b7f6baa
CM		 3905 OUTS (outf, dregs (dst0));
3906 OUTS (outf, ") = SEARCH ");
3907 OUTS (outf, dregs (src0));
086134ec 3908 OUTS (outf, " (");
4b7f6baa
CM		 3909 searchmod (aop, outf);
3910 OUTS (outf, ")");
4b7f6baa
CM		 3911 }
3912 else
b7d48530
NC		 3913 return 0;
3914
3915 return 4;
4b7f6baa
CM		 3916}
3917
3918static int
3919decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3920{
b7d48530
NC		 3921 /* dsp32shift
3922 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3923 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3924 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3925 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3926 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3927 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3928 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3929 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3930 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3931 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3932 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3933
4b7f6baa
CM		 3934 if (HLs == 0 && sop == 0 && sopcde == 0)
3935 {
4b7f6baa 3936 OUTS (outf, dregs_lo (dst0));
086134ec 3937 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3938 OUTS (outf, dregs_lo (src1));
3939 OUTS (outf, " BY ");
3940 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3941 }
3942 else if (HLs == 1 && sop == 0 && sopcde == 0)
3943 {
4b7f6baa 3944 OUTS (outf, dregs_lo (dst0));
086134ec 3945 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3946 OUTS (outf, dregs_hi (src1));
3947 OUTS (outf, " BY ");
3948 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3949 }
3950 else if (HLs == 2 && sop == 0 && sopcde == 0)
3951 {
4b7f6baa 3952 OUTS (outf, dregs_hi (dst0));
086134ec 3953 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3954 OUTS (outf, dregs_lo (src1));
3955 OUTS (outf, " BY ");
3956 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3957 }
3958 else if (HLs == 3 && sop == 0 && sopcde == 0)
3959 {
4b7f6baa 3960 OUTS (outf, dregs_hi (dst0));
086134ec 3961 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3962 OUTS (outf, dregs_hi (src1));
3963 OUTS (outf, " BY ");
3964 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3965 }
3966 else if (HLs == 0 && sop == 1 && sopcde == 0)
3967 {
4b7f6baa 3968 OUTS (outf, dregs_lo (dst0));
086134ec 3969 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3970 OUTS (outf, dregs_lo (src1));
3971 OUTS (outf, " BY ");
3972 OUTS (outf, dregs_lo (src0));
086134ec 3973 OUTS (outf, " (S)");
4b7f6baa
CM		 3974 }
3975 else if (HLs == 1 && sop == 1 && sopcde == 0)
3976 {
4b7f6baa 3977 OUTS (outf, dregs_lo (dst0));
086134ec 3978 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3979 OUTS (outf, dregs_hi (src1));
3980 OUTS (outf, " BY ");
3981 OUTS (outf, dregs_lo (src0));
086134ec 3982 OUTS (outf, " (S)");
4b7f6baa
CM		 3983 }
3984 else if (HLs == 2 && sop == 1 && sopcde == 0)
3985 {
4b7f6baa 3986 OUTS (outf, dregs_hi (dst0));
086134ec 3987 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3988 OUTS (outf, dregs_lo (src1));
3989 OUTS (outf, " BY ");
3990 OUTS (outf, dregs_lo (src0));
086134ec 3991 OUTS (outf, " (S)");
4b7f6baa
CM		 3992 }
3993 else if (HLs == 3 && sop == 1 && sopcde == 0)
3994 {
4b7f6baa 3995 OUTS (outf, dregs_hi (dst0));
086134ec 3996 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 3997 OUTS (outf, dregs_hi (src1));
3998 OUTS (outf, " BY ");
3999 OUTS (outf, dregs_lo (src0));
086134ec 4000 OUTS (outf, " (S)");
4b7f6baa
CM		 4001 }
4002 else if (sop == 2 && sopcde == 0)
4003 {
4b7f6baa 4004 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 4005 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4006 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4007 OUTS (outf, " BY ");
4008 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4009 }
4010 else if (sop == 0 && sopcde == 3)
4011 {
4b7f6baa 4012 OUTS (outf, acc01);
086134ec 4013 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4014 OUTS (outf, acc01);
4015 OUTS (outf, " BY ");
4016 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4017 }
4018 else if (sop == 1 && sopcde == 3)
4019 {
4b7f6baa 4020 OUTS (outf, acc01);
086134ec 4021 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4022 OUTS (outf, acc01);
4023 OUTS (outf, " BY ");
4024 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4025 }
4026 else if (sop == 2 && sopcde == 3)
4027 {
4b7f6baa 4028 OUTS (outf, acc01);
086134ec 4029 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4030 OUTS (outf, acc01);
4031 OUTS (outf, " BY ");
4032 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4033 }
4034 else if (sop == 3 && sopcde == 3)
4035 {
4b7f6baa 4036 OUTS (outf, dregs (dst0));
086134ec 4037 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4038 OUTS (outf, dregs (src1));
4039 OUTS (outf, " BY ");
4040 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4041 }
4042 else if (sop == 1 && sopcde == 1)
4043 {
4b7f6baa 4044 OUTS (outf, dregs (dst0));
086134ec 4045 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4046 OUTS (outf, dregs (src1));
4047 OUTS (outf, " BY ");
4048 OUTS (outf, dregs_lo (src0));
086134ec 4049 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4050 }
4051 else if (sop == 0 && sopcde == 1)
4052 {
4b7f6baa 4053 OUTS (outf, dregs (dst0));
086134ec 4054 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4055 OUTS (outf, dregs (src1));
4056 OUTS (outf, " BY ");
4057 OUTS (outf, dregs_lo (src0));
086134ec 4058 OUTS (outf, " (V)");
4b7f6baa
CM		 4059 }
4060 else if (sop == 0 && sopcde == 2)
4061 {
4b7f6baa 4062 OUTS (outf, dregs (dst0));
086134ec 4063 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4064 OUTS (outf, dregs (src1));
4065 OUTS (outf, " BY ");
4066 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4067 }
4068 else if (sop == 1 && sopcde == 2)
4069 {
4b7f6baa 4070 OUTS (outf, dregs (dst0));
086134ec 4071 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4072 OUTS (outf, dregs (src1));
4073 OUTS (outf, " BY ");
4074 OUTS (outf, dregs_lo (src0));
086134ec 4075 OUTS (outf, " (S)");
4b7f6baa
CM		 4076 }
4077 else if (sop == 2 && sopcde == 2)
4078 {
4b7f6baa 4079 OUTS (outf, dregs (dst0));
59a82d23 4080 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4081 OUTS (outf, dregs (src1));
4082 OUTS (outf, " BY ");
4083 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4084 }
4085 else if (sop == 3 && sopcde == 2)
4086 {
4b7f6baa 4087 OUTS (outf, dregs (dst0));
086134ec 4088 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4089 OUTS (outf, dregs (src1));
4090 OUTS (outf, " BY ");
4091 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4092 }
4093 else if (sop == 2 && sopcde == 1)
4094 {
4b7f6baa 4095 OUTS (outf, dregs (dst0));
59a82d23 4096 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4097 OUTS (outf, dregs (src1));
4098 OUTS (outf, " BY ");
4099 OUTS (outf, dregs_lo (src0));
086134ec 4100 OUTS (outf, " (V)");
4b7f6baa
CM		 4101 }
4102 else if (sop == 0 && sopcde == 4)
4103 {
4b7f6baa 4104 OUTS (outf, dregs (dst0));
086134ec 4105 OUTS (outf, " = PACK (");
4b7f6baa 4106 OUTS (outf, dregs_lo (src1));
086134ec 4107 OUTS (outf, ", ");
4b7f6baa
CM		 4108 OUTS (outf, dregs_lo (src0));
4109 OUTS (outf, ")");
4b7f6baa
CM		 4110 }
4111 else if (sop == 1 && sopcde == 4)
4112 {
4b7f6baa 4113 OUTS (outf, dregs (dst0));
086134ec 4114 OUTS (outf, " = PACK (");
4b7f6baa 4115 OUTS (outf, dregs_lo (src1));
086134ec 4116 OUTS (outf, ", ");
4b7f6baa
CM		 4117 OUTS (outf, dregs_hi (src0));
4118 OUTS (outf, ")");
4b7f6baa
CM		 4119 }
4120 else if (sop == 2 && sopcde == 4)
4121 {
4b7f6baa 4122 OUTS (outf, dregs (dst0));
086134ec 4123 OUTS (outf, " = PACK (");
4b7f6baa 4124 OUTS (outf, dregs_hi (src1));
086134ec 4125 OUTS (outf, ", ");
4b7f6baa
CM		 4126 OUTS (outf, dregs_lo (src0));
4127 OUTS (outf, ")");
4b7f6baa
CM		 4128 }
4129 else if (sop == 3 && sopcde == 4)
4130 {
4b7f6baa 4131 OUTS (outf, dregs (dst0));
086134ec 4132 OUTS (outf, " = PACK (");
4b7f6baa 4133 OUTS (outf, dregs_hi (src1));
086134ec 4134 OUTS (outf, ", ");
4b7f6baa
CM		 4135 OUTS (outf, dregs_hi (src0));
4136 OUTS (outf, ")");
4b7f6baa
CM		 4137 }
4138 else if (sop == 0 && sopcde == 5)
4139 {
4b7f6baa 4140 OUTS (outf, dregs_lo (dst0));
086134ec 4141 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4142 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4143 }
4144 else if (sop == 1 && sopcde == 5)
4145 {
4b7f6baa 4146 OUTS (outf, dregs_lo (dst0));
086134ec 4147 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4148 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4149 }
4150 else if (sop == 2 && sopcde == 5)
4151 {
4b7f6baa 4152 OUTS (outf, dregs_lo (dst0));
086134ec 4153 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4154 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4155 }
4156 else if (sop == 0 && sopcde == 6)
4157 {
4b7f6baa 4158 OUTS (outf, dregs_lo (dst0));
086134ec 4159 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4160 }
4161 else if (sop == 1 && sopcde == 6)
4162 {
4b7f6baa 4163 OUTS (outf, dregs_lo (dst0));
086134ec 4164 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4165 }
4166 else if (sop == 3 && sopcde == 6)
4167 {
4b7f6baa 4168 OUTS (outf, dregs_lo (dst0));
086134ec 4169 OUTS (outf, " = ONES ");
4b7f6baa 4170 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4171 }
4172 else if (sop == 0 && sopcde == 7)
4173 {
4b7f6baa 4174 OUTS (outf, dregs_lo (dst0));
086134ec 4175 OUTS (outf, " = EXPADJ (");
4b7f6baa 4176 OUTS (outf, dregs (src1));
086134ec 4177 OUTS (outf, ", ");
4b7f6baa
CM		 4178 OUTS (outf, dregs_lo (src0));
4179 OUTS (outf, ")");
4b7f6baa
CM		 4180 }
4181 else if (sop == 1 && sopcde == 7)
4182 {
4b7f6baa 4183 OUTS (outf, dregs_lo (dst0));
086134ec 4184 OUTS (outf, " = EXPADJ (");
4b7f6baa 4185 OUTS (outf, dregs (src1));
086134ec 4186 OUTS (outf, ", ");
4b7f6baa
CM		 4187 OUTS (outf, dregs_lo (src0));
4188 OUTS (outf, ") (V)");
4b7f6baa
CM		 4189 }
4190 else if (sop == 2 && sopcde == 7)
4191 {
4b7f6baa 4192 OUTS (outf, dregs_lo (dst0));
086134ec 4193 OUTS (outf, " = EXPADJ (");
4b7f6baa 4194 OUTS (outf, dregs_lo (src1));
086134ec 4195 OUTS (outf, ", ");
4b7f6baa
CM		 4196 OUTS (outf, dregs_lo (src0));
4197 OUTS (outf, ")");
4b7f6baa
CM		 4198 }
4199 else if (sop == 3 && sopcde == 7)
4200 {
4b7f6baa 4201 OUTS (outf, dregs_lo (dst0));
086134ec 4202 OUTS (outf, " = EXPADJ (");
4b7f6baa 4203 OUTS (outf, dregs_hi (src1));
086134ec 4204 OUTS (outf, ", ");
4b7f6baa
CM		 4205 OUTS (outf, dregs_lo (src0));
4206 OUTS (outf, ")");
4b7f6baa
CM		 4207 }
4208 else if (sop == 0 && sopcde == 8)
4209 {
4b7f6baa
CM		 4210 OUTS (outf, "BITMUX (");
4211 OUTS (outf, dregs (src0));
086134ec 4212 OUTS (outf, ", ");
4b7f6baa 4213 OUTS (outf, dregs (src1));
086134ec 4214 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4215 }
4216 else if (sop == 1 && sopcde == 8)
4217 {
4b7f6baa
CM		 4218 OUTS (outf, "BITMUX (");
4219 OUTS (outf, dregs (src0));
086134ec 4220 OUTS (outf, ", ");
4b7f6baa 4221 OUTS (outf, dregs (src1));
086134ec 4222 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4223 }
4224 else if (sop == 0 && sopcde == 9)
4225 {
4b7f6baa 4226 OUTS (outf, dregs_lo (dst0));
086134ec 4227 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4228 OUTS (outf, dregs (src1));
4229 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4230 }
4231 else if (sop == 1 && sopcde == 9)
4232 {
4b7f6baa 4233 OUTS (outf, dregs_lo (dst0));
086134ec 4234 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4235 OUTS (outf, dregs (src1));
4236 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4237 }
4238 else if (sop == 2 && sopcde == 9)
4239 {
4b7f6baa 4240 OUTS (outf, dregs (dst0));
086134ec 4241 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4242 OUTS (outf, dregs (src1));
086134ec 4243 OUTS (outf, ", ");
4b7f6baa 4244 OUTS (outf, dregs (src0));
086134ec 4245 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4246 }
4247 else if (sop == 3 && sopcde == 9)
4248 {
4b7f6baa 4249 OUTS (outf, dregs (dst0));
086134ec 4250 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4251 OUTS (outf, dregs (src1));
086134ec 4252 OUTS (outf, ", ");
4b7f6baa 4253 OUTS (outf, dregs (src0));
086134ec 4254 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4255 }
4256 else if (sop == 0 && sopcde == 10)
4257 {
4b7f6baa 4258 OUTS (outf, dregs (dst0));
086134ec 4259 OUTS (outf, " = EXTRACT (");
4b7f6baa 4260 OUTS (outf, dregs (src1));
086134ec 4261 OUTS (outf, ", ");
4b7f6baa
CM		 4262 OUTS (outf, dregs_lo (src0));
4263 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4264 }
4265 else if (sop == 1 && sopcde == 10)
4266 {
4b7f6baa 4267 OUTS (outf, dregs (dst0));
086134ec 4268 OUTS (outf, " = EXTRACT (");
4b7f6baa 4269 OUTS (outf, dregs (src1));
086134ec 4270 OUTS (outf, ", ");
4b7f6baa 4271 OUTS (outf, dregs_lo (src0));
086134ec 4272 OUTS (outf, ") (X)");
4b7f6baa
CM		 4273 }
4274 else if (sop == 2 && sopcde == 10)
4275 {
4b7f6baa 4276 OUTS (outf, dregs (dst0));
086134ec 4277 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4278 OUTS (outf, dregs (src1));
086134ec 4279 OUTS (outf, ", ");
4b7f6baa
CM		 4280 OUTS (outf, dregs (src0));
4281 OUTS (outf, ")");
4b7f6baa
CM		 4282 }
4283 else if (sop == 3 && sopcde == 10)
4284 {
4b7f6baa 4285 OUTS (outf, dregs (dst0));
086134ec 4286 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4287 OUTS (outf, dregs (src1));
086134ec 4288 OUTS (outf, ", ");
4b7f6baa 4289 OUTS (outf, dregs (src0));
086134ec 4290 OUTS (outf, ") (X)");
4b7f6baa
CM		 4291 }
4292 else if (sop == 0 && sopcde == 11)
4293 {
4b7f6baa 4294 OUTS (outf, dregs_lo (dst0));
086134ec 4295 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4296 OUTS (outf, dregs (src0));
4297 OUTS (outf, ")");
4b7f6baa
CM		 4298 }
4299 else if (sop == 1 && sopcde == 11)
4300 {
4b7f6baa 4301 OUTS (outf, dregs_lo (dst0));
086134ec 4302 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4303 OUTS (outf, dregs (src0));
4304 OUTS (outf, ")");
4b7f6baa
CM		 4305 }
4306 else if (sop == 0 && sopcde == 12)
086134ec 4307 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4308
4b7f6baa
CM		 4309 else if (sop == 1 && sopcde == 12)
4310 {
4b7f6baa 4311 OUTS (outf, dregs_lo (dst0));
086134ec 4312 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4313 }
4314 else if (sop == 0 && sopcde == 13)
4315 {
4b7f6baa 4316 OUTS (outf, dregs (dst0));
086134ec 4317 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4318 OUTS (outf, dregs (src1));
086134ec 4319 OUTS (outf, ", ");
4b7f6baa
CM		 4320 OUTS (outf, dregs (src0));
4321 OUTS (outf, ")");
4b7f6baa
CM		 4322 }
4323 else if (sop == 1 && sopcde == 13)
4324 {
4b7f6baa 4325 OUTS (outf, dregs (dst0));
086134ec 4326 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4327 OUTS (outf, dregs (src1));
086134ec 4328 OUTS (outf, ", ");
4b7f6baa
CM		 4329 OUTS (outf, dregs (src0));
4330 OUTS (outf, ")");
4b7f6baa
CM		 4331 }
4332 else if (sop == 2 && sopcde == 13)
4333 {
4b7f6baa 4334 OUTS (outf, dregs (dst0));
086134ec 4335 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4336 OUTS (outf, dregs (src1));
086134ec 4337 OUTS (outf, ", ");
4b7f6baa
CM		 4338 OUTS (outf, dregs (src0));
4339 OUTS (outf, ")");
4b7f6baa
CM		 4340 }
4341 else
b7d48530
NC		 4342 return 0;
4343
4344 return 4;
4b7f6baa
CM		 4345}
4346
4347static int
4348decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4349{
b7d48530
NC		 4350 /* dsp32shiftimm
4351 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4352 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4353 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4354 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4355 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4356 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4357 int bit8 = ((iw1 >> 8) & 0x1);
4358 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4359 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4360 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4361 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4362 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa
CM		 4363
4364
331f1cbe 4365 if (sop == 0 && sopcde == 0)
4b7f6baa 4366 {
331f1cbe
BS		 4367 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4368 OUTS (outf, " = ");
4369 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4370 OUTS (outf, " >>> ");
4b7f6baa 4371 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4372 }
331f1cbe 4373 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4374 {
331f1cbe
BS		 4375 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4376 OUTS (outf, " = ");
4377 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4378 OUTS (outf, " << ");
4b7f6baa 4379 OUTS (outf, uimm4 (immag));
331f1cbe 4380 OUTS (outf, " (S)");
4b7f6baa 4381 }
331f1cbe 4382 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4383 {
331f1cbe
BS		 4384 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4385 OUTS (outf, " = ");
4386 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4387 OUTS (outf, " >>> ");
4b7f6baa 4388 OUTS (outf, uimm4 (newimmag));
331f1cbe 4389 OUTS (outf, " (S)");
4b7f6baa 4390 }
331f1cbe 4391 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4392 {
331f1cbe
BS		 4393 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4394 OUTS (outf, " = ");
4395 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4396 OUTS (outf, " << ");
4b7f6baa 4397 OUTS (outf, uimm4 (immag));
4b7f6baa 4398 }
331f1cbe 4399 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4400 {
331f1cbe
BS		 4401 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4402 OUTS (outf, " = ");
4403 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4404 OUTS (outf, " >> ");
4b7f6baa 4405 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4406 }
4b7f6baa
CM		 4407 else if (sop == 2 && sopcde == 3 && HLs == 1)
4408 {
086134ec 4409 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4410 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4411 }
4412 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4413 {
086134ec 4414 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4415 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4416 }
4417 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4418 {
086134ec 4419 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4420 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4421 }
4422 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4423 {
086134ec 4424 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4425 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4426 }
4427 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4428 {
086134ec 4429 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4430 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4431 }
4432 else if (sop == 1 && sopcde == 3 && HLs == 0)
4433 {
086134ec 4434 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4435 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4436 }
4437 else if (sop == 1 && sopcde == 3 && HLs == 1)
4438 {
086134ec 4439 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4440 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4441 }
4442 else if (sop == 2 && sopcde == 3 && HLs == 0)
4443 {
086134ec 4444 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4445 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4446 }
4447 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4448 {
4b7f6baa 4449 OUTS (outf, dregs (dst0));
086134ec 4450 OUTS (outf, " = ");
4b7f6baa 4451 OUTS (outf, dregs (src1));
086134ec 4452 OUTS (outf, " << ");
4b7f6baa
CM		 4453 OUTS (outf, uimm5 (immag));
4454 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4455 }
4456 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4457 {
4b7f6baa 4458 OUTS (outf, dregs (dst0));
086134ec 4459 OUTS (outf, " = ");
4b7f6baa 4460 OUTS (outf, dregs (src1));
086134ec 4461 OUTS (outf, " >>> ");
4b7f6baa 4462 OUTS (outf, imm5 (-immag));
0b7691fd 4463 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4464 }
4465 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4466 {
4b7f6baa 4467 OUTS (outf, dregs (dst0));
086134ec 4468 OUTS (outf, " = ");
4b7f6baa
CM		 4469 OUTS (outf, dregs (src1));
4470 OUTS (outf, " >> ");
4471 OUTS (outf, uimm5 (newimmag));
4472 OUTS (outf, " (V)");
4b7f6baa
CM		 4473 }
4474 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4475 {
4b7f6baa 4476 OUTS (outf, dregs (dst0));
086134ec 4477 OUTS (outf, " = ");
4b7f6baa 4478 OUTS (outf, dregs (src1));
086134ec 4479 OUTS (outf, " << ");
4b7f6baa
CM		 4480 OUTS (outf, imm5 (immag));
4481 OUTS (outf, " (V)");
4b7f6baa
CM		 4482 }
4483 else if (sop == 0 && sopcde == 1)
4484 {
4b7f6baa 4485 OUTS (outf, dregs (dst0));
086134ec 4486 OUTS (outf, " = ");
4b7f6baa 4487 OUTS (outf, dregs (src1));
086134ec 4488 OUTS (outf, " >>> ");
4b7f6baa
CM		 4489 OUTS (outf, uimm5 (newimmag));
4490 OUTS (outf, " (V)");
4b7f6baa
CM		 4491 }
4492 else if (sop == 1 && sopcde == 2)
4493 {
4b7f6baa 4494 OUTS (outf, dregs (dst0));
086134ec 4495 OUTS (outf, " = ");
4b7f6baa 4496 OUTS (outf, dregs (src1));
086134ec 4497 OUTS (outf, " << ");
4b7f6baa 4498 OUTS (outf, uimm5 (immag));
086134ec 4499 OUTS (outf, " (S)");
4b7f6baa
CM		 4500 }
4501 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4502 {
4b7f6baa 4503 OUTS (outf, dregs (dst0));
086134ec 4504 OUTS (outf, " = ");
4b7f6baa 4505 OUTS (outf, dregs (src1));
086134ec 4506 OUTS (outf, " >> ");
4b7f6baa 4507 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4508 }
4509 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4510 {
4b7f6baa 4511 OUTS (outf, dregs (dst0));
086134ec 4512 OUTS (outf, " = ");
4b7f6baa 4513 OUTS (outf, dregs (src1));
086134ec 4514 OUTS (outf, " << ");
4b7f6baa 4515 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4516 }
4517 else if (sop == 3 && sopcde == 2)
4518 {
4b7f6baa 4519 OUTS (outf, dregs (dst0));
086134ec 4520 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4521 OUTS (outf, dregs (src1));
4522 OUTS (outf, " BY ");
4523 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4524 }
4525 else if (sop == 0 && sopcde == 2)
4526 {
4b7f6baa 4527 OUTS (outf, dregs (dst0));
086134ec 4528 OUTS (outf, " = ");
4b7f6baa 4529 OUTS (outf, dregs (src1));
086134ec 4530 OUTS (outf, " >>> ");
4b7f6baa 4531 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4532 }
4533 else
b7d48530
NC		 4534 return 0;
4535
4536 return 4;
4b7f6baa
CM		 4537}
4538
4539static int
4540decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4541{
b7d48530
NC		 4542 /* pseudoDEBUG
4543 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4544 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4545 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4546 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4547 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4548 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4549
219b747a
MF		 4550 if (parallel)
4551 return 0;
4552
4b7f6baa 4553 if (reg == 0 && fn == 3)
b7d48530
NC		 4554 OUTS (outf, "DBG A0");
4555
4b7f6baa 4556 else if (reg == 1 && fn == 3)
b7d48530
NC		 4557 OUTS (outf, "DBG A1");
4558
4b7f6baa 4559 else if (reg == 3 && fn == 3)
b7d48530
NC		 4560 OUTS (outf, "ABORT");
4561
4b7f6baa 4562 else if (reg == 4 && fn == 3)
b7d48530
NC		 4563 OUTS (outf, "HLT");
4564
4b7f6baa 4565 else if (reg == 5 && fn == 3)
b7d48530
NC		 4566 OUTS (outf, "DBGHALT");
4567
4b7f6baa
CM		 4568 else if (reg == 6 && fn == 3)
4569 {
086134ec 4570 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4571 OUTS (outf, dregs (grp));
4572 OUTS (outf, ")");
4b7f6baa
CM		 4573 }
4574 else if (reg == 7 && fn == 3)
b7d48530
NC		 4575 OUTS (outf, "DBG");
4576
4b7f6baa
CM		 4577 else if (grp == 0 && fn == 2)
4578 {
73a63ccf 4579 OUTS (outf, "OUTC ");
4b7f6baa 4580 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4581 }
4582 else if (fn == 0)
4583 {
a01eda85 4584 OUTS (outf, "DBG ");
4b7f6baa 4585 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4586 }
4587 else if (fn == 1)
4588 {
9805c0a5 4589 OUTS (outf, "PRNT ");
4b7f6baa 4590 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4591 }
4592 else
b7d48530
NC		 4593 return 0;
4594
4595 return 2;
4b7f6baa
CM		 4596}
4597
73a63ccf
MF		 4598static int
4599decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4600{
4601 /* psedoOChar
4602 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4603 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4604 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4605 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4606
219b747a
MF		 4607 if (parallel)
4608 return 0;
4609
73a63ccf
MF		 4610 OUTS (outf, "OUTC ");
4611 OUTS (outf, uimm8 (ch));
4612
4613 return 2;
4614}
4615
4b7f6baa
CM		 4616static int
4617decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4618{
b7d48530
NC		 4619 /* pseudodbg_assert
4620 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4621 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4622 |.expected......................................................|
4623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4624 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4625 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4626 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4627 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4628
219b747a
MF		 4629 if (parallel)
4630 return 0;
4631
4b7f6baa
CM		 4632 if (dbgop == 0)
4633 {
086134ec 4634 OUTS (outf, "DBGA (");
66a6900a 4635 OUTS (outf, regs_lo (regtest, grp));
086134ec 4636 OUTS (outf, ", ");
4b7f6baa
CM		 4637 OUTS (outf, uimm16 (expected));
4638 OUTS (outf, ")");
4b7f6baa
CM		 4639 }
4640 else if (dbgop == 1)
4641 {
086134ec 4642 OUTS (outf, "DBGA (");
66a6900a 4643 OUTS (outf, regs_hi (regtest, grp));
086134ec 4644 OUTS (outf, ", ");
4b7f6baa
CM		 4645 OUTS (outf, uimm16 (expected));
4646 OUTS (outf, ")");
4b7f6baa
CM		 4647 }
4648 else if (dbgop == 2)
4649 {
086134ec 4650 OUTS (outf, "DBGAL (");
66a6900a 4651 OUTS (outf, allregs (regtest, grp));
086134ec 4652 OUTS (outf, ", ");
4b7f6baa
CM		 4653 OUTS (outf, uimm16 (expected));
4654 OUTS (outf, ")");
4b7f6baa
CM		 4655 }
4656 else if (dbgop == 3)
4657 {
086134ec 4658 OUTS (outf, "DBGAH (");
66a6900a 4659 OUTS (outf, allregs (regtest, grp));
086134ec 4660 OUTS (outf, ", ");
4b7f6baa
CM		 4661 OUTS (outf, uimm16 (expected));
4662 OUTS (outf, ")");
4b7f6baa
CM		 4663 }
4664 else
b7d48530
NC		 4665 return 0;
4666 return 4;
4b7f6baa
CM		 4667}
4668
ad15c38e 4669static int
4b7f6baa
CM		 4670_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4671{
4b7f6baa
CM		 4672 bfd_byte buf[4];
4673 TIword iw0;
4674 TIword iw1;
4675 int status;
b7d48530
NC		 4676 int rv = 0;
4677
4b7f6baa 4678 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
c7e2358a
AM		 4679 /* FIXME */
4680 (void) status;
4b7f6baa 4681 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
c7e2358a
AM		 4682 /* FIXME */
4683 (void) status;
4b7f6baa
CM		 4684
4685 iw0 = bfd_getl16 (buf);
4686 iw1 = bfd_getl16 (buf + 2);
4687
4688 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4689 {
219b747a
MF		 4690 if (parallel)
4691 {
4692 OUTS (outf, "ILLEGAL");
4693 return 0;
4694 }
086134ec 4695 OUTS (outf, "MNOP");
4b7f6baa
CM		 4696 return 4;
4697 }
4698 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4699 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4700 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4701 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4702 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4703 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4704 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4705 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4706 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4707 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4708 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4709 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4710 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4711 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4712 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4713 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4714 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4715 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4716 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4717 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4718 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4719 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4720 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4721 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4722 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4723 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4724 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4725 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4726 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4727 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4728 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4729 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4730 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4731 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4732 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4733 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4734 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4735 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4736 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4737 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4738 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4739 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4740 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4741 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4742 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4743 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4744 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4745 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4746 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4747 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4748 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4749 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4750 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4751 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4752 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4753 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4754 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4755 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4756 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4757 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4758 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4759 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4760 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4761 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4762 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4763 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4764 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4765 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4766 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4767 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4768 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4769 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4770 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4771 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4772
219b747a
MF		 4773 if (rv == 0)
4774 OUTS (outf, "ILLEGAL");
4775
b7d48530 4776 return rv;
4b7f6baa
CM		 4777}
4778
4779
4780int
4781print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4782{
471e4e36
JZ		 4783 bfd_byte buf[2];
4784 unsigned short iw0;
4785 int status;
4b7f6baa 4786 int count = 0;
471e4e36
JZ		 4787
4788 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
c7e2358a
AM		 4789 /* FIXME */
4790 (void) status;
471e4e36 4791 iw0 = bfd_getl16 (buf);
4b7f6baa
CM		 4792
4793 count += _print_insn_bfin (pc, outf);
471e4e36 4794
4b7f6baa 4795 /* Proper display of multiple issue instructions. */
471e4e36 4796
219b747a 4797 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
b7d48530 4798 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4799 {
219b747a
MF		 4800 int legal = 1;
4801 int len;
4802
086134ec 4803 parallel = 1;
4b7f6baa 4804 outf->fprintf_func (outf->stream, " || ");
219b747a 4805 len = _print_insn_bfin (pc + 4, outf);
4b7f6baa 4806 outf->fprintf_func (outf->stream, " || ");
219b747a
MF		 4807 if (len != 2)
4808 legal = 0;
4809 len = _print_insn_bfin (pc + 6, outf);
4810 if (len != 2)
4811 legal = 0;
4812
4813 if (legal)
4814 count = 8;
4815 else
4816 {
4817 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4818 comment = 1;
4819 count = 0;
4820 }
086134ec 4821 parallel = 0;
4b7f6baa 4822 }
219b747a 4823
086134ec
BS		 4824 if (!comment)
4825 outf->fprintf_func (outf->stream, ";");
4826
219b747a
MF		 4827 if (count == 0)
4828 return 2;
4829
086134ec
BS		 4830 comment = 0;
4831
4b7f6baa
CM		 4832 return count;
4833}
GDB Binutils - Deliverables
This page took 0.509486 seconds and 4 git commands to generate.