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opcodes: blackfin: add multiple inclusion protection
[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c
CommitLineData
4b7f6baa 1/* Disassemble ADI Blackfin Instructions.
c7e2358a 2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4b7f6baa 3
9b201bb5
NC		 4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
4b7f6baa 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
4b7f6baa 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
4b7f6baa
CM		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21#include <stdio.h>
22#include <stdlib.h>
23#include <string.h>
24
25#include "opcode/bfin.h"
26
27#define M_S2RND 1
28#define M_T 2
29#define M_W32 3
30#define M_FU 4
31#define M_TFU 6
32#define M_IS 8
33#define M_ISS2 9
34#define M_IH 11
35#define M_IU 12
36
37#ifndef PRINTF
38#define PRINTF printf
39#endif
40
41#ifndef EXIT
42#define EXIT exit
43#endif
44
45typedef long TIword;
46
b7d48530
NC		 47#define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48#define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49#define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50#define MASKBITS(val, bits) (val & ((1 << bits) - 1))
4b7f6baa
CM		 51
52#include "dis-asm.h"
b7d48530 53
b21c9cb4
BS		 54typedef unsigned int bu32;
55
528c6277
MF		 56static char comment = 0;
57static char parallel = 0;
58
4b7f6baa
CM		 59typedef enum
60{
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
086134ec
BS		 62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
4b7f6baa
CM		 66} const_forms_t;
67
528c6277 68static const struct
4b7f6baa 69{
528c6277
MF		 70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
4b7f6baa
CM		 82} constant_formats[] =
83{
086134ec
BS		 84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
4b7f6baa
CM		 127};
128
528c6277
MF		 129static const char *
130fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
4b7f6baa
CM		 131{
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
7a360e83
MF		 141 /* truncate to 32-bits for proper symbol lookup/matching */
142 ea = (bu32)ea;
143
086134ec
BS		 144 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
145 {
146 outf->print_address_func (ea, outf);
147 return "";
148 }
149 else
150 {
0af1713e 151 sprintf (buf, "%lx", (unsigned long) x);
086134ec
BS		 152 return buf;
153 }
4b7f6baa
CM		 154 }
155
156 /* Negative constants have an implied sign bit. */
157 if (constant_formats[cf].negative)
158 {
159 int nb = constant_formats[cf].nbits + 1;
b7d48530 160
4b7f6baa
CM		 161 x = x | (1 << constant_formats[cf].nbits);
162 x = SIGNEXTEND (x, nb);
163 }
164 else
165 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
166
167 if (constant_formats[cf].offset)
168 x += constant_formats[cf].offset;
169
170 if (constant_formats[cf].scale)
171 x <<= constant_formats[cf].scale;
172
086134ec
BS		 173 if (constant_formats[cf].decimal)
174 {
175 if (constant_formats[cf].leading)
176 {
177 char ps[10];
178 sprintf (ps, "%%%ii", constant_formats[cf].leading);
179 sprintf (buf, ps, x);
180 }
181 else
182 sprintf (buf, "%li", x);
183 }
4b7f6baa 184 else
086134ec
BS		 185 {
186 if (constant_formats[cf].issigned && x < 0)
187 sprintf (buf, "-0x%x", abs (x));
188 else
0af1713e 189 sprintf (buf, "0x%lx", (unsigned long) x);
086134ec 190 }
4b7f6baa
CM		 191
192 return buf;
193}
194
b21c9cb4
BS		 195static bu32
196fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
197{
198 if (0 && constant_formats[cf].reloc)
199 {
200 bu32 ea = (((constant_formats[cf].pcrel
086134ec
BS		 201 ? SIGNEXTEND (x, constant_formats[cf].nbits)
202 : x) + constant_formats[cf].offset)
203 << constant_formats[cf].scale);
b21c9cb4 204 if (constant_formats[cf].pcrel)
086134ec 205 ea += pc;
b21c9cb4
BS		 206
207 return ea;
208 }
209
210 /* Negative constants have an implied sign bit. */
211 if (constant_formats[cf].negative)
212 {
213 int nb = constant_formats[cf].nbits + 1;
214 x = x | (1 << constant_formats[cf].nbits);
215 x = SIGNEXTEND (x, nb);
216 }
217 else if (constant_formats[cf].issigned)
218 x = SIGNEXTEND (x, constant_formats[cf].nbits);
219
220 x += constant_formats[cf].offset;
221 x <<= constant_formats[cf].scale;
222
223 return x;
224}
225
4b7f6baa
CM		 226enum machine_registers
227{
228 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
229 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
230 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
231 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
232 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
233 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
234 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
235 REG_L2, REG_L3,
236 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
237 REG_AQ, REG_V, REG_VS,
238 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
239 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
240 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
241 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
242 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
243 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
244 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
245 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
246 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
247 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
22215ae0 248 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
4b7f6baa
CM		 249 REG_LASTREG,
250};
251
252enum reg_class
253{
254 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
255 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
256 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
257 rc_sysregs3, rc_allregs,
258 LIM_REG_CLASSES
259};
260
528c6277 261static const char *reg_names[] =
4b7f6baa
CM		 262{
263 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
264 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
265 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
266 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
086134ec 267 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
4b7f6baa
CM		 268 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
269 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
270 "L2", "L3",
271 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
272 "AQ", "V", "VS",
273 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
274 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
275 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
276 "RETE", "EMUDAT",
277 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
278 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
279 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
280 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
281 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
282 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
283 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
22215ae0 284 "AC0_COPY", "V_COPY", "RND_MOD",
4b7f6baa
CM		 285 "LASTREG",
286 0
287};
288
289#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
290
291/* RL(0..7). */
292static enum machine_registers decode_dregs_lo[] =
293{
294 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
295};
296
b7d48530 297#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
4b7f6baa
CM		 298
299/* RH(0..7). */
300static enum machine_registers decode_dregs_hi[] =
301{
302 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
303};
304
b7d48530 305#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
4b7f6baa
CM		 306
307/* R(0..7). */
308static enum machine_registers decode_dregs[] =
309{
310 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
311};
312
b7d48530 313#define dregs(x) REGNAME (decode_dregs[(x) & 7])
4b7f6baa
CM		 314
315/* R BYTE(0..7). */
316static enum machine_registers decode_dregs_byte[] =
317{
318 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
319};
320
b7d48530 321#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
4b7f6baa
CM		 322
323/* P(0..5) SP FP. */
324static enum machine_registers decode_pregs[] =
325{
326 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
327};
328
b7d48530
NC		 329#define pregs(x) REGNAME (decode_pregs[(x) & 7])
330#define spfp(x) REGNAME (decode_spfp[(x) & 1])
331#define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
332#define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
333#define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
334#define accum(x) REGNAME (decode_accum[(x) & 1])
4b7f6baa
CM		 335
336/* I(0..3). */
337static enum machine_registers decode_iregs[] =
338{
339 REG_I0, REG_I1, REG_I2, REG_I3,
340};
341
b7d48530 342#define iregs(x) REGNAME (decode_iregs[(x) & 3])
4b7f6baa
CM		 343
344/* M(0..3). */
345static enum machine_registers decode_mregs[] =
346{
347 REG_M0, REG_M1, REG_M2, REG_M3,
348};
349
b7d48530
NC		 350#define mregs(x) REGNAME (decode_mregs[(x) & 3])
351#define bregs(x) REGNAME (decode_bregs[(x) & 3])
352#define lregs(x) REGNAME (decode_lregs[(x) & 3])
4b7f6baa
CM		 353
354/* dregs pregs. */
355static enum machine_registers decode_dpregs[] =
356{
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359};
360
b7d48530 361#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
4b7f6baa
CM		 362
363/* [dregs pregs]. */
364static enum machine_registers decode_gregs[] =
365{
366 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368};
369
b7d48530 370#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
4b7f6baa
CM		 371
372/* [dregs pregs (iregs mregs) (bregs lregs)]. */
373static enum machine_registers decode_regs[] =
374{
375 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
376 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
377 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
378 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
379};
380
b7d48530 381#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
4b7f6baa
CM		 382
383/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
384static enum machine_registers decode_regs_lo[] =
385{
386 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
387 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
388 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
389 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
390};
391
b7d48530 392#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
4b7f6baa
CM		 393/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
394static enum machine_registers decode_regs_hi[] =
395{
396 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
397 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
1985c81c 398 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
4b7f6baa
CM		 399 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
400};
401
b7d48530 402#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
4b7f6baa
CM		 403
404static enum machine_registers decode_statbits[] =
405{
22215ae0
MF		 406 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
407 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
408 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
410 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
411 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
412 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
413 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
4b7f6baa
CM		 414};
415
ad15c38e 416#define statbits(x) REGNAME (decode_statbits[(x) & 31])
4b7f6baa
CM		 417
418/* LC0 LC1. */
419static enum machine_registers decode_counters[] =
420{
421 REG_LC0, REG_LC1,
422};
423
b7d48530
NC		 424#define counters(x) REGNAME (decode_counters[(x) & 1])
425#define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
4b7f6baa
CM		 426
427/* [dregs pregs (iregs mregs) (bregs lregs)
428 dregs2_sysregs1 open sysregs2 sysregs3]. */
429static enum machine_registers decode_allregs[] =
430{
431 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
432 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
433 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
434 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
435 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
436 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
437 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
c958a8a8
JZ		 438 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
439 REG_LASTREG,
4b7f6baa
CM		 440};
441
50e2162a
MF		 442#define IS_DREG(g,r) ((g) == 0 && (r) < 8)
443#define IS_PREG(g,r) ((g) == 1 && (r) < 8)
c958a8a8 444#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
50e2162a
MF		 445#define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
446#define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
c958a8a8
JZ		 447#define IS_SYSREG(g,r) \
448 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
50e2162a
MF		 449#define IS_RESERVEDREG(g,r) \
450 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
451
452#define allreg(r,g) (!IS_RESERVEDREG (g, r))
453#define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
c958a8a8 454
b7d48530
NC		 455#define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
456#define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
086134ec 457#define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
b7d48530
NC		 458#define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
459#define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
460#define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
461#define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
462#define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
463#define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
464#define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
465#define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
466#define imm16(x) fmtconst (c_imm16, x, 0, outf)
086134ec 467#define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
b7d48530
NC		 468#define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
469#define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
470#define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
471#define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
472#define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
473#define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
474#define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
475#define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
476#define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
477#define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
086134ec 478#define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
b7d48530
NC		 479#define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
480#define imm3(x) fmtconst (c_imm3, x, 0, outf)
481#define imm4(x) fmtconst (c_imm4, x, 0, outf)
482#define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
483#define imm5(x) fmtconst (c_imm5, x, 0, outf)
086134ec 484#define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
b7d48530
NC		 485#define imm6(x) fmtconst (c_imm6, x, 0, outf)
486#define imm7(x) fmtconst (c_imm7, x, 0, outf)
086134ec 487#define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
b7d48530
NC		 488#define imm8(x) fmtconst (c_imm8, x, 0, outf)
489#define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
490#define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
b21c9cb4 491#define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
086134ec 492#define imm32(x) fmtconst (c_imm32, x, 0, outf)
b21c9cb4 493#define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
086134ec
BS		 494#define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
495#define imm7_val(x) fmtconst_val (c_imm7, x, 0)
b21c9cb4
BS		 496#define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
497#define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
4b7f6baa
CM		 498
499/* (arch.pm)arch_disassembler_functions. */
4b7f6baa 500#ifndef OUTS
4ca47a51 501#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
4b7f6baa
CM		 502#endif
503
4b7f6baa
CM		 504static void
505amod0 (int s0, int x0, disassemble_info *outf)
506{
b7d48530 507 if (s0 == 1 && x0 == 0)
086134ec 508 OUTS (outf, " (S)");
4b7f6baa 509 else if (s0 == 0 && x0 == 1)
086134ec 510 OUTS (outf, " (CO)");
4b7f6baa 511 else if (s0 == 1 && x0 == 1)
086134ec 512 OUTS (outf, " (SCO)");
4b7f6baa
CM		 513}
514
515static void
516amod1 (int s0, int x0, disassemble_info *outf)
517{
518 if (s0 == 0 && x0 == 0)
086134ec 519 OUTS (outf, " (NS)");
4b7f6baa 520 else if (s0 == 1 && x0 == 0)
086134ec 521 OUTS (outf, " (S)");
4b7f6baa
CM		 522}
523
524static void
525amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
526{
b7d48530 527 if (s0 == 1 && x0 == 0 && aop0 == 0)
086134ec 528 OUTS (outf, " (S)");
4b7f6baa 529 else if (s0 == 0 && x0 == 1 && aop0 == 0)
086134ec 530 OUTS (outf, " (CO)");
4b7f6baa 531 else if (s0 == 1 && x0 == 1 && aop0 == 0)
086134ec 532 OUTS (outf, " (SCO)");
4b7f6baa 533 else if (s0 == 0 && x0 == 0 && aop0 == 2)
086134ec 534 OUTS (outf, " (ASR)");
4b7f6baa 535 else if (s0 == 1 && x0 == 0 && aop0 == 2)
086134ec 536 OUTS (outf, " (S, ASR)");
4b7f6baa 537 else if (s0 == 0 && x0 == 1 && aop0 == 2)
086134ec 538 OUTS (outf, " (CO, ASR)");
4b7f6baa 539 else if (s0 == 1 && x0 == 1 && aop0 == 2)
086134ec 540 OUTS (outf, " (SCO, ASR)");
4b7f6baa 541 else if (s0 == 0 && x0 == 0 && aop0 == 3)
086134ec 542 OUTS (outf, " (ASL)");
4b7f6baa 543 else if (s0 == 1 && x0 == 0 && aop0 == 3)
086134ec 544 OUTS (outf, " (S, ASL)");
4b7f6baa 545 else if (s0 == 0 && x0 == 1 && aop0 == 3)
086134ec 546 OUTS (outf, " (CO, ASL)");
4b7f6baa 547 else if (s0 == 1 && x0 == 1 && aop0 == 3)
086134ec 548 OUTS (outf, " (SCO, ASL)");
4b7f6baa
CM		 549}
550
551static void
552searchmod (int r0, disassemble_info *outf)
553{
b7d48530
NC		 554 if (r0 == 0)
555 OUTS (outf, "GT");
556 else if (r0 == 1)
557 OUTS (outf, "GE");
558 else if (r0 == 2)
559 OUTS (outf, "LT");
560 else if (r0 == 3)
561 OUTS (outf, "LE");
4b7f6baa
CM		 562}
563
564static void
565aligndir (int r0, disassemble_info *outf)
566{
b7d48530 567 if (r0 == 1)
086134ec 568 OUTS (outf, " (R)");
4b7f6baa
CM		 569}
570
571static int
572decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
573{
528c6277 574 const char *s0, *s1;
4b7f6baa
CM		 575
576 if (h0)
577 s0 = dregs_hi (src0);
578 else
579 s0 = dregs_lo (src0);
580
581 if (h1)
582 s1 = dregs_hi (src1);
583 else
584 s1 = dregs_lo (src1);
585
586 OUTS (outf, s0);
587 OUTS (outf, " * ");
588 OUTS (outf, s1);
589 return 0;
590}
591
592static int
593decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
594{
528c6277
MF		 595 const char *a;
596 const char *sop = "<unknown op>";
4b7f6baa
CM		 597
598 if (which)
086134ec 599 a = "A1";
4b7f6baa 600 else
086134ec 601 a = "A0";
4b7f6baa
CM		 602
603 if (op == 3)
604 {
605 OUTS (outf, a);
606 return 0;
607 }
608
609 switch (op)
610 {
086134ec
BS		 611 case 0: sop = " = "; break;
612 case 1: sop = " += "; break;
613 case 2: sop = " -= "; break;
b7d48530 614 default: break;
4b7f6baa
CM		 615 }
616
617 OUTS (outf, a);
4b7f6baa 618 OUTS (outf, sop);
4b7f6baa
CM		 619 decode_multfunc (h0, h1, src0, src1, outf);
620
621 return 0;
622}
623
624static void
625decode_optmode (int mod, int MM, disassemble_info *outf)
626{
627 if (mod == 0 && MM == 0)
628 return;
629
630 OUTS (outf, " (");
631
632 if (MM && !mod)
633 {
634 OUTS (outf, "M)");
635 return;
636 }
637
638 if (MM)
639 OUTS (outf, "M, ");
b7d48530 640
4b7f6baa
CM		 641 if (mod == M_S2RND)
642 OUTS (outf, "S2RND");
643 else if (mod == M_T)
644 OUTS (outf, "T");
645 else if (mod == M_W32)
646 OUTS (outf, "W32");
647 else if (mod == M_FU)
648 OUTS (outf, "FU");
649 else if (mod == M_TFU)
650 OUTS (outf, "TFU");
651 else if (mod == M_IS)
652 OUTS (outf, "IS");
653 else if (mod == M_ISS2)
654 OUTS (outf, "ISS2");
655 else if (mod == M_IH)
656 OUTS (outf, "IH");
657 else if (mod == M_IU)
658 OUTS (outf, "IU");
659 else
660 abort ();
661
662 OUTS (outf, ")");
663}
b7d48530 664
b21c9cb4
BS		 665struct saved_state
666{
667 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
668 bu32 a0x, a0w, a1x, a1w;
669 bu32 lt[2], lc[2], lb[2];
670 int ac0, ac0_copy, ac1, an, aq;
671 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
672 int rnd_mod;
673 int v_internal;
674 bu32 pc, rets;
675
676 int ticks;
677 int insts;
678
679 int exception;
680
681 int end_of_registers;
682
683 int msize;
684 unsigned char *memory;
685 unsigned long bfd_mach;
686} saved_state;
687
688#define DREG(x) (saved_state.dpregs[x])
689#define GREG(x,i) DPREG ((x) | (i << 3))
690#define DPREG(x) (saved_state.dpregs[x])
691#define DREG(x) (saved_state.dpregs[x])
692#define PREG(x) (saved_state.dpregs[x + 8])
693#define SPREG PREG (6)
694#define FPREG PREG (7)
695#define IREG(x) (saved_state.iregs[x])
696#define MREG(x) (saved_state.mregs[x])
697#define BREG(x) (saved_state.bregs[x])
698#define LREG(x) (saved_state.lregs[x])
699#define A0XREG (saved_state.a0x)
700#define A0WREG (saved_state.a0w)
701#define A1XREG (saved_state.a1x)
702#define A1WREG (saved_state.a1w)
703#define CCREG (saved_state.cc)
704#define LC0REG (saved_state.lc[0])
705#define LT0REG (saved_state.lt[0])
706#define LB0REG (saved_state.lb[0])
707#define LC1REG (saved_state.lc[1])
708#define LT1REG (saved_state.lt[1])
709#define LB1REG (saved_state.lb[1])
710#define RETSREG (saved_state.rets)
711#define PCREG (saved_state.pc)
712
713static bu32 *
714get_allreg (int grp, int reg)
715{
716 int fullreg = (grp << 3) | reg;
717 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
718 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
719 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
720 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
721 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
722 , , , , , , , ,
723 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
724 REG_CYCLES2,
725 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
726 REG_LASTREG */
727 switch (fullreg >> 2)
728 {
729 case 0: case 1: return &DREG (reg); break;
730 case 2: case 3: return &PREG (reg); break;
731 case 4: return &IREG (reg & 3); break;
732 case 5: return &MREG (reg & 3); break;
733 case 6: return &BREG (reg & 3); break;
734 case 7: return &LREG (reg & 3); break;
735 default:
736 switch (fullreg)
086134ec
BS		 737 {
738 case 32: return &saved_state.a0x;
739 case 33: return &saved_state.a0w;
740 case 34: return &saved_state.a1x;
741 case 35: return &saved_state.a1w;
742 case 39: return &saved_state.rets;
743 case 48: return &LC0REG;
744 case 49: return &LT0REG;
745 case 50: return &LB0REG;
746 case 51: return &LC1REG;
747 case 52: return &LT1REG;
748 case 53: return &LB1REG;
749 }
b21c9cb4
BS		 750 return 0;
751 }
752}
753
4b7f6baa
CM		 754static int
755decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
756{
b7d48530
NC		 757 /* ProgCtrl
758 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
759 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
760 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 761 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
762 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
763
764 if (prgfunc == 0 && poprnd == 0)
b7d48530 765 OUTS (outf, "NOP");
219b747a
MF		 766 else if (parallel)
767 return 0;
4b7f6baa 768 else if (prgfunc == 1 && poprnd == 0)
b7d48530 769 OUTS (outf, "RTS");
4b7f6baa 770 else if (prgfunc == 1 && poprnd == 1)
b7d48530 771 OUTS (outf, "RTI");
4b7f6baa 772 else if (prgfunc == 1 && poprnd == 2)
b7d48530 773 OUTS (outf, "RTX");
4b7f6baa 774 else if (prgfunc == 1 && poprnd == 3)
b7d48530 775 OUTS (outf, "RTN");
4b7f6baa 776 else if (prgfunc == 1 && poprnd == 4)
b7d48530 777 OUTS (outf, "RTE");
4b7f6baa 778 else if (prgfunc == 2 && poprnd == 0)
b7d48530 779 OUTS (outf, "IDLE");
4b7f6baa 780 else if (prgfunc == 2 && poprnd == 3)
b7d48530 781 OUTS (outf, "CSYNC");
4b7f6baa 782 else if (prgfunc == 2 && poprnd == 4)
b7d48530 783 OUTS (outf, "SSYNC");
4b7f6baa 784 else if (prgfunc == 2 && poprnd == 5)
b7d48530 785 OUTS (outf, "EMUEXCPT");
50e2162a 786 else if (prgfunc == 3 && IS_DREG (0, poprnd))
4b7f6baa 787 {
086134ec 788 OUTS (outf, "CLI ");
4b7f6baa 789 OUTS (outf, dregs (poprnd));
4b7f6baa 790 }
50e2162a 791 else if (prgfunc == 4 && IS_DREG (0, poprnd))
4b7f6baa 792 {
086134ec 793 OUTS (outf, "STI ");
4b7f6baa 794 OUTS (outf, dregs (poprnd));
4b7f6baa 795 }
50e2162a 796 else if (prgfunc == 5 && IS_PREG (1, poprnd))
4b7f6baa 797 {
086134ec 798 OUTS (outf, "JUMP (");
4b7f6baa
CM		 799 OUTS (outf, pregs (poprnd));
800 OUTS (outf, ")");
4b7f6baa 801 }
50e2162a 802 else if (prgfunc == 6 && IS_PREG (1, poprnd))
4b7f6baa 803 {
086134ec 804 OUTS (outf, "CALL (");
4b7f6baa
CM		 805 OUTS (outf, pregs (poprnd));
806 OUTS (outf, ")");
4b7f6baa 807 }
50e2162a 808 else if (prgfunc == 7 && IS_PREG (1, poprnd))
4b7f6baa 809 {
086134ec 810 OUTS (outf, "CALL (PC + ");
4b7f6baa
CM		 811 OUTS (outf, pregs (poprnd));
812 OUTS (outf, ")");
4b7f6baa 813 }
50e2162a 814 else if (prgfunc == 8 && IS_PREG (1, poprnd))
4b7f6baa 815 {
086134ec 816 OUTS (outf, "JUMP (PC + ");
4b7f6baa
CM		 817 OUTS (outf, pregs (poprnd));
818 OUTS (outf, ")");
4b7f6baa
CM		 819 }
820 else if (prgfunc == 9)
821 {
086134ec 822 OUTS (outf, "RAISE ");
4b7f6baa 823 OUTS (outf, uimm4 (poprnd));
4b7f6baa
CM		 824 }
825 else if (prgfunc == 10)
826 {
086134ec 827 OUTS (outf, "EXCPT ");
4b7f6baa 828 OUTS (outf, uimm4 (poprnd));
4b7f6baa 829 }
219b747a 830 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
4b7f6baa 831 {
086134ec 832 OUTS (outf, "TESTSET (");
4b7f6baa
CM		 833 OUTS (outf, pregs (poprnd));
834 OUTS (outf, ")");
4b7f6baa
CM		 835 }
836 else
b7d48530
NC		 837 return 0;
838 return 2;
4b7f6baa
CM		 839}
840
841static int
842decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
843{
b7d48530
NC		 844 /* CaCTRL
845 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
846 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
847 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 848 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
849 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
850 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
851
219b747a
MF		 852 if (parallel)
853 return 0;
854
4b7f6baa
CM		 855 if (a == 0 && op == 0)
856 {
4b7f6baa
CM		 857 OUTS (outf, "PREFETCH[");
858 OUTS (outf, pregs (reg));
859 OUTS (outf, "]");
4b7f6baa
CM		 860 }
861 else if (a == 0 && op == 1)
862 {
4b7f6baa
CM		 863 OUTS (outf, "FLUSHINV[");
864 OUTS (outf, pregs (reg));
865 OUTS (outf, "]");
4b7f6baa
CM		 866 }
867 else if (a == 0 && op == 2)
868 {
4b7f6baa
CM		 869 OUTS (outf, "FLUSH[");
870 OUTS (outf, pregs (reg));
871 OUTS (outf, "]");
4b7f6baa
CM		 872 }
873 else if (a == 0 && op == 3)
874 {
4b7f6baa
CM		 875 OUTS (outf, "IFLUSH[");
876 OUTS (outf, pregs (reg));
877 OUTS (outf, "]");
4b7f6baa
CM		 878 }
879 else if (a == 1 && op == 0)
880 {
4b7f6baa
CM		 881 OUTS (outf, "PREFETCH[");
882 OUTS (outf, pregs (reg));
883 OUTS (outf, "++]");
4b7f6baa
CM		 884 }
885 else if (a == 1 && op == 1)
886 {
4b7f6baa
CM		 887 OUTS (outf, "FLUSHINV[");
888 OUTS (outf, pregs (reg));
889 OUTS (outf, "++]");
4b7f6baa
CM		 890 }
891 else if (a == 1 && op == 2)
892 {
4b7f6baa
CM		 893 OUTS (outf, "FLUSH[");
894 OUTS (outf, pregs (reg));
895 OUTS (outf, "++]");
4b7f6baa
CM		 896 }
897 else if (a == 1 && op == 3)
898 {
4b7f6baa
CM		 899 OUTS (outf, "IFLUSH[");
900 OUTS (outf, pregs (reg));
901 OUTS (outf, "++]");
4b7f6baa
CM		 902 }
903 else
b7d48530
NC		 904 return 0;
905 return 2;
4b7f6baa
CM		 906}
907
908static int
909decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
910{
b7d48530
NC		 911 /* PushPopReg
912 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
913 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
914 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 915 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
916 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
917 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
918
219b747a
MF		 919 if (parallel)
920 return 0;
921
50e2162a 922 if (W == 0 && mostreg (reg, grp))
4b7f6baa 923 {
4b7f6baa
CM		 924 OUTS (outf, allregs (reg, grp));
925 OUTS (outf, " = [SP++]");
4b7f6baa 926 }
219b747a 927 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
4b7f6baa 928 {
4b7f6baa
CM		 929 OUTS (outf, "[--SP] = ");
930 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 931 }
932 else
b7d48530
NC		 933 return 0;
934 return 2;
4b7f6baa
CM		 935}
936
937static int
938decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
939{
b7d48530
NC		 940 /* PushPopMultiple
941 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
942 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
943 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 944 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
945 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
946 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
947 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
948 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
4b7f6baa 949
219b747a
MF		 950 if (parallel)
951 return 0;
952
775f1cf0
MF		 953 if (pr > 5)
954 return 0;
955
4b7f6baa
CM		 956 if (W == 1 && d == 1 && p == 1)
957 {
4b7f6baa 958 OUTS (outf, "[--SP] = (R7:");
086134ec 959 OUTS (outf, imm5d (dr));
4b7f6baa 960 OUTS (outf, ", P5:");
086134ec 961 OUTS (outf, imm5d (pr));
4b7f6baa 962 OUTS (outf, ")");
4b7f6baa 963 }
219b747a 964 else if (W == 1 && d == 1 && p == 0 && pr == 0)
4b7f6baa 965 {
4b7f6baa 966 OUTS (outf, "[--SP] = (R7:");
086134ec 967 OUTS (outf, imm5d (dr));
4b7f6baa 968 OUTS (outf, ")");
4b7f6baa 969 }
219b747a 970 else if (W == 1 && d == 0 && p == 1 && dr == 0)
4b7f6baa 971 {
4b7f6baa 972 OUTS (outf, "[--SP] = (P5:");
086134ec 973 OUTS (outf, imm5d (pr));
4b7f6baa 974 OUTS (outf, ")");
4b7f6baa
CM		 975 }
976 else if (W == 0 && d == 1 && p == 1)
977 {
4b7f6baa 978 OUTS (outf, "(R7:");
086134ec 979 OUTS (outf, imm5d (dr));
4b7f6baa 980 OUTS (outf, ", P5:");
086134ec 981 OUTS (outf, imm5d (pr));
4b7f6baa 982 OUTS (outf, ") = [SP++]");
4b7f6baa 983 }
219b747a 984 else if (W == 0 && d == 1 && p == 0 && pr == 0)
4b7f6baa 985 {
4b7f6baa 986 OUTS (outf, "(R7:");
086134ec 987 OUTS (outf, imm5d (dr));
4b7f6baa 988 OUTS (outf, ") = [SP++]");
4b7f6baa 989 }
219b747a 990 else if (W == 0 && d == 0 && p == 1 && dr == 0)
4b7f6baa 991 {
4b7f6baa 992 OUTS (outf, "(P5:");
086134ec 993 OUTS (outf, imm5d (pr));
4b7f6baa 994 OUTS (outf, ") = [SP++]");
4b7f6baa
CM		 995 }
996 else
b7d48530
NC		 997 return 0;
998 return 2;
4b7f6baa
CM		 999}
1000
1001static int
1002decode_ccMV_0 (TIword iw0, disassemble_info *outf)
1003{
b7d48530
NC		 1004 /* ccMV
1005 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1006 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1007 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1008 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1009 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1010 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1011 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1012 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1013
219b747a
MF		 1014 if (parallel)
1015 return 0;
1016
4b7f6baa
CM		 1017 if (T == 1)
1018 {
4b7f6baa
CM		 1019 OUTS (outf, "IF CC ");
1020 OUTS (outf, gregs (dst, d));
1021 OUTS (outf, " = ");
1022 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1023 }
1024 else if (T == 0)
1025 {
086134ec 1026 OUTS (outf, "IF !CC ");
4b7f6baa
CM		 1027 OUTS (outf, gregs (dst, d));
1028 OUTS (outf, " = ");
1029 OUTS (outf, gregs (src, s));
4b7f6baa
CM		 1030 }
1031 else
b7d48530
NC		 1032 return 0;
1033 return 2;
4b7f6baa
CM		 1034}
1035
1036static int
1037decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1038{
b7d48530
NC		 1039 /* CCflag
1040 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1041 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1042 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1043 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1044 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1045 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1046 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1047 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1048
219b747a
MF		 1049 if (parallel)
1050 return 0;
1051
4b7f6baa
CM		 1052 if (opc == 0 && I == 0 && G == 0)
1053 {
086134ec 1054 OUTS (outf, "CC = ");
4b7f6baa 1055 OUTS (outf, dregs (x));
086134ec 1056 OUTS (outf, " == ");
4b7f6baa 1057 OUTS (outf, dregs (y));
4b7f6baa
CM		 1058 }
1059 else if (opc == 1 && I == 0 && G == 0)
1060 {
086134ec 1061 OUTS (outf, "CC = ");
4b7f6baa 1062 OUTS (outf, dregs (x));
086134ec 1063 OUTS (outf, " < ");
4b7f6baa 1064 OUTS (outf, dregs (y));
4b7f6baa
CM		 1065 }
1066 else if (opc == 2 && I == 0 && G == 0)
1067 {
086134ec 1068 OUTS (outf, "CC = ");
4b7f6baa 1069 OUTS (outf, dregs (x));
086134ec 1070 OUTS (outf, " <= ");
4b7f6baa 1071 OUTS (outf, dregs (y));
4b7f6baa
CM		 1072 }
1073 else if (opc == 3 && I == 0 && G == 0)
1074 {
086134ec 1075 OUTS (outf, "CC = ");
4b7f6baa 1076 OUTS (outf, dregs (x));
086134ec 1077 OUTS (outf, " < ");
4b7f6baa 1078 OUTS (outf, dregs (y));
086134ec 1079 OUTS (outf, " (IU)");
4b7f6baa
CM		 1080 }
1081 else if (opc == 4 && I == 0 && G == 0)
1082 {
086134ec 1083 OUTS (outf, "CC = ");
4b7f6baa 1084 OUTS (outf, dregs (x));
086134ec 1085 OUTS (outf, " <= ");
4b7f6baa 1086 OUTS (outf, dregs (y));
086134ec 1087 OUTS (outf, " (IU)");
4b7f6baa
CM		 1088 }
1089 else if (opc == 0 && I == 1 && G == 0)
1090 {
086134ec 1091 OUTS (outf, "CC = ");
4b7f6baa 1092 OUTS (outf, dregs (x));
086134ec 1093 OUTS (outf, " == ");
4b7f6baa 1094 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1095 }
1096 else if (opc == 1 && I == 1 && G == 0)
1097 {
086134ec 1098 OUTS (outf, "CC = ");
4b7f6baa 1099 OUTS (outf, dregs (x));
086134ec 1100 OUTS (outf, " < ");
4b7f6baa 1101 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1102 }
1103 else if (opc == 2 && I == 1 && G == 0)
1104 {
086134ec 1105 OUTS (outf, "CC = ");
4b7f6baa 1106 OUTS (outf, dregs (x));
086134ec 1107 OUTS (outf, " <= ");
4b7f6baa 1108 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1109 }
1110 else if (opc == 3 && I == 1 && G == 0)
1111 {
086134ec 1112 OUTS (outf, "CC = ");
4b7f6baa 1113 OUTS (outf, dregs (x));
086134ec 1114 OUTS (outf, " < ");
4b7f6baa 1115 OUTS (outf, uimm3 (y));
086134ec 1116 OUTS (outf, " (IU)");
4b7f6baa
CM		 1117 }
1118 else if (opc == 4 && I == 1 && G == 0)
1119 {
086134ec 1120 OUTS (outf, "CC = ");
4b7f6baa 1121 OUTS (outf, dregs (x));
086134ec 1122 OUTS (outf, " <= ");
4b7f6baa 1123 OUTS (outf, uimm3 (y));
086134ec 1124 OUTS (outf, " (IU)");
4b7f6baa
CM		 1125 }
1126 else if (opc == 0 && I == 0 && G == 1)
1127 {
086134ec 1128 OUTS (outf, "CC = ");
4b7f6baa 1129 OUTS (outf, pregs (x));
086134ec 1130 OUTS (outf, " == ");
4b7f6baa 1131 OUTS (outf, pregs (y));
4b7f6baa
CM		 1132 }
1133 else if (opc == 1 && I == 0 && G == 1)
1134 {
086134ec 1135 OUTS (outf, "CC = ");
4b7f6baa 1136 OUTS (outf, pregs (x));
086134ec 1137 OUTS (outf, " < ");
4b7f6baa 1138 OUTS (outf, pregs (y));
4b7f6baa
CM		 1139 }
1140 else if (opc == 2 && I == 0 && G == 1)
1141 {
086134ec 1142 OUTS (outf, "CC = ");
4b7f6baa 1143 OUTS (outf, pregs (x));
086134ec 1144 OUTS (outf, " <= ");
4b7f6baa 1145 OUTS (outf, pregs (y));
4b7f6baa
CM		 1146 }
1147 else if (opc == 3 && I == 0 && G == 1)
1148 {
086134ec 1149 OUTS (outf, "CC = ");
4b7f6baa 1150 OUTS (outf, pregs (x));
086134ec 1151 OUTS (outf, " < ");
4b7f6baa 1152 OUTS (outf, pregs (y));
086134ec 1153 OUTS (outf, " (IU)");
4b7f6baa
CM		 1154 }
1155 else if (opc == 4 && I == 0 && G == 1)
1156 {
086134ec 1157 OUTS (outf, "CC = ");
4b7f6baa 1158 OUTS (outf, pregs (x));
086134ec 1159 OUTS (outf, " <= ");
4b7f6baa 1160 OUTS (outf, pregs (y));
086134ec 1161 OUTS (outf, " (IU)");
4b7f6baa
CM		 1162 }
1163 else if (opc == 0 && I == 1 && G == 1)
1164 {
086134ec 1165 OUTS (outf, "CC = ");
4b7f6baa 1166 OUTS (outf, pregs (x));
086134ec 1167 OUTS (outf, " == ");
4b7f6baa 1168 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1169 }
1170 else if (opc == 1 && I == 1 && G == 1)
1171 {
086134ec 1172 OUTS (outf, "CC = ");
4b7f6baa 1173 OUTS (outf, pregs (x));
086134ec 1174 OUTS (outf, " < ");
4b7f6baa 1175 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1176 }
1177 else if (opc == 2 && I == 1 && G == 1)
1178 {
086134ec 1179 OUTS (outf, "CC = ");
4b7f6baa 1180 OUTS (outf, pregs (x));
086134ec 1181 OUTS (outf, " <= ");
4b7f6baa 1182 OUTS (outf, imm3 (y));
4b7f6baa
CM		 1183 }
1184 else if (opc == 3 && I == 1 && G == 1)
1185 {
086134ec 1186 OUTS (outf, "CC = ");
4b7f6baa 1187 OUTS (outf, pregs (x));
086134ec 1188 OUTS (outf, " < ");
4b7f6baa 1189 OUTS (outf, uimm3 (y));
086134ec 1190 OUTS (outf, " (IU)");
4b7f6baa
CM		 1191 }
1192 else if (opc == 4 && I == 1 && G == 1)
1193 {
086134ec 1194 OUTS (outf, "CC = ");
4b7f6baa 1195 OUTS (outf, pregs (x));
086134ec 1196 OUTS (outf, " <= ");
4b7f6baa 1197 OUTS (outf, uimm3 (y));
086134ec 1198 OUTS (outf, " (IU)");
4b7f6baa 1199 }
219b747a 1200 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1201 OUTS (outf, "CC = A0 == A1");
b7d48530 1202
219b747a 1203 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1204 OUTS (outf, "CC = A0 < A1");
b7d48530 1205
219b747a 1206 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
086134ec 1207 OUTS (outf, "CC = A0 <= A1");
b7d48530 1208
4b7f6baa 1209 else
b7d48530
NC		 1210 return 0;
1211 return 2;
4b7f6baa
CM		 1212}
1213
1214static int
1215decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1216{
b7d48530
NC		 1217 /* CC2dreg
1218 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1219 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1220 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1221 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1222 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1223
219b747a
MF		 1224 if (parallel)
1225 return 0;
1226
4b7f6baa
CM		 1227 if (op == 0)
1228 {
4b7f6baa 1229 OUTS (outf, dregs (reg));
086134ec 1230 OUTS (outf, " = CC");
4b7f6baa
CM		 1231 }
1232 else if (op == 1)
1233 {
086134ec 1234 OUTS (outf, "CC = ");
4b7f6baa 1235 OUTS (outf, dregs (reg));
4b7f6baa 1236 }
50e2162a 1237 else if (op == 3 && reg == 0)
086134ec 1238 OUTS (outf, "CC = !CC");
4b7f6baa 1239 else
b7d48530
NC		 1240 return 0;
1241
1242 return 2;
4b7f6baa
CM		 1243}
1244
1245static int
1246decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1247{
b7d48530
NC		 1248 /* CC2stat
1249 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1250 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1251 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1252 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1253 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1254 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1255
b2459327 1256 const char *bitname = statbits (cbit);
219b747a
MF		 1257
1258 if (parallel)
1259 return 0;
1260
b2459327
MF		 1261 if (decode_statbits[cbit] == REG_LASTREG)
1262 {
1263 /* All ASTAT bits except CC may be operated on in hardware, but may
1264 not have a dedicated insn, so still decode "valid" insns. */
1265 static char bitnames[64];
1266 if (cbit != 5)
1267 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1268 else
219b747a
MF		 1269 return 0;
1270
b2459327
MF		 1271 bitname = bitnames;
1272 }
1273
4b7f6baa
CM		 1274 if (op == 0 && D == 0)
1275 {
4b7f6baa 1276 OUTS (outf, "CC = ");
b2459327 1277 OUTS (outf, bitname);
4b7f6baa
CM		 1278 }
1279 else if (op == 1 && D == 0)
1280 {
086134ec 1281 OUTS (outf, "CC |= ");
b2459327 1282 OUTS (outf, bitname);
4b7f6baa
CM		 1283 }
1284 else if (op == 2 && D == 0)
1285 {
086134ec 1286 OUTS (outf, "CC &= ");
b2459327 1287 OUTS (outf, bitname);
4b7f6baa
CM		 1288 }
1289 else if (op == 3 && D == 0)
1290 {
086134ec 1291 OUTS (outf, "CC ^= ");
b2459327 1292 OUTS (outf, bitname);
4b7f6baa
CM		 1293 }
1294 else if (op == 0 && D == 1)
1295 {
b2459327 1296 OUTS (outf, bitname);
086134ec 1297 OUTS (outf, " = CC");
4b7f6baa
CM		 1298 }
1299 else if (op == 1 && D == 1)
1300 {
b2459327 1301 OUTS (outf, bitname);
086134ec 1302 OUTS (outf, " |= CC");
4b7f6baa
CM		 1303 }
1304 else if (op == 2 && D == 1)
1305 {
b2459327 1306 OUTS (outf, bitname);
086134ec 1307 OUTS (outf, " &= CC");
4b7f6baa
CM		 1308 }
1309 else if (op == 3 && D == 1)
1310 {
b2459327 1311 OUTS (outf, bitname);
086134ec 1312 OUTS (outf, " ^= CC");
4b7f6baa
CM		 1313 }
1314 else
b7d48530
NC		 1315 return 0;
1316
1317 return 2;
4b7f6baa
CM		 1318}
1319
1320static int
1321decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1322{
b7d48530
NC		 1323 /* BRCC
1324 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1325 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1326 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1327 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1328 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1329 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1330
219b747a
MF		 1331 if (parallel)
1332 return 0;
1333
4b7f6baa
CM		 1334 if (T == 1 && B == 1)
1335 {
086134ec 1336 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1337 OUTS (outf, pcrel10 (offset));
086134ec 1338 OUTS (outf, " (BP)");
4b7f6baa
CM		 1339 }
1340 else if (T == 0 && B == 1)
1341 {
086134ec 1342 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1343 OUTS (outf, pcrel10 (offset));
086134ec 1344 OUTS (outf, " (BP)");
4b7f6baa
CM		 1345 }
1346 else if (T == 1)
1347 {
086134ec 1348 OUTS (outf, "IF CC JUMP 0x");
4b7f6baa 1349 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1350 }
1351 else if (T == 0)
1352 {
086134ec 1353 OUTS (outf, "IF !CC JUMP 0x");
4b7f6baa 1354 OUTS (outf, pcrel10 (offset));
4b7f6baa
CM		 1355 }
1356 else
b7d48530
NC		 1357 return 0;
1358
1359 return 2;
4b7f6baa
CM		 1360}
1361
1362static int
1363decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1364{
b7d48530
NC		 1365 /* UJUMP
1366 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1367 | 0 | 0 | 1 | 0 |.offset........................................|
1368 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1369 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1370
219b747a
MF		 1371 if (parallel)
1372 return 0;
1373
086134ec 1374 OUTS (outf, "JUMP.S 0x");
4b7f6baa 1375 OUTS (outf, pcrel12 (offset));
b7d48530 1376 return 2;
4b7f6baa
CM		 1377}
1378
1379static int
1380decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1381{
b7d48530
NC		 1382 /* REGMV
1383 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1384 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1385 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1386 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1387 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1388 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1389 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1390
35fc57f3
MF		 1391 /* Reserved slots cannot be a src/dst. */
1392 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1393 goto invalid_move;
1394
1395 /* Standard register moves */
1396 if ((gs < 2) || /* Dregs/Pregs as source */
1397 (gd < 2) || /* Dregs/Pregs as dest */
1398 (gs == 4 && src < 4) || /* Accumulators as source */
1399 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1400 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1401 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1402 goto valid_move;
1403
1404 /* dareg = dareg (IMBL) */
1405 if (gs < 4 && gd < 4)
1406 goto valid_move;
1407
1408 /* USP can be src to sysregs, but not dagregs. */
1409 if ((gs == 7 && src == 0) && (gd >= 4))
1410 goto valid_move;
1411
1412 /* USP can move between genregs (only check Accumulators). */
1413 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1414 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1415 goto valid_move;
1416
1417 /* Still here ? Invalid reg pair. */
1418 invalid_move:
1419 return 0;
c958a8a8 1420
35fc57f3 1421 valid_move:
4b7f6baa 1422 OUTS (outf, allregs (dst, gd));
086134ec 1423 OUTS (outf, " = ");
4b7f6baa 1424 OUTS (outf, allregs (src, gs));
b7d48530 1425 return 2;
4b7f6baa
CM		 1426}
1427
1428static int
1429decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1430{
b7d48530
NC		 1431 /* ALU2op
1432 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1433 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1434 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1435 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1436 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1437 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1438
1439 if (opc == 0)
1440 {
4b7f6baa 1441 OUTS (outf, dregs (dst));
086134ec 1442 OUTS (outf, " >>>= ");
4b7f6baa 1443 OUTS (outf, dregs (src));
4b7f6baa
CM		 1444 }
1445 else if (opc == 1)
1446 {
4b7f6baa 1447 OUTS (outf, dregs (dst));
086134ec 1448 OUTS (outf, " >>= ");
4b7f6baa 1449 OUTS (outf, dregs (src));
4b7f6baa
CM		 1450 }
1451 else if (opc == 2)
1452 {
4b7f6baa 1453 OUTS (outf, dregs (dst));
086134ec 1454 OUTS (outf, " <<= ");
4b7f6baa 1455 OUTS (outf, dregs (src));
4b7f6baa
CM		 1456 }
1457 else if (opc == 3)
1458 {
4b7f6baa 1459 OUTS (outf, dregs (dst));
086134ec 1460 OUTS (outf, " *= ");
4b7f6baa 1461 OUTS (outf, dregs (src));
4b7f6baa
CM		 1462 }
1463 else if (opc == 4)
1464 {
4b7f6baa 1465 OUTS (outf, dregs (dst));
086134ec 1466 OUTS (outf, " = (");
4b7f6baa 1467 OUTS (outf, dregs (dst));
086134ec 1468 OUTS (outf, " + ");
4b7f6baa 1469 OUTS (outf, dregs (src));
086134ec 1470 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1471 }
1472 else if (opc == 5)
1473 {
4b7f6baa 1474 OUTS (outf, dregs (dst));
086134ec 1475 OUTS (outf, " = (");
4b7f6baa 1476 OUTS (outf, dregs (dst));
086134ec 1477 OUTS (outf, " + ");
4b7f6baa 1478 OUTS (outf, dregs (src));
086134ec 1479 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1480 }
1481 else if (opc == 8)
1482 {
086134ec 1483 OUTS (outf, "DIVQ (");
4b7f6baa 1484 OUTS (outf, dregs (dst));
086134ec 1485 OUTS (outf, ", ");
4b7f6baa
CM		 1486 OUTS (outf, dregs (src));
1487 OUTS (outf, ")");
4b7f6baa
CM		 1488 }
1489 else if (opc == 9)
1490 {
086134ec 1491 OUTS (outf, "DIVS (");
4b7f6baa 1492 OUTS (outf, dregs (dst));
086134ec 1493 OUTS (outf, ", ");
4b7f6baa
CM		 1494 OUTS (outf, dregs (src));
1495 OUTS (outf, ")");
4b7f6baa
CM		 1496 }
1497 else if (opc == 10)
1498 {
4b7f6baa 1499 OUTS (outf, dregs (dst));
086134ec 1500 OUTS (outf, " = ");
4b7f6baa 1501 OUTS (outf, dregs_lo (src));
086134ec 1502 OUTS (outf, " (X)");
4b7f6baa
CM		 1503 }
1504 else if (opc == 11)
1505 {
4b7f6baa 1506 OUTS (outf, dregs (dst));
086134ec 1507 OUTS (outf, " = ");
4b7f6baa 1508 OUTS (outf, dregs_lo (src));
086134ec 1509 OUTS (outf, " (Z)");
4b7f6baa
CM		 1510 }
1511 else if (opc == 12)
1512 {
4b7f6baa 1513 OUTS (outf, dregs (dst));
086134ec 1514 OUTS (outf, " = ");
4b7f6baa 1515 OUTS (outf, dregs_byte (src));
086134ec 1516 OUTS (outf, " (X)");
4b7f6baa
CM		 1517 }
1518 else if (opc == 13)
1519 {
4b7f6baa 1520 OUTS (outf, dregs (dst));
086134ec 1521 OUTS (outf, " = ");
4b7f6baa 1522 OUTS (outf, dregs_byte (src));
086134ec 1523 OUTS (outf, " (Z)");
4b7f6baa
CM		 1524 }
1525 else if (opc == 14)
1526 {
4b7f6baa 1527 OUTS (outf, dregs (dst));
086134ec 1528 OUTS (outf, " = -");
4b7f6baa 1529 OUTS (outf, dregs (src));
4b7f6baa
CM		 1530 }
1531 else if (opc == 15)
1532 {
4b7f6baa 1533 OUTS (outf, dregs (dst));
086134ec 1534 OUTS (outf, " =~ ");
4b7f6baa 1535 OUTS (outf, dregs (src));
4b7f6baa
CM		 1536 }
1537 else
b7d48530
NC		 1538 return 0;
1539
1540 return 2;
4b7f6baa
CM		 1541}
1542
1543static int
1544decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1545{
b7d48530
NC		 1546 /* PTR2op
1547 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1548 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1549 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1550 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1551 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1552 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1553
1554 if (opc == 0)
1555 {
4b7f6baa 1556 OUTS (outf, pregs (dst));
086134ec 1557 OUTS (outf, " -= ");
4b7f6baa 1558 OUTS (outf, pregs (src));
4b7f6baa
CM		 1559 }
1560 else if (opc == 1)
1561 {
4b7f6baa 1562 OUTS (outf, pregs (dst));
086134ec 1563 OUTS (outf, " = ");
4b7f6baa 1564 OUTS (outf, pregs (src));
086134ec 1565 OUTS (outf, " << 0x2");
4b7f6baa
CM		 1566 }
1567 else if (opc == 3)
1568 {
4b7f6baa 1569 OUTS (outf, pregs (dst));
086134ec 1570 OUTS (outf, " = ");
4b7f6baa 1571 OUTS (outf, pregs (src));
086134ec 1572 OUTS (outf, " >> 0x2");
4b7f6baa
CM		 1573 }
1574 else if (opc == 4)
1575 {
4b7f6baa 1576 OUTS (outf, pregs (dst));
086134ec 1577 OUTS (outf, " = ");
4b7f6baa 1578 OUTS (outf, pregs (src));
086134ec 1579 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 1580 }
1581 else if (opc == 5)
1582 {
4b7f6baa 1583 OUTS (outf, pregs (dst));
086134ec 1584 OUTS (outf, " += ");
4b7f6baa 1585 OUTS (outf, pregs (src));
086134ec 1586 OUTS (outf, " (BREV)");
4b7f6baa
CM		 1587 }
1588 else if (opc == 6)
1589 {
4b7f6baa 1590 OUTS (outf, pregs (dst));
086134ec 1591 OUTS (outf, " = (");
4b7f6baa 1592 OUTS (outf, pregs (dst));
086134ec 1593 OUTS (outf, " + ");
4b7f6baa 1594 OUTS (outf, pregs (src));
086134ec 1595 OUTS (outf, ") << 0x1");
4b7f6baa
CM		 1596 }
1597 else if (opc == 7)
1598 {
4b7f6baa 1599 OUTS (outf, pregs (dst));
086134ec 1600 OUTS (outf, " = (");
4b7f6baa 1601 OUTS (outf, pregs (dst));
086134ec 1602 OUTS (outf, " + ");
4b7f6baa 1603 OUTS (outf, pregs (src));
086134ec 1604 OUTS (outf, ") << 0x2");
4b7f6baa
CM		 1605 }
1606 else
b7d48530
NC		 1607 return 0;
1608
1609 return 2;
4b7f6baa
CM		 1610}
1611
1612static int
1613decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1614{
b7d48530
NC		 1615 /* LOGI2op
1616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1617 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1618 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1619 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1620 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1621 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1622
219b747a
MF		 1623 if (parallel)
1624 return 0;
1625
4b7f6baa
CM		 1626 if (opc == 0)
1627 {
086134ec 1628 OUTS (outf, "CC = !BITTST (");
4b7f6baa 1629 OUTS (outf, dregs (dst));
086134ec 1630 OUTS (outf, ", ");
4b7f6baa 1631 OUTS (outf, uimm5 (src));
086134ec
BS		 1632 OUTS (outf, ");\t\t/* bit");
1633 OUTS (outf, imm7d (src));
1634 OUTS (outf, " */");
1635 comment = 1;
4b7f6baa
CM		 1636 }
1637 else if (opc == 1)
1638 {
4b7f6baa
CM		 1639 OUTS (outf, "CC = BITTST (");
1640 OUTS (outf, dregs (dst));
086134ec 1641 OUTS (outf, ", ");
4b7f6baa 1642 OUTS (outf, uimm5 (src));
086134ec
BS		 1643 OUTS (outf, ");\t\t/* bit");
1644 OUTS (outf, imm7d (src));
1645 OUTS (outf, " */");
1646 comment = 1;
4b7f6baa
CM		 1647 }
1648 else if (opc == 2)
1649 {
4b7f6baa
CM		 1650 OUTS (outf, "BITSET (");
1651 OUTS (outf, dregs (dst));
086134ec 1652 OUTS (outf, ", ");
4b7f6baa 1653 OUTS (outf, uimm5 (src));
086134ec
BS		 1654 OUTS (outf, ");\t\t/* bit");
1655 OUTS (outf, imm7d (src));
1656 OUTS (outf, " */");
1657 comment = 1;
4b7f6baa
CM		 1658 }
1659 else if (opc == 3)
1660 {
4b7f6baa
CM		 1661 OUTS (outf, "BITTGL (");
1662 OUTS (outf, dregs (dst));
086134ec 1663 OUTS (outf, ", ");
4b7f6baa 1664 OUTS (outf, uimm5 (src));
086134ec
BS		 1665 OUTS (outf, ");\t\t/* bit");
1666 OUTS (outf, imm7d (src));
1667 OUTS (outf, " */");
1668 comment = 1;
4b7f6baa
CM		 1669 }
1670 else if (opc == 4)
1671 {
4b7f6baa
CM		 1672 OUTS (outf, "BITCLR (");
1673 OUTS (outf, dregs (dst));
086134ec 1674 OUTS (outf, ", ");
4b7f6baa 1675 OUTS (outf, uimm5 (src));
086134ec
BS		 1676 OUTS (outf, ");\t\t/* bit");
1677 OUTS (outf, imm7d (src));
1678 OUTS (outf, " */");
1679 comment = 1;
4b7f6baa
CM		 1680 }
1681 else if (opc == 5)
1682 {
4b7f6baa 1683 OUTS (outf, dregs (dst));
086134ec 1684 OUTS (outf, " >>>= ");
4b7f6baa 1685 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1686 }
1687 else if (opc == 6)
1688 {
4b7f6baa 1689 OUTS (outf, dregs (dst));
086134ec 1690 OUTS (outf, " >>= ");
4b7f6baa 1691 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1692 }
1693 else if (opc == 7)
1694 {
4b7f6baa 1695 OUTS (outf, dregs (dst));
086134ec 1696 OUTS (outf, " <<= ");
4b7f6baa 1697 OUTS (outf, uimm5 (src));
4b7f6baa
CM		 1698 }
1699 else
b7d48530
NC		 1700 return 0;
1701
1702 return 2;
4b7f6baa
CM		 1703}
1704
1705static int
1706decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1707{
b7d48530
NC		 1708 /* COMP3op
1709 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1710 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1711 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1712 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1713 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1714 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1715 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1716
1717 if (opc == 5 && src1 == src0)
1718 {
4b7f6baa 1719 OUTS (outf, pregs (dst));
086134ec 1720 OUTS (outf, " = ");
4b7f6baa 1721 OUTS (outf, pregs (src0));
086134ec 1722 OUTS (outf, " << 0x1");
4b7f6baa
CM		 1723 }
1724 else if (opc == 1)
1725 {
4b7f6baa 1726 OUTS (outf, dregs (dst));
086134ec 1727 OUTS (outf, " = ");
4b7f6baa 1728 OUTS (outf, dregs (src0));
086134ec 1729 OUTS (outf, " - ");
4b7f6baa 1730 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1731 }
1732 else if (opc == 2)
1733 {
4b7f6baa 1734 OUTS (outf, dregs (dst));
086134ec 1735 OUTS (outf, " = ");
4b7f6baa 1736 OUTS (outf, dregs (src0));
086134ec 1737 OUTS (outf, " & ");
4b7f6baa 1738 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1739 }
1740 else if (opc == 3)
1741 {
4b7f6baa 1742 OUTS (outf, dregs (dst));
086134ec 1743 OUTS (outf, " = ");
4b7f6baa 1744 OUTS (outf, dregs (src0));
086134ec 1745 OUTS (outf, " | ");
4b7f6baa 1746 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1747 }
1748 else if (opc == 4)
1749 {
4b7f6baa 1750 OUTS (outf, dregs (dst));
086134ec 1751 OUTS (outf, " = ");
4b7f6baa 1752 OUTS (outf, dregs (src0));
086134ec 1753 OUTS (outf, " ^ ");
4b7f6baa 1754 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1755 }
1756 else if (opc == 5)
1757 {
4b7f6baa 1758 OUTS (outf, pregs (dst));
086134ec 1759 OUTS (outf, " = ");
4b7f6baa 1760 OUTS (outf, pregs (src0));
086134ec 1761 OUTS (outf, " + ");
4b7f6baa 1762 OUTS (outf, pregs (src1));
4b7f6baa
CM		 1763 }
1764 else if (opc == 6)
1765 {
4b7f6baa 1766 OUTS (outf, pregs (dst));
086134ec 1767 OUTS (outf, " = ");
4b7f6baa 1768 OUTS (outf, pregs (src0));
086134ec 1769 OUTS (outf, " + (");
4b7f6baa 1770 OUTS (outf, pregs (src1));
086134ec 1771 OUTS (outf, " << 0x1)");
4b7f6baa
CM		 1772 }
1773 else if (opc == 7)
1774 {
4b7f6baa 1775 OUTS (outf, pregs (dst));
086134ec 1776 OUTS (outf, " = ");
4b7f6baa 1777 OUTS (outf, pregs (src0));
086134ec 1778 OUTS (outf, " + (");
4b7f6baa 1779 OUTS (outf, pregs (src1));
086134ec 1780 OUTS (outf, " << 0x2)");
4b7f6baa
CM		 1781 }
1782 else if (opc == 0)
1783 {
4b7f6baa 1784 OUTS (outf, dregs (dst));
086134ec 1785 OUTS (outf, " = ");
4b7f6baa 1786 OUTS (outf, dregs (src0));
086134ec 1787 OUTS (outf, " + ");
4b7f6baa 1788 OUTS (outf, dregs (src1));
4b7f6baa
CM		 1789 }
1790 else
b7d48530
NC		 1791 return 0;
1792
1793 return 2;
4b7f6baa
CM		 1794}
1795
1796static int
1797decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1798{
b7d48530
NC		 1799 /* COMPI2opD
1800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1801 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1802 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1803 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1804 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1805 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1806
086134ec
BS		 1807 bu32 *pval = get_allreg (0, dst);
1808
219b747a
MF		 1809 if (parallel)
1810 return 0;
1811
086134ec
BS		 1812 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1813 to combine them, so it prints out the right values.
1814 Here we keep track of the registers. */
1815 if (op == 0)
1816 {
1817 *pval = imm7_val (src);
1818 if (src & 0x40)
1819 *pval |= 0xFFFFFF80;
1820 else
1821 *pval &= 0x7F;
1822 }
1823
4b7f6baa
CM		 1824 if (op == 0)
1825 {
4b7f6baa 1826 OUTS (outf, dregs (dst));
086134ec 1827 OUTS (outf, " = ");
4b7f6baa 1828 OUTS (outf, imm7 (src));
086134ec
BS		 1829 OUTS (outf, " (X);\t\t/*\t\t");
1830 OUTS (outf, dregs (dst));
1831 OUTS (outf, "=");
1832 OUTS (outf, uimm32 (*pval));
1833 OUTS (outf, "(");
1834 OUTS (outf, imm32 (*pval));
1835 OUTS (outf, ") */");
1836 comment = 1;
4b7f6baa
CM		 1837 }
1838 else if (op == 1)
1839 {
4b7f6baa 1840 OUTS (outf, dregs (dst));
086134ec 1841 OUTS (outf, " += ");
4b7f6baa 1842 OUTS (outf, imm7 (src));
086134ec
BS		 1843 OUTS (outf, ";\t\t/* (");
1844 OUTS (outf, imm7d (src));
1845 OUTS (outf, ") */");
1846 comment = 1;
4b7f6baa
CM		 1847 }
1848 else
b7d48530
NC		 1849 return 0;
1850
1851 return 2;
4b7f6baa
CM		 1852}
1853
1854static int
1855decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1856{
b7d48530
NC		 1857 /* COMPI2opP
1858 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1859 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1860 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1861 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1862 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1863 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1864
086134ec
BS		 1865 bu32 *pval = get_allreg (1, dst);
1866
219b747a
MF		 1867 if (parallel)
1868 return 0;
1869
086134ec
BS		 1870 if (op == 0)
1871 {
1872 *pval = imm7_val (src);
1873 if (src & 0x40)
1874 *pval |= 0xFFFFFF80;
1875 else
1876 *pval &= 0x7F;
1877 }
1878
4b7f6baa
CM		 1879 if (op == 0)
1880 {
4b7f6baa 1881 OUTS (outf, pregs (dst));
086134ec 1882 OUTS (outf, " = ");
4b7f6baa 1883 OUTS (outf, imm7 (src));
086134ec
BS		 1884 OUTS (outf, " (X);\t\t/*\t\t");
1885 OUTS (outf, pregs (dst));
1886 OUTS (outf, "=");
1887 OUTS (outf, uimm32 (*pval));
1888 OUTS (outf, "(");
1889 OUTS (outf, imm32 (*pval));
1890 OUTS (outf, ") */");
1891 comment = 1;
4b7f6baa
CM		 1892 }
1893 else if (op == 1)
1894 {
4b7f6baa 1895 OUTS (outf, pregs (dst));
086134ec 1896 OUTS (outf, " += ");
4b7f6baa 1897 OUTS (outf, imm7 (src));
086134ec
BS		 1898 OUTS (outf, ";\t\t/* (");
1899 OUTS (outf, imm7d (src));
1900 OUTS (outf, ") */");
1901 comment = 1;
4b7f6baa
CM		 1902 }
1903 else
b7d48530
NC		 1904 return 0;
1905
1906 return 2;
4b7f6baa
CM		 1907}
1908
1909static int
1910decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1911{
b7d48530
NC		 1912 /* LDSTpmod
1913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1914 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1915 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 1916 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1917 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1918 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1919 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1920 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1921
1922 if (aop == 1 && W == 0 && idx == ptr)
1923 {
4b7f6baa 1924 OUTS (outf, dregs_lo (reg));
086134ec 1925 OUTS (outf, " = W[");
4b7f6baa
CM		 1926 OUTS (outf, pregs (ptr));
1927 OUTS (outf, "]");
4b7f6baa
CM		 1928 }
1929 else if (aop == 2 && W == 0 && idx == ptr)
1930 {
4b7f6baa 1931 OUTS (outf, dregs_hi (reg));
086134ec 1932 OUTS (outf, " = W[");
4b7f6baa
CM		 1933 OUTS (outf, pregs (ptr));
1934 OUTS (outf, "]");
4b7f6baa
CM		 1935 }
1936 else if (aop == 1 && W == 1 && idx == ptr)
1937 {
4b7f6baa
CM		 1938 OUTS (outf, "W[");
1939 OUTS (outf, pregs (ptr));
086134ec 1940 OUTS (outf, "] = ");
4b7f6baa 1941 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 1942 }
1943 else if (aop == 2 && W == 1 && idx == ptr)
1944 {
4b7f6baa
CM		 1945 OUTS (outf, "W[");
1946 OUTS (outf, pregs (ptr));
086134ec 1947 OUTS (outf, "] = ");
4b7f6baa 1948 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 1949 }
1950 else if (aop == 0 && W == 0)
1951 {
4b7f6baa 1952 OUTS (outf, dregs (reg));
086134ec 1953 OUTS (outf, " = [");
4b7f6baa 1954 OUTS (outf, pregs (ptr));
086134ec 1955 OUTS (outf, " ++ ");
4b7f6baa
CM		 1956 OUTS (outf, pregs (idx));
1957 OUTS (outf, "]");
4b7f6baa
CM		 1958 }
1959 else if (aop == 1 && W == 0)
1960 {
4b7f6baa 1961 OUTS (outf, dregs_lo (reg));
086134ec 1962 OUTS (outf, " = W[");
4b7f6baa 1963 OUTS (outf, pregs (ptr));
086134ec 1964 OUTS (outf, " ++ ");
4b7f6baa
CM		 1965 OUTS (outf, pregs (idx));
1966 OUTS (outf, "]");
4b7f6baa
CM		 1967 }
1968 else if (aop == 2 && W == 0)
1969 {
4b7f6baa 1970 OUTS (outf, dregs_hi (reg));
086134ec 1971 OUTS (outf, " = W[");
4b7f6baa 1972 OUTS (outf, pregs (ptr));
086134ec 1973 OUTS (outf, " ++ ");
4b7f6baa
CM		 1974 OUTS (outf, pregs (idx));
1975 OUTS (outf, "]");
4b7f6baa
CM		 1976 }
1977 else if (aop == 3 && W == 0)
1978 {
4b7f6baa 1979 OUTS (outf, dregs (reg));
086134ec 1980 OUTS (outf, " = W[");
4b7f6baa 1981 OUTS (outf, pregs (ptr));
086134ec 1982 OUTS (outf, " ++ ");
4b7f6baa
CM		 1983 OUTS (outf, pregs (idx));
1984 OUTS (outf, "] (Z)");
4b7f6baa
CM		 1985 }
1986 else if (aop == 3 && W == 1)
1987 {
4b7f6baa 1988 OUTS (outf, dregs (reg));
086134ec 1989 OUTS (outf, " = W[");
4b7f6baa 1990 OUTS (outf, pregs (ptr));
086134ec 1991 OUTS (outf, " ++ ");
4b7f6baa 1992 OUTS (outf, pregs (idx));
086134ec 1993 OUTS (outf, "] (X)");
4b7f6baa
CM		 1994 }
1995 else if (aop == 0 && W == 1)
1996 {
4b7f6baa
CM		 1997 OUTS (outf, "[");
1998 OUTS (outf, pregs (ptr));
086134ec 1999 OUTS (outf, " ++ ");
4b7f6baa 2000 OUTS (outf, pregs (idx));
086134ec 2001 OUTS (outf, "] = ");
4b7f6baa 2002 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2003 }
2004 else if (aop == 1 && W == 1)
2005 {
4b7f6baa
CM		 2006 OUTS (outf, "W[");
2007 OUTS (outf, pregs (ptr));
086134ec 2008 OUTS (outf, " ++ ");
4b7f6baa 2009 OUTS (outf, pregs (idx));
086134ec 2010 OUTS (outf, "] = ");
4b7f6baa 2011 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2012 }
2013 else if (aop == 2 && W == 1)
2014 {
4b7f6baa
CM		 2015 OUTS (outf, "W[");
2016 OUTS (outf, pregs (ptr));
086134ec 2017 OUTS (outf, " ++ ");
4b7f6baa 2018 OUTS (outf, pregs (idx));
086134ec 2019 OUTS (outf, "] = ");
4b7f6baa 2020 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2021 }
2022 else
b7d48530
NC		 2023 return 0;
2024
2025 return 2;
4b7f6baa
CM		 2026}
2027
2028static int
2029decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2030{
b7d48530
NC		 2031 /* dagMODim
2032 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2033 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2034 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2035 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2036 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2037 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2038 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2039
2040 if (op == 0 && br == 1)
2041 {
4b7f6baa 2042 OUTS (outf, iregs (i));
086134ec 2043 OUTS (outf, " += ");
4b7f6baa 2044 OUTS (outf, mregs (m));
086134ec 2045 OUTS (outf, " (BREV)");
4b7f6baa
CM		 2046 }
2047 else if (op == 0)
2048 {
4b7f6baa 2049 OUTS (outf, iregs (i));
086134ec 2050 OUTS (outf, " += ");
4b7f6baa 2051 OUTS (outf, mregs (m));
4b7f6baa 2052 }
219b747a 2053 else if (op == 1 && br == 0)
4b7f6baa 2054 {
4b7f6baa 2055 OUTS (outf, iregs (i));
086134ec 2056 OUTS (outf, " -= ");
4b7f6baa 2057 OUTS (outf, mregs (m));
4b7f6baa
CM		 2058 }
2059 else
b7d48530
NC		 2060 return 0;
2061
2062 return 2;
4b7f6baa
CM		 2063}
2064
2065static int
2066decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2067{
b7d48530
NC		 2068 /* dagMODik
2069 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2070 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2071 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2072 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2073 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2074
2075 if (op == 0)
2076 {
4b7f6baa 2077 OUTS (outf, iregs (i));
086134ec 2078 OUTS (outf, " += 0x2");
4b7f6baa
CM		 2079 }
2080 else if (op == 1)
2081 {
4b7f6baa 2082 OUTS (outf, iregs (i));
086134ec 2083 OUTS (outf, " -= 0x2");
4b7f6baa
CM		 2084 }
2085 else if (op == 2)
2086 {
4b7f6baa 2087 OUTS (outf, iregs (i));
086134ec 2088 OUTS (outf, " += 0x4");
4b7f6baa
CM		 2089 }
2090 else if (op == 3)
2091 {
4b7f6baa 2092 OUTS (outf, iregs (i));
086134ec 2093 OUTS (outf, " -= 0x4");
4b7f6baa
CM		 2094 }
2095 else
b7d48530
NC		 2096 return 0;
2097
086134ec
BS		 2098 if (! parallel )
2099 {
2100 OUTS (outf, ";\t\t/* ( ");
2101 if (op == 0 || op == 1)
2102 OUTS (outf, "2");
2103 else if (op == 2 || op == 3)
2104 OUTS (outf, "4");
2105 OUTS (outf, ") */");
2106 comment = 1;
2107 }
2108
b7d48530 2109 return 2;
4b7f6baa
CM		 2110}
2111
2112static int
2113decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2114{
b7d48530
NC		 2115 /* dspLDST
2116 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2117 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2118 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2119 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2120 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2121 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2122 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2123 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2124
2125 if (aop == 0 && W == 0 && m == 0)
2126 {
4b7f6baa 2127 OUTS (outf, dregs (reg));
086134ec 2128 OUTS (outf, " = [");
4b7f6baa
CM		 2129 OUTS (outf, iregs (i));
2130 OUTS (outf, "++]");
4b7f6baa
CM		 2131 }
2132 else if (aop == 0 && W == 0 && m == 1)
2133 {
4b7f6baa 2134 OUTS (outf, dregs_lo (reg));
086134ec 2135 OUTS (outf, " = W[");
4b7f6baa
CM		 2136 OUTS (outf, iregs (i));
2137 OUTS (outf, "++]");
4b7f6baa
CM		 2138 }
2139 else if (aop == 0 && W == 0 && m == 2)
2140 {
4b7f6baa 2141 OUTS (outf, dregs_hi (reg));
086134ec 2142 OUTS (outf, " = W[");
4b7f6baa
CM		 2143 OUTS (outf, iregs (i));
2144 OUTS (outf, "++]");
4b7f6baa
CM		 2145 }
2146 else if (aop == 1 && W == 0 && m == 0)
2147 {
4b7f6baa 2148 OUTS (outf, dregs (reg));
086134ec 2149 OUTS (outf, " = [");
4b7f6baa
CM		 2150 OUTS (outf, iregs (i));
2151 OUTS (outf, "--]");
4b7f6baa
CM		 2152 }
2153 else if (aop == 1 && W == 0 && m == 1)
2154 {
4b7f6baa 2155 OUTS (outf, dregs_lo (reg));
086134ec 2156 OUTS (outf, " = W[");
4b7f6baa
CM		 2157 OUTS (outf, iregs (i));
2158 OUTS (outf, "--]");
4b7f6baa
CM		 2159 }
2160 else if (aop == 1 && W == 0 && m == 2)
2161 {
4b7f6baa 2162 OUTS (outf, dregs_hi (reg));
086134ec 2163 OUTS (outf, " = W[");
4b7f6baa
CM		 2164 OUTS (outf, iregs (i));
2165 OUTS (outf, "--]");
4b7f6baa
CM		 2166 }
2167 else if (aop == 2 && W == 0 && m == 0)
2168 {
4b7f6baa 2169 OUTS (outf, dregs (reg));
086134ec 2170 OUTS (outf, " = [");
4b7f6baa
CM		 2171 OUTS (outf, iregs (i));
2172 OUTS (outf, "]");
4b7f6baa
CM		 2173 }
2174 else if (aop == 2 && W == 0 && m == 1)
2175 {
4b7f6baa 2176 OUTS (outf, dregs_lo (reg));
086134ec 2177 OUTS (outf, " = W[");
4b7f6baa
CM		 2178 OUTS (outf, iregs (i));
2179 OUTS (outf, "]");
4b7f6baa
CM		 2180 }
2181 else if (aop == 2 && W == 0 && m == 2)
2182 {
4b7f6baa 2183 OUTS (outf, dregs_hi (reg));
086134ec 2184 OUTS (outf, " = W[");
4b7f6baa
CM		 2185 OUTS (outf, iregs (i));
2186 OUTS (outf, "]");
4b7f6baa
CM		 2187 }
2188 else if (aop == 0 && W == 1 && m == 0)
2189 {
4b7f6baa
CM		 2190 OUTS (outf, "[");
2191 OUTS (outf, iregs (i));
086134ec 2192 OUTS (outf, "++] = ");
4b7f6baa 2193 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2194 }
2195 else if (aop == 0 && W == 1 && m == 1)
2196 {
4b7f6baa
CM		 2197 OUTS (outf, "W[");
2198 OUTS (outf, iregs (i));
086134ec 2199 OUTS (outf, "++] = ");
4b7f6baa 2200 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2201 }
2202 else if (aop == 0 && W == 1 && m == 2)
2203 {
4b7f6baa
CM		 2204 OUTS (outf, "W[");
2205 OUTS (outf, iregs (i));
086134ec 2206 OUTS (outf, "++] = ");
4b7f6baa 2207 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2208 }
2209 else if (aop == 1 && W == 1 && m == 0)
2210 {
4b7f6baa
CM		 2211 OUTS (outf, "[");
2212 OUTS (outf, iregs (i));
086134ec 2213 OUTS (outf, "--] = ");
4b7f6baa 2214 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2215 }
2216 else if (aop == 1 && W == 1 && m == 1)
2217 {
4b7f6baa
CM		 2218 OUTS (outf, "W[");
2219 OUTS (outf, iregs (i));
086134ec 2220 OUTS (outf, "--] = ");
4b7f6baa 2221 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2222 }
2223 else if (aop == 1 && W == 1 && m == 2)
2224 {
4b7f6baa
CM		 2225 OUTS (outf, "W[");
2226 OUTS (outf, iregs (i));
086134ec 2227 OUTS (outf, "--] = ");
4b7f6baa 2228 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2229 }
2230 else if (aop == 2 && W == 1 && m == 0)
2231 {
4b7f6baa
CM		 2232 OUTS (outf, "[");
2233 OUTS (outf, iregs (i));
086134ec 2234 OUTS (outf, "] = ");
4b7f6baa 2235 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2236 }
2237 else if (aop == 2 && W == 1 && m == 1)
2238 {
4b7f6baa
CM		 2239 OUTS (outf, "W[");
2240 OUTS (outf, iregs (i));
086134ec 2241 OUTS (outf, "] = ");
4b7f6baa 2242 OUTS (outf, dregs_lo (reg));
4b7f6baa
CM		 2243 }
2244 else if (aop == 2 && W == 1 && m == 2)
2245 {
4b7f6baa
CM		 2246 OUTS (outf, "W[");
2247 OUTS (outf, iregs (i));
086134ec 2248 OUTS (outf, "] = ");
4b7f6baa 2249 OUTS (outf, dregs_hi (reg));
4b7f6baa
CM		 2250 }
2251 else if (aop == 3 && W == 0)
2252 {
4b7f6baa 2253 OUTS (outf, dregs (reg));
086134ec 2254 OUTS (outf, " = [");
4b7f6baa 2255 OUTS (outf, iregs (i));
086134ec 2256 OUTS (outf, " ++ ");
4b7f6baa
CM		 2257 OUTS (outf, mregs (m));
2258 OUTS (outf, "]");
4b7f6baa
CM		 2259 }
2260 else if (aop == 3 && W == 1)
2261 {
4b7f6baa
CM		 2262 OUTS (outf, "[");
2263 OUTS (outf, iregs (i));
086134ec 2264 OUTS (outf, " ++ ");
4b7f6baa 2265 OUTS (outf, mregs (m));
086134ec 2266 OUTS (outf, "] = ");
4b7f6baa 2267 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2268 }
2269 else
b7d48530
NC		 2270 return 0;
2271
2272 return 2;
4b7f6baa
CM		 2273}
2274
2275static int
2276decode_LDST_0 (TIword iw0, disassemble_info *outf)
2277{
b7d48530
NC		 2278 /* LDST
2279 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2280 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2281 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2282 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2283 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2284 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2285 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2286 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2287 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2288
2289 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2290 {
4b7f6baa 2291 OUTS (outf, dregs (reg));
086134ec 2292 OUTS (outf, " = [");
4b7f6baa
CM		 2293 OUTS (outf, pregs (ptr));
2294 OUTS (outf, "++]");
4b7f6baa 2295 }
219b747a 2296 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2297 {
4b7f6baa 2298 OUTS (outf, pregs (reg));
086134ec 2299 OUTS (outf, " = [");
4b7f6baa
CM		 2300 OUTS (outf, pregs (ptr));
2301 OUTS (outf, "++]");
4b7f6baa
CM		 2302 }
2303 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2304 {
4b7f6baa 2305 OUTS (outf, dregs (reg));
086134ec 2306 OUTS (outf, " = W[");
4b7f6baa
CM		 2307 OUTS (outf, pregs (ptr));
2308 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2309 }
2310 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2311 {
4b7f6baa 2312 OUTS (outf, dregs (reg));
086134ec 2313 OUTS (outf, " = W[");
4b7f6baa 2314 OUTS (outf, pregs (ptr));
086134ec 2315 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2316 }
2317 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2318 {
4b7f6baa 2319 OUTS (outf, dregs (reg));
086134ec 2320 OUTS (outf, " = B[");
4b7f6baa
CM		 2321 OUTS (outf, pregs (ptr));
2322 OUTS (outf, "++] (Z)");
4b7f6baa
CM		 2323 }
2324 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2325 {
4b7f6baa 2326 OUTS (outf, dregs (reg));
086134ec 2327 OUTS (outf, " = B[");
4b7f6baa 2328 OUTS (outf, pregs (ptr));
086134ec 2329 OUTS (outf, "++] (X)");
4b7f6baa
CM		 2330 }
2331 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2332 {
4b7f6baa 2333 OUTS (outf, dregs (reg));
086134ec 2334 OUTS (outf, " = [");
4b7f6baa
CM		 2335 OUTS (outf, pregs (ptr));
2336 OUTS (outf, "--]");
4b7f6baa 2337 }
219b747a 2338 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
4b7f6baa 2339 {
4b7f6baa 2340 OUTS (outf, pregs (reg));
086134ec 2341 OUTS (outf, " = [");
4b7f6baa
CM		 2342 OUTS (outf, pregs (ptr));
2343 OUTS (outf, "--]");
4b7f6baa
CM		 2344 }
2345 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2346 {
4b7f6baa 2347 OUTS (outf, dregs (reg));
086134ec 2348 OUTS (outf, " = W[");
4b7f6baa
CM		 2349 OUTS (outf, pregs (ptr));
2350 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2351 }
2352 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2353 {
4b7f6baa 2354 OUTS (outf, dregs (reg));
086134ec 2355 OUTS (outf, " = W[");
4b7f6baa 2356 OUTS (outf, pregs (ptr));
086134ec 2357 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2358 }
2359 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2360 {
4b7f6baa 2361 OUTS (outf, dregs (reg));
086134ec 2362 OUTS (outf, " = B[");
4b7f6baa
CM		 2363 OUTS (outf, pregs (ptr));
2364 OUTS (outf, "--] (Z)");
4b7f6baa
CM		 2365 }
2366 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2367 {
4b7f6baa 2368 OUTS (outf, dregs (reg));
086134ec 2369 OUTS (outf, " = B[");
4b7f6baa 2370 OUTS (outf, pregs (ptr));
086134ec 2371 OUTS (outf, "--] (X)");
4b7f6baa
CM		 2372 }
2373 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2374 {
4b7f6baa 2375 OUTS (outf, dregs (reg));
086134ec 2376 OUTS (outf, " = [");
4b7f6baa
CM		 2377 OUTS (outf, pregs (ptr));
2378 OUTS (outf, "]");
4b7f6baa
CM		 2379 }
2380 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2381 {
4b7f6baa 2382 OUTS (outf, pregs (reg));
086134ec 2383 OUTS (outf, " = [");
4b7f6baa
CM		 2384 OUTS (outf, pregs (ptr));
2385 OUTS (outf, "]");
4b7f6baa
CM		 2386 }
2387 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2388 {
4b7f6baa 2389 OUTS (outf, dregs (reg));
086134ec 2390 OUTS (outf, " = W[");
4b7f6baa
CM		 2391 OUTS (outf, pregs (ptr));
2392 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2393 }
2394 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2395 {
4b7f6baa 2396 OUTS (outf, dregs (reg));
086134ec 2397 OUTS (outf, " = W[");
4b7f6baa 2398 OUTS (outf, pregs (ptr));
086134ec 2399 OUTS (outf, "] (X)");
4b7f6baa
CM		 2400 }
2401 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2402 {
4b7f6baa 2403 OUTS (outf, dregs (reg));
086134ec 2404 OUTS (outf, " = B[");
4b7f6baa
CM		 2405 OUTS (outf, pregs (ptr));
2406 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2407 }
2408 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2409 {
4b7f6baa 2410 OUTS (outf, dregs (reg));
086134ec 2411 OUTS (outf, " = B[");
4b7f6baa 2412 OUTS (outf, pregs (ptr));
086134ec 2413 OUTS (outf, "] (X)");
4b7f6baa
CM		 2414 }
2415 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2416 {
4b7f6baa
CM		 2417 OUTS (outf, "[");
2418 OUTS (outf, pregs (ptr));
086134ec 2419 OUTS (outf, "++] = ");
4b7f6baa 2420 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2421 }
2422 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2423 {
4b7f6baa
CM		 2424 OUTS (outf, "[");
2425 OUTS (outf, pregs (ptr));
086134ec 2426 OUTS (outf, "++] = ");
4b7f6baa 2427 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2428 }
2429 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2430 {
4b7f6baa
CM		 2431 OUTS (outf, "W[");
2432 OUTS (outf, pregs (ptr));
086134ec 2433 OUTS (outf, "++] = ");
4b7f6baa 2434 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2435 }
2436 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2437 {
4b7f6baa
CM		 2438 OUTS (outf, "B[");
2439 OUTS (outf, pregs (ptr));
086134ec 2440 OUTS (outf, "++] = ");
4b7f6baa 2441 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2442 }
2443 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2444 {
4b7f6baa
CM		 2445 OUTS (outf, "[");
2446 OUTS (outf, pregs (ptr));
086134ec 2447 OUTS (outf, "--] = ");
4b7f6baa 2448 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2449 }
2450 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2451 {
4b7f6baa
CM		 2452 OUTS (outf, "[");
2453 OUTS (outf, pregs (ptr));
086134ec 2454 OUTS (outf, "--] = ");
4b7f6baa 2455 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2456 }
2457 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2458 {
4b7f6baa
CM		 2459 OUTS (outf, "W[");
2460 OUTS (outf, pregs (ptr));
086134ec 2461 OUTS (outf, "--] = ");
4b7f6baa 2462 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2463 }
2464 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2465 {
4b7f6baa
CM		 2466 OUTS (outf, "B[");
2467 OUTS (outf, pregs (ptr));
086134ec 2468 OUTS (outf, "--] = ");
4b7f6baa 2469 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2470 }
2471 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2472 {
4b7f6baa
CM		 2473 OUTS (outf, "[");
2474 OUTS (outf, pregs (ptr));
086134ec 2475 OUTS (outf, "] = ");
4b7f6baa 2476 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2477 }
2478 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2479 {
4b7f6baa
CM		 2480 OUTS (outf, "[");
2481 OUTS (outf, pregs (ptr));
086134ec 2482 OUTS (outf, "] = ");
4b7f6baa 2483 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2484 }
2485 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2486 {
4b7f6baa
CM		 2487 OUTS (outf, "W[");
2488 OUTS (outf, pregs (ptr));
086134ec 2489 OUTS (outf, "] = ");
4b7f6baa 2490 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2491 }
2492 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2493 {
4b7f6baa
CM		 2494 OUTS (outf, "B[");
2495 OUTS (outf, pregs (ptr));
086134ec 2496 OUTS (outf, "] = ");
4b7f6baa 2497 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2498 }
2499 else
b7d48530
NC		 2500 return 0;
2501
2502 return 2;
4b7f6baa
CM		 2503}
2504
2505static int
2506decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2507{
b7d48530
NC		 2508 /* LDSTiiFP
2509 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2510 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2511 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2512 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2513 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2514 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2515
2516 if (W == 0)
2517 {
4b7f6baa 2518 OUTS (outf, dpregs (reg));
086134ec 2519 OUTS (outf, " = [FP ");
4b7f6baa
CM		 2520 OUTS (outf, negimm5s4 (offset));
2521 OUTS (outf, "]");
4b7f6baa
CM		 2522 }
2523 else if (W == 1)
2524 {
086134ec 2525 OUTS (outf, "[FP ");
4b7f6baa 2526 OUTS (outf, negimm5s4 (offset));
086134ec 2527 OUTS (outf, "] = ");
4b7f6baa 2528 OUTS (outf, dpregs (reg));
4b7f6baa
CM		 2529 }
2530 else
b7d48530
NC		 2531 return 0;
2532
2533 return 2;
4b7f6baa
CM		 2534}
2535
2536static int
2537decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2538{
b7d48530
NC		 2539 /* LDSTii
2540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2541 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2542 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2543 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2544 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2545 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2546 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2547 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2548
2549 if (W == 0 && op == 0)
2550 {
4b7f6baa 2551 OUTS (outf, dregs (reg));
086134ec 2552 OUTS (outf, " = [");
4b7f6baa 2553 OUTS (outf, pregs (ptr));
086134ec 2554 OUTS (outf, " + ");
4b7f6baa
CM		 2555 OUTS (outf, uimm4s4 (offset));
2556 OUTS (outf, "]");
4b7f6baa
CM		 2557 }
2558 else if (W == 0 && op == 1)
2559 {
4b7f6baa 2560 OUTS (outf, dregs (reg));
086134ec 2561 OUTS (outf, " = W[");
4b7f6baa 2562 OUTS (outf, pregs (ptr));
086134ec 2563 OUTS (outf, " + ");
4b7f6baa
CM		 2564 OUTS (outf, uimm4s2 (offset));
2565 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2566 }
2567 else if (W == 0 && op == 2)
2568 {
4b7f6baa 2569 OUTS (outf, dregs (reg));
086134ec 2570 OUTS (outf, " = W[");
4b7f6baa 2571 OUTS (outf, pregs (ptr));
086134ec 2572 OUTS (outf, " + ");
4b7f6baa 2573 OUTS (outf, uimm4s2 (offset));
086134ec 2574 OUTS (outf, "] (X)");
4b7f6baa
CM		 2575 }
2576 else if (W == 0 && op == 3)
2577 {
4b7f6baa 2578 OUTS (outf, pregs (reg));
086134ec 2579 OUTS (outf, " = [");
4b7f6baa 2580 OUTS (outf, pregs (ptr));
086134ec 2581 OUTS (outf, " + ");
4b7f6baa
CM		 2582 OUTS (outf, uimm4s4 (offset));
2583 OUTS (outf, "]");
4b7f6baa
CM		 2584 }
2585 else if (W == 1 && op == 0)
2586 {
4b7f6baa
CM		 2587 OUTS (outf, "[");
2588 OUTS (outf, pregs (ptr));
086134ec 2589 OUTS (outf, " + ");
4b7f6baa 2590 OUTS (outf, uimm4s4 (offset));
086134ec 2591 OUTS (outf, "] = ");
4b7f6baa 2592 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2593 }
2594 else if (W == 1 && op == 1)
2595 {
086134ec 2596 OUTS (outf, "W[");
4b7f6baa 2597 OUTS (outf, pregs (ptr));
086134ec 2598 OUTS (outf, " + ");
4b7f6baa 2599 OUTS (outf, uimm4s2 (offset));
086134ec 2600 OUTS (outf, "] = ");
4b7f6baa 2601 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2602 }
2603 else if (W == 1 && op == 3)
2604 {
4b7f6baa
CM		 2605 OUTS (outf, "[");
2606 OUTS (outf, pregs (ptr));
086134ec 2607 OUTS (outf, " + ");
4b7f6baa 2608 OUTS (outf, uimm4s4 (offset));
086134ec 2609 OUTS (outf, "] = ");
4b7f6baa 2610 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2611 }
2612 else
b7d48530
NC		 2613 return 0;
2614
2615 return 2;
4b7f6baa
CM		 2616}
2617
2618static int
2619decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2620{
b7d48530
NC		 2621 /* LoopSetup
2622 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2623 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2624 |.reg...........| - | - |.eoffset...............................|
2625 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2626 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2627 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2628 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2629 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2630 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2631
219b747a
MF		 2632 if (parallel)
2633 return 0;
2634
4b7f6baa
CM		 2635 if (rop == 0)
2636 {
4b7f6baa 2637 OUTS (outf, "LSETUP");
086134ec 2638 OUTS (outf, "(0x");
4b7f6baa 2639 OUTS (outf, pcrel4 (soffset));
086134ec 2640 OUTS (outf, ", 0x");
4b7f6baa 2641 OUTS (outf, lppcrel10 (eoffset));
086134ec 2642 OUTS (outf, ") ");
4b7f6baa 2643 OUTS (outf, counters (c));
4b7f6baa
CM		 2644 }
2645 else if (rop == 1)
2646 {
4b7f6baa 2647 OUTS (outf, "LSETUP");
086134ec 2648 OUTS (outf, "(0x");
4b7f6baa 2649 OUTS (outf, pcrel4 (soffset));
086134ec 2650 OUTS (outf, ", 0x");
4b7f6baa 2651 OUTS (outf, lppcrel10 (eoffset));
086134ec 2652 OUTS (outf, ") ");
4b7f6baa 2653 OUTS (outf, counters (c));
086134ec 2654 OUTS (outf, " = ");
4b7f6baa 2655 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2656 }
2657 else if (rop == 3)
2658 {
4b7f6baa 2659 OUTS (outf, "LSETUP");
086134ec 2660 OUTS (outf, "(0x");
4b7f6baa 2661 OUTS (outf, pcrel4 (soffset));
086134ec 2662 OUTS (outf, ", 0x");
4b7f6baa 2663 OUTS (outf, lppcrel10 (eoffset));
086134ec 2664 OUTS (outf, ") ");
4b7f6baa 2665 OUTS (outf, counters (c));
086134ec 2666 OUTS (outf, " = ");
4b7f6baa 2667 OUTS (outf, pregs (reg));
086134ec 2668 OUTS (outf, " >> 0x1");
4b7f6baa
CM		 2669 }
2670 else
b7d48530
NC		 2671 return 0;
2672
2673 return 4;
4b7f6baa
CM		 2674}
2675
2676static int
2677decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2678{
b7d48530
NC		 2679 /* LDIMMhalf
2680 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2681 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2682 |.hword.........................................................|
2683 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2684 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2685 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2686 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2687 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2688 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2689 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2690
b21c9cb4
BS		 2691 bu32 *pval = get_allreg (grp, reg);
2692
219b747a
MF		 2693 if (parallel)
2694 return 0;
2695
b21c9cb4
BS		 2696 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2697 to combine them, so it prints out the right values.
2698 Here we keep track of the registers. */
2699 if (H == 0 && S == 1 && Z == 0)
2700 {
2701 /* regs = imm16 (x) */
2702 *pval = imm16_val (hword);
086134ec
BS		 2703 if (hword & 0x8000)
2704 *pval |= 0xFFFF0000;
2705 else
2706 *pval &= 0xFFFF;
b21c9cb4
BS		 2707 }
2708 else if (H == 0 && S == 0 && Z == 1)
2709 {
2710 /* regs = luimm16 (Z) */
2711 *pval = luimm16_val (hword);
086134ec 2712 *pval &= 0xFFFF;
b21c9cb4
BS		 2713 }
2714 else if (H == 0 && S == 0 && Z == 0)
2715 {
2716 /* regs_lo = luimm16 */
2717 *pval &= 0xFFFF0000;
2718 *pval |= luimm16_val (hword);
2719 }
2720 else if (H == 1 && S == 0 && Z == 0)
2721 {
2722 /* regs_hi = huimm16 */
2723 *pval &= 0xFFFF;
2724 *pval |= luimm16_val (hword) << 16;
2725 }
2726
2727 /* Here we do the disassembly */
4b7f6baa
CM		 2728 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2729 {
4b7f6baa 2730 OUTS (outf, dregs_lo (reg));
086134ec
BS		 2731 OUTS (outf, " = ");
2732 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2733 }
2734 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2735 {
4b7f6baa 2736 OUTS (outf, dregs_hi (reg));
086134ec
BS		 2737 OUTS (outf, " = ");
2738 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2739 }
2740 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2741 {
4b7f6baa 2742 OUTS (outf, dregs (reg));
086134ec 2743 OUTS (outf, " = ");
4b7f6baa
CM		 2744 OUTS (outf, imm16 (hword));
2745 OUTS (outf, " (X)");
4b7f6baa
CM		 2746 }
2747 else if (H == 0 && S == 1 && Z == 0)
086134ec 2748 {
4b7f6baa 2749 OUTS (outf, regs (reg, grp));
086134ec 2750 OUTS (outf, " = ");
4b7f6baa
CM		 2751 OUTS (outf, imm16 (hword));
2752 OUTS (outf, " (X)");
4b7f6baa
CM		 2753 }
2754 else if (H == 0 && S == 0 && Z == 1)
2755 {
4b7f6baa 2756 OUTS (outf, regs (reg, grp));
086134ec
BS		 2757 OUTS (outf, " = ");
2758 OUTS (outf, uimm16 (hword));
2759 OUTS (outf, " (Z)");
4b7f6baa
CM		 2760 }
2761 else if (H == 0 && S == 0 && Z == 0)
2762 {
4b7f6baa 2763 OUTS (outf, regs_lo (reg, grp));
086134ec 2764 OUTS (outf, " = ");
b21c9cb4 2765 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2766 }
2767 else if (H == 1 && S == 0 && Z == 0)
2768 {
4b7f6baa 2769 OUTS (outf, regs_hi (reg, grp));
086134ec 2770 OUTS (outf, " = ");
b21c9cb4 2771 OUTS (outf, uimm16 (hword));
4b7f6baa
CM		 2772 }
2773 else
b7d48530
NC		 2774 return 0;
2775
b21c9cb4 2776 /* And we print out the 32-bit value if it is a pointer. */
086134ec 2777 if (S == 0 && Z == 0)
b21c9cb4 2778 {
086134ec
BS		 2779 OUTS (outf, ";\t\t/* (");
2780 OUTS (outf, imm16d (hword));
2781 OUTS (outf, ")\t");
2782
b21c9cb4 2783 /* If it is an MMR, don't print the symbol. */
086134ec
BS		 2784 if (*pval < 0xFFC00000 && grp == 1)
2785 {
2786 OUTS (outf, regs (reg, grp));
2787 OUTS (outf, "=0x");
2788 OUTS (outf, huimm32e (*pval));
2789 }
b21c9cb4 2790 else
086134ec
BS		 2791 {
2792 OUTS (outf, regs (reg, grp));
2793 OUTS (outf, "=0x");
2794 OUTS (outf, huimm32e (*pval));
2795 OUTS (outf, "(");
2796 OUTS (outf, imm32 (*pval));
2797 OUTS (outf, ")");
2798 }
b21c9cb4
BS		 2799
2800 OUTS (outf, " */");
086134ec
BS		 2801 comment = 1;
2802 }
2803 if (S == 1 || Z == 1)
2804 {
2805 OUTS (outf, ";\t\t/*\t\t");
2806 OUTS (outf, regs (reg, grp));
2807 OUTS (outf, "=0x");
2808 OUTS (outf, huimm32e (*pval));
2809 OUTS (outf, "(");
2810 OUTS (outf, imm32 (*pval));
2811 OUTS (outf, ") */");
2812 comment = 1;
b21c9cb4 2813 }
b7d48530 2814 return 4;
4b7f6baa
CM		 2815}
2816
2817static int
2818decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2819{
b7d48530
NC		 2820 /* CALLa
2821 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2822 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2823 |.lsw...........................................................|
2824 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2825 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2826 int lsw = ((iw1 >> 0) & 0xffff);
2827 int msw = ((iw0 >> 0) & 0xff);
2828
219b747a
MF		 2829 if (parallel)
2830 return 0;
2831
4b7f6baa 2832 if (S == 1)
086134ec 2833 OUTS (outf, "CALL 0x");
4b7f6baa 2834 else if (S == 0)
086134ec 2835 OUTS (outf, "JUMP.L 0x");
4b7f6baa 2836 else
b7d48530
NC		 2837 return 0;
2838
2839 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2840 return 4;
4b7f6baa
CM		 2841}
2842
2843static int
2844decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2845{
b7d48530
NC		 2846 /* LDSTidxI
2847 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2848 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2849 |.offset........................................................|
2850 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2851 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2852 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2853 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2854 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2855 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2856 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2857
2858 if (W == 0 && sz == 0 && Z == 0)
2859 {
4b7f6baa 2860 OUTS (outf, dregs (reg));
086134ec 2861 OUTS (outf, " = [");
4b7f6baa 2862 OUTS (outf, pregs (ptr));
086134ec 2863 OUTS (outf, " + ");
4b7f6baa
CM		 2864 OUTS (outf, imm16s4 (offset));
2865 OUTS (outf, "]");
4b7f6baa
CM		 2866 }
2867 else if (W == 0 && sz == 0 && Z == 1)
2868 {
4b7f6baa 2869 OUTS (outf, pregs (reg));
086134ec 2870 OUTS (outf, " = [");
4b7f6baa 2871 OUTS (outf, pregs (ptr));
086134ec 2872 OUTS (outf, " + ");
4b7f6baa
CM		 2873 OUTS (outf, imm16s4 (offset));
2874 OUTS (outf, "]");
4b7f6baa
CM		 2875 }
2876 else if (W == 0 && sz == 1 && Z == 0)
2877 {
4b7f6baa 2878 OUTS (outf, dregs (reg));
086134ec 2879 OUTS (outf, " = W[");
4b7f6baa 2880 OUTS (outf, pregs (ptr));
086134ec 2881 OUTS (outf, " + ");
4b7f6baa
CM		 2882 OUTS (outf, imm16s2 (offset));
2883 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2884 }
2885 else if (W == 0 && sz == 1 && Z == 1)
2886 {
4b7f6baa 2887 OUTS (outf, dregs (reg));
086134ec 2888 OUTS (outf, " = W[");
4b7f6baa 2889 OUTS (outf, pregs (ptr));
086134ec 2890 OUTS (outf, " + ");
4b7f6baa 2891 OUTS (outf, imm16s2 (offset));
086134ec 2892 OUTS (outf, "] (X)");
4b7f6baa
CM		 2893 }
2894 else if (W == 0 && sz == 2 && Z == 0)
2895 {
4b7f6baa 2896 OUTS (outf, dregs (reg));
086134ec 2897 OUTS (outf, " = B[");
4b7f6baa 2898 OUTS (outf, pregs (ptr));
086134ec 2899 OUTS (outf, " + ");
4b7f6baa
CM		 2900 OUTS (outf, imm16 (offset));
2901 OUTS (outf, "] (Z)");
4b7f6baa
CM		 2902 }
2903 else if (W == 0 && sz == 2 && Z == 1)
2904 {
4b7f6baa 2905 OUTS (outf, dregs (reg));
086134ec 2906 OUTS (outf, " = B[");
4b7f6baa 2907 OUTS (outf, pregs (ptr));
086134ec 2908 OUTS (outf, " + ");
4b7f6baa 2909 OUTS (outf, imm16 (offset));
086134ec 2910 OUTS (outf, "] (X)");
4b7f6baa
CM		 2911 }
2912 else if (W == 1 && sz == 0 && Z == 0)
2913 {
4b7f6baa
CM		 2914 OUTS (outf, "[");
2915 OUTS (outf, pregs (ptr));
086134ec 2916 OUTS (outf, " + ");
4b7f6baa 2917 OUTS (outf, imm16s4 (offset));
086134ec 2918 OUTS (outf, "] = ");
4b7f6baa 2919 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2920 }
2921 else if (W == 1 && sz == 0 && Z == 1)
2922 {
4b7f6baa
CM		 2923 OUTS (outf, "[");
2924 OUTS (outf, pregs (ptr));
086134ec 2925 OUTS (outf, " + ");
4b7f6baa 2926 OUTS (outf, imm16s4 (offset));
086134ec 2927 OUTS (outf, "] = ");
4b7f6baa 2928 OUTS (outf, pregs (reg));
4b7f6baa
CM		 2929 }
2930 else if (W == 1 && sz == 1 && Z == 0)
2931 {
4b7f6baa
CM		 2932 OUTS (outf, "W[");
2933 OUTS (outf, pregs (ptr));
086134ec 2934 OUTS (outf, " + ");
4b7f6baa 2935 OUTS (outf, imm16s2 (offset));
086134ec 2936 OUTS (outf, "] = ");
4b7f6baa 2937 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2938 }
2939 else if (W == 1 && sz == 2 && Z == 0)
2940 {
4b7f6baa
CM		 2941 OUTS (outf, "B[");
2942 OUTS (outf, pregs (ptr));
086134ec 2943 OUTS (outf, " + ");
4b7f6baa 2944 OUTS (outf, imm16 (offset));
086134ec 2945 OUTS (outf, "] = ");
4b7f6baa 2946 OUTS (outf, dregs (reg));
4b7f6baa
CM		 2947 }
2948 else
b7d48530
NC		 2949 return 0;
2950
2951 return 4;
4b7f6baa
CM		 2952}
2953
2954static int
2955decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2956{
b7d48530
NC		 2957 /* linkage
2958 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2959 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2960 |.framesize.....................................................|
2961 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 2962 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2963 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2964
219b747a
MF		 2965 if (parallel)
2966 return 0;
2967
4b7f6baa
CM		 2968 if (R == 0)
2969 {
4b7f6baa
CM		 2970 OUTS (outf, "LINK ");
2971 OUTS (outf, uimm16s4 (framesize));
086134ec
BS		 2972 OUTS (outf, ";\t\t/* (");
2973 OUTS (outf, uimm16s4d (framesize));
2974 OUTS (outf, ") */");
2975 comment = 1;
4b7f6baa
CM		 2976 }
2977 else if (R == 1)
b7d48530 2978 OUTS (outf, "UNLINK");
4b7f6baa 2979 else
b7d48530
NC		 2980 return 0;
2981
2982 return 4;
4b7f6baa
CM		 2983}
2984
2985static int
2986decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2987{
b7d48530
NC		 2988 /* dsp32mac
2989 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2990 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2991 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2992 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2993 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2994 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2995 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2996 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 2997 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 2998 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 2999 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3000 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3001 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3002 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3003 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3004 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
3005 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3006 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3007
3008 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3009 return 0;
3010
3011 if (op1 == 3 && MM)
3012 return 0;
3013
3014 if ((w1 || w0) && mmod == M_W32)
3015 return 0;
3016
ee171c8f 3017 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
4b7f6baa
CM		 3018 return 0;
3019
3020 if (w1 == 1 || op1 != 3)
3021 {
3022 if (w1)
3023 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3024
3025 if (op1 == 3)
3026 OUTS (outf, " = A1");
3027 else
3028 {
3029 if (w1)
3030 OUTS (outf, " = (");
3031 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3032 if (w1)
3033 OUTS (outf, ")");
3034 }
3035
3036 if (w0 == 1 || op0 != 3)
3037 {
3038 if (MM)
3039 OUTS (outf, " (M)");
3040 MM = 0;
3041 OUTS (outf, ", ");
3042 }
3043 }
3044
3045 if (w0 == 1 || op0 != 3)
3046 {
3047 if (w0)
3048 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3049
3050 if (op0 == 3)
3051 OUTS (outf, " = A0");
3052 else
3053 {
3054 if (w0)
3055 OUTS (outf, " = (");
3056 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3057 if (w0)
3058 OUTS (outf, ")");
3059 }
3060 }
3061
3062 decode_optmode (mmod, MM, outf);
3063
3064 return 4;
3065}
3066
3067static int
3068decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3069{
b7d48530
NC		 3070 /* dsp32mult
3071 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3072 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3073 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3074 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3075 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3076 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3077 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
4b7f6baa 3078 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
b7d48530 3079 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
4b7f6baa
CM		 3080 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3081 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
b7d48530
NC		 3082 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3083 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3084 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3085 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3086 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
4b7f6baa
CM		 3087
3088 if (w1 == 0 && w0 == 0)
3089 return 0;
b7d48530 3090
4b7f6baa
CM		 3091 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3092 return 0;
b7d48530 3093
4b7f6baa
CM		 3094 if (w1)
3095 {
3096 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3097 OUTS (outf, " = ");
3098 decode_multfunc (h01, h11, src0, src1, outf);
3099
3100 if (w0)
3101 {
3102 if (MM)
3103 OUTS (outf, " (M)");
3104 MM = 0;
3105 OUTS (outf, ", ");
3106 }
3107 }
3108
3109 if (w0)
3110 {
3111 OUTS (outf, dregs (dst));
3112 OUTS (outf, " = ");
3113 decode_multfunc (h00, h10, src0, src1, outf);
3114 }
3115
3116 decode_optmode (mmod, MM, outf);
3117 return 4;
3118}
3119
3120static int
3121decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3122{
b7d48530
NC		 3123 /* dsp32alu
3124 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3125 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3126 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3127 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 3128 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3129 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3130 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3131 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3132 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3133 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3134 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3135 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3136 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3137
3138 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3139 {
086134ec 3140 OUTS (outf, "A0.L = ");
4b7f6baa 3141 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3142 }
3143 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3144 {
086134ec 3145 OUTS (outf, "A1.H = ");
4b7f6baa 3146 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3147 }
3148 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3149 {
086134ec 3150 OUTS (outf, "A1.L = ");
4b7f6baa 3151 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3152 }
3153 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3154 {
086134ec 3155 OUTS (outf, "A0.H = ");
4b7f6baa 3156 OUTS (outf, dregs_hi (src0));
4b7f6baa
CM		 3157 }
3158 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3159 {
4b7f6baa 3160 OUTS (outf, dregs_hi (dst0));
086134ec 3161 OUTS (outf, " = ");
4b7f6baa 3162 OUTS (outf, dregs (src0));
086134ec 3163 OUTS (outf, " - ");
4b7f6baa 3164 OUTS (outf, dregs (src1));
086134ec 3165 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3166 }
3167 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3168 {
4b7f6baa 3169 OUTS (outf, dregs_hi (dst0));
086134ec 3170 OUTS (outf, " = ");
4b7f6baa 3171 OUTS (outf, dregs (src0));
086134ec 3172 OUTS (outf, " + ");
4b7f6baa 3173 OUTS (outf, dregs (src1));
086134ec 3174 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3175 }
3176 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3177 {
4b7f6baa 3178 OUTS (outf, dregs_lo (dst0));
086134ec 3179 OUTS (outf, " = ");
4b7f6baa 3180 OUTS (outf, dregs (src0));
086134ec 3181 OUTS (outf, " - ");
4b7f6baa 3182 OUTS (outf, dregs (src1));
086134ec 3183 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3184 }
3185 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3186 {
4b7f6baa 3187 OUTS (outf, dregs_lo (dst0));
086134ec 3188 OUTS (outf, " = ");
4b7f6baa 3189 OUTS (outf, dregs (src0));
086134ec 3190 OUTS (outf, " + ");
4b7f6baa 3191 OUTS (outf, dregs (src1));
086134ec 3192 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3193 }
3194 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3195 {
4b7f6baa 3196 OUTS (outf, dregs_lo (dst0));
086134ec 3197 OUTS (outf, " = ");
4b7f6baa 3198 OUTS (outf, dregs (src0));
086134ec 3199 OUTS (outf, " - ");
4b7f6baa 3200 OUTS (outf, dregs (src1));
086134ec 3201 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3202 }
3203 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3204 {
4b7f6baa 3205 OUTS (outf, dregs_hi (dst0));
086134ec 3206 OUTS (outf, " = ");
4b7f6baa 3207 OUTS (outf, dregs (src0));
086134ec 3208 OUTS (outf, " + ");
4b7f6baa 3209 OUTS (outf, dregs (src1));
086134ec 3210 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3211 }
3212 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3213 {
4b7f6baa 3214 OUTS (outf, dregs_lo (dst0));
086134ec 3215 OUTS (outf, " = ");
4b7f6baa 3216 OUTS (outf, dregs (src0));
086134ec 3217 OUTS (outf, " + ");
4b7f6baa 3218 OUTS (outf, dregs (src1));
086134ec 3219 OUTS (outf, " (RND20)");
4b7f6baa
CM		 3220 }
3221 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3222 {
4b7f6baa 3223 OUTS (outf, dregs_hi (dst0));
086134ec 3224 OUTS (outf, " = ");
4b7f6baa 3225 OUTS (outf, dregs (src0));
086134ec 3226 OUTS (outf, " - ");
4b7f6baa 3227 OUTS (outf, dregs (src1));
086134ec 3228 OUTS (outf, " (RND12)");
4b7f6baa
CM		 3229 }
3230 else if (HL == 1 && aop == 0 && aopcde == 2)
3231 {
4b7f6baa 3232 OUTS (outf, dregs_hi (dst0));
086134ec 3233 OUTS (outf, " = ");
4b7f6baa 3234 OUTS (outf, dregs_lo (src0));
086134ec 3235 OUTS (outf, " + ");
4b7f6baa 3236 OUTS (outf, dregs_lo (src1));
4b7f6baa 3237 amod1 (s, x, outf);
4b7f6baa
CM		 3238 }
3239 else if (HL == 1 && aop == 1 && aopcde == 2)
3240 {
4b7f6baa 3241 OUTS (outf, dregs_hi (dst0));
086134ec 3242 OUTS (outf, " = ");
4b7f6baa 3243 OUTS (outf, dregs_lo (src0));
086134ec 3244 OUTS (outf, " + ");
4b7f6baa 3245 OUTS (outf, dregs_hi (src1));
4b7f6baa 3246 amod1 (s, x, outf);
4b7f6baa
CM		 3247 }
3248 else if (HL == 1 && aop == 2 && aopcde == 2)
3249 {
4b7f6baa 3250 OUTS (outf, dregs_hi (dst0));
086134ec 3251 OUTS (outf, " = ");
4b7f6baa 3252 OUTS (outf, dregs_hi (src0));
086134ec 3253 OUTS (outf, " + ");
4b7f6baa 3254 OUTS (outf, dregs_lo (src1));
4b7f6baa 3255 amod1 (s, x, outf);
4b7f6baa
CM		 3256 }
3257 else if (HL == 1 && aop == 3 && aopcde == 2)
3258 {
4b7f6baa 3259 OUTS (outf, dregs_hi (dst0));
086134ec 3260 OUTS (outf, " = ");
4b7f6baa 3261 OUTS (outf, dregs_hi (src0));
086134ec 3262 OUTS (outf, " + ");
4b7f6baa 3263 OUTS (outf, dregs_hi (src1));
4b7f6baa 3264 amod1 (s, x, outf);
4b7f6baa
CM		 3265 }
3266 else if (HL == 0 && aop == 0 && aopcde == 3)
3267 {
4b7f6baa 3268 OUTS (outf, dregs_lo (dst0));
086134ec 3269 OUTS (outf, " = ");
4b7f6baa 3270 OUTS (outf, dregs_lo (src0));
086134ec 3271 OUTS (outf, " - ");
4b7f6baa 3272 OUTS (outf, dregs_lo (src1));
4b7f6baa 3273 amod1 (s, x, outf);
4b7f6baa
CM		 3274 }
3275 else if (HL == 0 && aop == 1 && aopcde == 3)
3276 {
4b7f6baa 3277 OUTS (outf, dregs_lo (dst0));
086134ec 3278 OUTS (outf, " = ");
4b7f6baa 3279 OUTS (outf, dregs_lo (src0));
086134ec 3280 OUTS (outf, " - ");
4b7f6baa 3281 OUTS (outf, dregs_hi (src1));
4b7f6baa 3282 amod1 (s, x, outf);
4b7f6baa
CM		 3283 }
3284 else if (HL == 0 && aop == 3 && aopcde == 2)
3285 {
4b7f6baa 3286 OUTS (outf, dregs_lo (dst0));
086134ec 3287 OUTS (outf, " = ");
4b7f6baa 3288 OUTS (outf, dregs_hi (src0));
086134ec 3289 OUTS (outf, " + ");
4b7f6baa 3290 OUTS (outf, dregs_hi (src1));
4b7f6baa 3291 amod1 (s, x, outf);
4b7f6baa
CM		 3292 }
3293 else if (HL == 1 && aop == 0 && aopcde == 3)
3294 {
4b7f6baa 3295 OUTS (outf, dregs_hi (dst0));
086134ec 3296 OUTS (outf, " = ");
4b7f6baa 3297 OUTS (outf, dregs_lo (src0));
086134ec 3298 OUTS (outf, " - ");
4b7f6baa 3299 OUTS (outf, dregs_lo (src1));
4b7f6baa 3300 amod1 (s, x, outf);
4b7f6baa
CM		 3301 }
3302 else if (HL == 1 && aop == 1 && aopcde == 3)
3303 {
4b7f6baa 3304 OUTS (outf, dregs_hi (dst0));
086134ec 3305 OUTS (outf, " = ");
4b7f6baa 3306 OUTS (outf, dregs_lo (src0));
086134ec 3307 OUTS (outf, " - ");
4b7f6baa 3308 OUTS (outf, dregs_hi (src1));
4b7f6baa 3309 amod1 (s, x, outf);
4b7f6baa
CM		 3310 }
3311 else if (HL == 1 && aop == 2 && aopcde == 3)
3312 {
4b7f6baa 3313 OUTS (outf, dregs_hi (dst0));
086134ec 3314 OUTS (outf, " = ");
4b7f6baa 3315 OUTS (outf, dregs_hi (src0));
086134ec 3316 OUTS (outf, " - ");
4b7f6baa 3317 OUTS (outf, dregs_lo (src1));
4b7f6baa 3318 amod1 (s, x, outf);
4b7f6baa
CM		 3319 }
3320 else if (HL == 1 && aop == 3 && aopcde == 3)
3321 {
4b7f6baa 3322 OUTS (outf, dregs_hi (dst0));
086134ec 3323 OUTS (outf, " = ");
4b7f6baa 3324 OUTS (outf, dregs_hi (src0));
086134ec 3325 OUTS (outf, " - ");
4b7f6baa 3326 OUTS (outf, dregs_hi (src1));
4b7f6baa 3327 amod1 (s, x, outf);
4b7f6baa
CM		 3328 }
3329 else if (HL == 0 && aop == 2 && aopcde == 2)
3330 {
4b7f6baa 3331 OUTS (outf, dregs_lo (dst0));
086134ec 3332 OUTS (outf, " = ");
4b7f6baa 3333 OUTS (outf, dregs_hi (src0));
086134ec 3334 OUTS (outf, " + ");
4b7f6baa 3335 OUTS (outf, dregs_lo (src1));
4b7f6baa 3336 amod1 (s, x, outf);
4b7f6baa
CM		 3337 }
3338 else if (HL == 0 && aop == 1 && aopcde == 2)
3339 {
4b7f6baa 3340 OUTS (outf, dregs_lo (dst0));
086134ec 3341 OUTS (outf, " = ");
4b7f6baa 3342 OUTS (outf, dregs_lo (src0));
086134ec 3343 OUTS (outf, " + ");
4b7f6baa 3344 OUTS (outf, dregs_hi (src1));
4b7f6baa 3345 amod1 (s, x, outf);
4b7f6baa
CM		 3346 }
3347 else if (HL == 0 && aop == 2 && aopcde == 3)
3348 {
4b7f6baa 3349 OUTS (outf, dregs_lo (dst0));
086134ec 3350 OUTS (outf, " = ");
4b7f6baa 3351 OUTS (outf, dregs_hi (src0));
086134ec 3352 OUTS (outf, " - ");
4b7f6baa 3353 OUTS (outf, dregs_lo (src1));
4b7f6baa 3354 amod1 (s, x, outf);
4b7f6baa
CM		 3355 }
3356 else if (HL == 0 && aop == 3 && aopcde == 3)
3357 {
4b7f6baa 3358 OUTS (outf, dregs_lo (dst0));
086134ec 3359 OUTS (outf, " = ");
4b7f6baa 3360 OUTS (outf, dregs_hi (src0));
086134ec 3361 OUTS (outf, " - ");
4b7f6baa 3362 OUTS (outf, dregs_hi (src1));
4b7f6baa 3363 amod1 (s, x, outf);
4b7f6baa
CM		 3364 }
3365 else if (HL == 0 && aop == 0 && aopcde == 2)
3366 {
4b7f6baa 3367 OUTS (outf, dregs_lo (dst0));
086134ec 3368 OUTS (outf, " = ");
4b7f6baa 3369 OUTS (outf, dregs_lo (src0));
086134ec 3370 OUTS (outf, " + ");
4b7f6baa 3371 OUTS (outf, dregs_lo (src1));
4b7f6baa 3372 amod1 (s, x, outf);
4b7f6baa
CM		 3373 }
3374 else if (aop == 0 && aopcde == 9 && s == 1)
3375 {
086134ec 3376 OUTS (outf, "A0 = ");
4b7f6baa 3377 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3378 }
3379 else if (aop == 3 && aopcde == 11 && s == 0)
086134ec 3380 OUTS (outf, "A0 -= A1");
b7d48530 3381
4b7f6baa 3382 else if (aop == 3 && aopcde == 11 && s == 1)
086134ec 3383 OUTS (outf, "A0 -= A1 (W32)");
b7d48530 3384
4b7f6baa
CM		 3385 else if (aop == 3 && aopcde == 22 && HL == 1)
3386 {
4b7f6baa 3387 OUTS (outf, dregs (dst0));
086134ec 3388 OUTS (outf, " = BYTEOP2M (");
4b7f6baa
CM		 3389 OUTS (outf, dregs (src0 + 1));
3390 OUTS (outf, ":");
e1791cb8 3391 OUTS (outf, imm5d (src0));
086134ec 3392 OUTS (outf, ", ");
4b7f6baa
CM		 3393 OUTS (outf, dregs (src1 + 1));
3394 OUTS (outf, ":");
e1791cb8 3395 OUTS (outf, imm5d (src1));
086134ec 3396 OUTS (outf, ") (TH");
4b7f6baa
CM		 3397 if (s == 1)
3398 OUTS (outf, ", R)");
3399 else
3400 OUTS (outf, ")");
4b7f6baa
CM		 3401 }
3402 else if (aop == 3 && aopcde == 22 && HL == 0)
3403 {
4b7f6baa 3404 OUTS (outf, dregs (dst0));
086134ec 3405 OUTS (outf, " = BYTEOP2M (");
4b7f6baa
CM		 3406 OUTS (outf, dregs (src0 + 1));
3407 OUTS (outf, ":");
e1791cb8 3408 OUTS (outf, imm5d (src0));
086134ec 3409 OUTS (outf, ", ");
4b7f6baa
CM		 3410 OUTS (outf, dregs (src1 + 1));
3411 OUTS (outf, ":");
e1791cb8 3412 OUTS (outf, imm5d (src1));
086134ec 3413 OUTS (outf, ") (TL");
4b7f6baa
CM		 3414 if (s == 1)
3415 OUTS (outf, ", R)");
3416 else
3417 OUTS (outf, ")");
4b7f6baa
CM		 3418 }
3419 else if (aop == 2 && aopcde == 22 && HL == 1)
3420 {
4b7f6baa 3421 OUTS (outf, dregs (dst0));
086134ec 3422 OUTS (outf, " = BYTEOP2M (");
4b7f6baa
CM		 3423 OUTS (outf, dregs (src0 + 1));
3424 OUTS (outf, ":");
e1791cb8 3425 OUTS (outf, imm5d (src0));
086134ec 3426 OUTS (outf, ", ");
4b7f6baa
CM		 3427 OUTS (outf, dregs (src1 + 1));
3428 OUTS (outf, ":");
e1791cb8 3429 OUTS (outf, imm5d (src1));
086134ec 3430 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3431 if (s == 1)
3432 OUTS (outf, ", R)");
3433 else
3434 OUTS (outf, ")");
4b7f6baa
CM		 3435 }
3436 else if (aop == 2 && aopcde == 22 && HL == 0)
3437 {
4b7f6baa 3438 OUTS (outf, dregs (dst0));
086134ec 3439 OUTS (outf, " = BYTEOP2M (");
4b7f6baa
CM		 3440 OUTS (outf, dregs (src0 + 1));
3441 OUTS (outf, ":");
e1791cb8 3442 OUTS (outf, imm5d (src0));
086134ec 3443 OUTS (outf, ", ");
4b7f6baa
CM		 3444 OUTS (outf, dregs (src1 + 1));
3445 OUTS (outf, ":");
e1791cb8 3446 OUTS (outf, imm5d (src1));
086134ec 3447 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3448 if (s == 1)
3449 OUTS (outf, ", R)");
3450 else
3451 OUTS (outf, ")");
4b7f6baa
CM		 3452 }
3453 else if (aop == 1 && aopcde == 22 && HL == 1)
3454 {
4b7f6baa 3455 OUTS (outf, dregs (dst0));
086134ec 3456 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3457 OUTS (outf, dregs (src0 + 1));
3458 OUTS (outf, ":");
086134ec
BS		 3459 OUTS (outf, imm5d (src0));
3460 OUTS (outf, ", ");
4b7f6baa
CM		 3461 OUTS (outf, dregs (src1 + 1));
3462 OUTS (outf, ":");
086134ec
BS		 3463 OUTS (outf, imm5d (src1));
3464 OUTS (outf, ") (TH");
4b7f6baa
CM		 3465 if (s == 1)
3466 OUTS (outf, ", R)");
3467 else
3468 OUTS (outf, ")");
4b7f6baa
CM		 3469 }
3470 else if (aop == 1 && aopcde == 22 && HL == 0)
3471 {
4b7f6baa 3472 OUTS (outf, dregs (dst0));
086134ec 3473 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3474 OUTS (outf, dregs (src0 + 1));
3475 OUTS (outf, ":");
086134ec
BS		 3476 OUTS (outf, imm5d (src0));
3477 OUTS (outf, ", ");
4b7f6baa
CM		 3478 OUTS (outf, dregs (src1 + 1));
3479 OUTS (outf, ":");
086134ec
BS		 3480 OUTS (outf, imm5d (src1));
3481 OUTS (outf, ") (TL");
4b7f6baa
CM		 3482 if (s == 1)
3483 OUTS (outf, ", R)");
3484 else
3485 OUTS (outf, ")");
4b7f6baa
CM		 3486 }
3487 else if (aop == 0 && aopcde == 22 && HL == 1)
3488 {
4b7f6baa 3489 OUTS (outf, dregs (dst0));
086134ec 3490 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3491 OUTS (outf, dregs (src0 + 1));
3492 OUTS (outf, ":");
086134ec
BS		 3493 OUTS (outf, imm5d (src0));
3494 OUTS (outf, ", ");
4b7f6baa
CM		 3495 OUTS (outf, dregs (src1 + 1));
3496 OUTS (outf, ":");
086134ec
BS		 3497 OUTS (outf, imm5d (src1));
3498 OUTS (outf, ") (RNDH");
4b7f6baa
CM		 3499 if (s == 1)
3500 OUTS (outf, ", R)");
3501 else
3502 OUTS (outf, ")");
4b7f6baa
CM		 3503 }
3504 else if (aop == 0 && aopcde == 22 && HL == 0)
3505 {
4b7f6baa 3506 OUTS (outf, dregs (dst0));
086134ec 3507 OUTS (outf, " = BYTEOP2P (");
4b7f6baa
CM		 3508 OUTS (outf, dregs (src0 + 1));
3509 OUTS (outf, ":");
086134ec
BS		 3510 OUTS (outf, imm5d (src0));
3511 OUTS (outf, ", ");
4b7f6baa
CM		 3512 OUTS (outf, dregs (src1 + 1));
3513 OUTS (outf, ":");
086134ec
BS		 3514 OUTS (outf, imm5d (src1));
3515 OUTS (outf, ") (RNDL");
4b7f6baa
CM		 3516 if (s == 1)
3517 OUTS (outf, ", R)");
3518 else
3519 OUTS (outf, ")");
4b7f6baa
CM		 3520 }
3521 else if (aop == 0 && s == 0 && aopcde == 8)
086134ec 3522 OUTS (outf, "A0 = 0");
b7d48530 3523
4b7f6baa 3524 else if (aop == 0 && s == 1 && aopcde == 8)
086134ec 3525 OUTS (outf, "A0 = A0 (S)");
b7d48530 3526
4b7f6baa 3527 else if (aop == 1 && s == 0 && aopcde == 8)
086134ec 3528 OUTS (outf, "A1 = 0");
b7d48530 3529
4b7f6baa 3530 else if (aop == 1 && s == 1 && aopcde == 8)
086134ec 3531 OUTS (outf, "A1 = A1 (S)");
b7d48530 3532
4b7f6baa 3533 else if (aop == 2 && s == 0 && aopcde == 8)
086134ec 3534 OUTS (outf, "A1 = A0 = 0");
b7d48530 3535
4b7f6baa 3536 else if (aop == 2 && s == 1 && aopcde == 8)
086134ec 3537 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
b7d48530 3538
4b7f6baa 3539 else if (aop == 3 && s == 0 && aopcde == 8)
086134ec 3540 OUTS (outf, "A0 = A1");
b7d48530 3541
4b7f6baa 3542 else if (aop == 3 && s == 1 && aopcde == 8)
086134ec 3543 OUTS (outf, "A1 = A0");
b7d48530 3544
4b7f6baa
CM		 3545 else if (aop == 1 && aopcde == 9 && s == 0)
3546 {
086134ec 3547 OUTS (outf, "A0.X = ");
4b7f6baa 3548 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3549 }
3550 else if (aop == 1 && HL == 0 && aopcde == 11)
3551 {
4b7f6baa 3552 OUTS (outf, dregs_lo (dst0));
086134ec 3553 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3554 }
3555 else if (aop == 3 && HL == 0 && aopcde == 16)
086134ec 3556 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
b7d48530 3557
4b7f6baa
CM		 3558 else if (aop == 0 && aopcde == 23 && HL == 1)
3559 {
4b7f6baa 3560 OUTS (outf, dregs (dst0));
086134ec 3561 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3562 OUTS (outf, dregs (src0 + 1));
3563 OUTS (outf, ":");
086134ec
BS		 3564 OUTS (outf, imm5d (src0));
3565 OUTS (outf, ", ");
4b7f6baa
CM		 3566 OUTS (outf, dregs (src1 + 1));
3567 OUTS (outf, ":");
086134ec
BS		 3568 OUTS (outf, imm5d (src1));
3569 OUTS (outf, ") (HI");
4b7f6baa
CM		 3570 if (s == 1)
3571 OUTS (outf, ", R)");
3572 else
3573 OUTS (outf, ")");
4b7f6baa
CM		 3574 }
3575 else if (aop == 3 && aopcde == 9 && s == 0)
3576 {
086134ec 3577 OUTS (outf, "A1.X = ");
4b7f6baa 3578 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 3579 }
3580 else if (aop == 1 && HL == 1 && aopcde == 16)
086134ec 3581 OUTS (outf, "A1 = ABS A1");
b7d48530 3582
4b7f6baa 3583 else if (aop == 0 && HL == 1 && aopcde == 16)
086134ec 3584 OUTS (outf, "A1 = ABS A0");
b7d48530 3585
4b7f6baa
CM		 3586 else if (aop == 2 && aopcde == 9 && s == 1)
3587 {
086134ec 3588 OUTS (outf, "A1 = ");
4b7f6baa 3589 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3590 }
3591 else if (HL == 0 && aop == 3 && aopcde == 12)
3592 {
4b7f6baa 3593 OUTS (outf, dregs_lo (dst0));
086134ec 3594 OUTS (outf, " = ");
4b7f6baa 3595 OUTS (outf, dregs (src0));
086134ec 3596 OUTS (outf, " (RND)");
4b7f6baa
CM		 3597 }
3598 else if (aop == 1 && HL == 0 && aopcde == 16)
086134ec 3599 OUTS (outf, "A0 = ABS A1");
b7d48530 3600
4b7f6baa 3601 else if (aop == 0 && HL == 0 && aopcde == 16)
086134ec 3602 OUTS (outf, "A0 = ABS A0");
b7d48530 3603
4b7f6baa
CM		 3604 else if (aop == 3 && HL == 0 && aopcde == 15)
3605 {
4b7f6baa 3606 OUTS (outf, dregs (dst0));
086134ec 3607 OUTS (outf, " = -");
4b7f6baa 3608 OUTS (outf, dregs (src0));
086134ec 3609 OUTS (outf, " (V)");
4b7f6baa
CM		 3610 }
3611 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3612 {
4b7f6baa 3613 OUTS (outf, dregs (dst0));
086134ec 3614 OUTS (outf, " = -");
4b7f6baa 3615 OUTS (outf, dregs (src0));
086134ec 3616 OUTS (outf, " (S)");
4b7f6baa
CM		 3617 }
3618 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3619 {
4b7f6baa 3620 OUTS (outf, dregs (dst0));
086134ec 3621 OUTS (outf, " = -");
4b7f6baa 3622 OUTS (outf, dregs (src0));
086134ec 3623 OUTS (outf, " (NS)");
4b7f6baa
CM		 3624 }
3625 else if (aop == 1 && HL == 1 && aopcde == 11)
3626 {
4b7f6baa 3627 OUTS (outf, dregs_hi (dst0));
086134ec 3628 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3629 }
3630 else if (aop == 2 && aopcde == 11 && s == 0)
086134ec 3631 OUTS (outf, "A0 += A1");
b7d48530 3632
4b7f6baa 3633 else if (aop == 2 && aopcde == 11 && s == 1)
086134ec 3634 OUTS (outf, "A0 += A1 (W32)");
b7d48530 3635
4b7f6baa 3636 else if (aop == 3 && HL == 0 && aopcde == 14)
086134ec 3637 OUTS (outf, "A1 = -A1, A0 = -A0");
b7d48530 3638
4b7f6baa
CM		 3639 else if (HL == 1 && aop == 3 && aopcde == 12)
3640 {
4b7f6baa 3641 OUTS (outf, dregs_hi (dst0));
086134ec 3642 OUTS (outf, " = ");
4b7f6baa 3643 OUTS (outf, dregs (src0));
086134ec 3644 OUTS (outf, " (RND)");
4b7f6baa
CM		 3645 }
3646 else if (aop == 0 && aopcde == 23 && HL == 0)
3647 {
4b7f6baa 3648 OUTS (outf, dregs (dst0));
086134ec 3649 OUTS (outf, " = BYTEOP3P (");
4b7f6baa
CM		 3650 OUTS (outf, dregs (src0 + 1));
3651 OUTS (outf, ":");
086134ec
BS		 3652 OUTS (outf, imm5d (src0));
3653 OUTS (outf, ", ");
4b7f6baa
CM		 3654 OUTS (outf, dregs (src1 + 1));
3655 OUTS (outf, ":");
086134ec
BS		 3656 OUTS (outf, imm5d (src1));
3657 OUTS (outf, ") (LO");
4b7f6baa
CM		 3658 if (s == 1)
3659 OUTS (outf, ", R)");
3660 else
3661 OUTS (outf, ")");
4b7f6baa
CM		 3662 }
3663 else if (aop == 0 && HL == 0 && aopcde == 14)
086134ec 3664 OUTS (outf, "A0 = -A0");
b7d48530 3665
4b7f6baa 3666 else if (aop == 1 && HL == 0 && aopcde == 14)
086134ec 3667 OUTS (outf, "A0 = -A1");
b7d48530 3668
4b7f6baa 3669 else if (aop == 0 && HL == 1 && aopcde == 14)
086134ec 3670 OUTS (outf, "A1 = -A0");
b7d48530 3671
4b7f6baa 3672 else if (aop == 1 && HL == 1 && aopcde == 14)
086134ec 3673 OUTS (outf, "A1 = -A1");
b7d48530 3674
4b7f6baa
CM		 3675 else if (aop == 0 && aopcde == 12)
3676 {
4b7f6baa 3677 OUTS (outf, dregs_hi (dst0));
086134ec 3678 OUTS (outf, " = ");
4b7f6baa 3679 OUTS (outf, dregs_lo (dst0));
086134ec 3680 OUTS (outf, " = SIGN (");
4b7f6baa 3681 OUTS (outf, dregs_hi (src0));
086134ec 3682 OUTS (outf, ") * ");
4b7f6baa 3683 OUTS (outf, dregs_hi (src1));
086134ec 3684 OUTS (outf, " + SIGN (");
4b7f6baa 3685 OUTS (outf, dregs_lo (src0));
086134ec 3686 OUTS (outf, ") * ");
4b7f6baa 3687 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 3688 }
3689 else if (aop == 2 && aopcde == 0)
3690 {
4b7f6baa 3691 OUTS (outf, dregs (dst0));
086134ec 3692 OUTS (outf, " = ");
4b7f6baa 3693 OUTS (outf, dregs (src0));
086134ec 3694 OUTS (outf, " -|+ ");
4b7f6baa 3695 OUTS (outf, dregs (src1));
4b7f6baa 3696 amod0 (s, x, outf);
4b7f6baa
CM		 3697 }
3698 else if (aop == 1 && aopcde == 12)
3699 {
4b7f6baa 3700 OUTS (outf, dregs (dst1));
086134ec 3701 OUTS (outf, " = A1.L + A1.H, ");
4b7f6baa 3702 OUTS (outf, dregs (dst0));
086134ec 3703 OUTS (outf, " = A0.L + A0.H");
4b7f6baa
CM		 3704 }
3705 else if (aop == 2 && aopcde == 4)
3706 {
4b7f6baa 3707 OUTS (outf, dregs (dst1));
086134ec 3708 OUTS (outf, " = ");
4b7f6baa 3709 OUTS (outf, dregs (src0));
086134ec 3710 OUTS (outf, " + ");
4b7f6baa 3711 OUTS (outf, dregs (src1));
086134ec 3712 OUTS (outf, ", ");
4b7f6baa 3713 OUTS (outf, dregs (dst0));
086134ec 3714 OUTS (outf, " = ");
4b7f6baa 3715 OUTS (outf, dregs (src0));
086134ec 3716 OUTS (outf, " - ");
4b7f6baa 3717 OUTS (outf, dregs (src1));
4b7f6baa 3718 amod1 (s, x, outf);
4b7f6baa
CM		 3719 }
3720 else if (HL == 0 && aopcde == 1)
3721 {
4b7f6baa 3722 OUTS (outf, dregs (dst1));
086134ec 3723 OUTS (outf, " = ");
4b7f6baa 3724 OUTS (outf, dregs (src0));
086134ec 3725 OUTS (outf, " +|+ ");
4b7f6baa 3726 OUTS (outf, dregs (src1));
086134ec 3727 OUTS (outf, ", ");
4b7f6baa 3728 OUTS (outf, dregs (dst0));
086134ec 3729 OUTS (outf, " = ");
4b7f6baa 3730 OUTS (outf, dregs (src0));
086134ec 3731 OUTS (outf, " -|- ");
4b7f6baa
CM		 3732 OUTS (outf, dregs (src1));
3733 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3734 }
3735 else if (aop == 0 && aopcde == 11)
3736 {
4b7f6baa 3737 OUTS (outf, dregs (dst0));
086134ec 3738 OUTS (outf, " = (A0 += A1)");
4b7f6baa
CM		 3739 }
3740 else if (aop == 0 && aopcde == 10)
3741 {
4b7f6baa 3742 OUTS (outf, dregs_lo (dst0));
086134ec 3743 OUTS (outf, " = A0.X");
4b7f6baa
CM		 3744 }
3745 else if (aop == 1 && aopcde == 10)
3746 {
4b7f6baa 3747 OUTS (outf, dregs_lo (dst0));
086134ec 3748 OUTS (outf, " = A1.X");
4b7f6baa
CM		 3749 }
3750 else if (aop == 1 && aopcde == 0)
3751 {
4b7f6baa 3752 OUTS (outf, dregs (dst0));
086134ec 3753 OUTS (outf, " = ");
4b7f6baa 3754 OUTS (outf, dregs (src0));
086134ec 3755 OUTS (outf, " +|- ");
4b7f6baa 3756 OUTS (outf, dregs (src1));
4b7f6baa 3757 amod0 (s, x, outf);
4b7f6baa
CM		 3758 }
3759 else if (aop == 3 && aopcde == 0)
3760 {
4b7f6baa 3761 OUTS (outf, dregs (dst0));
086134ec 3762 OUTS (outf, " = ");
4b7f6baa 3763 OUTS (outf, dregs (src0));
086134ec 3764 OUTS (outf, " -|- ");
4b7f6baa 3765 OUTS (outf, dregs (src1));
4b7f6baa 3766 amod0 (s, x, outf);
4b7f6baa
CM		 3767 }
3768 else if (aop == 1 && aopcde == 4)
3769 {
4b7f6baa 3770 OUTS (outf, dregs (dst0));
086134ec 3771 OUTS (outf, " = ");
4b7f6baa 3772 OUTS (outf, dregs (src0));
086134ec 3773 OUTS (outf, " - ");
4b7f6baa 3774 OUTS (outf, dregs (src1));
4b7f6baa 3775 amod1 (s, x, outf);
4b7f6baa
CM		 3776 }
3777 else if (aop == 0 && aopcde == 17)
3778 {
4b7f6baa 3779 OUTS (outf, dregs (dst1));
086134ec 3780 OUTS (outf, " = A1 + A0, ");
4b7f6baa 3781 OUTS (outf, dregs (dst0));
086134ec 3782 OUTS (outf, " = A1 - A0");
4b7f6baa 3783 amod1 (s, x, outf);
4b7f6baa
CM		 3784 }
3785 else if (aop == 1 && aopcde == 17)
3786 {
4b7f6baa 3787 OUTS (outf, dregs (dst1));
086134ec 3788 OUTS (outf, " = A0 + A1, ");
4b7f6baa 3789 OUTS (outf, dregs (dst0));
086134ec 3790 OUTS (outf, " = A0 - A1");
4b7f6baa 3791 amod1 (s, x, outf);
4b7f6baa
CM		 3792 }
3793 else if (aop == 0 && aopcde == 18)
3794 {
086134ec 3795 OUTS (outf, "SAA (");
4b7f6baa
CM		 3796 OUTS (outf, dregs (src0 + 1));
3797 OUTS (outf, ":");
086134ec
BS		 3798 OUTS (outf, imm5d (src0));
3799 OUTS (outf, ", ");
4b7f6baa
CM		 3800 OUTS (outf, dregs (src1 + 1));
3801 OUTS (outf, ":");
086134ec
BS		 3802 OUTS (outf, imm5d (src1));
3803 OUTS (outf, ")");
4b7f6baa 3804 aligndir (s, outf);
4b7f6baa
CM		 3805 }
3806 else if (aop == 3 && aopcde == 18)
b7d48530
NC		 3807 OUTS (outf, "DISALGNEXCPT");
3808
4b7f6baa
CM		 3809 else if (aop == 0 && aopcde == 20)
3810 {
4b7f6baa 3811 OUTS (outf, dregs (dst0));
086134ec 3812 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3813 OUTS (outf, dregs (src0 + 1));
3814 OUTS (outf, ":");
086134ec
BS		 3815 OUTS (outf, imm5d (src0));
3816 OUTS (outf, ", ");
4b7f6baa
CM		 3817 OUTS (outf, dregs (src1 + 1));
3818 OUTS (outf, ":");
086134ec 3819 OUTS (outf, imm5d (src1));
4b7f6baa
CM		 3820 OUTS (outf, ")");
3821 aligndir (s, outf);
4b7f6baa
CM		 3822 }
3823 else if (aop == 1 && aopcde == 20)
3824 {
4b7f6baa 3825 OUTS (outf, dregs (dst0));
086134ec 3826 OUTS (outf, " = BYTEOP1P (");
4b7f6baa
CM		 3827 OUTS (outf, dregs (src0 + 1));
3828 OUTS (outf, ":");
086134ec
BS		 3829 OUTS (outf, imm5d (src0));
3830 OUTS (outf, ", ");
4b7f6baa
CM		 3831 OUTS (outf, dregs (src1 + 1));
3832 OUTS (outf, ":");
086134ec
BS		 3833 OUTS (outf, imm5d (src1));
3834 OUTS (outf, ") (T");
4b7f6baa
CM		 3835 if (s == 1)
3836 OUTS (outf, ", R)");
3837 else
3838 OUTS (outf, ")");
4b7f6baa
CM		 3839 }
3840 else if (aop == 0 && aopcde == 21)
3841 {
4b7f6baa
CM		 3842 OUTS (outf, "(");
3843 OUTS (outf, dregs (dst1));
086134ec 3844 OUTS (outf, ", ");
4b7f6baa 3845 OUTS (outf, dregs (dst0));
086134ec 3846 OUTS (outf, ") = BYTEOP16P (");
4b7f6baa
CM		 3847 OUTS (outf, dregs (src0 + 1));
3848 OUTS (outf, ":");
086134ec
BS		 3849 OUTS (outf, imm5d (src0));
3850 OUTS (outf, ", ");
4b7f6baa
CM		 3851 OUTS (outf, dregs (src1 + 1));
3852 OUTS (outf, ":");
086134ec
BS		 3853 OUTS (outf, imm5d (src1));
3854 OUTS (outf, ")");
4b7f6baa 3855 aligndir (s, outf);
4b7f6baa
CM		 3856 }
3857 else if (aop == 1 && aopcde == 21)
3858 {
4b7f6baa
CM		 3859 OUTS (outf, "(");
3860 OUTS (outf, dregs (dst1));
086134ec 3861 OUTS (outf, ", ");
4b7f6baa 3862 OUTS (outf, dregs (dst0));
086134ec 3863 OUTS (outf, ") = BYTEOP16M (");
4b7f6baa
CM		 3864 OUTS (outf, dregs (src0 + 1));
3865 OUTS (outf, ":");
086134ec
BS		 3866 OUTS (outf, imm5d (src0));
3867 OUTS (outf, ", ");
4b7f6baa
CM		 3868 OUTS (outf, dregs (src1 + 1));
3869 OUTS (outf, ":");
086134ec
BS		 3870 OUTS (outf, imm5d (src1));
3871 OUTS (outf, ")");
4b7f6baa 3872 aligndir (s, outf);
4b7f6baa
CM		 3873 }
3874 else if (aop == 2 && aopcde == 7)
3875 {
4b7f6baa 3876 OUTS (outf, dregs (dst0));
086134ec 3877 OUTS (outf, " = ABS ");
4b7f6baa 3878 OUTS (outf, dregs (src0));
4b7f6baa
CM		 3879 }
3880 else if (aop == 1 && aopcde == 7)
3881 {
4b7f6baa 3882 OUTS (outf, dregs (dst0));
086134ec 3883 OUTS (outf, " = MIN (");
4b7f6baa 3884 OUTS (outf, dregs (src0));
086134ec 3885 OUTS (outf, ", ");
4b7f6baa
CM		 3886 OUTS (outf, dregs (src1));
3887 OUTS (outf, ")");
4b7f6baa
CM		 3888 }
3889 else if (aop == 0 && aopcde == 7)
3890 {
4b7f6baa 3891 OUTS (outf, dregs (dst0));
086134ec 3892 OUTS (outf, " = MAX (");
4b7f6baa 3893 OUTS (outf, dregs (src0));
086134ec 3894 OUTS (outf, ", ");
4b7f6baa
CM		 3895 OUTS (outf, dregs (src1));
3896 OUTS (outf, ")");
4b7f6baa
CM		 3897 }
3898 else if (aop == 2 && aopcde == 6)
3899 {
4b7f6baa 3900 OUTS (outf, dregs (dst0));
086134ec 3901 OUTS (outf, " = ABS ");
4b7f6baa 3902 OUTS (outf, dregs (src0));
086134ec 3903 OUTS (outf, " (V)");
4b7f6baa
CM		 3904 }
3905 else if (aop == 1 && aopcde == 6)
3906 {
4b7f6baa 3907 OUTS (outf, dregs (dst0));
086134ec 3908 OUTS (outf, " = MIN (");
4b7f6baa 3909 OUTS (outf, dregs (src0));
086134ec 3910 OUTS (outf, ", ");
4b7f6baa 3911 OUTS (outf, dregs (src1));
086134ec 3912 OUTS (outf, ") (V)");
4b7f6baa
CM		 3913 }
3914 else if (aop == 0 && aopcde == 6)
3915 {
4b7f6baa 3916 OUTS (outf, dregs (dst0));
086134ec 3917 OUTS (outf, " = MAX (");
4b7f6baa 3918 OUTS (outf, dregs (src0));
086134ec 3919 OUTS (outf, ", ");
4b7f6baa 3920 OUTS (outf, dregs (src1));
086134ec 3921 OUTS (outf, ") (V)");
4b7f6baa
CM		 3922 }
3923 else if (HL == 1 && aopcde == 1)
3924 {
4b7f6baa 3925 OUTS (outf, dregs (dst1));
086134ec 3926 OUTS (outf, " = ");
4b7f6baa 3927 OUTS (outf, dregs (src0));
086134ec 3928 OUTS (outf, " +|- ");
4b7f6baa 3929 OUTS (outf, dregs (src1));
086134ec 3930 OUTS (outf, ", ");
4b7f6baa 3931 OUTS (outf, dregs (dst0));
086134ec 3932 OUTS (outf, " = ");
4b7f6baa 3933 OUTS (outf, dregs (src0));
086134ec 3934 OUTS (outf, " -|+ ");
4b7f6baa
CM		 3935 OUTS (outf, dregs (src1));
3936 amod0amod2 (s, x, aop, outf);
4b7f6baa
CM		 3937 }
3938 else if (aop == 0 && aopcde == 4)
3939 {
4b7f6baa 3940 OUTS (outf, dregs (dst0));
086134ec 3941 OUTS (outf, " = ");
4b7f6baa 3942 OUTS (outf, dregs (src0));
086134ec 3943 OUTS (outf, " + ");
4b7f6baa 3944 OUTS (outf, dregs (src1));
4b7f6baa 3945 amod1 (s, x, outf);
4b7f6baa
CM		 3946 }
3947 else if (aop == 0 && aopcde == 0)
3948 {
4b7f6baa 3949 OUTS (outf, dregs (dst0));
086134ec 3950 OUTS (outf, " = ");
4b7f6baa 3951 OUTS (outf, dregs (src0));
086134ec 3952 OUTS (outf, " +|+ ");
4b7f6baa 3953 OUTS (outf, dregs (src1));
4b7f6baa 3954 amod0 (s, x, outf);
4b7f6baa
CM		 3955 }
3956 else if (aop == 0 && aopcde == 24)
3957 {
4b7f6baa 3958 OUTS (outf, dregs (dst0));
086134ec 3959 OUTS (outf, " = BYTEPACK (");
4b7f6baa 3960 OUTS (outf, dregs (src0));
086134ec 3961 OUTS (outf, ", ");
4b7f6baa
CM		 3962 OUTS (outf, dregs (src1));
3963 OUTS (outf, ")");
4b7f6baa
CM		 3964 }
3965 else if (aop == 1 && aopcde == 24)
3966 {
4b7f6baa
CM		 3967 OUTS (outf, "(");
3968 OUTS (outf, dregs (dst1));
086134ec 3969 OUTS (outf, ", ");
4b7f6baa
CM		 3970 OUTS (outf, dregs (dst0));
3971 OUTS (outf, ") = BYTEUNPACK ");
3972 OUTS (outf, dregs (src0 + 1));
3973 OUTS (outf, ":");
086134ec 3974 OUTS (outf, imm5d (src0));
4b7f6baa 3975 aligndir (s, outf);
4b7f6baa
CM		 3976 }
3977 else if (aopcde == 13)
3978 {
4b7f6baa
CM		 3979 OUTS (outf, "(");
3980 OUTS (outf, dregs (dst1));
086134ec 3981 OUTS (outf, ", ");
4b7f6baa
CM		 3982 OUTS (outf, dregs (dst0));
3983 OUTS (outf, ") = SEARCH ");
3984 OUTS (outf, dregs (src0));
086134ec 3985 OUTS (outf, " (");
4b7f6baa
CM		 3986 searchmod (aop, outf);
3987 OUTS (outf, ")");
4b7f6baa
CM		 3988 }
3989 else
b7d48530
NC		 3990 return 0;
3991
3992 return 4;
4b7f6baa
CM		 3993}
3994
3995static int
3996decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3997{
b7d48530
NC		 3998 /* dsp32shift
3999 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4000 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
4001 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
4002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4003 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
4004 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
4005 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
4006 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
4007 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
4008 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
4009 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
4010
4b7f6baa
CM		 4011 if (HLs == 0 && sop == 0 && sopcde == 0)
4012 {
4b7f6baa 4013 OUTS (outf, dregs_lo (dst0));
086134ec 4014 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4015 OUTS (outf, dregs_lo (src1));
4016 OUTS (outf, " BY ");
4017 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4018 }
4019 else if (HLs == 1 && sop == 0 && sopcde == 0)
4020 {
4b7f6baa 4021 OUTS (outf, dregs_lo (dst0));
086134ec 4022 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4023 OUTS (outf, dregs_hi (src1));
4024 OUTS (outf, " BY ");
4025 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4026 }
4027 else if (HLs == 2 && sop == 0 && sopcde == 0)
4028 {
4b7f6baa 4029 OUTS (outf, dregs_hi (dst0));
086134ec 4030 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4031 OUTS (outf, dregs_lo (src1));
4032 OUTS (outf, " BY ");
4033 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4034 }
4035 else if (HLs == 3 && sop == 0 && sopcde == 0)
4036 {
4b7f6baa 4037 OUTS (outf, dregs_hi (dst0));
086134ec 4038 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4039 OUTS (outf, dregs_hi (src1));
4040 OUTS (outf, " BY ");
4041 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4042 }
4043 else if (HLs == 0 && sop == 1 && sopcde == 0)
4044 {
4b7f6baa 4045 OUTS (outf, dregs_lo (dst0));
086134ec 4046 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4047 OUTS (outf, dregs_lo (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
086134ec 4050 OUTS (outf, " (S)");
4b7f6baa
CM		 4051 }
4052 else if (HLs == 1 && sop == 1 && sopcde == 0)
4053 {
4b7f6baa 4054 OUTS (outf, dregs_lo (dst0));
086134ec 4055 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4056 OUTS (outf, dregs_hi (src1));
4057 OUTS (outf, " BY ");
4058 OUTS (outf, dregs_lo (src0));
086134ec 4059 OUTS (outf, " (S)");
4b7f6baa
CM		 4060 }
4061 else if (HLs == 2 && sop == 1 && sopcde == 0)
4062 {
4b7f6baa 4063 OUTS (outf, dregs_hi (dst0));
086134ec 4064 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4065 OUTS (outf, dregs_lo (src1));
4066 OUTS (outf, " BY ");
4067 OUTS (outf, dregs_lo (src0));
086134ec 4068 OUTS (outf, " (S)");
4b7f6baa
CM		 4069 }
4070 else if (HLs == 3 && sop == 1 && sopcde == 0)
4071 {
4b7f6baa 4072 OUTS (outf, dregs_hi (dst0));
086134ec 4073 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4074 OUTS (outf, dregs_hi (src1));
4075 OUTS (outf, " BY ");
4076 OUTS (outf, dregs_lo (src0));
086134ec 4077 OUTS (outf, " (S)");
4b7f6baa
CM		 4078 }
4079 else if (sop == 2 && sopcde == 0)
4080 {
4b7f6baa 4081 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
086134ec 4082 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4083 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4084 OUTS (outf, " BY ");
4085 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4086 }
4087 else if (sop == 0 && sopcde == 3)
4088 {
4b7f6baa 4089 OUTS (outf, acc01);
086134ec 4090 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4091 OUTS (outf, acc01);
4092 OUTS (outf, " BY ");
4093 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4094 }
4095 else if (sop == 1 && sopcde == 3)
4096 {
4b7f6baa 4097 OUTS (outf, acc01);
086134ec 4098 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4099 OUTS (outf, acc01);
4100 OUTS (outf, " BY ");
4101 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4102 }
4103 else if (sop == 2 && sopcde == 3)
4104 {
4b7f6baa 4105 OUTS (outf, acc01);
086134ec 4106 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4107 OUTS (outf, acc01);
4108 OUTS (outf, " BY ");
4109 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4110 }
4111 else if (sop == 3 && sopcde == 3)
4112 {
4b7f6baa 4113 OUTS (outf, dregs (dst0));
086134ec 4114 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4115 OUTS (outf, dregs (src1));
4116 OUTS (outf, " BY ");
4117 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4118 }
4119 else if (sop == 1 && sopcde == 1)
4120 {
4b7f6baa 4121 OUTS (outf, dregs (dst0));
086134ec 4122 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4123 OUTS (outf, dregs (src1));
4124 OUTS (outf, " BY ");
4125 OUTS (outf, dregs_lo (src0));
086134ec 4126 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4127 }
4128 else if (sop == 0 && sopcde == 1)
4129 {
4b7f6baa 4130 OUTS (outf, dregs (dst0));
086134ec 4131 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4132 OUTS (outf, dregs (src1));
4133 OUTS (outf, " BY ");
4134 OUTS (outf, dregs_lo (src0));
086134ec 4135 OUTS (outf, " (V)");
4b7f6baa
CM		 4136 }
4137 else if (sop == 0 && sopcde == 2)
4138 {
4b7f6baa 4139 OUTS (outf, dregs (dst0));
086134ec 4140 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4141 OUTS (outf, dregs (src1));
4142 OUTS (outf, " BY ");
4143 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4144 }
4145 else if (sop == 1 && sopcde == 2)
4146 {
4b7f6baa 4147 OUTS (outf, dregs (dst0));
086134ec 4148 OUTS (outf, " = ASHIFT ");
4b7f6baa
CM		 4149 OUTS (outf, dregs (src1));
4150 OUTS (outf, " BY ");
4151 OUTS (outf, dregs_lo (src0));
086134ec 4152 OUTS (outf, " (S)");
4b7f6baa
CM		 4153 }
4154 else if (sop == 2 && sopcde == 2)
4155 {
4b7f6baa 4156 OUTS (outf, dregs (dst0));
59a82d23 4157 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4158 OUTS (outf, dregs (src1));
4159 OUTS (outf, " BY ");
4160 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4161 }
4162 else if (sop == 3 && sopcde == 2)
4163 {
4b7f6baa 4164 OUTS (outf, dregs (dst0));
086134ec 4165 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4166 OUTS (outf, dregs (src1));
4167 OUTS (outf, " BY ");
4168 OUTS (outf, dregs_lo (src0));
4b7f6baa
CM		 4169 }
4170 else if (sop == 2 && sopcde == 1)
4171 {
4b7f6baa 4172 OUTS (outf, dregs (dst0));
59a82d23 4173 OUTS (outf, " = LSHIFT ");
4b7f6baa
CM		 4174 OUTS (outf, dregs (src1));
4175 OUTS (outf, " BY ");
4176 OUTS (outf, dregs_lo (src0));
086134ec 4177 OUTS (outf, " (V)");
4b7f6baa
CM		 4178 }
4179 else if (sop == 0 && sopcde == 4)
4180 {
4b7f6baa 4181 OUTS (outf, dregs (dst0));
086134ec 4182 OUTS (outf, " = PACK (");
4b7f6baa 4183 OUTS (outf, dregs_lo (src1));
086134ec 4184 OUTS (outf, ", ");
4b7f6baa
CM		 4185 OUTS (outf, dregs_lo (src0));
4186 OUTS (outf, ")");
4b7f6baa
CM		 4187 }
4188 else if (sop == 1 && sopcde == 4)
4189 {
4b7f6baa 4190 OUTS (outf, dregs (dst0));
086134ec 4191 OUTS (outf, " = PACK (");
4b7f6baa 4192 OUTS (outf, dregs_lo (src1));
086134ec 4193 OUTS (outf, ", ");
4b7f6baa
CM		 4194 OUTS (outf, dregs_hi (src0));
4195 OUTS (outf, ")");
4b7f6baa
CM		 4196 }
4197 else if (sop == 2 && sopcde == 4)
4198 {
4b7f6baa 4199 OUTS (outf, dregs (dst0));
086134ec 4200 OUTS (outf, " = PACK (");
4b7f6baa 4201 OUTS (outf, dregs_hi (src1));
086134ec 4202 OUTS (outf, ", ");
4b7f6baa
CM		 4203 OUTS (outf, dregs_lo (src0));
4204 OUTS (outf, ")");
4b7f6baa
CM		 4205 }
4206 else if (sop == 3 && sopcde == 4)
4207 {
4b7f6baa 4208 OUTS (outf, dregs (dst0));
086134ec 4209 OUTS (outf, " = PACK (");
4b7f6baa 4210 OUTS (outf, dregs_hi (src1));
086134ec 4211 OUTS (outf, ", ");
4b7f6baa
CM		 4212 OUTS (outf, dregs_hi (src0));
4213 OUTS (outf, ")");
4b7f6baa
CM		 4214 }
4215 else if (sop == 0 && sopcde == 5)
4216 {
4b7f6baa 4217 OUTS (outf, dregs_lo (dst0));
086134ec 4218 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4219 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4220 }
4221 else if (sop == 1 && sopcde == 5)
4222 {
4b7f6baa 4223 OUTS (outf, dregs_lo (dst0));
086134ec 4224 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4225 OUTS (outf, dregs_lo (src1));
4b7f6baa
CM		 4226 }
4227 else if (sop == 2 && sopcde == 5)
4228 {
4b7f6baa 4229 OUTS (outf, dregs_lo (dst0));
086134ec 4230 OUTS (outf, " = SIGNBITS ");
4b7f6baa 4231 OUTS (outf, dregs_hi (src1));
4b7f6baa
CM		 4232 }
4233 else if (sop == 0 && sopcde == 6)
4234 {
4b7f6baa 4235 OUTS (outf, dregs_lo (dst0));
086134ec 4236 OUTS (outf, " = SIGNBITS A0");
4b7f6baa
CM		 4237 }
4238 else if (sop == 1 && sopcde == 6)
4239 {
4b7f6baa 4240 OUTS (outf, dregs_lo (dst0));
086134ec 4241 OUTS (outf, " = SIGNBITS A1");
4b7f6baa
CM		 4242 }
4243 else if (sop == 3 && sopcde == 6)
4244 {
4b7f6baa 4245 OUTS (outf, dregs_lo (dst0));
086134ec 4246 OUTS (outf, " = ONES ");
4b7f6baa 4247 OUTS (outf, dregs (src1));
4b7f6baa
CM		 4248 }
4249 else if (sop == 0 && sopcde == 7)
4250 {
4b7f6baa 4251 OUTS (outf, dregs_lo (dst0));
086134ec 4252 OUTS (outf, " = EXPADJ (");
4b7f6baa 4253 OUTS (outf, dregs (src1));
086134ec 4254 OUTS (outf, ", ");
4b7f6baa
CM		 4255 OUTS (outf, dregs_lo (src0));
4256 OUTS (outf, ")");
4b7f6baa
CM		 4257 }
4258 else if (sop == 1 && sopcde == 7)
4259 {
4b7f6baa 4260 OUTS (outf, dregs_lo (dst0));
086134ec 4261 OUTS (outf, " = EXPADJ (");
4b7f6baa 4262 OUTS (outf, dregs (src1));
086134ec 4263 OUTS (outf, ", ");
4b7f6baa
CM		 4264 OUTS (outf, dregs_lo (src0));
4265 OUTS (outf, ") (V)");
4b7f6baa
CM		 4266 }
4267 else if (sop == 2 && sopcde == 7)
4268 {
4b7f6baa 4269 OUTS (outf, dregs_lo (dst0));
086134ec 4270 OUTS (outf, " = EXPADJ (");
4b7f6baa 4271 OUTS (outf, dregs_lo (src1));
086134ec 4272 OUTS (outf, ", ");
4b7f6baa
CM		 4273 OUTS (outf, dregs_lo (src0));
4274 OUTS (outf, ")");
4b7f6baa
CM		 4275 }
4276 else if (sop == 3 && sopcde == 7)
4277 {
4b7f6baa 4278 OUTS (outf, dregs_lo (dst0));
086134ec 4279 OUTS (outf, " = EXPADJ (");
4b7f6baa 4280 OUTS (outf, dregs_hi (src1));
086134ec 4281 OUTS (outf, ", ");
4b7f6baa
CM		 4282 OUTS (outf, dregs_lo (src0));
4283 OUTS (outf, ")");
4b7f6baa
CM		 4284 }
4285 else if (sop == 0 && sopcde == 8)
4286 {
4b7f6baa
CM		 4287 OUTS (outf, "BITMUX (");
4288 OUTS (outf, dregs (src0));
086134ec 4289 OUTS (outf, ", ");
4b7f6baa 4290 OUTS (outf, dregs (src1));
086134ec 4291 OUTS (outf, ", A0) (ASR)");
4b7f6baa
CM		 4292 }
4293 else if (sop == 1 && sopcde == 8)
4294 {
4b7f6baa
CM		 4295 OUTS (outf, "BITMUX (");
4296 OUTS (outf, dregs (src0));
086134ec 4297 OUTS (outf, ", ");
4b7f6baa 4298 OUTS (outf, dregs (src1));
086134ec 4299 OUTS (outf, ", A0) (ASL)");
4b7f6baa
CM		 4300 }
4301 else if (sop == 0 && sopcde == 9)
4302 {
4b7f6baa 4303 OUTS (outf, dregs_lo (dst0));
086134ec 4304 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4305 OUTS (outf, dregs (src1));
4306 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4307 }
4308 else if (sop == 1 && sopcde == 9)
4309 {
4b7f6baa 4310 OUTS (outf, dregs_lo (dst0));
086134ec 4311 OUTS (outf, " = VIT_MAX (");
4b7f6baa
CM		 4312 OUTS (outf, dregs (src1));
4313 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4314 }
4315 else if (sop == 2 && sopcde == 9)
4316 {
4b7f6baa 4317 OUTS (outf, dregs (dst0));
086134ec 4318 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4319 OUTS (outf, dregs (src1));
086134ec 4320 OUTS (outf, ", ");
4b7f6baa 4321 OUTS (outf, dregs (src0));
086134ec 4322 OUTS (outf, ") (ASL)");
4b7f6baa
CM		 4323 }
4324 else if (sop == 3 && sopcde == 9)
4325 {
4b7f6baa 4326 OUTS (outf, dregs (dst0));
086134ec 4327 OUTS (outf, " = VIT_MAX (");
4b7f6baa 4328 OUTS (outf, dregs (src1));
086134ec 4329 OUTS (outf, ", ");
4b7f6baa 4330 OUTS (outf, dregs (src0));
086134ec 4331 OUTS (outf, ") (ASR)");
4b7f6baa
CM		 4332 }
4333 else if (sop == 0 && sopcde == 10)
4334 {
4b7f6baa 4335 OUTS (outf, dregs (dst0));
086134ec 4336 OUTS (outf, " = EXTRACT (");
4b7f6baa 4337 OUTS (outf, dregs (src1));
086134ec 4338 OUTS (outf, ", ");
4b7f6baa
CM		 4339 OUTS (outf, dregs_lo (src0));
4340 OUTS (outf, ") (Z)");
4b7f6baa
CM		 4341 }
4342 else if (sop == 1 && sopcde == 10)
4343 {
4b7f6baa 4344 OUTS (outf, dregs (dst0));
086134ec 4345 OUTS (outf, " = EXTRACT (");
4b7f6baa 4346 OUTS (outf, dregs (src1));
086134ec 4347 OUTS (outf, ", ");
4b7f6baa 4348 OUTS (outf, dregs_lo (src0));
086134ec 4349 OUTS (outf, ") (X)");
4b7f6baa
CM		 4350 }
4351 else if (sop == 2 && sopcde == 10)
4352 {
4b7f6baa 4353 OUTS (outf, dregs (dst0));
086134ec 4354 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4355 OUTS (outf, dregs (src1));
086134ec 4356 OUTS (outf, ", ");
4b7f6baa
CM		 4357 OUTS (outf, dregs (src0));
4358 OUTS (outf, ")");
4b7f6baa
CM		 4359 }
4360 else if (sop == 3 && sopcde == 10)
4361 {
4b7f6baa 4362 OUTS (outf, dregs (dst0));
086134ec 4363 OUTS (outf, " = DEPOSIT (");
4b7f6baa 4364 OUTS (outf, dregs (src1));
086134ec 4365 OUTS (outf, ", ");
4b7f6baa 4366 OUTS (outf, dregs (src0));
086134ec 4367 OUTS (outf, ") (X)");
4b7f6baa
CM		 4368 }
4369 else if (sop == 0 && sopcde == 11)
4370 {
4b7f6baa 4371 OUTS (outf, dregs_lo (dst0));
086134ec 4372 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4b7f6baa
CM		 4373 OUTS (outf, dregs (src0));
4374 OUTS (outf, ")");
4b7f6baa
CM		 4375 }
4376 else if (sop == 1 && sopcde == 11)
4377 {
4b7f6baa 4378 OUTS (outf, dregs_lo (dst0));
086134ec 4379 OUTS (outf, " = CC = BXOR (A0, ");
4b7f6baa
CM		 4380 OUTS (outf, dregs (src0));
4381 OUTS (outf, ")");
4b7f6baa
CM		 4382 }
4383 else if (sop == 0 && sopcde == 12)
086134ec 4384 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
b7d48530 4385
4b7f6baa
CM		 4386 else if (sop == 1 && sopcde == 12)
4387 {
4b7f6baa 4388 OUTS (outf, dregs_lo (dst0));
086134ec 4389 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4b7f6baa
CM		 4390 }
4391 else if (sop == 0 && sopcde == 13)
4392 {
4b7f6baa 4393 OUTS (outf, dregs (dst0));
086134ec 4394 OUTS (outf, " = ALIGN8 (");
4b7f6baa 4395 OUTS (outf, dregs (src1));
086134ec 4396 OUTS (outf, ", ");
4b7f6baa
CM		 4397 OUTS (outf, dregs (src0));
4398 OUTS (outf, ")");
4b7f6baa
CM		 4399 }
4400 else if (sop == 1 && sopcde == 13)
4401 {
4b7f6baa 4402 OUTS (outf, dregs (dst0));
086134ec 4403 OUTS (outf, " = ALIGN16 (");
4b7f6baa 4404 OUTS (outf, dregs (src1));
086134ec 4405 OUTS (outf, ", ");
4b7f6baa
CM		 4406 OUTS (outf, dregs (src0));
4407 OUTS (outf, ")");
4b7f6baa
CM		 4408 }
4409 else if (sop == 2 && sopcde == 13)
4410 {
4b7f6baa 4411 OUTS (outf, dregs (dst0));
086134ec 4412 OUTS (outf, " = ALIGN24 (");
4b7f6baa 4413 OUTS (outf, dregs (src1));
086134ec 4414 OUTS (outf, ", ");
4b7f6baa
CM		 4415 OUTS (outf, dregs (src0));
4416 OUTS (outf, ")");
4b7f6baa
CM		 4417 }
4418 else
b7d48530
NC		 4419 return 0;
4420
4421 return 4;
4b7f6baa
CM		 4422}
4423
4424static int
4425decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4426{
b7d48530
NC		 4427 /* dsp32shiftimm
4428 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4429 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4430 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4431 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4432 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4433 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4434 int bit8 = ((iw1 >> 8) & 0x1);
4435 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4b7f6baa 4436 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
b7d48530
NC		 4437 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4438 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4439 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4b7f6baa
CM		 4440
4441
331f1cbe 4442 if (sop == 0 && sopcde == 0)
4b7f6baa 4443 {
331f1cbe
BS		 4444 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4445 OUTS (outf, " = ");
4446 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4447 OUTS (outf, " >>> ");
4b7f6baa 4448 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4449 }
331f1cbe 4450 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4b7f6baa 4451 {
331f1cbe
BS		 4452 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4453 OUTS (outf, " = ");
4454 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4455 OUTS (outf, " << ");
4b7f6baa 4456 OUTS (outf, uimm4 (immag));
331f1cbe 4457 OUTS (outf, " (S)");
4b7f6baa 4458 }
331f1cbe 4459 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4b7f6baa 4460 {
331f1cbe
BS		 4461 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4462 OUTS (outf, " = ");
4463 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4464 OUTS (outf, " >>> ");
4b7f6baa 4465 OUTS (outf, uimm4 (newimmag));
331f1cbe 4466 OUTS (outf, " (S)");
4b7f6baa 4467 }
331f1cbe 4468 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4b7f6baa 4469 {
331f1cbe
BS		 4470 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4471 OUTS (outf, " = ");
4472 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4473 OUTS (outf, " << ");
4b7f6baa 4474 OUTS (outf, uimm4 (immag));
4b7f6baa 4475 }
331f1cbe 4476 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4b7f6baa 4477 {
331f1cbe
BS		 4478 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4479 OUTS (outf, " = ");
4480 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4481 OUTS (outf, " >> ");
4b7f6baa 4482 OUTS (outf, uimm4 (newimmag));
4b7f6baa 4483 }
4b7f6baa
CM		 4484 else if (sop == 2 && sopcde == 3 && HLs == 1)
4485 {
086134ec 4486 OUTS (outf, "A1 = ROT A1 BY ");
4b7f6baa 4487 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4488 }
4489 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4490 {
086134ec 4491 OUTS (outf, "A0 = A0 << ");
4b7f6baa 4492 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4493 }
4494 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4495 {
086134ec 4496 OUTS (outf, "A0 = A0 >>> ");
4b7f6baa 4497 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4498 }
4499 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4500 {
086134ec 4501 OUTS (outf, "A1 = A1 << ");
4b7f6baa 4502 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4503 }
4504 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4505 {
086134ec 4506 OUTS (outf, "A1 = A1 >>> ");
4b7f6baa 4507 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4508 }
4509 else if (sop == 1 && sopcde == 3 && HLs == 0)
4510 {
086134ec 4511 OUTS (outf, "A0 = A0 >> ");
4b7f6baa 4512 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4513 }
4514 else if (sop == 1 && sopcde == 3 && HLs == 1)
4515 {
086134ec 4516 OUTS (outf, "A1 = A1 >> ");
4b7f6baa 4517 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4518 }
4519 else if (sop == 2 && sopcde == 3 && HLs == 0)
4520 {
086134ec 4521 OUTS (outf, "A0 = ROT A0 BY ");
4b7f6baa 4522 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4523 }
4524 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4525 {
4b7f6baa 4526 OUTS (outf, dregs (dst0));
086134ec 4527 OUTS (outf, " = ");
4b7f6baa 4528 OUTS (outf, dregs (src1));
086134ec 4529 OUTS (outf, " << ");
4b7f6baa
CM		 4530 OUTS (outf, uimm5 (immag));
4531 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4532 }
4533 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4534 {
4b7f6baa 4535 OUTS (outf, dregs (dst0));
086134ec 4536 OUTS (outf, " = ");
4b7f6baa 4537 OUTS (outf, dregs (src1));
086134ec 4538 OUTS (outf, " >>> ");
4b7f6baa 4539 OUTS (outf, imm5 (-immag));
0b7691fd 4540 OUTS (outf, " (V, S)");
4b7f6baa
CM		 4541 }
4542 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4543 {
4b7f6baa 4544 OUTS (outf, dregs (dst0));
086134ec 4545 OUTS (outf, " = ");
4b7f6baa
CM		 4546 OUTS (outf, dregs (src1));
4547 OUTS (outf, " >> ");
4548 OUTS (outf, uimm5 (newimmag));
4549 OUTS (outf, " (V)");
4b7f6baa
CM		 4550 }
4551 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4552 {
4b7f6baa 4553 OUTS (outf, dregs (dst0));
086134ec 4554 OUTS (outf, " = ");
4b7f6baa 4555 OUTS (outf, dregs (src1));
086134ec 4556 OUTS (outf, " << ");
4b7f6baa
CM		 4557 OUTS (outf, imm5 (immag));
4558 OUTS (outf, " (V)");
4b7f6baa
CM		 4559 }
4560 else if (sop == 0 && sopcde == 1)
4561 {
4b7f6baa 4562 OUTS (outf, dregs (dst0));
086134ec 4563 OUTS (outf, " = ");
4b7f6baa 4564 OUTS (outf, dregs (src1));
086134ec 4565 OUTS (outf, " >>> ");
4b7f6baa
CM		 4566 OUTS (outf, uimm5 (newimmag));
4567 OUTS (outf, " (V)");
4b7f6baa
CM		 4568 }
4569 else if (sop == 1 && sopcde == 2)
4570 {
4b7f6baa 4571 OUTS (outf, dregs (dst0));
086134ec 4572 OUTS (outf, " = ");
4b7f6baa 4573 OUTS (outf, dregs (src1));
086134ec 4574 OUTS (outf, " << ");
4b7f6baa 4575 OUTS (outf, uimm5 (immag));
086134ec 4576 OUTS (outf, " (S)");
4b7f6baa
CM		 4577 }
4578 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4579 {
4b7f6baa 4580 OUTS (outf, dregs (dst0));
086134ec 4581 OUTS (outf, " = ");
4b7f6baa 4582 OUTS (outf, dregs (src1));
086134ec 4583 OUTS (outf, " >> ");
4b7f6baa 4584 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4585 }
4586 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4587 {
4b7f6baa 4588 OUTS (outf, dregs (dst0));
086134ec 4589 OUTS (outf, " = ");
4b7f6baa 4590 OUTS (outf, dregs (src1));
086134ec 4591 OUTS (outf, " << ");
4b7f6baa 4592 OUTS (outf, uimm5 (immag));
4b7f6baa
CM		 4593 }
4594 else if (sop == 3 && sopcde == 2)
4595 {
4b7f6baa 4596 OUTS (outf, dregs (dst0));
086134ec 4597 OUTS (outf, " = ROT ");
4b7f6baa
CM		 4598 OUTS (outf, dregs (src1));
4599 OUTS (outf, " BY ");
4600 OUTS (outf, imm6 (immag));
4b7f6baa
CM		 4601 }
4602 else if (sop == 0 && sopcde == 2)
4603 {
4b7f6baa 4604 OUTS (outf, dregs (dst0));
086134ec 4605 OUTS (outf, " = ");
4b7f6baa 4606 OUTS (outf, dregs (src1));
086134ec 4607 OUTS (outf, " >>> ");
4b7f6baa 4608 OUTS (outf, uimm5 (newimmag));
4b7f6baa
CM		 4609 }
4610 else
b7d48530
NC		 4611 return 0;
4612
4613 return 4;
4b7f6baa
CM		 4614}
4615
4616static int
4617decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4618{
b7d48530
NC		 4619 /* pseudoDEBUG
4620 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4621 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4622 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa
CM		 4623 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4624 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4625 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4626
219b747a
MF		 4627 if (parallel)
4628 return 0;
4629
4b7f6baa 4630 if (reg == 0 && fn == 3)
b7d48530
NC		 4631 OUTS (outf, "DBG A0");
4632
4b7f6baa 4633 else if (reg == 1 && fn == 3)
b7d48530
NC		 4634 OUTS (outf, "DBG A1");
4635
4b7f6baa 4636 else if (reg == 3 && fn == 3)
b7d48530
NC		 4637 OUTS (outf, "ABORT");
4638
4b7f6baa 4639 else if (reg == 4 && fn == 3)
b7d48530
NC		 4640 OUTS (outf, "HLT");
4641
4b7f6baa 4642 else if (reg == 5 && fn == 3)
b7d48530
NC		 4643 OUTS (outf, "DBGHALT");
4644
4b7f6baa
CM		 4645 else if (reg == 6 && fn == 3)
4646 {
086134ec 4647 OUTS (outf, "DBGCMPLX (");
4b7f6baa
CM		 4648 OUTS (outf, dregs (grp));
4649 OUTS (outf, ")");
4b7f6baa
CM		 4650 }
4651 else if (reg == 7 && fn == 3)
b7d48530
NC		 4652 OUTS (outf, "DBG");
4653
4b7f6baa
CM		 4654 else if (grp == 0 && fn == 2)
4655 {
73a63ccf 4656 OUTS (outf, "OUTC ");
4b7f6baa 4657 OUTS (outf, dregs (reg));
4b7f6baa
CM		 4658 }
4659 else if (fn == 0)
4660 {
a01eda85 4661 OUTS (outf, "DBG ");
4b7f6baa 4662 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4663 }
4664 else if (fn == 1)
4665 {
4b7f6baa
CM		 4666 OUTS (outf, "PRNT");
4667 OUTS (outf, allregs (reg, grp));
4b7f6baa
CM		 4668 }
4669 else
b7d48530
NC		 4670 return 0;
4671
4672 return 2;
4b7f6baa
CM		 4673}
4674
73a63ccf
MF		 4675static int
4676decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4677{
4678 /* psedoOChar
4679 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4680 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4681 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4682 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4683
219b747a
MF		 4684 if (parallel)
4685 return 0;
4686
73a63ccf
MF		 4687 OUTS (outf, "OUTC ");
4688 OUTS (outf, uimm8 (ch));
4689
4690 return 2;
4691}
4692
4b7f6baa
CM		 4693static int
4694decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4695{
b7d48530
NC		 4696 /* pseudodbg_assert
4697 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 4698 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
b7d48530
NC		 4699 |.expected......................................................|
4700 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4b7f6baa 4701 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
b7d48530 4702 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
66a6900a 4703 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
b7d48530 4704 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4b7f6baa 4705
219b747a
MF		 4706 if (parallel)
4707 return 0;
4708
4b7f6baa
CM		 4709 if (dbgop == 0)
4710 {
086134ec 4711 OUTS (outf, "DBGA (");
66a6900a 4712 OUTS (outf, regs_lo (regtest, grp));
086134ec 4713 OUTS (outf, ", ");
4b7f6baa
CM		 4714 OUTS (outf, uimm16 (expected));
4715 OUTS (outf, ")");
4b7f6baa
CM		 4716 }
4717 else if (dbgop == 1)
4718 {
086134ec 4719 OUTS (outf, "DBGA (");
66a6900a 4720 OUTS (outf, regs_hi (regtest, grp));
086134ec 4721 OUTS (outf, ", ");
4b7f6baa
CM		 4722 OUTS (outf, uimm16 (expected));
4723 OUTS (outf, ")");
4b7f6baa
CM		 4724 }
4725 else if (dbgop == 2)
4726 {
086134ec 4727 OUTS (outf, "DBGAL (");
66a6900a 4728 OUTS (outf, allregs (regtest, grp));
086134ec 4729 OUTS (outf, ", ");
4b7f6baa
CM		 4730 OUTS (outf, uimm16 (expected));
4731 OUTS (outf, ")");
4b7f6baa
CM		 4732 }
4733 else if (dbgop == 3)
4734 {
086134ec 4735 OUTS (outf, "DBGAH (");
66a6900a 4736 OUTS (outf, allregs (regtest, grp));
086134ec 4737 OUTS (outf, ", ");
4b7f6baa
CM		 4738 OUTS (outf, uimm16 (expected));
4739 OUTS (outf, ")");
4b7f6baa
CM		 4740 }
4741 else
b7d48530
NC		 4742 return 0;
4743 return 4;
4b7f6baa
CM		 4744}
4745
ad15c38e 4746static int
4b7f6baa
CM		 4747_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4748{
4b7f6baa
CM		 4749 bfd_byte buf[4];
4750 TIword iw0;
4751 TIword iw1;
4752 int status;
b7d48530
NC		 4753 int rv = 0;
4754
4b7f6baa 4755 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
c7e2358a
AM		 4756 /* FIXME */
4757 (void) status;
4b7f6baa 4758 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
c7e2358a
AM		 4759 /* FIXME */
4760 (void) status;
4b7f6baa
CM		 4761
4762 iw0 = bfd_getl16 (buf);
4763 iw1 = bfd_getl16 (buf + 2);
4764
4765 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4766 {
219b747a
MF		 4767 if (parallel)
4768 {
4769 OUTS (outf, "ILLEGAL");
4770 return 0;
4771 }
086134ec 4772 OUTS (outf, "MNOP");
4b7f6baa
CM		 4773 return 4;
4774 }
4775 else if ((iw0 & 0xff00) == 0x0000)
b7d48530 4776 rv = decode_ProgCtrl_0 (iw0, outf);
4b7f6baa 4777 else if ((iw0 & 0xffc0) == 0x0240)
b7d48530 4778 rv = decode_CaCTRL_0 (iw0, outf);
4b7f6baa 4779 else if ((iw0 & 0xff80) == 0x0100)
b7d48530 4780 rv = decode_PushPopReg_0 (iw0, outf);
4b7f6baa 4781 else if ((iw0 & 0xfe00) == 0x0400)
b7d48530 4782 rv = decode_PushPopMultiple_0 (iw0, outf);
4b7f6baa 4783 else if ((iw0 & 0xfe00) == 0x0600)
b7d48530 4784 rv = decode_ccMV_0 (iw0, outf);
4b7f6baa 4785 else if ((iw0 & 0xf800) == 0x0800)
b7d48530 4786 rv = decode_CCflag_0 (iw0, outf);
4b7f6baa 4787 else if ((iw0 & 0xffe0) == 0x0200)
b7d48530 4788 rv = decode_CC2dreg_0 (iw0, outf);
4b7f6baa 4789 else if ((iw0 & 0xff00) == 0x0300)
b7d48530 4790 rv = decode_CC2stat_0 (iw0, outf);
4b7f6baa 4791 else if ((iw0 & 0xf000) == 0x1000)
b7d48530 4792 rv = decode_BRCC_0 (iw0, pc, outf);
4b7f6baa 4793 else if ((iw0 & 0xf000) == 0x2000)
b7d48530 4794 rv = decode_UJUMP_0 (iw0, pc, outf);
4b7f6baa 4795 else if ((iw0 & 0xf000) == 0x3000)
b7d48530 4796 rv = decode_REGMV_0 (iw0, outf);
4b7f6baa 4797 else if ((iw0 & 0xfc00) == 0x4000)
b7d48530 4798 rv = decode_ALU2op_0 (iw0, outf);
4b7f6baa 4799 else if ((iw0 & 0xfe00) == 0x4400)
b7d48530 4800 rv = decode_PTR2op_0 (iw0, outf);
4b7f6baa 4801 else if ((iw0 & 0xf800) == 0x4800)
b7d48530 4802 rv = decode_LOGI2op_0 (iw0, outf);
4b7f6baa 4803 else if ((iw0 & 0xf000) == 0x5000)
b7d48530 4804 rv = decode_COMP3op_0 (iw0, outf);
4b7f6baa 4805 else if ((iw0 & 0xf800) == 0x6000)
b7d48530 4806 rv = decode_COMPI2opD_0 (iw0, outf);
4b7f6baa 4807 else if ((iw0 & 0xf800) == 0x6800)
b7d48530 4808 rv = decode_COMPI2opP_0 (iw0, outf);
4b7f6baa 4809 else if ((iw0 & 0xf000) == 0x8000)
b7d48530 4810 rv = decode_LDSTpmod_0 (iw0, outf);
4b7f6baa 4811 else if ((iw0 & 0xff60) == 0x9e60)
b7d48530 4812 rv = decode_dagMODim_0 (iw0, outf);
4b7f6baa 4813 else if ((iw0 & 0xfff0) == 0x9f60)
b7d48530 4814 rv = decode_dagMODik_0 (iw0, outf);
4b7f6baa 4815 else if ((iw0 & 0xfc00) == 0x9c00)
b7d48530 4816 rv = decode_dspLDST_0 (iw0, outf);
4b7f6baa 4817 else if ((iw0 & 0xf000) == 0x9000)
b7d48530 4818 rv = decode_LDST_0 (iw0, outf);
4b7f6baa 4819 else if ((iw0 & 0xfc00) == 0xb800)
b7d48530 4820 rv = decode_LDSTiiFP_0 (iw0, outf);
4b7f6baa 4821 else if ((iw0 & 0xe000) == 0xA000)
b7d48530 4822 rv = decode_LDSTii_0 (iw0, outf);
4b7f6baa 4823 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
b7d48530 4824 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4b7f6baa 4825 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
b7d48530 4826 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4b7f6baa 4827 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4828 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4b7f6baa 4829 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4830 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4b7f6baa 4831 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
b7d48530 4832 rv = decode_linkage_0 (iw0, iw1, outf);
4b7f6baa 4833 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4834 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4b7f6baa 4835 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
b7d48530 4836 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4b7f6baa 4837 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
b7d48530 4838 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4b7f6baa 4839 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
b7d48530 4840 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4b7f6baa 4841 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
b7d48530 4842 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4b7f6baa 4843 else if ((iw0 & 0xff00) == 0xf800)
b7d48530 4844 rv = decode_pseudoDEBUG_0 (iw0, outf);
4b7f6baa 4845 else if ((iw0 & 0xFF00) == 0xF900)
73a63ccf 4846 rv = decode_pseudoOChar_0 (iw0, outf);
66a6900a 4847 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
b7d48530 4848 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4b7f6baa 4849
219b747a
MF		 4850 if (rv == 0)
4851 OUTS (outf, "ILLEGAL");
4852
b7d48530 4853 return rv;
4b7f6baa
CM		 4854}
4855
4856
4857int
4858print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4859{
471e4e36
JZ		 4860 bfd_byte buf[2];
4861 unsigned short iw0;
4862 int status;
4b7f6baa 4863 int count = 0;
471e4e36
JZ		 4864
4865 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
c7e2358a
AM		 4866 /* FIXME */
4867 (void) status;
471e4e36 4868 iw0 = bfd_getl16 (buf);
4b7f6baa
CM		 4869
4870 count += _print_insn_bfin (pc, outf);
471e4e36 4871
4b7f6baa 4872 /* Proper display of multiple issue instructions. */
471e4e36 4873
219b747a 4874 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
b7d48530 4875 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4b7f6baa 4876 {
219b747a
MF		 4877 int legal = 1;
4878 int len;
4879
086134ec 4880 parallel = 1;
4b7f6baa 4881 outf->fprintf_func (outf->stream, " || ");
219b747a 4882 len = _print_insn_bfin (pc + 4, outf);
4b7f6baa 4883 outf->fprintf_func (outf->stream, " || ");
219b747a
MF		 4884 if (len != 2)
4885 legal = 0;
4886 len = _print_insn_bfin (pc + 6, outf);
4887 if (len != 2)
4888 legal = 0;
4889
4890 if (legal)
4891 count = 8;
4892 else
4893 {
4894 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4895 comment = 1;
4896 count = 0;
4897 }
086134ec 4898 parallel = 0;
4b7f6baa 4899 }
219b747a 4900
086134ec
BS		 4901 if (!comment)
4902 outf->fprintf_func (outf->stream, ";");
4903
219b747a
MF		 4904 if (count == 0)
4905 return 2;
4906
086134ec
BS		 4907 comment = 0;
4908
4b7f6baa
CM		 4909 return count;
4910}
GDB Binutils - Deliverables
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