mips64 rtype_to_howto error status
[deliverable/binutils-gdb.git] / opcodes / disassemble.c
CommitLineData
252b5132 1/* Select disassembly routine for specified architecture.
219d1afa 2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
252b5132 3
9b201bb5
NC
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7499d566 7 it under the terms of the GNU General Public License as published by
9b201bb5 8 the Free Software Foundation; either version 3 of the License, or
7499d566 9 (at your option) any later version.
252b5132 10
7499d566
NC
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
252b5132 15
7499d566
NC
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
9b201bb5
NC
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
0d8dfecf 21#include "sysdep.h"
88c1242d 22#include "disassemble.h"
65b48a81 23#include "safe-ctype.h"
003ca0fd 24#include <assert.h>
252b5132
RH
25
26#ifdef ARCH_all
a06ea964 27#define ARCH_aarch64
252b5132
RH
28#define ARCH_alpha
29#define ARCH_arc
30#define ARCH_arm
adde6300 31#define ARCH_avr
4b7f6baa 32#define ARCH_bfin
3d3d428f 33#define ARCH_cr16
6c95a37f 34#define ARCH_cris
1fe1f39c 35#define ARCH_crx
252b5132
RH
36#define ARCH_d10v
37#define ARCH_d30v
d172d4ba 38#define ARCH_dlx
56b13185 39#define ARCH_epiphany
e729279b
NC
40#define ARCH_fr30
41#define ARCH_frv
3f8107ab 42#define ARCH_ft32
252b5132
RH
43#define ARCH_h8300
44#define ARCH_h8500
45#define ARCH_hppa
5b93d8bb 46#define ARCH_i370
252b5132 47#define ARCH_i386
9d751335 48#define ARCH_i860
252b5132 49#define ARCH_i960
800eeca4 50#define ARCH_ia64
e729279b
NC
51#define ARCH_ip2k
52#define ARCH_iq2000
84e94c90 53#define ARCH_lm32
e729279b 54#define ARCH_m32c
252b5132 55#define ARCH_m32r
60bcf0fa
NC
56#define ARCH_m68hc11
57#define ARCH_m68hc12
e729279b 58#define ARCH_m68k
252b5132
RH
59#define ARCH_m88k
60#define ARCH_mcore
bd2f2e55 61#define ARCH_mep
a3c62988 62#define ARCH_metag
7ba29e2a 63#define ARCH_microblaze
252b5132 64#define ARCH_mips
3c3bdf30 65#define ARCH_mmix
252b5132
RH
66#define ARCH_mn10200
67#define ARCH_mn10300
59b1530d 68#define ARCH_moxie
d031aafb 69#define ARCH_mt
2469cfa2 70#define ARCH_msp430
35c08157 71#define ARCH_nds32
36591ba1 72#define ARCH_nios2
252b5132 73#define ARCH_ns32k
73589c9d 74#define ARCH_or1k
e135f41b 75#define ARCH_pdp11
1e608f98 76#define ARCH_pj
252b5132 77#define ARCH_powerpc
11146849 78#define ARCH_pru
0bccfb29 79#define ARCH_riscv
252b5132 80#define ARCH_rs6000
99c513f6 81#define ARCH_rl78
c7927a3c 82#define ARCH_rx
a85d7ed0 83#define ARCH_s390
1c0d3aa6 84#define ARCH_score
252b5132
RH
85#define ARCH_sh
86#define ARCH_sparc
e9f53129 87#define ARCH_spu
252b5132 88#define ARCH_tic30
026df7c5 89#define ARCH_tic4x
5c84d377 90#define ARCH_tic54x
40b36596 91#define ARCH_tic6x
252b5132 92#define ARCH_tic80
aa137e4d
NC
93#define ARCH_tilegx
94#define ARCH_tilepro
252b5132
RH
95#define ARCH_v850
96#define ARCH_vax
1945cfa5 97#define ARCH_visium
252b5132 98#define ARCH_w65
62ecb94c 99#define ARCH_wasm32
93fbbb04 100#define ARCH_xstormy16
d70c5fc7 101#define ARCH_xc16x
f6c1a2d5 102#define ARCH_xgate
e0001a05 103#define ARCH_xtensa
3c9b82ba 104#define ARCH_z80
252b5132 105#define ARCH_z8k
d28847ce 106#define INCLUDE_SHMEDIA
252b5132
RH
107#endif
108
49f58d10
JB
109#ifdef ARCH_m32c
110#include "m32c-desc.h"
111#endif
252b5132
RH
112
113disassembler_ftype
b28b8b5e
L
114disassembler (enum bfd_architecture a,
115 bfd_boolean big ATTRIBUTE_UNUSED,
116 unsigned long mach ATTRIBUTE_UNUSED,
e347efc3 117 bfd *abfd ATTRIBUTE_UNUSED)
252b5132 118{
252b5132
RH
119 disassembler_ftype disassemble;
120
121 switch (a)
122 {
123 /* If you add a case to this table, also add it to the
124 ARCH_all definition right above this function. */
a06ea964
NC
125#ifdef ARCH_aarch64
126 case bfd_arch_aarch64:
127 disassemble = print_insn_aarch64;
128 break;
129#endif
252b5132
RH
130#ifdef ARCH_alpha
131 case bfd_arch_alpha:
132 disassemble = print_insn_alpha;
133 break;
134#endif
135#ifdef ARCH_arc
136 case bfd_arch_arc:
6ca4eb77
AM
137 disassemble = arc_get_disassembler (abfd);
138 break;
252b5132
RH
139#endif
140#ifdef ARCH_arm
141 case bfd_arch_arm:
003ca0fd 142 if (big)
252b5132
RH
143 disassemble = print_insn_big_arm;
144 else
145 disassemble = print_insn_little_arm;
146 break;
147#endif
adde6300
AM
148#ifdef ARCH_avr
149 case bfd_arch_avr:
150 disassemble = print_insn_avr;
151 break;
152#endif
4b7f6baa
CM
153#ifdef ARCH_bfin
154 case bfd_arch_bfin:
155 disassemble = print_insn_bfin;
156 break;
157#endif
3d3d428f
NC
158#ifdef ARCH_cr16
159 case bfd_arch_cr16:
160 disassemble = print_insn_cr16;
161 break;
162#endif
6c95a37f
HPN
163#ifdef ARCH_cris
164 case bfd_arch_cris:
78966507 165 disassemble = cris_get_disassembler (abfd);
6c95a37f 166 break;
1fe1f39c
NC
167#endif
168#ifdef ARCH_crx
169 case bfd_arch_crx:
170 disassemble = print_insn_crx;
171 break;
6c95a37f 172#endif
252b5132
RH
173#ifdef ARCH_d10v
174 case bfd_arch_d10v:
175 disassemble = print_insn_d10v;
176 break;
177#endif
178#ifdef ARCH_d30v
179 case bfd_arch_d30v:
180 disassemble = print_insn_d30v;
181 break;
182#endif
d172d4ba
NC
183#ifdef ARCH_dlx
184 case bfd_arch_dlx:
185 /* As far as I know we only handle big-endian DLX objects. */
186 disassemble = print_insn_dlx;
187 break;
188#endif
252b5132
RH
189#ifdef ARCH_h8300
190 case bfd_arch_h8300:
003ca0fd 191 if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn)
252b5132 192 disassemble = print_insn_h8300h;
003ca0fd
YQ
193 else if (mach == bfd_mach_h8300s
194 || mach == bfd_mach_h8300sn
195 || mach == bfd_mach_h8300sx
196 || mach == bfd_mach_h8300sxn)
252b5132 197 disassemble = print_insn_h8300s;
b7ed8fad 198 else
252b5132
RH
199 disassemble = print_insn_h8300;
200 break;
201#endif
202#ifdef ARCH_h8500
203 case bfd_arch_h8500:
204 disassemble = print_insn_h8500;
205 break;
206#endif
207#ifdef ARCH_hppa
208 case bfd_arch_hppa:
209 disassemble = print_insn_hppa;
210 break;
211#endif
5b93d8bb
AM
212#ifdef ARCH_i370
213 case bfd_arch_i370:
214 disassemble = print_insn_i370;
215 break;
216#endif
252b5132
RH
217#ifdef ARCH_i386
218 case bfd_arch_i386:
7b6d09fb 219 case bfd_arch_iamcu:
8a9036a4 220 case bfd_arch_l1om:
7a9068fe 221 case bfd_arch_k1om:
e396998b 222 disassemble = print_insn_i386;
252b5132
RH
223 break;
224#endif
9d751335
JE
225#ifdef ARCH_i860
226 case bfd_arch_i860:
227 disassemble = print_insn_i860;
228 break;
229#endif
252b5132
RH
230#ifdef ARCH_i960
231 case bfd_arch_i960:
232 disassemble = print_insn_i960;
233 break;
234#endif
800eeca4
JW
235#ifdef ARCH_ia64
236 case bfd_arch_ia64:
237 disassemble = print_insn_ia64;
238 break;
239#endif
a40cbfa3
NC
240#ifdef ARCH_ip2k
241 case bfd_arch_ip2k:
242 disassemble = print_insn_ip2k;
243 break;
244#endif
cfb8c092
NC
245#ifdef ARCH_epiphany
246 case bfd_arch_epiphany:
247 disassemble = print_insn_epiphany;
248 break;
249#endif
252b5132
RH
250#ifdef ARCH_fr30
251 case bfd_arch_fr30:
252 disassemble = print_insn_fr30;
253 break;
254#endif
84e94c90
NC
255#ifdef ARCH_lm32
256 case bfd_arch_lm32:
257 disassemble = print_insn_lm32;
258 break;
259#endif
252b5132
RH
260#ifdef ARCH_m32r
261 case bfd_arch_m32r:
262 disassemble = print_insn_m32r;
263 break;
264#endif
6927f982
NC
265#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) \
266 || defined(ARCH_9s12x) || defined(ARCH_m9s12xg)
60bcf0fa
NC
267 case bfd_arch_m68hc11:
268 disassemble = print_insn_m68hc11;
269 break;
270 case bfd_arch_m68hc12:
271 disassemble = print_insn_m68hc12;
272 break;
6927f982
NC
273 case bfd_arch_m9s12x:
274 disassemble = print_insn_m9s12x;
275 break;
276 case bfd_arch_m9s12xg:
277 disassemble = print_insn_m9s12xg;
278 break;
60bcf0fa 279#endif
252b5132
RH
280#ifdef ARCH_m68k
281 case bfd_arch_m68k:
282 disassemble = print_insn_m68k;
283 break;
284#endif
285#ifdef ARCH_m88k
286 case bfd_arch_m88k:
287 disassemble = print_insn_m88k;
288 break;
289#endif
d031aafb
NS
290#ifdef ARCH_mt
291 case bfd_arch_mt:
292 disassemble = print_insn_mt;
ac188222
DB
293 break;
294#endif
7ba29e2a
NC
295#ifdef ARCH_microblaze
296 case bfd_arch_microblaze:
297 disassemble = print_insn_microblaze;
298 break;
299#endif
2469cfa2
NC
300#ifdef ARCH_msp430
301 case bfd_arch_msp430:
302 disassemble = print_insn_msp430;
303 break;
304#endif
35c08157
KLC
305#ifdef ARCH_nds32
306 case bfd_arch_nds32:
307 disassemble = print_insn_nds32;
308 break;
309#endif
252b5132
RH
310#ifdef ARCH_ns32k
311 case bfd_arch_ns32k:
312 disassemble = print_insn_ns32k;
313 break;
314#endif
315#ifdef ARCH_mcore
316 case bfd_arch_mcore:
317 disassemble = print_insn_mcore;
318 break;
319#endif
bd2f2e55
DB
320#ifdef ARCH_mep
321 case bfd_arch_mep:
322 disassemble = print_insn_mep;
323 break;
324#endif
a3c62988
NC
325#ifdef ARCH_metag
326 case bfd_arch_metag:
327 disassemble = print_insn_metag;
328 break;
329#endif
252b5132
RH
330#ifdef ARCH_mips
331 case bfd_arch_mips:
003ca0fd 332 if (big)
252b5132
RH
333 disassemble = print_insn_big_mips;
334 else
335 disassemble = print_insn_little_mips;
336 break;
337#endif
3c3bdf30
NC
338#ifdef ARCH_mmix
339 case bfd_arch_mmix:
340 disassemble = print_insn_mmix;
341 break;
342#endif
252b5132
RH
343#ifdef ARCH_mn10200
344 case bfd_arch_mn10200:
345 disassemble = print_insn_mn10200;
346 break;
347#endif
348#ifdef ARCH_mn10300
349 case bfd_arch_mn10300:
350 disassemble = print_insn_mn10300;
351 break;
352#endif
36591ba1
SL
353#ifdef ARCH_nios2
354 case bfd_arch_nios2:
003ca0fd 355 if (big)
36591ba1
SL
356 disassemble = print_insn_big_nios2;
357 else
358 disassemble = print_insn_little_nios2;
359 break;
360#endif
73589c9d
CS
361#ifdef ARCH_or1k
362 case bfd_arch_or1k:
363 disassemble = print_insn_or1k;
3b16e843
NC
364 break;
365#endif
e135f41b
NC
366#ifdef ARCH_pdp11
367 case bfd_arch_pdp11:
368 disassemble = print_insn_pdp11;
369 break;
370#endif
1e608f98
ILT
371#ifdef ARCH_pj
372 case bfd_arch_pj:
373 disassemble = print_insn_pj;
374 break;
375#endif
252b5132
RH
376#ifdef ARCH_powerpc
377 case bfd_arch_powerpc:
003ca0fd 378 if (big)
252b5132
RH
379 disassemble = print_insn_big_powerpc;
380 else
381 disassemble = print_insn_little_powerpc;
382 break;
383#endif
11146849
DD
384#ifdef ARCH_pru
385 case bfd_arch_pru:
386 disassemble = print_insn_pru;
387 break;
388#endif
e23eba97
NC
389#ifdef ARCH_riscv
390 case bfd_arch_riscv:
391 disassemble = print_insn_riscv;
ae4c0df4 392 break;
e23eba97 393#endif
252b5132
RH
394#ifdef ARCH_rs6000
395 case bfd_arch_rs6000:
003ca0fd 396 if (mach == bfd_mach_ppc_620)
7f6d05e8
CP
397 disassemble = print_insn_big_powerpc;
398 else
399 disassemble = print_insn_rs6000;
252b5132
RH
400 break;
401#endif
99c513f6
DD
402#ifdef ARCH_rl78
403 case bfd_arch_rl78:
0952813b 404 disassemble = rl78_get_disassembler (abfd);
99c513f6
DD
405 break;
406#endif
c7927a3c
NC
407#ifdef ARCH_rx
408 case bfd_arch_rx:
409 disassemble = print_insn_rx;
410 break;
411#endif
a85d7ed0
NC
412#ifdef ARCH_s390
413 case bfd_arch_s390:
414 disassemble = print_insn_s390;
415 break;
416#endif
1c0d3aa6
NC
417#ifdef ARCH_score
418 case bfd_arch_score:
003ca0fd 419 if (big)
6ca4eb77 420 disassemble = print_insn_big_score;
1c0d3aa6 421 else
6ca4eb77 422 disassemble = print_insn_little_score;
1c0d3aa6
NC
423 break;
424#endif
252b5132
RH
425#ifdef ARCH_sh
426 case bfd_arch_sh:
1c509ca8 427 disassemble = print_insn_sh;
252b5132
RH
428 break;
429#endif
430#ifdef ARCH_sparc
431 case bfd_arch_sparc:
432 disassemble = print_insn_sparc;
433 break;
434#endif
e9f53129
AM
435#ifdef ARCH_spu
436 case bfd_arch_spu:
437 disassemble = print_insn_spu;
438 break;
439#endif
252b5132
RH
440#ifdef ARCH_tic30
441 case bfd_arch_tic30:
442 disassemble = print_insn_tic30;
443 break;
444#endif
026df7c5
NC
445#ifdef ARCH_tic4x
446 case bfd_arch_tic4x:
447 disassemble = print_insn_tic4x;
448 break;
449#endif
5c84d377
TW
450#ifdef ARCH_tic54x
451 case bfd_arch_tic54x:
452 disassemble = print_insn_tic54x;
453 break;
454#endif
40b36596
JM
455#ifdef ARCH_tic6x
456 case bfd_arch_tic6x:
457 disassemble = print_insn_tic6x;
458 break;
459#endif
252b5132
RH
460#ifdef ARCH_tic80
461 case bfd_arch_tic80:
462 disassemble = print_insn_tic80;
463 break;
464#endif
3f8107ab
AM
465#ifdef ARCH_ft32
466 case bfd_arch_ft32:
467 disassemble = print_insn_ft32;
468 break;
469#endif
252b5132
RH
470#ifdef ARCH_v850
471 case bfd_arch_v850:
de863c74 472 case bfd_arch_v850_rh850:
252b5132
RH
473 disassemble = print_insn_v850;
474 break;
475#endif
476#ifdef ARCH_w65
477 case bfd_arch_w65:
478 disassemble = print_insn_w65;
479 break;
480#endif
62ecb94c
PC
481#ifdef ARCH_wasm32
482 case bfd_arch_wasm32:
483 disassemble = print_insn_wasm32;
484 break;
485#endif
f6c1a2d5
NC
486#ifdef ARCH_xgate
487 case bfd_arch_xgate:
488 disassemble = print_insn_xgate;
489 break;
490#endif
93fbbb04
GK
491#ifdef ARCH_xstormy16
492 case bfd_arch_xstormy16:
493 disassemble = print_insn_xstormy16;
494 break;
495#endif
d70c5fc7
NC
496#ifdef ARCH_xc16x
497 case bfd_arch_xc16x:
498 disassemble = print_insn_xc16x;
499 break;
500#endif
e0001a05
NC
501#ifdef ARCH_xtensa
502 case bfd_arch_xtensa:
503 disassemble = print_insn_xtensa;
504 break;
505#endif
3c9b82ba
NC
506#ifdef ARCH_z80
507 case bfd_arch_z80:
508 disassemble = print_insn_z80;
509 break;
510#endif
252b5132
RH
511#ifdef ARCH_z8k
512 case bfd_arch_z8k:
003ca0fd 513 if (mach == bfd_mach_z8001)
252b5132 514 disassemble = print_insn_z8001;
b7ed8fad 515 else
252b5132
RH
516 disassemble = print_insn_z8002;
517 break;
518#endif
519#ifdef ARCH_vax
520 case bfd_arch_vax:
521 disassemble = print_insn_vax;
522 break;
fd3c93d5 523#endif
1945cfa5
EB
524#ifdef ARCH_visium
525 case bfd_arch_visium:
526 disassemble = print_insn_visium;
527 break;
528#endif
fd3c93d5
DB
529#ifdef ARCH_frv
530 case bfd_arch_frv:
531 disassemble = print_insn_frv;
532 break;
47b1a55a 533#endif
59b1530d
AG
534#ifdef ARCH_moxie
535 case bfd_arch_moxie:
536 disassemble = print_insn_moxie;
537 break;
538#endif
47b1a55a
SC
539#ifdef ARCH_iq2000
540 case bfd_arch_iq2000:
541 disassemble = print_insn_iq2000;
542 break;
49f58d10
JB
543#endif
544#ifdef ARCH_m32c
545 case bfd_arch_m32c:
546 disassemble = print_insn_m32c;
547 break;
aa137e4d
NC
548#endif
549#ifdef ARCH_tilegx
550 case bfd_arch_tilegx:
551 disassemble = print_insn_tilegx;
552 break;
553#endif
554#ifdef ARCH_tilepro
555 case bfd_arch_tilepro:
556 disassemble = print_insn_tilepro;
557 break;
252b5132
RH
558#endif
559 default:
560 return 0;
561 }
562 return disassemble;
563}
94470b23
NC
564
565void
e6c7cdec 566disassembler_usage (FILE *stream ATTRIBUTE_UNUSED)
94470b23 567{
a06ea964
NC
568#ifdef ARCH_aarch64
569 print_aarch64_disassembler_options (stream);
570#endif
37fd5ef3
CZ
571#ifdef ARCH_arc
572 print_arc_disassembler_options (stream);
573#endif
58efb6c0
NC
574#ifdef ARCH_arm
575 print_arm_disassembler_options (stream);
576#endif
640c0ccd
CD
577#ifdef ARCH_mips
578 print_mips_disassembler_options (stream);
579#endif
07dd56a9
NC
580#ifdef ARCH_powerpc
581 print_ppc_disassembler_options (stream);
582#endif
e23eba97
NC
583#ifdef ARCH_riscv
584 print_riscv_disassembler_options (stream);
585#endif
f59a29b9
L
586#ifdef ARCH_i386
587 print_i386_disassembler_options (stream);
588#endif
112b7c50
AK
589#ifdef ARCH_s390
590 print_s390_disassembler_options (stream);
591#endif
62ecb94c
PC
592#ifdef ARCH_wasm32
593 print_wasm32_disassembler_options (stream);
594#endif
b7ed8fad 595
94470b23
NC
596 return;
597}
22a398e1
NC
598
599void
600disassemble_init_for_target (struct disassemble_info * info)
601{
602 if (info == NULL)
603 return;
604
605 switch (info->arch)
606 {
a06ea964
NC
607#ifdef ARCH_aarch64
608 case bfd_arch_aarch64:
609 info->symbol_is_valid = aarch64_symbol_is_valid;
610 info->disassembler_needs_relocs = TRUE;
611 break;
612#endif
22a398e1
NC
613#ifdef ARCH_arm
614 case bfd_arch_arm:
615 info->symbol_is_valid = arm_symbol_is_valid;
d99b6465 616 info->disassembler_needs_relocs = TRUE;
22a398e1 617 break;
0bcb06d2
AS
618#endif
619#ifdef ARCH_ia64
620 case bfd_arch_ia64:
621 info->skip_zeroes = 16;
622 break;
623#endif
624#ifdef ARCH_tic4x
625 case bfd_arch_tic4x:
626 info->skip_zeroes = 32;
fb53f5a8 627 break;
49f58d10 628#endif
bd2f2e55
DB
629#ifdef ARCH_mep
630 case bfd_arch_mep:
631 info->skip_zeroes = 256;
632 info->skip_zeroes_at_end = 0;
633 break;
634#endif
a3c62988
NC
635#ifdef ARCH_metag
636 case bfd_arch_metag:
637 info->disassembler_needs_relocs = TRUE;
638 break;
639#endif
49f58d10
JB
640#ifdef ARCH_m32c
641 case bfd_arch_m32c:
6ca4eb77
AM
642 /* This processor in fact is little endian. The value set here
643 reflects the way opcodes are written in the cgen description. */
49f58d10 644 info->endian = BFD_ENDIAN_BIG;
fb53f5a8
DB
645 if (! info->insn_sets)
646 {
647 info->insn_sets = cgen_bitset_create (ISA_MAX);
648 if (info->mach == bfd_mach_m16c)
649 cgen_bitset_set (info->insn_sets, ISA_M16C);
650 else
651 cgen_bitset_set (info->insn_sets, ISA_M32C);
652 }
49f58d10 653 break;
b240011a 654#endif
024d185c
DD
655#ifdef ARCH_pru
656 case bfd_arch_pru:
657 info->disassembler_needs_relocs = TRUE;
658 break;
659#endif
fbc22555
DD
660#ifdef ARCH_powerpc
661 case bfd_arch_powerpc:
662#endif
b240011a
AM
663#ifdef ARCH_rs6000
664 case bfd_arch_rs6000:
665#endif
666#if defined (ARCH_powerpc) || defined (ARCH_rs6000)
667 disassemble_init_powerpc (info);
668 break;
65b48a81 669#endif
62ecb94c
PC
670#ifdef ARCH_wasm32
671 case bfd_arch_wasm32:
672 disassemble_init_wasm32 (info);
673 break;
674#endif
65b48a81
PB
675#ifdef ARCH_s390
676 case bfd_arch_s390:
677 disassemble_init_s390 (info);
678 break;
22a398e1
NC
679#endif
680 default:
681 break;
682 }
683}
65b48a81
PB
684
685/* Remove whitespace and consecutive commas from OPTIONS. */
686
687char *
688remove_whitespace_and_extra_commas (char *options)
689{
690 char *str;
691 size_t i, len;
692
693 if (options == NULL)
694 return NULL;
695
696 /* Strip off all trailing whitespace and commas. */
697 for (len = strlen (options); len > 0; len--)
698 {
699 if (!ISSPACE (options[len - 1]) && options[len - 1] != ',')
700 break;
701 options[len - 1] = '\0';
702 }
703
704 /* Convert all remaining whitespace to commas. */
705 for (i = 0; options[i] != '\0'; i++)
706 if (ISSPACE (options[i]))
707 options[i] = ',';
708
709 /* Remove consecutive commas. */
710 for (str = options; *str != '\0'; str++)
711 if (*str == ',' && (*(str + 1) == ',' || str == options))
712 {
713 char *next = str + 1;
714 while (*next == ',')
715 next++;
716 len = strlen (next);
717 if (str != options)
718 str++;
719 memmove (str, next, len);
720 next[len - (size_t)(next - str)] = '\0';
721 }
722 return (strlen (options) != 0) ? options : NULL;
723}
724
725/* Like STRCMP, but treat ',' the same as '\0' so that we match
726 strings like "foobar" against "foobar,xxyyzz,...". */
727
728int
729disassembler_options_cmp (const char *s1, const char *s2)
730{
731 unsigned char c1, c2;
732
733 do
734 {
735 c1 = (unsigned char) *s1++;
736 if (c1 == ',')
737 c1 = '\0';
738 c2 = (unsigned char) *s2++;
739 if (c2 == ',')
740 c2 = '\0';
741 if (c1 == '\0')
742 return c1 - c2;
743 }
744 while (c1 == c2);
745
746 return c1 - c2;
747}
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