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* cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
[deliverable/binutils-gdb.git] / opcodes / xstormy16-desc.c
CommitLineData
93fbbb04
GK		 1/* CPU data for xstormy16.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
1951c6f7 5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
93fbbb04
GK		 6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <stdio.h>
27#include <stdarg.h>
28#include "ansidecl.h"
29#include "bfd.h"
30#include "symcat.h"
31#include "xstormy16-desc.h"
32#include "xstormy16-opc.h"
33#include "opintl.h"
34#include "libiberty.h"
35
36/* Attributes. */
37
38static const CGEN_ATTR_ENTRY bool_attr[] =
39{
40 { "#f", 0 },
41 { "#t", 1 },
42 { 0, 0 }
43};
44
45static const CGEN_ATTR_ENTRY MACH_attr[] =
46{
47 { "base", MACH_BASE },
48 { "xstormy16", MACH_XSTORMY16 },
49 { "max", MACH_MAX },
50 { 0, 0 }
51};
52
53static const CGEN_ATTR_ENTRY ISA_attr[] =
54{
55 { "xstormy16", ISA_XSTORMY16 },
56 { "max", ISA_MAX },
57 { 0, 0 }
58};
59
60const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
61{
62 { "MACH", & MACH_attr[0], & MACH_attr[0] },
63 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
64 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
65 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
66 { "RESERVED", &bool_attr[0], &bool_attr[0] },
67 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
68 { "SIGNED", &bool_attr[0], &bool_attr[0] },
69 { 0, 0, 0 }
70};
71
72const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
73{
74 { "MACH", & MACH_attr[0], & MACH_attr[0] },
75 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
76 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
77 { "PC", &bool_attr[0], &bool_attr[0] },
78 { "PROFILE", &bool_attr[0], &bool_attr[0] },
79 { 0, 0, 0 }
80};
81
82const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
83{
84 { "MACH", & MACH_attr[0], & MACH_attr[0] },
85 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
86 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
87 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
88 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
89 { "SIGNED", &bool_attr[0], &bool_attr[0] },
90 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
91 { "RELAX", &bool_attr[0], &bool_attr[0] },
92 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
93 { 0, 0, 0 }
94};
95
96const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
97{
98 { "MACH", & MACH_attr[0], & MACH_attr[0] },
99 { "ALIAS", &bool_attr[0], &bool_attr[0] },
100 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
101 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
102 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
103 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
104 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
105 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
106 { "RELAX", &bool_attr[0], &bool_attr[0] },
107 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
108 { "PBB", &bool_attr[0], &bool_attr[0] },
109 { 0, 0, 0 }
110};
111
112/* Instruction set variants. */
113
114static const CGEN_ISA xstormy16_cgen_isa_table[] = {
115 { "xstormy16", 32, 32, 16, 32 },
116 { 0, 0, 0, 0, 0 }
117};
118
119/* Machine variants. */
120
121static const CGEN_MACH xstormy16_cgen_mach_table[] = {
122 { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
123 { 0, 0, 0, 0 }
124};
125
126static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
127{
128 { "r0", 0, {0, {0}}, 0, 0 },
129 { "r1", 1, {0, {0}}, 0, 0 },
130 { "r2", 2, {0, {0}}, 0, 0 },
131 { "r3", 3, {0, {0}}, 0, 0 },
132 { "r4", 4, {0, {0}}, 0, 0 },
133 { "r5", 5, {0, {0}}, 0, 0 },
134 { "r6", 6, {0, {0}}, 0, 0 },
135 { "r7", 7, {0, {0}}, 0, 0 },
136 { "r8", 8, {0, {0}}, 0, 0 },
137 { "r9", 9, {0, {0}}, 0, 0 },
138 { "r10", 10, {0, {0}}, 0, 0 },
139 { "r11", 11, {0, {0}}, 0, 0 },
140 { "r12", 12, {0, {0}}, 0, 0 },
141 { "r13", 13, {0, {0}}, 0, 0 },
142 { "r14", 14, {0, {0}}, 0, 0 },
143 { "r15", 15, {0, {0}}, 0, 0 },
144 { "psw", 14, {0, {0}}, 0, 0 },
145 { "sp", 15, {0, {0}}, 0, 0 }
146};
147
148CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
149{
150 & xstormy16_cgen_opval_gr_names_entries[0],
151 18,
152 0, 0, 0, 0, ""
153};
154
1951c6f7 155static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
93fbbb04
GK		 156{
157 { "r8", 0, {0, {0}}, 0, 0 },
1951c6f7
MG		 158 { "r9", 1, {0, {0}}, 0, 0 },
159 { "r10", 2, {0, {0}}, 0, 0 },
160 { "r11", 3, {0, {0}}, 0, 0 },
161 { "r12", 4, {0, {0}}, 0, 0 },
162 { "r13", 5, {0, {0}}, 0, 0 },
163 { "r14", 6, {0, {0}}, 0, 0 },
164 { "r15", 7, {0, {0}}, 0, 0 },
165 { "psw", 6, {0, {0}}, 0, 0 },
166 { "sp", 7, {0, {0}}, 0, 0 }
93fbbb04
GK		 167};
168
1951c6f7 169CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
93fbbb04 170{
1951c6f7
MG		 171 & xstormy16_cgen_opval_gr_Rb_names_entries[0],
172 10,
93fbbb04
GK		 173 0, 0, 0, 0, ""
174};
175
176static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
177{
178 { "ge", 0, {0, {0}}, 0, 0 },
179 { "nc", 1, {0, {0}}, 0, 0 },
180 { "lt", 2, {0, {0}}, 0, 0 },
181 { "c", 3, {0, {0}}, 0, 0 },
182 { "gt", 4, {0, {0}}, 0, 0 },
183 { "hi", 5, {0, {0}}, 0, 0 },
184 { "le", 6, {0, {0}}, 0, 0 },
185 { "ls", 7, {0, {0}}, 0, 0 },
186 { "pl", 8, {0, {0}}, 0, 0 },
187 { "nv", 9, {0, {0}}, 0, 0 },
188 { "mi", 10, {0, {0}}, 0, 0 },
189 { "v", 11, {0, {0}}, 0, 0 },
190 { "nz.b", 12, {0, {0}}, 0, 0 },
191 { "nz", 13, {0, {0}}, 0, 0 },
192 { "z.b", 14, {0, {0}}, 0, 0 },
193 { "z", 15, {0, {0}}, 0, 0 }
194};
195
196CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
197{
198 & xstormy16_cgen_opval_h_branchcond_entries[0],
199 16,
200 0, 0, 0, 0, ""
201};
202
203static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
204{
205 { ".b", 0, {0, {0}}, 0, 0 },
206 { ".w", 1, {0, {0}}, 0, 0 },
207 { "", 1, {0, {0}}, 0, 0 }
208};
209
210CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
211{
212 & xstormy16_cgen_opval_h_wordsize_entries[0],
213 3,
214 0, 0, 0, 0, ""
215};
216
217
218/* The hardware table. */
219
220#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
221#define A(a) (1 << CGEN_HW_##a)
222#else
223#define A(a) (1 << CGEN_HW_/**/a)
224#endif
225
226const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
227{
228 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
229 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
230 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
231 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
232 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
233 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
234 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
1951c6f7
MG		 235 { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
236 { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
93fbbb04
GK		 237 { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
238 { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
239 { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
240 { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
241 { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
242 { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
243 { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
244 { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
245 { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
246 { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
247 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
248};
249
250#undef A
251
252
253/* The instruction field table. */
254
255#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
256#define A(a) (1 << CGEN_IFLD_##a)
257#else
258#define A(a) (1 << CGEN_IFLD_/**/a)
259#endif
260
261const CGEN_IFLD xstormy16_cgen_ifld_table[] =
262{
263 { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
264 { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
265 { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
266 { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
267 { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
268 { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
269 { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
270 { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
271 { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
272 { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
273 { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
274 { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
275 { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
276 { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
277 { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
278 { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
279 { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
280 { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
281 { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
282 { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
283 { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
284 { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
285 { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
286 { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
287 { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
288 { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
289 { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
290 { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
291 { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
292 { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
293 { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
294 { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
295 { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
296 { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
297 { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
298 { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
299 { 0, 0, 0, 0, 0, 0, {0, {0}} }
300};
301
302#undef A
303
304
9a2e995d
GH		 305
306/* multi ifield declarations */
307
308const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
309
310
311/* multi ifield definitions */
312
313const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
314{
315 { 0, &(xstormy16_cgen_ifld_table[34]) },
316 { 0, &(xstormy16_cgen_ifld_table[35]) },
317 {0,0}
318};
319
93fbbb04
GK		 320/* The operand table. */
321
322#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
323#define A(a) (1 << CGEN_OPERAND_##a)
324#else
325#define A(a) (1 << CGEN_OPERAND_/**/a)
326#endif
327#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
328#define OPERAND(op) XSTORMY16_OPERAND_##op
329#else
330#define OPERAND(op) XSTORMY16_OPERAND_/**/op
331#endif
332
333const CGEN_OPERAND xstormy16_cgen_operand_table[] =
334{
335/* pc: program counter */
336 { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
9a2e995d 337 { 0, &(xstormy16_cgen_ifld_table[0]) },
93fbbb04
GK		 338 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
339/* psw-z8: */
340 { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
9a2e995d 341 { 0, 0 },
93fbbb04
GK		 342 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
343/* psw-z16: */
344 { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
9a2e995d 345 { 0, 0 },
93fbbb04
GK		 346 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
347/* psw-cy: */
348 { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
9a2e995d 349 { 0, 0 },
93fbbb04
GK		 350 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
351/* psw-hc: */
352 { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
9a2e995d 353 { 0, 0 },
93fbbb04
GK		 354 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
355/* psw-ov: */
356 { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
9a2e995d 357 { 0, 0 },
93fbbb04
GK		 358 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
359/* psw-pt: */
360 { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
9a2e995d 361 { 0, 0 },
93fbbb04
GK		 362 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
363/* psw-s: */
364 { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
9a2e995d 365 { 0, 0 },
93fbbb04
GK		 366 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
367/* Rd: general register destination */
368 { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
9a2e995d 369 { 0, &(xstormy16_cgen_ifld_table[2]) },
93fbbb04
GK		 370 { 0, { (1<<MACH_BASE) } } },
371/* Rdm: general register destination */
372 { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
9a2e995d 373 { 0, &(xstormy16_cgen_ifld_table[3]) },
93fbbb04
GK		 374 { 0, { (1<<MACH_BASE) } } },
375/* Rm: general register for memory */
376 { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
9a2e995d 377 { 0, &(xstormy16_cgen_ifld_table[4]) },
93fbbb04
GK		 378 { 0, { (1<<MACH_BASE) } } },
379/* Rs: general register source */
380 { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
9a2e995d 381 { 0, &(xstormy16_cgen_ifld_table[5]) },
93fbbb04
GK		 382 { 0, { (1<<MACH_BASE) } } },
383/* Rb: base register */
1951c6f7 384 { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
9a2e995d 385 { 0, &(xstormy16_cgen_ifld_table[6]) },
93fbbb04
GK		 386 { 0, { (1<<MACH_BASE) } } },
387/* Rbj: base register for jump */
388 { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
9a2e995d 389 { 0, &(xstormy16_cgen_ifld_table[7]) },
93fbbb04
GK		 390 { 0, { (1<<MACH_BASE) } } },
391/* bcond2: branch condition opcode */
392 { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
9a2e995d 393 { 0, &(xstormy16_cgen_ifld_table[9]) },
93fbbb04
GK		 394 { 0, { (1<<MACH_BASE) } } },
395/* ws2: word size opcode */
396 { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
9a2e995d 397 { 0, &(xstormy16_cgen_ifld_table[11]) },
93fbbb04
GK		 398 { 0, { (1<<MACH_BASE) } } },
399/* bcond5: branch condition opcode */
400 { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
9a2e995d 401 { 0, &(xstormy16_cgen_ifld_table[18]) },
93fbbb04
GK		 402 { 0, { (1<<MACH_BASE) } } },
403/* imm2: 2 bit unsigned immediate */
404 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
9a2e995d 405 { 0, &(xstormy16_cgen_ifld_table[21]) },
93fbbb04
GK		 406 { 0, { (1<<MACH_BASE) } } },
407/* imm3: 3 bit unsigned immediate */
408 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
9a2e995d 409 { 0, &(xstormy16_cgen_ifld_table[22]) },
93fbbb04
GK		 410 { 0, { (1<<MACH_BASE) } } },
411/* imm3b: 3 bit unsigned immediate for bit tests */
412 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
9a2e995d 413 { 0, &(xstormy16_cgen_ifld_table[23]) },
93fbbb04
GK		 414 { 0, { (1<<MACH_BASE) } } },
415/* imm4: 4 bit unsigned immediate */
416 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
9a2e995d 417 { 0, &(xstormy16_cgen_ifld_table[24]) },
93fbbb04
GK		 418 { 0, { (1<<MACH_BASE) } } },
419/* imm8: 8 bit unsigned immediate */
420 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
9a2e995d 421 { 0, &(xstormy16_cgen_ifld_table[25]) },
93fbbb04
GK		 422 { 0, { (1<<MACH_BASE) } } },
423/* imm8small: 8 bit unsigned immediate */
424 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
9a2e995d 425 { 0, &(xstormy16_cgen_ifld_table[25]) },
93fbbb04
GK		 426 { 0, { (1<<MACH_BASE) } } },
427/* imm12: 12 bit signed immediate */
428 { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
9a2e995d 429 { 0, &(xstormy16_cgen_ifld_table[26]) },
93fbbb04
GK		 430 { 0, { (1<<MACH_BASE) } } },
431/* imm16: 16 bit immediate */
432 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
9a2e995d 433 { 0, &(xstormy16_cgen_ifld_table[27]) },
93fbbb04
GK		 434 { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
435/* lmem8: 8 bit unsigned immediate low memory */
436 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
9a2e995d 437 { 0, &(xstormy16_cgen_ifld_table[28]) },
93fbbb04
GK		 438 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
439/* hmem8: 8 bit unsigned immediate high memory */
440 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
9a2e995d 441 { 0, &(xstormy16_cgen_ifld_table[29]) },
93fbbb04
GK		 442 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
443/* rel8-2: 8 bit relative address */
444 { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
9a2e995d 445 { 0, &(xstormy16_cgen_ifld_table[30]) },
93fbbb04
GK		 446 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
447/* rel8-4: 8 bit relative address */
448 { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
9a2e995d 449 { 0, &(xstormy16_cgen_ifld_table[31]) },
93fbbb04
GK		 450 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
451/* rel12: 12 bit relative address */
452 { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
9a2e995d 453 { 0, &(xstormy16_cgen_ifld_table[32]) },
93fbbb04
GK		 454 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
455/* rel12a: 12 bit relative address */
456 { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
9a2e995d 457 { 0, &(xstormy16_cgen_ifld_table[33]) },
93fbbb04
GK		 458 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
459/* abs24: 24 bit absolute address */
460 { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
9a2e995d 461 { 2, &(XSTORMY16_F_ABS24_MULTI_IFIELD[0]) },
93fbbb04
GK		 462 { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
463/* psw: program status word */
464 { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
9a2e995d 465 { 0, 0 },
93fbbb04
GK		 466 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
467/* Rpsw: N0-N3 of the program status word */
468 { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
9a2e995d 469 { 0, 0 },
93fbbb04
GK		 470 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
471/* sp: stack pointer */
472 { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
9a2e995d 473 { 0, 0 },
93fbbb04
GK		 474 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
475/* R0: R0 */
476 { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
9a2e995d 477 { 0, 0 },
93fbbb04
GK		 478 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
479/* R1: R1 */
480 { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
9a2e995d 481 { 0, 0 },
93fbbb04
GK		 482 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
483/* R2: R2 */
484 { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
9a2e995d 485 { 0, 0 },
93fbbb04
GK		 486 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
487/* R8: R8 */
488 { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
9a2e995d 489 { 0, 0 },
93fbbb04
GK		 490 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
491 { 0, 0, 0, 0, 0, {0, {0}} }
492};
493
494#undef A
495
496
497/* The instruction table. */
498
499#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
500#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
501#define A(a) (1 << CGEN_INSN_##a)
502#else
503#define A(a) (1 << CGEN_INSN_/**/a)
504#endif
505
506static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
507{
508 /* Special null first entry.
509 A `num' value of zero is thus invalid.
510 Also, the special `invalid' insn resides here. */
511 { 0, 0, 0, 0, {0, {0}} },
512/* mov$ws2 $lmem8,#$imm16 */
513 {
514 XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
515 { 0, { (1<<MACH_BASE) } }
516 },
517/* mov$ws2 $hmem8,#$imm16 */
518 {
519 XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
520 { 0, { (1<<MACH_BASE) } }
521 },
522/* mov$ws2 $Rm,$lmem8 */
523 {
524 XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
525 { 0, { (1<<MACH_BASE) } }
526 },
527/* mov$ws2 $Rm,$hmem8 */
528 {
529 XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
530 { 0, { (1<<MACH_BASE) } }
531 },
532/* mov$ws2 $lmem8,$Rm */
533 {
534 XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
535 { 0, { (1<<MACH_BASE) } }
536 },
537/* mov$ws2 $hmem8,$Rm */
538 {
539 XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
540 { 0, { (1<<MACH_BASE) } }
541 },
542/* mov$ws2 $Rdm,($Rs) */
543 {
544 XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
545 { 0, { (1<<MACH_BASE) } }
546 },
547/* mov$ws2 $Rdm,($Rs++) */
548 {
549 XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
550 { 0, { (1<<MACH_BASE) } }
551 },
552/* mov$ws2 $Rdm,(--$Rs) */
553 {
554 XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
555 { 0, { (1<<MACH_BASE) } }
556 },
557/* mov$ws2 ($Rs),$Rdm */
558 {
559 XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
560 { 0, { (1<<MACH_BASE) } }
561 },
562/* mov$ws2 ($Rs++),$Rdm */
563 {
564 XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
565 { 0, { (1<<MACH_BASE) } }
566 },
567/* mov$ws2 (--$Rs),$Rdm */
568 {
569 XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
570 { 0, { (1<<MACH_BASE) } }
571 },
572/* mov$ws2 $Rdm,($Rs,$imm12) */
573 {
574 XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
575 { 0, { (1<<MACH_BASE) } }
576 },
577/* mov$ws2 $Rdm,($Rs++,$imm12) */
578 {
579 XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
580 { 0, { (1<<MACH_BASE) } }
581 },
582/* mov$ws2 $Rdm,(--$Rs,$imm12) */
583 {
584 XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
585 { 0, { (1<<MACH_BASE) } }
586 },
587/* mov$ws2 ($Rs,$imm12),$Rdm */
588 {
589 XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
590 { 0, { (1<<MACH_BASE) } }
591 },
592/* mov$ws2 ($Rs++,$imm12),$Rdm */
593 {
594 XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
595 { 0, { (1<<MACH_BASE) } }
596 },
597/* mov$ws2 (--$Rs,$imm12),$Rdm */
598 {
599 XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
600 { 0, { (1<<MACH_BASE) } }
601 },
602/* mov $Rd,$Rs */
603 {
604 XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
605 { 0, { (1<<MACH_BASE) } }
606 },
607/* mov.w Rx,#$imm8 */
608 {
609 XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
610 { 0, { (1<<MACH_BASE) } }
611 },
612/* mov.w $Rm,#$imm8small */
613 {
614 XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
615 { 0, { (1<<MACH_BASE) } }
616 },
617/* mov.w $Rd,#$imm16 */
618 {
619 XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
620 { 0, { (1<<MACH_BASE) } }
621 },
622/* mov.b $Rd,RxL */
623 {
624 XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
625 { 0, { (1<<MACH_BASE) } }
626 },
627/* mov.b $Rd,RxH */
628 {
629 XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
630 { 0, { (1<<MACH_BASE) } }
631 },
632/* movf$ws2 $Rdm,($Rs) */
633 {
634 XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
635 { 0, { (1<<MACH_BASE) } }
636 },
637/* movf$ws2 $Rdm,($Rs++) */
638 {
639 XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
640 { 0, { (1<<MACH_BASE) } }
641 },
642/* movf$ws2 $Rdm,(--$Rs) */
643 {
644 XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
645 { 0, { (1<<MACH_BASE) } }
646 },
647/* movf$ws2 ($Rs),$Rdm */
648 {
649 XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
650 { 0, { (1<<MACH_BASE) } }
651 },
652/* movf$ws2 ($Rs++),$Rdm */
653 {
654 XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
655 { 0, { (1<<MACH_BASE) } }
656 },
657/* movf$ws2 (--$Rs),$Rdm */
658 {
659 XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
660 { 0, { (1<<MACH_BASE) } }
661 },
662/* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
663 {
664 XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
665 { 0, { (1<<MACH_BASE) } }
666 },
667/* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
668 {
669 XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
670 { 0, { (1<<MACH_BASE) } }
671 },
672/* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
673 {
674 XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
675 { 0, { (1<<MACH_BASE) } }
676 },
677/* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
678 {
679 XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
680 { 0, { (1<<MACH_BASE) } }
681 },
682/* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
683 {
684 XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
685 { 0, { (1<<MACH_BASE) } }
686 },
687/* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
688 {
689 XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
690 { 0, { (1<<MACH_BASE) } }
691 },
692/* mask $Rd,$Rs */
693 {
694 XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
695 { 0, { (1<<MACH_BASE) } }
696 },
697/* mask $Rd,#$imm16 */
698 {
699 XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
700 { 0, { (1<<MACH_BASE) } }
701 },
702/* push $Rd */
703 {
704 XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
705 { 0, { (1<<MACH_BASE) } }
706 },
707/* pop $Rd */
708 {
709 XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
710 { 0, { (1<<MACH_BASE) } }
711 },
712/* swpn $Rd */
713 {
714 XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
715 { 0, { (1<<MACH_BASE) } }
716 },
717/* swpb $Rd */
718 {
719 XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
720 { 0, { (1<<MACH_BASE) } }
721 },
722/* swpw $Rd,$Rs */
723 {
724 XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
725 { 0, { (1<<MACH_BASE) } }
726 },
727/* and $Rd,$Rs */
728 {
729 XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
730 { 0, { (1<<MACH_BASE) } }
731 },
732/* and Rx,#$imm8 */
733 {
734 XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
735 { 0, { (1<<MACH_BASE) } }
736 },
737/* and $Rd,#$imm16 */
738 {
739 XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
740 { 0, { (1<<MACH_BASE) } }
741 },
742/* or $Rd,$Rs */
743 {
744 XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
745 { 0, { (1<<MACH_BASE) } }
746 },
747/* or Rx,#$imm8 */
748 {
749 XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
750 { 0, { (1<<MACH_BASE) } }
751 },
752/* or $Rd,#$imm16 */
753 {
754 XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
755 { 0, { (1<<MACH_BASE) } }
756 },
757/* xor $Rd,$Rs */
758 {
759 XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
760 { 0, { (1<<MACH_BASE) } }
761 },
762/* xor Rx,#$imm8 */
763 {
764 XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
765 { 0, { (1<<MACH_BASE) } }
766 },
767/* xor $Rd,#$imm16 */
768 {
769 XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
770 { 0, { (1<<MACH_BASE) } }
771 },
772/* not $Rd */
773 {
774 XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
775 { 0, { (1<<MACH_BASE) } }
776 },
777/* add $Rd,$Rs */
778 {
779 XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
780 { 0, { (1<<MACH_BASE) } }
781 },
782/* add $Rd,#$imm4 */
783 {
784 XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
785 { 0, { (1<<MACH_BASE) } }
786 },
787/* add Rx,#$imm8 */
788 {
789 XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
790 { 0, { (1<<MACH_BASE) } }
791 },
792/* add $Rd,#$imm16 */
793 {
794 XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
795 { 0, { (1<<MACH_BASE) } }
796 },
797/* adc $Rd,$Rs */
798 {
799 XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
800 { 0, { (1<<MACH_BASE) } }
801 },
802/* adc $Rd,#$imm4 */
803 {
804 XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
805 { 0, { (1<<MACH_BASE) } }
806 },
807/* adc Rx,#$imm8 */
808 {
809 XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
810 { 0, { (1<<MACH_BASE) } }
811 },
812/* adc $Rd,#$imm16 */
813 {
814 XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
815 { 0, { (1<<MACH_BASE) } }
816 },
817/* sub $Rd,$Rs */
818 {
819 XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
820 { 0, { (1<<MACH_BASE) } }
821 },
822/* sub $Rd,#$imm4 */
823 {
824 XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
825 { 0, { (1<<MACH_BASE) } }
826 },
827/* sub Rx,#$imm8 */
828 {
829 XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
830 { 0, { (1<<MACH_BASE) } }
831 },
832/* sub $Rd,#$imm16 */
833 {
834 XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
835 { 0, { (1<<MACH_BASE) } }
836 },
837/* sbc $Rd,$Rs */
838 {
839 XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
840 { 0, { (1<<MACH_BASE) } }
841 },
842/* sbc $Rd,#$imm4 */
843 {
844 XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
845 { 0, { (1<<MACH_BASE) } }
846 },
847/* sbc Rx,#$imm8 */
848 {
849 XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
850 { 0, { (1<<MACH_BASE) } }
851 },
852/* sbc $Rd,#$imm16 */
853 {
854 XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
855 { 0, { (1<<MACH_BASE) } }
856 },
857/* inc $Rd,#$imm2 */
858 {
859 XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
860 { 0, { (1<<MACH_BASE) } }
861 },
862/* dec $Rd,#$imm2 */
863 {
864 XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
865 { 0, { (1<<MACH_BASE) } }
866 },
867/* rrc $Rd,$Rs */
868 {
869 XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
870 { 0, { (1<<MACH_BASE) } }
871 },
872/* rrc $Rd,#$imm4 */
873 {
874 XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
875 { 0, { (1<<MACH_BASE) } }
876 },
877/* rlc $Rd,$Rs */
878 {
879 XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
880 { 0, { (1<<MACH_BASE) } }
881 },
882/* rlc $Rd,#$imm4 */
883 {
884 XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
885 { 0, { (1<<MACH_BASE) } }
886 },
887/* shr $Rd,$Rs */
888 {
889 XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
890 { 0, { (1<<MACH_BASE) } }
891 },
892/* shr $Rd,#$imm4 */
893 {
894 XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
895 { 0, { (1<<MACH_BASE) } }
896 },
897/* shl $Rd,$Rs */
898 {
899 XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
900 { 0, { (1<<MACH_BASE) } }
901 },
902/* shl $Rd,#$imm4 */
903 {
904 XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
905 { 0, { (1<<MACH_BASE) } }
906 },
907/* asr $Rd,$Rs */
908 {
909 XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
910 { 0, { (1<<MACH_BASE) } }
911 },
912/* asr $Rd,#$imm4 */
913 {
914 XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
915 { 0, { (1<<MACH_BASE) } }
916 },
917/* set1 $Rd,#$imm4 */
918 {
919 XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
920 { 0, { (1<<MACH_BASE) } }
921 },
922/* set1 $Rd,$Rs */
923 {
924 XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
925 { 0, { (1<<MACH_BASE) } }
926 },
927/* set1 $lmem8,#$imm3 */
928 {
929 XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
930 { 0, { (1<<MACH_BASE) } }
931 },
932/* set1 $hmem8,#$imm3 */
933 {
934 XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
935 { 0, { (1<<MACH_BASE) } }
936 },
937/* clr1 $Rd,#$imm4 */
938 {
939 XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
940 { 0, { (1<<MACH_BASE) } }
941 },
942/* clr1 $Rd,$Rs */
943 {
944 XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
945 { 0, { (1<<MACH_BASE) } }
946 },
947/* clr1 $lmem8,#$imm3 */
948 {
949 XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
950 { 0, { (1<<MACH_BASE) } }
951 },
952/* clr1 $hmem8,#$imm3 */
953 {
954 XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
955 { 0, { (1<<MACH_BASE) } }
956 },
957/* cbw $Rd */
958 {
959 XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
960 { 0, { (1<<MACH_BASE) } }
961 },
962/* rev $Rd */
963 {
964 XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
965 { 0, { (1<<MACH_BASE) } }
966 },
967/* b$bcond5 $Rd,$Rs,$rel12 */
968 {
969 XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
970 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
971 },
972/* b$bcond5 $Rm,#$imm8,$rel12 */
973 {
974 XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
975 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
976 },
977/* b$bcond2 Rx,#$imm16,${rel8-4} */
978 {
979 XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
980 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
981 },
982/* bn $Rd,#$imm4,$rel12 */
983 {
984 XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
985 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
986 },
987/* bn $Rd,$Rs,$rel12 */
988 {
989 XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
990 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
991 },
992/* bn $lmem8,#$imm3b,$rel12 */
993 {
994 XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
995 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
996 },
997/* bn $hmem8,#$imm3b,$rel12 */
998 {
999 XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
1000 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1001 },
1002/* bp $Rd,#$imm4,$rel12 */
1003 {
1004 XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
1005 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1006 },
1007/* bp $Rd,$Rs,$rel12 */
1008 {
1009 XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
1010 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1011 },
1012/* bp $lmem8,#$imm3b,$rel12 */
1013 {
1014 XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
1015 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1016 },
1017/* bp $hmem8,#$imm3b,$rel12 */
1018 {
1019 XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
1020 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1021 },
1022/* b$bcond2 ${rel8-2} */
1023 {
1024 XSTORMY16_INSN_BCC, "bcc", "b", 16,
1025 { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1026 },
1027/* br $Rd */
1028 {
1029 XSTORMY16_INSN_BGR, "bgr", "br", 16,
1030 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1031 },
1032/* br $rel12a */
1033 {
1034 XSTORMY16_INSN_BR, "br", "br", 16,
1035 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1036 },
1037/* jmp $Rbj,$Rd */
1038 {
1039 XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
1040 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1041 },
1042/* jmpf $abs24 */
1043 {
1044 XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
1045 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1046 },
1047/* callr $Rd */
1048 {
1049 XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
1050 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1051 },
1052/* callr $rel12a */
1053 {
1054 XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
1055 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1056 },
1057/* call $Rbj,$Rd */
1058 {
1059 XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
1060 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1061 },
1062/* callf $abs24 */
1063 {
1064 XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
1065 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1066 },
1067/* icallr $Rd */
1068 {
1069 XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
1070 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1071 },
1072/* icall $Rbj,$Rd */
1073 {
1074 XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
1075 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1076 },
1077/* icallf $abs24 */
1078 {
1079 XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
1080 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1081 },
1082/* iret */
1083 {
1084 XSTORMY16_INSN_IRET, "iret", "iret", 16,
1085 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1086 },
1087/* ret */
1088 {
1089 XSTORMY16_INSN_RET, "ret", "ret", 16,
1090 { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1091 },
1092/* mul */
1093 {
1094 XSTORMY16_INSN_MUL, "mul", "mul", 16,
1095 { 0, { (1<<MACH_BASE) } }
1096 },
1097/* div */
1098 {
1099 XSTORMY16_INSN_DIV, "div", "div", 16,
1100 { 0, { (1<<MACH_BASE) } }
1101 },
193eb15d
DD		 1102/* sdiv */
1103 {
1104 XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
1105 { 0, { (1<<MACH_BASE) } }
1106 },
1107/* sdivlh */
1108 {
1109 XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
1110 { 0, { (1<<MACH_BASE) } }
1111 },
1112/* divlh */
1113 {
1114 XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
1115 { 0, { (1<<MACH_BASE) } }
1116 },
93fbbb04
GK		 1117/* nop */
1118 {
1119 XSTORMY16_INSN_NOP, "nop", "nop", 16,
1120 { 0, { (1<<MACH_BASE) } }
1121 },
1122/* halt */
1123 {
1124 XSTORMY16_INSN_HALT, "halt", "halt", 16,
1125 { 0, { (1<<MACH_BASE) } }
1126 },
1127/* hold */
1128 {
1129 XSTORMY16_INSN_HOLD, "hold", "hold", 16,
1130 { 0, { (1<<MACH_BASE) } }
1131 },
1951c6f7
MG		 1132/* holdx */
1133 {
1134 XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
1135 { 0, { (1<<MACH_BASE) } }
1136 },
93fbbb04
GK		 1137/* brk */
1138 {
1139 XSTORMY16_INSN_BRK, "brk", "brk", 16,
1140 { 0, { (1<<MACH_BASE) } }
1141 },
1142/* --unused-- */
1143 {
1144 XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
1145 { 0, { (1<<MACH_BASE) } }
1146 },
1147};
1148
1149#undef OP
1150#undef A
1151
1152/* Initialize anything needed to be done once, before any cpu_open call. */
1153static void init_tables PARAMS ((void));
1154
1155static void
1156init_tables ()
1157{
1158}
1159
1160static const CGEN_MACH * lookup_mach_via_bfd_name
1161 PARAMS ((const CGEN_MACH *, const char *));
1162static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1163static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1164static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1165static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1166static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1167
1168/* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */
1169
1170static const CGEN_MACH *
1171lookup_mach_via_bfd_name (table, name)
1172 const CGEN_MACH *table;
1173 const char *name;
1174{
1175 while (table->name)
1176 {
1177 if (strcmp (name, table->bfd_name) == 0)
1178 return table;
1179 ++table;
1180 }
1181 abort ();
1182}
1183
1184/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1185
1186static void
1187build_hw_table (cd)
1188 CGEN_CPU_TABLE *cd;
1189{
1190 int i;
1191 int machs = cd->machs;
1192 const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
1193 /* MAX_HW is only an upper bound on the number of selected entries.
1194 However each entry is indexed by it's enum so there can be holes in
1195 the table. */
1196 const CGEN_HW_ENTRY **selected =
1197 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1198
1199 cd->hw_table.init_entries = init;
1200 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1201 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1202 /* ??? For now we just use machs to determine which ones we want. */
1203 for (i = 0; init[i].name != NULL; ++i)
1204 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1205 & machs)
1206 selected[init[i].type] = &init[i];
1207 cd->hw_table.entries = selected;
1208 cd->hw_table.num_entries = MAX_HW;
1209}
1210
1211/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1212
1213static void
1214build_ifield_table (cd)
1215 CGEN_CPU_TABLE *cd;
1216{
1217 cd->ifld_table = & xstormy16_cgen_ifld_table[0];
1218}
1219
1220/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */
1221
1222static void
1223build_operand_table (cd)
1224 CGEN_CPU_TABLE *cd;
1225{
1226 int i;
1227 int machs = cd->machs;
1228 const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
1229 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1230 However each entry is indexed by it's enum so there can be holes in
1231 the table. */
1232 const CGEN_OPERAND **selected =
1233 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1234
1235 cd->operand_table.init_entries = init;
1236 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1237 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1238 /* ??? For now we just use mach to determine which ones we want. */
1239 for (i = 0; init[i].name != NULL; ++i)
1240 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1241 & machs)
1242 selected[init[i].type] = &init[i];
1243 cd->operand_table.entries = selected;
1244 cd->operand_table.num_entries = MAX_OPERANDS;
1245}
1246
1247/* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
1248 ??? This could leave out insns not supported by the specified mach/isa,
1249 but that would cause errors like "foo only supported by bar" to become
1250 "unknown insn", so for now we include all insns and require the app to
1251 do the checking later.
1252 ??? On the other hand, parsing of such insns may require their hardware or
1253 operand elements to be in the table [which they mightn't be]. */
1254
1255static void
1256build_insn_table (cd)
1257 CGEN_CPU_TABLE *cd;
1258{
1259 int i;
1260 const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
1261 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1262
1263 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1264 for (i = 0; i < MAX_INSNS; ++i)
1265 insns[i].base = &ib[i];
1266 cd->insn_table.init_entries = insns;
1267 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1268 cd->insn_table.num_init_entries = MAX_INSNS;
1269}
1270
1271/* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */
1272
1273static void
1274xstormy16_cgen_rebuild_tables (cd)
1275 CGEN_CPU_TABLE *cd;
1276{
1277 int i;
1278 unsigned int isas = cd->isas;
1279 unsigned int machs = cd->machs;
1280
1281 cd->int_insn_p = CGEN_INT_INSN_P;
1282
1283 /* Data derived from the isa spec. */
1284#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1285 cd->default_insn_bitsize = UNSET;
1286 cd->base_insn_bitsize = UNSET;
1287 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1288 cd->max_insn_bitsize = 0;
1289 for (i = 0; i < MAX_ISAS; ++i)
1290 if (((1 << i) & isas) != 0)
1291 {
1292 const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
1293
9a2e995d
GH		 1294 /* Default insn sizes of all selected isas must be
1295 equal or we set the result to 0, meaning "unknown". */
93fbbb04
GK		 1296 if (cd->default_insn_bitsize == UNSET)
1297 cd->default_insn_bitsize = isa->default_insn_bitsize;
1298 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1299 ; /* this is ok */
1300 else
1301 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1302
9a2e995d
GH		 1303 /* Base insn sizes of all selected isas must be equal
1304 or we set the result to 0, meaning "unknown". */
93fbbb04
GK		 1305 if (cd->base_insn_bitsize == UNSET)
1306 cd->base_insn_bitsize = isa->base_insn_bitsize;
1307 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1308 ; /* this is ok */
1309 else
1310 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1311
1312 /* Set min,max insn sizes. */
1313 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1314 cd->min_insn_bitsize = isa->min_insn_bitsize;
1315 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1316 cd->max_insn_bitsize = isa->max_insn_bitsize;
1317 }
1318
1319 /* Data derived from the mach spec. */
1320 for (i = 0; i < MAX_MACHS; ++i)
1321 if (((1 << i) & machs) != 0)
1322 {
1323 const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
1324
1325 if (mach->insn_chunk_bitsize != 0)
1326 {
1327 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1328 {
1329 fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1330 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1331 abort ();
1332 }
1333
1334 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1335 }
1336 }
1337
1338 /* Determine which hw elements are used by MACH. */
1339 build_hw_table (cd);
1340
1341 /* Build the ifield table. */
1342 build_ifield_table (cd);
1343
1344 /* Determine which operands are used by MACH/ISA. */
1345 build_operand_table (cd);
1346
1347 /* Build the instruction table. */
1348 build_insn_table (cd);
1349}
1350
1351/* Initialize a cpu table and return a descriptor.
1352 It's much like opening a file, and must be the first function called.
1353 The arguments are a set of (type/value) pairs, terminated with
1354 CGEN_CPU_OPEN_END.
1355
1356 Currently supported values:
1357 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1358 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1359 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1360 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1361 CGEN_CPU_OPEN_END: terminates arguments
1362
1363 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1364 precluded.
1365
1366 ??? We only support ISO C stdargs here, not K&R.
1367 Laziness, plus experiment to see if anything requires K&R - eventually
1368 K&R will no longer be supported - e.g. GDB is currently trying this. */
1369
1370CGEN_CPU_DESC
1371xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1372{
1373 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1374 static int init_p;
1375 unsigned int isas = 0; /* 0 = "unspecified" */
1376 unsigned int machs = 0; /* 0 = "unspecified" */
1377 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1378 va_list ap;
1379
1380 if (! init_p)
1381 {
1382 init_tables ();
1383 init_p = 1;
1384 }
1385
1386 memset (cd, 0, sizeof (*cd));
1387
1388 va_start (ap, arg_type);
1389 while (arg_type != CGEN_CPU_OPEN_END)
1390 {
1391 switch (arg_type)
1392 {
1393 case CGEN_CPU_OPEN_ISAS :
1394 isas = va_arg (ap, unsigned int);
1395 break;
1396 case CGEN_CPU_OPEN_MACHS :
1397 machs = va_arg (ap, unsigned int);
1398 break;
1399 case CGEN_CPU_OPEN_BFDMACH :
1400 {
1401 const char *name = va_arg (ap, const char *);
1402 const CGEN_MACH *mach =
1403 lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
1404
1405 machs |= 1 << mach->num;
1406 break;
1407 }
1408 case CGEN_CPU_OPEN_ENDIAN :
1409 endian = va_arg (ap, enum cgen_endian);
1410 break;
1411 default :
1412 fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
1413 arg_type);
1414 abort (); /* ??? return NULL? */
1415 }
1416 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1417 }
1418 va_end (ap);
1419
1420 /* mach unspecified means "all" */
1421 if (machs == 0)
1422 machs = (1 << MAX_MACHS) - 1;
1423 /* base mach is always selected */
1424 machs |= 1;
1425 /* isa unspecified means "all" */
1426 if (isas == 0)
1427 isas = (1 << MAX_ISAS) - 1;
1428 if (endian == CGEN_ENDIAN_UNKNOWN)
1429 {
1430 /* ??? If target has only one, could have a default. */
1431 fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
1432 abort ();
1433 }
1434
1435 cd->isas = isas;
1436 cd->machs = machs;
1437 cd->endian = endian;
1438 /* FIXME: for the sparc case we can determine insn-endianness statically.
1439 The worry here is where both data and insn endian can be independently
1440 chosen, in which case this function will need another argument.
1441 Actually, will want to allow for more arguments in the future anyway. */
1442 cd->insn_endian = endian;
1443
1444 /* Table (re)builder. */
1445 cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
1446 xstormy16_cgen_rebuild_tables (cd);
1447
1448 /* Default to not allowing signed overflow. */
1449 cd->signed_overflow_ok_p = 0;
1450
1451 return (CGEN_CPU_DESC) cd;
1452}
1453
1454/* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1455 MACH_NAME is the bfd name of the mach. */
1456
1457CGEN_CPU_DESC
1458xstormy16_cgen_cpu_open_1 (mach_name, endian)
1459 const char *mach_name;
1460 enum cgen_endian endian;
1461{
1462 return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1463 CGEN_CPU_OPEN_ENDIAN, endian,
1464 CGEN_CPU_OPEN_END);
1465}
1466
1467/* Close a cpu table.
1468 ??? This can live in a machine independent file, but there's currently
1469 no place to put this file (there's no libcgen). libopcodes is the wrong
1470 place as some simulator ports use this but they don't use libopcodes. */
1471
1472void
1473xstormy16_cgen_cpu_close (cd)
1474 CGEN_CPU_DESC cd;
1475{
a978a3e5
NC		 1476 unsigned int i;
1477 CGEN_INSN *insns;
1478
1479 if (cd->macro_insn_table.init_entries)
1480 {
1481 insns = cd->macro_insn_table.init_entries;
1482 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1483 {
1484 if (CGEN_INSN_RX ((insns)))
1485 regfree(CGEN_INSN_RX (insns));
1486 }
1487 }
1488
1489 if (cd->insn_table.init_entries)
1490 {
1491 insns = cd->insn_table.init_entries;
1492 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1493 {
1494 if (CGEN_INSN_RX (insns))
1495 regfree(CGEN_INSN_RX (insns));
1496 }
1497 }
1498
1499
1500
1501 if (cd->macro_insn_table.init_entries)
1502 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1503
93fbbb04
GK		 1504 if (cd->insn_table.init_entries)
1505 free ((CGEN_INSN *) cd->insn_table.init_entries);
a978a3e5 1506
93fbbb04
GK		 1507 if (cd->hw_table.entries)
1508 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
a978a3e5
NC		 1509
1510 if (cd->operand_table.entries)
1511 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1512
93fbbb04
GK		 1513 free (cd);
1514}
1515
GDB Binutils - Deliverables
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