drivers/gpu/drm/i915/intel_bios.h

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #ifndef _INTEL_BIOS_H_
  29 #define _INTEL_BIOS_H_
  30
  31 /**
  32  * struct vbt_header - VBT Header structure
  33  * @signature:          VBT signature, always starts with "$VBT"
  34  * @version:            Version of this structure
  35  * @header_size:        Size of this structure
  36  * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  37  * @vbt_checksum:       Checksum
  38  * @reserved0:          Reserved
  39  * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  40  * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  41  */
  42 struct vbt_header {
  43         u8 signature[20];
  44         u16 version;
  45         u16 header_size;
  46         u16 vbt_size;
  47         u8 vbt_checksum;
  48         u8 reserved0;
  49         u32 bdb_offset;
  50         u32 aim_offset[4];
  51 } __packed;
  52
  53 /**
  54  * struct bdb_header - BDB Header structure
  55  * @signature:          BDB signature "BIOS_DATA_BLOCK"
  56  * @version:            Version of the data block definitions
  57  * @header_size:        Size of this structure
  58  * @bdb_size:           Size of BDB (BDB Header and data blocks)
  59  */
  60 struct bdb_header {
  61         u8 signature[16];
  62         u16 version;
  63         u16 header_size;
  64         u16 bdb_size;
  65 } __packed;
  66
  67 /* strictly speaking, this is a "skip" block, but it has interesting info */
  68 struct vbios_data {
  69         u8 type; /* 0 == desktop, 1 == mobile */
  70         u8 relstage;
  71         u8 chipset;
  72         u8 lvds_present:1;
  73         u8 tv_present:1;
  74         u8 rsvd2:6; /* finish byte */
  75         u8 rsvd3[4];
  76         u8 signon[155];
  77         u8 copyright[61];
  78         u16 code_segment;
  79         u8 dos_boot_mode;
  80         u8 bandwidth_percent;
  81         u8 rsvd4; /* popup memory size */
  82         u8 resize_pci_bios;
  83         u8 rsvd5; /* is crt already on ddc2 */
  84 } __packed;
  85
  86 /*
  87  * There are several types of BIOS data blocks (BDBs), each block has
  88  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  89  * Known types are listed below.
  90  */
  91 #define BDB_GENERAL_FEATURES      1
  92 #define BDB_GENERAL_DEFINITIONS   2
  93 #define BDB_OLD_TOGGLE_LIST       3
  94 #define BDB_MODE_SUPPORT_LIST     4
  95 #define BDB_GENERIC_MODE_TABLE    5
  96 #define BDB_EXT_MMIO_REGS         6
  97 #define BDB_SWF_IO                7
  98 #define BDB_SWF_MMIO              8
  99 #define BDB_PSR                   9
 100 #define BDB_MODE_REMOVAL_TABLE   10
 101 #define BDB_CHILD_DEVICE_TABLE   11
 102 #define BDB_DRIVER_FEATURES      12
 103 #define BDB_DRIVER_PERSISTENCE   13
 104 #define BDB_EXT_TABLE_PTRS       14
 105 #define BDB_DOT_CLOCK_OVERRIDE   15
 106 #define BDB_DISPLAY_SELECT       16
 107 /* 17 rsvd */
 108 #define BDB_DRIVER_ROTATION      18
 109 #define BDB_DISPLAY_REMOVE       19
 110 #define BDB_OEM_CUSTOM           20
 111 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
 112 #define BDB_SDVO_LVDS_OPTIONS    22
 113 #define BDB_SDVO_PANEL_DTDS      23
 114 #define BDB_SDVO_LVDS_PNP_IDS    24
 115 #define BDB_SDVO_LVDS_POWER_SEQ  25
 116 #define BDB_TV_OPTIONS           26
 117 #define BDB_EDP                  27
 118 #define BDB_LVDS_OPTIONS         40
 119 #define BDB_LVDS_LFP_DATA_PTRS   41
 120 #define BDB_LVDS_LFP_DATA        42
 121 #define BDB_LVDS_BACKLIGHT       43
 122 #define BDB_LVDS_POWER           44
 123 #define BDB_MIPI_CONFIG          52
 124 #define BDB_MIPI_SEQUENCE        53
 125 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 126
 127 struct bdb_general_features {
 128         /* bits 1 */
 129         u8 panel_fitting:2;
 130         u8 flexaim:1;
 131         u8 msg_enable:1;
 132         u8 clear_screen:3;
 133         u8 color_flip:1;
 134
 135         /* bits 2 */
 136         u8 download_ext_vbt:1;
 137         u8 enable_ssc:1;
 138         u8 ssc_freq:1;
 139         u8 enable_lfp_on_override:1;
 140         u8 disable_ssc_ddt:1;
 141         u8 rsvd7:1;
 142         u8 display_clock_mode:1;
 143         u8 rsvd8:1; /* finish byte */
 144
 145         /* bits 3 */
 146         u8 disable_smooth_vision:1;
 147         u8 single_dvi:1;
 148         u8 rsvd9:1;
 149         u8 fdi_rx_polarity_inverted:1;
 150         u8 rsvd10:4; /* finish byte */
 151
 152         /* bits 4 */
 153         u8 legacy_monitor_detect;
 154
 155         /* bits 5 */
 156         u8 int_crt_support:1;
 157         u8 int_tv_support:1;
 158         u8 int_efp_support:1;
 159         u8 dp_ssc_enb:1;        /* PCH attached eDP supports SSC */
 160         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 161         u8 rsvd11:3; /* finish byte */
 162 } __packed;
 163
 164 /* pre-915 */
 165 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 166 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 167 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 168 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 169
 170 /* Pre 915 */
 171 #define DEVICE_TYPE_NONE        0x00
 172 #define DEVICE_TYPE_CRT         0x01
 173 #define DEVICE_TYPE_TV          0x09
 174 #define DEVICE_TYPE_EFP         0x12
 175 #define DEVICE_TYPE_LFP         0x22
 176 /* On 915+ */
 177 #define DEVICE_TYPE_CRT_DPMS            0x6001
 178 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 179 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 180 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 181 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 182 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 183 #define DEVICE_TYPE_TV_SCART            0x0209
 184 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 185 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 186 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 187 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 188 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 189 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 190 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 191 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 192 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 193 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 194 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 195 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 196 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 197
 198 #define DEVICE_CFG_NONE         0x00
 199 #define DEVICE_CFG_12BIT_DVOB   0x01
 200 #define DEVICE_CFG_12BIT_DVOC   0x02
 201 #define DEVICE_CFG_24BIT_DVOBC  0x09
 202 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 203 #define DEVICE_CFG_DUAL_DVOB    0x11
 204 #define DEVICE_CFG_DUAL_DVOC    0x12
 205 #define DEVICE_CFG_DUAL_DVOBC   0x13
 206 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 207 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 208
 209 #define DEVICE_WIRE_NONE        0x00
 210 #define DEVICE_WIRE_DVOB        0x01
 211 #define DEVICE_WIRE_DVOC        0x02
 212 #define DEVICE_WIRE_DVOBC       0x03
 213 #define DEVICE_WIRE_DVOBB       0x05
 214 #define DEVICE_WIRE_DVOCC       0x06
 215 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 216 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 217
 218 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 219 #define DEVICE_PORT_DVOB        0x01
 220 #define DEVICE_PORT_DVOC        0x02
 221
 222 /*
 223  * We used to keep this struct but without any version control. We should avoid
 224  * using it in the future, but it should be safe to keep using it in the old
 225  * code. Do not change; we rely on its size.
 226  */
 227 struct old_child_dev_config {
 228         u16 handle;
 229         u16 device_type;
 230         u8  device_id[10]; /* ascii string */
 231         u16 addin_offset;
 232         u8  dvo_port; /* See Device_PORT_* above */
 233         u8  i2c_pin;
 234         u8  slave_addr;
 235         u8  ddc_pin;
 236         u16 edid_ptr;
 237         u8  dvo_cfg; /* See DEVICE_CFG_* above */
 238         u8  dvo2_port;
 239         u8  i2c2_pin;
 240         u8  slave2_addr;
 241         u8  ddc2_pin;
 242         u8  capabilities;
 243         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
 244         u8  dvo2_wiring;
 245         u16 extended_type;
 246         u8  dvo_function;
 247 } __packed;
 248
 249 /* This one contains field offsets that are known to be common for all BDB
 250  * versions. Notice that the meaning of the contents contents may still change,
 251  * but at least the offsets are consistent. */
 252
 253 /* Definitions for flags_1 */
 254 #define IBOOST_ENABLE (1<<3)
 255
 256 struct common_child_dev_config {
 257         u16 handle;
 258         u16 device_type;
 259         u8 not_common1[12];
 260         u8 dvo_port;
 261         u8 not_common2[2];
 262         u8 ddc_pin;
 263         u16 edid_ptr;
 264         u8 obsolete;
 265         u8 flags_1;
 266         u8 not_common3[13];
 267         u8 iboost_level;
 268 } __packed;
 269
 270
 271 /* This field changes depending on the BDB version, so the most reliable way to
 272  * read it is by checking the BDB version and reading the raw pointer. */
 273 union child_device_config {
 274         /* This one is safe to be used anywhere, but the code should still check
 275          * the BDB version. */
 276         u8 raw[33];
 277         /* This one should only be kept for legacy code. */
 278         struct old_child_dev_config old;
 279         /* This one should also be safe to use anywhere, even without version
 280          * checks. */
 281         struct common_child_dev_config common;
 282 } __packed;
 283
 284 struct bdb_general_definitions {
 285         /* DDC GPIO */
 286         u8 crt_ddc_gmbus_pin;
 287
 288         /* DPMS bits */
 289         u8 dpms_acpi:1;
 290         u8 skip_boot_crt_detect:1;
 291         u8 dpms_aim:1;
 292         u8 rsvd1:5; /* finish byte */
 293
 294         /* boot device bits */
 295         u8 boot_display[2];
 296         u8 child_dev_size;
 297
 298         /*
 299          * Device info:
 300          * If TV is present, it'll be at devices[0].
 301          * LVDS will be next, either devices[0] or [1], if present.
 302          * On some platforms the number of device is 6. But could be as few as
 303          * 4 if both TV and LVDS are missing.
 304          * And the device num is related with the size of general definition
 305          * block. It is obtained by using the following formula:
 306          * number = (block_size - sizeof(bdb_general_definitions))/
 307          *           defs->child_dev_size;
 308          */
 309         uint8_t devices[0];
 310 } __packed;
 311
 312 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 313 #define MODE_MASK               0x3
 314
 315 struct bdb_lvds_options {
 316         u8 panel_type;
 317         u8 rsvd1;
 318         /* LVDS capabilities, stored in a dword */
 319         u8 pfit_mode:2;
 320         u8 pfit_text_mode_enhanced:1;
 321         u8 pfit_gfx_mode_enhanced:1;
 322         u8 pfit_ratio_auto:1;
 323         u8 pixel_dither:1;
 324         u8 lvds_edid:1;
 325         u8 rsvd2:1;
 326         u8 rsvd4;
 327         /* LVDS Panel channel bits stored here */
 328         u32 lvds_panel_channel_bits;
 329         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 330         u16 ssc_bits;
 331         u16 ssc_freq;
 332         u16 ssc_ddt;
 333         /* Panel color depth defined here */
 334         u16 panel_color_depth;
 335         /* LVDS panel type bits stored here */
 336         u32 dps_panel_type_bits;
 337         /* LVDS backlight control type bits stored here */
 338         u32 blt_control_type_bits;
 339 } __packed;
 340
 341 /* LFP pointer table contains entries to the struct below */
 342 struct bdb_lvds_lfp_data_ptr {
 343         u16 fp_timing_offset; /* offsets are from start of bdb */
 344         u8 fp_table_size;
 345         u16 dvo_timing_offset;
 346         u8 dvo_table_size;
 347         u16 panel_pnp_id_offset;
 348         u8 pnp_table_size;
 349 } __packed;
 350
 351 struct bdb_lvds_lfp_data_ptrs {
 352         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 353         struct bdb_lvds_lfp_data_ptr ptr[16];
 354 } __packed;
 355
 356 /* LFP data has 3 blocks per entry */
 357 struct lvds_fp_timing {
 358         u16 x_res;
 359         u16 y_res;
 360         u32 lvds_reg;
 361         u32 lvds_reg_val;
 362         u32 pp_on_reg;
 363         u32 pp_on_reg_val;
 364         u32 pp_off_reg;
 365         u32 pp_off_reg_val;
 366         u32 pp_cycle_reg;
 367         u32 pp_cycle_reg_val;
 368         u32 pfit_reg;
 369         u32 pfit_reg_val;
 370         u16 terminator;
 371 } __packed;
 372
 373 struct lvds_dvo_timing {
 374         u16 clock;              /**< In 10khz */
 375         u8 hactive_lo;
 376         u8 hblank_lo;
 377         u8 hblank_hi:4;
 378         u8 hactive_hi:4;
 379         u8 vactive_lo;
 380         u8 vblank_lo;
 381         u8 vblank_hi:4;
 382         u8 vactive_hi:4;
 383         u8 hsync_off_lo;
 384         u8 hsync_pulse_width;
 385         u8 vsync_pulse_width:4;
 386         u8 vsync_off:4;
 387         u8 rsvd0:6;
 388         u8 hsync_off_hi:2;
 389         u8 h_image;
 390         u8 v_image;
 391         u8 max_hv;
 392         u8 h_border;
 393         u8 v_border;
 394         u8 rsvd1:3;
 395         u8 digital:2;
 396         u8 vsync_positive:1;
 397         u8 hsync_positive:1;
 398         u8 rsvd2:1;
 399 } __packed;
 400
 401 struct lvds_pnp_id {
 402         u16 mfg_name;
 403         u16 product_code;
 404         u32 serial;
 405         u8 mfg_week;
 406         u8 mfg_year;
 407 } __packed;
 408
 409 struct bdb_lvds_lfp_data_entry {
 410         struct lvds_fp_timing fp_timing;
 411         struct lvds_dvo_timing dvo_timing;
 412         struct lvds_pnp_id pnp_id;
 413 } __packed;
 414
 415 struct bdb_lvds_lfp_data {
 416         struct bdb_lvds_lfp_data_entry data[16];
 417 } __packed;
 418
 419 #define BDB_BACKLIGHT_TYPE_NONE 0
 420 #define BDB_BACKLIGHT_TYPE_PWM  2
 421
 422 struct bdb_lfp_backlight_data_entry {
 423         u8 type:2;
 424         u8 active_low_pwm:1;
 425         u8 obsolete1:5;
 426         u16 pwm_freq_hz;
 427         u8 min_brightness;
 428         u8 obsolete2;
 429         u8 obsolete3;
 430 } __packed;
 431
 432 struct bdb_lfp_backlight_data {
 433         u8 entry_size;
 434         struct bdb_lfp_backlight_data_entry data[16];
 435         u8 level[16];
 436 } __packed;
 437
 438 struct aimdb_header {
 439         char signature[16];
 440         char oem_device[20];
 441         u16 aimdb_version;
 442         u16 aimdb_header_size;
 443         u16 aimdb_size;
 444 } __packed;
 445
 446 struct aimdb_block {
 447         u8 aimdb_id;
 448         u16 aimdb_size;
 449 } __packed;
 450
 451 struct vch_panel_data {
 452         u16 fp_timing_offset;
 453         u8 fp_timing_size;
 454         u16 dvo_timing_offset;
 455         u8 dvo_timing_size;
 456         u16 text_fitting_offset;
 457         u8 text_fitting_size;
 458         u16 graphics_fitting_offset;
 459         u8 graphics_fitting_size;
 460 } __packed;
 461
 462 struct vch_bdb_22 {
 463         struct aimdb_block aimdb_block;
 464         struct vch_panel_data panels[16];
 465 } __packed;
 466
 467 struct bdb_sdvo_lvds_options {
 468         u8 panel_backlight;
 469         u8 h40_set_panel_type;
 470         u8 panel_type;
 471         u8 ssc_clk_freq;
 472         u16 als_low_trip;
 473         u16 als_high_trip;
 474         u8 sclalarcoeff_tab_row_num;
 475         u8 sclalarcoeff_tab_row_size;
 476         u8 coefficient[8];
 477         u8 panel_misc_bits_1;
 478         u8 panel_misc_bits_2;
 479         u8 panel_misc_bits_3;
 480         u8 panel_misc_bits_4;
 481 } __packed;
 482
 483
 484 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 485 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 486 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 487 #define BDB_DRIVER_FEATURE_EDP                  3
 488
 489 struct bdb_driver_features {
 490         u8 boot_dev_algorithm:1;
 491         u8 block_display_switch:1;
 492         u8 allow_display_switch:1;
 493         u8 hotplug_dvo:1;
 494         u8 dual_view_zoom:1;
 495         u8 int15h_hook:1;
 496         u8 sprite_in_clone:1;
 497         u8 primary_lfp_id:1;
 498
 499         u16 boot_mode_x;
 500         u16 boot_mode_y;
 501         u8 boot_mode_bpp;
 502         u8 boot_mode_refresh;
 503
 504         u16 enable_lfp_primary:1;
 505         u16 selective_mode_pruning:1;
 506         u16 dual_frequency:1;
 507         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 508         u16 nt_clone_support:1;
 509         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 510         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 511         u16 cui_aspect_scaling:1;
 512         u16 preserve_aspect_ratio:1;
 513         u16 sdvo_device_power_down:1;
 514         u16 crt_hotplug:1;
 515         u16 lvds_config:2;
 516         u16 tv_hotplug:1;
 517         u16 hdmi_config:2;
 518
 519         u8 static_display:1;
 520         u8 reserved2:7;
 521         u16 legacy_crt_max_x;
 522         u16 legacy_crt_max_y;
 523         u8 legacy_crt_max_refresh;
 524
 525         u8 hdmi_termination;
 526         u8 custom_vbt_version;
 527         /* Driver features data block */
 528         u16 rmpm_enabled:1;
 529         u16 s2ddt_enabled:1;
 530         u16 dpst_enabled:1;
 531         u16 bltclt_enabled:1;
 532         u16 adb_enabled:1;
 533         u16 drrs_enabled:1;
 534         u16 grs_enabled:1;
 535         u16 gpmt_enabled:1;
 536         u16 tbt_enabled:1;
 537         u16 psr_enabled:1;
 538         u16 ips_enabled:1;
 539         u16 reserved3:4;
 540         u16 pc_feature_valid:1;
 541 } __packed;
 542
 543 #define EDP_18BPP       0
 544 #define EDP_24BPP       1
 545 #define EDP_30BPP       2
 546 #define EDP_RATE_1_62   0
 547 #define EDP_RATE_2_7    1
 548 #define EDP_LANE_1      0
 549 #define EDP_LANE_2      1
 550 #define EDP_LANE_4      3
 551 #define EDP_PREEMPHASIS_NONE    0
 552 #define EDP_PREEMPHASIS_3_5dB   1
 553 #define EDP_PREEMPHASIS_6dB     2
 554 #define EDP_PREEMPHASIS_9_5dB   3
 555 #define EDP_VSWING_0_4V         0
 556 #define EDP_VSWING_0_6V         1
 557 #define EDP_VSWING_0_8V         2
 558 #define EDP_VSWING_1_2V         3
 559
 560 struct edp_power_seq {
 561         u16 t1_t3;
 562         u16 t8;
 563         u16 t9;
 564         u16 t10;
 565         u16 t11_t12;
 566 } __packed;
 567
 568 struct edp_link_params {
 569         u8 rate:4;
 570         u8 lanes:4;
 571         u8 preemphasis:4;
 572         u8 vswing:4;
 573 } __packed;
 574
 575 struct bdb_edp {
 576         struct edp_power_seq power_seqs[16];
 577         u32 color_depth;
 578         struct edp_link_params link_params[16];
 579         u32 sdrrs_msa_timing_delay;
 580
 581         /* ith bit indicates enabled/disabled for (i+1)th panel */
 582         u16 edp_s3d_feature;
 583         u16 edp_t3_optimization;
 584         u64 edp_vswing_preemph;         /* v173 */
 585 } __packed;
 586
 587 struct psr_table {
 588         /* Feature bits */
 589         u8 full_link:1;
 590         u8 require_aux_to_wakeup:1;
 591         u8 feature_bits_rsvd:6;
 592
 593         /* Wait times */
 594         u8 idle_frames:4;
 595         u8 lines_to_wait:3;
 596         u8 wait_times_rsvd:1;
 597
 598         /* TP wake up time in multiple of 100 */
 599         u16 tp1_wakeup_time;
 600         u16 tp2_tp3_wakeup_time;
 601 } __packed;
 602
 603 struct bdb_psr {
 604         struct psr_table psr_table[16];
 605 } __packed;
 606
 607 /*
 608  * Driver<->VBIOS interaction occurs through scratch bits in
 609  * GR18 & SWF*.
 610  */
 611
 612 /* GR18 bits are set on display switch and hotkey events */
 613 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 614 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 615 #define   GR18_HK_NONE          (0x0<<3)
 616 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 617 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 618 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 619 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 620 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 621 #define   GR18_HK_PFIT          (0x8<<3)
 622 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 623 #define   GR18_HK_MULTIPLE      (0xc<<3)
 624 #define GR18_USER_INT_EN        (1<<2)
 625 #define GR18_A0000_FLUSH_EN     (1<<1)
 626 #define GR18_SMM_EN             (1<<0)
 627
 628 /* Set by driver, cleared by VBIOS */
 629 #define SWF00_YRES_SHIFT        16
 630 #define SWF00_XRES_SHIFT        0
 631 #define SWF00_RES_MASK          0xffff
 632
 633 /* Set by VBIOS at boot time and driver at runtime */
 634 #define SWF01_TV2_FORMAT_SHIFT  8
 635 #define SWF01_TV1_FORMAT_SHIFT  0
 636 #define SWF01_TV_FORMAT_MASK    0xffff
 637
 638 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 639 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 640 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 641 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 642 #define   SWF10_OLD_TOGGLE      0x0
 643 #define   SWF10_TOGGLE_LIST_1   0x1
 644 #define   SWF10_TOGGLE_LIST_2   0x2
 645 #define   SWF10_TOGGLE_LIST_3   0x3
 646 #define   SWF10_TOGGLE_LIST_4   0x4
 647 #define SWF10_PANNING_EN        (1<<23)
 648 #define SWF10_DRIVER_LOADED     (1<<22)
 649 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 650 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 651 #define SWF10_OVERLAY_EN        (1<<19)
 652 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 653 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 654 #define SWF10_VGA_HOLDOFF       (1<<16)
 655 #define SWF10_ACTIVE_DISP_MASK  0xffff
 656 #define   SWF10_PIPEB_LFP2      (1<<15)
 657 #define   SWF10_PIPEB_EFP2      (1<<14)
 658 #define   SWF10_PIPEB_TV2       (1<<13)
 659 #define   SWF10_PIPEB_CRT2      (1<<12)
 660 #define   SWF10_PIPEB_LFP       (1<<11)
 661 #define   SWF10_PIPEB_EFP       (1<<10)
 662 #define   SWF10_PIPEB_TV        (1<<9)
 663 #define   SWF10_PIPEB_CRT       (1<<8)
 664 #define   SWF10_PIPEA_LFP2      (1<<7)
 665 #define   SWF10_PIPEA_EFP2      (1<<6)
 666 #define   SWF10_PIPEA_TV2       (1<<5)
 667 #define   SWF10_PIPEA_CRT2      (1<<4)
 668 #define   SWF10_PIPEA_LFP       (1<<3)
 669 #define   SWF10_PIPEA_EFP       (1<<2)
 670 #define   SWF10_PIPEA_TV        (1<<1)
 671 #define   SWF10_PIPEA_CRT       (1<<0)
 672
 673 #define SWF11_MEMORY_SIZE_SHIFT 16
 674 #define SWF11_SV_TEST_EN        (1<<15)
 675 #define SWF11_IS_AGP            (1<<14)
 676 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 677 #define SWF11_DPMS_REDUCED      (1<<12)
 678 #define SWF11_IS_VBE_MODE       (1<<11)
 679 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 680 #define SWF11_DPMS_MASK         0x07
 681 #define   SWF11_DPMS_OFF        (1<<2)
 682 #define   SWF11_DPMS_SUSPEND    (1<<1)
 683 #define   SWF11_DPMS_STANDBY    (1<<0)
 684 #define   SWF11_DPMS_ON         0
 685
 686 #define SWF14_GFX_PFIT_EN       (1<<31)
 687 #define SWF14_TEXT_PFIT_EN      (1<<30)
 688 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 689 #define SWF14_POPUP_EN          (1<<28)
 690 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 691 #define SWF14_DISP_DETECT_EN    (1<<26)
 692 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 693 #define SWF14_DRIVER_STATUS     (1<<24)
 694 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 695 #define SWF14_OS_TYPE_WINNT     (1<<22)
 696 /* 21:19 rsvd */
 697 #define SWF14_PM_TYPE_MASK      0x00070000
 698 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 699 #define   SWF14_PM_ACPI         (0x3 << 16)
 700 #define   SWF14_PM_APM_12       (0x2 << 16)
 701 #define   SWF14_PM_APM_11       (0x1 << 16)
 702 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 703           /* if GR18 indicates a display switch */
 704 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 705 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 706 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 707 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 708 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 709 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 710 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 711 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 712 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 713 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 714 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 715 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 716 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 717 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 718 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 719 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 720           /* if GR18 indicates a panel fitting request */
 721 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 722           /* if GR18 indicates an APM change request */
 723 #define   SWF14_APM_HIBERNATE   0x4
 724 #define   SWF14_APM_SUSPEND     0x3
 725 #define   SWF14_APM_STANDBY     0x1
 726 #define   SWF14_APM_RESTORE     0x0
 727
 728 /* Add the device class for LFP, TV, HDMI */
 729 #define  DEVICE_TYPE_INT_LFP    0x1022
 730 #define  DEVICE_TYPE_INT_TV     0x1009
 731 #define  DEVICE_TYPE_HDMI       0x60D2
 732 #define  DEVICE_TYPE_DP         0x68C6
 733 #define  DEVICE_TYPE_eDP        0x78C6
 734
 735 #define  DEVICE_TYPE_CLASS_EXTENSION    (1 << 15)
 736 #define  DEVICE_TYPE_POWER_MANAGEMENT   (1 << 14)
 737 #define  DEVICE_TYPE_HOTPLUG_SIGNALING  (1 << 13)
 738 #define  DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
 739 #define  DEVICE_TYPE_NOT_HDMI_OUTPUT    (1 << 11)
 740 #define  DEVICE_TYPE_MIPI_OUTPUT        (1 << 10)
 741 #define  DEVICE_TYPE_COMPOSITE_OUTPUT   (1 << 9)
 742 #define  DEVICE_TYPE_DUAL_CHANNEL       (1 << 8)
 743 #define  DEVICE_TYPE_HIGH_SPEED_LINK    (1 << 6)
 744 #define  DEVICE_TYPE_LVDS_SINGALING     (1 << 5)
 745 #define  DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
 746 #define  DEVICE_TYPE_VIDEO_SIGNALING    (1 << 3)
 747 #define  DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
 748 #define  DEVICE_TYPE_DIGITAL_OUTPUT     (1 << 1)
 749 #define  DEVICE_TYPE_ANALOG_OUTPUT      (1 << 0)
 750
 751 /*
 752  * Bits we care about when checking for DEVICE_TYPE_eDP
 753  * Depending on the system, the other bits may or may not
 754  * be set for eDP outputs.
 755  */
 756 #define DEVICE_TYPE_eDP_BITS \
 757         (DEVICE_TYPE_INTERNAL_CONNECTOR | \
 758          DEVICE_TYPE_MIPI_OUTPUT | \
 759          DEVICE_TYPE_COMPOSITE_OUTPUT | \
 760          DEVICE_TYPE_DUAL_CHANNEL | \
 761          DEVICE_TYPE_LVDS_SINGALING | \
 762          DEVICE_TYPE_TMDS_DVI_SIGNALING | \
 763          DEVICE_TYPE_VIDEO_SIGNALING | \
 764          DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
 765          DEVICE_TYPE_ANALOG_OUTPUT)
 766
 767 /* define the DVO port for HDMI output type */
 768 #define         DVO_B           1
 769 #define         DVO_C           2
 770 #define         DVO_D           3
 771
 772 /* Possible values for the "DVO Port" field for versions >= 155: */
 773 #define DVO_PORT_HDMIA  0
 774 #define DVO_PORT_HDMIB  1
 775 #define DVO_PORT_HDMIC  2
 776 #define DVO_PORT_HDMID  3
 777 #define DVO_PORT_LVDS   4
 778 #define DVO_PORT_TV     5
 779 #define DVO_PORT_CRT    6
 780 #define DVO_PORT_DPB    7
 781 #define DVO_PORT_DPC    8
 782 #define DVO_PORT_DPD    9
 783 #define DVO_PORT_DPA    10
 784 #define DVO_PORT_DPE    11
 785 #define DVO_PORT_HDMIE  12
 786 #define DVO_PORT_MIPIA  21
 787 #define DVO_PORT_MIPIB  22
 788 #define DVO_PORT_MIPIC  23
 789 #define DVO_PORT_MIPID  24
 790
 791 /* Block 52 contains MIPI Panel info
 792  * 6 such enteries will there. Index into correct
 793  * entery is based on the panel_index in #40 LFP
 794  */
 795 #define MAX_MIPI_CONFIGURATIONS 6
 796
 797 #define MIPI_DSI_UNDEFINED_PANEL_ID     0
 798 #define MIPI_DSI_GENERIC_PANEL_ID       1
 799
 800 /*
 801  * PMIC vs SoC Backlight support specified in pwm_blc
 802  * field in mipi_config block below.
 803 */
 804 #define PPS_BLC_PMIC   0
 805 #define PPS_BLC_SOC    1
 806
 807 struct mipi_config {
 808         u16 panel_id;
 809
 810         /* General Params */
 811         u32 enable_dithering:1;
 812         u32 rsvd1:1;
 813         u32 is_bridge:1;
 814
 815         u32 panel_arch_type:2;
 816         u32 is_cmd_mode:1;
 817
 818 #define NON_BURST_SYNC_PULSE    0x1
 819 #define NON_BURST_SYNC_EVENTS   0x2
 820 #define BURST_MODE              0x3
 821         u32 video_transfer_mode:2;
 822
 823         u32 cabc_supported:1;
 824         u32 pwm_blc:1;
 825
 826         /* Bit 13:10 */
 827 #define PIXEL_FORMAT_RGB565                     0x1
 828 #define PIXEL_FORMAT_RGB666                     0x2
 829 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED      0x3
 830 #define PIXEL_FORMAT_RGB888                     0x4
 831         u32 videomode_color_format:4;
 832
 833         /* Bit 15:14 */
 834 #define ENABLE_ROTATION_0       0x0
 835 #define ENABLE_ROTATION_90      0x1
 836 #define ENABLE_ROTATION_180     0x2
 837 #define ENABLE_ROTATION_270     0x3
 838         u32 rotation:2;
 839         u32 bta_enabled:1;
 840         u32 rsvd2:15;
 841
 842         /* 2 byte Port Description */
 843 #define DUAL_LINK_NOT_SUPPORTED 0
 844 #define DUAL_LINK_FRONT_BACK    1
 845 #define DUAL_LINK_PIXEL_ALT     2
 846         u16 dual_link:2;
 847         u16 lane_cnt:2;
 848         u16 pixel_overlap:3;
 849         u16 rsvd3:9;
 850
 851         u16 rsvd4;
 852
 853         u8 rsvd5;
 854         u32 target_burst_mode_freq;
 855         u32 dsi_ddr_clk;
 856         u32 bridge_ref_clk;
 857
 858 #define  BYTE_CLK_SEL_20MHZ             0
 859 #define  BYTE_CLK_SEL_10MHZ             1
 860 #define  BYTE_CLK_SEL_5MHZ              2
 861         u8 byte_clk_sel:2;
 862
 863         u8 rsvd6:6;
 864
 865         /* DPHY Flags */
 866         u16 dphy_param_valid:1;
 867         u16 eot_pkt_disabled:1;
 868         u16 enable_clk_stop:1;
 869         u16 rsvd7:13;
 870
 871         u32 hs_tx_timeout;
 872         u32 lp_rx_timeout;
 873         u32 turn_around_timeout;
 874         u32 device_reset_timer;
 875         u32 master_init_timer;
 876         u32 dbi_bw_timer;
 877         u32 lp_byte_clk_val;
 878
 879         /*  4 byte Dphy Params */
 880         u32 prepare_cnt:6;
 881         u32 rsvd8:2;
 882         u32 clk_zero_cnt:8;
 883         u32 trail_cnt:5;
 884         u32 rsvd9:3;
 885         u32 exit_zero_cnt:6;
 886         u32 rsvd10:2;
 887
 888         u32 clk_lane_switch_cnt;
 889         u32 hl_switch_cnt;
 890
 891         u32 rsvd11[6];
 892
 893         /* timings based on dphy spec */
 894         u8 tclk_miss;
 895         u8 tclk_post;
 896         u8 rsvd12;
 897         u8 tclk_pre;
 898         u8 tclk_prepare;
 899         u8 tclk_settle;
 900         u8 tclk_term_enable;
 901         u8 tclk_trail;
 902         u16 tclk_prepare_clkzero;
 903         u8 rsvd13;
 904         u8 td_term_enable;
 905         u8 teot;
 906         u8 ths_exit;
 907         u8 ths_prepare;
 908         u16 ths_prepare_hszero;
 909         u8 rsvd14;
 910         u8 ths_settle;
 911         u8 ths_skip;
 912         u8 ths_trail;
 913         u8 tinit;
 914         u8 tlpx;
 915         u8 rsvd15[3];
 916
 917         /* GPIOs */
 918         u8 panel_enable;
 919         u8 bl_enable;
 920         u8 pwm_enable;
 921         u8 reset_r_n;
 922         u8 pwr_down_r;
 923         u8 stdby_r_n;
 924
 925 } __packed;
 926
 927 /* Block 52 contains MIPI configuration block
 928  * 6 * bdb_mipi_config, followed by 6 pps data
 929  * block below
 930  *
 931  * all delays has a unit of 100us
 932  */
 933 struct mipi_pps_data {
 934         u16 panel_on_delay;
 935         u16 bl_enable_delay;
 936         u16 bl_disable_delay;
 937         u16 panel_off_delay;
 938         u16 panel_power_cycle_delay;
 939 } __packed;
 940
 941 struct bdb_mipi_config {
 942         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 943         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 944 } __packed;
 945
 946 /* Block 53 contains MIPI sequences as needed by the panel
 947  * for enabling it. This block can be variable in size and
 948  * can be maximum of 6 blocks
 949  */
 950 struct bdb_mipi_sequence {
 951         u8 version;
 952         u8 data[0];
 953 } __packed;
 954
 955 /* MIPI Sequnece Block definitions */
 956 enum mipi_seq {
 957         MIPI_SEQ_END = 0,
 958         MIPI_SEQ_ASSERT_RESET,
 959         MIPI_SEQ_INIT_OTP,
 960         MIPI_SEQ_DISPLAY_ON,
 961         MIPI_SEQ_DISPLAY_OFF,
 962         MIPI_SEQ_DEASSERT_RESET,
 963         MIPI_SEQ_BACKLIGHT_ON,          /* sequence block v2+ */
 964         MIPI_SEQ_BACKLIGHT_OFF,         /* sequence block v2+ */
 965         MIPI_SEQ_TEAR_ON,               /* sequence block v2+ */
 966         MIPI_SEQ_TEAR_OFF,              /* sequence block v3+ */
 967         MIPI_SEQ_POWER_ON,              /* sequence block v3+ */
 968         MIPI_SEQ_POWER_OFF,             /* sequence block v3+ */
 969         MIPI_SEQ_MAX
 970 };
 971
 972 enum mipi_seq_element {
 973         MIPI_SEQ_ELEM_END = 0,
 974         MIPI_SEQ_ELEM_SEND_PKT,
 975         MIPI_SEQ_ELEM_DELAY,
 976         MIPI_SEQ_ELEM_GPIO,
 977         MIPI_SEQ_ELEM_I2C,              /* sequence block v2+ */
 978         MIPI_SEQ_ELEM_SPI,              /* sequence block v3+ */
 979         MIPI_SEQ_ELEM_PMIC,             /* sequence block v3+ */
 980         MIPI_SEQ_ELEM_MAX
 981 };
 982
 983 enum mipi_gpio_pin_index {
 984         MIPI_GPIO_UNDEFINED = 0,
 985         MIPI_GPIO_PANEL_ENABLE,
 986         MIPI_GPIO_BL_ENABLE,
 987         MIPI_GPIO_PWM_ENABLE,
 988         MIPI_GPIO_RESET_N,
 989         MIPI_GPIO_PWR_DOWN_R,
 990         MIPI_GPIO_STDBY_RST_N,
 991         MIPI_GPIO_MAX
 992 };
 993
 994 #endif /* _INTEL_BIOS_H_ */