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Merge drm-fixes into drm-next.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915_drv.h"
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
27
28 #include <linux/pm_runtime.h>
29
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
31
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
33
34 static const char * const forcewake_domain_names[] = {
35 "render",
36 "blitter",
37 "media",
38 };
39
40 const char *
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
42 {
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
44
45 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
46 return forcewake_domain_names[id];
47
48 WARN_ON(id);
49
50 return "unknown";
51 }
52
53 static inline void
54 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
55 {
56 WARN_ON(!i915_mmio_reg_valid(d->reg_set));
57 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
58 }
59
60 static inline void
61 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
62 {
63 mod_timer_pinned(&d->timer, jiffies + 1);
64 }
65
66 static inline void
67 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
68 {
69 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
70 FORCEWAKE_KERNEL) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
73 intel_uncore_forcewake_domain_to_str(d->id));
74 }
75
76 static inline void
77 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
78 {
79 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
80 }
81
82 static inline void
83 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
84 {
85 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
86 FORCEWAKE_KERNEL),
87 FORCEWAKE_ACK_TIMEOUT_MS))
88 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
89 intel_uncore_forcewake_domain_to_str(d->id));
90 }
91
92 static inline void
93 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
94 {
95 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
96 }
97
98 static inline void
99 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
100 {
101 /* something from same cacheline, but not from the set register */
102 if (i915_mmio_reg_valid(d->reg_post))
103 __raw_posting_read(d->i915, d->reg_post);
104 }
105
106 static void
107 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
108 {
109 struct intel_uncore_forcewake_domain *d;
110 enum forcewake_domain_id id;
111
112 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
113 fw_domain_wait_ack_clear(d);
114 fw_domain_get(d);
115 fw_domain_wait_ack(d);
116 }
117 }
118
119 static void
120 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
121 {
122 struct intel_uncore_forcewake_domain *d;
123 enum forcewake_domain_id id;
124
125 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
126 fw_domain_put(d);
127 fw_domain_posting_read(d);
128 }
129 }
130
131 static void
132 fw_domains_posting_read(struct drm_i915_private *dev_priv)
133 {
134 struct intel_uncore_forcewake_domain *d;
135 enum forcewake_domain_id id;
136
137 /* No need to do for all, just do for first found */
138 for_each_fw_domain(d, dev_priv, id) {
139 fw_domain_posting_read(d);
140 break;
141 }
142 }
143
144 static void
145 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
146 {
147 struct intel_uncore_forcewake_domain *d;
148 enum forcewake_domain_id id;
149
150 if (dev_priv->uncore.fw_domains == 0)
151 return;
152
153 for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
154 fw_domain_reset(d);
155
156 fw_domains_posting_read(dev_priv);
157 }
158
159 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
160 {
161 /* w/a for a sporadic read returning 0 by waiting for the GT
162 * thread to wake up.
163 */
164 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
165 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
166 DRM_ERROR("GT thread status wait timed out\n");
167 }
168
169 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
170 enum forcewake_domains fw_domains)
171 {
172 fw_domains_get(dev_priv, fw_domains);
173
174 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
175 __gen6_gt_wait_for_thread_c0(dev_priv);
176 }
177
178 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
179 {
180 u32 gtfifodbg;
181
182 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
183 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
184 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
185 }
186
187 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
188 enum forcewake_domains fw_domains)
189 {
190 fw_domains_put(dev_priv, fw_domains);
191 gen6_gt_check_fifodbg(dev_priv);
192 }
193
194 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
195 {
196 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
197
198 return count & GT_FIFO_FREE_ENTRIES_MASK;
199 }
200
201 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
202 {
203 int ret = 0;
204
205 /* On VLV, FIFO will be shared by both SW and HW.
206 * So, we need to read the FREE_ENTRIES everytime */
207 if (IS_VALLEYVIEW(dev_priv->dev))
208 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
209
210 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
211 int loop = 500;
212 u32 fifo = fifo_free_entries(dev_priv);
213
214 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
215 udelay(10);
216 fifo = fifo_free_entries(dev_priv);
217 }
218 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
219 ++ret;
220 dev_priv->uncore.fifo_count = fifo;
221 }
222 dev_priv->uncore.fifo_count--;
223
224 return ret;
225 }
226
227 static void intel_uncore_fw_release_timer(unsigned long arg)
228 {
229 struct intel_uncore_forcewake_domain *domain = (void *)arg;
230 unsigned long irqflags;
231
232 assert_rpm_device_not_suspended(domain->i915);
233
234 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
235 if (WARN_ON(domain->wake_count == 0))
236 domain->wake_count++;
237
238 if (--domain->wake_count == 0)
239 domain->i915->uncore.funcs.force_wake_put(domain->i915,
240 1 << domain->id);
241
242 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
243 }
244
245 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
246 {
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 unsigned long irqflags;
249 struct intel_uncore_forcewake_domain *domain;
250 int retry_count = 100;
251 enum forcewake_domain_id id;
252 enum forcewake_domains fw = 0, active_domains;
253
254 /* Hold uncore.lock across reset to prevent any register access
255 * with forcewake not set correctly. Wait until all pending
256 * timers are run before holding.
257 */
258 while (1) {
259 active_domains = 0;
260
261 for_each_fw_domain(domain, dev_priv, id) {
262 if (del_timer_sync(&domain->timer) == 0)
263 continue;
264
265 intel_uncore_fw_release_timer((unsigned long)domain);
266 }
267
268 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
269
270 for_each_fw_domain(domain, dev_priv, id) {
271 if (timer_pending(&domain->timer))
272 active_domains |= (1 << id);
273 }
274
275 if (active_domains == 0)
276 break;
277
278 if (--retry_count == 0) {
279 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
280 break;
281 }
282
283 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
284 cond_resched();
285 }
286
287 WARN_ON(active_domains);
288
289 for_each_fw_domain(domain, dev_priv, id)
290 if (domain->wake_count)
291 fw |= 1 << id;
292
293 if (fw)
294 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
295
296 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
297
298 if (restore) { /* If reset with a user forcewake, try to restore */
299 if (fw)
300 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
301
302 if (IS_GEN6(dev) || IS_GEN7(dev))
303 dev_priv->uncore.fifo_count =
304 fifo_free_entries(dev_priv);
305 }
306
307 if (!restore)
308 assert_forcewakes_inactive(dev_priv);
309
310 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
311 }
312
313 static void intel_uncore_ellc_detect(struct drm_device *dev)
314 {
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
318 INTEL_INFO(dev)->gen >= 9) &&
319 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
320 /* The docs do not explain exactly how the calculation can be
321 * made. It is somewhat guessable, but for now, it's always
322 * 128MB.
323 * NB: We can't write IDICR yet because we do not have gt funcs
324 * set up */
325 dev_priv->ellc_size = 128;
326 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
327 }
328 }
329
330 static bool
331 fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
332 {
333 u32 dbg;
334
335 dbg = __raw_i915_read32(dev_priv, FPGA_DBG);
336 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
337 return false;
338
339 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
340
341 return true;
342 }
343
344 static bool
345 vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
346 {
347 u32 cer;
348
349 cer = __raw_i915_read32(dev_priv, CLAIM_ER);
350 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
351 return false;
352
353 __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR);
354
355 return true;
356 }
357
358 static bool
359 check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
360 {
361 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv))
362 return fpga_check_for_unclaimed_mmio(dev_priv);
363
364 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
365 return vlv_check_for_unclaimed_mmio(dev_priv);
366
367 return false;
368 }
369
370 static void __intel_uncore_early_sanitize(struct drm_device *dev,
371 bool restore_forcewake)
372 {
373 struct drm_i915_private *dev_priv = dev->dev_private;
374
375 /* clear out unclaimed reg detection bit */
376 if (check_for_unclaimed_mmio(dev_priv))
377 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
378
379 /* clear out old GT FIFO errors */
380 if (IS_GEN6(dev) || IS_GEN7(dev))
381 __raw_i915_write32(dev_priv, GTFIFODBG,
382 __raw_i915_read32(dev_priv, GTFIFODBG));
383
384 /* WaDisableShadowRegForCpd:chv */
385 if (IS_CHERRYVIEW(dev)) {
386 __raw_i915_write32(dev_priv, GTFIFOCTL,
387 __raw_i915_read32(dev_priv, GTFIFOCTL) |
388 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
389 GT_FIFO_CTL_RC6_POLICY_STALL);
390 }
391
392 intel_uncore_forcewake_reset(dev, restore_forcewake);
393 }
394
395 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
396 {
397 __intel_uncore_early_sanitize(dev, restore_forcewake);
398 i915_check_and_clear_faults(dev);
399 }
400
401 void intel_uncore_sanitize(struct drm_device *dev)
402 {
403 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
404
405 /* BIOS often leaves RC6 enabled, but disable it for hw init */
406 intel_disable_gt_powersave(dev);
407 }
408
409 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
410 enum forcewake_domains fw_domains)
411 {
412 struct intel_uncore_forcewake_domain *domain;
413 enum forcewake_domain_id id;
414
415 if (!dev_priv->uncore.funcs.force_wake_get)
416 return;
417
418 fw_domains &= dev_priv->uncore.fw_domains;
419
420 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
421 if (domain->wake_count++)
422 fw_domains &= ~(1 << id);
423 }
424
425 if (fw_domains)
426 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
427 }
428
429 /**
430 * intel_uncore_forcewake_get - grab forcewake domain references
431 * @dev_priv: i915 device instance
432 * @fw_domains: forcewake domains to get reference on
433 *
434 * This function can be used get GT's forcewake domain references.
435 * Normal register access will handle the forcewake domains automatically.
436 * However if some sequence requires the GT to not power down a particular
437 * forcewake domains this function should be called at the beginning of the
438 * sequence. And subsequently the reference should be dropped by symmetric
439 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
440 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
441 */
442 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
443 enum forcewake_domains fw_domains)
444 {
445 unsigned long irqflags;
446
447 if (!dev_priv->uncore.funcs.force_wake_get)
448 return;
449
450 assert_rpm_wakelock_held(dev_priv);
451
452 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
453 __intel_uncore_forcewake_get(dev_priv, fw_domains);
454 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
455 }
456
457 /**
458 * intel_uncore_forcewake_get__locked - grab forcewake domain references
459 * @dev_priv: i915 device instance
460 * @fw_domains: forcewake domains to get reference on
461 *
462 * See intel_uncore_forcewake_get(). This variant places the onus
463 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
464 */
465 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
466 enum forcewake_domains fw_domains)
467 {
468 assert_spin_locked(&dev_priv->uncore.lock);
469
470 if (!dev_priv->uncore.funcs.force_wake_get)
471 return;
472
473 __intel_uncore_forcewake_get(dev_priv, fw_domains);
474 }
475
476 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
477 enum forcewake_domains fw_domains)
478 {
479 struct intel_uncore_forcewake_domain *domain;
480 enum forcewake_domain_id id;
481
482 if (!dev_priv->uncore.funcs.force_wake_put)
483 return;
484
485 fw_domains &= dev_priv->uncore.fw_domains;
486
487 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
488 if (WARN_ON(domain->wake_count == 0))
489 continue;
490
491 if (--domain->wake_count)
492 continue;
493
494 domain->wake_count++;
495 fw_domain_arm_timer(domain);
496 }
497 }
498
499 /**
500 * intel_uncore_forcewake_put - release a forcewake domain reference
501 * @dev_priv: i915 device instance
502 * @fw_domains: forcewake domains to put references
503 *
504 * This function drops the device-level forcewakes for specified
505 * domains obtained by intel_uncore_forcewake_get().
506 */
507 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
508 enum forcewake_domains fw_domains)
509 {
510 unsigned long irqflags;
511
512 if (!dev_priv->uncore.funcs.force_wake_put)
513 return;
514
515 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
516 __intel_uncore_forcewake_put(dev_priv, fw_domains);
517 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
518 }
519
520 /**
521 * intel_uncore_forcewake_put__locked - grab forcewake domain references
522 * @dev_priv: i915 device instance
523 * @fw_domains: forcewake domains to get reference on
524 *
525 * See intel_uncore_forcewake_put(). This variant places the onus
526 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
527 */
528 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
529 enum forcewake_domains fw_domains)
530 {
531 assert_spin_locked(&dev_priv->uncore.lock);
532
533 if (!dev_priv->uncore.funcs.force_wake_put)
534 return;
535
536 __intel_uncore_forcewake_put(dev_priv, fw_domains);
537 }
538
539 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
540 {
541 struct intel_uncore_forcewake_domain *domain;
542 enum forcewake_domain_id id;
543
544 if (!dev_priv->uncore.funcs.force_wake_get)
545 return;
546
547 for_each_fw_domain(domain, dev_priv, id)
548 WARN_ON(domain->wake_count);
549 }
550
551 /* We give fast paths for the really cool registers */
552 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
553
554 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
555
556 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
557 (REG_RANGE((reg), 0x2000, 0x4000) || \
558 REG_RANGE((reg), 0x5000, 0x8000) || \
559 REG_RANGE((reg), 0xB000, 0x12000) || \
560 REG_RANGE((reg), 0x2E000, 0x30000))
561
562 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
563 (REG_RANGE((reg), 0x12000, 0x14000) || \
564 REG_RANGE((reg), 0x22000, 0x24000) || \
565 REG_RANGE((reg), 0x30000, 0x40000))
566
567 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
568 (REG_RANGE((reg), 0x2000, 0x4000) || \
569 REG_RANGE((reg), 0x5200, 0x8000) || \
570 REG_RANGE((reg), 0x8300, 0x8500) || \
571 REG_RANGE((reg), 0xB000, 0xB480) || \
572 REG_RANGE((reg), 0xE000, 0xE800))
573
574 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
575 (REG_RANGE((reg), 0x8800, 0x8900) || \
576 REG_RANGE((reg), 0xD000, 0xD800) || \
577 REG_RANGE((reg), 0x12000, 0x14000) || \
578 REG_RANGE((reg), 0x1A000, 0x1C000) || \
579 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
580 REG_RANGE((reg), 0x30000, 0x38000))
581
582 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
583 (REG_RANGE((reg), 0x4000, 0x5000) || \
584 REG_RANGE((reg), 0x8000, 0x8300) || \
585 REG_RANGE((reg), 0x8500, 0x8600) || \
586 REG_RANGE((reg), 0x9000, 0xB000) || \
587 REG_RANGE((reg), 0xF000, 0x10000))
588
589 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
590 REG_RANGE((reg), 0xB00, 0x2000)
591
592 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
593 (REG_RANGE((reg), 0x2000, 0x2700) || \
594 REG_RANGE((reg), 0x3000, 0x4000) || \
595 REG_RANGE((reg), 0x5200, 0x8000) || \
596 REG_RANGE((reg), 0x8140, 0x8160) || \
597 REG_RANGE((reg), 0x8300, 0x8500) || \
598 REG_RANGE((reg), 0x8C00, 0x8D00) || \
599 REG_RANGE((reg), 0xB000, 0xB480) || \
600 REG_RANGE((reg), 0xE000, 0xE900) || \
601 REG_RANGE((reg), 0x24400, 0x24800))
602
603 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
604 (REG_RANGE((reg), 0x8130, 0x8140) || \
605 REG_RANGE((reg), 0x8800, 0x8A00) || \
606 REG_RANGE((reg), 0xD000, 0xD800) || \
607 REG_RANGE((reg), 0x12000, 0x14000) || \
608 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
609 REG_RANGE((reg), 0x30000, 0x40000))
610
611 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
612 REG_RANGE((reg), 0x9400, 0x9800)
613
614 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
615 ((reg) < 0x40000 && \
616 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
617 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
618 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
619 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
620
621 static void
622 ilk_dummy_write(struct drm_i915_private *dev_priv)
623 {
624 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
625 * the chip from rc6 before touching it for real. MI_MODE is masked,
626 * hence harmless to write 0 into. */
627 __raw_i915_write32(dev_priv, MI_MODE, 0);
628 }
629
630 static void
631 __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
632 const i915_reg_t reg,
633 const bool read,
634 const bool before)
635 {
636 /* XXX. We limit the auto arming traces for mmio
637 * debugs on these platforms. There are just too many
638 * revealed by these and CI/Bat suffers from the noise.
639 * Please fix and then re-enable the automatic traces.
640 */
641 if (i915.mmio_debug < 2 &&
642 (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
643 return;
644
645 if (WARN(check_for_unclaimed_mmio(dev_priv),
646 "Unclaimed register detected %s %s register 0x%x\n",
647 before ? "before" : "after",
648 read ? "reading" : "writing to",
649 i915_mmio_reg_offset(reg)))
650 i915.mmio_debug--; /* Only report the first N failures */
651 }
652
653 static inline void
654 unclaimed_reg_debug(struct drm_i915_private *dev_priv,
655 const i915_reg_t reg,
656 const bool read,
657 const bool before)
658 {
659 if (likely(!i915.mmio_debug))
660 return;
661
662 __unclaimed_reg_debug(dev_priv, reg, read, before);
663 }
664
665 #define GEN2_READ_HEADER(x) \
666 u##x val = 0; \
667 assert_rpm_wakelock_held(dev_priv);
668
669 #define GEN2_READ_FOOTER \
670 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
671 return val
672
673 #define __gen2_read(x) \
674 static u##x \
675 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
676 GEN2_READ_HEADER(x); \
677 val = __raw_i915_read##x(dev_priv, reg); \
678 GEN2_READ_FOOTER; \
679 }
680
681 #define __gen5_read(x) \
682 static u##x \
683 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
684 GEN2_READ_HEADER(x); \
685 ilk_dummy_write(dev_priv); \
686 val = __raw_i915_read##x(dev_priv, reg); \
687 GEN2_READ_FOOTER; \
688 }
689
690 __gen5_read(8)
691 __gen5_read(16)
692 __gen5_read(32)
693 __gen5_read(64)
694 __gen2_read(8)
695 __gen2_read(16)
696 __gen2_read(32)
697 __gen2_read(64)
698
699 #undef __gen5_read
700 #undef __gen2_read
701
702 #undef GEN2_READ_FOOTER
703 #undef GEN2_READ_HEADER
704
705 #define GEN6_READ_HEADER(x) \
706 u32 offset = i915_mmio_reg_offset(reg); \
707 unsigned long irqflags; \
708 u##x val = 0; \
709 assert_rpm_wakelock_held(dev_priv); \
710 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
711 unclaimed_reg_debug(dev_priv, reg, true, true)
712
713 #define GEN6_READ_FOOTER \
714 unclaimed_reg_debug(dev_priv, reg, true, false); \
715 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
716 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
717 return val
718
719 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
720 enum forcewake_domains fw_domains)
721 {
722 struct intel_uncore_forcewake_domain *domain;
723 enum forcewake_domain_id id;
724
725 if (WARN_ON(!fw_domains))
726 return;
727
728 /* Ideally GCC would be constant-fold and eliminate this loop */
729 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
730 if (domain->wake_count) {
731 fw_domains &= ~(1 << id);
732 continue;
733 }
734
735 domain->wake_count++;
736 fw_domain_arm_timer(domain);
737 }
738
739 if (fw_domains)
740 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
741 }
742
743 #define __gen6_read(x) \
744 static u##x \
745 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
746 GEN6_READ_HEADER(x); \
747 if (NEEDS_FORCE_WAKE(offset)) \
748 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
749 val = __raw_i915_read##x(dev_priv, reg); \
750 GEN6_READ_FOOTER; \
751 }
752
753 #define __vlv_read(x) \
754 static u##x \
755 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
756 enum forcewake_domains fw_engine = 0; \
757 GEN6_READ_HEADER(x); \
758 if (!NEEDS_FORCE_WAKE(offset)) \
759 fw_engine = 0; \
760 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
761 fw_engine = FORCEWAKE_RENDER; \
762 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
763 fw_engine = FORCEWAKE_MEDIA; \
764 if (fw_engine) \
765 __force_wake_get(dev_priv, fw_engine); \
766 val = __raw_i915_read##x(dev_priv, reg); \
767 GEN6_READ_FOOTER; \
768 }
769
770 #define __chv_read(x) \
771 static u##x \
772 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
773 enum forcewake_domains fw_engine = 0; \
774 GEN6_READ_HEADER(x); \
775 if (!NEEDS_FORCE_WAKE(offset)) \
776 fw_engine = 0; \
777 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
778 fw_engine = FORCEWAKE_RENDER; \
779 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
780 fw_engine = FORCEWAKE_MEDIA; \
781 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
782 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
783 if (fw_engine) \
784 __force_wake_get(dev_priv, fw_engine); \
785 val = __raw_i915_read##x(dev_priv, reg); \
786 GEN6_READ_FOOTER; \
787 }
788
789 #define SKL_NEEDS_FORCE_WAKE(reg) \
790 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
791
792 #define __gen9_read(x) \
793 static u##x \
794 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
795 enum forcewake_domains fw_engine; \
796 GEN6_READ_HEADER(x); \
797 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
798 fw_engine = 0; \
799 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
800 fw_engine = FORCEWAKE_RENDER; \
801 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
802 fw_engine = FORCEWAKE_MEDIA; \
803 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
804 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
805 else \
806 fw_engine = FORCEWAKE_BLITTER; \
807 if (fw_engine) \
808 __force_wake_get(dev_priv, fw_engine); \
809 val = __raw_i915_read##x(dev_priv, reg); \
810 GEN6_READ_FOOTER; \
811 }
812
813 __gen9_read(8)
814 __gen9_read(16)
815 __gen9_read(32)
816 __gen9_read(64)
817 __chv_read(8)
818 __chv_read(16)
819 __chv_read(32)
820 __chv_read(64)
821 __vlv_read(8)
822 __vlv_read(16)
823 __vlv_read(32)
824 __vlv_read(64)
825 __gen6_read(8)
826 __gen6_read(16)
827 __gen6_read(32)
828 __gen6_read(64)
829
830 #undef __gen9_read
831 #undef __chv_read
832 #undef __vlv_read
833 #undef __gen6_read
834 #undef GEN6_READ_FOOTER
835 #undef GEN6_READ_HEADER
836
837 #define VGPU_READ_HEADER(x) \
838 unsigned long irqflags; \
839 u##x val = 0; \
840 assert_rpm_device_not_suspended(dev_priv); \
841 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
842
843 #define VGPU_READ_FOOTER \
844 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
845 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
846 return val
847
848 #define __vgpu_read(x) \
849 static u##x \
850 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
851 VGPU_READ_HEADER(x); \
852 val = __raw_i915_read##x(dev_priv, reg); \
853 VGPU_READ_FOOTER; \
854 }
855
856 __vgpu_read(8)
857 __vgpu_read(16)
858 __vgpu_read(32)
859 __vgpu_read(64)
860
861 #undef __vgpu_read
862 #undef VGPU_READ_FOOTER
863 #undef VGPU_READ_HEADER
864
865 #define GEN2_WRITE_HEADER \
866 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
867 assert_rpm_wakelock_held(dev_priv); \
868
869 #define GEN2_WRITE_FOOTER
870
871 #define __gen2_write(x) \
872 static void \
873 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
874 GEN2_WRITE_HEADER; \
875 __raw_i915_write##x(dev_priv, reg, val); \
876 GEN2_WRITE_FOOTER; \
877 }
878
879 #define __gen5_write(x) \
880 static void \
881 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
882 GEN2_WRITE_HEADER; \
883 ilk_dummy_write(dev_priv); \
884 __raw_i915_write##x(dev_priv, reg, val); \
885 GEN2_WRITE_FOOTER; \
886 }
887
888 __gen5_write(8)
889 __gen5_write(16)
890 __gen5_write(32)
891 __gen5_write(64)
892 __gen2_write(8)
893 __gen2_write(16)
894 __gen2_write(32)
895 __gen2_write(64)
896
897 #undef __gen5_write
898 #undef __gen2_write
899
900 #undef GEN2_WRITE_FOOTER
901 #undef GEN2_WRITE_HEADER
902
903 #define GEN6_WRITE_HEADER \
904 u32 offset = i915_mmio_reg_offset(reg); \
905 unsigned long irqflags; \
906 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
907 assert_rpm_wakelock_held(dev_priv); \
908 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
909 unclaimed_reg_debug(dev_priv, reg, false, true)
910
911 #define GEN6_WRITE_FOOTER \
912 unclaimed_reg_debug(dev_priv, reg, false, false); \
913 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
914
915 #define __gen6_write(x) \
916 static void \
917 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
918 u32 __fifo_ret = 0; \
919 GEN6_WRITE_HEADER; \
920 if (NEEDS_FORCE_WAKE(offset)) { \
921 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
922 } \
923 __raw_i915_write##x(dev_priv, reg, val); \
924 if (unlikely(__fifo_ret)) { \
925 gen6_gt_check_fifodbg(dev_priv); \
926 } \
927 GEN6_WRITE_FOOTER; \
928 }
929
930 #define __hsw_write(x) \
931 static void \
932 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
933 u32 __fifo_ret = 0; \
934 GEN6_WRITE_HEADER; \
935 if (NEEDS_FORCE_WAKE(offset)) { \
936 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
937 } \
938 __raw_i915_write##x(dev_priv, reg, val); \
939 if (unlikely(__fifo_ret)) { \
940 gen6_gt_check_fifodbg(dev_priv); \
941 } \
942 GEN6_WRITE_FOOTER; \
943 }
944
945 static const i915_reg_t gen8_shadowed_regs[] = {
946 FORCEWAKE_MT,
947 GEN6_RPNSWREQ,
948 GEN6_RC_VIDEO_FREQ,
949 RING_TAIL(RENDER_RING_BASE),
950 RING_TAIL(GEN6_BSD_RING_BASE),
951 RING_TAIL(VEBOX_RING_BASE),
952 RING_TAIL(BLT_RING_BASE),
953 /* TODO: Other registers are not yet used */
954 };
955
956 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv,
957 i915_reg_t reg)
958 {
959 int i;
960 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
961 if (i915_mmio_reg_equal(reg, gen8_shadowed_regs[i]))
962 return true;
963
964 return false;
965 }
966
967 #define __gen8_write(x) \
968 static void \
969 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
970 GEN6_WRITE_HEADER; \
971 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
972 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
973 __raw_i915_write##x(dev_priv, reg, val); \
974 GEN6_WRITE_FOOTER; \
975 }
976
977 #define __chv_write(x) \
978 static void \
979 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
980 enum forcewake_domains fw_engine = 0; \
981 GEN6_WRITE_HEADER; \
982 if (!NEEDS_FORCE_WAKE(offset) || \
983 is_gen8_shadowed(dev_priv, reg)) \
984 fw_engine = 0; \
985 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
986 fw_engine = FORCEWAKE_RENDER; \
987 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
988 fw_engine = FORCEWAKE_MEDIA; \
989 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
990 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
991 if (fw_engine) \
992 __force_wake_get(dev_priv, fw_engine); \
993 __raw_i915_write##x(dev_priv, reg, val); \
994 GEN6_WRITE_FOOTER; \
995 }
996
997 static const i915_reg_t gen9_shadowed_regs[] = {
998 RING_TAIL(RENDER_RING_BASE),
999 RING_TAIL(GEN6_BSD_RING_BASE),
1000 RING_TAIL(VEBOX_RING_BASE),
1001 RING_TAIL(BLT_RING_BASE),
1002 FORCEWAKE_BLITTER_GEN9,
1003 FORCEWAKE_RENDER_GEN9,
1004 FORCEWAKE_MEDIA_GEN9,
1005 GEN6_RPNSWREQ,
1006 GEN6_RC_VIDEO_FREQ,
1007 /* TODO: Other registers are not yet used */
1008 };
1009
1010 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv,
1011 i915_reg_t reg)
1012 {
1013 int i;
1014 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1015 if (i915_mmio_reg_equal(reg, gen9_shadowed_regs[i]))
1016 return true;
1017
1018 return false;
1019 }
1020
1021 #define __gen9_write(x) \
1022 static void \
1023 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
1024 bool trace) { \
1025 enum forcewake_domains fw_engine; \
1026 GEN6_WRITE_HEADER; \
1027 if (!SKL_NEEDS_FORCE_WAKE(offset) || \
1028 is_gen9_shadowed(dev_priv, reg)) \
1029 fw_engine = 0; \
1030 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1031 fw_engine = FORCEWAKE_RENDER; \
1032 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1033 fw_engine = FORCEWAKE_MEDIA; \
1034 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1035 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1036 else \
1037 fw_engine = FORCEWAKE_BLITTER; \
1038 if (fw_engine) \
1039 __force_wake_get(dev_priv, fw_engine); \
1040 __raw_i915_write##x(dev_priv, reg, val); \
1041 GEN6_WRITE_FOOTER; \
1042 }
1043
1044 __gen9_write(8)
1045 __gen9_write(16)
1046 __gen9_write(32)
1047 __gen9_write(64)
1048 __chv_write(8)
1049 __chv_write(16)
1050 __chv_write(32)
1051 __chv_write(64)
1052 __gen8_write(8)
1053 __gen8_write(16)
1054 __gen8_write(32)
1055 __gen8_write(64)
1056 __hsw_write(8)
1057 __hsw_write(16)
1058 __hsw_write(32)
1059 __hsw_write(64)
1060 __gen6_write(8)
1061 __gen6_write(16)
1062 __gen6_write(32)
1063 __gen6_write(64)
1064
1065 #undef __gen9_write
1066 #undef __chv_write
1067 #undef __gen8_write
1068 #undef __hsw_write
1069 #undef __gen6_write
1070 #undef GEN6_WRITE_FOOTER
1071 #undef GEN6_WRITE_HEADER
1072
1073 #define VGPU_WRITE_HEADER \
1074 unsigned long irqflags; \
1075 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1076 assert_rpm_device_not_suspended(dev_priv); \
1077 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1078
1079 #define VGPU_WRITE_FOOTER \
1080 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1081
1082 #define __vgpu_write(x) \
1083 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1084 i915_reg_t reg, u##x val, bool trace) { \
1085 VGPU_WRITE_HEADER; \
1086 __raw_i915_write##x(dev_priv, reg, val); \
1087 VGPU_WRITE_FOOTER; \
1088 }
1089
1090 __vgpu_write(8)
1091 __vgpu_write(16)
1092 __vgpu_write(32)
1093 __vgpu_write(64)
1094
1095 #undef __vgpu_write
1096 #undef VGPU_WRITE_FOOTER
1097 #undef VGPU_WRITE_HEADER
1098
1099 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1100 do { \
1101 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1102 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1103 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1104 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1105 } while (0)
1106
1107 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1108 do { \
1109 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1110 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1111 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1112 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1113 } while (0)
1114
1115
1116 static void fw_domain_init(struct drm_i915_private *dev_priv,
1117 enum forcewake_domain_id domain_id,
1118 i915_reg_t reg_set,
1119 i915_reg_t reg_ack)
1120 {
1121 struct intel_uncore_forcewake_domain *d;
1122
1123 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1124 return;
1125
1126 d = &dev_priv->uncore.fw_domain[domain_id];
1127
1128 WARN_ON(d->wake_count);
1129
1130 d->wake_count = 0;
1131 d->reg_set = reg_set;
1132 d->reg_ack = reg_ack;
1133
1134 if (IS_GEN6(dev_priv)) {
1135 d->val_reset = 0;
1136 d->val_set = FORCEWAKE_KERNEL;
1137 d->val_clear = 0;
1138 } else {
1139 /* WaRsClearFWBitsAtReset:bdw,skl */
1140 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1141 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1142 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1143 }
1144
1145 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1146 d->reg_post = FORCEWAKE_ACK_VLV;
1147 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1148 d->reg_post = ECOBUS;
1149
1150 d->i915 = dev_priv;
1151 d->id = domain_id;
1152
1153 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1154
1155 dev_priv->uncore.fw_domains |= (1 << domain_id);
1156
1157 fw_domain_reset(d);
1158 }
1159
1160 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1161 {
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164 if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1165 return;
1166
1167 if (IS_GEN9(dev)) {
1168 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1169 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1170 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1171 FORCEWAKE_RENDER_GEN9,
1172 FORCEWAKE_ACK_RENDER_GEN9);
1173 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1174 FORCEWAKE_BLITTER_GEN9,
1175 FORCEWAKE_ACK_BLITTER_GEN9);
1176 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1177 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1178 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1179 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1180 if (!IS_CHERRYVIEW(dev))
1181 dev_priv->uncore.funcs.force_wake_put =
1182 fw_domains_put_with_fifo;
1183 else
1184 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1185 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1186 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1187 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1188 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1189 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1190 dev_priv->uncore.funcs.force_wake_get =
1191 fw_domains_get_with_thread_status;
1192 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1193 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1194 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1195 } else if (IS_IVYBRIDGE(dev)) {
1196 u32 ecobus;
1197
1198 /* IVB configs may use multi-threaded forcewake */
1199
1200 /* A small trick here - if the bios hasn't configured
1201 * MT forcewake, and if the device is in RC6, then
1202 * force_wake_mt_get will not wake the device and the
1203 * ECOBUS read will return zero. Which will be
1204 * (correctly) interpreted by the test below as MT
1205 * forcewake being disabled.
1206 */
1207 dev_priv->uncore.funcs.force_wake_get =
1208 fw_domains_get_with_thread_status;
1209 dev_priv->uncore.funcs.force_wake_put =
1210 fw_domains_put_with_fifo;
1211
1212 /* We need to init first for ECOBUS access and then
1213 * determine later if we want to reinit, in case of MT access is
1214 * not working. In this stage we don't know which flavour this
1215 * ivb is, so it is better to reset also the gen6 fw registers
1216 * before the ecobus check.
1217 */
1218
1219 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1220 __raw_posting_read(dev_priv, ECOBUS);
1221
1222 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1223 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1224
1225 mutex_lock(&dev->struct_mutex);
1226 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1227 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1228 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1229 mutex_unlock(&dev->struct_mutex);
1230
1231 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1232 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1233 DRM_INFO("when using vblank-synced partial screen updates.\n");
1234 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1235 FORCEWAKE, FORCEWAKE_ACK);
1236 }
1237 } else if (IS_GEN6(dev)) {
1238 dev_priv->uncore.funcs.force_wake_get =
1239 fw_domains_get_with_thread_status;
1240 dev_priv->uncore.funcs.force_wake_put =
1241 fw_domains_put_with_fifo;
1242 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1243 FORCEWAKE, FORCEWAKE_ACK);
1244 }
1245
1246 /* All future platforms are expected to require complex power gating */
1247 WARN_ON(dev_priv->uncore.fw_domains == 0);
1248 }
1249
1250 void intel_uncore_init(struct drm_device *dev)
1251 {
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254 i915_check_vgpu(dev);
1255
1256 intel_uncore_ellc_detect(dev);
1257 intel_uncore_fw_domains_init(dev);
1258 __intel_uncore_early_sanitize(dev, false);
1259
1260 dev_priv->uncore.unclaimed_mmio_check = 1;
1261
1262 switch (INTEL_INFO(dev)->gen) {
1263 default:
1264 case 9:
1265 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1266 ASSIGN_READ_MMIO_VFUNCS(gen9);
1267 break;
1268 case 8:
1269 if (IS_CHERRYVIEW(dev)) {
1270 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1271 ASSIGN_READ_MMIO_VFUNCS(chv);
1272
1273 } else {
1274 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1275 ASSIGN_READ_MMIO_VFUNCS(gen6);
1276 }
1277 break;
1278 case 7:
1279 case 6:
1280 if (IS_HASWELL(dev)) {
1281 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1282 } else {
1283 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1284 }
1285
1286 if (IS_VALLEYVIEW(dev)) {
1287 ASSIGN_READ_MMIO_VFUNCS(vlv);
1288 } else {
1289 ASSIGN_READ_MMIO_VFUNCS(gen6);
1290 }
1291 break;
1292 case 5:
1293 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1294 ASSIGN_READ_MMIO_VFUNCS(gen5);
1295 break;
1296 case 4:
1297 case 3:
1298 case 2:
1299 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1300 ASSIGN_READ_MMIO_VFUNCS(gen2);
1301 break;
1302 }
1303
1304 if (intel_vgpu_active(dev)) {
1305 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1306 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1307 }
1308
1309 i915_check_and_clear_faults(dev);
1310 }
1311 #undef ASSIGN_WRITE_MMIO_VFUNCS
1312 #undef ASSIGN_READ_MMIO_VFUNCS
1313
1314 void intel_uncore_fini(struct drm_device *dev)
1315 {
1316 /* Paranoia: make sure we have disabled everything before we exit. */
1317 intel_uncore_sanitize(dev);
1318 intel_uncore_forcewake_reset(dev, false);
1319 }
1320
1321 #define GEN_RANGE(l, h) GENMASK(h, l)
1322
1323 static const struct register_whitelist {
1324 i915_reg_t offset_ldw, offset_udw;
1325 uint32_t size;
1326 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1327 uint32_t gen_bitmask;
1328 } whitelist[] = {
1329 { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1330 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
1331 .size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
1332 };
1333
1334 int i915_reg_read_ioctl(struct drm_device *dev,
1335 void *data, struct drm_file *file)
1336 {
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 struct drm_i915_reg_read *reg = data;
1339 struct register_whitelist const *entry = whitelist;
1340 unsigned size;
1341 i915_reg_t offset_ldw, offset_udw;
1342 int i, ret = 0;
1343
1344 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1345 if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
1346 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1347 break;
1348 }
1349
1350 if (i == ARRAY_SIZE(whitelist))
1351 return -EINVAL;
1352
1353 /* We use the low bits to encode extra flags as the register should
1354 * be naturally aligned (and those that are not so aligned merely
1355 * limit the available flags for that register).
1356 */
1357 offset_ldw = entry->offset_ldw;
1358 offset_udw = entry->offset_udw;
1359 size = entry->size;
1360 size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
1361
1362 intel_runtime_pm_get(dev_priv);
1363
1364 switch (size) {
1365 case 8 | 1:
1366 reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
1367 break;
1368 case 8:
1369 reg->val = I915_READ64(offset_ldw);
1370 break;
1371 case 4:
1372 reg->val = I915_READ(offset_ldw);
1373 break;
1374 case 2:
1375 reg->val = I915_READ16(offset_ldw);
1376 break;
1377 case 1:
1378 reg->val = I915_READ8(offset_ldw);
1379 break;
1380 default:
1381 ret = -EINVAL;
1382 goto out;
1383 }
1384
1385 out:
1386 intel_runtime_pm_put(dev_priv);
1387 return ret;
1388 }
1389
1390 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1391 void *data, struct drm_file *file)
1392 {
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 struct drm_i915_reset_stats *args = data;
1395 struct i915_ctx_hang_stats *hs;
1396 struct intel_context *ctx;
1397 int ret;
1398
1399 if (args->flags || args->pad)
1400 return -EINVAL;
1401
1402 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1403 return -EPERM;
1404
1405 ret = mutex_lock_interruptible(&dev->struct_mutex);
1406 if (ret)
1407 return ret;
1408
1409 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1410 if (IS_ERR(ctx)) {
1411 mutex_unlock(&dev->struct_mutex);
1412 return PTR_ERR(ctx);
1413 }
1414 hs = &ctx->hang_stats;
1415
1416 if (capable(CAP_SYS_ADMIN))
1417 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1418 else
1419 args->reset_count = 0;
1420
1421 args->batch_active = hs->batch_active;
1422 args->batch_pending = hs->batch_pending;
1423
1424 mutex_unlock(&dev->struct_mutex);
1425
1426 return 0;
1427 }
1428
1429 static int i915_reset_complete(struct drm_device *dev)
1430 {
1431 u8 gdrst;
1432 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1433 return (gdrst & GRDOM_RESET_STATUS) == 0;
1434 }
1435
1436 static int i915_do_reset(struct drm_device *dev)
1437 {
1438 /* assert reset for at least 20 usec */
1439 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1440 udelay(20);
1441 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1442
1443 return wait_for(i915_reset_complete(dev), 500);
1444 }
1445
1446 static int g4x_reset_complete(struct drm_device *dev)
1447 {
1448 u8 gdrst;
1449 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1450 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1451 }
1452
1453 static int g33_do_reset(struct drm_device *dev)
1454 {
1455 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1456 return wait_for(g4x_reset_complete(dev), 500);
1457 }
1458
1459 static int g4x_do_reset(struct drm_device *dev)
1460 {
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 int ret;
1463
1464 pci_write_config_byte(dev->pdev, I915_GDRST,
1465 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1466 ret = wait_for(g4x_reset_complete(dev), 500);
1467 if (ret)
1468 return ret;
1469
1470 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1471 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1472 POSTING_READ(VDECCLK_GATE_D);
1473
1474 pci_write_config_byte(dev->pdev, I915_GDRST,
1475 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1476 ret = wait_for(g4x_reset_complete(dev), 500);
1477 if (ret)
1478 return ret;
1479
1480 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1481 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1482 POSTING_READ(VDECCLK_GATE_D);
1483
1484 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1485
1486 return 0;
1487 }
1488
1489 static int ironlake_do_reset(struct drm_device *dev)
1490 {
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 int ret;
1493
1494 I915_WRITE(ILK_GDSR,
1495 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1496 ret = wait_for((I915_READ(ILK_GDSR) &
1497 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1498 if (ret)
1499 return ret;
1500
1501 I915_WRITE(ILK_GDSR,
1502 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1503 ret = wait_for((I915_READ(ILK_GDSR) &
1504 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1505 if (ret)
1506 return ret;
1507
1508 I915_WRITE(ILK_GDSR, 0);
1509
1510 return 0;
1511 }
1512
1513 static int gen6_do_reset(struct drm_device *dev)
1514 {
1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 int ret;
1517
1518 /* Reset the chip */
1519
1520 /* GEN6_GDRST is not in the gt power well, no need to check
1521 * for fifo space for the write or forcewake the chip for
1522 * the read
1523 */
1524 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1525
1526 /* Spin waiting for the device to ack the reset request */
1527 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1528
1529 intel_uncore_forcewake_reset(dev, true);
1530
1531 return ret;
1532 }
1533
1534 static int wait_for_register(struct drm_i915_private *dev_priv,
1535 i915_reg_t reg,
1536 const u32 mask,
1537 const u32 value,
1538 const unsigned long timeout_ms)
1539 {
1540 return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1541 }
1542
1543 static int gen8_do_reset(struct drm_device *dev)
1544 {
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_engine_cs *engine;
1547 int i;
1548
1549 for_each_ring(engine, dev_priv, i) {
1550 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1551 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1552
1553 if (wait_for_register(dev_priv,
1554 RING_RESET_CTL(engine->mmio_base),
1555 RESET_CTL_READY_TO_RESET,
1556 RESET_CTL_READY_TO_RESET,
1557 700)) {
1558 DRM_ERROR("%s: reset request timeout\n", engine->name);
1559 goto not_ready;
1560 }
1561 }
1562
1563 return gen6_do_reset(dev);
1564
1565 not_ready:
1566 for_each_ring(engine, dev_priv, i)
1567 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1568 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1569
1570 return -EIO;
1571 }
1572
1573 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1574 {
1575 if (!i915.reset)
1576 return NULL;
1577
1578 if (INTEL_INFO(dev)->gen >= 8)
1579 return gen8_do_reset;
1580 else if (INTEL_INFO(dev)->gen >= 6)
1581 return gen6_do_reset;
1582 else if (IS_GEN5(dev))
1583 return ironlake_do_reset;
1584 else if (IS_G4X(dev))
1585 return g4x_do_reset;
1586 else if (IS_G33(dev))
1587 return g33_do_reset;
1588 else if (INTEL_INFO(dev)->gen >= 3)
1589 return i915_do_reset;
1590 else
1591 return NULL;
1592 }
1593
1594 int intel_gpu_reset(struct drm_device *dev)
1595 {
1596 struct drm_i915_private *dev_priv = to_i915(dev);
1597 int (*reset)(struct drm_device *);
1598 int ret;
1599
1600 reset = intel_get_gpu_reset(dev);
1601 if (reset == NULL)
1602 return -ENODEV;
1603
1604 /* If the power well sleeps during the reset, the reset
1605 * request may be dropped and never completes (causing -EIO).
1606 */
1607 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1608 ret = reset(dev);
1609 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1610
1611 return ret;
1612 }
1613
1614 bool intel_has_gpu_reset(struct drm_device *dev)
1615 {
1616 return intel_get_gpu_reset(dev) != NULL;
1617 }
1618
1619 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv)
1620 {
1621 return check_for_unclaimed_mmio(dev_priv);
1622 }
1623
1624 bool
1625 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
1626 {
1627 if (unlikely(i915.mmio_debug ||
1628 dev_priv->uncore.unclaimed_mmio_check <= 0))
1629 return false;
1630
1631 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
1632 DRM_DEBUG("Unclaimed register detected, "
1633 "enabling oneshot unclaimed register reporting. "
1634 "Please use i915.mmio_debug=N for more information.\n");
1635 i915.mmio_debug++;
1636 dev_priv->uncore.unclaimed_mmio_check--;
1637 return true;
1638 }
1639
1640 return false;
1641 }
Linux kernel - Deliverables
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