drivers/gpu/drm/rcar-du/rcar_du_group.c

   1 /*
   2  * rcar_du_group.c  --  R-Car Display Unit Channels Pair
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 /*
  15  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
  16  * unit, timings generator, ...) and device-global resources (start/stop
  17  * control, planes, ...) shared between the two CRTCs.
  18  *
  19  * The R8A7790 introduced a third CRTC with its own set of global resources.
  20  * This would be modeled as two separate DU device instances if it wasn't for
  21  * a handful or resources that are shared between the three CRTCs (mostly
  22  * related to input and output routing). For this reason the R8A7790 DU must be
  23  * modeled as a single device with three CRTCs, two sets of "semi-global"
  24  * resources, and a few device-global resources.
  25  *
  26  * The rcar_du_group object is a driver specific object, without any real
  27  * counterpart in the DU documentation, that models those semi-global resources.
  28  */
  29
  30 #include <linux/clk.h>
  31 #include <linux/io.h>
  32
  33 #include "rcar_du_drv.h"
  34 #include "rcar_du_group.h"
  35 #include "rcar_du_regs.h"
  36
  37 u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
  38 {
  39         return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
  40 }
  41
  42 void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
  43 {
  44         rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
  45 }
  46
  47 static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
  48 {
  49         u32 defr6 = DEFR6_CODE | DEFR6_ODPM12_DISP;
  50
  51         if (rgrp->num_crtcs > 1)
  52                 defr6 |= DEFR6_ODPM22_DISP;
  53
  54         rcar_du_group_write(rgrp, DEFR6, defr6);
  55 }
  56
  57 static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
  58 {
  59         struct rcar_du_device *rcdu = rgrp->dev;
  60         unsigned int possible_crtcs =
  61                 rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
  62         u32 defr8 = DEFR8_CODE;
  63
  64         if (rcdu->info->gen < 3) {
  65                 defr8 |= DEFR8_DEFE8;
  66
  67                 /* On Gen2 the DEFR8 register for the first group also controls
  68                  * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
  69                  * DU instances that support it.
  70                  */
  71                 if (rgrp->index == 0) {
  72                         if (possible_crtcs > 1)
  73                                 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
  74                         if (rgrp->dev->vspd1_sink == 2)
  75                                 defr8 |= DEFR8_VSCS;
  76                 }
  77         } else {
  78                 /* On Gen3 VSPD routing can't be configured, but DPAD routing
  79                  * needs to be set despite having a single option available.
  80                  */
  81                 u32 crtc = ffs(possible_crtcs) - 1;
  82
  83                 if (crtc / 2 == rgrp->index)
  84                         defr8 |= DEFR8_DRGBS_DU(crtc);
  85         }
  86
  87         rcar_du_group_write(rgrp, DEFR8, defr8);
  88 }
  89
  90 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
  91 {
  92         struct rcar_du_device *rcdu = rgrp->dev;
  93
  94         /* Enable extended features */
  95         rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
  96         if (rcdu->info->gen < 3) {
  97                 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
  98                 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
  99                 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
 100         }
 101         rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
 102
 103         rcar_du_group_setup_pins(rgrp);
 104
 105         if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
 106                 rcar_du_group_setup_defr8(rgrp);
 107
 108                 /* Configure input dot clock routing. We currently hardcode the
 109                  * configuration to routing DOTCLKINn to DUn.
 110                  */
 111                 rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE |
 112                                     DIDSR_LCDS_DCLKIN(2) |
 113                                     DIDSR_LCDS_DCLKIN(1) |
 114                                     DIDSR_LCDS_DCLKIN(0) |
 115                                     DIDSR_PDCS_CLK(2, 0) |
 116                                     DIDSR_PDCS_CLK(1, 0) |
 117                                     DIDSR_PDCS_CLK(0, 0));
 118         }
 119
 120         if (rcdu->info->gen >= 3)
 121                 rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
 122
 123         /* Use DS1PR and DS2PR to configure planes priorities and connects the
 124          * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
 125          */
 126         rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
 127
 128         /* Apply planes to CRTCs association. */
 129         mutex_lock(&rgrp->lock);
 130         rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
 131                             rgrp->dptsr_planes);
 132         mutex_unlock(&rgrp->lock);
 133 }
 134
 135 /*
 136  * rcar_du_group_get - Acquire a reference to the DU channels group
 137  *
 138  * Acquiring the first reference setups core registers. A reference must be held
 139  * before accessing any hardware registers.
 140  *
 141  * This function must be called with the DRM mode_config lock held.
 142  *
 143  * Return 0 in case of success or a negative error code otherwise.
 144  */
 145 int rcar_du_group_get(struct rcar_du_group *rgrp)
 146 {
 147         if (rgrp->use_count)
 148                 goto done;
 149
 150         rcar_du_group_setup(rgrp);
 151
 152 done:
 153         rgrp->use_count++;
 154         return 0;
 155 }
 156
 157 /*
 158  * rcar_du_group_put - Release a reference to the DU
 159  *
 160  * This function must be called with the DRM mode_config lock held.
 161  */
 162 void rcar_du_group_put(struct rcar_du_group *rgrp)
 163 {
 164         --rgrp->use_count;
 165 }
 166
 167 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 168 {
 169         rcar_du_group_write(rgrp, DSYSR,
 170                 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
 171                 (start ? DSYSR_DEN : DSYSR_DRES));
 172 }
 173
 174 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 175 {
 176         /* Many of the configuration bits are only updated when the display
 177          * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
 178          * of those bits could be pre-configured, but others (especially the
 179          * bits related to plane assignment to display timing controllers) need
 180          * to be modified at runtime.
 181          *
 182          * Restart the display controller if a start is requested. Sorry for the
 183          * flicker. It should be possible to move most of the "DRES-update" bits
 184          * setup to driver initialization time and minimize the number of cases
 185          * when the display controller will have to be restarted.
 186          */
 187         if (start) {
 188                 if (rgrp->used_crtcs++ != 0)
 189                         __rcar_du_group_start_stop(rgrp, false);
 190                 __rcar_du_group_start_stop(rgrp, true);
 191         } else {
 192                 if (--rgrp->used_crtcs == 0)
 193                         __rcar_du_group_start_stop(rgrp, false);
 194         }
 195 }
 196
 197 void rcar_du_group_restart(struct rcar_du_group *rgrp)
 198 {
 199         rgrp->need_restart = false;
 200
 201         __rcar_du_group_start_stop(rgrp, false);
 202         __rcar_du_group_start_stop(rgrp, true);
 203 }
 204
 205 int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
 206 {
 207         int ret;
 208
 209         if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
 210                 return 0;
 211
 212         /* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
 213          * configured in the DEFR8 register of the first group. As this function
 214          * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
 215          * the first group clock before accessing the register.
 216          */
 217         ret = clk_prepare_enable(rcdu->crtcs[0].clock);
 218         if (ret < 0)
 219                 return ret;
 220
 221         rcar_du_group_setup_defr8(&rcdu->groups[0]);
 222
 223         clk_disable_unprepare(rcdu->crtcs[0].clock);
 224
 225         return 0;
 226 }
 227
 228 int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
 229 {
 230         struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2];
 231         u32 dorcr = rcar_du_group_read(rgrp, DORCR);
 232
 233         dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
 234
 235         /* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
 236          * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
 237          * by default.
 238          */
 239         if (crtc0->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
 240                 dorcr |= DORCR_PG2D_DS1;
 241         else
 242                 dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
 243
 244         rcar_du_group_write(rgrp, DORCR, dorcr);
 245
 246         return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
 247 }