2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
34 #include "drm_atomic.h"
35 #include "drm_atomic_helper.h"
36 #include "drm_crtc_helper.h"
37 #include "linux/clk.h"
38 #include "drm_fb_cma_helper.h"
39 #include "linux/component.h"
40 #include "linux/of_device.h"
46 const struct vc4_crtc_data
*data
;
49 /* Which HVS channel we're using for our CRTC. */
52 struct drm_pending_vblank_event
*event
;
55 struct vc4_crtc_state
{
56 struct drm_crtc_state base
;
57 /* Dlist area for this CRTC configuration. */
58 struct drm_mm_node mm
;
61 static inline struct vc4_crtc
*
62 to_vc4_crtc(struct drm_crtc
*crtc
)
64 return (struct vc4_crtc
*)crtc
;
67 static inline struct vc4_crtc_state
*
68 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
70 return (struct vc4_crtc_state
*)crtc_state
;
73 struct vc4_crtc_data
{
74 /* Which channel of the HVS this pixelvalve sources from. */
77 enum vc4_encoder_type encoder0_type
;
78 enum vc4_encoder_type encoder1_type
;
81 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
82 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
84 #define CRTC_REG(reg) { reg, #reg }
90 CRTC_REG(PV_V_CONTROL
),
96 CRTC_REG(PV_VERTA_EVEN
),
97 CRTC_REG(PV_VERTB_EVEN
),
101 CRTC_REG(PV_HACT_ACT
),
104 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
108 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
109 DRM_INFO("0x%04x (%s): 0x%08x\n",
110 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
111 CRTC_READ(crtc_regs
[i
].reg
));
115 #ifdef CONFIG_DEBUG_FS
116 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
118 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
119 struct drm_device
*dev
= node
->minor
->dev
;
120 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
121 struct drm_crtc
*crtc
;
122 struct vc4_crtc
*vc4_crtc
;
126 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
133 vc4_crtc
= to_vc4_crtc(crtc
);
135 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
136 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
137 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
138 CRTC_READ(crtc_regs
[i
].reg
));
145 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
147 drm_crtc_cleanup(crtc
);
150 static u32
vc4_get_fifo_full_level(u32 format
)
152 static const u32 fifo_len_bytes
= 64;
153 static const u32 hvs_latency_pix
= 6;
156 case PV_CONTROL_FORMAT_DSIV_16
:
157 case PV_CONTROL_FORMAT_DSIC_16
:
158 return fifo_len_bytes
- 2 * hvs_latency_pix
;
159 case PV_CONTROL_FORMAT_DSIV_18
:
160 return fifo_len_bytes
- 14;
161 case PV_CONTROL_FORMAT_24
:
162 case PV_CONTROL_FORMAT_DSIV_24
:
164 return fifo_len_bytes
- 3 * hvs_latency_pix
;
169 * Returns the clock select bit for the connector attached to the
172 static int vc4_get_clock_select(struct drm_crtc
*crtc
)
174 struct drm_connector
*connector
;
176 drm_for_each_connector(connector
, crtc
->dev
) {
177 if (connector
->state
->crtc
== crtc
) {
178 struct drm_encoder
*encoder
= connector
->encoder
;
179 struct vc4_encoder
*vc4_encoder
=
180 to_vc4_encoder(encoder
);
182 return vc4_encoder
->clock_select
;
189 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
191 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
192 struct drm_crtc_state
*state
= crtc
->state
;
193 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
194 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
195 u32 vactive
= (mode
->vdisplay
>> (interlace
? 1 : 0));
196 u32 format
= PV_CONTROL_FORMAT_24
;
197 bool debug_dump_regs
= false;
198 int clock_select
= vc4_get_clock_select(crtc
);
200 if (debug_dump_regs
) {
201 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
202 vc4_crtc_dump_regs(vc4_crtc
);
205 /* Reset the PV fifo. */
206 CRTC_WRITE(PV_CONTROL
, 0);
207 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
208 CRTC_WRITE(PV_CONTROL
, 0);
211 VC4_SET_FIELD(mode
->htotal
- mode
->hsync_end
,
213 VC4_SET_FIELD(mode
->hsync_end
- mode
->hsync_start
,
216 VC4_SET_FIELD(mode
->hsync_start
- mode
->hdisplay
,
218 VC4_SET_FIELD(mode
->hdisplay
, PV_HORZB_HACTIVE
));
221 CRTC_WRITE(PV_VERTA_EVEN
,
222 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
- 1,
224 VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
226 CRTC_WRITE(PV_VERTB_EVEN
,
227 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
229 VC4_SET_FIELD(vactive
, PV_VERTB_VACTIVE
));
232 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
);
234 CRTC_WRITE(PV_V_CONTROL
,
235 PV_VCONTROL_CONTINUOUS
|
236 (interlace
? PV_VCONTROL_INTERLACE
: 0));
238 CRTC_WRITE(PV_CONTROL
,
239 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
240 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
241 PV_CONTROL_FIFO_LEVEL
) |
242 PV_CONTROL_CLR_AT_START
|
243 PV_CONTROL_TRIGGER_UNDERFLOW
|
244 PV_CONTROL_WAIT_HSTART
|
245 VC4_SET_FIELD(clock_select
, PV_CONTROL_CLK_SELECT
) |
246 PV_CONTROL_FIFO_CLR
|
249 if (debug_dump_regs
) {
250 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
251 vc4_crtc_dump_regs(vc4_crtc
);
255 static void require_hvs_enabled(struct drm_device
*dev
)
257 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
259 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
260 SCALER_DISPCTRL_ENABLE
);
263 static void vc4_crtc_disable(struct drm_crtc
*crtc
)
265 struct drm_device
*dev
= crtc
->dev
;
266 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
267 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
268 u32 chan
= vc4_crtc
->channel
;
270 require_hvs_enabled(dev
);
272 CRTC_WRITE(PV_V_CONTROL
,
273 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
274 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
275 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
277 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
278 SCALER_DISPCTRLX_ENABLE
) {
279 HVS_WRITE(SCALER_DISPCTRLX(chan
),
280 SCALER_DISPCTRLX_RESET
);
282 /* While the docs say that reset is self-clearing, it
283 * seems it doesn't actually.
285 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
288 /* Once we leave, the scaler should be disabled and its fifo empty. */
290 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
292 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
293 SCALER_DISPSTATX_MODE
) !=
294 SCALER_DISPSTATX_MODE_DISABLED
);
296 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
297 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
298 SCALER_DISPSTATX_EMPTY
);
301 static void vc4_crtc_enable(struct drm_crtc
*crtc
)
303 struct drm_device
*dev
= crtc
->dev
;
304 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
305 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
306 struct drm_crtc_state
*state
= crtc
->state
;
307 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
309 require_hvs_enabled(dev
);
311 /* Turn on the scaler, which will wait for vstart to start
314 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
315 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
316 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
317 SCALER_DISPCTRLX_ENABLE
);
319 /* Turn on the pixel valve, which will emit the vstart signal. */
320 CRTC_WRITE(PV_V_CONTROL
,
321 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
324 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
325 struct drm_crtc_state
*state
)
327 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
328 struct drm_device
*dev
= crtc
->dev
;
329 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
330 struct drm_plane
*plane
;
335 /* The pixelvalve can only feed one encoder (and encoders are
336 * 1:1 with connectors.)
338 if (hweight32(state
->connector_mask
) > 1)
341 drm_atomic_crtc_state_for_each_plane(plane
, state
) {
342 struct drm_plane_state
*plane_state
=
343 state
->state
->plane_states
[drm_plane_index(plane
)];
345 /* plane might not have changed, in which case take
349 plane_state
= plane
->state
;
351 dlist_count
+= vc4_plane_dlist_size(plane_state
);
354 dlist_count
++; /* Account for SCALER_CTL0_END. */
356 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
357 ret
= drm_mm_insert_node(&vc4
->hvs
->dlist_mm
, &vc4_state
->mm
,
359 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
366 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
367 struct drm_crtc_state
*old_state
)
369 struct drm_device
*dev
= crtc
->dev
;
370 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
371 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
372 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
373 struct drm_plane
*plane
;
374 bool debug_dump_regs
= false;
375 u32 __iomem
*dlist_start
= vc4
->hvs
->dlist
+ vc4_state
->mm
.start
;
376 u32 __iomem
*dlist_next
= dlist_start
;
378 if (debug_dump_regs
) {
379 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
380 vc4_hvs_dump_state(dev
);
383 /* Copy all the active planes' dlist contents to the hardware dlist. */
384 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
385 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
388 writel(SCALER_CTL0_END
, dlist_next
);
391 WARN_ON_ONCE(dlist_next
- dlist_start
!= vc4_state
->mm
.size
);
393 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
394 vc4_state
->mm
.start
);
396 if (debug_dump_regs
) {
397 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
398 vc4_hvs_dump_state(dev
);
401 if (crtc
->state
->event
) {
404 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
406 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
408 spin_lock_irqsave(&dev
->event_lock
, flags
);
409 vc4_crtc
->event
= crtc
->state
->event
;
410 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
411 crtc
->state
->event
= NULL
;
415 int vc4_enable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
417 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
418 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
420 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
425 void vc4_disable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
427 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
428 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
430 CRTC_WRITE(PV_INTEN
, 0);
433 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
435 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
436 struct drm_device
*dev
= crtc
->dev
;
439 spin_lock_irqsave(&dev
->event_lock
, flags
);
440 if (vc4_crtc
->event
) {
441 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
442 vc4_crtc
->event
= NULL
;
444 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
447 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
449 struct vc4_crtc
*vc4_crtc
= data
;
450 u32 stat
= CRTC_READ(PV_INTSTAT
);
451 irqreturn_t ret
= IRQ_NONE
;
453 if (stat
& PV_INT_VFP_START
) {
454 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
455 drm_crtc_handle_vblank(&vc4_crtc
->base
);
456 vc4_crtc_handle_page_flip(vc4_crtc
);
463 struct vc4_async_flip_state
{
464 struct drm_crtc
*crtc
;
465 struct drm_framebuffer
*fb
;
466 struct drm_pending_vblank_event
*event
;
468 struct vc4_seqno_cb cb
;
471 /* Called when the V3D execution for the BO being flipped to is done, so that
472 * we can actually update the plane's address to point to it.
475 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
477 struct vc4_async_flip_state
*flip_state
=
478 container_of(cb
, struct vc4_async_flip_state
, cb
);
479 struct drm_crtc
*crtc
= flip_state
->crtc
;
480 struct drm_device
*dev
= crtc
->dev
;
481 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
482 struct drm_plane
*plane
= crtc
->primary
;
484 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
485 if (flip_state
->event
) {
488 spin_lock_irqsave(&dev
->event_lock
, flags
);
489 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
490 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
493 drm_framebuffer_unreference(flip_state
->fb
);
496 up(&vc4
->async_modeset
);
499 /* Implements async (non-vblank-synced) page flips.
501 * The page flip ioctl needs to return immediately, so we grab the
502 * modeset semaphore on the pipe, and queue the address update for
503 * when V3D is done with the BO being flipped to.
505 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
506 struct drm_framebuffer
*fb
,
507 struct drm_pending_vblank_event
*event
,
510 struct drm_device
*dev
= crtc
->dev
;
511 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
512 struct drm_plane
*plane
= crtc
->primary
;
514 struct vc4_async_flip_state
*flip_state
;
515 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
516 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
518 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
522 drm_framebuffer_reference(fb
);
524 flip_state
->crtc
= crtc
;
525 flip_state
->event
= event
;
527 /* Make sure all other async modesetes have landed. */
528 ret
= down_interruptible(&vc4
->async_modeset
);
534 /* Immediately update the plane's legacy fb pointer, so that later
535 * modeset prep sees the state that will be present when the semaphore
538 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
541 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
542 vc4_async_page_flip_complete
);
544 /* Driver takes ownership of state on successful async commit. */
548 static int vc4_page_flip(struct drm_crtc
*crtc
,
549 struct drm_framebuffer
*fb
,
550 struct drm_pending_vblank_event
*event
,
553 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
554 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
556 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
);
559 static struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
)
561 struct vc4_crtc_state
*vc4_state
;
563 vc4_state
= kzalloc(sizeof(*vc4_state
), GFP_KERNEL
);
567 __drm_atomic_helper_crtc_duplicate_state(crtc
, &vc4_state
->base
);
568 return &vc4_state
->base
;
571 static void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
572 struct drm_crtc_state
*state
)
574 struct vc4_dev
*vc4
= to_vc4_dev(crtc
->dev
);
575 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
577 if (vc4_state
->mm
.allocated
) {
580 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
581 drm_mm_remove_node(&vc4_state
->mm
);
582 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
586 __drm_atomic_helper_crtc_destroy_state(crtc
, state
);
589 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
590 .set_config
= drm_atomic_helper_set_config
,
591 .destroy
= vc4_crtc_destroy
,
592 .page_flip
= vc4_page_flip
,
593 .set_property
= NULL
,
594 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
595 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
596 .reset
= drm_atomic_helper_crtc_reset
,
597 .atomic_duplicate_state
= vc4_crtc_duplicate_state
,
598 .atomic_destroy_state
= vc4_crtc_destroy_state
,
601 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
602 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
603 .disable
= vc4_crtc_disable
,
604 .enable
= vc4_crtc_enable
,
605 .atomic_check
= vc4_crtc_atomic_check
,
606 .atomic_flush
= vc4_crtc_atomic_flush
,
609 static const struct vc4_crtc_data pv0_data
= {
611 .encoder0_type
= VC4_ENCODER_TYPE_DSI0
,
612 .encoder1_type
= VC4_ENCODER_TYPE_DPI
,
615 static const struct vc4_crtc_data pv1_data
= {
617 .encoder0_type
= VC4_ENCODER_TYPE_DSI1
,
618 .encoder1_type
= VC4_ENCODER_TYPE_SMI
,
621 static const struct vc4_crtc_data pv2_data
= {
623 .encoder0_type
= VC4_ENCODER_TYPE_VEC
,
624 .encoder1_type
= VC4_ENCODER_TYPE_HDMI
,
627 static const struct of_device_id vc4_crtc_dt_match
[] = {
628 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
629 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
630 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
634 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
635 struct drm_crtc
*crtc
)
637 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
638 struct drm_encoder
*encoder
;
640 drm_for_each_encoder(encoder
, drm
) {
641 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
643 if (vc4_encoder
->type
== vc4_crtc
->data
->encoder0_type
) {
644 vc4_encoder
->clock_select
= 0;
645 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
646 } else if (vc4_encoder
->type
== vc4_crtc
->data
->encoder1_type
) {
647 vc4_encoder
->clock_select
= 1;
648 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
653 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
655 struct platform_device
*pdev
= to_platform_device(dev
);
656 struct drm_device
*drm
= dev_get_drvdata(master
);
657 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
658 struct vc4_crtc
*vc4_crtc
;
659 struct drm_crtc
*crtc
;
660 struct drm_plane
*primary_plane
, *cursor_plane
, *destroy_plane
, *temp
;
661 const struct of_device_id
*match
;
664 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
667 crtc
= &vc4_crtc
->base
;
669 match
= of_match_device(vc4_crtc_dt_match
, dev
);
672 vc4_crtc
->data
= match
->data
;
674 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
675 if (IS_ERR(vc4_crtc
->regs
))
676 return PTR_ERR(vc4_crtc
->regs
);
678 /* For now, we create just the primary and the legacy cursor
679 * planes. We should be able to stack more planes on easily,
680 * but to do that we would need to compute the bandwidth
681 * requirement of the plane configuration, and reject ones
682 * that will take too much.
684 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
685 if (IS_ERR(primary_plane
)) {
686 dev_err(dev
, "failed to construct primary plane\n");
687 ret
= PTR_ERR(primary_plane
);
691 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, NULL
,
692 &vc4_crtc_funcs
, NULL
);
693 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
694 primary_plane
->crtc
= crtc
;
695 vc4
->crtc
[drm_crtc_index(crtc
)] = vc4_crtc
;
696 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
698 /* Set up some arbitrary number of planes. We're not limited
699 * by a set number of physical registers, just the space in
700 * the HVS (16k) and how small an plane can be (28 bytes).
701 * However, each plane we set up takes up some memory, and
702 * increases the cost of looping over planes, which atomic
703 * modesetting does quite a bit. As a result, we pick a
704 * modest number of planes to expose, that should hopefully
705 * still cover any sane usecase.
707 for (i
= 0; i
< 8; i
++) {
708 struct drm_plane
*plane
=
709 vc4_plane_init(drm
, DRM_PLANE_TYPE_OVERLAY
);
714 plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
717 /* Set up the legacy cursor after overlay initialization,
718 * since we overlay planes on the CRTC in the order they were
721 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
722 if (!IS_ERR(cursor_plane
)) {
723 cursor_plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
724 cursor_plane
->crtc
= crtc
;
725 crtc
->cursor
= cursor_plane
;
728 CRTC_WRITE(PV_INTEN
, 0);
729 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
730 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
731 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
733 goto err_destroy_planes
;
735 vc4_set_crtc_possible_masks(drm
, crtc
);
737 platform_set_drvdata(pdev
, vc4_crtc
);
742 list_for_each_entry_safe(destroy_plane
, temp
,
743 &drm
->mode_config
.plane_list
, head
) {
744 if (destroy_plane
->possible_crtcs
== 1 << drm_crtc_index(crtc
))
745 destroy_plane
->funcs
->destroy(destroy_plane
);
751 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
754 struct platform_device
*pdev
= to_platform_device(dev
);
755 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
757 vc4_crtc_destroy(&vc4_crtc
->base
);
759 CRTC_WRITE(PV_INTEN
, 0);
761 platform_set_drvdata(pdev
, NULL
);
764 static const struct component_ops vc4_crtc_ops
= {
765 .bind
= vc4_crtc_bind
,
766 .unbind
= vc4_crtc_unbind
,
769 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
771 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
774 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
776 component_del(&pdev
->dev
, &vc4_crtc_ops
);
780 struct platform_driver vc4_crtc_driver
= {
781 .probe
= vc4_crtc_dev_probe
,
782 .remove
= vc4_crtc_dev_remove
,
785 .of_match_table
= vc4_crtc_dt_match
,