drivers/infiniband/hw/hns/hns_roce_cmd.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_CMD_H
  34 #define _HNS_ROCE_CMD_H
  35
  36 #define HNS_ROCE_MAILBOX_SIZE           4096
  37
  38 enum {
  39         /* TPT commands */
  40         HNS_ROCE_CMD_SW2HW_MPT          = 0xd,
  41         HNS_ROCE_CMD_HW2SW_MPT          = 0xf,
  42
  43         /* CQ commands */
  44         HNS_ROCE_CMD_SW2HW_CQ           = 0x16,
  45         HNS_ROCE_CMD_HW2SW_CQ           = 0x17,
  46
  47         /* QP/EE commands */
  48         HNS_ROCE_CMD_RST2INIT_QP        = 0x19,
  49         HNS_ROCE_CMD_INIT2RTR_QP        = 0x1a,
  50         HNS_ROCE_CMD_RTR2RTS_QP         = 0x1b,
  51         HNS_ROCE_CMD_RTS2RTS_QP         = 0x1c,
  52         HNS_ROCE_CMD_2ERR_QP            = 0x1e,
  53         HNS_ROCE_CMD_RTS2SQD_QP         = 0x1f,
  54         HNS_ROCE_CMD_SQD2SQD_QP         = 0x38,
  55         HNS_ROCE_CMD_SQD2RTS_QP         = 0x20,
  56         HNS_ROCE_CMD_2RST_QP            = 0x21,
  57         HNS_ROCE_CMD_QUERY_QP           = 0x22,
  58 };
  59
  60 enum {
  61         HNS_ROCE_CMD_TIME_CLASS_A       = 10000,
  62         HNS_ROCE_CMD_TIME_CLASS_B       = 10000,
  63         HNS_ROCE_CMD_TIME_CLASS_C       = 10000,
  64 };
  65
  66 struct hns_roce_cmd_mailbox {
  67         void                   *buf;
  68         dma_addr_t              dma;
  69 };
  70
  71 int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
  72                       unsigned long in_modifier, u8 op_modifier, u16 op,
  73                       unsigned long timeout);
  74
  75 struct hns_roce_cmd_mailbox
  76         *hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
  77 void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
  78                                struct hns_roce_cmd_mailbox *mailbox);
  79
  80 #endif /* _HNS_ROCE_CMD_H */