2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 enum ena_admin_aq_opcode
{
36 ENA_ADMIN_CREATE_SQ
= 1,
38 ENA_ADMIN_DESTROY_SQ
= 2,
40 ENA_ADMIN_CREATE_CQ
= 3,
42 ENA_ADMIN_DESTROY_CQ
= 4,
44 ENA_ADMIN_GET_FEATURE
= 8,
46 ENA_ADMIN_SET_FEATURE
= 9,
48 ENA_ADMIN_GET_STATS
= 11,
51 enum ena_admin_aq_completion_status
{
52 ENA_ADMIN_SUCCESS
= 0,
54 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE
= 1,
56 ENA_ADMIN_BAD_OPCODE
= 2,
58 ENA_ADMIN_UNSUPPORTED_OPCODE
= 3,
60 ENA_ADMIN_MALFORMED_REQUEST
= 4,
62 /* Additional status is provided in ACQ entry extended_status */
63 ENA_ADMIN_ILLEGAL_PARAMETER
= 5,
65 ENA_ADMIN_UNKNOWN_ERROR
= 6,
68 enum ena_admin_aq_feature_id
{
69 ENA_ADMIN_DEVICE_ATTRIBUTES
= 1,
71 ENA_ADMIN_MAX_QUEUES_NUM
= 2,
73 ENA_ADMIN_RSS_HASH_FUNCTION
= 10,
75 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG
= 11,
77 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG
= 12,
81 ENA_ADMIN_RSS_HASH_INPUT
= 18,
83 ENA_ADMIN_INTERRUPT_MODERATION
= 20,
85 ENA_ADMIN_AENQ_CONFIG
= 26,
87 ENA_ADMIN_LINK_CONFIG
= 27,
89 ENA_ADMIN_HOST_ATTR_CONFIG
= 28,
91 ENA_ADMIN_FEATURES_OPCODE_NUM
= 32,
94 enum ena_admin_placement_policy_type
{
95 /* descriptors and headers are in host memory */
96 ENA_ADMIN_PLACEMENT_POLICY_HOST
= 1,
98 /* descriptors and headers are in device memory (a.k.a Low Latency
101 ENA_ADMIN_PLACEMENT_POLICY_DEV
= 3,
104 enum ena_admin_link_types
{
105 ENA_ADMIN_LINK_SPEED_1G
= 0x1,
107 ENA_ADMIN_LINK_SPEED_2_HALF_G
= 0x2,
109 ENA_ADMIN_LINK_SPEED_5G
= 0x4,
111 ENA_ADMIN_LINK_SPEED_10G
= 0x8,
113 ENA_ADMIN_LINK_SPEED_25G
= 0x10,
115 ENA_ADMIN_LINK_SPEED_40G
= 0x20,
117 ENA_ADMIN_LINK_SPEED_50G
= 0x40,
119 ENA_ADMIN_LINK_SPEED_100G
= 0x80,
121 ENA_ADMIN_LINK_SPEED_200G
= 0x100,
123 ENA_ADMIN_LINK_SPEED_400G
= 0x200,
126 enum ena_admin_completion_policy_type
{
127 /* completion queue entry for each sq descriptor */
128 ENA_ADMIN_COMPLETION_POLICY_DESC
= 0,
130 /* completion queue entry upon request in sq descriptor */
131 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND
= 1,
133 /* current queue head pointer is updated in OS memory upon sq
136 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND
= 2,
138 /* current queue head pointer is updated in OS memory for each sq
141 ENA_ADMIN_COMPLETION_POLICY_HEAD
= 3,
144 /* basic stats return ena_admin_basic_stats while extanded stats return a
145 * buffer (string format) with additional statistics per queue and per
148 enum ena_admin_get_stats_type
{
149 ENA_ADMIN_GET_STATS_TYPE_BASIC
= 0,
151 ENA_ADMIN_GET_STATS_TYPE_EXTENDED
= 1,
154 enum ena_admin_get_stats_scope
{
155 ENA_ADMIN_SPECIFIC_QUEUE
= 0,
157 ENA_ADMIN_ETH_TRAFFIC
= 1,
160 struct ena_admin_aq_common_desc
{
166 /* as appears in ena_admin_aq_opcode */
170 * 1 : ctrl_data - control buffer address valid
171 * 2 : ctrl_data_indirect - control buffer address
172 * points to list of pages with addresses of control
179 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
180 * page list chunk. Used also at the end of indirect mode page list chunks,
183 struct ena_admin_ctrl_buff_info
{
186 struct ena_common_mem_addr address
;
189 struct ena_admin_sq
{
193 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
200 struct ena_admin_aq_entry
{
201 struct ena_admin_aq_common_desc aq_common_descriptor
;
204 u32 inline_data_w1
[3];
206 struct ena_admin_ctrl_buff_info control_buffer
;
209 u32 inline_data_w4
[12];
212 struct ena_admin_acq_common_desc
{
213 /* command identifier to associate it with the aq descriptor
228 /* serves as a hint what AQ entries can be revoked */
232 struct ena_admin_acq_entry
{
233 struct ena_admin_acq_common_desc acq_common_descriptor
;
235 u32 response_specific_data
[14];
238 struct ena_admin_aq_create_sq_cmd
{
239 struct ena_admin_aq_common_desc aq_common_descriptor
;
241 /* 4:0 : reserved0_w1
242 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
248 /* 3:0 : placement_policy - Describing where the SQ
249 * descriptor ring and the SQ packet headers reside:
250 * 0x1 - descriptors and headers are in OS memory,
251 * 0x3 - descriptors and headers in device memory
252 * (a.k.a Low Latency Queue)
253 * 6:4 : completion_policy - Describing what policy
254 * to use for generation completion entry (cqe) in
255 * the CQ associated with this SQ: 0x0 - cqe for each
256 * sq descriptor, 0x1 - cqe upon request in sq
257 * descriptor, 0x2 - current queue head pointer is
258 * updated in OS memory upon sq descriptor request
259 * 0x3 - current queue head pointer is updated in OS
260 * memory for each sq descriptor
265 /* 0 : is_physically_contiguous - Described if the
266 * queue ring memory is allocated in physical
267 * contiguous pages or split.
268 * 7:1 : reserved17_w1
272 /* associated completion queue id. This CQ must be created prior to
277 /* submission queue depth in entries */
280 /* SQ physical base address in OS memory. This field should not be
281 * used for Low Latency queues. Has to be page aligned.
283 struct ena_common_mem_addr sq_ba
;
285 /* specifies queue head writeback location in OS memory. Valid if
286 * completion_policy is set to completion_policy_head_on_demand or
287 * completion_policy_head. Has to be cache aligned
289 struct ena_common_mem_addr sq_head_writeback
;
296 enum ena_admin_sq_direction
{
297 ENA_ADMIN_SQ_DIRECTION_TX
= 1,
299 ENA_ADMIN_SQ_DIRECTION_RX
= 2,
302 struct ena_admin_acq_create_sq_resp_desc
{
303 struct ena_admin_acq_common_desc acq_common_desc
;
309 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
310 u32 sq_doorbell_offset
;
312 /* low latency queue ring base address as an offset to PCIe MMIO
315 u32 llq_descriptors_offset
;
317 /* low latency queue headers' memory as an offset to PCIe MMIO
320 u32 llq_headers_offset
;
323 struct ena_admin_aq_destroy_sq_cmd
{
324 struct ena_admin_aq_common_desc aq_common_descriptor
;
326 struct ena_admin_sq sq
;
329 struct ena_admin_acq_destroy_sq_resp_desc
{
330 struct ena_admin_acq_common_desc acq_common_desc
;
333 struct ena_admin_aq_create_cq_cmd
{
334 struct ena_admin_aq_common_desc aq_common_descriptor
;
337 * 5 : interrupt_mode_enabled - if set, cq operates
338 * in interrupt mode, otherwise - polling
343 /* 4:0 : cq_entry_size_words - size of CQ entry in
344 * 32-bit words, valid values: 4, 8.
349 /* completion queue depth in # of entries. must be power of 2 */
352 /* msix vector assigned to this cq */
355 /* cq physical base address in OS memory. CQ must be physically
358 struct ena_common_mem_addr cq_ba
;
361 struct ena_admin_acq_create_cq_resp_desc
{
362 struct ena_admin_acq_common_desc acq_common_desc
;
366 /* actual cq depth in number of entries */
369 u32 numa_node_register_offset
;
371 u32 cq_head_db_register_offset
;
373 u32 cq_interrupt_unmask_register_offset
;
376 struct ena_admin_aq_destroy_cq_cmd
{
377 struct ena_admin_aq_common_desc aq_common_descriptor
;
384 struct ena_admin_acq_destroy_cq_resp_desc
{
385 struct ena_admin_acq_common_desc acq_common_desc
;
388 /* ENA AQ Get Statistics command. Extended statistics are placed in control
389 * buffer pointed by AQ entry
391 struct ena_admin_aq_get_stats_cmd
{
392 struct ena_admin_aq_common_desc aq_common_descriptor
;
395 /* command specific inline data */
396 u32 inline_data_w1
[3];
398 struct ena_admin_ctrl_buff_info control_buffer
;
401 /* stats type as defined in enum ena_admin_get_stats_type */
404 /* stats scope defined in enum ena_admin_get_stats_scope */
409 /* queue id. used when scope is specific_queue */
412 /* device id, value 0xFFFF means mine. only privileged device can get
413 * stats of other device
418 /* Basic Statistics Command. */
419 struct ena_admin_basic_stats
{
441 struct ena_admin_acq_get_stats_resp
{
442 struct ena_admin_acq_common_desc acq_common_desc
;
444 struct ena_admin_basic_stats basic_stats
;
447 struct ena_admin_get_set_feature_common_desc
{
448 /* 1:0 : select - 0x1 - current value; 0x3 - default
454 /* as appears in ena_admin_aq_feature_id */
460 struct ena_admin_device_attr_feature_desc
{
465 /* bitmap of ena_admin_aq_feature_id */
466 u32 supported_features
;
470 /* Indicates how many bits are used physical address access. */
473 /* Indicates how many bits are used virtual address access. */
476 /* unicast MAC address (in Network byte order) */
484 struct ena_admin_queue_feature_desc
{
500 /* Maximum Descriptors number, including meta descriptor, allowed for
503 u16 max_packet_tx_descs
;
505 /* Maximum Descriptors number allowed for a single Rx packet */
506 u16 max_packet_rx_descs
;
509 struct ena_admin_set_feature_mtu_desc
{
514 struct ena_admin_set_feature_host_attr_desc
{
515 /* host OS info base address in OS memory. host info is 4KB of
516 * physically contiguous
518 struct ena_common_mem_addr os_info_ba
;
520 /* host debug area base address in OS memory. debug area must be
521 * physically contiguous
523 struct ena_common_mem_addr debug_ba
;
525 /* debug area size */
529 struct ena_admin_feature_intr_moder_desc
{
530 /* interrupt delay granularity in usec */
531 u16 intr_delay_resolution
;
536 struct ena_admin_get_feature_link_desc
{
537 /* Link speed in Mb */
540 /* bit field of enum ena_admin_link types */
544 * 1 : duplex - Full Duplex
550 struct ena_admin_feature_aenq_desc
{
551 /* bitmask for AENQ groups the device can report */
552 u32 supported_groups
;
554 /* bitmask for AENQ groups to report */
558 struct ena_admin_feature_offload_desc
{
559 /* 0 : TX_L3_csum_ipv4
560 * 1 : TX_L4_ipv4_csum_part - The checksum field
561 * should be initialized with pseudo header checksum
562 * 2 : TX_L4_ipv4_csum_full
563 * 3 : TX_L4_ipv6_csum_part - The checksum field
564 * should be initialized with pseudo header checksum
565 * 4 : TX_L4_ipv6_csum_full
572 /* Receive side supported stateless offload
573 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
574 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
575 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
576 * 3 : RX_hash - Hash calculation
583 enum ena_admin_hash_functions
{
584 ENA_ADMIN_TOEPLITZ
= 1,
589 struct ena_admin_feature_rss_flow_hash_control
{
597 struct ena_admin_feature_rss_flow_hash_function
{
598 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
601 /* 7:0 : selected_func - bitmask of
602 * ena_admin_hash_functions
610 /* RSS flow hash protocols */
611 enum ena_admin_flow_hash_proto
{
612 ENA_ADMIN_RSS_TCP4
= 0,
614 ENA_ADMIN_RSS_UDP4
= 1,
616 ENA_ADMIN_RSS_TCP6
= 2,
618 ENA_ADMIN_RSS_UDP6
= 3,
620 ENA_ADMIN_RSS_IP4
= 4,
622 ENA_ADMIN_RSS_IP6
= 5,
624 ENA_ADMIN_RSS_IP4_FRAG
= 6,
626 ENA_ADMIN_RSS_NOT_IP
= 7,
628 ENA_ADMIN_RSS_PROTO_NUM
= 16,
631 /* RSS flow hash fields */
632 enum ena_admin_flow_hash_fields
{
633 /* Ethernet Dest Addr */
634 ENA_ADMIN_RSS_L2_DA
= 0,
636 /* Ethernet Src Addr */
637 ENA_ADMIN_RSS_L2_SA
= 1,
639 /* ipv4/6 Dest Addr */
640 ENA_ADMIN_RSS_L3_DA
= 2,
642 /* ipv4/6 Src Addr */
643 ENA_ADMIN_RSS_L3_SA
= 5,
645 /* tcp/udp Dest Port */
646 ENA_ADMIN_RSS_L4_DP
= 6,
648 /* tcp/udp Src Port */
649 ENA_ADMIN_RSS_L4_SP
= 7,
652 struct ena_admin_proto_input
{
653 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
659 struct ena_admin_feature_rss_hash_control
{
660 struct ena_admin_proto_input supported_fields
[ENA_ADMIN_RSS_PROTO_NUM
];
662 struct ena_admin_proto_input selected_fields
[ENA_ADMIN_RSS_PROTO_NUM
];
664 struct ena_admin_proto_input reserved2
[ENA_ADMIN_RSS_PROTO_NUM
];
666 struct ena_admin_proto_input reserved3
[ENA_ADMIN_RSS_PROTO_NUM
];
669 struct ena_admin_feature_rss_flow_hash_input
{
670 /* supported hash input sorting
671 * 1 : L3_sort - support swap L3 addresses if DA is
673 * 2 : L4_sort - support swap L4 ports if DP smaller
676 u16 supported_input_sort
;
678 /* enabled hash input sorting
679 * 1 : enable_L3_sort - enable swap L3 addresses if
681 * 2 : enable_L4_sort - enable swap L4 ports if DP
684 u16 enabled_input_sort
;
687 enum ena_admin_os_type
{
688 ENA_ADMIN_OS_LINUX
= 1,
690 ENA_ADMIN_OS_WIN
= 2,
692 ENA_ADMIN_OS_DPDK
= 3,
694 ENA_ADMIN_OS_FREEBSD
= 4,
696 ENA_ADMIN_OS_IPXE
= 5,
699 struct ena_admin_host_info
{
700 /* defined in enum ena_admin_os_type */
703 /* os distribution string format */
706 /* OS distribution numeric format */
709 /* kernel version string format */
710 u8 kernel_ver_str
[32];
712 /* Kernel version numeric format */
721 /* features bitmap */
722 u32 supported_network_features
[4];
725 struct ena_admin_rss_ind_table_entry
{
731 struct ena_admin_feature_rss_ind_table
{
732 /* min supported table size (2^min_size) */
735 /* max supported table size (2^max_size) */
738 /* table size (2^size) */
743 /* index of the inline entry. 0xFFFFFFFF means invalid */
746 /* used for updating single entry, ignored when setting the entire
747 * table through the control buffer.
749 struct ena_admin_rss_ind_table_entry inline_entry
;
752 struct ena_admin_get_feat_cmd
{
753 struct ena_admin_aq_common_desc aq_common_descriptor
;
755 struct ena_admin_ctrl_buff_info control_buffer
;
757 struct ena_admin_get_set_feature_common_desc feat_common
;
762 struct ena_admin_get_feat_resp
{
763 struct ena_admin_acq_common_desc acq_common_desc
;
768 struct ena_admin_device_attr_feature_desc dev_attr
;
770 struct ena_admin_queue_feature_desc max_queue
;
772 struct ena_admin_feature_aenq_desc aenq
;
774 struct ena_admin_get_feature_link_desc link
;
776 struct ena_admin_feature_offload_desc offload
;
778 struct ena_admin_feature_rss_flow_hash_function flow_hash_func
;
780 struct ena_admin_feature_rss_flow_hash_input flow_hash_input
;
782 struct ena_admin_feature_rss_ind_table ind_table
;
784 struct ena_admin_feature_intr_moder_desc intr_moderation
;
788 struct ena_admin_set_feat_cmd
{
789 struct ena_admin_aq_common_desc aq_common_descriptor
;
791 struct ena_admin_ctrl_buff_info control_buffer
;
793 struct ena_admin_get_set_feature_common_desc feat_common
;
799 struct ena_admin_set_feature_mtu_desc mtu
;
801 /* host attributes */
802 struct ena_admin_set_feature_host_attr_desc host_attr
;
804 /* AENQ configuration */
805 struct ena_admin_feature_aenq_desc aenq
;
807 /* rss flow hash function */
808 struct ena_admin_feature_rss_flow_hash_function flow_hash_func
;
810 /* rss flow hash input */
811 struct ena_admin_feature_rss_flow_hash_input flow_hash_input
;
813 /* rss indirection table */
814 struct ena_admin_feature_rss_ind_table ind_table
;
818 struct ena_admin_set_feat_resp
{
819 struct ena_admin_acq_common_desc acq_common_desc
;
826 struct ena_admin_aenq_common_desc
{
841 /* asynchronous event notification groups */
842 enum ena_admin_aenq_group
{
843 ENA_ADMIN_LINK_CHANGE
= 0,
845 ENA_ADMIN_FATAL_ERROR
= 1,
847 ENA_ADMIN_WARNING
= 2,
849 ENA_ADMIN_NOTIFICATION
= 3,
851 ENA_ADMIN_KEEP_ALIVE
= 4,
853 ENA_ADMIN_AENQ_GROUPS_NUM
= 5,
856 enum ena_admin_aenq_notification_syndrom
{
857 ENA_ADMIN_SUSPEND
= 0,
859 ENA_ADMIN_RESUME
= 1,
862 struct ena_admin_aenq_entry
{
863 struct ena_admin_aenq_common_desc aenq_common_desc
;
865 /* command specific inline data */
866 u32 inline_data_w4
[12];
869 struct ena_admin_aenq_link_change_desc
{
870 struct ena_admin_aenq_common_desc aenq_common_desc
;
872 /* 0 : link_status */
876 struct ena_admin_ena_mmio_req_read_less_resp
{
881 /* value is valid when poll is cleared */
886 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
887 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
888 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
889 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
890 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
891 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
894 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
895 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
897 /* acq_common_desc */
898 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
899 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
901 /* aq_create_sq_cmd */
902 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
903 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
904 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
905 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
906 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
907 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
909 /* aq_create_cq_cmd */
910 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
911 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
912 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
914 /* get_set_feature_common_desc */
915 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
917 /* get_feature_link_desc */
918 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
919 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
920 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
922 /* feature_offload_desc */
923 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
924 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
925 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
926 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
927 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
928 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
929 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
930 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
931 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
932 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
933 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
934 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
935 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
936 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
937 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
938 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
939 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
940 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
941 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
942 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
943 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
944 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
946 /* feature_rss_flow_hash_function */
947 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
948 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
950 /* feature_rss_flow_hash_input */
951 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
952 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
953 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
954 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
955 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
956 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
957 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
958 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
961 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
962 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
963 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
964 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
965 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
967 /* aenq_common_desc */
968 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
970 /* aenq_link_change_desc */
971 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
973 #endif /*_ENA_ADMIN_H_ */