opcodes/ChangeLog

   1 2020-06-26  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c: (print_insn): Avoid straight assignment to
   4         priv.orig_sizeflag when processing -M sub-options.
   5
   6 2020-06-25  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c: Adjust description of J macro.
   9         (dis386, x86_64_table, mod_table): Replace J.
  10         (putop): Remove handling of J.
  11
  12 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  15
  16 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-dis.c: Adjust description of "LQ" macro.
  19         (dis386_twobyte): Use LQ for sysret.
  20         (putop): Adjust handling of LQ.
  21
  22 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  23
  24         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  25         * riscv-dis.c: Include elfxx-riscv.h.
  26
  27 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  28
  29         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  30
  31 2020-06-17  Lili Cui  <lili.cui@intel.com>
  32
  33         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  34
  35 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         PR gas/26115
  38         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  39         * i386-opc.tbl: Likewise.
  40         * i386-tbl.h: Regenerated.
  41
  42 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  43
  44         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  45
  46 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  47
  48         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  49         (SR_CORE): Likewise.
  50         (SR_FEAT): Likewise.
  51         (SR_RNG): Likewise.
  52         (SR_V8_1): Likewise.
  53         (SR_V8_2): Likewise.
  54         (SR_V8_3): Likewise.
  55         (SR_V8_4): Likewise.
  56         (SR_PAN): Likewise.
  57         (SR_RAS): Likewise.
  58         (SR_SSBS): Likewise.
  59         (SR_SVE): Likewise.
  60         (SR_ID_PFR2): Likewise.
  61         (SR_PROFILE): Likewise.
  62         (SR_MEMTAG): Likewise.
  63         (SR_SCXTNUM): Likewise.
  64         (aarch64_sys_regs): Refactor to store feature information in the table.
  65         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  66         that now describe their own features.
  67         (aarch64_pstatefield_supported_p): Likewise.
  68
  69 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         * i386-dis.c (prefix_table): Fix a typo in comments.
  72
  73 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-dis.c (rex_ignored): Delete.
  76         (ckprefix): Drop rex_ignored initialization.
  77         (get_valid_dis386): Drop setting of rex_ignored.
  78         (print_insn): Drop checking of rex_ignored. Don't record data
  79         size prefix as used with VEX-and-alike encodings.
  80
  81 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  82
  83         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
  84         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
  85         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
  86         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
  87         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
  88         VEX_0F12, and VEX_0F16.
  89         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
  90         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
  91         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
  92         from movlps and movhlps. New MOD_0F12_PREFIX_2,
  93         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
  94         MOD_VEX_0F16_PREFIX_2 entries.
  95
  96 2020-06-09  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
  99         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 100         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 101         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 102         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 103         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 104         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 105         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 106         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 107         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 108         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 109         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 110         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 111         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 112         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 113         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 114         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 115         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 116         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 117         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 118         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 119         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 120         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 121         EVEX_W_0FC6_P_2): Delete.
 122         (print_insn): Add EVEX.W vs embedded prefix consistency check
 123         to prefix validation.
 124         * i386-dis-evex.h (evex_table): Don't further descend for
 125         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 126         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 127         and 0F2B.
 128         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 129         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 130         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 131         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 132         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 133         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 134         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 135         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 136         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 137         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 138         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 139         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 140         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 141         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 142         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 143         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 144         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 145         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 146         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 147         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 148         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 149         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 150         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 151         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 152         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 153         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 154         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 155
 156 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 159         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 160         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 161         vmovmskpX.
 162         (print_insn): Drop pointless check against bad_opcode. Split
 163         prefix validation into legacy and VEX-and-alike parts.
 164         (putop): Re-work 'X' macro handling.
 165
 166 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (MOD_0F51): Rename to ...
 169         (MOD_0F50): ... this.
 170
 171 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 172
 173         * arm-dis.c (arm_opcodes): Add dfb.
 174         (thumb32_opcodes): Add dfb.
 175
 176 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 179
 180 2020-06-06  Alan Modra  <amodra@gmail.com>
 181
 182         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 183
 184 2020-06-05  Alan Modra  <amodra@gmail.com>
 185
 186         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 187         size is large enough.
 188
 189 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 190
 191         * disassemble.c (disassemble_init_for_target): Set endian_code for
 192         bpf targets.
 193         * bpf-desc.c: Regenerate.
 194         * bpf-opc.c: Likewise.
 195         * bpf-dis.c: Likewise.
 196
 197 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 198
 199         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 200         (cgen_put_insn_value): Likewise.
 201         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 202         * cgen-dis.in (print_insn): Likewise.
 203         * cgen-ibld.in (insert_1): Likewise.
 204         (insert_1): Likewise.
 205         (insert_insn_normal): Likewise.
 206         (extract_1): Likewise.
 207         * bpf-dis.c: Regenerate.
 208         * bpf-ibld.c: Likewise.
 209         * bpf-ibld.c: Likewise.
 210         * cgen-dis.in: Likewise.
 211         * cgen-ibld.in: Likewise.
 212         * cgen-opc.c: Likewise.
 213         * epiphany-dis.c: Likewise.
 214         * epiphany-ibld.c: Likewise.
 215         * fr30-dis.c: Likewise.
 216         * fr30-ibld.c: Likewise.
 217         * frv-dis.c: Likewise.
 218         * frv-ibld.c: Likewise.
 219         * ip2k-dis.c: Likewise.
 220         * ip2k-ibld.c: Likewise.
 221         * iq2000-dis.c: Likewise.
 222         * iq2000-ibld.c: Likewise.
 223         * lm32-dis.c: Likewise.
 224         * lm32-ibld.c: Likewise.
 225         * m32c-dis.c: Likewise.
 226         * m32c-ibld.c: Likewise.
 227         * m32r-dis.c: Likewise.
 228         * m32r-ibld.c: Likewise.
 229         * mep-dis.c: Likewise.
 230         * mep-ibld.c: Likewise.
 231         * mt-dis.c: Likewise.
 232         * mt-ibld.c: Likewise.
 233         * or1k-dis.c: Likewise.
 234         * or1k-ibld.c: Likewise.
 235         * xc16x-dis.c: Likewise.
 236         * xc16x-ibld.c: Likewise.
 237         * xstormy16-dis.c: Likewise.
 238         * xstormy16-ibld.c: Likewise.
 239
 240 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 241
 242         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 243         (print_insn_): Handle instruction endian.
 244         * bpf-dis.c: Regenerate.
 245         * bpf-desc.c: Regenerate.
 246         * epiphany-dis.c: Likewise.
 247         * epiphany-desc.c: Likewise.
 248         * fr30-dis.c: Likewise.
 249         * fr30-desc.c: Likewise.
 250         * frv-dis.c: Likewise.
 251         * frv-desc.c: Likewise.
 252         * ip2k-dis.c: Likewise.
 253         * ip2k-desc.c: Likewise.
 254         * iq2000-dis.c: Likewise.
 255         * iq2000-desc.c: Likewise.
 256         * lm32-dis.c: Likewise.
 257         * lm32-desc.c: Likewise.
 258         * m32c-dis.c: Likewise.
 259         * m32c-desc.c: Likewise.
 260         * m32r-dis.c: Likewise.
 261         * m32r-desc.c: Likewise.
 262         * mep-dis.c: Likewise.
 263         * mep-desc.c: Likewise.
 264         * mt-dis.c: Likewise.
 265         * mt-desc.c: Likewise.
 266         * or1k-dis.c: Likewise.
 267         * or1k-desc.c: Likewise.
 268         * xc16x-dis.c: Likewise.
 269         * xc16x-desc.c: Likewise.
 270         * xstormy16-dis.c: Likewise.
 271         * xstormy16-desc.c: Likewise.
 272
 273 2020-06-03  Nick Clifton  <nickc@redhat.com>
 274
 275         * po/sr.po: Updated Serbian translation.
 276
 277 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 278
 279         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 280         (riscv_get_priv_spec_class): Likewise.
 281
 282 2020-06-01  Alan Modra  <amodra@gmail.com>
 283
 284         * bpf-desc.c: Regenerate.
 285
 286 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 287             David Faust <david.faust@oracle.com>
 288
 289         * bpf-desc.c: Regenerate.
 290         * bpf-opc.h: Likewise.
 291         * bpf-opc.c: Likewise.
 292         * bpf-dis.c: Likewise.
 293
 294 2020-05-28  Alan Modra  <amodra@gmail.com>
 295
 296         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 297         values.
 298
 299 2020-05-28  Alan Modra  <amodra@gmail.com>
 300
 301         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 302         immediates.
 303         (print_insn_ns32k): Revert last change.
 304
 305 2020-05-28  Nick Clifton  <nickc@redhat.com>
 306
 307         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 308         static.
 309
 310 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 311
 312         Fix extraction of signed constants in nios2 disassembler (again).
 313
 314         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 315         extractions of signed fields.
 316
 317 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 318
 319         * s390-opc.txt: Relocate vector load/store instructions with
 320         additional alignment parameter and change architecture level
 321         constraint from z14 to z13.
 322
 323 2020-05-21  Alan Modra  <amodra@gmail.com>
 324
 325         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 326         * sparc-dis.c: Likewise.
 327         * tic4x-dis.c: Likewise.
 328         * xtensa-dis.c: Likewise.
 329         * bpf-desc.c: Regenerate.
 330         * epiphany-desc.c: Regenerate.
 331         * fr30-desc.c: Regenerate.
 332         * frv-desc.c: Regenerate.
 333         * ip2k-desc.c: Regenerate.
 334         * iq2000-desc.c: Regenerate.
 335         * lm32-desc.c: Regenerate.
 336         * m32c-desc.c: Regenerate.
 337         * m32r-desc.c: Regenerate.
 338         * mep-asm.c: Regenerate.
 339         * mep-desc.c: Regenerate.
 340         * mt-desc.c: Regenerate.
 341         * or1k-desc.c: Regenerate.
 342         * xc16x-desc.c: Regenerate.
 343         * xstormy16-desc.c: Regenerate.
 344
 345 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 346
 347         * riscv-opc.c (riscv_ext_version_table): The table used to store
 348         all information about the supported spec and the corresponding ISA
 349         versions.  Currently, only Zicsr is supported to verify the
 350         correctness of Z sub extension settings.  Others will be supported
 351         in the future patches.
 352         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 353         classes and the corresponding strings.
 354         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 355         spec class by giving a ISA spec string.
 356         * riscv-opc.c (struct priv_spec_t): New structure.
 357         (struct priv_spec_t priv_specs): List for all supported privilege spec
 358         classes and the corresponding strings.
 359         (riscv_get_priv_spec_class): New function.  Get the corresponding
 360         privilege spec class by giving a spec string.
 361         (riscv_get_priv_spec_name): New function.  Get the corresponding
 362         privilege spec string by giving a CSR version class.
 363         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 364         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 365         according to the chosen version.  Build a hash table riscv_csr_hash to
 366         store the valid CSR for the chosen pirv verison.  Dump the direct
 367         CSR address rather than it's name if it is invalid.
 368         (parse_riscv_dis_option_without_args): New function.  Parse the options
 369         without arguments.
 370         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 371         parse the options without arguments first, and then handle the options
 372         with arguments.  Add the new option -Mpriv-spec, which has argument.
 373         * riscv-dis.c (print_riscv_disassembler_options): Add description
 374         about the new OBJDUMP option.
 375
 376 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 377
 378         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 379         WC values on POWER10 sync, dcbf  and wait instructions.
 380         (insert_pl, extract_pl): New functions.
 381         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 382         (LS3): New , 3-bit L for sync.
 383         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 384         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 385         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 386         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 387         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 388         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 389         <wait>: Enable PL operand on POWER10.
 390         <dcbf>: Enable L3OPT operand on POWER10.
 391         <sync>: Enable SC2 operand on POWER10.
 392
 393 2020-05-19  Stafford Horne  <shorne@gmail.com>
 394
 395         PR 25184
 396         * or1k-asm.c: Regenerate.
 397         * or1k-desc.c: Regenerate.
 398         * or1k-desc.h: Regenerate.
 399         * or1k-dis.c: Regenerate.
 400         * or1k-ibld.c: Regenerate.
 401         * or1k-opc.c: Regenerate.
 402         * or1k-opc.h: Regenerate.
 403         * or1k-opinst.c: Regenerate.
 404
 405 2020-05-11  Alan Modra  <amodra@gmail.com>
 406
 407         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 408         xsmaxcqp, xsmincqp.
 409
 410 2020-05-11  Alan Modra  <amodra@gmail.com>
 411
 412         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 413         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 414
 415 2020-05-11  Alan Modra  <amodra@gmail.com>
 416
 417         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 418
 419 2020-05-11  Alan Modra  <amodra@gmail.com>
 420
 421         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 422         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 423
 424 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 425
 426         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 427         mnemonics.
 428
 429 2020-05-11  Alan Modra  <amodra@gmail.com>
 430
 431         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 432         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 433         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 434         (prefix_opcodes): Add xxeval.
 435
 436 2020-05-11  Alan Modra  <amodra@gmail.com>
 437
 438         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 439         xxgenpcvwm, xxgenpcvdm.
 440
 441 2020-05-11  Alan Modra  <amodra@gmail.com>
 442
 443         * ppc-opc.c (MP, VXVAM_MASK): Define.
 444         (VXVAPS_MASK): Use VXVA_MASK.
 445         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 446         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 447         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 448         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 449
 450 2020-05-11  Alan Modra  <amodra@gmail.com>
 451             Peter Bergner  <bergner@linux.ibm.com>
 452
 453         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 454         New functions.
 455         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 456         YMSK2, XA6a, XA6ap, XB6a entries.
 457         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 458         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 459         (PPCVSX4): Define.
 460         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 461         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 462         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 463         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 464         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 465         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 466         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 467         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 468         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 469         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 470         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 471         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 472         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 473         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 474
 475 2020-05-11  Alan Modra  <amodra@gmail.com>
 476
 477         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 478         (insert_xts, extract_xts): New functions.
 479         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 480         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 481         (VXRC_MASK, VXSH_MASK): Define.
 482         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 483         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 484         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 485         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 486         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 487         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 488         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 489
 490 2020-05-11  Alan Modra  <amodra@gmail.com>
 491
 492         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 493         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 494         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 495         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 496         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 497
 498 2020-05-11  Alan Modra  <amodra@gmail.com>
 499
 500         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 501         (XTP, DQXP, DQXP_MASK): Define.
 502         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 503         (prefix_opcodes): Add plxvp and pstxvp.
 504
 505 2020-05-11  Alan Modra  <amodra@gmail.com>
 506
 507         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 508         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 509         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 510
 511 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 512
 513         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 514
 515 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 516
 517         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 518         (L1OPT): Define.
 519         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 520
 521 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 522
 523         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 524
 525 2020-05-11  Alan Modra  <amodra@gmail.com>
 526
 527         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 528
 529 2020-05-11  Alan Modra  <amodra@gmail.com>
 530
 531         * ppc-dis.c (ppc_opts): Add "power10" entry.
 532         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 533         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 534
 535 2020-05-11  Nick Clifton  <nickc@redhat.com>
 536
 537         * po/fr.po: Updated French translation.
 538
 539 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 540
 541         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 542         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 543         (operand_general_constraint_met_p): validate
 544         AARCH64_OPND_UNDEFINED.
 545         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 546         for FLD_imm16_2.
 547         * aarch64-asm-2.c: Regenerated.
 548         * aarch64-dis-2.c: Regenerated.
 549         * aarch64-opc-2.c: Regenerated.
 550
 551 2020-04-29  Nick Clifton  <nickc@redhat.com>
 552
 553         PR 22699
 554         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 555         and SETRC insns.
 556
 557 2020-04-29  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/sv.po: Updated Swedish translation.
 560
 561 2020-04-29  Nick Clifton  <nickc@redhat.com>
 562
 563         PR 22699
 564         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 565         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 566         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 567         IMM0_8U case.
 568
 569 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 570
 571         PR 25848
 572         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 573         cmpi only on m68020up and cpu32.
 574
 575 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 576
 577         * aarch64-asm.c (aarch64_ins_none): New.
 578         * aarch64-asm.h (ins_none): New declaration.
 579         * aarch64-dis.c (aarch64_ext_none): New.
 580         * aarch64-dis.h (ext_none): New declaration.
 581         * aarch64-opc.c (aarch64_print_operand): Update case for
 582         AARCH64_OPND_BARRIER_PSB.
 583         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 584         (AARCH64_OPERANDS): Update inserter/extracter for
 585         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 586         * aarch64-asm-2.c: Regenerated.
 587         * aarch64-dis-2.c: Regenerated.
 588         * aarch64-opc-2.c: Regenerated.
 589
 590 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 591
 592         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 593         (aarch64_feature_ras, RAS): Likewise.
 594         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 595         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 596         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 597         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 598         * aarch64-asm-2.c: Regenerated.
 599         * aarch64-dis-2.c: Regenerated.
 600         * aarch64-opc-2.c: Regenerated.
 601
 602 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 603
 604         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 605         (print_insn_neon): Support disassembly of conditional
 606         instructions.
 607
 608 2020-02-16  David Faust  <david.faust@oracle.com>
 609
 610         * bpf-desc.c: Regenerate.
 611         * bpf-desc.h: Likewise.
 612         * bpf-opc.c: Regenerate.
 613         * bpf-opc.h: Likewise.
 614
 615 2020-04-07  Lili Cui  <lili.cui@intel.com>
 616
 617         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 618         (prefix_table): New instructions (see prefixes above).
 619         (rm_table): Likewise
 620         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 621         CPU_ANY_TSXLDTRK_FLAGS.
 622         (cpu_flags): Add CpuTSXLDTRK.
 623         * i386-opc.h (enum): Add CpuTSXLDTRK.
 624         (i386_cpu_flags): Add cputsxldtrk.
 625         * i386-opc.tbl: Add XSUSPLDTRK insns.
 626         * i386-init.h: Regenerate.
 627         * i386-tbl.h: Likewise.
 628
 629 2020-04-02  Lili Cui  <lili.cui@intel.com>
 630
 631         * i386-dis.c (prefix_table): New instructions serialize.
 632         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 633         CPU_ANY_SERIALIZE_FLAGS.
 634         (cpu_flags): Add CpuSERIALIZE.
 635         * i386-opc.h (enum): Add CpuSERIALIZE.
 636         (i386_cpu_flags): Add cpuserialize.
 637         * i386-opc.tbl: Add SERIALIZE insns.
 638         * i386-init.h: Regenerate.
 639         * i386-tbl.h: Likewise.
 640
 641 2020-03-26  Alan Modra  <amodra@gmail.com>
 642
 643         * disassemble.h (opcodes_assert): Declare.
 644         (OPCODES_ASSERT): Define.
 645         * disassemble.c: Don't include assert.h.  Include opintl.h.
 646         (opcodes_assert): New function.
 647         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 648         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 649         calculate maxlen.  Omit insn decoding when insn length exceeds
 650         maxlen.  Exit from nibble loop when looking for E, before
 651         accessing next data byte.  Move processing of E outside loop.
 652         Replace tests of maxlen in loop with assertions.
 653
 654 2020-03-26  Alan Modra  <amodra@gmail.com>
 655
 656         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 657
 658 2020-03-25  Alan Modra  <amodra@gmail.com>
 659
 660         * z80-dis.c (suffix): Init mybuf.
 661
 662 2020-03-22  Alan Modra  <amodra@gmail.com>
 663
 664         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 665         successflly read from section.
 666
 667 2020-03-22  Alan Modra  <amodra@gmail.com>
 668
 669         * arc-dis.c (find_format): Use ISO C string concatenation rather
 670         than line continuation within a string.  Don't access needs_limm
 671         before testing opcode != NULL.
 672
 673 2020-03-22  Alan Modra  <amodra@gmail.com>
 674
 675         * ns32k-dis.c (print_insn_arg): Update comment.
 676         (print_insn_ns32k): Reduce size of index_offset array, and
 677         initialize, passing -1 to print_insn_arg for args that are not
 678         an index.  Don't exit arg loop early.  Abort on bad arg number.
 679
 680 2020-03-22  Alan Modra  <amodra@gmail.com>
 681
 682         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 683         * s12z-opc.c: Formatting.
 684         (operands_f): Return an int.
 685         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 686         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 687         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 688         (exg_sex_discrim): Likewise.
 689         (create_immediate_operand, create_bitfield_operand),
 690         (create_register_operand_with_size, create_register_all_operand),
 691         (create_register_all16_operand, create_simple_memory_operand),
 692         (create_memory_operand, create_memory_auto_operand): Don't
 693         segfault on malloc failure.
 694         (z_ext24_decode): Return an int status, negative on fail, zero
 695         on success.
 696         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 697         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 698         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 699         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 700         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 701         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 702         (loop_primitive_decode, shift_decode, psh_pul_decode),
 703         (bit_field_decode): Similarly.
 704         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 705         to return value, update callers.
 706         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 707         Don't segfault on NULL operand.
 708         (decode_operation): Return OP_INVALID on first fail.
 709         (decode_s12z): Check all reads, returning -1 on fail.
 710
 711 2020-03-20  Alan Modra  <amodra@gmail.com>
 712
 713         * metag-dis.c (print_insn_metag): Don't ignore status from
 714         read_memory_func.
 715
 716 2020-03-20  Alan Modra  <amodra@gmail.com>
 717
 718         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 719         Initialize parts of buffer not written when handling a possible
 720         2-byte insn at end of section.  Don't attempt decoding of such
 721         an insn by the 4-byte machinery.
 722
 723 2020-03-20  Alan Modra  <amodra@gmail.com>
 724
 725         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 726         partially filled buffer.  Prevent lookup of 4-byte insns when
 727         only VLE 2-byte insns are possible due to section size.  Print
 728         ".word" rather than ".long" for 2-byte leftovers.
 729
 730 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 731
 732         PR 25641
 733         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 734
 735 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-dis.c (X86_64_0D): Rename to ...
 738         (X86_64_0E): ... this.
 739
 740 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 743         * Makefile.in: Regenerated.
 744
 745 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 748         3-operand pseudos.
 749         * i386-tbl.h: Re-generate.
 750
 751 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 754         vprot*, vpsha*, and vpshl*.
 755         * i386-tbl.h: Re-generate.
 756
 757 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 758
 759         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 760         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 761         * i386-tbl.h: Re-generate.
 762
 763 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 766         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 767         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 768         * i386-tbl.h: Re-generate.
 769
 770 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-gen.c (struct template_arg, struct template_instance,
 773         struct template_param, struct template, templates,
 774         parse_template, expand_templates): New.
 775         (process_i386_opcodes): Various local variables moved to
 776         expand_templates. Call parse_template and expand_templates.
 777         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 778         * i386-tbl.h: Re-generate.
 779
 780 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 783         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 784         register and memory source templates. Replace VexW= by VexW*
 785         where applicable.
 786         * i386-tbl.h: Re-generate.
 787
 788 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 791         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 792         * i386-tbl.h: Re-generate.
 793
 794 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 797         * i386-tbl.h: Re-generate.
 798
 799 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 802         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 803         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 804         VexW0 on SSE2AVX variants.
 805         (vmovq): Drop NoRex64 from XMM/XMM variants.
 806         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 807         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 808         applicable use VexW0.
 809         * i386-tbl.h: Re-generate.
 810
 811 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 814         * i386-opc.h (Rex64): Delete.
 815         (struct i386_opcode_modifier): Remove rex64 field.
 816         * i386-opc.tbl (crc32): Drop Rex64.
 817         Replace Rex64 with Size64 everywhere else.
 818         * i386-tbl.h: Re-generate.
 819
 820 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-dis.c (OP_E_memory): Exclude recording of used address
 823         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 824         addressed memory operands for MPX insns.
 825
 826 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 827
 828         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 829         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 830         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 831         (ptwrite): Split into non-64-bit and 64-bit forms.
 832         * i386-tbl.h: Re-generate.
 833
 834 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 837         template.
 838         * i386-tbl.h: Re-generate.
 839
 840 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 843         (prefix_table): Move vmmcall here. Add vmgexit.
 844         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 845         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 846         (cpu_flags): Add CpuSEV_ES entry.
 847         * i386-opc.h (CpuSEV_ES): New.
 848         (union i386_cpu_flags): Add cpusev_es field.
 849         * i386-opc.tbl (vmgexit): New.
 850         * i386-init.h, i386-tbl.h: Re-generate.
 851
 852 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 853
 854         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 855         with MnemonicSize.
 856         * i386-opc.h (IGNORESIZE): New.
 857         (DEFAULTSIZE): Likewise.
 858         (IgnoreSize): Removed.
 859         (DefaultSize): Likewise.
 860         (MnemonicSize): New.
 861         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 862         mnemonicsize.
 863         * i386-opc.tbl (IgnoreSize): New.
 864         (DefaultSize): Likewise.
 865         * i386-tbl.h: Regenerated.
 866
 867 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 868
 869         PR 25627
 870         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 871         instructions.
 872
 873 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 874
 875         PR gas/25622
 876         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 877         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 878         * i386-tbl.h: Regenerated.
 879
 880 2020-02-26  Alan Modra  <amodra@gmail.com>
 881
 882         * aarch64-asm.c: Indent labels correctly.
 883         * aarch64-dis.c: Likewise.
 884         * aarch64-gen.c: Likewise.
 885         * aarch64-opc.c: Likewise.
 886         * alpha-dis.c: Likewise.
 887         * i386-dis.c: Likewise.
 888         * nds32-asm.c: Likewise.
 889         * nfp-dis.c: Likewise.
 890         * visium-dis.c: Likewise.
 891
 892 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 893
 894         * arc-regs.h (int_vector_base): Make it available for all ARC
 895         CPUs.
 896
 897 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 898
 899         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 900         changed.
 901
 902 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 903
 904         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 905         c.mv/c.li if rs1 is zero.
 906
 907 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 908
 909         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 910         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 911         CPU_POPCNT_FLAGS.
 912         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 913         * i386-opc.h (CpuABM): Removed.
 914         (CpuPOPCNT): New.
 915         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 916         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 917         popcnt.  Remove CpuABM from lzcnt.
 918         * i386-init.h: Regenerated.
 919         * i386-tbl.h: Likewise.
 920
 921 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 924         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 925         VexW1 instead of open-coding them.
 926         * i386-tbl.h: Re-generate.
 927
 928 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (AddrPrefixOpReg): Define.
 931         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 932         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 933         templates. Drop NoRex64.
 934         * i386-tbl.h: Re-generate.
 935
 936 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 937
 938         PR gas/6518
 939         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 940         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 941         into Intel syntax instance (with Unpsecified) and AT&T one
 942         (without).
 943         (vcvtneps2bf16): Likewise, along with folding the two so far
 944         separate ones.
 945         * i386-tbl.h: Re-generate.
 946
 947 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 948
 949         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 950         CPU_ANY_SSE4A_FLAGS.
 951
 952 2020-02-17  Alan Modra  <amodra@gmail.com>
 953
 954         * i386-gen.c (cpu_flag_init): Correct last change.
 955
 956 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 959         CPU_ANY_SSE4_FLAGS.
 960
 961 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 962
 963         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 964         (movzx): Likewise.
 965
 966 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 967
 968         PR gas/25438
 969         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 970         destination for Cpu64-only variant.
 971         (movzx): Fold patterns.
 972         * i386-tbl.h: Re-generate.
 973
 974 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 977         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 978         CPU_ANY_SSE4_FLAGS entry.
 979         * i386-init.h: Re-generate.
 980
 981 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 982
 983         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 984         with Unspecified, making the present one AT&T syntax only.
 985         * i386-tbl.h: Re-generate.
 986
 987 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 988
 989         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 990         * i386-tbl.h: Re-generate.
 991
 992 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 993
 994         PR gas/24546
 995         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 996         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 997         Amd64 and Intel64 templates.
 998         (call, jmp): Likewise for far indirect variants. Dro
 999         Unspecified.
1000         * i386-tbl.h: Re-generate.
1001
1002 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1003
1004         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1005         * i386-opc.h (ShortForm): Delete.
1006         (struct i386_opcode_modifier): Remove shortform field.
1007         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1008         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1009         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1010         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1011         Drop ShortForm.
1012         * i386-tbl.h: Re-generate.
1013
1014 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1017         fucompi): Drop ShortForm from operand-less templates.
1018         * i386-tbl.h: Re-generate.
1019
1020 2020-02-11  Alan Modra  <amodra@gmail.com>
1021
1022         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1023         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1024         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1025         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1026         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1027
1028 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1029
1030         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1031         (cde_opcodes): Add VCX* instructions.
1032
1033 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1034             Matthew Malcomson  <matthew.malcomson@arm.com>
1035
1036         * arm-dis.c (struct cdeopcode32): New.
1037         (CDE_OPCODE): New macro.
1038         (cde_opcodes): New disassembly table.
1039         (regnames): New option to table.
1040         (cde_coprocs): New global variable.
1041         (print_insn_cde): New
1042         (print_insn_thumb32): Use print_insn_cde.
1043         (parse_arm_disassembler_options): Parse coprocN args.
1044
1045 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         PR gas/25516
1048         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1049         with ISA64.
1050         * i386-opc.h (AMD64): Removed.
1051         (Intel64): Likewose.
1052         (AMD64): New.
1053         (INTEL64): Likewise.
1054         (INTEL64ONLY): Likewise.
1055         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1056         * i386-opc.tbl (Amd64): New.
1057         (Intel64): Likewise.
1058         (Intel64Only): Likewise.
1059         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1060         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1061         * i386-tbl.h: Regenerated.
1062
1063 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1064
1065         PR 25469
1066         * z80-dis.c: Add support for GBZ80 opcodes.
1067
1068 2020-02-04  Alan Modra  <amodra@gmail.com>
1069
1070         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1071
1072 2020-02-03  Alan Modra  <amodra@gmail.com>
1073
1074         * m32c-ibld.c: Regenerate.
1075
1076 2020-02-01  Alan Modra  <amodra@gmail.com>
1077
1078         * frv-ibld.c: Regenerate.
1079
1080 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1081
1082         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1083         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1084         (OP_E_memory): Replace xmm_mdq_mode case label by
1085         vex_scalar_w_dq_mode one.
1086         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1087
1088 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1089
1090         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1091         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1092         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1093         (intel_operand_size): Drop vex_w_dq_mode case label.
1094
1095 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1096
1097         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1098         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1099
1100 2020-01-30  Alan Modra  <amodra@gmail.com>
1101
1102         * m32c-ibld.c: Regenerate.
1103
1104 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1105
1106         * bpf-opc.c: Regenerate.
1107
1108 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1111         (dis386): Use them to replace C2/C3 table entries.
1112         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1113         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1114         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1115         * i386-tbl.h: Re-generate.
1116
1117 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1120         forms.
1121         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1122         DefaultSize.
1123         * i386-tbl.h: Re-generate.
1124
1125 2020-01-30  Alan Modra  <amodra@gmail.com>
1126
1127         * tic4x-dis.c (tic4x_dp): Make unsigned.
1128
1129 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1130             Jan Beulich  <jbeulich@suse.com>
1131
1132         PR binutils/25445
1133         * i386-dis.c (MOVSXD_Fixup): New function.
1134         (movsxd_mode): New enum.
1135         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1136         (intel_operand_size): Handle movsxd_mode.
1137         (OP_E_register): Likewise.
1138         (OP_G): Likewise.
1139         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1140         register on movsxd.  Add movsxd with 16-bit destination register
1141         for AMD64 and Intel64 ISAs.
1142         * i386-tbl.h: Regenerated.
1143
1144 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1145
1146         PR 25403
1147         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1148         * aarch64-asm-2.c: Regenerate
1149         * aarch64-dis-2.c: Likewise.
1150         * aarch64-opc-2.c: Likewise.
1151
1152 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1153
1154         * i386-opc.tbl (sysret): Drop DefaultSize.
1155         * i386-tbl.h: Re-generate.
1156
1157 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1160         Dword.
1161         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1162         * i386-tbl.h: Re-generate.
1163
1164 2020-01-20  Nick Clifton  <nickc@redhat.com>
1165
1166         * po/de.po: Updated German translation.
1167         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1168         * po/uk.po: Updated Ukranian translation.
1169
1170 2020-01-20  Alan Modra  <amodra@gmail.com>
1171
1172         * hppa-dis.c (fput_const): Remove useless cast.
1173
1174 2020-01-20  Alan Modra  <amodra@gmail.com>
1175
1176         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1177
1178 2020-01-18  Nick Clifton  <nickc@redhat.com>
1179
1180         * configure: Regenerate.
1181         * po/opcodes.pot: Regenerate.
1182
1183 2020-01-18  Nick Clifton  <nickc@redhat.com>
1184
1185         Binutils 2.34 branch created.
1186
1187 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1188
1189         * opintl.h: Fix spelling error (seperate).
1190
1191 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1192
1193         * i386-opc.tbl: Add {vex} pseudo prefix.
1194         * i386-tbl.h: Regenerated.
1195
1196 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1197
1198         PR 25376
1199         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1200         (neon_opcodes): Likewise.
1201         (select_arm_features): Make sure we enable MVE bits when selecting
1202         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1203         any architecture.
1204
1205 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1206
1207         * i386-opc.tbl: Drop stale comment from XOP section.
1208
1209 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1212         (extractps): Add VexWIG to SSE2AVX forms.
1213         * i386-tbl.h: Re-generate.
1214
1215 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1216
1217         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1218         Size64 from and use VexW1 on SSE2AVX forms.
1219         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1220         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1221         * i386-tbl.h: Re-generate.
1222
1223 2020-01-15  Alan Modra  <amodra@gmail.com>
1224
1225         * tic4x-dis.c (tic4x_version): Make unsigned long.
1226         (optab, optab_special, registernames): New file scope vars.
1227         (tic4x_print_register): Set up registernames rather than
1228         malloc'd registertable.
1229         (tic4x_disassemble): Delete optable and optable_special.  Use
1230         optab and optab_special instead.  Throw away old optab,
1231         optab_special and registernames when info->mach changes.
1232
1233 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1234
1235         PR 25377
1236         * z80-dis.c (suffix): Use .db instruction to generate double
1237         prefix.
1238
1239 2020-01-14  Alan Modra  <amodra@gmail.com>
1240
1241         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1242         values to unsigned before shifting.
1243
1244 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1245
1246         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1247         flow instructions.
1248         (print_insn_thumb16, print_insn_thumb32): Likewise.
1249         (print_insn): Initialize the insn info.
1250         * i386-dis.c (print_insn): Initialize the insn info fields, and
1251         detect jumps.
1252
1253 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1254
1255         * arc-opc.c (C_NE): Make it required.
1256
1257 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1258
1259         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1260         reserved register name.
1261
1262 2020-01-13  Alan Modra  <amodra@gmail.com>
1263
1264         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1265         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1266
1267 2020-01-13  Alan Modra  <amodra@gmail.com>
1268
1269         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1270         result of wasm_read_leb128 in a uint64_t and check that bits
1271         are not lost when copying to other locals.  Use uint32_t for
1272         most locals.  Use PRId64 when printing int64_t.
1273
1274 2020-01-13  Alan Modra  <amodra@gmail.com>
1275
1276         * score-dis.c: Formatting.
1277         * score7-dis.c: Formatting.
1278
1279 2020-01-13  Alan Modra  <amodra@gmail.com>
1280
1281         * score-dis.c (print_insn_score48): Use unsigned variables for
1282         unsigned values.  Don't left shift negative values.
1283         (print_insn_score32): Likewise.
1284         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1285
1286 2020-01-13  Alan Modra  <amodra@gmail.com>
1287
1288         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1289
1290 2020-01-13  Alan Modra  <amodra@gmail.com>
1291
1292         * fr30-ibld.c: Regenerate.
1293
1294 2020-01-13  Alan Modra  <amodra@gmail.com>
1295
1296         * xgate-dis.c (print_insn): Don't left shift signed value.
1297         (ripBits): Formatting, use 1u.
1298
1299 2020-01-10  Alan Modra  <amodra@gmail.com>
1300
1301         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1302         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1303
1304 2020-01-10  Alan Modra  <amodra@gmail.com>
1305
1306         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1307         and XRREG value earlier to avoid a shift with negative exponent.
1308         * m10200-dis.c (disassemble): Similarly.
1309
1310 2020-01-09  Nick Clifton  <nickc@redhat.com>
1311
1312         PR 25224
1313         * z80-dis.c (ld_ii_ii): Use correct cast.
1314
1315 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1316
1317         PR 25224
1318         * z80-dis.c (ld_ii_ii): Use character constant when checking
1319         opcode byte value.
1320
1321 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1322
1323         * i386-dis.c (SEP_Fixup): New.
1324         (SEP): Define.
1325         (dis386_twobyte): Use it for sysenter/sysexit.
1326         (enum x86_64_isa): Change amd64 enumerator to value 1.
1327         (OP_J): Compare isa64 against intel64 instead of amd64.
1328         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1329         forms.
1330         * i386-tbl.h: Re-generate.
1331
1332 2020-01-08  Alan Modra  <amodra@gmail.com>
1333
1334         * z8k-dis.c: Include libiberty.h
1335         (instr_data_s): Make max_fetched unsigned.
1336         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1337         Don't exceed byte_info bounds.
1338         (output_instr): Make num_bytes unsigned.
1339         (unpack_instr): Likewise for nibl_count and loop.
1340         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1341         idx unsigned.
1342         * z8k-opc.h: Regenerate.
1343
1344 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1345
1346         * arc-tbl.h (llock): Use 'LLOCK' as class.
1347         (llockd): Likewise.
1348         (scond): Use 'SCOND' as class.
1349         (scondd): Likewise.
1350         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1351         (scondd): Likewise.
1352
1353 2020-01-06  Alan Modra  <amodra@gmail.com>
1354
1355         * m32c-ibld.c: Regenerate.
1356
1357 2020-01-06  Alan Modra  <amodra@gmail.com>
1358
1359         PR 25344
1360         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1361         Peek at next byte to prevent recursion on repeated prefix bytes.
1362         Ensure uninitialised "mybuf" is not accessed.
1363         (print_insn_z80): Don't zero n_fetch and n_used here,..
1364         (print_insn_z80_buf): ..do it here instead.
1365
1366 2020-01-04  Alan Modra  <amodra@gmail.com>
1367
1368         * m32r-ibld.c: Regenerate.
1369
1370 2020-01-04  Alan Modra  <amodra@gmail.com>
1371
1372         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1373
1374 2020-01-04  Alan Modra  <amodra@gmail.com>
1375
1376         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1377
1378 2020-01-04  Alan Modra  <amodra@gmail.com>
1379
1380         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1381
1382 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1383
1384         * aarch64-tbl.h (aarch64_opcode_table): Use
1385         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1386
1387 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1388
1389         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1390         forms of SUDOT and USDOT.
1391
1392 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1393
1394         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1395         uzip{1,2}.
1396         * opcodes/aarch64-dis-2.c: Re-generate.
1397
1398 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1399
1400         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1401         FMMLA encoding.
1402         * opcodes/aarch64-dis-2.c: Re-generate.
1403
1404 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1405
1406         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1407
1408 2020-01-01  Alan Modra  <amodra@gmail.com>
1409
1410         Update year range in copyright notice of all files.
1411
1412 For older changes see ChangeLog-2019
1413 \f
1414 Copyright (C) 2020 Free Software Foundation, Inc.
1415
1416 Copying and distribution of this file, with or without modification,
1417 are permitted in any medium without royalty provided the copyright
1418 notice and this notice are preserved.
1419
1420 Local Variables:
1421 mode: change-log
1422 left-margin: 8
1423 fill-column: 74
1424 version-control: never
1425 End: