opcodes/ChangeLog

   1 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
   4         instructions.
   5
   6 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
   7
   8         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
   9         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
  10         (aarch64_opcode_table): Add fcmla and fcadd.
  11         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
  12         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
  13         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
  14         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
  15         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
  16         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
  17         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
  18         (operand_general_constraint_met_p): Rotate and index range check.
  19         (aarch64_print_operand): Handle rotate operand.
  20         * aarch64-asm-2.c: Regenerate.
  21         * aarch64-dis-2.c: Likewise.
  22         * aarch64-opc-2.c: Likewise.
  23
  24 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  25
  26         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
  27         * aarch64-asm-2.c: Regenerate.
  28         * aarch64-dis-2.c: Regenerate.
  29         * aarch64-opc-2.c: Regenerate.
  30
  31 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  32
  33         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
  34         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
  35         * aarch64-asm-2.c: Regenerate.
  36         * aarch64-dis-2.c: Regenerate.
  37         * aarch64-opc-2.c: Regenerate.
  38
  39 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  40
  41         * aarch64-tbl.h (QL_X1NIL): New.
  42         (arch64_opcode_table): Add ldraa, ldrab.
  43         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
  44         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
  45         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
  46         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
  47         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
  48         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
  49         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
  50         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
  51         (aarch64_print_operand): Likewise.
  52         * aarch64-asm-2.c: Regenerate.
  53         * aarch64-dis-2.c: Regenerate.
  54         * aarch64-opc-2.c: Regenerate.
  55
  56 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  57
  58         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
  59         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
  60         * aarch64-asm-2.c: Regenerate.
  61         * aarch64-dis-2.c: Regenerate.
  62         * aarch64-opc-2.c: Regenerate.
  63
  64 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  65
  66         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
  67         (AARCH64_OPERANDS): Add Rm_SP.
  68         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
  69         * aarch64-asm-2.c: Regenerate.
  70         * aarch64-dis-2.c: Regenerate.
  71         * aarch64-opc-2.c: Regenerate.
  72
  73 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  74
  75         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
  76         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
  77         autdzb, xpaci, xpacd.
  78         * aarch64-asm-2.c: Regenerate.
  79         * aarch64-dis-2.c: Regenerate.
  80         * aarch64-opc-2.c: Regenerate.
  81
  82 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  83
  84         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
  85         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
  86         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
  87         (aarch64_sys_reg_supported_p): Add feature test for new registers.
  88
  89 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  90
  91         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
  92         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
  93         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
  94         autibsp.
  95         * aarch64-asm-2.c: Regenerate.
  96         * aarch64-dis-2.c: Regenerate.
  97
  98 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  99
 100         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 101
 102 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         PR binutils/20799
 105         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 106         * i386-dis.c (EdqwS): Removed.
 107         (dqw_swap_mode): Likewise.
 108         (intel_operand_size): Don't check dqw_swap_mode.
 109         (OP_E_register): Likewise.
 110         (OP_E_memory): Likewise.
 111         (OP_G): Likewise.
 112         (OP_EX): Likewise.
 113         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 114         * i386-tbl.h: Regerated.
 115
 116 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         * i386-opc.tbl: Merge AVX512F vmovq.
 119         * i386-tbl.h: Regerated.
 120
 121 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         PR binutils/20701
 124         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 125         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 126         (three_byte_table): Remove THREE_BYTE_0F7A.
 127
 128 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         PR binutils/20775
 131         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 132         (FGRPd9_4): Replace 1 with 2.
 133         (FGRPd9_5): Replace 2 with 3.
 134         (FGRPd9_6): Replace 3 with 4.
 135         (FGRPd9_7): Replace 4 with 5.
 136         (FGRPda_5): Replace 5 with 6.
 137         (FGRPdb_4): Replace 6 with 7.
 138         (FGRPde_3): Replace 7 with 8.
 139         (FGRPdf_4): Replace 8 with 9.
 140         (fgrps): Add an entry for Bad_Opcode.
 141
 142 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 143
 144         * arc-opc.c (arc_flag_operands): Add F_DI14.
 145         (arc_flag_classes): Add C_DI14.
 146         * arc-nps400-tbl.h: Add new exc instructions.
 147
 148 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 149
 150         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 151         major opcode 0xa.
 152         * arc-nps-400-tbl.h: Add dcmac instruction.
 153         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 154         (insert_nps_rbdouble_64): Added.
 155         (extract_nps_rbdouble_64): Added.
 156         (insert_nps_proto_size): Added.
 157         (extract_nps_proto_size): Added.
 158
 159 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 160
 161         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 162         relating to long instruction processing, add new limm field.
 163         (OPCODE): Rename to...
 164         (OPCODE_32BIT_INSN): ...this.
 165         (OPCODE_AC): Delete.
 166         (skip_this_opcode): Handle different instruction lengths, update
 167         macro name.
 168         (special_flag_p): Update parameter type.
 169         (find_format_from_table): Update for more instruction lengths.
 170         (find_format_long_instructions): Delete.
 171         (find_format): Update for more instruction lengths.
 172         (arc_insn_length): Likewise.
 173         (extract_operand_value): Update for more instruction lengths.
 174         (operand_iterator_next): Remove code relating to long
 175         instructions.
 176         (arc_opcode_to_insn_type): New function.
 177         (print_insn_arc):Update for more instructions lengths.
 178         * arc-ext.c (extInstruction_t): Change argument type.
 179         * arc-ext.h (extInstruction_t): Change argument type.
 180         * arc-fxi.h: Change type unsigned to unsigned long long
 181         extensively throughout.
 182         * arc-nps400-tbl.h: Add long instructions taken from
 183         arc_long_opcodes table in arc-opc.c.
 184         * arc-opc.c: Update parameter types on insert/extract handlers.
 185         (arc_long_opcodes): Delete.
 186         (arc_num_long_opcodes): Delete.
 187         (arc_opcode_len): Update for more instruction lengths.
 188
 189 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 190
 191         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 192
 193 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 194
 195         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 196         with arc_opcode_len.
 197         (find_format_long_instructions): Likewise.
 198         * arc-opc.c (arc_opcode_len): New function.
 199
 200 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 201
 202         * arc-nps400-tbl.h: Fix some instruction masks.
 203
 204 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 205
 206         * i386-dis.c (REG_82): Removed.
 207         (X86_64_82_REG_0): Likewise.
 208         (X86_64_82_REG_1): Likewise.
 209         (X86_64_82_REG_2): Likewise.
 210         (X86_64_82_REG_3): Likewise.
 211         (X86_64_82_REG_4): Likewise.
 212         (X86_64_82_REG_5): Likewise.
 213         (X86_64_82_REG_6): Likewise.
 214         (X86_64_82_REG_7): Likewise.
 215         (X86_64_82): New.
 216         (dis386): Use X86_64_82 instead of REG_82.
 217         (reg_table): Remove REG_82.
 218         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 219         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 220         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 221         X86_64_82_REG_7.
 222
 223 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         PR binutils/20754
 226         * i386-dis.c (REG_82): New.
 227         (X86_64_82_REG_0): Likewise.
 228         (X86_64_82_REG_1): Likewise.
 229         (X86_64_82_REG_2): Likewise.
 230         (X86_64_82_REG_3): Likewise.
 231         (X86_64_82_REG_4): Likewise.
 232         (X86_64_82_REG_5): Likewise.
 233         (X86_64_82_REG_6): Likewise.
 234         (X86_64_82_REG_7): Likewise.
 235         (dis386): Use REG_82.
 236         (reg_table): Add REG_82.
 237         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 238         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 239         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 240
 241 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         * i386-dis.c (REG_82): Renamed to ...
 244         (REG_83): This.
 245         (dis386): Updated.
 246         (reg_table): Likewise.
 247
 248 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 249
 250         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 251         * i386-dis-evex.h (evex_table): Updated.
 252         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 253         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 254         (cpu_flags): Add CpuAVX512_4VNNIW.
 255         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 256         (i386_cpu_flags): Add cpuavx512_4vnniw.
 257         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 258         * i386-init.h: Regenerate.
 259         * i386-tbl.h: Ditto.
 260
 261 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 262
 263         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 264         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 265         * i386-dis-evex.h (evex_table): Updated.
 266         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 267         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 268         (cpu_flags): Add CpuAVX512_4FMAPS.
 269         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 270         * i386-opc.h (AVX512_4FMAP): New.
 271         (i386_cpu_flags): Add cpuavx512_4fmaps.
 272         (ImplicitQuadGroup): New.
 273         (i386_opcode_modifier): Add implicitquadgroup.
 274         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 275         * i386-init.h: Regenerate.
 276         * i386-tbl.h: Ditto.
 277
 278 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 279             Andrew Waterman <andrew@sifive.com>
 280
 281         Add support for RISC-V architecture.
 282         * configure.ac: Add entry for bfd_riscv_arch.
 283         * configure: Regenerate.
 284         * disassemble.c (disassembler): Add support for riscv.
 285         (disassembler_usage): Likewise.
 286         * riscv-dis.c: New file.
 287         * riscv-opc.c: New file.
 288
 289 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 290
 291         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 292         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 293         (rm_table): Update the RM_0FAE_REG_7 entry.
 294         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 295         (cpu_flags): Remove CpuPCOMMIT.
 296         * i386-opc.h (CpuPCOMMIT): Removed.
 297         (i386_cpu_flags): Remove cpupcommit.
 298         * i386-opc.tbl: Remove pcommit.
 299         * i386-init.h: Regenerated.
 300         * i386-tbl.h: Likewise.
 301
 302 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         PR binutis/20705
 305         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 306         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 307         32-bit mode.  Don't check vex.register_specifier in 32-bit
 308         mode.
 309         (OP_VEX): Check for invalid mask registers.
 310
 311 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         PR binutis/20699
 314         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 315         sizeflag.
 316
 317 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         PR binutis/20704
 320         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 321
 322 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 323
 324         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 325         local variable to `index_regno'.
 326
 327 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 328
 329         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 330
 331 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 332
 333         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 334         usage on ISA basis.
 335
 336 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 337
 338         PR target/20666
 339         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 340
 341 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 342
 343         PR target/20667
 344         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 345         available.
 346
 347 2016-10-07  Alan Modra  <amodra@gmail.com>
 348
 349         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 350
 351 2016-10-06  Alan Modra  <amodra@gmail.com>
 352
 353         * aarch64-opc.c: Spell fall through comments consistently.
 354         * i386-dis.c: Likewise.
 355         * aarch64-dis.c: Add missing fall through comments.
 356         * aarch64-opc.c: Likewise.
 357         * arc-dis.c: Likewise.
 358         * arm-dis.c: Likewise.
 359         * i386-dis.c: Likewise.
 360         * m68k-dis.c: Likewise.
 361         * mep-asm.c: Likewise.
 362         * ns32k-dis.c: Likewise.
 363         * sh-dis.c: Likewise.
 364         * tic4x-dis.c: Likewise.
 365         * tic6x-dis.c: Likewise.
 366         * vax-dis.c: Likewise.
 367
 368 2016-10-06  Alan Modra  <amodra@gmail.com>
 369
 370         * arc-ext.c (create_map): Add missing break.
 371         * msp430-decode.opc (encode_as): Likewise.
 372         * msp430-decode.c: Regenerate.
 373
 374 2016-10-06  Alan Modra  <amodra@gmail.com>
 375
 376         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 377         * crx-dis.c (print_insn_crx): Likewise.
 378
 379 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 380
 381         PR binutils/20657
 382         * i386-dis.c (putop): Don't assign alt twice.
 383
 384 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 385
 386         PR target/20553
 387         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 388
 389 2016-09-29  Alan Modra  <amodra@gmail.com>
 390
 391         * ppc-opc.c (L): Make compulsory.
 392         (LOPT): New, optional form of L.
 393         (HTM_R): Define as LOPT.
 394         (L0, L1): Delete.
 395         (L32OPT): New, optional for 32-bit L.
 396         (L2OPT): New, 2-bit L for dcbf.
 397         (SVC_LEC): Update.
 398         (L2): Define.
 399         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 400         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 401         <dcbf>: Use L2OPT.
 402         <tlbiel, tlbie>: Use LOPT.
 403         <wclr, wclrall>: Use L2.
 404
 405 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 406
 407         * Makefile.in: Regenerate.
 408         * configure: Likewise.
 409
 410 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 411
 412         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 413         (EXTINSN2OP): Use EXTINSN2OPF.
 414         (bspeekm, bspop, modapp): New extension instructions.
 415         * arc-opc.c (F_DNZ_ND): Define.
 416         (F_DNZ_D): Likewise.
 417         (F_SIZEB1): Changed.
 418         (C_DNZ_D): Define.
 419         (C_HARD): Changed.
 420         * arc-tbl.h (dbnz): New instruction.
 421         (prealloc): Allow it for ARC EM.
 422         (xbfu): Likewise.
 423
 424 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 425
 426         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 427         after commas in addresses.
 428         (aarch64_print_operand): Likewise.
 429
 430 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 431
 432         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 433         rather than "should be" or "expected to be" in error messages.
 434
 435 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 436
 437         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 438         (print_mnemonic_name): ...here.
 439         (print_comment): New function.
 440         (print_aarch64_insn): Call it.
 441         * aarch64-opc.c (aarch64_conds): Add SVE names.
 442         (aarch64_print_operand): Print alternative condition names in
 443         a comment.
 444
 445 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 446
 447         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 448         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 449         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 450         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 451         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 452         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 453         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 454         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 455         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 456         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 457         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 458         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 459         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 460         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 461         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 462         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 463         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 464         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 465         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 466         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 467         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 468         (aarch64_feature_sve): New variable.
 469         (SVE): New macro.
 470         (_SVE_INSN): Likewise.
 471         (aarch64_opcode_table): Add SVE instructions.
 472         * aarch64-opc.h (extract_fields): Declare.
 473         * aarch64-opc-2.c: Regenerate.
 474         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 475         * aarch64-asm-2.c: Regenerate.
 476         * aarch64-dis.c (extract_fields): Make global.
 477         (do_misc_decoding): Handle the new SVE aarch64_ops.
 478         * aarch64-dis-2.c: Regenerate.
 479
 480 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 481
 482         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 483         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 484         aarch64_field_kinds.
 485         * aarch64-opc.c (fields): Add corresponding entries.
 486         * aarch64-asm.c (aarch64_get_variant): New function.
 487         (aarch64_encode_variant_using_iclass): Likewise.
 488         (aarch64_opcode_encode): Call it.
 489         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 490         (aarch64_opcode_decode): Call it.
 491
 492 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 493
 494         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 495         and FP register operands.
 496         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 497         (FLD_SVE_Vn): New aarch64_field_kinds.
 498         * aarch64-opc.c (fields): Add corresponding entries.
 499         (aarch64_print_operand): Handle the new SVE core and FP register
 500         operands.
 501         * aarch64-opc-2.c: Regenerate.
 502         * aarch64-asm-2.c: Likewise.
 503         * aarch64-dis-2.c: Likewise.
 504
 505 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 506
 507         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 508         immediate operands.
 509         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 510         * aarch64-opc.c (fields): Add corresponding entry.
 511         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 512         operands.
 513         (aarch64_print_operand): Likewise.
 514         * aarch64-opc-2.c: Regenerate.
 515         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 516         (ins_sve_float_zero_one): New inserters.
 517         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 518         (aarch64_ins_sve_float_half_two): Likewise.
 519         (aarch64_ins_sve_float_zero_one): Likewise.
 520         * aarch64-asm-2.c: Regenerate.
 521         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 522         (ext_sve_float_zero_one): New extractors.
 523         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 524         (aarch64_ext_sve_float_half_two): Likewise.
 525         (aarch64_ext_sve_float_zero_one): Likewise.
 526         * aarch64-dis-2.c: Regenerate.
 527
 528 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 529
 530         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 531         integer immediate operands.
 532         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 533         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 534         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 535         * aarch64-opc.c (fields): Add corresponding entries.
 536         (operand_general_constraint_met_p): Handle the new SVE integer
 537         immediate operands.
 538         (aarch64_print_operand): Likewise.
 539         (aarch64_sve_dupm_mov_immediate_p): New function.
 540         * aarch64-opc-2.c: Regenerate.
 541         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 542         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 543         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 544         (aarch64_ins_limm): ...here.
 545         (aarch64_ins_inv_limm): New function.
 546         (aarch64_ins_sve_aimm): Likewise.
 547         (aarch64_ins_sve_asimm): Likewise.
 548         (aarch64_ins_sve_limm_mov): Likewise.
 549         (aarch64_ins_sve_shlimm): Likewise.
 550         (aarch64_ins_sve_shrimm): Likewise.
 551         * aarch64-asm-2.c: Regenerate.
 552         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 553         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 554         * aarch64-dis.c (decode_limm): New function, split out from...
 555         (aarch64_ext_limm): ...here.
 556         (aarch64_ext_inv_limm): New function.
 557         (decode_sve_aimm): Likewise.
 558         (aarch64_ext_sve_aimm): Likewise.
 559         (aarch64_ext_sve_asimm): Likewise.
 560         (aarch64_ext_sve_limm_mov): Likewise.
 561         (aarch64_top_bit): Likewise.
 562         (aarch64_ext_sve_shlimm): Likewise.
 563         (aarch64_ext_sve_shrimm): Likewise.
 564         * aarch64-dis-2.c: Regenerate.
 565
 566 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 567
 568         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 569         operands.
 570         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 571         the AARCH64_MOD_MUL_VL entry.
 572         (value_aligned_p): Cope with non-power-of-two alignments.
 573         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 574         (print_immediate_offset_address): Likewise.
 575         (aarch64_print_operand): Likewise.
 576         * aarch64-opc-2.c: Regenerate.
 577         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 578         (ins_sve_addr_ri_s9xvl): New inserters.
 579         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 580         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 581         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 582         * aarch64-asm-2.c: Regenerate.
 583         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 584         (ext_sve_addr_ri_s9xvl): New extractors.
 585         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 586         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 587         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 588         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 589         * aarch64-dis-2.c: Regenerate.
 590
 591 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 592
 593         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 594         address operands.
 595         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 596         (FLD_SVE_xs_22): New aarch64_field_kinds.
 597         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 598         (get_operand_specific_data): New function.
 599         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 600         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 601         (operand_general_constraint_met_p): Handle the new SVE address
 602         operands.
 603         (sve_reg): New array.
 604         (get_addr_sve_reg_name): New function.
 605         (aarch64_print_operand): Handle the new SVE address operands.
 606         * aarch64-opc-2.c: Regenerate.
 607         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 608         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 609         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 610         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 611         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 612         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 613         (aarch64_ins_sve_addr_zi_u5): Likewise.
 614         (aarch64_ins_sve_addr_zz): Likewise.
 615         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 616         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 617         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 618         * aarch64-asm-2.c: Regenerate.
 619         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 620         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 621         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 622         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 623         (aarch64_ext_sve_addr_ri_u6): Likewise.
 624         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 625         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 626         (aarch64_ext_sve_addr_zi_u5): Likewise.
 627         (aarch64_ext_sve_addr_zz): Likewise.
 628         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 629         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 630         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 631         * aarch64-dis-2.c: Regenerate.
 632
 633 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 634
 635         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 636         AARCH64_OPND_SVE_PATTERN_SCALED.
 637         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 638         * aarch64-opc.c (fields): Add a corresponding entry.
 639         (set_multiplier_out_of_range_error): New function.
 640         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 641         (operand_general_constraint_met_p): Handle
 642         AARCH64_OPND_SVE_PATTERN_SCALED.
 643         (print_register_offset_address): Use PRIi64 to print the
 644         shift amount.
 645         (aarch64_print_operand): Likewise.  Handle
 646         AARCH64_OPND_SVE_PATTERN_SCALED.
 647         * aarch64-opc-2.c: Regenerate.
 648         * aarch64-asm.h (ins_sve_scale): New inserter.
 649         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 650         * aarch64-asm-2.c: Regenerate.
 651         * aarch64-dis.h (ext_sve_scale): New inserter.
 652         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 653         * aarch64-dis-2.c: Regenerate.
 654
 655 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 656
 657         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 658         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 659         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 660         (FLD_SVE_prfop): Likewise.
 661         * aarch64-opc.c: Include libiberty.h.
 662         (aarch64_sve_pattern_array): New variable.
 663         (aarch64_sve_prfop_array): Likewise.
 664         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 665         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 666         AARCH64_OPND_SVE_PRFOP.
 667         * aarch64-asm-2.c: Regenerate.
 668         * aarch64-dis-2.c: Likewise.
 669         * aarch64-opc-2.c: Likewise.
 670
 671 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 672
 673         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 674         AARCH64_OPND_QLF_P_[ZM].
 675         (aarch64_print_operand): Print /z and /m where appropriate.
 676
 677 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 678
 679         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 680         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 681         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 682         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 683         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 684         * aarch64-opc.c (fields): Add corresponding entries here.
 685         (operand_general_constraint_met_p): Check that SVE register lists
 686         have the correct length.  Check the ranges of SVE index registers.
 687         Check for cases where p8-p15 are used in 3-bit predicate fields.
 688         (aarch64_print_operand): Handle the new SVE operands.
 689         * aarch64-opc-2.c: Regenerate.
 690         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 691         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 692         (aarch64_ins_sve_reglist): Likewise.
 693         * aarch64-asm-2.c: Regenerate.
 694         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 695         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 696         (aarch64_ext_sve_reglist): Likewise.
 697         * aarch64-dis-2.c: Regenerate.
 698
 699 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 700
 701         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 702         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 703         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 704         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 705         tied operands.
 706
 707 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 708
 709         * aarch64-opc.c (get_offset_int_reg_name): New function.
 710         (print_immediate_offset_address): Likewise.
 711         (print_register_offset_address): Take the base and offset
 712         registers as parameters.
 713         (aarch64_print_operand): Update caller accordingly.  Use
 714         print_immediate_offset_address.
 715
 716 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 717
 718         * aarch64-opc.c (BANK): New macro.
 719         (R32, R64): Take a register number as argument
 720         (int_reg): Use BANK.
 721
 722 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 723
 724         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 725         (aarch64_print_operand): Update accordingly.
 726
 727 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 728
 729         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 730         for FPIMM.
 731         * aarch64-asm.h (ins_fpimm): New inserter.
 732         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 733         * aarch64-asm-2.c: Regenerate.
 734         * aarch64-dis.h (ext_fpimm): New extractor.
 735         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 736         (aarch64_ext_fpimm): New function.
 737         * aarch64-dis-2.c: Regenerate.
 738
 739 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 740
 741         * aarch64-asm.c: Include libiberty.h.
 742         (insert_fields): New function.
 743         (aarch64_ins_imm): Use it.
 744         * aarch64-dis.c (extract_fields): New function.
 745         (aarch64_ext_imm): Use it.
 746
 747 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 748
 749         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 750         with an esize parameter.
 751         (operand_general_constraint_met_p): Update accordingly.
 752         Fix misindented code.
 753         * aarch64-asm.c (aarch64_ins_limm): Update call to
 754         aarch64_logical_immediate_p.
 755
 756 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 757
 758         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 759
 760 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 761
 762         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 763
 764 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 765
 766         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 767
 768 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 769
 770         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 771         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 772         xor3>: Delete mnemonics.
 773         <cp_abort>: Rename mnemonic from ...
 774         <cpabort>: ...to this.
 775         <setb>: Change to a X form instruction.
 776         <sync>: Change to 1 operand form.
 777         <copy>: Delete mnemonic.
 778         <copy_first>: Rename mnemonic from ...
 779         <copy>: ...to this.
 780         <paste, paste.>: Delete mnemonics.
 781         <paste_last>: Rename mnemonic from ...
 782         <paste.>: ...to this.
 783
 784 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 785
 786         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 787
 788 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 789
 790         * s390-mkopc.c (main): Support alternate arch strings.
 791
 792 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 793
 794         * s390-opc.txt: Fix kmctr instruction type.
 795
 796 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 797
 798         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 799         * i386-init.h: Regenerated.
 800
 801 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 802
 803         * opcodes/arc-dis.c (print_insn_arc): Changed.
 804
 805 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 806
 807         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 808         camellia_fl.
 809
 810 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 811
 812         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 813         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 814         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 815
 816 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 817
 818         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 819         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 820         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 821         PREFIX_MOD_3_0FAE_REG_4.
 822         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 823         PREFIX_MOD_3_0FAE_REG_4.
 824         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 825         (cpu_flags): Add CpuPTWRITE.
 826         * i386-opc.h (CpuPTWRITE): New.
 827         (i386_cpu_flags): Add cpuptwrite.
 828         * i386-opc.tbl: Add ptwrite instruction.
 829         * i386-init.h: Regenerated.
 830         * i386-tbl.h: Likewise.
 831
 832 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 833
 834         * arc-dis.h: Wrap around in extern "C".
 835
 836 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 837
 838         * aarch64-tbl.h (V8_2_INSN): New macro.
 839         (aarch64_opcode_table): Use it.
 840
 841 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 842
 843         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 844         CORE_INSN, __FP_INSN and SIMD_INSN.
 845
 846 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 847
 848         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 849         (aarch64_opcode_table): Update uses accordingly.
 850
 851 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 852         Kwok Cheung Yeung  <kcy@codesourcery.com>
 853
 854         opcodes/
 855         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 856         'e_cmplwi' to 'e_cmpli' instead.
 857         (OPVUPRT, OPVUPRT_MASK): Define.
 858         (powerpc_opcodes): Add E200Z4 insns.
 859         (vle_opcodes): Add context save/restore insns.
 860
 861 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 862
 863         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 864         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 865         "j".
 866
 867 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 868
 869         * arc-nps400-tbl.h: Change block comments to GNU format.
 870         * arc-dis.c: Add new globals addrtypenames,
 871         addrtypenames_max, and addtypeunknown.
 872         (get_addrtype): New function.
 873         (print_insn_arc): Print colons and address types when
 874         required.
 875         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 876         define insert and extract functions for all address types.
 877         (arc_operands): Add operands for colon and all address
 878         types.
 879         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 880         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 881         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 882         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 883         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 884         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 885
 886 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         * configure: Regenerated.
 889
 890 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 891
 892         * arc-dis.c (skipclass): New structure.
 893         (decodelist): New variable.
 894         (is_compatible_p): New function.
 895         (new_element): Likewise.
 896         (skip_class_p): Likewise.
 897         (find_format_from_table): Use skip_class_p function.
 898         (find_format): Decode first the extension instructions.
 899         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 900         e_flags.
 901         (parse_option): New function.
 902         (parse_disassembler_options): Likewise.
 903         (print_arc_disassembler_options): Likewise.
 904         (print_insn_arc): Use parse_disassembler_options function.  Proper
 905         select ARCv2 cpu variant.
 906         * disassemble.c (disassembler_usage): Add ARC disassembler
 907         options.
 908
 909 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 910
 911         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 912         annotation from the "nal" entry and reorder it beyond "bltzal".
 913
 914 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 915
 916         * sparc-opc.c (ldtxa): New macro.
 917         (sparc_opcodes): Use the macro defined above to add entries for
 918         the LDTXA instructions.
 919         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 920         instruction.
 921
 922 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 923
 924         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 925         and "jmpc".
 926
 927 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 930         (movzb): Adjust to cover all permitted suffixes.
 931         (movzw): New.
 932         * i386-tbl.h: Re-generate.
 933
 934 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 937         (lgdt): Remove Tbyte from non-64-bit variant.
 938         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 939         xsaves64, xsavec64): Remove Disp16.
 940         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 941         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 942         64-bit variants.
 943         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 944         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 945         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 946         64-bit variants.
 947         * i386-tbl.h: Re-generate.
 948
 949 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 950
 951         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 952         * i386-tbl.h: Re-generate.
 953
 954 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 955
 956         * arm-dis.c (print_insn): Fix typo in comment.
 957
 958 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 959
 960         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 961         range of ldst_elemlist operands.
 962         (print_register_list): Use PRIi64 to print the index.
 963         (aarch64_print_operand): Likewise.
 964
 965 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 966
 967         * mcore-opc.h: Remove sentinal.
 968         * mcore-dis.c (print_insn_mcore): Adjust.
 969
 970 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 971
 972         * arc-opc.c: Correct description of availability of NPS400
 973         features.
 974
 975 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 976
 977         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 978         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 979         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 980         xor3>: New mnemonics.
 981         <setb>: Change to a VX form instruction.
 982         (insert_sh6): Add support for rldixor.
 983         (extract_sh6): Likewise.
 984
 985 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 986
 987         * arc-ext.h: Wrap in extern C.
 988
 989 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 990
 991         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 992         Use same method for determining instruction length on ARC700 and
 993         NPS-400.
 994         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 995         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 996         with the NPS400 subclass.
 997         * arc-opc.c: Likewise.
 998
 999 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1000
1001         * sparc-opc.c (rdasr): New macro.
1002         (wrasr): Likewise.
1003         (rdpr): Likewise.
1004         (wrpr): Likewise.
1005         (rdhpr): Likewise.
1006         (wrhpr): Likewise.
1007         (sparc_opcodes): Use the macros above to fix and expand the
1008         definition of read/write instructions from/to
1009         asr/privileged/hyperprivileged instructions.
1010         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1011         %hva_mask_nz.  Prefer softint_set and softint_clear over
1012         set_softint and clear_softint.
1013         (print_insn_sparc): Support %ver in Rd.
1014
1015 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1016
1017         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1018         architecture according to the hardware capabilities they require.
1019
1020 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1021
1022         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1023         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1024         bfd_mach_sparc_v9{c,d,e,v,m}.
1025         * sparc-opc.c (MASK_V9C): Define.
1026         (MASK_V9D): Likewise.
1027         (MASK_V9E): Likewise.
1028         (MASK_V9V): Likewise.
1029         (MASK_V9M): Likewise.
1030         (v6): Add MASK_V9{C,D,E,V,M}.
1031         (v6notlet): Likewise.
1032         (v7): Likewise.
1033         (v8): Likewise.
1034         (v9): Likewise.
1035         (v9andleon): Likewise.
1036         (v9a): Likewise.
1037         (v9b): Likewise.
1038         (v9c): Define.
1039         (v9d): Likewise.
1040         (v9e): Likewise.
1041         (v9v): Likewise.
1042         (v9m): Likewise.
1043         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1044
1045 2016-06-15  Nick Clifton  <nickc@redhat.com>
1046
1047         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1048         constants to match expected behaviour.
1049         (nds32_parse_opcode): Likewise.  Also for whitespace.
1050
1051 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1052
1053         * arc-opc.c (extract_rhv1): Extract value from insn.
1054
1055 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1056
1057         * arc-nps400-tbl.h: Add ldbit instruction.
1058         * arc-opc.c: Add flag classes required for ldbit.
1059
1060 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1061
1062         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1063         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1064         support the above instructions.
1065
1066 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1067
1068         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1069         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1070         csma, cbba, zncv, and hofs.
1071         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1072         support the above instructions.
1073
1074 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1075
1076         * arc-nps400-tbl.h: Add andab and orab instructions.
1077
1078 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1079
1080         * arc-nps400-tbl.h: Add addl-like instructions.
1081
1082 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1083
1084         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1085
1086 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1087
1088         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1089         instructions.
1090
1091 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1092
1093         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1094         variable.
1095         (init_disasm): Handle new command line option "insnlength".
1096         (print_s390_disassembler_options): Mention new option in help
1097         output.
1098         (print_insn_s390): Use the encoded insn length when dumping
1099         unknown instructions.
1100
1101 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1102
1103         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1104          to the address and set as symbol address for LDS/ STS immediate operands.
1105
1106 2016-06-07  Alan Modra  <amodra@gmail.com>
1107
1108         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1109         cpu for "vle" to e500.
1110         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1111         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1112         (PPCNONE): Delete, substitute throughout.
1113         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1114         except for major opcode 4 and 31.
1115         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1116
1117 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1118
1119         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1120         ARM_EXT_RAS in relevant entries.
1121
1122 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1123
1124         PR binutils/20196
1125         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1126         opcodes for E6500.
1127
1128 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1129
1130         PR binutis/18386
1131         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1132         (indir_v_mode): New.
1133         Add comments for '&'.
1134         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1135         (putop): Handle '&'.
1136         (intel_operand_size): Handle indir_v_mode.
1137         (OP_E_register): Likewise.
1138         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1139         64-bit indirect call/jmp for AMD64.
1140         * i386-tbl.h: Regenerated
1141
1142 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1143
1144         * arc-dis.c (struct arc_operand_iterator): New structure.
1145         (find_format_from_table): All the old content from find_format,
1146         with some minor adjustments, and parameter renaming.
1147         (find_format_long_instructions): New function.
1148         (find_format): Rewritten.
1149         (arc_insn_length): Add LSB parameter.
1150         (extract_operand_value): New function.
1151         (operand_iterator_next): New function.
1152         (print_insn_arc): Use new functions to find opcode, and iterator
1153         over operands.
1154         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1155         (extract_nps_3bit_dst_short): New function.
1156         (insert_nps_3bit_src2_short): New function.
1157         (extract_nps_3bit_src2_short): New function.
1158         (insert_nps_bitop1_size): New function.
1159         (extract_nps_bitop1_size): New function.
1160         (insert_nps_bitop2_size): New function.
1161         (extract_nps_bitop2_size): New function.
1162         (insert_nps_bitop_mod4_msb): New function.
1163         (extract_nps_bitop_mod4_msb): New function.
1164         (insert_nps_bitop_mod4_lsb): New function.
1165         (extract_nps_bitop_mod4_lsb): New function.
1166         (insert_nps_bitop_dst_pos3_pos4): New function.
1167         (extract_nps_bitop_dst_pos3_pos4): New function.
1168         (insert_nps_bitop_ins_ext): New function.
1169         (extract_nps_bitop_ins_ext): New function.
1170         (arc_operands): Add new operands.
1171         (arc_long_opcodes): New global array.
1172         (arc_num_long_opcodes): New global.
1173         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1174
1175 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1176
1177         * nds32-asm.h: Add extern "C".
1178         * sh-opc.h: Likewise.
1179
1180 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1181
1182         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1183         0,b,limm to the rflt instruction.
1184
1185 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1186
1187         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1188         constant.
1189
1190 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1191
1192         PR gas/20145
1193         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1194         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1195         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1196         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1197         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1198         * i386-init.h: Regenerated.
1199
1200 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1201
1202         PR gas/20145
1203         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1204         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1205         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1206         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1207         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1208         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1209         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1210         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1211         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1212         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1213         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1214         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1215         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1216         CpuRegMask for AVX512.
1217         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1218         and CpuRegMask.
1219         (set_bitfield_from_cpu_flag_init): New function.
1220         (set_bitfield): Remove const on f.  Call
1221         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1222         * i386-opc.h (CpuRegMMX): New.
1223         (CpuRegXMM): Likewise.
1224         (CpuRegYMM): Likewise.
1225         (CpuRegZMM): Likewise.
1226         (CpuRegMask): Likewise.
1227         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1228         and cpuregmask.
1229         * i386-init.h: Regenerated.
1230         * i386-tbl.h: Likewise.
1231
1232 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1233
1234         PR gas/20154
1235         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1236         (opcode_modifiers): Add AMD64 and Intel64.
1237         (main): Properly verify CpuMax.
1238         * i386-opc.h (CpuAMD64): Removed.
1239         (CpuIntel64): Likewise.
1240         (CpuMax): Set to CpuNo64.
1241         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1242         (AMD64): New.
1243         (Intel64): Likewise.
1244         (i386_opcode_modifier): Add amd64 and intel64.
1245         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1246         on call and jmp.
1247         * i386-init.h: Regenerated.
1248         * i386-tbl.h: Likewise.
1249
1250 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1251
1252         PR gas/20154
1253         * i386-gen.c (main): Fail if CpuMax is incorrect.
1254         * i386-opc.h (CpuMax): Set to CpuIntel64.
1255         * i386-tbl.h: Regenerated.
1256
1257 2016-05-27  Nick Clifton  <nickc@redhat.com>
1258
1259         PR target/20150
1260         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1261         (msp430dis_opcode_unsigned): New function.
1262         (msp430dis_opcode_signed): New function.
1263         (msp430_singleoperand): Use the new opcode reading functions.
1264         Only disassenmble bytes if they were successfully read.
1265         (msp430_doubleoperand): Likewise.
1266         (msp430_branchinstr): Likewise.
1267         (msp430x_callx_instr): Likewise.
1268         (print_insn_msp430): Check that it is safe to read bytes before
1269         attempting disassembly.  Use the new opcode reading functions.
1270
1271 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1272
1273         * ppc-opc.c (CY): New define.  Document it.
1274         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1275
1276 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1277
1278         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1279         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1280         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1281         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1282         CPU_ANY_AVX_FLAGS.
1283         * i386-init.h: Regenerated.
1284
1285 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1286
1287         PR gas/20141
1288         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1289         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1290         * i386-init.h: Regenerated.
1291
1292 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1293
1294         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1295         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1296         * i386-init.h: Regenerated.
1297
1298 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1299
1300         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1301         information.
1302         (print_insn_arc): Set insn_type information.
1303         * arc-opc.c (C_CC): Add F_CLASS_COND.
1304         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1305         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1306         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1307         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1308         (brne, brne_s, jeq_s, jne_s): Likewise.
1309
1310 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1311
1312         * arc-tbl.h (neg): New instruction variant.
1313
1314 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1315
1316         * arc-dis.c (find_format, find_format, get_auxreg)
1317         (print_insn_arc): Changed.
1318         * arc-ext.h (INSERT_XOP): Likewise.
1319
1320 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1321
1322         * tic54x-dis.c (sprint_mmr): Adjust.
1323         * tic54x-opc.c: Likewise.
1324
1325 2016-05-19  Alan Modra  <amodra@gmail.com>
1326
1327         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1328
1329 2016-05-19  Alan Modra  <amodra@gmail.com>
1330
1331         * ppc-opc.c: Formatting.
1332         (NSISIGNOPT): Define.
1333         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1334
1335 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1336
1337         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1338         replacing references to `micromips_ase' throughout.
1339         (_print_insn_mips): Don't use file-level microMIPS annotation to
1340         determine the disassembly mode with the symbol table.
1341
1342 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1343
1344         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1345
1346 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1347
1348         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1349         mips64r6.
1350         * mips-opc.c (D34): New macro.
1351         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1352
1353 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1354
1355         * i386-dis.c (prefix_table): Add RDPID instruction.
1356         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1357         (cpu_flags): Add RDPID bitfield.
1358         * i386-opc.h (enum): Add RDPID element.
1359         (i386_cpu_flags): Add RDPID field.
1360         * i386-opc.tbl: Add RDPID instruction.
1361         * i386-init.h: Regenerate.
1362         * i386-tbl.h: Regenerate.
1363
1364 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1365
1366         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1367         branch type of a symbol.
1368         (print_insn): Likewise.
1369
1370 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1371
1372         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1373         Mainline Security Extensions instructions.
1374         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1375         Extensions instructions.
1376         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1377         instructions.
1378         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1379         special registers.
1380
1381 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1382
1383         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1384
1385 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1386
1387         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1388         (arcExtMap_genOpcode): Likewise.
1389         * arc-opc.c (arg_32bit_rc): Define new variable.
1390         (arg_32bit_u6): Likewise.
1391         (arg_32bit_limm): Likewise.
1392
1393 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1394
1395         * aarch64-gen.c (VERIFIER): Define.
1396         * aarch64-opc.c (VERIFIER): Define.
1397         (verify_ldpsw): Use static linkage.
1398         * aarch64-opc.h (verify_ldpsw): Remove.
1399         * aarch64-tbl.h: Use VERIFIER for verifiers.
1400
1401 2016-04-28  Nick Clifton  <nickc@redhat.com>
1402
1403         PR target/19722
1404         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1405         * aarch64-opc.c (verify_ldpsw): New function.
1406         * aarch64-opc.h (verify_ldpsw): New prototype.
1407         * aarch64-tbl.h: Add initialiser for verifier field.
1408         (LDPSW): Set verifier to verify_ldpsw.
1409
1410 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1411
1412         PR binutils/19983
1413         PR binutils/19984
1414         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1415         smaller than address size.
1416
1417 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1418
1419         * alpha-dis.c: Regenerate.
1420         * crx-dis.c: Likewise.
1421         * disassemble.c: Likewise.
1422         * epiphany-opc.c: Likewise.
1423         * fr30-opc.c: Likewise.
1424         * frv-opc.c: Likewise.
1425         * ip2k-opc.c: Likewise.
1426         * iq2000-opc.c: Likewise.
1427         * lm32-opc.c: Likewise.
1428         * lm32-opinst.c: Likewise.
1429         * m32c-opc.c: Likewise.
1430         * m32r-opc.c: Likewise.
1431         * m32r-opinst.c: Likewise.
1432         * mep-opc.c: Likewise.
1433         * mt-opc.c: Likewise.
1434         * or1k-opc.c: Likewise.
1435         * or1k-opinst.c: Likewise.
1436         * tic80-opc.c: Likewise.
1437         * xc16x-opc.c: Likewise.
1438         * xstormy16-opc.c: Likewise.
1439
1440 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1441
1442         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1443         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1444         calcsd, and calcxd instructions.
1445         * arc-opc.c (insert_nps_bitop_size): Delete.
1446         (extract_nps_bitop_size): Delete.
1447         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1448         (extract_nps_qcmp_m3): Define.
1449         (extract_nps_qcmp_m2): Define.
1450         (extract_nps_qcmp_m1): Define.
1451         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1452         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1453         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1454         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1455         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1456         NPS_QCMP_M3.
1457
1458 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1459
1460         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1461
1462 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1463
1464         * Makefile.in: Regenerated with automake 1.11.6.
1465         * aclocal.m4: Likewise.
1466
1467 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1468
1469         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1470         instructions.
1471         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1472         (extract_nps_cmem_uimm16): New function.
1473         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1474
1475 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1476
1477         * arc-dis.c (arc_insn_length): New function.
1478         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1479         (find_format): Change insnLen parameter to unsigned.
1480
1481 2016-04-13  Nick Clifton  <nickc@redhat.com>
1482
1483         PR target/19937
1484         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1485         the LD.B and LD.BU instructions.
1486
1487 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1488
1489         * arc-dis.c (find_format): Check for extension flags.
1490         (print_flags): New function.
1491         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1492         .extAuxRegister.
1493         * arc-ext.c (arcExtMap_coreRegName): Use
1494         LAST_EXTENSION_CORE_REGISTER.
1495         (arcExtMap_coreReadWrite): Likewise.
1496         (dump_ARC_extmap): Update printing.
1497         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1498         (arc_aux_regs): Add cpu field.
1499         * arc-regs.h: Add cpu field, lower case name aux registers.
1500
1501 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1502
1503         * arc-tbl.h: Add rtsc, sleep with no arguments.
1504
1505 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1506
1507         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1508         Initialize.
1509         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1510         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1511         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1512         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1513         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1514         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1515         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1516         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1517         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1518         (arc_opcode arc_opcodes): Null terminate the array.
1519         (arc_num_opcodes): Remove.
1520         * arc-ext.h (INSERT_XOP): Define.
1521         (extInstruction_t): Likewise.
1522         (arcExtMap_instName): Delete.
1523         (arcExtMap_insn): New function.
1524         (arcExtMap_genOpcode): Likewise.
1525         * arc-ext.c (ExtInstruction): Remove.
1526         (create_map): Zero initialize instruction fields.
1527         (arcExtMap_instName): Remove.
1528         (arcExtMap_insn): New function.
1529         (dump_ARC_extmap): More info while debuging.
1530         (arcExtMap_genOpcode): New function.
1531         * arc-dis.c (find_format): New function.
1532         (print_insn_arc): Use find_format.
1533         (arc_get_disassembler): Enable dump_ARC_extmap only when
1534         debugging.
1535
1536 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1537
1538         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1539         instruction bits out.
1540
1541 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1542
1543         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1544         * arc-opc.c (arc_flag_operands): Add new flags.
1545         (arc_flag_classes): Add new classes.
1546
1547 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1548
1549         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1550
1551 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1552
1553         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1554         encode1, rflt, crc16, and crc32 instructions.
1555         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1556         (arc_flag_classes): Add C_NPS_R.
1557         (insert_nps_bitop_size_2b): New function.
1558         (extract_nps_bitop_size_2b): Likewise.
1559         (insert_nps_bitop_uimm8): Likewise.
1560         (extract_nps_bitop_uimm8): Likewise.
1561         (arc_operands): Add new operand entries.
1562
1563 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1564
1565         * arc-regs.h: Add a new subclass field.  Add double assist
1566         accumulator register values.
1567         * arc-tbl.h: Use DPA subclass to mark the double assist
1568         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1569         * arc-opc.c (RSP): Define instead of SP.
1570         (arc_aux_regs): Add the subclass field.
1571
1572 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1573
1574         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1575
1576 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1577
1578         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1579         NPS_R_SRC1.
1580
1581 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1582
1583         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1584         issues.  No functional changes.
1585
1586 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1587
1588         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1589         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1590         (RTT): Remove duplicate.
1591         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1592         (PCT_CONFIG*): Remove.
1593         (D1L, D1H, D2H, D2L): Define.
1594
1595 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1596
1597         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1598
1599 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1600
1601         * arc-tbl.h (invld07): Remove.
1602         * arc-ext-tbl.h: New file.
1603         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1604         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1605
1606 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1607
1608         Fix -Wstack-usage warnings.
1609         * aarch64-dis.c (print_operands): Substitute size.
1610         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1611
1612 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1613
1614         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1615         to get a proper diagnostic when an invalid ASR register is used.
1616
1617 2016-03-22  Nick Clifton  <nickc@redhat.com>
1618
1619         * configure: Regenerate.
1620
1621 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1622
1623         * arc-nps400-tbl.h: New file.
1624         * arc-opc.c: Add top level comment.
1625         (insert_nps_3bit_dst): New function.
1626         (extract_nps_3bit_dst): New function.
1627         (insert_nps_3bit_src2): New function.
1628         (extract_nps_3bit_src2): New function.
1629         (insert_nps_bitop_size): New function.
1630         (extract_nps_bitop_size): New function.
1631         (arc_flag_operands): Add nps400 entries.
1632         (arc_flag_classes): Add nps400 entries.
1633         (arc_operands): Add nps400 entries.
1634         (arc_opcodes): Add nps400 include.
1635
1636 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1637
1638         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1639         the new class enum values.
1640
1641 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1642
1643         * arc-dis.c (print_insn_arc): Handle nps400.
1644
1645 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1646
1647         * arc-opc.c (BASE): Delete.
1648
1649 2016-03-18  Nick Clifton  <nickc@redhat.com>
1650
1651         PR target/19721
1652         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1653         of MOV insn that aliases an ORR insn.
1654
1655 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1656
1657         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1658
1659 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1660
1661         * mcore-opc.h: Add const qualifiers.
1662         * microblaze-opc.h (struct op_code_struct): Likewise.
1663         * sh-opc.h: Likewise.
1664         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1665         (tic4x_print_op): Likewise.
1666
1667 2016-03-02  Alan Modra  <amodra@gmail.com>
1668
1669         * or1k-desc.h: Regenerate.
1670         * fr30-ibld.c: Regenerate.
1671         * rl78-decode.c: Regenerate.
1672
1673 2016-03-01  Nick Clifton  <nickc@redhat.com>
1674
1675         PR target/19747
1676         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1677
1678 2016-02-24  Renlin Li  <renlin.li@arm.com>
1679
1680         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1681         (print_insn_coprocessor): Support fp16 instructions.
1682
1683 2016-02-24  Renlin Li  <renlin.li@arm.com>
1684
1685         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1686         vminnm, vrint(mpna).
1687
1688 2016-02-24  Renlin Li  <renlin.li@arm.com>
1689
1690         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1691         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1692
1693 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1694
1695         * i386-dis.c (print_insn): Parenthesize expression to prevent
1696         truncated addresses.
1697         (OP_J): Likewise.
1698
1699 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1700             Janek van Oirschot  <jvanoirs@synopsys.com>
1701
1702         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1703         variable.
1704
1705 2016-02-04  Nick Clifton  <nickc@redhat.com>
1706
1707         PR target/19561
1708         * msp430-dis.c (print_insn_msp430): Add a special case for
1709         decoding an RRC instruction with the ZC bit set in the extension
1710         word.
1711
1712 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1713
1714         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1715         * epiphany-ibld.c: Regenerate.
1716         * fr30-ibld.c: Regenerate.
1717         * frv-ibld.c: Regenerate.
1718         * ip2k-ibld.c: Regenerate.
1719         * iq2000-ibld.c: Regenerate.
1720         * lm32-ibld.c: Regenerate.
1721         * m32c-ibld.c: Regenerate.
1722         * m32r-ibld.c: Regenerate.
1723         * mep-ibld.c: Regenerate.
1724         * mt-ibld.c: Regenerate.
1725         * or1k-ibld.c: Regenerate.
1726         * xc16x-ibld.c: Regenerate.
1727         * xstormy16-ibld.c: Regenerate.
1728
1729 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1730
1731         * epiphany-dis.c: Regenerated from latest cpu files.
1732
1733 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1734
1735         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1736         test bit.
1737
1738 2016-01-25  Renlin Li  <renlin.li@arm.com>
1739
1740         * arm-dis.c (mapping_symbol_for_insn): New function.
1741         (find_ifthen_state): Call mapping_symbol_for_insn().
1742
1743 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1744
1745         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1746         of MSR UAO immediate operand.
1747
1748 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1749
1750         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1751         instruction support.
1752
1753 2016-01-17  Alan Modra  <amodra@gmail.com>
1754
1755         * configure: Regenerate.
1756
1757 2016-01-14  Nick Clifton  <nickc@redhat.com>
1758
1759         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1760         instructions that can support stack pointer operations.
1761         * rl78-decode.c: Regenerate.
1762         * rl78-dis.c: Fix display of stack pointer in MOVW based
1763         instructions.
1764
1765 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1766
1767         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1768         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1769         erxtatus_el1 and erxaddr_el1.
1770
1771 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1772
1773         * arm-dis.c (arm_opcodes): Add "esb".
1774         (thumb_opcodes): Likewise.
1775
1776 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1777
1778         * ppc-opc.c <xscmpnedp>: Delete.
1779         <xvcmpnedp>: Likewise.
1780         <xvcmpnedp.>: Likewise.
1781         <xvcmpnesp>: Likewise.
1782         <xvcmpnesp.>: Likewise.
1783
1784 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1785
1786         PR gas/13050
1787         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1788         addition to ISA_A.
1789
1790 2016-01-01  Alan Modra  <amodra@gmail.com>
1791
1792         Update year range in copyright notice of all files.
1793
1794 For older changes see ChangeLog-2015
1795 \f
1796 Copyright (C) 2016 Free Software Foundation, Inc.
1797
1798 Copying and distribution of this file, with or without modification,
1799 are permitted in any medium without royalty provided the copyright
1800 notice and this notice are preserved.
1801
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1803 mode: change-log
1804 left-margin: 8
1805 fill-column: 74
1806 version-control: never
1807 End: