opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Edqa { OP_E, dqa_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VCMP { VCMP_Fixup, 0 }
 445 #define VPCMP { VPCMP_Fixup, 0 }
 446 #define VPCOM { VPCOM_Fixup, 0 }
 447
 448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* operand size depends on the W bit as well as address mode.  */
 595   dqa_mode,
 596   /* normal vex mode */
 597   vex_mode,
 598   /* 128bit vex mode */
 599   vex128_mode,
 600   /* 256bit vex mode */
 601   vex256_mode,
 602   /* operand size depends on the VEX.W bit.  */
 603   vex_w_dq_mode,
 604
 605   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 606   vex_vsib_d_w_dq_mode,
 607   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 608   vex_vsib_d_w_d_mode,
 609   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 610   vex_vsib_q_w_dq_mode,
 611   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 612   vex_vsib_q_w_d_mode,
 613
 614   /* scalar, ignore vector length.  */
 615   scalar_mode,
 616   /* like b_mode, ignore vector length.  */
 617   b_scalar_mode,
 618   /* like w_mode, ignore vector length.  */
 619   w_scalar_mode,
 620   /* like d_mode, ignore vector length.  */
 621   d_scalar_mode,
 622   /* like d_swap_mode, ignore vector length.  */
 623   d_scalar_swap_mode,
 624   /* like q_mode, ignore vector length.  */
 625   q_scalar_mode,
 626   /* like q_swap_mode, ignore vector length.  */
 627   q_scalar_swap_mode,
 628   /* like vex_mode, ignore vector length.  */
 629   vex_scalar_mode,
 630   /* like vex_w_dq_mode, ignore vector length.  */
 631   vex_scalar_w_dq_mode,
 632
 633   /* Static rounding.  */
 634   evex_rounding_mode,
 635   /* Static rounding, 64-bit mode only.  */
 636   evex_rounding_64_mode,
 637   /* Supress all exceptions.  */
 638   evex_sae_mode,
 639
 640   /* Mask register operand.  */
 641   mask_mode,
 642   /* Mask register operand.  */
 643   mask_bd_mode,
 644
 645   es_reg,
 646   cs_reg,
 647   ss_reg,
 648   ds_reg,
 649   fs_reg,
 650   gs_reg,
 651
 652   eAX_reg,
 653   eCX_reg,
 654   eDX_reg,
 655   eBX_reg,
 656   eSP_reg,
 657   eBP_reg,
 658   eSI_reg,
 659   eDI_reg,
 660
 661   al_reg,
 662   cl_reg,
 663   dl_reg,
 664   bl_reg,
 665   ah_reg,
 666   ch_reg,
 667   dh_reg,
 668   bh_reg,
 669
 670   ax_reg,
 671   cx_reg,
 672   dx_reg,
 673   bx_reg,
 674   sp_reg,
 675   bp_reg,
 676   si_reg,
 677   di_reg,
 678
 679   rAX_reg,
 680   rCX_reg,
 681   rDX_reg,
 682   rBX_reg,
 683   rSP_reg,
 684   rBP_reg,
 685   rSI_reg,
 686   rDI_reg,
 687
 688   z_mode_ax_reg,
 689   indir_dx_reg
 690 };
 691
 692 enum
 693 {
 694   FLOATCODE = 1,
 695   USE_REG_TABLE,
 696   USE_MOD_TABLE,
 697   USE_RM_TABLE,
 698   USE_PREFIX_TABLE,
 699   USE_X86_64_TABLE,
 700   USE_3BYTE_TABLE,
 701   USE_XOP_8F_TABLE,
 702   USE_VEX_C4_TABLE,
 703   USE_VEX_C5_TABLE,
 704   USE_VEX_LEN_TABLE,
 705   USE_VEX_W_TABLE,
 706   USE_EVEX_TABLE,
 707   USE_EVEX_LEN_TABLE
 708 };
 709
 710 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 711
 712 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 713 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 714 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 715 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 716 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 717 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 718 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 719 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 720 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 721 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 722 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 723 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 724 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 725 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 726 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 727 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 728
 729 enum
 730 {
 731   REG_80 = 0,
 732   REG_81,
 733   REG_83,
 734   REG_8F,
 735   REG_C0,
 736   REG_C1,
 737   REG_C6,
 738   REG_C7,
 739   REG_D0,
 740   REG_D1,
 741   REG_D2,
 742   REG_D3,
 743   REG_F6,
 744   REG_F7,
 745   REG_FE,
 746   REG_FF,
 747   REG_0F00,
 748   REG_0F01,
 749   REG_0F0D,
 750   REG_0F18,
 751   REG_0F1C_MOD_0,
 752   REG_0F1E_MOD_3,
 753   REG_0F71,
 754   REG_0F72,
 755   REG_0F73,
 756   REG_0FA6,
 757   REG_0FA7,
 758   REG_0FAE,
 759   REG_0FBA,
 760   REG_0FC7,
 761   REG_VEX_0F71,
 762   REG_VEX_0F72,
 763   REG_VEX_0F73,
 764   REG_VEX_0FAE,
 765   REG_VEX_0F38F3,
 766   REG_XOP_LWPCB,
 767   REG_XOP_LWP,
 768   REG_XOP_TBM_01,
 769   REG_XOP_TBM_02,
 770
 771   REG_EVEX_0F71,
 772   REG_EVEX_0F72,
 773   REG_EVEX_0F73,
 774   REG_EVEX_0F38C6,
 775   REG_EVEX_0F38C7
 776 };
 777
 778 enum
 779 {
 780   MOD_8D = 0,
 781   MOD_C6_REG_7,
 782   MOD_C7_REG_7,
 783   MOD_FF_REG_3,
 784   MOD_FF_REG_5,
 785   MOD_0F01_REG_0,
 786   MOD_0F01_REG_1,
 787   MOD_0F01_REG_2,
 788   MOD_0F01_REG_3,
 789   MOD_0F01_REG_5,
 790   MOD_0F01_REG_7,
 791   MOD_0F12_PREFIX_0,
 792   MOD_0F13,
 793   MOD_0F16_PREFIX_0,
 794   MOD_0F17,
 795   MOD_0F18_REG_0,
 796   MOD_0F18_REG_1,
 797   MOD_0F18_REG_2,
 798   MOD_0F18_REG_3,
 799   MOD_0F18_REG_4,
 800   MOD_0F18_REG_5,
 801   MOD_0F18_REG_6,
 802   MOD_0F18_REG_7,
 803   MOD_0F1A_PREFIX_0,
 804   MOD_0F1B_PREFIX_0,
 805   MOD_0F1B_PREFIX_1,
 806   MOD_0F1C_PREFIX_0,
 807   MOD_0F1E_PREFIX_1,
 808   MOD_0F24,
 809   MOD_0F26,
 810   MOD_0F2B_PREFIX_0,
 811   MOD_0F2B_PREFIX_1,
 812   MOD_0F2B_PREFIX_2,
 813   MOD_0F2B_PREFIX_3,
 814   MOD_0F51,
 815   MOD_0F71_REG_2,
 816   MOD_0F71_REG_4,
 817   MOD_0F71_REG_6,
 818   MOD_0F72_REG_2,
 819   MOD_0F72_REG_4,
 820   MOD_0F72_REG_6,
 821   MOD_0F73_REG_2,
 822   MOD_0F73_REG_3,
 823   MOD_0F73_REG_6,
 824   MOD_0F73_REG_7,
 825   MOD_0FAE_REG_0,
 826   MOD_0FAE_REG_1,
 827   MOD_0FAE_REG_2,
 828   MOD_0FAE_REG_3,
 829   MOD_0FAE_REG_4,
 830   MOD_0FAE_REG_5,
 831   MOD_0FAE_REG_6,
 832   MOD_0FAE_REG_7,
 833   MOD_0FB2,
 834   MOD_0FB4,
 835   MOD_0FB5,
 836   MOD_0FC3,
 837   MOD_0FC7_REG_3,
 838   MOD_0FC7_REG_4,
 839   MOD_0FC7_REG_5,
 840   MOD_0FC7_REG_6,
 841   MOD_0FC7_REG_7,
 842   MOD_0FD7,
 843   MOD_0FE7_PREFIX_2,
 844   MOD_0FF0_PREFIX_3,
 845   MOD_0F382A_PREFIX_2,
 846   MOD_0F38F5_PREFIX_2,
 847   MOD_0F38F6_PREFIX_0,
 848   MOD_0F38F8_PREFIX_2,
 849   MOD_0F38F9_PREFIX_0,
 850   MOD_62_32BIT,
 851   MOD_C4_32BIT,
 852   MOD_C5_32BIT,
 853   MOD_VEX_0F12_PREFIX_0,
 854   MOD_VEX_0F13,
 855   MOD_VEX_0F16_PREFIX_0,
 856   MOD_VEX_0F17,
 857   MOD_VEX_0F2B,
 858   MOD_VEX_W_0_0F41_P_0_LEN_1,
 859   MOD_VEX_W_1_0F41_P_0_LEN_1,
 860   MOD_VEX_W_0_0F41_P_2_LEN_1,
 861   MOD_VEX_W_1_0F41_P_2_LEN_1,
 862   MOD_VEX_W_0_0F42_P_0_LEN_1,
 863   MOD_VEX_W_1_0F42_P_0_LEN_1,
 864   MOD_VEX_W_0_0F42_P_2_LEN_1,
 865   MOD_VEX_W_1_0F42_P_2_LEN_1,
 866   MOD_VEX_W_0_0F44_P_0_LEN_1,
 867   MOD_VEX_W_1_0F44_P_0_LEN_1,
 868   MOD_VEX_W_0_0F44_P_2_LEN_1,
 869   MOD_VEX_W_1_0F44_P_2_LEN_1,
 870   MOD_VEX_W_0_0F45_P_0_LEN_1,
 871   MOD_VEX_W_1_0F45_P_0_LEN_1,
 872   MOD_VEX_W_0_0F45_P_2_LEN_1,
 873   MOD_VEX_W_1_0F45_P_2_LEN_1,
 874   MOD_VEX_W_0_0F46_P_0_LEN_1,
 875   MOD_VEX_W_1_0F46_P_0_LEN_1,
 876   MOD_VEX_W_0_0F46_P_2_LEN_1,
 877   MOD_VEX_W_1_0F46_P_2_LEN_1,
 878   MOD_VEX_W_0_0F47_P_0_LEN_1,
 879   MOD_VEX_W_1_0F47_P_0_LEN_1,
 880   MOD_VEX_W_0_0F47_P_2_LEN_1,
 881   MOD_VEX_W_1_0F47_P_2_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 884   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 885   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 887   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 888   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 889   MOD_VEX_0F50,
 890   MOD_VEX_0F71_REG_2,
 891   MOD_VEX_0F71_REG_4,
 892   MOD_VEX_0F71_REG_6,
 893   MOD_VEX_0F72_REG_2,
 894   MOD_VEX_0F72_REG_4,
 895   MOD_VEX_0F72_REG_6,
 896   MOD_VEX_0F73_REG_2,
 897   MOD_VEX_0F73_REG_3,
 898   MOD_VEX_0F73_REG_6,
 899   MOD_VEX_0F73_REG_7,
 900   MOD_VEX_W_0_0F91_P_0_LEN_0,
 901   MOD_VEX_W_1_0F91_P_0_LEN_0,
 902   MOD_VEX_W_0_0F91_P_2_LEN_0,
 903   MOD_VEX_W_1_0F91_P_2_LEN_0,
 904   MOD_VEX_W_0_0F92_P_0_LEN_0,
 905   MOD_VEX_W_0_0F92_P_2_LEN_0,
 906   MOD_VEX_W_0_0F92_P_3_LEN_0,
 907   MOD_VEX_W_1_0F92_P_3_LEN_0,
 908   MOD_VEX_W_0_0F93_P_0_LEN_0,
 909   MOD_VEX_W_0_0F93_P_2_LEN_0,
 910   MOD_VEX_W_0_0F93_P_3_LEN_0,
 911   MOD_VEX_W_1_0F93_P_3_LEN_0,
 912   MOD_VEX_W_0_0F98_P_0_LEN_0,
 913   MOD_VEX_W_1_0F98_P_0_LEN_0,
 914   MOD_VEX_W_0_0F98_P_2_LEN_0,
 915   MOD_VEX_W_1_0F98_P_2_LEN_0,
 916   MOD_VEX_W_0_0F99_P_0_LEN_0,
 917   MOD_VEX_W_1_0F99_P_0_LEN_0,
 918   MOD_VEX_W_0_0F99_P_2_LEN_0,
 919   MOD_VEX_W_1_0F99_P_2_LEN_0,
 920   MOD_VEX_0FAE_REG_2,
 921   MOD_VEX_0FAE_REG_3,
 922   MOD_VEX_0FD7_PREFIX_2,
 923   MOD_VEX_0FE7_PREFIX_2,
 924   MOD_VEX_0FF0_PREFIX_3,
 925   MOD_VEX_0F381A_PREFIX_2,
 926   MOD_VEX_0F382A_PREFIX_2,
 927   MOD_VEX_0F382C_PREFIX_2,
 928   MOD_VEX_0F382D_PREFIX_2,
 929   MOD_VEX_0F382E_PREFIX_2,
 930   MOD_VEX_0F382F_PREFIX_2,
 931   MOD_VEX_0F385A_PREFIX_2,
 932   MOD_VEX_0F388C_PREFIX_2,
 933   MOD_VEX_0F388E_PREFIX_2,
 934   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 938   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 939   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 940   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 941   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 942
 943   MOD_EVEX_0F10_PREFIX_1,
 944   MOD_EVEX_0F10_PREFIX_3,
 945   MOD_EVEX_0F11_PREFIX_1,
 946   MOD_EVEX_0F11_PREFIX_3,
 947   MOD_EVEX_0F12_PREFIX_0,
 948   MOD_EVEX_0F16_PREFIX_0,
 949   MOD_EVEX_0F38C6_REG_1,
 950   MOD_EVEX_0F38C6_REG_2,
 951   MOD_EVEX_0F38C6_REG_5,
 952   MOD_EVEX_0F38C6_REG_6,
 953   MOD_EVEX_0F38C7_REG_1,
 954   MOD_EVEX_0F38C7_REG_2,
 955   MOD_EVEX_0F38C7_REG_5,
 956   MOD_EVEX_0F38C7_REG_6
 957 };
 958
 959 enum
 960 {
 961   RM_C6_REG_7 = 0,
 962   RM_C7_REG_7,
 963   RM_0F01_REG_0,
 964   RM_0F01_REG_1,
 965   RM_0F01_REG_2,
 966   RM_0F01_REG_3,
 967   RM_0F01_REG_5,
 968   RM_0F01_REG_7,
 969   RM_0F1E_MOD_3_REG_7,
 970   RM_0FAE_REG_6,
 971   RM_0FAE_REG_7
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_MOD_0_0F01_REG_5,
 978   PREFIX_MOD_3_0F01_REG_5_RM_0,
 979   PREFIX_MOD_3_0F01_REG_5_RM_2,
 980   PREFIX_0F09,
 981   PREFIX_0F10,
 982   PREFIX_0F11,
 983   PREFIX_0F12,
 984   PREFIX_0F16,
 985   PREFIX_0F1A,
 986   PREFIX_0F1B,
 987   PREFIX_0F1C,
 988   PREFIX_0F1E,
 989   PREFIX_0F2A,
 990   PREFIX_0F2B,
 991   PREFIX_0F2C,
 992   PREFIX_0F2D,
 993   PREFIX_0F2E,
 994   PREFIX_0F2F,
 995   PREFIX_0F51,
 996   PREFIX_0F52,
 997   PREFIX_0F53,
 998   PREFIX_0F58,
 999   PREFIX_0F59,
1000   PREFIX_0F5A,
1001   PREFIX_0F5B,
1002   PREFIX_0F5C,
1003   PREFIX_0F5D,
1004   PREFIX_0F5E,
1005   PREFIX_0F5F,
1006   PREFIX_0F60,
1007   PREFIX_0F61,
1008   PREFIX_0F62,
1009   PREFIX_0F6C,
1010   PREFIX_0F6D,
1011   PREFIX_0F6F,
1012   PREFIX_0F70,
1013   PREFIX_0F73_REG_3,
1014   PREFIX_0F73_REG_7,
1015   PREFIX_0F78,
1016   PREFIX_0F79,
1017   PREFIX_0F7C,
1018   PREFIX_0F7D,
1019   PREFIX_0F7E,
1020   PREFIX_0F7F,
1021   PREFIX_0FAE_REG_0,
1022   PREFIX_0FAE_REG_1,
1023   PREFIX_0FAE_REG_2,
1024   PREFIX_0FAE_REG_3,
1025   PREFIX_MOD_0_0FAE_REG_4,
1026   PREFIX_MOD_3_0FAE_REG_4,
1027   PREFIX_MOD_0_0FAE_REG_5,
1028   PREFIX_MOD_3_0FAE_REG_5,
1029   PREFIX_MOD_0_0FAE_REG_6,
1030   PREFIX_MOD_1_0FAE_REG_6,
1031   PREFIX_0FAE_REG_7,
1032   PREFIX_0FB8,
1033   PREFIX_0FBC,
1034   PREFIX_0FBD,
1035   PREFIX_0FC2,
1036   PREFIX_MOD_0_0FC3,
1037   PREFIX_MOD_0_0FC7_REG_6,
1038   PREFIX_MOD_3_0FC7_REG_6,
1039   PREFIX_MOD_3_0FC7_REG_7,
1040   PREFIX_0FD0,
1041   PREFIX_0FD6,
1042   PREFIX_0FE6,
1043   PREFIX_0FE7,
1044   PREFIX_0FF0,
1045   PREFIX_0FF7,
1046   PREFIX_0F3810,
1047   PREFIX_0F3814,
1048   PREFIX_0F3815,
1049   PREFIX_0F3817,
1050   PREFIX_0F3820,
1051   PREFIX_0F3821,
1052   PREFIX_0F3822,
1053   PREFIX_0F3823,
1054   PREFIX_0F3824,
1055   PREFIX_0F3825,
1056   PREFIX_0F3828,
1057   PREFIX_0F3829,
1058   PREFIX_0F382A,
1059   PREFIX_0F382B,
1060   PREFIX_0F3830,
1061   PREFIX_0F3831,
1062   PREFIX_0F3832,
1063   PREFIX_0F3833,
1064   PREFIX_0F3834,
1065   PREFIX_0F3835,
1066   PREFIX_0F3837,
1067   PREFIX_0F3838,
1068   PREFIX_0F3839,
1069   PREFIX_0F383A,
1070   PREFIX_0F383B,
1071   PREFIX_0F383C,
1072   PREFIX_0F383D,
1073   PREFIX_0F383E,
1074   PREFIX_0F383F,
1075   PREFIX_0F3840,
1076   PREFIX_0F3841,
1077   PREFIX_0F3880,
1078   PREFIX_0F3881,
1079   PREFIX_0F3882,
1080   PREFIX_0F38C8,
1081   PREFIX_0F38C9,
1082   PREFIX_0F38CA,
1083   PREFIX_0F38CB,
1084   PREFIX_0F38CC,
1085   PREFIX_0F38CD,
1086   PREFIX_0F38CF,
1087   PREFIX_0F38DB,
1088   PREFIX_0F38DC,
1089   PREFIX_0F38DD,
1090   PREFIX_0F38DE,
1091   PREFIX_0F38DF,
1092   PREFIX_0F38F0,
1093   PREFIX_0F38F1,
1094   PREFIX_0F38F5,
1095   PREFIX_0F38F6,
1096   PREFIX_0F38F8,
1097   PREFIX_0F38F9,
1098   PREFIX_0F3A08,
1099   PREFIX_0F3A09,
1100   PREFIX_0F3A0A,
1101   PREFIX_0F3A0B,
1102   PREFIX_0F3A0C,
1103   PREFIX_0F3A0D,
1104   PREFIX_0F3A0E,
1105   PREFIX_0F3A14,
1106   PREFIX_0F3A15,
1107   PREFIX_0F3A16,
1108   PREFIX_0F3A17,
1109   PREFIX_0F3A20,
1110   PREFIX_0F3A21,
1111   PREFIX_0F3A22,
1112   PREFIX_0F3A40,
1113   PREFIX_0F3A41,
1114   PREFIX_0F3A42,
1115   PREFIX_0F3A44,
1116   PREFIX_0F3A60,
1117   PREFIX_0F3A61,
1118   PREFIX_0F3A62,
1119   PREFIX_0F3A63,
1120   PREFIX_0F3ACC,
1121   PREFIX_0F3ACE,
1122   PREFIX_0F3ACF,
1123   PREFIX_0F3ADF,
1124   PREFIX_VEX_0F10,
1125   PREFIX_VEX_0F11,
1126   PREFIX_VEX_0F12,
1127   PREFIX_VEX_0F16,
1128   PREFIX_VEX_0F2A,
1129   PREFIX_VEX_0F2C,
1130   PREFIX_VEX_0F2D,
1131   PREFIX_VEX_0F2E,
1132   PREFIX_VEX_0F2F,
1133   PREFIX_VEX_0F41,
1134   PREFIX_VEX_0F42,
1135   PREFIX_VEX_0F44,
1136   PREFIX_VEX_0F45,
1137   PREFIX_VEX_0F46,
1138   PREFIX_VEX_0F47,
1139   PREFIX_VEX_0F4A,
1140   PREFIX_VEX_0F4B,
1141   PREFIX_VEX_0F51,
1142   PREFIX_VEX_0F52,
1143   PREFIX_VEX_0F53,
1144   PREFIX_VEX_0F58,
1145   PREFIX_VEX_0F59,
1146   PREFIX_VEX_0F5A,
1147   PREFIX_VEX_0F5B,
1148   PREFIX_VEX_0F5C,
1149   PREFIX_VEX_0F5D,
1150   PREFIX_VEX_0F5E,
1151   PREFIX_VEX_0F5F,
1152   PREFIX_VEX_0F60,
1153   PREFIX_VEX_0F61,
1154   PREFIX_VEX_0F62,
1155   PREFIX_VEX_0F63,
1156   PREFIX_VEX_0F64,
1157   PREFIX_VEX_0F65,
1158   PREFIX_VEX_0F66,
1159   PREFIX_VEX_0F67,
1160   PREFIX_VEX_0F68,
1161   PREFIX_VEX_0F69,
1162   PREFIX_VEX_0F6A,
1163   PREFIX_VEX_0F6B,
1164   PREFIX_VEX_0F6C,
1165   PREFIX_VEX_0F6D,
1166   PREFIX_VEX_0F6E,
1167   PREFIX_VEX_0F6F,
1168   PREFIX_VEX_0F70,
1169   PREFIX_VEX_0F71_REG_2,
1170   PREFIX_VEX_0F71_REG_4,
1171   PREFIX_VEX_0F71_REG_6,
1172   PREFIX_VEX_0F72_REG_2,
1173   PREFIX_VEX_0F72_REG_4,
1174   PREFIX_VEX_0F72_REG_6,
1175   PREFIX_VEX_0F73_REG_2,
1176   PREFIX_VEX_0F73_REG_3,
1177   PREFIX_VEX_0F73_REG_6,
1178   PREFIX_VEX_0F73_REG_7,
1179   PREFIX_VEX_0F74,
1180   PREFIX_VEX_0F75,
1181   PREFIX_VEX_0F76,
1182   PREFIX_VEX_0F77,
1183   PREFIX_VEX_0F7C,
1184   PREFIX_VEX_0F7D,
1185   PREFIX_VEX_0F7E,
1186   PREFIX_VEX_0F7F,
1187   PREFIX_VEX_0F90,
1188   PREFIX_VEX_0F91,
1189   PREFIX_VEX_0F92,
1190   PREFIX_VEX_0F93,
1191   PREFIX_VEX_0F98,
1192   PREFIX_VEX_0F99,
1193   PREFIX_VEX_0FC2,
1194   PREFIX_VEX_0FC4,
1195   PREFIX_VEX_0FC5,
1196   PREFIX_VEX_0FD0,
1197   PREFIX_VEX_0FD1,
1198   PREFIX_VEX_0FD2,
1199   PREFIX_VEX_0FD3,
1200   PREFIX_VEX_0FD4,
1201   PREFIX_VEX_0FD5,
1202   PREFIX_VEX_0FD6,
1203   PREFIX_VEX_0FD7,
1204   PREFIX_VEX_0FD8,
1205   PREFIX_VEX_0FD9,
1206   PREFIX_VEX_0FDA,
1207   PREFIX_VEX_0FDB,
1208   PREFIX_VEX_0FDC,
1209   PREFIX_VEX_0FDD,
1210   PREFIX_VEX_0FDE,
1211   PREFIX_VEX_0FDF,
1212   PREFIX_VEX_0FE0,
1213   PREFIX_VEX_0FE1,
1214   PREFIX_VEX_0FE2,
1215   PREFIX_VEX_0FE3,
1216   PREFIX_VEX_0FE4,
1217   PREFIX_VEX_0FE5,
1218   PREFIX_VEX_0FE6,
1219   PREFIX_VEX_0FE7,
1220   PREFIX_VEX_0FE8,
1221   PREFIX_VEX_0FE9,
1222   PREFIX_VEX_0FEA,
1223   PREFIX_VEX_0FEB,
1224   PREFIX_VEX_0FEC,
1225   PREFIX_VEX_0FED,
1226   PREFIX_VEX_0FEE,
1227   PREFIX_VEX_0FEF,
1228   PREFIX_VEX_0FF0,
1229   PREFIX_VEX_0FF1,
1230   PREFIX_VEX_0FF2,
1231   PREFIX_VEX_0FF3,
1232   PREFIX_VEX_0FF4,
1233   PREFIX_VEX_0FF5,
1234   PREFIX_VEX_0FF6,
1235   PREFIX_VEX_0FF7,
1236   PREFIX_VEX_0FF8,
1237   PREFIX_VEX_0FF9,
1238   PREFIX_VEX_0FFA,
1239   PREFIX_VEX_0FFB,
1240   PREFIX_VEX_0FFC,
1241   PREFIX_VEX_0FFD,
1242   PREFIX_VEX_0FFE,
1243   PREFIX_VEX_0F3800,
1244   PREFIX_VEX_0F3801,
1245   PREFIX_VEX_0F3802,
1246   PREFIX_VEX_0F3803,
1247   PREFIX_VEX_0F3804,
1248   PREFIX_VEX_0F3805,
1249   PREFIX_VEX_0F3806,
1250   PREFIX_VEX_0F3807,
1251   PREFIX_VEX_0F3808,
1252   PREFIX_VEX_0F3809,
1253   PREFIX_VEX_0F380A,
1254   PREFIX_VEX_0F380B,
1255   PREFIX_VEX_0F380C,
1256   PREFIX_VEX_0F380D,
1257   PREFIX_VEX_0F380E,
1258   PREFIX_VEX_0F380F,
1259   PREFIX_VEX_0F3813,
1260   PREFIX_VEX_0F3816,
1261   PREFIX_VEX_0F3817,
1262   PREFIX_VEX_0F3818,
1263   PREFIX_VEX_0F3819,
1264   PREFIX_VEX_0F381A,
1265   PREFIX_VEX_0F381C,
1266   PREFIX_VEX_0F381D,
1267   PREFIX_VEX_0F381E,
1268   PREFIX_VEX_0F3820,
1269   PREFIX_VEX_0F3821,
1270   PREFIX_VEX_0F3822,
1271   PREFIX_VEX_0F3823,
1272   PREFIX_VEX_0F3824,
1273   PREFIX_VEX_0F3825,
1274   PREFIX_VEX_0F3828,
1275   PREFIX_VEX_0F3829,
1276   PREFIX_VEX_0F382A,
1277   PREFIX_VEX_0F382B,
1278   PREFIX_VEX_0F382C,
1279   PREFIX_VEX_0F382D,
1280   PREFIX_VEX_0F382E,
1281   PREFIX_VEX_0F382F,
1282   PREFIX_VEX_0F3830,
1283   PREFIX_VEX_0F3831,
1284   PREFIX_VEX_0F3832,
1285   PREFIX_VEX_0F3833,
1286   PREFIX_VEX_0F3834,
1287   PREFIX_VEX_0F3835,
1288   PREFIX_VEX_0F3836,
1289   PREFIX_VEX_0F3837,
1290   PREFIX_VEX_0F3838,
1291   PREFIX_VEX_0F3839,
1292   PREFIX_VEX_0F383A,
1293   PREFIX_VEX_0F383B,
1294   PREFIX_VEX_0F383C,
1295   PREFIX_VEX_0F383D,
1296   PREFIX_VEX_0F383E,
1297   PREFIX_VEX_0F383F,
1298   PREFIX_VEX_0F3840,
1299   PREFIX_VEX_0F3841,
1300   PREFIX_VEX_0F3845,
1301   PREFIX_VEX_0F3846,
1302   PREFIX_VEX_0F3847,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F3878,
1307   PREFIX_VEX_0F3879,
1308   PREFIX_VEX_0F388C,
1309   PREFIX_VEX_0F388E,
1310   PREFIX_VEX_0F3890,
1311   PREFIX_VEX_0F3891,
1312   PREFIX_VEX_0F3892,
1313   PREFIX_VEX_0F3893,
1314   PREFIX_VEX_0F3896,
1315   PREFIX_VEX_0F3897,
1316   PREFIX_VEX_0F3898,
1317   PREFIX_VEX_0F3899,
1318   PREFIX_VEX_0F389A,
1319   PREFIX_VEX_0F389B,
1320   PREFIX_VEX_0F389C,
1321   PREFIX_VEX_0F389D,
1322   PREFIX_VEX_0F389E,
1323   PREFIX_VEX_0F389F,
1324   PREFIX_VEX_0F38A6,
1325   PREFIX_VEX_0F38A7,
1326   PREFIX_VEX_0F38A8,
1327   PREFIX_VEX_0F38A9,
1328   PREFIX_VEX_0F38AA,
1329   PREFIX_VEX_0F38AB,
1330   PREFIX_VEX_0F38AC,
1331   PREFIX_VEX_0F38AD,
1332   PREFIX_VEX_0F38AE,
1333   PREFIX_VEX_0F38AF,
1334   PREFIX_VEX_0F38B6,
1335   PREFIX_VEX_0F38B7,
1336   PREFIX_VEX_0F38B8,
1337   PREFIX_VEX_0F38B9,
1338   PREFIX_VEX_0F38BA,
1339   PREFIX_VEX_0F38BB,
1340   PREFIX_VEX_0F38BC,
1341   PREFIX_VEX_0F38BD,
1342   PREFIX_VEX_0F38BE,
1343   PREFIX_VEX_0F38BF,
1344   PREFIX_VEX_0F38CF,
1345   PREFIX_VEX_0F38DB,
1346   PREFIX_VEX_0F38DC,
1347   PREFIX_VEX_0F38DD,
1348   PREFIX_VEX_0F38DE,
1349   PREFIX_VEX_0F38DF,
1350   PREFIX_VEX_0F38F2,
1351   PREFIX_VEX_0F38F3_REG_1,
1352   PREFIX_VEX_0F38F3_REG_2,
1353   PREFIX_VEX_0F38F3_REG_3,
1354   PREFIX_VEX_0F38F5,
1355   PREFIX_VEX_0F38F6,
1356   PREFIX_VEX_0F38F7,
1357   PREFIX_VEX_0F3A00,
1358   PREFIX_VEX_0F3A01,
1359   PREFIX_VEX_0F3A02,
1360   PREFIX_VEX_0F3A04,
1361   PREFIX_VEX_0F3A05,
1362   PREFIX_VEX_0F3A06,
1363   PREFIX_VEX_0F3A08,
1364   PREFIX_VEX_0F3A09,
1365   PREFIX_VEX_0F3A0A,
1366   PREFIX_VEX_0F3A0B,
1367   PREFIX_VEX_0F3A0C,
1368   PREFIX_VEX_0F3A0D,
1369   PREFIX_VEX_0F3A0E,
1370   PREFIX_VEX_0F3A0F,
1371   PREFIX_VEX_0F3A14,
1372   PREFIX_VEX_0F3A15,
1373   PREFIX_VEX_0F3A16,
1374   PREFIX_VEX_0F3A17,
1375   PREFIX_VEX_0F3A18,
1376   PREFIX_VEX_0F3A19,
1377   PREFIX_VEX_0F3A1D,
1378   PREFIX_VEX_0F3A20,
1379   PREFIX_VEX_0F3A21,
1380   PREFIX_VEX_0F3A22,
1381   PREFIX_VEX_0F3A30,
1382   PREFIX_VEX_0F3A31,
1383   PREFIX_VEX_0F3A32,
1384   PREFIX_VEX_0F3A33,
1385   PREFIX_VEX_0F3A38,
1386   PREFIX_VEX_0F3A39,
1387   PREFIX_VEX_0F3A40,
1388   PREFIX_VEX_0F3A41,
1389   PREFIX_VEX_0F3A42,
1390   PREFIX_VEX_0F3A44,
1391   PREFIX_VEX_0F3A46,
1392   PREFIX_VEX_0F3A48,
1393   PREFIX_VEX_0F3A49,
1394   PREFIX_VEX_0F3A4A,
1395   PREFIX_VEX_0F3A4B,
1396   PREFIX_VEX_0F3A4C,
1397   PREFIX_VEX_0F3A5C,
1398   PREFIX_VEX_0F3A5D,
1399   PREFIX_VEX_0F3A5E,
1400   PREFIX_VEX_0F3A5F,
1401   PREFIX_VEX_0F3A60,
1402   PREFIX_VEX_0F3A61,
1403   PREFIX_VEX_0F3A62,
1404   PREFIX_VEX_0F3A63,
1405   PREFIX_VEX_0F3A68,
1406   PREFIX_VEX_0F3A69,
1407   PREFIX_VEX_0F3A6A,
1408   PREFIX_VEX_0F3A6B,
1409   PREFIX_VEX_0F3A6C,
1410   PREFIX_VEX_0F3A6D,
1411   PREFIX_VEX_0F3A6E,
1412   PREFIX_VEX_0F3A6F,
1413   PREFIX_VEX_0F3A78,
1414   PREFIX_VEX_0F3A79,
1415   PREFIX_VEX_0F3A7A,
1416   PREFIX_VEX_0F3A7B,
1417   PREFIX_VEX_0F3A7C,
1418   PREFIX_VEX_0F3A7D,
1419   PREFIX_VEX_0F3A7E,
1420   PREFIX_VEX_0F3A7F,
1421   PREFIX_VEX_0F3ACE,
1422   PREFIX_VEX_0F3ACF,
1423   PREFIX_VEX_0F3ADF,
1424   PREFIX_VEX_0F3AF0,
1425
1426   PREFIX_EVEX_0F10,
1427   PREFIX_EVEX_0F11,
1428   PREFIX_EVEX_0F12,
1429   PREFIX_EVEX_0F13,
1430   PREFIX_EVEX_0F14,
1431   PREFIX_EVEX_0F15,
1432   PREFIX_EVEX_0F16,
1433   PREFIX_EVEX_0F17,
1434   PREFIX_EVEX_0F28,
1435   PREFIX_EVEX_0F29,
1436   PREFIX_EVEX_0F2A,
1437   PREFIX_EVEX_0F2B,
1438   PREFIX_EVEX_0F2C,
1439   PREFIX_EVEX_0F2D,
1440   PREFIX_EVEX_0F2E,
1441   PREFIX_EVEX_0F2F,
1442   PREFIX_EVEX_0F51,
1443   PREFIX_EVEX_0F54,
1444   PREFIX_EVEX_0F55,
1445   PREFIX_EVEX_0F56,
1446   PREFIX_EVEX_0F57,
1447   PREFIX_EVEX_0F58,
1448   PREFIX_EVEX_0F59,
1449   PREFIX_EVEX_0F5A,
1450   PREFIX_EVEX_0F5B,
1451   PREFIX_EVEX_0F5C,
1452   PREFIX_EVEX_0F5D,
1453   PREFIX_EVEX_0F5E,
1454   PREFIX_EVEX_0F5F,
1455   PREFIX_EVEX_0F60,
1456   PREFIX_EVEX_0F61,
1457   PREFIX_EVEX_0F62,
1458   PREFIX_EVEX_0F63,
1459   PREFIX_EVEX_0F64,
1460   PREFIX_EVEX_0F65,
1461   PREFIX_EVEX_0F66,
1462   PREFIX_EVEX_0F67,
1463   PREFIX_EVEX_0F68,
1464   PREFIX_EVEX_0F69,
1465   PREFIX_EVEX_0F6A,
1466   PREFIX_EVEX_0F6B,
1467   PREFIX_EVEX_0F6C,
1468   PREFIX_EVEX_0F6D,
1469   PREFIX_EVEX_0F6E,
1470   PREFIX_EVEX_0F6F,
1471   PREFIX_EVEX_0F70,
1472   PREFIX_EVEX_0F71_REG_2,
1473   PREFIX_EVEX_0F71_REG_4,
1474   PREFIX_EVEX_0F71_REG_6,
1475   PREFIX_EVEX_0F72_REG_0,
1476   PREFIX_EVEX_0F72_REG_1,
1477   PREFIX_EVEX_0F72_REG_2,
1478   PREFIX_EVEX_0F72_REG_4,
1479   PREFIX_EVEX_0F72_REG_6,
1480   PREFIX_EVEX_0F73_REG_2,
1481   PREFIX_EVEX_0F73_REG_3,
1482   PREFIX_EVEX_0F73_REG_6,
1483   PREFIX_EVEX_0F73_REG_7,
1484   PREFIX_EVEX_0F74,
1485   PREFIX_EVEX_0F75,
1486   PREFIX_EVEX_0F76,
1487   PREFIX_EVEX_0F78,
1488   PREFIX_EVEX_0F79,
1489   PREFIX_EVEX_0F7A,
1490   PREFIX_EVEX_0F7B,
1491   PREFIX_EVEX_0F7E,
1492   PREFIX_EVEX_0F7F,
1493   PREFIX_EVEX_0FC2,
1494   PREFIX_EVEX_0FC4,
1495   PREFIX_EVEX_0FC5,
1496   PREFIX_EVEX_0FC6,
1497   PREFIX_EVEX_0FD1,
1498   PREFIX_EVEX_0FD2,
1499   PREFIX_EVEX_0FD3,
1500   PREFIX_EVEX_0FD4,
1501   PREFIX_EVEX_0FD5,
1502   PREFIX_EVEX_0FD6,
1503   PREFIX_EVEX_0FD8,
1504   PREFIX_EVEX_0FD9,
1505   PREFIX_EVEX_0FDA,
1506   PREFIX_EVEX_0FDB,
1507   PREFIX_EVEX_0FDC,
1508   PREFIX_EVEX_0FDD,
1509   PREFIX_EVEX_0FDE,
1510   PREFIX_EVEX_0FDF,
1511   PREFIX_EVEX_0FE0,
1512   PREFIX_EVEX_0FE1,
1513   PREFIX_EVEX_0FE2,
1514   PREFIX_EVEX_0FE3,
1515   PREFIX_EVEX_0FE4,
1516   PREFIX_EVEX_0FE5,
1517   PREFIX_EVEX_0FE6,
1518   PREFIX_EVEX_0FE7,
1519   PREFIX_EVEX_0FE8,
1520   PREFIX_EVEX_0FE9,
1521   PREFIX_EVEX_0FEA,
1522   PREFIX_EVEX_0FEB,
1523   PREFIX_EVEX_0FEC,
1524   PREFIX_EVEX_0FED,
1525   PREFIX_EVEX_0FEE,
1526   PREFIX_EVEX_0FEF,
1527   PREFIX_EVEX_0FF1,
1528   PREFIX_EVEX_0FF2,
1529   PREFIX_EVEX_0FF3,
1530   PREFIX_EVEX_0FF4,
1531   PREFIX_EVEX_0FF5,
1532   PREFIX_EVEX_0FF6,
1533   PREFIX_EVEX_0FF8,
1534   PREFIX_EVEX_0FF9,
1535   PREFIX_EVEX_0FFA,
1536   PREFIX_EVEX_0FFB,
1537   PREFIX_EVEX_0FFC,
1538   PREFIX_EVEX_0FFD,
1539   PREFIX_EVEX_0FFE,
1540   PREFIX_EVEX_0F3800,
1541   PREFIX_EVEX_0F3804,
1542   PREFIX_EVEX_0F380B,
1543   PREFIX_EVEX_0F380C,
1544   PREFIX_EVEX_0F380D,
1545   PREFIX_EVEX_0F3810,
1546   PREFIX_EVEX_0F3811,
1547   PREFIX_EVEX_0F3812,
1548   PREFIX_EVEX_0F3813,
1549   PREFIX_EVEX_0F3814,
1550   PREFIX_EVEX_0F3815,
1551   PREFIX_EVEX_0F3816,
1552   PREFIX_EVEX_0F3818,
1553   PREFIX_EVEX_0F3819,
1554   PREFIX_EVEX_0F381A,
1555   PREFIX_EVEX_0F381B,
1556   PREFIX_EVEX_0F381C,
1557   PREFIX_EVEX_0F381D,
1558   PREFIX_EVEX_0F381E,
1559   PREFIX_EVEX_0F381F,
1560   PREFIX_EVEX_0F3820,
1561   PREFIX_EVEX_0F3821,
1562   PREFIX_EVEX_0F3822,
1563   PREFIX_EVEX_0F3823,
1564   PREFIX_EVEX_0F3824,
1565   PREFIX_EVEX_0F3825,
1566   PREFIX_EVEX_0F3826,
1567   PREFIX_EVEX_0F3827,
1568   PREFIX_EVEX_0F3828,
1569   PREFIX_EVEX_0F3829,
1570   PREFIX_EVEX_0F382A,
1571   PREFIX_EVEX_0F382B,
1572   PREFIX_EVEX_0F382C,
1573   PREFIX_EVEX_0F382D,
1574   PREFIX_EVEX_0F3830,
1575   PREFIX_EVEX_0F3831,
1576   PREFIX_EVEX_0F3832,
1577   PREFIX_EVEX_0F3833,
1578   PREFIX_EVEX_0F3834,
1579   PREFIX_EVEX_0F3835,
1580   PREFIX_EVEX_0F3836,
1581   PREFIX_EVEX_0F3837,
1582   PREFIX_EVEX_0F3838,
1583   PREFIX_EVEX_0F3839,
1584   PREFIX_EVEX_0F383A,
1585   PREFIX_EVEX_0F383B,
1586   PREFIX_EVEX_0F383C,
1587   PREFIX_EVEX_0F383D,
1588   PREFIX_EVEX_0F383E,
1589   PREFIX_EVEX_0F383F,
1590   PREFIX_EVEX_0F3840,
1591   PREFIX_EVEX_0F3842,
1592   PREFIX_EVEX_0F3843,
1593   PREFIX_EVEX_0F3844,
1594   PREFIX_EVEX_0F3845,
1595   PREFIX_EVEX_0F3846,
1596   PREFIX_EVEX_0F3847,
1597   PREFIX_EVEX_0F384C,
1598   PREFIX_EVEX_0F384D,
1599   PREFIX_EVEX_0F384E,
1600   PREFIX_EVEX_0F384F,
1601   PREFIX_EVEX_0F3850,
1602   PREFIX_EVEX_0F3851,
1603   PREFIX_EVEX_0F3852,
1604   PREFIX_EVEX_0F3853,
1605   PREFIX_EVEX_0F3854,
1606   PREFIX_EVEX_0F3855,
1607   PREFIX_EVEX_0F3858,
1608   PREFIX_EVEX_0F3859,
1609   PREFIX_EVEX_0F385A,
1610   PREFIX_EVEX_0F385B,
1611   PREFIX_EVEX_0F3862,
1612   PREFIX_EVEX_0F3863,
1613   PREFIX_EVEX_0F3864,
1614   PREFIX_EVEX_0F3865,
1615   PREFIX_EVEX_0F3866,
1616   PREFIX_EVEX_0F3870,
1617   PREFIX_EVEX_0F3871,
1618   PREFIX_EVEX_0F3872,
1619   PREFIX_EVEX_0F3873,
1620   PREFIX_EVEX_0F3875,
1621   PREFIX_EVEX_0F3876,
1622   PREFIX_EVEX_0F3877,
1623   PREFIX_EVEX_0F3878,
1624   PREFIX_EVEX_0F3879,
1625   PREFIX_EVEX_0F387A,
1626   PREFIX_EVEX_0F387B,
1627   PREFIX_EVEX_0F387C,
1628   PREFIX_EVEX_0F387D,
1629   PREFIX_EVEX_0F387E,
1630   PREFIX_EVEX_0F387F,
1631   PREFIX_EVEX_0F3883,
1632   PREFIX_EVEX_0F3888,
1633   PREFIX_EVEX_0F3889,
1634   PREFIX_EVEX_0F388A,
1635   PREFIX_EVEX_0F388B,
1636   PREFIX_EVEX_0F388D,
1637   PREFIX_EVEX_0F388F,
1638   PREFIX_EVEX_0F3890,
1639   PREFIX_EVEX_0F3891,
1640   PREFIX_EVEX_0F3892,
1641   PREFIX_EVEX_0F3893,
1642   PREFIX_EVEX_0F3896,
1643   PREFIX_EVEX_0F3897,
1644   PREFIX_EVEX_0F3898,
1645   PREFIX_EVEX_0F3899,
1646   PREFIX_EVEX_0F389A,
1647   PREFIX_EVEX_0F389B,
1648   PREFIX_EVEX_0F389C,
1649   PREFIX_EVEX_0F389D,
1650   PREFIX_EVEX_0F389E,
1651   PREFIX_EVEX_0F389F,
1652   PREFIX_EVEX_0F38A0,
1653   PREFIX_EVEX_0F38A1,
1654   PREFIX_EVEX_0F38A2,
1655   PREFIX_EVEX_0F38A3,
1656   PREFIX_EVEX_0F38A6,
1657   PREFIX_EVEX_0F38A7,
1658   PREFIX_EVEX_0F38A8,
1659   PREFIX_EVEX_0F38A9,
1660   PREFIX_EVEX_0F38AA,
1661   PREFIX_EVEX_0F38AB,
1662   PREFIX_EVEX_0F38AC,
1663   PREFIX_EVEX_0F38AD,
1664   PREFIX_EVEX_0F38AE,
1665   PREFIX_EVEX_0F38AF,
1666   PREFIX_EVEX_0F38B4,
1667   PREFIX_EVEX_0F38B5,
1668   PREFIX_EVEX_0F38B6,
1669   PREFIX_EVEX_0F38B7,
1670   PREFIX_EVEX_0F38B8,
1671   PREFIX_EVEX_0F38B9,
1672   PREFIX_EVEX_0F38BA,
1673   PREFIX_EVEX_0F38BB,
1674   PREFIX_EVEX_0F38BC,
1675   PREFIX_EVEX_0F38BD,
1676   PREFIX_EVEX_0F38BE,
1677   PREFIX_EVEX_0F38BF,
1678   PREFIX_EVEX_0F38C4,
1679   PREFIX_EVEX_0F38C6_REG_1,
1680   PREFIX_EVEX_0F38C6_REG_2,
1681   PREFIX_EVEX_0F38C6_REG_5,
1682   PREFIX_EVEX_0F38C6_REG_6,
1683   PREFIX_EVEX_0F38C7_REG_1,
1684   PREFIX_EVEX_0F38C7_REG_2,
1685   PREFIX_EVEX_0F38C7_REG_5,
1686   PREFIX_EVEX_0F38C7_REG_6,
1687   PREFIX_EVEX_0F38C8,
1688   PREFIX_EVEX_0F38CA,
1689   PREFIX_EVEX_0F38CB,
1690   PREFIX_EVEX_0F38CC,
1691   PREFIX_EVEX_0F38CD,
1692   PREFIX_EVEX_0F38CF,
1693   PREFIX_EVEX_0F38DC,
1694   PREFIX_EVEX_0F38DD,
1695   PREFIX_EVEX_0F38DE,
1696   PREFIX_EVEX_0F38DF,
1697
1698   PREFIX_EVEX_0F3A00,
1699   PREFIX_EVEX_0F3A01,
1700   PREFIX_EVEX_0F3A03,
1701   PREFIX_EVEX_0F3A04,
1702   PREFIX_EVEX_0F3A05,
1703   PREFIX_EVEX_0F3A08,
1704   PREFIX_EVEX_0F3A09,
1705   PREFIX_EVEX_0F3A0A,
1706   PREFIX_EVEX_0F3A0B,
1707   PREFIX_EVEX_0F3A0F,
1708   PREFIX_EVEX_0F3A14,
1709   PREFIX_EVEX_0F3A15,
1710   PREFIX_EVEX_0F3A16,
1711   PREFIX_EVEX_0F3A17,
1712   PREFIX_EVEX_0F3A18,
1713   PREFIX_EVEX_0F3A19,
1714   PREFIX_EVEX_0F3A1A,
1715   PREFIX_EVEX_0F3A1B,
1716   PREFIX_EVEX_0F3A1D,
1717   PREFIX_EVEX_0F3A1E,
1718   PREFIX_EVEX_0F3A1F,
1719   PREFIX_EVEX_0F3A20,
1720   PREFIX_EVEX_0F3A21,
1721   PREFIX_EVEX_0F3A22,
1722   PREFIX_EVEX_0F3A23,
1723   PREFIX_EVEX_0F3A25,
1724   PREFIX_EVEX_0F3A26,
1725   PREFIX_EVEX_0F3A27,
1726   PREFIX_EVEX_0F3A38,
1727   PREFIX_EVEX_0F3A39,
1728   PREFIX_EVEX_0F3A3A,
1729   PREFIX_EVEX_0F3A3B,
1730   PREFIX_EVEX_0F3A3E,
1731   PREFIX_EVEX_0F3A3F,
1732   PREFIX_EVEX_0F3A42,
1733   PREFIX_EVEX_0F3A43,
1734   PREFIX_EVEX_0F3A44,
1735   PREFIX_EVEX_0F3A50,
1736   PREFIX_EVEX_0F3A51,
1737   PREFIX_EVEX_0F3A54,
1738   PREFIX_EVEX_0F3A55,
1739   PREFIX_EVEX_0F3A56,
1740   PREFIX_EVEX_0F3A57,
1741   PREFIX_EVEX_0F3A66,
1742   PREFIX_EVEX_0F3A67,
1743   PREFIX_EVEX_0F3A70,
1744   PREFIX_EVEX_0F3A71,
1745   PREFIX_EVEX_0F3A72,
1746   PREFIX_EVEX_0F3A73,
1747   PREFIX_EVEX_0F3ACE,
1748   PREFIX_EVEX_0F3ACF
1749 };
1750
1751 enum
1752 {
1753   X86_64_06 = 0,
1754   X86_64_07,
1755   X86_64_0D,
1756   X86_64_16,
1757   X86_64_17,
1758   X86_64_1E,
1759   X86_64_1F,
1760   X86_64_27,
1761   X86_64_2F,
1762   X86_64_37,
1763   X86_64_3F,
1764   X86_64_60,
1765   X86_64_61,
1766   X86_64_62,
1767   X86_64_63,
1768   X86_64_6D,
1769   X86_64_6F,
1770   X86_64_82,
1771   X86_64_9A,
1772   X86_64_C4,
1773   X86_64_C5,
1774   X86_64_CE,
1775   X86_64_D4,
1776   X86_64_D5,
1777   X86_64_E8,
1778   X86_64_E9,
1779   X86_64_EA,
1780   X86_64_0F01_REG_0,
1781   X86_64_0F01_REG_1,
1782   X86_64_0F01_REG_2,
1783   X86_64_0F01_REG_3
1784 };
1785
1786 enum
1787 {
1788   THREE_BYTE_0F38 = 0,
1789   THREE_BYTE_0F3A
1790 };
1791
1792 enum
1793 {
1794   XOP_08 = 0,
1795   XOP_09,
1796   XOP_0A
1797 };
1798
1799 enum
1800 {
1801   VEX_0F = 0,
1802   VEX_0F38,
1803   VEX_0F3A
1804 };
1805
1806 enum
1807 {
1808   EVEX_0F = 0,
1809   EVEX_0F38,
1810   EVEX_0F3A
1811 };
1812
1813 enum
1814 {
1815   VEX_LEN_0F12_P_0_M_0 = 0,
1816   VEX_LEN_0F12_P_0_M_1,
1817   VEX_LEN_0F12_P_2,
1818   VEX_LEN_0F13_M_0,
1819   VEX_LEN_0F16_P_0_M_0,
1820   VEX_LEN_0F16_P_0_M_1,
1821   VEX_LEN_0F16_P_2,
1822   VEX_LEN_0F17_M_0,
1823   VEX_LEN_0F2A_P_1,
1824   VEX_LEN_0F2A_P_3,
1825   VEX_LEN_0F2C_P_1,
1826   VEX_LEN_0F2C_P_3,
1827   VEX_LEN_0F2D_P_1,
1828   VEX_LEN_0F2D_P_3,
1829   VEX_LEN_0F41_P_0,
1830   VEX_LEN_0F41_P_2,
1831   VEX_LEN_0F42_P_0,
1832   VEX_LEN_0F42_P_2,
1833   VEX_LEN_0F44_P_0,
1834   VEX_LEN_0F44_P_2,
1835   VEX_LEN_0F45_P_0,
1836   VEX_LEN_0F45_P_2,
1837   VEX_LEN_0F46_P_0,
1838   VEX_LEN_0F46_P_2,
1839   VEX_LEN_0F47_P_0,
1840   VEX_LEN_0F47_P_2,
1841   VEX_LEN_0F4A_P_0,
1842   VEX_LEN_0F4A_P_2,
1843   VEX_LEN_0F4B_P_0,
1844   VEX_LEN_0F4B_P_2,
1845   VEX_LEN_0F6E_P_2,
1846   VEX_LEN_0F77_P_0,
1847   VEX_LEN_0F7E_P_1,
1848   VEX_LEN_0F7E_P_2,
1849   VEX_LEN_0F90_P_0,
1850   VEX_LEN_0F90_P_2,
1851   VEX_LEN_0F91_P_0,
1852   VEX_LEN_0F91_P_2,
1853   VEX_LEN_0F92_P_0,
1854   VEX_LEN_0F92_P_2,
1855   VEX_LEN_0F92_P_3,
1856   VEX_LEN_0F93_P_0,
1857   VEX_LEN_0F93_P_2,
1858   VEX_LEN_0F93_P_3,
1859   VEX_LEN_0F98_P_0,
1860   VEX_LEN_0F98_P_2,
1861   VEX_LEN_0F99_P_0,
1862   VEX_LEN_0F99_P_2,
1863   VEX_LEN_0FAE_R_2_M_0,
1864   VEX_LEN_0FAE_R_3_M_0,
1865   VEX_LEN_0FC4_P_2,
1866   VEX_LEN_0FC5_P_2,
1867   VEX_LEN_0FD6_P_2,
1868   VEX_LEN_0FF7_P_2,
1869   VEX_LEN_0F3816_P_2,
1870   VEX_LEN_0F3819_P_2,
1871   VEX_LEN_0F381A_P_2_M_0,
1872   VEX_LEN_0F3836_P_2,
1873   VEX_LEN_0F3841_P_2,
1874   VEX_LEN_0F385A_P_2_M_0,
1875   VEX_LEN_0F38DB_P_2,
1876   VEX_LEN_0F38F2_P_0,
1877   VEX_LEN_0F38F3_R_1_P_0,
1878   VEX_LEN_0F38F3_R_2_P_0,
1879   VEX_LEN_0F38F3_R_3_P_0,
1880   VEX_LEN_0F38F5_P_0,
1881   VEX_LEN_0F38F5_P_1,
1882   VEX_LEN_0F38F5_P_3,
1883   VEX_LEN_0F38F6_P_3,
1884   VEX_LEN_0F38F7_P_0,
1885   VEX_LEN_0F38F7_P_1,
1886   VEX_LEN_0F38F7_P_2,
1887   VEX_LEN_0F38F7_P_3,
1888   VEX_LEN_0F3A00_P_2,
1889   VEX_LEN_0F3A01_P_2,
1890   VEX_LEN_0F3A06_P_2,
1891   VEX_LEN_0F3A14_P_2,
1892   VEX_LEN_0F3A15_P_2,
1893   VEX_LEN_0F3A16_P_2,
1894   VEX_LEN_0F3A17_P_2,
1895   VEX_LEN_0F3A18_P_2,
1896   VEX_LEN_0F3A19_P_2,
1897   VEX_LEN_0F3A20_P_2,
1898   VEX_LEN_0F3A21_P_2,
1899   VEX_LEN_0F3A22_P_2,
1900   VEX_LEN_0F3A30_P_2,
1901   VEX_LEN_0F3A31_P_2,
1902   VEX_LEN_0F3A32_P_2,
1903   VEX_LEN_0F3A33_P_2,
1904   VEX_LEN_0F3A38_P_2,
1905   VEX_LEN_0F3A39_P_2,
1906   VEX_LEN_0F3A41_P_2,
1907   VEX_LEN_0F3A46_P_2,
1908   VEX_LEN_0F3A60_P_2,
1909   VEX_LEN_0F3A61_P_2,
1910   VEX_LEN_0F3A62_P_2,
1911   VEX_LEN_0F3A63_P_2,
1912   VEX_LEN_0F3A6A_P_2,
1913   VEX_LEN_0F3A6B_P_2,
1914   VEX_LEN_0F3A6E_P_2,
1915   VEX_LEN_0F3A6F_P_2,
1916   VEX_LEN_0F3A7A_P_2,
1917   VEX_LEN_0F3A7B_P_2,
1918   VEX_LEN_0F3A7E_P_2,
1919   VEX_LEN_0F3A7F_P_2,
1920   VEX_LEN_0F3ADF_P_2,
1921   VEX_LEN_0F3AF0_P_3,
1922   VEX_LEN_0FXOP_08_CC,
1923   VEX_LEN_0FXOP_08_CD,
1924   VEX_LEN_0FXOP_08_CE,
1925   VEX_LEN_0FXOP_08_CF,
1926   VEX_LEN_0FXOP_08_EC,
1927   VEX_LEN_0FXOP_08_ED,
1928   VEX_LEN_0FXOP_08_EE,
1929   VEX_LEN_0FXOP_08_EF,
1930   VEX_LEN_0FXOP_09_80,
1931   VEX_LEN_0FXOP_09_81
1932 };
1933
1934 enum
1935 {
1936   EVEX_LEN_0F6E_P_2 = 0,
1937   EVEX_LEN_0F7E_P_1,
1938   EVEX_LEN_0F7E_P_2,
1939   EVEX_LEN_0FD6_P_2
1940 };
1941
1942 enum
1943 {
1944   VEX_W_0F41_P_0_LEN_1 = 0,
1945   VEX_W_0F41_P_2_LEN_1,
1946   VEX_W_0F42_P_0_LEN_1,
1947   VEX_W_0F42_P_2_LEN_1,
1948   VEX_W_0F44_P_0_LEN_0,
1949   VEX_W_0F44_P_2_LEN_0,
1950   VEX_W_0F45_P_0_LEN_1,
1951   VEX_W_0F45_P_2_LEN_1,
1952   VEX_W_0F46_P_0_LEN_1,
1953   VEX_W_0F46_P_2_LEN_1,
1954   VEX_W_0F47_P_0_LEN_1,
1955   VEX_W_0F47_P_2_LEN_1,
1956   VEX_W_0F4A_P_0_LEN_1,
1957   VEX_W_0F4A_P_2_LEN_1,
1958   VEX_W_0F4B_P_0_LEN_1,
1959   VEX_W_0F4B_P_2_LEN_1,
1960   VEX_W_0F90_P_0_LEN_0,
1961   VEX_W_0F90_P_2_LEN_0,
1962   VEX_W_0F91_P_0_LEN_0,
1963   VEX_W_0F91_P_2_LEN_0,
1964   VEX_W_0F92_P_0_LEN_0,
1965   VEX_W_0F92_P_2_LEN_0,
1966   VEX_W_0F92_P_3_LEN_0,
1967   VEX_W_0F93_P_0_LEN_0,
1968   VEX_W_0F93_P_2_LEN_0,
1969   VEX_W_0F93_P_3_LEN_0,
1970   VEX_W_0F98_P_0_LEN_0,
1971   VEX_W_0F98_P_2_LEN_0,
1972   VEX_W_0F99_P_0_LEN_0,
1973   VEX_W_0F99_P_2_LEN_0,
1974   VEX_W_0F380C_P_2,
1975   VEX_W_0F380D_P_2,
1976   VEX_W_0F380E_P_2,
1977   VEX_W_0F380F_P_2,
1978   VEX_W_0F3816_P_2,
1979   VEX_W_0F3818_P_2,
1980   VEX_W_0F3819_P_2,
1981   VEX_W_0F381A_P_2_M_0,
1982   VEX_W_0F382C_P_2_M_0,
1983   VEX_W_0F382D_P_2_M_0,
1984   VEX_W_0F382E_P_2_M_0,
1985   VEX_W_0F382F_P_2_M_0,
1986   VEX_W_0F3836_P_2,
1987   VEX_W_0F3846_P_2,
1988   VEX_W_0F3858_P_2,
1989   VEX_W_0F3859_P_2,
1990   VEX_W_0F385A_P_2_M_0,
1991   VEX_W_0F3878_P_2,
1992   VEX_W_0F3879_P_2,
1993   VEX_W_0F38CF_P_2,
1994   VEX_W_0F3A00_P_2,
1995   VEX_W_0F3A01_P_2,
1996   VEX_W_0F3A02_P_2,
1997   VEX_W_0F3A04_P_2,
1998   VEX_W_0F3A05_P_2,
1999   VEX_W_0F3A06_P_2,
2000   VEX_W_0F3A18_P_2,
2001   VEX_W_0F3A19_P_2,
2002   VEX_W_0F3A30_P_2_LEN_0,
2003   VEX_W_0F3A31_P_2_LEN_0,
2004   VEX_W_0F3A32_P_2_LEN_0,
2005   VEX_W_0F3A33_P_2_LEN_0,
2006   VEX_W_0F3A38_P_2,
2007   VEX_W_0F3A39_P_2,
2008   VEX_W_0F3A46_P_2,
2009   VEX_W_0F3A48_P_2,
2010   VEX_W_0F3A49_P_2,
2011   VEX_W_0F3A4A_P_2,
2012   VEX_W_0F3A4B_P_2,
2013   VEX_W_0F3A4C_P_2,
2014   VEX_W_0F3ACE_P_2,
2015   VEX_W_0F3ACF_P_2,
2016
2017   EVEX_W_0F10_P_0,
2018   EVEX_W_0F10_P_1_M_0,
2019   EVEX_W_0F10_P_1_M_1,
2020   EVEX_W_0F10_P_2,
2021   EVEX_W_0F10_P_3_M_0,
2022   EVEX_W_0F10_P_3_M_1,
2023   EVEX_W_0F11_P_0,
2024   EVEX_W_0F11_P_1_M_0,
2025   EVEX_W_0F11_P_1_M_1,
2026   EVEX_W_0F11_P_2,
2027   EVEX_W_0F11_P_3_M_0,
2028   EVEX_W_0F11_P_3_M_1,
2029   EVEX_W_0F12_P_0_M_0,
2030   EVEX_W_0F12_P_0_M_1,
2031   EVEX_W_0F12_P_1,
2032   EVEX_W_0F12_P_2,
2033   EVEX_W_0F12_P_3,
2034   EVEX_W_0F13_P_0,
2035   EVEX_W_0F13_P_2,
2036   EVEX_W_0F14_P_0,
2037   EVEX_W_0F14_P_2,
2038   EVEX_W_0F15_P_0,
2039   EVEX_W_0F15_P_2,
2040   EVEX_W_0F16_P_0_M_0,
2041   EVEX_W_0F16_P_0_M_1,
2042   EVEX_W_0F16_P_1,
2043   EVEX_W_0F16_P_2,
2044   EVEX_W_0F17_P_0,
2045   EVEX_W_0F17_P_2,
2046   EVEX_W_0F28_P_0,
2047   EVEX_W_0F28_P_2,
2048   EVEX_W_0F29_P_0,
2049   EVEX_W_0F29_P_2,
2050   EVEX_W_0F2A_P_1,
2051   EVEX_W_0F2A_P_3,
2052   EVEX_W_0F2B_P_0,
2053   EVEX_W_0F2B_P_2,
2054   EVEX_W_0F2E_P_0,
2055   EVEX_W_0F2E_P_2,
2056   EVEX_W_0F2F_P_0,
2057   EVEX_W_0F2F_P_2,
2058   EVEX_W_0F51_P_0,
2059   EVEX_W_0F51_P_1,
2060   EVEX_W_0F51_P_2,
2061   EVEX_W_0F51_P_3,
2062   EVEX_W_0F54_P_0,
2063   EVEX_W_0F54_P_2,
2064   EVEX_W_0F55_P_0,
2065   EVEX_W_0F55_P_2,
2066   EVEX_W_0F56_P_0,
2067   EVEX_W_0F56_P_2,
2068   EVEX_W_0F57_P_0,
2069   EVEX_W_0F57_P_2,
2070   EVEX_W_0F58_P_0,
2071   EVEX_W_0F58_P_1,
2072   EVEX_W_0F58_P_2,
2073   EVEX_W_0F58_P_3,
2074   EVEX_W_0F59_P_0,
2075   EVEX_W_0F59_P_1,
2076   EVEX_W_0F59_P_2,
2077   EVEX_W_0F59_P_3,
2078   EVEX_W_0F5A_P_0,
2079   EVEX_W_0F5A_P_1,
2080   EVEX_W_0F5A_P_2,
2081   EVEX_W_0F5A_P_3,
2082   EVEX_W_0F5B_P_0,
2083   EVEX_W_0F5B_P_1,
2084   EVEX_W_0F5B_P_2,
2085   EVEX_W_0F5C_P_0,
2086   EVEX_W_0F5C_P_1,
2087   EVEX_W_0F5C_P_2,
2088   EVEX_W_0F5C_P_3,
2089   EVEX_W_0F5D_P_0,
2090   EVEX_W_0F5D_P_1,
2091   EVEX_W_0F5D_P_2,
2092   EVEX_W_0F5D_P_3,
2093   EVEX_W_0F5E_P_0,
2094   EVEX_W_0F5E_P_1,
2095   EVEX_W_0F5E_P_2,
2096   EVEX_W_0F5E_P_3,
2097   EVEX_W_0F5F_P_0,
2098   EVEX_W_0F5F_P_1,
2099   EVEX_W_0F5F_P_2,
2100   EVEX_W_0F5F_P_3,
2101   EVEX_W_0F62_P_2,
2102   EVEX_W_0F66_P_2,
2103   EVEX_W_0F6A_P_2,
2104   EVEX_W_0F6B_P_2,
2105   EVEX_W_0F6C_P_2,
2106   EVEX_W_0F6D_P_2,
2107   EVEX_W_0F6E_P_2,
2108   EVEX_W_0F6F_P_1,
2109   EVEX_W_0F6F_P_2,
2110   EVEX_W_0F6F_P_3,
2111   EVEX_W_0F70_P_2,
2112   EVEX_W_0F72_R_2_P_2,
2113   EVEX_W_0F72_R_6_P_2,
2114   EVEX_W_0F73_R_2_P_2,
2115   EVEX_W_0F73_R_6_P_2,
2116   EVEX_W_0F76_P_2,
2117   EVEX_W_0F78_P_0,
2118   EVEX_W_0F78_P_2,
2119   EVEX_W_0F79_P_0,
2120   EVEX_W_0F79_P_2,
2121   EVEX_W_0F7A_P_1,
2122   EVEX_W_0F7A_P_2,
2123   EVEX_W_0F7A_P_3,
2124   EVEX_W_0F7B_P_1,
2125   EVEX_W_0F7B_P_2,
2126   EVEX_W_0F7B_P_3,
2127   EVEX_W_0F7E_P_1,
2128   EVEX_W_0F7E_P_2,
2129   EVEX_W_0F7F_P_1,
2130   EVEX_W_0F7F_P_2,
2131   EVEX_W_0F7F_P_3,
2132   EVEX_W_0FC2_P_0,
2133   EVEX_W_0FC2_P_1,
2134   EVEX_W_0FC2_P_2,
2135   EVEX_W_0FC2_P_3,
2136   EVEX_W_0FC6_P_0,
2137   EVEX_W_0FC6_P_2,
2138   EVEX_W_0FD2_P_2,
2139   EVEX_W_0FD3_P_2,
2140   EVEX_W_0FD4_P_2,
2141   EVEX_W_0FD6_P_2,
2142   EVEX_W_0FE6_P_1,
2143   EVEX_W_0FE6_P_2,
2144   EVEX_W_0FE6_P_3,
2145   EVEX_W_0FE7_P_2,
2146   EVEX_W_0FF2_P_2,
2147   EVEX_W_0FF3_P_2,
2148   EVEX_W_0FF4_P_2,
2149   EVEX_W_0FFA_P_2,
2150   EVEX_W_0FFB_P_2,
2151   EVEX_W_0FFE_P_2,
2152   EVEX_W_0F380C_P_2,
2153   EVEX_W_0F380D_P_2,
2154   EVEX_W_0F3810_P_1,
2155   EVEX_W_0F3810_P_2,
2156   EVEX_W_0F3811_P_1,
2157   EVEX_W_0F3811_P_2,
2158   EVEX_W_0F3812_P_1,
2159   EVEX_W_0F3812_P_2,
2160   EVEX_W_0F3813_P_1,
2161   EVEX_W_0F3813_P_2,
2162   EVEX_W_0F3814_P_1,
2163   EVEX_W_0F3815_P_1,
2164   EVEX_W_0F3818_P_2,
2165   EVEX_W_0F3819_P_2,
2166   EVEX_W_0F381A_P_2,
2167   EVEX_W_0F381B_P_2,
2168   EVEX_W_0F381E_P_2,
2169   EVEX_W_0F381F_P_2,
2170   EVEX_W_0F3820_P_1,
2171   EVEX_W_0F3821_P_1,
2172   EVEX_W_0F3822_P_1,
2173   EVEX_W_0F3823_P_1,
2174   EVEX_W_0F3824_P_1,
2175   EVEX_W_0F3825_P_1,
2176   EVEX_W_0F3825_P_2,
2177   EVEX_W_0F3826_P_1,
2178   EVEX_W_0F3826_P_2,
2179   EVEX_W_0F3828_P_1,
2180   EVEX_W_0F3828_P_2,
2181   EVEX_W_0F3829_P_1,
2182   EVEX_W_0F3829_P_2,
2183   EVEX_W_0F382A_P_1,
2184   EVEX_W_0F382A_P_2,
2185   EVEX_W_0F382B_P_2,
2186   EVEX_W_0F3830_P_1,
2187   EVEX_W_0F3831_P_1,
2188   EVEX_W_0F3832_P_1,
2189   EVEX_W_0F3833_P_1,
2190   EVEX_W_0F3834_P_1,
2191   EVEX_W_0F3835_P_1,
2192   EVEX_W_0F3835_P_2,
2193   EVEX_W_0F3837_P_2,
2194   EVEX_W_0F3838_P_1,
2195   EVEX_W_0F3839_P_1,
2196   EVEX_W_0F383A_P_1,
2197   EVEX_W_0F3840_P_2,
2198   EVEX_W_0F3854_P_2,
2199   EVEX_W_0F3855_P_2,
2200   EVEX_W_0F3858_P_2,
2201   EVEX_W_0F3859_P_2,
2202   EVEX_W_0F385A_P_2,
2203   EVEX_W_0F385B_P_2,
2204   EVEX_W_0F3862_P_2,
2205   EVEX_W_0F3863_P_2,
2206   EVEX_W_0F3866_P_2,
2207   EVEX_W_0F3870_P_2,
2208   EVEX_W_0F3871_P_2,
2209   EVEX_W_0F3872_P_2,
2210   EVEX_W_0F3873_P_2,
2211   EVEX_W_0F3875_P_2,
2212   EVEX_W_0F3878_P_2,
2213   EVEX_W_0F3879_P_2,
2214   EVEX_W_0F387A_P_2,
2215   EVEX_W_0F387B_P_2,
2216   EVEX_W_0F387D_P_2,
2217   EVEX_W_0F3883_P_2,
2218   EVEX_W_0F388D_P_2,
2219   EVEX_W_0F3891_P_2,
2220   EVEX_W_0F3893_P_2,
2221   EVEX_W_0F38A1_P_2,
2222   EVEX_W_0F38A3_P_2,
2223   EVEX_W_0F38C7_R_1_P_2,
2224   EVEX_W_0F38C7_R_2_P_2,
2225   EVEX_W_0F38C7_R_5_P_2,
2226   EVEX_W_0F38C7_R_6_P_2,
2227
2228   EVEX_W_0F3A00_P_2,
2229   EVEX_W_0F3A01_P_2,
2230   EVEX_W_0F3A04_P_2,
2231   EVEX_W_0F3A05_P_2,
2232   EVEX_W_0F3A08_P_2,
2233   EVEX_W_0F3A09_P_2,
2234   EVEX_W_0F3A0A_P_2,
2235   EVEX_W_0F3A0B_P_2,
2236   EVEX_W_0F3A18_P_2,
2237   EVEX_W_0F3A19_P_2,
2238   EVEX_W_0F3A1A_P_2,
2239   EVEX_W_0F3A1B_P_2,
2240   EVEX_W_0F3A1D_P_2,
2241   EVEX_W_0F3A21_P_2,
2242   EVEX_W_0F3A23_P_2,
2243   EVEX_W_0F3A38_P_2,
2244   EVEX_W_0F3A39_P_2,
2245   EVEX_W_0F3A3A_P_2,
2246   EVEX_W_0F3A3B_P_2,
2247   EVEX_W_0F3A3E_P_2,
2248   EVEX_W_0F3A3F_P_2,
2249   EVEX_W_0F3A42_P_2,
2250   EVEX_W_0F3A43_P_2,
2251   EVEX_W_0F3A50_P_2,
2252   EVEX_W_0F3A51_P_2,
2253   EVEX_W_0F3A56_P_2,
2254   EVEX_W_0F3A57_P_2,
2255   EVEX_W_0F3A66_P_2,
2256   EVEX_W_0F3A67_P_2,
2257   EVEX_W_0F3A70_P_2,
2258   EVEX_W_0F3A71_P_2,
2259   EVEX_W_0F3A72_P_2,
2260   EVEX_W_0F3A73_P_2,
2261   EVEX_W_0F3ACE_P_2,
2262   EVEX_W_0F3ACF_P_2
2263 };
2264
2265 typedef void (*op_rtn) (int bytemode, int sizeflag);
2266
2267 struct dis386 {
2268   const char *name;
2269   struct
2270     {
2271       op_rtn rtn;
2272       int bytemode;
2273     } op[MAX_OPERANDS];
2274   unsigned int prefix_requirement;
2275 };
2276
2277 /* Upper case letters in the instruction names here are macros.
2278    'A' => print 'b' if no register operands or suffix_always is true
2279    'B' => print 'b' if suffix_always is true
2280    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2281           size prefix
2282    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2283           suffix_always is true
2284    'E' => print 'e' if 32-bit form of jcxz
2285    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2286    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2287    'H' => print ",pt" or ",pn" branch hint
2288    'I' => honor following macro letter even in Intel mode (implemented only
2289           for some of the macro letters)
2290    'J' => print 'l'
2291    'K' => print 'd' or 'q' if rex prefix is present.
2292    'L' => print 'l' if suffix_always is true
2293    'M' => print 'r' if intel_mnemonic is false.
2294    'N' => print 'n' if instruction has no wait "prefix"
2295    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2296    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2297           or suffix_always is true.  print 'q' if rex prefix is present.
2298    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2299           is true
2300    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2301    'S' => print 'w', 'l' or 'q' if suffix_always is true
2302    'T' => print 'q' in 64bit mode if instruction has no operand size
2303           prefix and behave as 'P' otherwise
2304    'U' => print 'q' in 64bit mode if instruction has no operand size
2305           prefix and behave as 'Q' otherwise
2306    'V' => print 'q' in 64bit mode if instruction has no operand size
2307           prefix and behave as 'S' otherwise
2308    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2309    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2310    'Y' unused.
2311    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2312    '!' => change condition from true to false or from false to true.
2313    '%' => add 1 upper case letter to the macro.
2314    '^' => print 'w' or 'l' depending on operand size prefix or
2315           suffix_always is true (lcall/ljmp).
2316    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2317           on operand size prefix.
2318    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2319           has no operand size prefix for AMD64 ISA, behave as 'P'
2320           otherwise
2321
2322    2 upper case letter macros:
2323    "XY" => print 'x' or 'y' if suffix_always is true or no register
2324            operands and no broadcast.
2325    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2326            register operands and no broadcast.
2327    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2328    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2329            or suffix_always is true
2330    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2331    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2332    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2333    "LW" => print 'd', 'q' depending on the VEX.W bit
2334    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2335            an operand size prefix, or suffix_always is true.  print
2336            'q' if rex prefix is present.
2337
2338    Many of the above letters print nothing in Intel mode.  See "putop"
2339    for the details.
2340
2341    Braces '{' and '}', and vertical bars '|', indicate alternative
2342    mnemonic strings for AT&T and Intel.  */
2343
2344 static const struct dis386 dis386[] = {
2345   /* 00 */
2346   { "addB",             { Ebh1, Gb }, 0 },
2347   { "addS",             { Evh1, Gv }, 0 },
2348   { "addB",             { Gb, EbS }, 0 },
2349   { "addS",             { Gv, EvS }, 0 },
2350   { "addB",             { AL, Ib }, 0 },
2351   { "addS",             { eAX, Iv }, 0 },
2352   { X86_64_TABLE (X86_64_06) },
2353   { X86_64_TABLE (X86_64_07) },
2354   /* 08 */
2355   { "orB",              { Ebh1, Gb }, 0 },
2356   { "orS",              { Evh1, Gv }, 0 },
2357   { "orB",              { Gb, EbS }, 0 },
2358   { "orS",              { Gv, EvS }, 0 },
2359   { "orB",              { AL, Ib }, 0 },
2360   { "orS",              { eAX, Iv }, 0 },
2361   { X86_64_TABLE (X86_64_0D) },
2362   { Bad_Opcode },       /* 0x0f extended opcode escape */
2363   /* 10 */
2364   { "adcB",             { Ebh1, Gb }, 0 },
2365   { "adcS",             { Evh1, Gv }, 0 },
2366   { "adcB",             { Gb, EbS }, 0 },
2367   { "adcS",             { Gv, EvS }, 0 },
2368   { "adcB",             { AL, Ib }, 0 },
2369   { "adcS",             { eAX, Iv }, 0 },
2370   { X86_64_TABLE (X86_64_16) },
2371   { X86_64_TABLE (X86_64_17) },
2372   /* 18 */
2373   { "sbbB",             { Ebh1, Gb }, 0 },
2374   { "sbbS",             { Evh1, Gv }, 0 },
2375   { "sbbB",             { Gb, EbS }, 0 },
2376   { "sbbS",             { Gv, EvS }, 0 },
2377   { "sbbB",             { AL, Ib }, 0 },
2378   { "sbbS",             { eAX, Iv }, 0 },
2379   { X86_64_TABLE (X86_64_1E) },
2380   { X86_64_TABLE (X86_64_1F) },
2381   /* 20 */
2382   { "andB",             { Ebh1, Gb }, 0 },
2383   { "andS",             { Evh1, Gv }, 0 },
2384   { "andB",             { Gb, EbS }, 0 },
2385   { "andS",             { Gv, EvS }, 0 },
2386   { "andB",             { AL, Ib }, 0 },
2387   { "andS",             { eAX, Iv }, 0 },
2388   { Bad_Opcode },       /* SEG ES prefix */
2389   { X86_64_TABLE (X86_64_27) },
2390   /* 28 */
2391   { "subB",             { Ebh1, Gb }, 0 },
2392   { "subS",             { Evh1, Gv }, 0 },
2393   { "subB",             { Gb, EbS }, 0 },
2394   { "subS",             { Gv, EvS }, 0 },
2395   { "subB",             { AL, Ib }, 0 },
2396   { "subS",             { eAX, Iv }, 0 },
2397   { Bad_Opcode },       /* SEG CS prefix */
2398   { X86_64_TABLE (X86_64_2F) },
2399   /* 30 */
2400   { "xorB",             { Ebh1, Gb }, 0 },
2401   { "xorS",             { Evh1, Gv }, 0 },
2402   { "xorB",             { Gb, EbS }, 0 },
2403   { "xorS",             { Gv, EvS }, 0 },
2404   { "xorB",             { AL, Ib }, 0 },
2405   { "xorS",             { eAX, Iv }, 0 },
2406   { Bad_Opcode },       /* SEG SS prefix */
2407   { X86_64_TABLE (X86_64_37) },
2408   /* 38 */
2409   { "cmpB",             { Eb, Gb }, 0 },
2410   { "cmpS",             { Ev, Gv }, 0 },
2411   { "cmpB",             { Gb, EbS }, 0 },
2412   { "cmpS",             { Gv, EvS }, 0 },
2413   { "cmpB",             { AL, Ib }, 0 },
2414   { "cmpS",             { eAX, Iv }, 0 },
2415   { Bad_Opcode },       /* SEG DS prefix */
2416   { X86_64_TABLE (X86_64_3F) },
2417   /* 40 */
2418   { "inc{S|}",          { RMeAX }, 0 },
2419   { "inc{S|}",          { RMeCX }, 0 },
2420   { "inc{S|}",          { RMeDX }, 0 },
2421   { "inc{S|}",          { RMeBX }, 0 },
2422   { "inc{S|}",          { RMeSP }, 0 },
2423   { "inc{S|}",          { RMeBP }, 0 },
2424   { "inc{S|}",          { RMeSI }, 0 },
2425   { "inc{S|}",          { RMeDI }, 0 },
2426   /* 48 */
2427   { "dec{S|}",          { RMeAX }, 0 },
2428   { "dec{S|}",          { RMeCX }, 0 },
2429   { "dec{S|}",          { RMeDX }, 0 },
2430   { "dec{S|}",          { RMeBX }, 0 },
2431   { "dec{S|}",          { RMeSP }, 0 },
2432   { "dec{S|}",          { RMeBP }, 0 },
2433   { "dec{S|}",          { RMeSI }, 0 },
2434   { "dec{S|}",          { RMeDI }, 0 },
2435   /* 50 */
2436   { "pushV",            { RMrAX }, 0 },
2437   { "pushV",            { RMrCX }, 0 },
2438   { "pushV",            { RMrDX }, 0 },
2439   { "pushV",            { RMrBX }, 0 },
2440   { "pushV",            { RMrSP }, 0 },
2441   { "pushV",            { RMrBP }, 0 },
2442   { "pushV",            { RMrSI }, 0 },
2443   { "pushV",            { RMrDI }, 0 },
2444   /* 58 */
2445   { "popV",             { RMrAX }, 0 },
2446   { "popV",             { RMrCX }, 0 },
2447   { "popV",             { RMrDX }, 0 },
2448   { "popV",             { RMrBX }, 0 },
2449   { "popV",             { RMrSP }, 0 },
2450   { "popV",             { RMrBP }, 0 },
2451   { "popV",             { RMrSI }, 0 },
2452   { "popV",             { RMrDI }, 0 },
2453   /* 60 */
2454   { X86_64_TABLE (X86_64_60) },
2455   { X86_64_TABLE (X86_64_61) },
2456   { X86_64_TABLE (X86_64_62) },
2457   { X86_64_TABLE (X86_64_63) },
2458   { Bad_Opcode },       /* seg fs */
2459   { Bad_Opcode },       /* seg gs */
2460   { Bad_Opcode },       /* op size prefix */
2461   { Bad_Opcode },       /* adr size prefix */
2462   /* 68 */
2463   { "pushT",            { sIv }, 0 },
2464   { "imulS",            { Gv, Ev, Iv }, 0 },
2465   { "pushT",            { sIbT }, 0 },
2466   { "imulS",            { Gv, Ev, sIb }, 0 },
2467   { "ins{b|}",          { Ybr, indirDX }, 0 },
2468   { X86_64_TABLE (X86_64_6D) },
2469   { "outs{b|}",         { indirDXr, Xb }, 0 },
2470   { X86_64_TABLE (X86_64_6F) },
2471   /* 70 */
2472   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2473   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2474   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2475   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2476   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2477   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2478   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2479   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2480   /* 78 */
2481   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2482   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2483   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2484   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2485   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2486   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2487   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2488   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2489   /* 80 */
2490   { REG_TABLE (REG_80) },
2491   { REG_TABLE (REG_81) },
2492   { X86_64_TABLE (X86_64_82) },
2493   { REG_TABLE (REG_83) },
2494   { "testB",            { Eb, Gb }, 0 },
2495   { "testS",            { Ev, Gv }, 0 },
2496   { "xchgB",            { Ebh2, Gb }, 0 },
2497   { "xchgS",            { Evh2, Gv }, 0 },
2498   /* 88 */
2499   { "movB",             { Ebh3, Gb }, 0 },
2500   { "movS",             { Evh3, Gv }, 0 },
2501   { "movB",             { Gb, EbS }, 0 },
2502   { "movS",             { Gv, EvS }, 0 },
2503   { "movD",             { Sv, Sw }, 0 },
2504   { MOD_TABLE (MOD_8D) },
2505   { "movD",             { Sw, Sv }, 0 },
2506   { REG_TABLE (REG_8F) },
2507   /* 90 */
2508   { PREFIX_TABLE (PREFIX_90) },
2509   { "xchgS",            { RMeCX, eAX }, 0 },
2510   { "xchgS",            { RMeDX, eAX }, 0 },
2511   { "xchgS",            { RMeBX, eAX }, 0 },
2512   { "xchgS",            { RMeSP, eAX }, 0 },
2513   { "xchgS",            { RMeBP, eAX }, 0 },
2514   { "xchgS",            { RMeSI, eAX }, 0 },
2515   { "xchgS",            { RMeDI, eAX }, 0 },
2516   /* 98 */
2517   { "cW{t|}R",          { XX }, 0 },
2518   { "cR{t|}O",          { XX }, 0 },
2519   { X86_64_TABLE (X86_64_9A) },
2520   { Bad_Opcode },       /* fwait */
2521   { "pushfT",           { XX }, 0 },
2522   { "popfT",            { XX }, 0 },
2523   { "sahf",             { XX }, 0 },
2524   { "lahf",             { XX }, 0 },
2525   /* a0 */
2526   { "mov%LB",           { AL, Ob }, 0 },
2527   { "mov%LS",           { eAX, Ov }, 0 },
2528   { "mov%LB",           { Ob, AL }, 0 },
2529   { "mov%LS",           { Ov, eAX }, 0 },
2530   { "movs{b|}",         { Ybr, Xb }, 0 },
2531   { "movs{R|}",         { Yvr, Xv }, 0 },
2532   { "cmps{b|}",         { Xb, Yb }, 0 },
2533   { "cmps{R|}",         { Xv, Yv }, 0 },
2534   /* a8 */
2535   { "testB",            { AL, Ib }, 0 },
2536   { "testS",            { eAX, Iv }, 0 },
2537   { "stosB",            { Ybr, AL }, 0 },
2538   { "stosS",            { Yvr, eAX }, 0 },
2539   { "lodsB",            { ALr, Xb }, 0 },
2540   { "lodsS",            { eAXr, Xv }, 0 },
2541   { "scasB",            { AL, Yb }, 0 },
2542   { "scasS",            { eAX, Yv }, 0 },
2543   /* b0 */
2544   { "movB",             { RMAL, Ib }, 0 },
2545   { "movB",             { RMCL, Ib }, 0 },
2546   { "movB",             { RMDL, Ib }, 0 },
2547   { "movB",             { RMBL, Ib }, 0 },
2548   { "movB",             { RMAH, Ib }, 0 },
2549   { "movB",             { RMCH, Ib }, 0 },
2550   { "movB",             { RMDH, Ib }, 0 },
2551   { "movB",             { RMBH, Ib }, 0 },
2552   /* b8 */
2553   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2554   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2555   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2556   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2557   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2558   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2559   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2560   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2561   /* c0 */
2562   { REG_TABLE (REG_C0) },
2563   { REG_TABLE (REG_C1) },
2564   { "retT",             { Iw, BND }, 0 },
2565   { "retT",             { BND }, 0 },
2566   { X86_64_TABLE (X86_64_C4) },
2567   { X86_64_TABLE (X86_64_C5) },
2568   { REG_TABLE (REG_C6) },
2569   { REG_TABLE (REG_C7) },
2570   /* c8 */
2571   { "enterT",           { Iw, Ib }, 0 },
2572   { "leaveT",           { XX }, 0 },
2573   { "Jret{|f}P",        { Iw }, 0 },
2574   { "Jret{|f}P",        { XX }, 0 },
2575   { "int3",             { XX }, 0 },
2576   { "int",              { Ib }, 0 },
2577   { X86_64_TABLE (X86_64_CE) },
2578   { "iret%LP",          { XX }, 0 },
2579   /* d0 */
2580   { REG_TABLE (REG_D0) },
2581   { REG_TABLE (REG_D1) },
2582   { REG_TABLE (REG_D2) },
2583   { REG_TABLE (REG_D3) },
2584   { X86_64_TABLE (X86_64_D4) },
2585   { X86_64_TABLE (X86_64_D5) },
2586   { Bad_Opcode },
2587   { "xlat",             { DSBX }, 0 },
2588   /* d8 */
2589   { FLOAT },
2590   { FLOAT },
2591   { FLOAT },
2592   { FLOAT },
2593   { FLOAT },
2594   { FLOAT },
2595   { FLOAT },
2596   { FLOAT },
2597   /* e0 */
2598   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2599   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2600   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2601   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2602   { "inB",              { AL, Ib }, 0 },
2603   { "inG",              { zAX, Ib }, 0 },
2604   { "outB",             { Ib, AL }, 0 },
2605   { "outG",             { Ib, zAX }, 0 },
2606   /* e8 */
2607   { X86_64_TABLE (X86_64_E8) },
2608   { X86_64_TABLE (X86_64_E9) },
2609   { X86_64_TABLE (X86_64_EA) },
2610   { "jmp",              { Jb, BND }, 0 },
2611   { "inB",              { AL, indirDX }, 0 },
2612   { "inG",              { zAX, indirDX }, 0 },
2613   { "outB",             { indirDX, AL }, 0 },
2614   { "outG",             { indirDX, zAX }, 0 },
2615   /* f0 */
2616   { Bad_Opcode },       /* lock prefix */
2617   { "icebp",            { XX }, 0 },
2618   { Bad_Opcode },       /* repne */
2619   { Bad_Opcode },       /* repz */
2620   { "hlt",              { XX }, 0 },
2621   { "cmc",              { XX }, 0 },
2622   { REG_TABLE (REG_F6) },
2623   { REG_TABLE (REG_F7) },
2624   /* f8 */
2625   { "clc",              { XX }, 0 },
2626   { "stc",              { XX }, 0 },
2627   { "cli",              { XX }, 0 },
2628   { "sti",              { XX }, 0 },
2629   { "cld",              { XX }, 0 },
2630   { "std",              { XX }, 0 },
2631   { REG_TABLE (REG_FE) },
2632   { REG_TABLE (REG_FF) },
2633 };
2634
2635 static const struct dis386 dis386_twobyte[] = {
2636   /* 00 */
2637   { REG_TABLE (REG_0F00 ) },
2638   { REG_TABLE (REG_0F01 ) },
2639   { "larS",             { Gv, Ew }, 0 },
2640   { "lslS",             { Gv, Ew }, 0 },
2641   { Bad_Opcode },
2642   { "syscall",          { XX }, 0 },
2643   { "clts",             { XX }, 0 },
2644   { "sysret%LP",                { XX }, 0 },
2645   /* 08 */
2646   { "invd",             { XX }, 0 },
2647   { PREFIX_TABLE (PREFIX_0F09) },
2648   { Bad_Opcode },
2649   { "ud2",              { XX }, 0 },
2650   { Bad_Opcode },
2651   { REG_TABLE (REG_0F0D) },
2652   { "femms",            { XX }, 0 },
2653   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2654   /* 10 */
2655   { PREFIX_TABLE (PREFIX_0F10) },
2656   { PREFIX_TABLE (PREFIX_0F11) },
2657   { PREFIX_TABLE (PREFIX_0F12) },
2658   { MOD_TABLE (MOD_0F13) },
2659   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2660   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2661   { PREFIX_TABLE (PREFIX_0F16) },
2662   { MOD_TABLE (MOD_0F17) },
2663   /* 18 */
2664   { REG_TABLE (REG_0F18) },
2665   { "nopQ",             { Ev }, 0 },
2666   { PREFIX_TABLE (PREFIX_0F1A) },
2667   { PREFIX_TABLE (PREFIX_0F1B) },
2668   { PREFIX_TABLE (PREFIX_0F1C) },
2669   { "nopQ",             { Ev }, 0 },
2670   { PREFIX_TABLE (PREFIX_0F1E) },
2671   { "nopQ",             { Ev }, 0 },
2672   /* 20 */
2673   { "movZ",             { Rm, Cm }, 0 },
2674   { "movZ",             { Rm, Dm }, 0 },
2675   { "movZ",             { Cm, Rm }, 0 },
2676   { "movZ",             { Dm, Rm }, 0 },
2677   { MOD_TABLE (MOD_0F24) },
2678   { Bad_Opcode },
2679   { MOD_TABLE (MOD_0F26) },
2680   { Bad_Opcode },
2681   /* 28 */
2682   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2683   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2684   { PREFIX_TABLE (PREFIX_0F2A) },
2685   { PREFIX_TABLE (PREFIX_0F2B) },
2686   { PREFIX_TABLE (PREFIX_0F2C) },
2687   { PREFIX_TABLE (PREFIX_0F2D) },
2688   { PREFIX_TABLE (PREFIX_0F2E) },
2689   { PREFIX_TABLE (PREFIX_0F2F) },
2690   /* 30 */
2691   { "wrmsr",            { XX }, 0 },
2692   { "rdtsc",            { XX }, 0 },
2693   { "rdmsr",            { XX }, 0 },
2694   { "rdpmc",            { XX }, 0 },
2695   { "sysenter",         { XX }, 0 },
2696   { "sysexit",          { XX }, 0 },
2697   { Bad_Opcode },
2698   { "getsec",           { XX }, 0 },
2699   /* 38 */
2700   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2701   { Bad_Opcode },
2702   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2703   { Bad_Opcode },
2704   { Bad_Opcode },
2705   { Bad_Opcode },
2706   { Bad_Opcode },
2707   { Bad_Opcode },
2708   /* 40 */
2709   { "cmovoS",           { Gv, Ev }, 0 },
2710   { "cmovnoS",          { Gv, Ev }, 0 },
2711   { "cmovbS",           { Gv, Ev }, 0 },
2712   { "cmovaeS",          { Gv, Ev }, 0 },
2713   { "cmoveS",           { Gv, Ev }, 0 },
2714   { "cmovneS",          { Gv, Ev }, 0 },
2715   { "cmovbeS",          { Gv, Ev }, 0 },
2716   { "cmovaS",           { Gv, Ev }, 0 },
2717   /* 48 */
2718   { "cmovsS",           { Gv, Ev }, 0 },
2719   { "cmovnsS",          { Gv, Ev }, 0 },
2720   { "cmovpS",           { Gv, Ev }, 0 },
2721   { "cmovnpS",          { Gv, Ev }, 0 },
2722   { "cmovlS",           { Gv, Ev }, 0 },
2723   { "cmovgeS",          { Gv, Ev }, 0 },
2724   { "cmovleS",          { Gv, Ev }, 0 },
2725   { "cmovgS",           { Gv, Ev }, 0 },
2726   /* 50 */
2727   { MOD_TABLE (MOD_0F51) },
2728   { PREFIX_TABLE (PREFIX_0F51) },
2729   { PREFIX_TABLE (PREFIX_0F52) },
2730   { PREFIX_TABLE (PREFIX_0F53) },
2731   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2732   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2733   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2734   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2735   /* 58 */
2736   { PREFIX_TABLE (PREFIX_0F58) },
2737   { PREFIX_TABLE (PREFIX_0F59) },
2738   { PREFIX_TABLE (PREFIX_0F5A) },
2739   { PREFIX_TABLE (PREFIX_0F5B) },
2740   { PREFIX_TABLE (PREFIX_0F5C) },
2741   { PREFIX_TABLE (PREFIX_0F5D) },
2742   { PREFIX_TABLE (PREFIX_0F5E) },
2743   { PREFIX_TABLE (PREFIX_0F5F) },
2744   /* 60 */
2745   { PREFIX_TABLE (PREFIX_0F60) },
2746   { PREFIX_TABLE (PREFIX_0F61) },
2747   { PREFIX_TABLE (PREFIX_0F62) },
2748   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2749   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2750   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2751   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2752   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2753   /* 68 */
2754   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2755   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2756   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2757   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2758   { PREFIX_TABLE (PREFIX_0F6C) },
2759   { PREFIX_TABLE (PREFIX_0F6D) },
2760   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2761   { PREFIX_TABLE (PREFIX_0F6F) },
2762   /* 70 */
2763   { PREFIX_TABLE (PREFIX_0F70) },
2764   { REG_TABLE (REG_0F71) },
2765   { REG_TABLE (REG_0F72) },
2766   { REG_TABLE (REG_0F73) },
2767   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2768   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2770   { "emms",             { XX }, PREFIX_OPCODE },
2771   /* 78 */
2772   { PREFIX_TABLE (PREFIX_0F78) },
2773   { PREFIX_TABLE (PREFIX_0F79) },
2774   { Bad_Opcode },
2775   { Bad_Opcode },
2776   { PREFIX_TABLE (PREFIX_0F7C) },
2777   { PREFIX_TABLE (PREFIX_0F7D) },
2778   { PREFIX_TABLE (PREFIX_0F7E) },
2779   { PREFIX_TABLE (PREFIX_0F7F) },
2780   /* 80 */
2781   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2782   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2783   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2784   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2785   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2786   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2787   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2788   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2789   /* 88 */
2790   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2791   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2792   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2793   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2794   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2795   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2796   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2797   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2798   /* 90 */
2799   { "seto",             { Eb }, 0 },
2800   { "setno",            { Eb }, 0 },
2801   { "setb",             { Eb }, 0 },
2802   { "setae",            { Eb }, 0 },
2803   { "sete",             { Eb }, 0 },
2804   { "setne",            { Eb }, 0 },
2805   { "setbe",            { Eb }, 0 },
2806   { "seta",             { Eb }, 0 },
2807   /* 98 */
2808   { "sets",             { Eb }, 0 },
2809   { "setns",            { Eb }, 0 },
2810   { "setp",             { Eb }, 0 },
2811   { "setnp",            { Eb }, 0 },
2812   { "setl",             { Eb }, 0 },
2813   { "setge",            { Eb }, 0 },
2814   { "setle",            { Eb }, 0 },
2815   { "setg",             { Eb }, 0 },
2816   /* a0 */
2817   { "pushT",            { fs }, 0 },
2818   { "popT",             { fs }, 0 },
2819   { "cpuid",            { XX }, 0 },
2820   { "btS",              { Ev, Gv }, 0 },
2821   { "shldS",            { Ev, Gv, Ib }, 0 },
2822   { "shldS",            { Ev, Gv, CL }, 0 },
2823   { REG_TABLE (REG_0FA6) },
2824   { REG_TABLE (REG_0FA7) },
2825   /* a8 */
2826   { "pushT",            { gs }, 0 },
2827   { "popT",             { gs }, 0 },
2828   { "rsm",              { XX }, 0 },
2829   { "btsS",             { Evh1, Gv }, 0 },
2830   { "shrdS",            { Ev, Gv, Ib }, 0 },
2831   { "shrdS",            { Ev, Gv, CL }, 0 },
2832   { REG_TABLE (REG_0FAE) },
2833   { "imulS",            { Gv, Ev }, 0 },
2834   /* b0 */
2835   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2836   { "cmpxchgS",         { Evh1, Gv }, 0 },
2837   { MOD_TABLE (MOD_0FB2) },
2838   { "btrS",             { Evh1, Gv }, 0 },
2839   { MOD_TABLE (MOD_0FB4) },
2840   { MOD_TABLE (MOD_0FB5) },
2841   { "movz{bR|x}",       { Gv, Eb }, 0 },
2842   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2843   /* b8 */
2844   { PREFIX_TABLE (PREFIX_0FB8) },
2845   { "ud1S",             { Gv, Ev }, 0 },
2846   { REG_TABLE (REG_0FBA) },
2847   { "btcS",             { Evh1, Gv }, 0 },
2848   { PREFIX_TABLE (PREFIX_0FBC) },
2849   { PREFIX_TABLE (PREFIX_0FBD) },
2850   { "movs{bR|x}",       { Gv, Eb }, 0 },
2851   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2852   /* c0 */
2853   { "xaddB",            { Ebh1, Gb }, 0 },
2854   { "xaddS",            { Evh1, Gv }, 0 },
2855   { PREFIX_TABLE (PREFIX_0FC2) },
2856   { MOD_TABLE (MOD_0FC3) },
2857   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2858   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2859   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2860   { REG_TABLE (REG_0FC7) },
2861   /* c8 */
2862   { "bswap",            { RMeAX }, 0 },
2863   { "bswap",            { RMeCX }, 0 },
2864   { "bswap",            { RMeDX }, 0 },
2865   { "bswap",            { RMeBX }, 0 },
2866   { "bswap",            { RMeSP }, 0 },
2867   { "bswap",            { RMeBP }, 0 },
2868   { "bswap",            { RMeSI }, 0 },
2869   { "bswap",            { RMeDI }, 0 },
2870   /* d0 */
2871   { PREFIX_TABLE (PREFIX_0FD0) },
2872   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2873   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2874   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2875   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2876   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2877   { PREFIX_TABLE (PREFIX_0FD6) },
2878   { MOD_TABLE (MOD_0FD7) },
2879   /* d8 */
2880   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2881   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2882   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2883   { "pand",             { MX, EM }, PREFIX_OPCODE },
2884   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2885   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2886   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2887   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2888   /* e0 */
2889   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2890   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2891   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2892   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2893   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2894   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2895   { PREFIX_TABLE (PREFIX_0FE6) },
2896   { PREFIX_TABLE (PREFIX_0FE7) },
2897   /* e8 */
2898   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2899   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2900   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2901   { "por",              { MX, EM }, PREFIX_OPCODE },
2902   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2903   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2904   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2905   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2906   /* f0 */
2907   { PREFIX_TABLE (PREFIX_0FF0) },
2908   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2909   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2910   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2911   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2912   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2913   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2914   { PREFIX_TABLE (PREFIX_0FF7) },
2915   /* f8 */
2916   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2917   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2918   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2919   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2920   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2921   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2922   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2923   { "ud0S",             { Gv, Ev }, 0 },
2924 };
2925
2926 static const unsigned char onebyte_has_modrm[256] = {
2927   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2928   /*       -------------------------------        */
2929   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2930   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2931   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2932   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2933   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2934   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2935   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2936   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2937   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2938   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2939   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2940   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2941   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2942   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2943   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2944   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2945   /*       -------------------------------        */
2946   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2947 };
2948
2949 static const unsigned char twobyte_has_modrm[256] = {
2950   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2951   /*       -------------------------------        */
2952   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2953   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2954   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2955   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2956   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2957   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2958   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2959   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2960   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2961   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2962   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2963   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2964   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2965   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2966   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2967   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2968   /*       -------------------------------        */
2969   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2970 };
2971
2972 static char obuf[100];
2973 static char *obufp;
2974 static char *mnemonicendp;
2975 static char scratchbuf[100];
2976 static unsigned char *start_codep;
2977 static unsigned char *insn_codep;
2978 static unsigned char *codep;
2979 static unsigned char *end_codep;
2980 static int last_lock_prefix;
2981 static int last_repz_prefix;
2982 static int last_repnz_prefix;
2983 static int last_data_prefix;
2984 static int last_addr_prefix;
2985 static int last_rex_prefix;
2986 static int last_seg_prefix;
2987 static int fwait_prefix;
2988 /* The active segment register prefix.  */
2989 static int active_seg_prefix;
2990 #define MAX_CODE_LENGTH 15
2991 /* We can up to 14 prefixes since the maximum instruction length is
2992    15bytes.  */
2993 static int all_prefixes[MAX_CODE_LENGTH - 1];
2994 static disassemble_info *the_info;
2995 static struct
2996   {
2997     int mod;
2998     int reg;
2999     int rm;
3000   }
3001 modrm;
3002 static unsigned char need_modrm;
3003 static struct
3004   {
3005     int scale;
3006     int index;
3007     int base;
3008   }
3009 sib;
3010 static struct
3011   {
3012     int register_specifier;
3013     int length;
3014     int prefix;
3015     int w;
3016     int evex;
3017     int r;
3018     int v;
3019     int mask_register_specifier;
3020     int zeroing;
3021     int ll;
3022     int b;
3023   }
3024 vex;
3025 static unsigned char need_vex;
3026 static unsigned char need_vex_reg;
3027 static unsigned char vex_w_done;
3028
3029 struct op
3030   {
3031     const char *name;
3032     unsigned int len;
3033   };
3034
3035 /* If we are accessing mod/rm/reg without need_modrm set, then the
3036    values are stale.  Hitting this abort likely indicates that you
3037    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3038 #define MODRM_CHECK  if (!need_modrm) abort ()
3039
3040 static const char **names64;
3041 static const char **names32;
3042 static const char **names16;
3043 static const char **names8;
3044 static const char **names8rex;
3045 static const char **names_seg;
3046 static const char *index64;
3047 static const char *index32;
3048 static const char **index16;
3049 static const char **names_bnd;
3050
3051 static const char *intel_names64[] = {
3052   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3053   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3054 };
3055 static const char *intel_names32[] = {
3056   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3057   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3058 };
3059 static const char *intel_names16[] = {
3060   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3061   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3062 };
3063 static const char *intel_names8[] = {
3064   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3065 };
3066 static const char *intel_names8rex[] = {
3067   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3068   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3069 };
3070 static const char *intel_names_seg[] = {
3071   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3072 };
3073 static const char *intel_index64 = "riz";
3074 static const char *intel_index32 = "eiz";
3075 static const char *intel_index16[] = {
3076   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3077 };
3078
3079 static const char *att_names64[] = {
3080   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3081   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3082 };
3083 static const char *att_names32[] = {
3084   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3085   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3086 };
3087 static const char *att_names16[] = {
3088   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3089   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3090 };
3091 static const char *att_names8[] = {
3092   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3093 };
3094 static const char *att_names8rex[] = {
3095   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3096   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3097 };
3098 static const char *att_names_seg[] = {
3099   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3100 };
3101 static const char *att_index64 = "%riz";
3102 static const char *att_index32 = "%eiz";
3103 static const char *att_index16[] = {
3104   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3105 };
3106
3107 static const char **names_mm;
3108 static const char *intel_names_mm[] = {
3109   "mm0", "mm1", "mm2", "mm3",
3110   "mm4", "mm5", "mm6", "mm7"
3111 };
3112 static const char *att_names_mm[] = {
3113   "%mm0", "%mm1", "%mm2", "%mm3",
3114   "%mm4", "%mm5", "%mm6", "%mm7"
3115 };
3116
3117 static const char *intel_names_bnd[] = {
3118   "bnd0", "bnd1", "bnd2", "bnd3"
3119 };
3120
3121 static const char *att_names_bnd[] = {
3122   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3123 };
3124
3125 static const char **names_xmm;
3126 static const char *intel_names_xmm[] = {
3127   "xmm0", "xmm1", "xmm2", "xmm3",
3128   "xmm4", "xmm5", "xmm6", "xmm7",
3129   "xmm8", "xmm9", "xmm10", "xmm11",
3130   "xmm12", "xmm13", "xmm14", "xmm15",
3131   "xmm16", "xmm17", "xmm18", "xmm19",
3132   "xmm20", "xmm21", "xmm22", "xmm23",
3133   "xmm24", "xmm25", "xmm26", "xmm27",
3134   "xmm28", "xmm29", "xmm30", "xmm31"
3135 };
3136 static const char *att_names_xmm[] = {
3137   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3138   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3139   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3140   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3141   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3142   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3143   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3144   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3145 };
3146
3147 static const char **names_ymm;
3148 static const char *intel_names_ymm[] = {
3149   "ymm0", "ymm1", "ymm2", "ymm3",
3150   "ymm4", "ymm5", "ymm6", "ymm7",
3151   "ymm8", "ymm9", "ymm10", "ymm11",
3152   "ymm12", "ymm13", "ymm14", "ymm15",
3153   "ymm16", "ymm17", "ymm18", "ymm19",
3154   "ymm20", "ymm21", "ymm22", "ymm23",
3155   "ymm24", "ymm25", "ymm26", "ymm27",
3156   "ymm28", "ymm29", "ymm30", "ymm31"
3157 };
3158 static const char *att_names_ymm[] = {
3159   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3160   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3161   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3162   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3163   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3164   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3165   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3166   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3167 };
3168
3169 static const char **names_zmm;
3170 static const char *intel_names_zmm[] = {
3171   "zmm0", "zmm1", "zmm2", "zmm3",
3172   "zmm4", "zmm5", "zmm6", "zmm7",
3173   "zmm8", "zmm9", "zmm10", "zmm11",
3174   "zmm12", "zmm13", "zmm14", "zmm15",
3175   "zmm16", "zmm17", "zmm18", "zmm19",
3176   "zmm20", "zmm21", "zmm22", "zmm23",
3177   "zmm24", "zmm25", "zmm26", "zmm27",
3178   "zmm28", "zmm29", "zmm30", "zmm31"
3179 };
3180 static const char *att_names_zmm[] = {
3181   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3182   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3183   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3184   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3185   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3186   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3187   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3188   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3189 };
3190
3191 static const char **names_mask;
3192 static const char *intel_names_mask[] = {
3193   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3194 };
3195 static const char *att_names_mask[] = {
3196   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3197 };
3198
3199 static const char *names_rounding[] =
3200 {
3201   "{rn-sae}",
3202   "{rd-sae}",
3203   "{ru-sae}",
3204   "{rz-sae}"
3205 };
3206
3207 static const struct dis386 reg_table[][8] = {
3208   /* REG_80 */
3209   {
3210     { "addA",   { Ebh1, Ib }, 0 },
3211     { "orA",    { Ebh1, Ib }, 0 },
3212     { "adcA",   { Ebh1, Ib }, 0 },
3213     { "sbbA",   { Ebh1, Ib }, 0 },
3214     { "andA",   { Ebh1, Ib }, 0 },
3215     { "subA",   { Ebh1, Ib }, 0 },
3216     { "xorA",   { Ebh1, Ib }, 0 },
3217     { "cmpA",   { Eb, Ib }, 0 },
3218   },
3219   /* REG_81 */
3220   {
3221     { "addQ",   { Evh1, Iv }, 0 },
3222     { "orQ",    { Evh1, Iv }, 0 },
3223     { "adcQ",   { Evh1, Iv }, 0 },
3224     { "sbbQ",   { Evh1, Iv }, 0 },
3225     { "andQ",   { Evh1, Iv }, 0 },
3226     { "subQ",   { Evh1, Iv }, 0 },
3227     { "xorQ",   { Evh1, Iv }, 0 },
3228     { "cmpQ",   { Ev, Iv }, 0 },
3229   },
3230   /* REG_83 */
3231   {
3232     { "addQ",   { Evh1, sIb }, 0 },
3233     { "orQ",    { Evh1, sIb }, 0 },
3234     { "adcQ",   { Evh1, sIb }, 0 },
3235     { "sbbQ",   { Evh1, sIb }, 0 },
3236     { "andQ",   { Evh1, sIb }, 0 },
3237     { "subQ",   { Evh1, sIb }, 0 },
3238     { "xorQ",   { Evh1, sIb }, 0 },
3239     { "cmpQ",   { Ev, sIb }, 0 },
3240   },
3241   /* REG_8F */
3242   {
3243     { "popU",   { stackEv }, 0 },
3244     { XOP_8F_TABLE (XOP_09) },
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { XOP_8F_TABLE (XOP_09) },
3249   },
3250   /* REG_C0 */
3251   {
3252     { "rolA",   { Eb, Ib }, 0 },
3253     { "rorA",   { Eb, Ib }, 0 },
3254     { "rclA",   { Eb, Ib }, 0 },
3255     { "rcrA",   { Eb, Ib }, 0 },
3256     { "shlA",   { Eb, Ib }, 0 },
3257     { "shrA",   { Eb, Ib }, 0 },
3258     { "shlA",   { Eb, Ib }, 0 },
3259     { "sarA",   { Eb, Ib }, 0 },
3260   },
3261   /* REG_C1 */
3262   {
3263     { "rolQ",   { Ev, Ib }, 0 },
3264     { "rorQ",   { Ev, Ib }, 0 },
3265     { "rclQ",   { Ev, Ib }, 0 },
3266     { "rcrQ",   { Ev, Ib }, 0 },
3267     { "shlQ",   { Ev, Ib }, 0 },
3268     { "shrQ",   { Ev, Ib }, 0 },
3269     { "shlQ",   { Ev, Ib }, 0 },
3270     { "sarQ",   { Ev, Ib }, 0 },
3271   },
3272   /* REG_C6 */
3273   {
3274     { "movA",   { Ebh3, Ib }, 0 },
3275     { Bad_Opcode },
3276     { Bad_Opcode },
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { Bad_Opcode },
3280     { Bad_Opcode },
3281     { MOD_TABLE (MOD_C6_REG_7) },
3282   },
3283   /* REG_C7 */
3284   {
3285     { "movQ",   { Evh3, Iv }, 0 },
3286     { Bad_Opcode },
3287     { Bad_Opcode },
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { Bad_Opcode },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_C7_REG_7) },
3293   },
3294   /* REG_D0 */
3295   {
3296     { "rolA",   { Eb, I1 }, 0 },
3297     { "rorA",   { Eb, I1 }, 0 },
3298     { "rclA",   { Eb, I1 }, 0 },
3299     { "rcrA",   { Eb, I1 }, 0 },
3300     { "shlA",   { Eb, I1 }, 0 },
3301     { "shrA",   { Eb, I1 }, 0 },
3302     { "shlA",   { Eb, I1 }, 0 },
3303     { "sarA",   { Eb, I1 }, 0 },
3304   },
3305   /* REG_D1 */
3306   {
3307     { "rolQ",   { Ev, I1 }, 0 },
3308     { "rorQ",   { Ev, I1 }, 0 },
3309     { "rclQ",   { Ev, I1 }, 0 },
3310     { "rcrQ",   { Ev, I1 }, 0 },
3311     { "shlQ",   { Ev, I1 }, 0 },
3312     { "shrQ",   { Ev, I1 }, 0 },
3313     { "shlQ",   { Ev, I1 }, 0 },
3314     { "sarQ",   { Ev, I1 }, 0 },
3315   },
3316   /* REG_D2 */
3317   {
3318     { "rolA",   { Eb, CL }, 0 },
3319     { "rorA",   { Eb, CL }, 0 },
3320     { "rclA",   { Eb, CL }, 0 },
3321     { "rcrA",   { Eb, CL }, 0 },
3322     { "shlA",   { Eb, CL }, 0 },
3323     { "shrA",   { Eb, CL }, 0 },
3324     { "shlA",   { Eb, CL }, 0 },
3325     { "sarA",   { Eb, CL }, 0 },
3326   },
3327   /* REG_D3 */
3328   {
3329     { "rolQ",   { Ev, CL }, 0 },
3330     { "rorQ",   { Ev, CL }, 0 },
3331     { "rclQ",   { Ev, CL }, 0 },
3332     { "rcrQ",   { Ev, CL }, 0 },
3333     { "shlQ",   { Ev, CL }, 0 },
3334     { "shrQ",   { Ev, CL }, 0 },
3335     { "shlQ",   { Ev, CL }, 0 },
3336     { "sarQ",   { Ev, CL }, 0 },
3337   },
3338   /* REG_F6 */
3339   {
3340     { "testA",  { Eb, Ib }, 0 },
3341     { "testA",  { Eb, Ib }, 0 },
3342     { "notA",   { Ebh1 }, 0 },
3343     { "negA",   { Ebh1 }, 0 },
3344     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3345     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3346     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3347     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3348   },
3349   /* REG_F7 */
3350   {
3351     { "testQ",  { Ev, Iv }, 0 },
3352     { "testQ",  { Ev, Iv }, 0 },
3353     { "notQ",   { Evh1 }, 0 },
3354     { "negQ",   { Evh1 }, 0 },
3355     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3356     { "imulQ",  { Ev }, 0 },
3357     { "divQ",   { Ev }, 0 },
3358     { "idivQ",  { Ev }, 0 },
3359   },
3360   /* REG_FE */
3361   {
3362     { "incA",   { Ebh1 }, 0 },
3363     { "decA",   { Ebh1 }, 0 },
3364   },
3365   /* REG_FF */
3366   {
3367     { "incQ",   { Evh1 }, 0 },
3368     { "decQ",   { Evh1 }, 0 },
3369     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3370     { MOD_TABLE (MOD_FF_REG_3) },
3371     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3372     { MOD_TABLE (MOD_FF_REG_5) },
3373     { "pushU",  { stackEv }, 0 },
3374     { Bad_Opcode },
3375   },
3376   /* REG_0F00 */
3377   {
3378     { "sldtD",  { Sv }, 0 },
3379     { "strD",   { Sv }, 0 },
3380     { "lldt",   { Ew }, 0 },
3381     { "ltr",    { Ew }, 0 },
3382     { "verr",   { Ew }, 0 },
3383     { "verw",   { Ew }, 0 },
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386   },
3387   /* REG_0F01 */
3388   {
3389     { MOD_TABLE (MOD_0F01_REG_0) },
3390     { MOD_TABLE (MOD_0F01_REG_1) },
3391     { MOD_TABLE (MOD_0F01_REG_2) },
3392     { MOD_TABLE (MOD_0F01_REG_3) },
3393     { "smswD",  { Sv }, 0 },
3394     { MOD_TABLE (MOD_0F01_REG_5) },
3395     { "lmsw",   { Ew }, 0 },
3396     { MOD_TABLE (MOD_0F01_REG_7) },
3397   },
3398   /* REG_0F0D */
3399   {
3400     { "prefetch",       { Mb }, 0 },
3401     { "prefetchw",      { Mb }, 0 },
3402     { "prefetchwt1",    { Mb }, 0 },
3403     { "prefetch",       { Mb }, 0 },
3404     { "prefetch",       { Mb }, 0 },
3405     { "prefetch",       { Mb }, 0 },
3406     { "prefetch",       { Mb }, 0 },
3407     { "prefetch",       { Mb }, 0 },
3408   },
3409   /* REG_0F18 */
3410   {
3411     { MOD_TABLE (MOD_0F18_REG_0) },
3412     { MOD_TABLE (MOD_0F18_REG_1) },
3413     { MOD_TABLE (MOD_0F18_REG_2) },
3414     { MOD_TABLE (MOD_0F18_REG_3) },
3415     { MOD_TABLE (MOD_0F18_REG_4) },
3416     { MOD_TABLE (MOD_0F18_REG_5) },
3417     { MOD_TABLE (MOD_0F18_REG_6) },
3418     { MOD_TABLE (MOD_0F18_REG_7) },
3419   },
3420   /* REG_0F1C_MOD_0 */
3421   {
3422     { "cldemote",       { Mb }, 0 },
3423     { "nopQ",           { Ev }, 0 },
3424     { "nopQ",           { Ev }, 0 },
3425     { "nopQ",           { Ev }, 0 },
3426     { "nopQ",           { Ev }, 0 },
3427     { "nopQ",           { Ev }, 0 },
3428     { "nopQ",           { Ev }, 0 },
3429     { "nopQ",           { Ev }, 0 },
3430   },
3431   /* REG_0F1E_MOD_3 */
3432   {
3433     { "nopQ",           { Ev }, 0 },
3434     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3435     { "nopQ",           { Ev }, 0 },
3436     { "nopQ",           { Ev }, 0 },
3437     { "nopQ",           { Ev }, 0 },
3438     { "nopQ",           { Ev }, 0 },
3439     { "nopQ",           { Ev }, 0 },
3440     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3441   },
3442   /* REG_0F71 */
3443   {
3444     { Bad_Opcode },
3445     { Bad_Opcode },
3446     { MOD_TABLE (MOD_0F71_REG_2) },
3447     { Bad_Opcode },
3448     { MOD_TABLE (MOD_0F71_REG_4) },
3449     { Bad_Opcode },
3450     { MOD_TABLE (MOD_0F71_REG_6) },
3451   },
3452   /* REG_0F72 */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { MOD_TABLE (MOD_0F72_REG_2) },
3457     { Bad_Opcode },
3458     { MOD_TABLE (MOD_0F72_REG_4) },
3459     { Bad_Opcode },
3460     { MOD_TABLE (MOD_0F72_REG_6) },
3461   },
3462   /* REG_0F73 */
3463   {
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F73_REG_2) },
3467     { MOD_TABLE (MOD_0F73_REG_3) },
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F73_REG_6) },
3471     { MOD_TABLE (MOD_0F73_REG_7) },
3472   },
3473   /* REG_0FA6 */
3474   {
3475     { "montmul",        { { OP_0f07, 0 } }, 0 },
3476     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3477     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3478   },
3479   /* REG_0FA7 */
3480   {
3481     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3482     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3483     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3484     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3485     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3486     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3487   },
3488   /* REG_0FAE */
3489   {
3490     { MOD_TABLE (MOD_0FAE_REG_0) },
3491     { MOD_TABLE (MOD_0FAE_REG_1) },
3492     { MOD_TABLE (MOD_0FAE_REG_2) },
3493     { MOD_TABLE (MOD_0FAE_REG_3) },
3494     { MOD_TABLE (MOD_0FAE_REG_4) },
3495     { MOD_TABLE (MOD_0FAE_REG_5) },
3496     { MOD_TABLE (MOD_0FAE_REG_6) },
3497     { MOD_TABLE (MOD_0FAE_REG_7) },
3498   },
3499   /* REG_0FBA */
3500   {
3501     { Bad_Opcode },
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "btQ",    { Ev, Ib }, 0 },
3506     { "btsQ",   { Evh1, Ib }, 0 },
3507     { "btrQ",   { Evh1, Ib }, 0 },
3508     { "btcQ",   { Evh1, Ib }, 0 },
3509   },
3510   /* REG_0FC7 */
3511   {
3512     { Bad_Opcode },
3513     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_0FC7_REG_3) },
3516     { MOD_TABLE (MOD_0FC7_REG_4) },
3517     { MOD_TABLE (MOD_0FC7_REG_5) },
3518     { MOD_TABLE (MOD_0FC7_REG_6) },
3519     { MOD_TABLE (MOD_0FC7_REG_7) },
3520   },
3521   /* REG_VEX_0F71 */
3522   {
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3528     { Bad_Opcode },
3529     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3530   },
3531   /* REG_VEX_0F72 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3536     { Bad_Opcode },
3537     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3540   },
3541   /* REG_VEX_0F73 */
3542   {
3543     { Bad_Opcode },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3546     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3550     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3551   },
3552   /* REG_VEX_0FAE */
3553   {
3554     { Bad_Opcode },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3557     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3558   },
3559   /* REG_VEX_0F38F3 */
3560   {
3561     { Bad_Opcode },
3562     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3563     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3564     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3565   },
3566   /* REG_XOP_LWPCB */
3567   {
3568     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3569     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3570   },
3571   /* REG_XOP_LWP */
3572   {
3573     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3574     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3575   },
3576   /* REG_XOP_TBM_01 */
3577   {
3578     { Bad_Opcode },
3579     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3580     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3581     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3582     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3583     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3584     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3585     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3586   },
3587   /* REG_XOP_TBM_02 */
3588   {
3589     { Bad_Opcode },
3590     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3596   },
3597 #define NEED_REG_TABLE
3598 #include "i386-dis-evex.h"
3599 #undef NEED_REG_TABLE
3600 };
3601
3602 static const struct dis386 prefix_table[][4] = {
3603   /* PREFIX_90 */
3604   {
3605     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3606     { "pause", { XX }, 0 },
3607     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3608     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3609   },
3610
3611   /* PREFIX_MOD_0_0F01_REG_5 */
3612   {
3613     { Bad_Opcode },
3614     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3615   },
3616
3617   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3618   {
3619     { Bad_Opcode },
3620     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3621   },
3622
3623   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3624   {
3625     { Bad_Opcode },
3626     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3627   },
3628
3629   /* PREFIX_0F09 */
3630   {
3631     { "wbinvd",   { XX }, 0 },
3632     { "wbnoinvd", { XX }, 0 },
3633   },
3634
3635   /* PREFIX_0F10 */
3636   {
3637     { "movups", { XM, EXx }, PREFIX_OPCODE },
3638     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3639     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3640     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3641   },
3642
3643   /* PREFIX_0F11 */
3644   {
3645     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3646     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3647     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3648     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3649   },
3650
3651   /* PREFIX_0F12 */
3652   {
3653     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3654     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3655     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3656     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3657   },
3658
3659   /* PREFIX_0F16 */
3660   {
3661     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3662     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3663     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3664   },
3665
3666   /* PREFIX_0F1A */
3667   {
3668     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3669     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3670     { "bndmov", { Gbnd, Ebnd }, 0 },
3671     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3672   },
3673
3674   /* PREFIX_0F1B */
3675   {
3676     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3677     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3678     { "bndmov", { EbndS, Gbnd }, 0 },
3679     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3680   },
3681
3682   /* PREFIX_0F1C */
3683   {
3684     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3685     { "nopQ",   { Ev }, PREFIX_OPCODE },
3686     { "nopQ",   { Ev }, PREFIX_OPCODE },
3687     { "nopQ",   { Ev }, PREFIX_OPCODE },
3688   },
3689
3690   /* PREFIX_0F1E */
3691   {
3692     { "nopQ",   { Ev }, PREFIX_OPCODE },
3693     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695     { "nopQ",   { Ev }, PREFIX_OPCODE },
3696   },
3697
3698   /* PREFIX_0F2A */
3699   {
3700     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3701     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3702     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3703     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3704   },
3705
3706   /* PREFIX_0F2B */
3707   {
3708     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3709     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3710     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3711     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3712   },
3713
3714   /* PREFIX_0F2C */
3715   {
3716     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3717     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3718     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3719     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3720   },
3721
3722   /* PREFIX_0F2D */
3723   {
3724     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3725     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3726     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3727     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3728   },
3729
3730   /* PREFIX_0F2E */
3731   {
3732     { "ucomiss",{ XM, EXd }, 0 },
3733     { Bad_Opcode },
3734     { "ucomisd",{ XM, EXq }, 0 },
3735   },
3736
3737   /* PREFIX_0F2F */
3738   {
3739     { "comiss", { XM, EXd }, 0 },
3740     { Bad_Opcode },
3741     { "comisd", { XM, EXq }, 0 },
3742   },
3743
3744   /* PREFIX_0F51 */
3745   {
3746     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3747     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3748     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3749     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F52 */
3753   {
3754     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3755     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3756   },
3757
3758   /* PREFIX_0F53 */
3759   {
3760     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3761     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3762   },
3763
3764   /* PREFIX_0F58 */
3765   {
3766     { "addps", { XM, EXx }, PREFIX_OPCODE },
3767     { "addss", { XM, EXd }, PREFIX_OPCODE },
3768     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3769     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3770   },
3771
3772   /* PREFIX_0F59 */
3773   {
3774     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3775     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3776     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3777     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3778   },
3779
3780   /* PREFIX_0F5A */
3781   {
3782     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3783     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3784     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3785     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3786   },
3787
3788   /* PREFIX_0F5B */
3789   {
3790     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3791     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3792     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F5C */
3796   {
3797     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3798     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3799     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3800     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3801   },
3802
3803   /* PREFIX_0F5D */
3804   {
3805     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3806     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3807     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3808     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F5E */
3812   {
3813     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3814     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3815     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3816     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3817   },
3818
3819   /* PREFIX_0F5F */
3820   {
3821     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3822     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3823     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3824     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0F60 */
3828   {
3829     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3830     { Bad_Opcode },
3831     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F61 */
3835   {
3836     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3837     { Bad_Opcode },
3838     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F62 */
3842   {
3843     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3844     { Bad_Opcode },
3845     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F6C */
3849   {
3850     { Bad_Opcode },
3851     { Bad_Opcode },
3852     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F6D */
3856   {
3857     { Bad_Opcode },
3858     { Bad_Opcode },
3859     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F6F */
3863   {
3864     { "movq",   { MX, EM }, PREFIX_OPCODE },
3865     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3866     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F70 */
3870   {
3871     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3872     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3873     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3874     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F73_REG_3 */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "psrldq", { XS, Ib }, 0 },
3882   },
3883
3884   /* PREFIX_0F73_REG_7 */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "pslldq", { XS, Ib }, 0 },
3889   },
3890
3891   /* PREFIX_0F78 */
3892   {
3893     {"vmread",  { Em, Gm }, 0 },
3894     { Bad_Opcode },
3895     {"extrq",   { XS, Ib, Ib }, 0 },
3896     {"insertq", { XM, XS, Ib, Ib }, 0 },
3897   },
3898
3899   /* PREFIX_0F79 */
3900   {
3901     {"vmwrite", { Gm, Em }, 0 },
3902     { Bad_Opcode },
3903     {"extrq",   { XM, XS }, 0 },
3904     {"insertq", { XM, XS }, 0 },
3905   },
3906
3907   /* PREFIX_0F7C */
3908   {
3909     { Bad_Opcode },
3910     { Bad_Opcode },
3911     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3912     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3913   },
3914
3915   /* PREFIX_0F7D */
3916   {
3917     { Bad_Opcode },
3918     { Bad_Opcode },
3919     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3920     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3921   },
3922
3923   /* PREFIX_0F7E */
3924   {
3925     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3926     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3927     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F7F */
3931   {
3932     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3933     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3934     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0FAE_REG_0 */
3938   {
3939     { Bad_Opcode },
3940     { "rdfsbase", { Ev }, 0 },
3941   },
3942
3943   /* PREFIX_0FAE_REG_1 */
3944   {
3945     { Bad_Opcode },
3946     { "rdgsbase", { Ev }, 0 },
3947   },
3948
3949   /* PREFIX_0FAE_REG_2 */
3950   {
3951     { Bad_Opcode },
3952     { "wrfsbase", { Ev }, 0 },
3953   },
3954
3955   /* PREFIX_0FAE_REG_3 */
3956   {
3957     { Bad_Opcode },
3958     { "wrgsbase", { Ev }, 0 },
3959   },
3960
3961   /* PREFIX_MOD_0_0FAE_REG_4 */
3962   {
3963     { "xsave",  { FXSAVE }, 0 },
3964     { "ptwrite%LQ", { Edq }, 0 },
3965   },
3966
3967   /* PREFIX_MOD_3_0FAE_REG_4 */
3968   {
3969     { Bad_Opcode },
3970     { "ptwrite%LQ", { Edq }, 0 },
3971   },
3972
3973   /* PREFIX_MOD_0_0FAE_REG_5 */
3974   {
3975     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_MOD_3_0FAE_REG_5 */
3979   {
3980     { "lfence",         { Skip_MODRM }, 0 },
3981     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3982   },
3983
3984   /* PREFIX_MOD_0_0FAE_REG_6 */
3985   {
3986     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3987     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3988     { "clwb",   { Mb }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_MOD_1_0FAE_REG_6 */
3992   {
3993     { RM_TABLE (RM_0FAE_REG_6) },
3994     { "umonitor",       { Eva }, PREFIX_OPCODE },
3995     { "tpause", { Edq }, PREFIX_OPCODE },
3996     { "umwait", { Edq }, PREFIX_OPCODE },
3997   },
3998
3999   /* PREFIX_0FAE_REG_7 */
4000   {
4001     { "clflush",        { Mb }, 0 },
4002     { Bad_Opcode },
4003     { "clflushopt",     { Mb }, 0 },
4004   },
4005
4006   /* PREFIX_0FB8 */
4007   {
4008     { Bad_Opcode },
4009     { "popcntS", { Gv, Ev }, 0 },
4010   },
4011
4012   /* PREFIX_0FBC */
4013   {
4014     { "bsfS",   { Gv, Ev }, 0 },
4015     { "tzcntS", { Gv, Ev }, 0 },
4016     { "bsfS",   { Gv, Ev }, 0 },
4017   },
4018
4019   /* PREFIX_0FBD */
4020   {
4021     { "bsrS",   { Gv, Ev }, 0 },
4022     { "lzcntS", { Gv, Ev }, 0 },
4023     { "bsrS",   { Gv, Ev }, 0 },
4024   },
4025
4026   /* PREFIX_0FC2 */
4027   {
4028     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4029     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4030     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4031     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_MOD_0_0FC3 */
4035   {
4036     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_MOD_0_0FC7_REG_6 */
4040   {
4041     { "vmptrld",{ Mq }, 0 },
4042     { "vmxon",  { Mq }, 0 },
4043     { "vmclear",{ Mq }, 0 },
4044   },
4045
4046   /* PREFIX_MOD_3_0FC7_REG_6 */
4047   {
4048     { "rdrand", { Ev }, 0 },
4049     { Bad_Opcode },
4050     { "rdrand", { Ev }, 0 }
4051   },
4052
4053   /* PREFIX_MOD_3_0FC7_REG_7 */
4054   {
4055     { "rdseed", { Ev }, 0 },
4056     { "rdpid",  { Em }, 0 },
4057     { "rdseed", { Ev }, 0 },
4058   },
4059
4060   /* PREFIX_0FD0 */
4061   {
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { "addsubpd", { XM, EXx }, 0 },
4065     { "addsubps", { XM, EXx }, 0 },
4066   },
4067
4068   /* PREFIX_0FD6 */
4069   {
4070     { Bad_Opcode },
4071     { "movq2dq",{ XM, MS }, 0 },
4072     { "movq",   { EXqS, XM }, 0 },
4073     { "movdq2q",{ MX, XS }, 0 },
4074   },
4075
4076   /* PREFIX_0FE6 */
4077   {
4078     { Bad_Opcode },
4079     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4080     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4081     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0FE7 */
4085   {
4086     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4087     { Bad_Opcode },
4088     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4089   },
4090
4091   /* PREFIX_0FF0 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4097   },
4098
4099   /* PREFIX_0FF7 */
4100   {
4101     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4102     { Bad_Opcode },
4103     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F3810 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3814 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3815 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3817 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3820 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3821 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3822 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3823 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3824 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3825 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3828 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3829 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F382A */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4195   },
4196
4197   /* PREFIX_0F382B */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3830 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3831 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3832 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3833 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3834 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3835 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3837 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3838 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3839 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F383A */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F383B */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383C */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383D */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383E */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383F */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F3840 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3841 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3880 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3881 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3882 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F38C8 */
4345   {
4346     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F38C9 */
4350   {
4351     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F38CA */
4355   {
4356     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F38CB */
4360   {
4361     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F38CC */
4365   {
4366     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38CD */
4370   {
4371     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38CF */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38DB */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DC */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DD */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DE */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DF */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38F0 */
4417   {
4418     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4419     { Bad_Opcode },
4420     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4421     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F38F1 */
4425   {
4426     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4427     { Bad_Opcode },
4428     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4429     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38F5 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4437   },
4438
4439   /* PREFIX_0F38F6 */
4440   {
4441     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4442     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4443     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4444     { Bad_Opcode },
4445   },
4446
4447   /* PREFIX_0F38F8 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4452   },
4453
4454   /* PREFIX_0F38F9 */
4455   {
4456     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4457   },
4458
4459   /* PREFIX_0F3A08 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F3A09 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A0A */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A0B */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A0C */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A0D */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A0E */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A14 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A15 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A16 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A17 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A20 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A21 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A22 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A40 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A41 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A42 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A44 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A60 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A61 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A62 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A63 */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3ACC */
4614   {
4615     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F3ACE */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F3ACF */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F3ADF */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_VEX_0F10 */
4640   {
4641     { "vmovups",        { XM, EXx }, 0 },
4642     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4643     { "vmovupd",        { XM, EXx }, 0 },
4644     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4645   },
4646
4647   /* PREFIX_VEX_0F11 */
4648   {
4649     { "vmovups",        { EXxS, XM }, 0 },
4650     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4651     { "vmovupd",        { EXxS, XM }, 0 },
4652     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4653   },
4654
4655   /* PREFIX_VEX_0F12 */
4656   {
4657     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4658     { "vmovsldup",      { XM, EXx }, 0 },
4659     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4660     { "vmovddup",       { XM, EXymmq }, 0 },
4661   },
4662
4663   /* PREFIX_VEX_0F16 */
4664   {
4665     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4666     { "vmovshdup",      { XM, EXx }, 0 },
4667     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F2A */
4671   {
4672     { Bad_Opcode },
4673     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4674     { Bad_Opcode },
4675     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4676   },
4677
4678   /* PREFIX_VEX_0F2C */
4679   {
4680     { Bad_Opcode },
4681     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4684   },
4685
4686   /* PREFIX_VEX_0F2D */
4687   {
4688     { Bad_Opcode },
4689     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4690     { Bad_Opcode },
4691     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4692   },
4693
4694   /* PREFIX_VEX_0F2E */
4695   {
4696     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4697     { Bad_Opcode },
4698     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4699   },
4700
4701   /* PREFIX_VEX_0F2F */
4702   {
4703     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4704     { Bad_Opcode },
4705     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4706   },
4707
4708   /* PREFIX_VEX_0F41 */
4709   {
4710     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F42 */
4716   {
4717     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F44 */
4723   {
4724     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F45 */
4730   {
4731     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4734   },
4735
4736   /* PREFIX_VEX_0F46 */
4737   {
4738     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4739     { Bad_Opcode },
4740     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4741   },
4742
4743   /* PREFIX_VEX_0F47 */
4744   {
4745     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F4A */
4751   {
4752     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4753     { Bad_Opcode },
4754     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F4B */
4758   {
4759     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F51 */
4765   {
4766     { "vsqrtps",        { XM, EXx }, 0 },
4767     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4768     { "vsqrtpd",        { XM, EXx }, 0 },
4769     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F52 */
4773   {
4774     { "vrsqrtps",       { XM, EXx }, 0 },
4775     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F53 */
4779   {
4780     { "vrcpps",         { XM, EXx }, 0 },
4781     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4782   },
4783
4784   /* PREFIX_VEX_0F58 */
4785   {
4786     { "vaddps",         { XM, Vex, EXx }, 0 },
4787     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4788     { "vaddpd",         { XM, Vex, EXx }, 0 },
4789     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F59 */
4793   {
4794     { "vmulps",         { XM, Vex, EXx }, 0 },
4795     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4796     { "vmulpd",         { XM, Vex, EXx }, 0 },
4797     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4798   },
4799
4800   /* PREFIX_VEX_0F5A */
4801   {
4802     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4803     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4804     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4805     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F5B */
4809   {
4810     { "vcvtdq2ps",      { XM, EXx }, 0 },
4811     { "vcvttps2dq",     { XM, EXx }, 0 },
4812     { "vcvtps2dq",      { XM, EXx }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F5C */
4816   {
4817     { "vsubps",         { XM, Vex, EXx }, 0 },
4818     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4819     { "vsubpd",         { XM, Vex, EXx }, 0 },
4820     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F5D */
4824   {
4825     { "vminps",         { XM, Vex, EXx }, 0 },
4826     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4827     { "vminpd",         { XM, Vex, EXx }, 0 },
4828     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F5E */
4832   {
4833     { "vdivps",         { XM, Vex, EXx }, 0 },
4834     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4835     { "vdivpd",         { XM, Vex, EXx }, 0 },
4836     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F5F */
4840   {
4841     { "vmaxps",         { XM, Vex, EXx }, 0 },
4842     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4843     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4844     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F60 */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F61 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F62 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F63 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4873   },
4874
4875   /* PREFIX_VEX_0F64 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F65 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4887   },
4888
4889   /* PREFIX_VEX_0F66 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4894   },
4895
4896   /* PREFIX_VEX_0F67 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4901   },
4902
4903   /* PREFIX_VEX_0F68 */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4908   },
4909
4910   /* PREFIX_VEX_0F69 */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4915   },
4916
4917   /* PREFIX_VEX_0F6A */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F6B */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F6C */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4936   },
4937
4938   /* PREFIX_VEX_0F6D */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F6E */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F6F */
4953   {
4954     { Bad_Opcode },
4955     { "vmovdqu",        { XM, EXx }, 0 },
4956     { "vmovdqa",        { XM, EXx }, 0 },
4957   },
4958
4959   /* PREFIX_VEX_0F70 */
4960   {
4961     { Bad_Opcode },
4962     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4963     { "vpshufd",        { XM, EXx, Ib }, 0 },
4964     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F71_REG_2 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4972   },
4973
4974   /* PREFIX_VEX_0F71_REG_4 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { "vpsraw",         { Vex, XS, Ib }, 0 },
4979   },
4980
4981   /* PREFIX_VEX_0F71_REG_6 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { "vpsllw",         { Vex, XS, Ib }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F72_REG_2 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { "vpsrld",         { Vex, XS, Ib }, 0 },
4993   },
4994
4995   /* PREFIX_VEX_0F72_REG_4 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { "vpsrad",         { Vex, XS, Ib }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F72_REG_6 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vpslld",         { Vex, XS, Ib }, 0 },
5007   },
5008
5009   /* PREFIX_VEX_0F73_REG_2 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5014   },
5015
5016   /* PREFIX_VEX_0F73_REG_3 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5021   },
5022
5023   /* PREFIX_VEX_0F73_REG_6 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpsllq",         { Vex, XS, Ib }, 0 },
5028   },
5029
5030   /* PREFIX_VEX_0F73_REG_7 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vpslldq",        { Vex, XS, Ib }, 0 },
5035   },
5036
5037   /* PREFIX_VEX_0F74 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0F75 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5049   },
5050
5051   /* PREFIX_VEX_0F76 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0F77 */
5059   {
5060     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5061   },
5062
5063   /* PREFIX_VEX_0F7C */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5068     { "vhaddps",        { XM, Vex, EXx }, 0 },
5069   },
5070
5071   /* PREFIX_VEX_0F7D */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5076     { "vhsubps",        { XM, Vex, EXx }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0F7E */
5080   {
5081     { Bad_Opcode },
5082     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5083     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5084   },
5085
5086   /* PREFIX_VEX_0F7F */
5087   {
5088     { Bad_Opcode },
5089     { "vmovdqu",        { EXxS, XM }, 0 },
5090     { "vmovdqa",        { EXxS, XM }, 0 },
5091   },
5092
5093   /* PREFIX_VEX_0F90 */
5094   {
5095     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0F91 */
5101   {
5102     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5103     { Bad_Opcode },
5104     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5105   },
5106
5107   /* PREFIX_VEX_0F92 */
5108   {
5109     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5110     { Bad_Opcode },
5111     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5112     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5113   },
5114
5115   /* PREFIX_VEX_0F93 */
5116   {
5117     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5120     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5121   },
5122
5123   /* PREFIX_VEX_0F98 */
5124   {
5125     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F99 */
5131   {
5132     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0FC2 */
5138   {
5139     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5140     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5141     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5142     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5143   },
5144
5145   /* PREFIX_VEX_0FC4 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0FC5 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0FD0 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5164     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5165   },
5166
5167   /* PREFIX_VEX_0FD1 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FD2 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5179   },
5180
5181   /* PREFIX_VEX_0FD3 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5186   },
5187
5188   /* PREFIX_VEX_0FD4 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vpaddq",         { XM, Vex, EXx }, 0 },
5193   },
5194
5195   /* PREFIX_VEX_0FD5 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { "vpmullw",        { XM, Vex, EXx }, 0 },
5200   },
5201
5202   /* PREFIX_VEX_0FD6 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FD7 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5214   },
5215
5216   /* PREFIX_VEX_0FD8 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5221   },
5222
5223   /* PREFIX_VEX_0FD9 */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5228   },
5229
5230   /* PREFIX_VEX_0FDA */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { "vpminub",        { XM, Vex, EXx }, 0 },
5235   },
5236
5237   /* PREFIX_VEX_0FDB */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vpand",          { XM, Vex, EXx }, 0 },
5242   },
5243
5244   /* PREFIX_VEX_0FDC */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5249   },
5250
5251   /* PREFIX_VEX_0FDD */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5256   },
5257
5258   /* PREFIX_VEX_0FDE */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5263   },
5264
5265   /* PREFIX_VEX_0FDF */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vpandn",         { XM, Vex, EXx }, 0 },
5270   },
5271
5272   /* PREFIX_VEX_0FE0 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vpavgb",         { XM, Vex, EXx }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FE1 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FE2 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FE3 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpavgw",         { XM, Vex, EXx }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FE4 */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FE5 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FE6 */
5315   {
5316     { Bad_Opcode },
5317     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5318     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5319     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5320   },
5321
5322   /* PREFIX_VEX_0FE7 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FE8 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5334   },
5335
5336   /* PREFIX_VEX_0FE9 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5341   },
5342
5343   /* PREFIX_VEX_0FEA */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { "vpminsw",        { XM, Vex, EXx }, 0 },
5348   },
5349
5350   /* PREFIX_VEX_0FEB */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { "vpor",           { XM, Vex, EXx }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FEC */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5362   },
5363
5364   /* PREFIX_VEX_0FED */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FEE */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5376   },
5377
5378   /* PREFIX_VEX_0FEF */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { "vpxor",          { XM, Vex, EXx }, 0 },
5383   },
5384
5385   /* PREFIX_VEX_0FF0 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5391   },
5392
5393   /* PREFIX_VEX_0FF1 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5398   },
5399
5400   /* PREFIX_VEX_0FF2 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0FF3 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0FF4 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5419   },
5420
5421   /* PREFIX_VEX_0FF5 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5426   },
5427
5428   /* PREFIX_VEX_0FF6 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0FF7 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0FF8 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { "vpsubb",         { XM, Vex, EXx }, 0 },
5447   },
5448
5449   /* PREFIX_VEX_0FF9 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vpsubw",         { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0FFA */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpsubd",         { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0FFB */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpsubq",         { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0FFC */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vpaddb",         { XM, Vex, EXx }, 0 },
5475   },
5476
5477   /* PREFIX_VEX_0FFD */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpaddw",         { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0FFE */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { "vpaddd",         { XM, Vex, EXx }, 0 },
5489   },
5490
5491   /* PREFIX_VEX_0F3800 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "vpshufb",        { XM, Vex, EXx }, 0 },
5496   },
5497
5498   /* PREFIX_VEX_0F3801 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vphaddw",        { XM, Vex, EXx }, 0 },
5503   },
5504
5505   /* PREFIX_VEX_0F3802 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { "vphaddd",        { XM, Vex, EXx }, 0 },
5510   },
5511
5512   /* PREFIX_VEX_0F3803 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5517   },
5518
5519   /* PREFIX_VEX_0F3804 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5524   },
5525
5526   /* PREFIX_VEX_0F3805 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vphsubw",        { XM, Vex, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3806 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { "vphsubd",        { XM, Vex, EXx }, 0 },
5538   },
5539
5540   /* PREFIX_VEX_0F3807 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5545   },
5546
5547   /* PREFIX_VEX_0F3808 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { "vpsignb",        { XM, Vex, EXx }, 0 },
5552   },
5553
5554   /* PREFIX_VEX_0F3809 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpsignw",        { XM, Vex, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F380A */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { "vpsignd",        { XM, Vex, EXx }, 0 },
5566   },
5567
5568   /* PREFIX_VEX_0F380B */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F380C */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F380D */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F380E */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F380F */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F3813 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5608   },
5609
5610   /* PREFIX_VEX_0F3816 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F3817 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { "vptest",         { XM, EXx }, 0 },
5622   },
5623
5624   /* PREFIX_VEX_0F3818 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F3819 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F381A */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F381C */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { "vpabsb",         { XM, EXx }, 0 },
5650   },
5651
5652   /* PREFIX_VEX_0F381D */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vpabsw",         { XM, EXx }, 0 },
5657   },
5658
5659   /* PREFIX_VEX_0F381E */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { "vpabsd",         { XM, EXx }, 0 },
5664   },
5665
5666   /* PREFIX_VEX_0F3820 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5671   },
5672
5673   /* PREFIX_VEX_0F3821 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5678   },
5679
5680   /* PREFIX_VEX_0F3822 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F3823 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F3824 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3825 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F3828 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5713   },
5714
5715   /* PREFIX_VEX_0F3829 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F382A */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F382B */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5734   },
5735
5736   /* PREFIX_VEX_0F382C */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F382D */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F382E */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F382F */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F3830 */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5769   },
5770
5771   /* PREFIX_VEX_0F3831 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5776   },
5777
5778   /* PREFIX_VEX_0F3832 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5783   },
5784
5785   /* PREFIX_VEX_0F3833 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3834 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5797   },
5798
5799   /* PREFIX_VEX_0F3835 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3836 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3837 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5818   },
5819
5820   /* PREFIX_VEX_0F3838 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { "vpminsb",        { XM, Vex, EXx }, 0 },
5825   },
5826
5827   /* PREFIX_VEX_0F3839 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vpminsd",        { XM, Vex, EXx }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F383A */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { "vpminuw",        { XM, Vex, EXx }, 0 },
5839   },
5840
5841   /* PREFIX_VEX_0F383B */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { "vpminud",        { XM, Vex, EXx }, 0 },
5846   },
5847
5848   /* PREFIX_VEX_0F383C */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5853   },
5854
5855   /* PREFIX_VEX_0F383D */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F383E */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5867   },
5868
5869   /* PREFIX_VEX_0F383F */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F3840 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpmulld",        { XM, Vex, EXx }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F3841 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F3845 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5895   },
5896
5897   /* PREFIX_VEX_0F3846 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3847 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5909   },
5910
5911   /* PREFIX_VEX_0F3858 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F3859 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F385A */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5930   },
5931
5932   /* PREFIX_VEX_0F3878 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3879 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5944   },
5945
5946   /* PREFIX_VEX_0F388C */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F388E */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F3890 */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5965   },
5966
5967   /* PREFIX_VEX_0F3891 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5972   },
5973
5974   /* PREFIX_VEX_0F3892 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5979   },
5980
5981   /* PREFIX_VEX_0F3893 */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5986   },
5987
5988   /* PREFIX_VEX_0F3896 */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5993   },
5994
5995   /* PREFIX_VEX_0F3897 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6000   },
6001
6002   /* PREFIX_VEX_0F3898 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6007   },
6008
6009   /* PREFIX_VEX_0F3899 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6014   },
6015
6016   /* PREFIX_VEX_0F389A */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6021   },
6022
6023   /* PREFIX_VEX_0F389B */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6028   },
6029
6030   /* PREFIX_VEX_0F389C */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6035   },
6036
6037   /* PREFIX_VEX_0F389D */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6042   },
6043
6044   /* PREFIX_VEX_0F389E */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F389F */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F38A6 */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6063     { Bad_Opcode },
6064   },
6065
6066   /* PREFIX_VEX_0F38A7 */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F38A8 */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F38A9 */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F38AA */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F38AB */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F38AC */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38AD */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6113   },
6114
6115   /* PREFIX_VEX_0F38AE */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6120   },
6121
6122   /* PREFIX_VEX_0F38AF */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F38B6 */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F38B7 */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F38B8 */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F38B9 */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F38BA */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F38BB */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F38BC */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F38BD */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F38BE */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F38BF */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F38CF */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6204   },
6205
6206   /* PREFIX_VEX_0F38DB */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6211   },
6212
6213   /* PREFIX_VEX_0F38DC */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vaesenc",        { XM, Vex, EXx }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F38DD */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F38DE */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vaesdec",        { XM, Vex, EXx }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38DF */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6239   },
6240
6241   /* PREFIX_VEX_0F38F2 */
6242   {
6243     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6244   },
6245
6246   /* PREFIX_VEX_0F38F3_REG_1 */
6247   {
6248     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6249   },
6250
6251   /* PREFIX_VEX_0F38F3_REG_2 */
6252   {
6253     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6254   },
6255
6256   /* PREFIX_VEX_0F38F3_REG_3 */
6257   {
6258     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6259   },
6260
6261   /* PREFIX_VEX_0F38F5 */
6262   {
6263     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6264     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6265     { Bad_Opcode },
6266     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6267   },
6268
6269   /* PREFIX_VEX_0F38F6 */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6275   },
6276
6277   /* PREFIX_VEX_0F38F7 */
6278   {
6279     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6280     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6283   },
6284
6285   /* PREFIX_VEX_0F3A00 */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6290   },
6291
6292   /* PREFIX_VEX_0F3A01 */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F3A02 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F3A04 */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6311   },
6312
6313   /* PREFIX_VEX_0F3A05 */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6318   },
6319
6320   /* PREFIX_VEX_0F3A06 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A08 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { "vroundps",       { XM, EXx, Ib }, 0 },
6332   },
6333
6334   /* PREFIX_VEX_0F3A09 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { "vroundpd",       { XM, EXx, Ib }, 0 },
6339   },
6340
6341   /* PREFIX_VEX_0F3A0A */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6346   },
6347
6348   /* PREFIX_VEX_0F3A0B */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6353   },
6354
6355   /* PREFIX_VEX_0F3A0C */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6360   },
6361
6362   /* PREFIX_VEX_0F3A0D */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6367   },
6368
6369   /* PREFIX_VEX_0F3A0E */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6374   },
6375
6376   /* PREFIX_VEX_0F3A0F */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6381   },
6382
6383   /* PREFIX_VEX_0F3A14 */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6388   },
6389
6390   /* PREFIX_VEX_0F3A15 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A16 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A17 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A18 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A19 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A1D */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6430   },
6431
6432   /* PREFIX_VEX_0F3A20 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A21 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A22 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A30 */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A31 */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A32 */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A33 */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A38 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A39 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A40 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6500   },
6501
6502   /* PREFIX_VEX_0F3A41 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A42 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6514   },
6515
6516   /* PREFIX_VEX_0F3A44 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6521   },
6522
6523   /* PREFIX_VEX_0F3A46 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A48 */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6535   },
6536
6537   /* PREFIX_VEX_0F3A49 */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A4A */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6549   },
6550
6551   /* PREFIX_VEX_0F3A4B */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6556   },
6557
6558   /* PREFIX_VEX_0F3A4C */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A5C */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6570   },
6571
6572   /* PREFIX_VEX_0F3A5D */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6577   },
6578
6579   /* PREFIX_VEX_0F3A5E */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6584   },
6585
6586   /* PREFIX_VEX_0F3A5F */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6591   },
6592
6593   /* PREFIX_VEX_0F3A60 */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6598     { Bad_Opcode },
6599   },
6600
6601   /* PREFIX_VEX_0F3A61 */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A62 */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A63 */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6620   },
6621
6622   /* PREFIX_VEX_0F3A68 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6627   },
6628
6629   /* PREFIX_VEX_0F3A69 */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6634   },
6635
6636   /* PREFIX_VEX_0F3A6A */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6641   },
6642
6643   /* PREFIX_VEX_0F3A6B */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A6C */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6655   },
6656
6657   /* PREFIX_VEX_0F3A6D */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6662   },
6663
6664   /* PREFIX_VEX_0F3A6E */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6669   },
6670
6671   /* PREFIX_VEX_0F3A6F */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A78 */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6683   },
6684
6685   /* PREFIX_VEX_0F3A79 */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3A7A */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3A7B */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3A7C */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6711     { Bad_Opcode },
6712   },
6713
6714   /* PREFIX_VEX_0F3A7D */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6719   },
6720
6721   /* PREFIX_VEX_0F3A7E */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6726   },
6727
6728   /* PREFIX_VEX_0F3A7F */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3ACE */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6740   },
6741
6742   /* PREFIX_VEX_0F3ACF */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6747   },
6748
6749   /* PREFIX_VEX_0F3ADF */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6754   },
6755
6756   /* PREFIX_VEX_0F3AF0 */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6762   },
6763
6764 #define NEED_PREFIX_TABLE
6765 #include "i386-dis-evex.h"
6766 #undef NEED_PREFIX_TABLE
6767 };
6768
6769 static const struct dis386 x86_64_table[][2] = {
6770   /* X86_64_06 */
6771   {
6772     { "pushP", { es }, 0 },
6773   },
6774
6775   /* X86_64_07 */
6776   {
6777     { "popP", { es }, 0 },
6778   },
6779
6780   /* X86_64_0D */
6781   {
6782     { "pushP", { cs }, 0 },
6783   },
6784
6785   /* X86_64_16 */
6786   {
6787     { "pushP", { ss }, 0 },
6788   },
6789
6790   /* X86_64_17 */
6791   {
6792     { "popP", { ss }, 0 },
6793   },
6794
6795   /* X86_64_1E */
6796   {
6797     { "pushP", { ds }, 0 },
6798   },
6799
6800   /* X86_64_1F */
6801   {
6802     { "popP", { ds }, 0 },
6803   },
6804
6805   /* X86_64_27 */
6806   {
6807     { "daa", { XX }, 0 },
6808   },
6809
6810   /* X86_64_2F */
6811   {
6812     { "das", { XX }, 0 },
6813   },
6814
6815   /* X86_64_37 */
6816   {
6817     { "aaa", { XX }, 0 },
6818   },
6819
6820   /* X86_64_3F */
6821   {
6822     { "aas", { XX }, 0 },
6823   },
6824
6825   /* X86_64_60 */
6826   {
6827     { "pushaP", { XX }, 0 },
6828   },
6829
6830   /* X86_64_61 */
6831   {
6832     { "popaP", { XX }, 0 },
6833   },
6834
6835   /* X86_64_62 */
6836   {
6837     { MOD_TABLE (MOD_62_32BIT) },
6838     { EVEX_TABLE (EVEX_0F) },
6839   },
6840
6841   /* X86_64_63 */
6842   {
6843     { "arpl", { Ew, Gw }, 0 },
6844     { "movs{lq|xd}", { Gv, Ed }, 0 },
6845   },
6846
6847   /* X86_64_6D */
6848   {
6849     { "ins{R|}", { Yzr, indirDX }, 0 },
6850     { "ins{G|}", { Yzr, indirDX }, 0 },
6851   },
6852
6853   /* X86_64_6F */
6854   {
6855     { "outs{R|}", { indirDXr, Xz }, 0 },
6856     { "outs{G|}", { indirDXr, Xz }, 0 },
6857   },
6858
6859   /* X86_64_82 */
6860   {
6861     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6862     { REG_TABLE (REG_80) },
6863   },
6864
6865   /* X86_64_9A */
6866   {
6867     { "Jcall{T|}", { Ap }, 0 },
6868   },
6869
6870   /* X86_64_C4 */
6871   {
6872     { MOD_TABLE (MOD_C4_32BIT) },
6873     { VEX_C4_TABLE (VEX_0F) },
6874   },
6875
6876   /* X86_64_C5 */
6877   {
6878     { MOD_TABLE (MOD_C5_32BIT) },
6879     { VEX_C5_TABLE (VEX_0F) },
6880   },
6881
6882   /* X86_64_CE */
6883   {
6884     { "into", { XX }, 0 },
6885   },
6886
6887   /* X86_64_D4 */
6888   {
6889     { "aam", { Ib }, 0 },
6890   },
6891
6892   /* X86_64_D5 */
6893   {
6894     { "aad", { Ib }, 0 },
6895   },
6896
6897   /* X86_64_E8 */
6898   {
6899     { "callP",          { Jv, BND }, 0 },
6900     { "call@",          { Jv, BND }, 0 }
6901   },
6902
6903   /* X86_64_E9 */
6904   {
6905     { "jmpP",           { Jv, BND }, 0 },
6906     { "jmp@",           { Jv, BND }, 0 }
6907   },
6908
6909   /* X86_64_EA */
6910   {
6911     { "Jjmp{T|}", { Ap }, 0 },
6912   },
6913
6914   /* X86_64_0F01_REG_0 */
6915   {
6916     { "sgdt{Q|IQ}", { M }, 0 },
6917     { "sgdt", { M }, 0 },
6918   },
6919
6920   /* X86_64_0F01_REG_1 */
6921   {
6922     { "sidt{Q|IQ}", { M }, 0 },
6923     { "sidt", { M }, 0 },
6924   },
6925
6926   /* X86_64_0F01_REG_2 */
6927   {
6928     { "lgdt{Q|Q}", { M }, 0 },
6929     { "lgdt", { M }, 0 },
6930   },
6931
6932   /* X86_64_0F01_REG_3 */
6933   {
6934     { "lidt{Q|Q}", { M }, 0 },
6935     { "lidt", { M }, 0 },
6936   },
6937 };
6938
6939 static const struct dis386 three_byte_table[][256] = {
6940
6941   /* THREE_BYTE_0F38 */
6942   {
6943     /* 00 */
6944     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6945     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6946     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6947     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6948     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6949     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6950     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6951     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6952     /* 08 */
6953     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6954     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6955     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6956     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 10 */
6962     { PREFIX_TABLE (PREFIX_0F3810) },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { PREFIX_TABLE (PREFIX_0F3814) },
6967     { PREFIX_TABLE (PREFIX_0F3815) },
6968     { Bad_Opcode },
6969     { PREFIX_TABLE (PREFIX_0F3817) },
6970     /* 18 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6976     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6977     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6978     { Bad_Opcode },
6979     /* 20 */
6980     { PREFIX_TABLE (PREFIX_0F3820) },
6981     { PREFIX_TABLE (PREFIX_0F3821) },
6982     { PREFIX_TABLE (PREFIX_0F3822) },
6983     { PREFIX_TABLE (PREFIX_0F3823) },
6984     { PREFIX_TABLE (PREFIX_0F3824) },
6985     { PREFIX_TABLE (PREFIX_0F3825) },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 28 */
6989     { PREFIX_TABLE (PREFIX_0F3828) },
6990     { PREFIX_TABLE (PREFIX_0F3829) },
6991     { PREFIX_TABLE (PREFIX_0F382A) },
6992     { PREFIX_TABLE (PREFIX_0F382B) },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 30 */
6998     { PREFIX_TABLE (PREFIX_0F3830) },
6999     { PREFIX_TABLE (PREFIX_0F3831) },
7000     { PREFIX_TABLE (PREFIX_0F3832) },
7001     { PREFIX_TABLE (PREFIX_0F3833) },
7002     { PREFIX_TABLE (PREFIX_0F3834) },
7003     { PREFIX_TABLE (PREFIX_0F3835) },
7004     { Bad_Opcode },
7005     { PREFIX_TABLE (PREFIX_0F3837) },
7006     /* 38 */
7007     { PREFIX_TABLE (PREFIX_0F3838) },
7008     { PREFIX_TABLE (PREFIX_0F3839) },
7009     { PREFIX_TABLE (PREFIX_0F383A) },
7010     { PREFIX_TABLE (PREFIX_0F383B) },
7011     { PREFIX_TABLE (PREFIX_0F383C) },
7012     { PREFIX_TABLE (PREFIX_0F383D) },
7013     { PREFIX_TABLE (PREFIX_0F383E) },
7014     { PREFIX_TABLE (PREFIX_0F383F) },
7015     /* 40 */
7016     { PREFIX_TABLE (PREFIX_0F3840) },
7017     { PREFIX_TABLE (PREFIX_0F3841) },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 48 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 50 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 58 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 60 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* 68 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* 70 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* 78 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* 80 */
7088     { PREFIX_TABLE (PREFIX_0F3880) },
7089     { PREFIX_TABLE (PREFIX_0F3881) },
7090     { PREFIX_TABLE (PREFIX_0F3882) },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* 88 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* 90 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* 98 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* a0 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* a8 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* b0 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* b8 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* c0 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* c8 */
7169     { PREFIX_TABLE (PREFIX_0F38C8) },
7170     { PREFIX_TABLE (PREFIX_0F38C9) },
7171     { PREFIX_TABLE (PREFIX_0F38CA) },
7172     { PREFIX_TABLE (PREFIX_0F38CB) },
7173     { PREFIX_TABLE (PREFIX_0F38CC) },
7174     { PREFIX_TABLE (PREFIX_0F38CD) },
7175     { Bad_Opcode },
7176     { PREFIX_TABLE (PREFIX_0F38CF) },
7177     /* d0 */
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     /* d8 */
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { PREFIX_TABLE (PREFIX_0F38DB) },
7191     { PREFIX_TABLE (PREFIX_0F38DC) },
7192     { PREFIX_TABLE (PREFIX_0F38DD) },
7193     { PREFIX_TABLE (PREFIX_0F38DE) },
7194     { PREFIX_TABLE (PREFIX_0F38DF) },
7195     /* e0 */
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* e8 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* f0 */
7214     { PREFIX_TABLE (PREFIX_0F38F0) },
7215     { PREFIX_TABLE (PREFIX_0F38F1) },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { PREFIX_TABLE (PREFIX_0F38F5) },
7220     { PREFIX_TABLE (PREFIX_0F38F6) },
7221     { Bad_Opcode },
7222     /* f8 */
7223     { PREFIX_TABLE (PREFIX_0F38F8) },
7224     { PREFIX_TABLE (PREFIX_0F38F9) },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231   },
7232   /* THREE_BYTE_0F3A */
7233   {
7234     /* 00 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 08 */
7244     { PREFIX_TABLE (PREFIX_0F3A08) },
7245     { PREFIX_TABLE (PREFIX_0F3A09) },
7246     { PREFIX_TABLE (PREFIX_0F3A0A) },
7247     { PREFIX_TABLE (PREFIX_0F3A0B) },
7248     { PREFIX_TABLE (PREFIX_0F3A0C) },
7249     { PREFIX_TABLE (PREFIX_0F3A0D) },
7250     { PREFIX_TABLE (PREFIX_0F3A0E) },
7251     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7252     /* 10 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { PREFIX_TABLE (PREFIX_0F3A14) },
7258     { PREFIX_TABLE (PREFIX_0F3A15) },
7259     { PREFIX_TABLE (PREFIX_0F3A16) },
7260     { PREFIX_TABLE (PREFIX_0F3A17) },
7261     /* 18 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 20 */
7271     { PREFIX_TABLE (PREFIX_0F3A20) },
7272     { PREFIX_TABLE (PREFIX_0F3A21) },
7273     { PREFIX_TABLE (PREFIX_0F3A22) },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 28 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 30 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 38 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 40 */
7307     { PREFIX_TABLE (PREFIX_0F3A40) },
7308     { PREFIX_TABLE (PREFIX_0F3A41) },
7309     { PREFIX_TABLE (PREFIX_0F3A42) },
7310     { Bad_Opcode },
7311     { PREFIX_TABLE (PREFIX_0F3A44) },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 48 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 50 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 58 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 60 */
7343     { PREFIX_TABLE (PREFIX_0F3A60) },
7344     { PREFIX_TABLE (PREFIX_0F3A61) },
7345     { PREFIX_TABLE (PREFIX_0F3A62) },
7346     { PREFIX_TABLE (PREFIX_0F3A63) },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 68 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* 70 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 78 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 80 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 88 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* 90 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 98 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* a0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* a8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* b0 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* b8 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* c0 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* c8 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { PREFIX_TABLE (PREFIX_0F3ACC) },
7465     { Bad_Opcode },
7466     { PREFIX_TABLE (PREFIX_0F3ACE) },
7467     { PREFIX_TABLE (PREFIX_0F3ACF) },
7468     /* d0 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* d8 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { PREFIX_TABLE (PREFIX_0F3ADF) },
7486     /* e0 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* e8 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* f0 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* f8 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522   },
7523 };
7524
7525 static const struct dis386 xop_table[][256] = {
7526   /* XOP_08 */
7527   {
7528     /* 00 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 08 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 10 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 18 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 20 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 28 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 30 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 38 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 40 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 48 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 50 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 58 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* 60 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* 68 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* 70 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* 78 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* 80 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7679     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7680     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7681     /* 88 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7689     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7690     /* 90 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7698     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7699     /* 98 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7708     /* a0 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7716     { Bad_Opcode },
7717     /* a8 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* b0 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7734     { Bad_Opcode },
7735     /* b8 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* c0 */
7745     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7746     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7747     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7748     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     /* c8 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7759     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7760     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7761     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7762     /* d0 */
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* d8 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     /* e0 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     /* e8 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7795     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7796     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7797     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7798     /* f0 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     /* f8 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816   },
7817   /* XOP_09 */
7818   {
7819     /* 00 */
7820     { Bad_Opcode },
7821     { REG_TABLE (REG_XOP_TBM_01) },
7822     { REG_TABLE (REG_XOP_TBM_02) },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 08 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 10 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { REG_TABLE (REG_XOP_LWPCB) },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 18 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 20 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 28 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 30 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 38 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 40 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 48 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 50 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 58 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 60 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* 68 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* 70 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* 78 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* 80 */
7964     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7965     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7966     { "vfrczss",        { XM, EXd }, 0 },
7967     { "vfrczsd",        { XM, EXq }, 0 },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* 88 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* 90 */
7982     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     /* 98 */
7991     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* a0 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* a8 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* b0 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* b8 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* c0 */
8036     { Bad_Opcode },
8037     { "vphaddbw",       { XM, EXxmm }, 0 },
8038     { "vphaddbd",       { XM, EXxmm }, 0 },
8039     { "vphaddbq",       { XM, EXxmm }, 0 },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { "vphaddwd",       { XM, EXxmm }, 0 },
8043     { "vphaddwq",       { XM, EXxmm }, 0 },
8044     /* c8 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { "vphadddq",       { XM, EXxmm }, 0 },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* d0 */
8054     { Bad_Opcode },
8055     { "vphaddubw",      { XM, EXxmm }, 0 },
8056     { "vphaddubd",      { XM, EXxmm }, 0 },
8057     { "vphaddubq",      { XM, EXxmm }, 0 },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { "vphadduwd",      { XM, EXxmm }, 0 },
8061     { "vphadduwq",      { XM, EXxmm }, 0 },
8062     /* d8 */
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { "vphaddudq",      { XM, EXxmm }, 0 },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* e0 */
8072     { Bad_Opcode },
8073     { "vphsubbw",       { XM, EXxmm }, 0 },
8074     { "vphsubwd",       { XM, EXxmm }, 0 },
8075     { "vphsubdq",       { XM, EXxmm }, 0 },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* e8 */
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     /* f0 */
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* f8 */
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107   },
8108   /* XOP_0A */
8109   {
8110     /* 00 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 08 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 10 */
8129     { "bextr",  { Gv, Ev, Iq }, 0 },
8130     { Bad_Opcode },
8131     { REG_TABLE (REG_XOP_LWP) },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 18 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 20 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 28 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 30 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 38 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 40 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 48 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 50 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* 58 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 60 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 68 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* 70 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* 78 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* 80 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* 88 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* 90 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* 98 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* a0 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* a8 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* b0 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* b8 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* c0 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* c8 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* d0 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* d8 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* e0 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* e8 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* f0 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* f8 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398   },
8399 };
8400
8401 static const struct dis386 vex_table[][256] = {
8402   /* VEX_0F */
8403   {
8404     /* 00 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* 08 */
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     /* 10 */
8423     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8426     { MOD_TABLE (MOD_VEX_0F13) },
8427     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8428     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8429     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8430     { MOD_TABLE (MOD_VEX_0F17) },
8431     /* 18 */
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     /* 20 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     /* 28 */
8450     { "vmovapX",        { XM, EXx }, 0 },
8451     { "vmovapX",        { EXxS, XM }, 0 },
8452     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8453     { MOD_TABLE (MOD_VEX_0F2B) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8458     /* 30 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 38 */
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 40 */
8477     { Bad_Opcode },
8478     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8479     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8480     { Bad_Opcode },
8481     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8485     /* 48 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* 50 */
8495     { MOD_TABLE (MOD_VEX_0F50) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8497     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8499     { "vandpX",         { XM, Vex, EXx }, 0 },
8500     { "vandnpX",        { XM, Vex, EXx }, 0 },
8501     { "vorpX",          { XM, Vex, EXx }, 0 },
8502     { "vxorpX",         { XM, Vex, EXx }, 0 },
8503     /* 58 */
8504     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8511     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8512     /* 60 */
8513     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8521     /* 68 */
8522     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8530     /* 70 */
8531     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8532     { REG_TABLE (REG_VEX_0F71) },
8533     { REG_TABLE (REG_VEX_0F72) },
8534     { REG_TABLE (REG_VEX_0F73) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8539     /* 78 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8548     /* 80 */
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     /* 88 */
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     /* 90 */
8567     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     /* 98 */
8576     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     /* a0 */
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     /* a8 */
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { REG_TABLE (REG_VEX_0FAE) },
8601     { Bad_Opcode },
8602     /* b0 */
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     /* b8 */
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     /* c0 */
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8624     { Bad_Opcode },
8625     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8626     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8627     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8628     { Bad_Opcode },
8629     /* c8 */
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     /* d0 */
8639     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8641     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8647     /* d8 */
8648     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8656     /* e0 */
8657     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8664     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8665     /* e8 */
8666     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8674     /* f0 */
8675     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8683     /* f8 */
8684     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8691     { Bad_Opcode },
8692   },
8693   /* VEX_0F38 */
8694   {
8695     /* 00 */
8696     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8704     /* 08 */
8705     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8713     /* 10 */
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8722     /* 18 */
8723     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8726     { Bad_Opcode },
8727     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8730     { Bad_Opcode },
8731     /* 20 */
8732     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 28 */
8741     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8749     /* 30 */
8750     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8758     /* 38 */
8759     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8767     /* 40 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8776     /* 48 */
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     /* 50 */
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     /* 58 */
8795     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     /* 60 */
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     /* 68 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* 70 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* 78 */
8831     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* 80 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     /* 88 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8854     { Bad_Opcode },
8855     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8856     { Bad_Opcode },
8857     /* 90 */
8858     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8866     /* 98 */
8867     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8875     /* a0 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8884     /* a8 */
8885     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8893     /* b0 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8902     /* b8 */
8903     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8911     /* c0 */
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     /* c8 */
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8929     /* d0 */
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     /* d8 */
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8947     /* e0 */
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     /* e8 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     /* f0 */
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8969     { REG_TABLE (REG_VEX_0F38F3) },
8970     { Bad_Opcode },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8974     /* f8 */
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983   },
8984   /* VEX_0F3A */
8985   {
8986     /* 00 */
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8990     { Bad_Opcode },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8994     { Bad_Opcode },
8995     /* 08 */
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9004     /* 10 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9013     /* 18 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 20 */
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     /* 28 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 30 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 38 */
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 40 */
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9062     { Bad_Opcode },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9064     { Bad_Opcode },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9066     { Bad_Opcode },
9067     /* 48 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* 50 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* 58 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9094     /* 60 */
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* 68 */
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9112     /* 70 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* 78 */
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9130     /* 80 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* 88 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* 90 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* 98 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* a0 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* a8 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* b0 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     /* b8 */
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* c0 */
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* c8 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9219     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9220     /* d0 */
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     /* d8 */
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9238     /* e0 */
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     /* e8 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     /* f0 */
9257     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     /* f8 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274   },
9275 };
9276
9277 #define NEED_OPCODE_TABLE
9278 #include "i386-dis-evex.h"
9279 #undef NEED_OPCODE_TABLE
9280 static const struct dis386 vex_len_table[][2] = {
9281   /* VEX_LEN_0F12_P_0_M_0 */
9282   {
9283     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9284   },
9285
9286   /* VEX_LEN_0F12_P_0_M_1 */
9287   {
9288     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9289   },
9290
9291   /* VEX_LEN_0F12_P_2 */
9292   {
9293     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9294   },
9295
9296   /* VEX_LEN_0F13_M_0 */
9297   {
9298     { "vmovlpX",        { EXq, XM }, 0 },
9299   },
9300
9301   /* VEX_LEN_0F16_P_0_M_0 */
9302   {
9303     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F16_P_0_M_1 */
9307   {
9308     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F16_P_2 */
9312   {
9313     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9314   },
9315
9316   /* VEX_LEN_0F17_M_0 */
9317   {
9318     { "vmovhpX",        { EXq, XM }, 0 },
9319   },
9320
9321   /* VEX_LEN_0F2A_P_1 */
9322   {
9323     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9324     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9325   },
9326
9327   /* VEX_LEN_0F2A_P_3 */
9328   {
9329     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9330     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F2C_P_1 */
9334   {
9335     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9336     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9337   },
9338
9339   /* VEX_LEN_0F2C_P_3 */
9340   {
9341     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9342     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F2D_P_1 */
9346   {
9347     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9348     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9349   },
9350
9351   /* VEX_LEN_0F2D_P_3 */
9352   {
9353     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9354     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9355   },
9356
9357   /* VEX_LEN_0F41_P_0 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9361   },
9362   /* VEX_LEN_0F41_P_2 */
9363   {
9364     { Bad_Opcode },
9365     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9366   },
9367   /* VEX_LEN_0F42_P_0 */
9368   {
9369     { Bad_Opcode },
9370     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9371   },
9372   /* VEX_LEN_0F42_P_2 */
9373   {
9374     { Bad_Opcode },
9375     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9376   },
9377   /* VEX_LEN_0F44_P_0 */
9378   {
9379     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9380   },
9381   /* VEX_LEN_0F44_P_2 */
9382   {
9383     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9384   },
9385   /* VEX_LEN_0F45_P_0 */
9386   {
9387     { Bad_Opcode },
9388     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9389   },
9390   /* VEX_LEN_0F45_P_2 */
9391   {
9392     { Bad_Opcode },
9393     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9394   },
9395   /* VEX_LEN_0F46_P_0 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9399   },
9400   /* VEX_LEN_0F46_P_2 */
9401   {
9402     { Bad_Opcode },
9403     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9404   },
9405   /* VEX_LEN_0F47_P_0 */
9406   {
9407     { Bad_Opcode },
9408     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9409   },
9410   /* VEX_LEN_0F47_P_2 */
9411   {
9412     { Bad_Opcode },
9413     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9414   },
9415   /* VEX_LEN_0F4A_P_0 */
9416   {
9417     { Bad_Opcode },
9418     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9419   },
9420   /* VEX_LEN_0F4A_P_2 */
9421   {
9422     { Bad_Opcode },
9423     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9424   },
9425   /* VEX_LEN_0F4B_P_0 */
9426   {
9427     { Bad_Opcode },
9428     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9429   },
9430   /* VEX_LEN_0F4B_P_2 */
9431   {
9432     { Bad_Opcode },
9433     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9434   },
9435
9436   /* VEX_LEN_0F6E_P_2 */
9437   {
9438     { "vmovK",          { XMScalar, Edq }, 0 },
9439   },
9440
9441   /* VEX_LEN_0F77_P_1 */
9442   {
9443     { "vzeroupper",     { XX }, 0 },
9444     { "vzeroall",       { XX }, 0 },
9445   },
9446
9447   /* VEX_LEN_0F7E_P_1 */
9448   {
9449     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9450   },
9451
9452   /* VEX_LEN_0F7E_P_2 */
9453   {
9454     { "vmovK",          { Edq, XMScalar }, 0 },
9455   },
9456
9457   /* VEX_LEN_0F90_P_0 */
9458   {
9459     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9460   },
9461
9462   /* VEX_LEN_0F90_P_2 */
9463   {
9464     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9465   },
9466
9467   /* VEX_LEN_0F91_P_0 */
9468   {
9469     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9470   },
9471
9472   /* VEX_LEN_0F91_P_2 */
9473   {
9474     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9475   },
9476
9477   /* VEX_LEN_0F92_P_0 */
9478   {
9479     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9480   },
9481
9482   /* VEX_LEN_0F92_P_2 */
9483   {
9484     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9485   },
9486
9487   /* VEX_LEN_0F92_P_3 */
9488   {
9489     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9490   },
9491
9492   /* VEX_LEN_0F93_P_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9495   },
9496
9497   /* VEX_LEN_0F93_P_2 */
9498   {
9499     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9500   },
9501
9502   /* VEX_LEN_0F93_P_3 */
9503   {
9504     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9505   },
9506
9507   /* VEX_LEN_0F98_P_0 */
9508   {
9509     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9510   },
9511
9512   /* VEX_LEN_0F98_P_2 */
9513   {
9514     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9515   },
9516
9517   /* VEX_LEN_0F99_P_0 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9520   },
9521
9522   /* VEX_LEN_0F99_P_2 */
9523   {
9524     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9525   },
9526
9527   /* VEX_LEN_0FAE_R_2_M_0 */
9528   {
9529     { "vldmxcsr",       { Md }, 0 },
9530   },
9531
9532   /* VEX_LEN_0FAE_R_3_M_0 */
9533   {
9534     { "vstmxcsr",       { Md }, 0 },
9535   },
9536
9537   /* VEX_LEN_0FC4_P_2 */
9538   {
9539     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9540   },
9541
9542   /* VEX_LEN_0FC5_P_2 */
9543   {
9544     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9545   },
9546
9547   /* VEX_LEN_0FD6_P_2 */
9548   {
9549     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9550   },
9551
9552   /* VEX_LEN_0FF7_P_2 */
9553   {
9554     { "vmaskmovdqu",    { XM, XS }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F3816_P_2 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9561   },
9562
9563   /* VEX_LEN_0F3819_P_2 */
9564   {
9565     { Bad_Opcode },
9566     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9567   },
9568
9569   /* VEX_LEN_0F381A_P_2_M_0 */
9570   {
9571     { Bad_Opcode },
9572     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9573   },
9574
9575   /* VEX_LEN_0F3836_P_2 */
9576   {
9577     { Bad_Opcode },
9578     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9579   },
9580
9581   /* VEX_LEN_0F3841_P_2 */
9582   {
9583     { "vphminposuw",    { XM, EXx }, 0 },
9584   },
9585
9586   /* VEX_LEN_0F385A_P_2_M_0 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9590   },
9591
9592   /* VEX_LEN_0F38DB_P_2 */
9593   {
9594     { "vaesimc",        { XM, EXx }, 0 },
9595   },
9596
9597   /* VEX_LEN_0F38F2_P_0 */
9598   {
9599     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9600   },
9601
9602   /* VEX_LEN_0F38F3_R_1_P_0 */
9603   {
9604     { "blsrS",          { VexGdq, Edq }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F38F3_R_2_P_0 */
9608   {
9609     { "blsmskS",        { VexGdq, Edq }, 0 },
9610   },
9611
9612   /* VEX_LEN_0F38F3_R_3_P_0 */
9613   {
9614     { "blsiS",          { VexGdq, Edq }, 0 },
9615   },
9616
9617   /* VEX_LEN_0F38F5_P_0 */
9618   {
9619     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F38F5_P_1 */
9623   {
9624     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F38F5_P_3 */
9628   {
9629     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F38F6_P_3 */
9633   {
9634     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F38F7_P_0 */
9638   {
9639     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F38F7_P_1 */
9643   {
9644     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F38F7_P_2 */
9648   {
9649     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9650   },
9651
9652   /* VEX_LEN_0F38F7_P_3 */
9653   {
9654     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9655   },
9656
9657   /* VEX_LEN_0F3A00_P_2 */
9658   {
9659     { Bad_Opcode },
9660     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9661   },
9662
9663   /* VEX_LEN_0F3A01_P_2 */
9664   {
9665     { Bad_Opcode },
9666     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9667   },
9668
9669   /* VEX_LEN_0F3A06_P_2 */
9670   {
9671     { Bad_Opcode },
9672     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9673   },
9674
9675   /* VEX_LEN_0F3A14_P_2 */
9676   {
9677     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9678   },
9679
9680   /* VEX_LEN_0F3A15_P_2 */
9681   {
9682     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9683   },
9684
9685   /* VEX_LEN_0F3A16_P_2  */
9686   {
9687     { "vpextrK",        { Edq, XM, Ib }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F3A17_P_2 */
9691   {
9692     { "vextractps",     { Edqd, XM, Ib }, 0 },
9693   },
9694
9695   /* VEX_LEN_0F3A18_P_2 */
9696   {
9697     { Bad_Opcode },
9698     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9699   },
9700
9701   /* VEX_LEN_0F3A19_P_2 */
9702   {
9703     { Bad_Opcode },
9704     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9705   },
9706
9707   /* VEX_LEN_0F3A20_P_2 */
9708   {
9709     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9710   },
9711
9712   /* VEX_LEN_0F3A21_P_2 */
9713   {
9714     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9715   },
9716
9717   /* VEX_LEN_0F3A22_P_2 */
9718   {
9719     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F3A30_P_2 */
9723   {
9724     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9725   },
9726
9727   /* VEX_LEN_0F3A31_P_2 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9730   },
9731
9732   /* VEX_LEN_0F3A32_P_2 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9735   },
9736
9737   /* VEX_LEN_0F3A33_P_2 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9740   },
9741
9742   /* VEX_LEN_0F3A38_P_2 */
9743   {
9744     { Bad_Opcode },
9745     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9746   },
9747
9748   /* VEX_LEN_0F3A39_P_2 */
9749   {
9750     { Bad_Opcode },
9751     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9752   },
9753
9754   /* VEX_LEN_0F3A41_P_2 */
9755   {
9756     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9757   },
9758
9759   /* VEX_LEN_0F3A46_P_2 */
9760   {
9761     { Bad_Opcode },
9762     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9763   },
9764
9765   /* VEX_LEN_0F3A60_P_2 */
9766   {
9767     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9768   },
9769
9770   /* VEX_LEN_0F3A61_P_2 */
9771   {
9772     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9773   },
9774
9775   /* VEX_LEN_0F3A62_P_2 */
9776   {
9777     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A63_P_2 */
9781   {
9782     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9783   },
9784
9785   /* VEX_LEN_0F3A6A_P_2 */
9786   {
9787     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9788   },
9789
9790   /* VEX_LEN_0F3A6B_P_2 */
9791   {
9792     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9793   },
9794
9795   /* VEX_LEN_0F3A6E_P_2 */
9796   {
9797     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9798   },
9799
9800   /* VEX_LEN_0F3A6F_P_2 */
9801   {
9802     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9803   },
9804
9805   /* VEX_LEN_0F3A7A_P_2 */
9806   {
9807     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9808   },
9809
9810   /* VEX_LEN_0F3A7B_P_2 */
9811   {
9812     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9813   },
9814
9815   /* VEX_LEN_0F3A7E_P_2 */
9816   {
9817     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9818   },
9819
9820   /* VEX_LEN_0F3A7F_P_2 */
9821   {
9822     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9823   },
9824
9825   /* VEX_LEN_0F3ADF_P_2 */
9826   {
9827     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9828   },
9829
9830   /* VEX_LEN_0F3AF0_P_3 */
9831   {
9832     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9833   },
9834
9835   /* VEX_LEN_0FXOP_08_CC */
9836   {
9837      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9838   },
9839
9840   /* VEX_LEN_0FXOP_08_CD */
9841   {
9842      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9843   },
9844
9845   /* VEX_LEN_0FXOP_08_CE */
9846   {
9847      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9848   },
9849
9850   /* VEX_LEN_0FXOP_08_CF */
9851   {
9852      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9853   },
9854
9855   /* VEX_LEN_0FXOP_08_EC */
9856   {
9857      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_08_ED */
9861   {
9862      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9863   },
9864
9865   /* VEX_LEN_0FXOP_08_EE */
9866   {
9867      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9868   },
9869
9870   /* VEX_LEN_0FXOP_08_EF */
9871   {
9872      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9873   },
9874
9875   /* VEX_LEN_0FXOP_09_80 */
9876   {
9877     { "vfrczps",        { XM, EXxmm }, 0 },
9878     { "vfrczps",        { XM, EXymmq }, 0 },
9879   },
9880
9881   /* VEX_LEN_0FXOP_09_81 */
9882   {
9883     { "vfrczpd",        { XM, EXxmm }, 0 },
9884     { "vfrczpd",        { XM, EXymmq }, 0 },
9885   },
9886 };
9887
9888 static const struct dis386 evex_len_table[][3] = {
9889 #define NEED_EVEX_LEN_TABLE
9890 #include "i386-dis-evex.h"
9891 #undef NEED_EVEX_LEN_TABLE
9892 };
9893
9894 static const struct dis386 vex_w_table[][2] = {
9895   {
9896     /* VEX_W_0F41_P_0_LEN_1 */
9897     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9898     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9899   },
9900   {
9901     /* VEX_W_0F41_P_2_LEN_1 */
9902     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9903     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9904   },
9905   {
9906     /* VEX_W_0F42_P_0_LEN_1 */
9907     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9908     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9909   },
9910   {
9911     /* VEX_W_0F42_P_2_LEN_1 */
9912     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9913     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9914   },
9915   {
9916     /* VEX_W_0F44_P_0_LEN_0 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F44_P_2_LEN_0 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9924   },
9925   {
9926     /* VEX_W_0F45_P_0_LEN_1 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9928     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9929   },
9930   {
9931     /* VEX_W_0F45_P_2_LEN_1 */
9932     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9933     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9934   },
9935   {
9936     /* VEX_W_0F46_P_0_LEN_1 */
9937     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9938     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9939   },
9940   {
9941     /* VEX_W_0F46_P_2_LEN_1 */
9942     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9943     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9944   },
9945   {
9946     /* VEX_W_0F47_P_0_LEN_1 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9948     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9949   },
9950   {
9951     /* VEX_W_0F47_P_2_LEN_1 */
9952     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9953     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9954   },
9955   {
9956     /* VEX_W_0F4A_P_0_LEN_1 */
9957     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9958     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9959   },
9960   {
9961     /* VEX_W_0F4A_P_2_LEN_1 */
9962     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9963     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9964   },
9965   {
9966     /* VEX_W_0F4B_P_0_LEN_1 */
9967     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9968     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9969   },
9970   {
9971     /* VEX_W_0F4B_P_2_LEN_1 */
9972     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F90_P_0_LEN_0 */
9976     { "kmovw",          { MaskG, MaskE }, 0 },
9977     { "kmovq",          { MaskG, MaskE }, 0 },
9978   },
9979   {
9980     /* VEX_W_0F90_P_2_LEN_0 */
9981     { "kmovb",          { MaskG, MaskBDE }, 0 },
9982     { "kmovd",          { MaskG, MaskBDE }, 0 },
9983   },
9984   {
9985     /* VEX_W_0F91_P_0_LEN_0 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9987     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F91_P_2_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9992     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9993   },
9994   {
9995     /* VEX_W_0F92_P_0_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F92_P_2_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F92_P_3_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10005     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F93_P_0_LEN_0 */
10009     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10010   },
10011   {
10012     /* VEX_W_0F93_P_2_LEN_0 */
10013     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10014   },
10015   {
10016     /* VEX_W_0F93_P_3_LEN_0 */
10017     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10018     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10019   },
10020   {
10021     /* VEX_W_0F98_P_0_LEN_0 */
10022     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10023     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F98_P_2_LEN_0 */
10027     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10028     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F99_P_0_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10033     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10034   },
10035   {
10036     /* VEX_W_0F99_P_2_LEN_0 */
10037     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10038     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10039   },
10040   {
10041     /* VEX_W_0F380C_P_2  */
10042     { "vpermilps",      { XM, Vex, EXx }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F380D_P_2  */
10046     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F380E_P_2  */
10050     { "vtestps",        { XM, EXx }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F380F_P_2  */
10054     { "vtestpd",        { XM, EXx }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3816_P_2  */
10058     { "vpermps",        { XM, Vex, EXx }, 0 },
10059   },
10060   {
10061     /* VEX_W_0F3818_P_2 */
10062     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10063   },
10064   {
10065     /* VEX_W_0F3819_P_2 */
10066     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F381A_P_2_M_0 */
10070     { "vbroadcastf128", { XM, Mxmm }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F382C_P_2_M_0 */
10074     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F382D_P_2_M_0 */
10078     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F382E_P_2_M_0 */
10082     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F382F_P_2_M_0 */
10086     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F3836_P_2  */
10090     { "vpermd",         { XM, Vex, EXx }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3846_P_2 */
10094     { "vpsravd",        { XM, Vex, EXx }, 0 },
10095   },
10096   {
10097     /* VEX_W_0F3858_P_2 */
10098     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10099   },
10100   {
10101     /* VEX_W_0F3859_P_2 */
10102     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10103   },
10104   {
10105     /* VEX_W_0F385A_P_2_M_0 */
10106     { "vbroadcasti128", { XM, Mxmm }, 0 },
10107   },
10108   {
10109     /* VEX_W_0F3878_P_2 */
10110     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10111   },
10112   {
10113     /* VEX_W_0F3879_P_2 */
10114     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10115   },
10116   {
10117     /* VEX_W_0F38CF_P_2 */
10118     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A00_P_2 */
10122     { Bad_Opcode },
10123     { "vpermq",         { XM, EXx, Ib }, 0 },
10124   },
10125   {
10126     /* VEX_W_0F3A01_P_2 */
10127     { Bad_Opcode },
10128     { "vpermpd",        { XM, EXx, Ib }, 0 },
10129   },
10130   {
10131     /* VEX_W_0F3A02_P_2 */
10132     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A04_P_2 */
10136     { "vpermilps",      { XM, EXx, Ib }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F3A05_P_2 */
10140     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F3A06_P_2 */
10144     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10145   },
10146   {
10147     /* VEX_W_0F3A18_P_2 */
10148     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10149   },
10150   {
10151     /* VEX_W_0F3A19_P_2 */
10152     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10153   },
10154   {
10155     /* VEX_W_0F3A30_P_2_LEN_0 */
10156     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10157     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10158   },
10159   {
10160     /* VEX_W_0F3A31_P_2_LEN_0 */
10161     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10162     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10163   },
10164   {
10165     /* VEX_W_0F3A32_P_2_LEN_0 */
10166     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10167     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10168   },
10169   {
10170     /* VEX_W_0F3A33_P_2_LEN_0 */
10171     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10172     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10173   },
10174   {
10175     /* VEX_W_0F3A38_P_2 */
10176     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F3A39_P_2 */
10180     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10181   },
10182   {
10183     /* VEX_W_0F3A46_P_2 */
10184     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10185   },
10186   {
10187     /* VEX_W_0F3A48_P_2 */
10188     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10189     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10190   },
10191   {
10192     /* VEX_W_0F3A49_P_2 */
10193     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10194     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3A4A_P_2 */
10198     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3A4B_P_2 */
10202     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10203   },
10204   {
10205     /* VEX_W_0F3A4C_P_2 */
10206     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10207   },
10208   {
10209     /* VEX_W_0F3ACE_P_2 */
10210     { Bad_Opcode },
10211     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10212   },
10213   {
10214     /* VEX_W_0F3ACF_P_2 */
10215     { Bad_Opcode },
10216     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10217   },
10218 #define NEED_VEX_W_TABLE
10219 #include "i386-dis-evex.h"
10220 #undef NEED_VEX_W_TABLE
10221 };
10222
10223 static const struct dis386 mod_table[][2] = {
10224   {
10225     /* MOD_8D */
10226     { "leaS",           { Gv, M }, 0 },
10227   },
10228   {
10229     /* MOD_C6_REG_7 */
10230     { Bad_Opcode },
10231     { RM_TABLE (RM_C6_REG_7) },
10232   },
10233   {
10234     /* MOD_C7_REG_7 */
10235     { Bad_Opcode },
10236     { RM_TABLE (RM_C7_REG_7) },
10237   },
10238   {
10239     /* MOD_FF_REG_3 */
10240     { "Jcall^", { indirEp }, 0 },
10241   },
10242   {
10243     /* MOD_FF_REG_5 */
10244     { "Jjmp^", { indirEp }, 0 },
10245   },
10246   {
10247     /* MOD_0F01_REG_0 */
10248     { X86_64_TABLE (X86_64_0F01_REG_0) },
10249     { RM_TABLE (RM_0F01_REG_0) },
10250   },
10251   {
10252     /* MOD_0F01_REG_1 */
10253     { X86_64_TABLE (X86_64_0F01_REG_1) },
10254     { RM_TABLE (RM_0F01_REG_1) },
10255   },
10256   {
10257     /* MOD_0F01_REG_2 */
10258     { X86_64_TABLE (X86_64_0F01_REG_2) },
10259     { RM_TABLE (RM_0F01_REG_2) },
10260   },
10261   {
10262     /* MOD_0F01_REG_3 */
10263     { X86_64_TABLE (X86_64_0F01_REG_3) },
10264     { RM_TABLE (RM_0F01_REG_3) },
10265   },
10266   {
10267     /* MOD_0F01_REG_5 */
10268     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10269     { RM_TABLE (RM_0F01_REG_5) },
10270   },
10271   {
10272     /* MOD_0F01_REG_7 */
10273     { "invlpg",         { Mb }, 0 },
10274     { RM_TABLE (RM_0F01_REG_7) },
10275   },
10276   {
10277     /* MOD_0F12_PREFIX_0 */
10278     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10279     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10280   },
10281   {
10282     /* MOD_0F13 */
10283     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10284   },
10285   {
10286     /* MOD_0F16_PREFIX_0 */
10287     { "movhps",         { XM, EXq }, 0 },
10288     { "movlhps",        { XM, EXq }, 0 },
10289   },
10290   {
10291     /* MOD_0F17 */
10292     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10293   },
10294   {
10295     /* MOD_0F18_REG_0 */
10296     { "prefetchnta",    { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_1 */
10300     { "prefetcht0",     { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_2 */
10304     { "prefetcht1",     { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_3 */
10308     { "prefetcht2",     { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F18_REG_4 */
10312     { "nop/reserved",   { Mb }, 0 },
10313   },
10314   {
10315     /* MOD_0F18_REG_5 */
10316     { "nop/reserved",   { Mb }, 0 },
10317   },
10318   {
10319     /* MOD_0F18_REG_6 */
10320     { "nop/reserved",   { Mb }, 0 },
10321   },
10322   {
10323     /* MOD_0F18_REG_7 */
10324     { "nop/reserved",   { Mb }, 0 },
10325   },
10326   {
10327     /* MOD_0F1A_PREFIX_0 */
10328     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10329     { "nopQ",           { Ev }, 0 },
10330   },
10331   {
10332     /* MOD_0F1B_PREFIX_0 */
10333     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10334     { "nopQ",           { Ev }, 0 },
10335   },
10336   {
10337     /* MOD_0F1B_PREFIX_1 */
10338     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10339     { "nopQ",           { Ev }, 0 },
10340   },
10341   {
10342     /* MOD_0F1C_PREFIX_0 */
10343     { REG_TABLE (REG_0F1C_MOD_0) },
10344     { "nopQ",           { Ev }, 0 },
10345   },
10346   {
10347     /* MOD_0F1E_PREFIX_1 */
10348     { "nopQ",           { Ev }, 0 },
10349     { REG_TABLE (REG_0F1E_MOD_3) },
10350   },
10351   {
10352     /* MOD_0F24 */
10353     { Bad_Opcode },
10354     { "movL",           { Rd, Td }, 0 },
10355   },
10356   {
10357     /* MOD_0F26 */
10358     { Bad_Opcode },
10359     { "movL",           { Td, Rd }, 0 },
10360   },
10361   {
10362     /* MOD_0F2B_PREFIX_0 */
10363     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10364   },
10365   {
10366     /* MOD_0F2B_PREFIX_1 */
10367     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10368   },
10369   {
10370     /* MOD_0F2B_PREFIX_2 */
10371     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10372   },
10373   {
10374     /* MOD_0F2B_PREFIX_3 */
10375     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10376   },
10377   {
10378     /* MOD_0F51 */
10379     { Bad_Opcode },
10380     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10381   },
10382   {
10383     /* MOD_0F71_REG_2 */
10384     { Bad_Opcode },
10385     { "psrlw",          { MS, Ib }, 0 },
10386   },
10387   {
10388     /* MOD_0F71_REG_4 */
10389     { Bad_Opcode },
10390     { "psraw",          { MS, Ib }, 0 },
10391   },
10392   {
10393     /* MOD_0F71_REG_6 */
10394     { Bad_Opcode },
10395     { "psllw",          { MS, Ib }, 0 },
10396   },
10397   {
10398     /* MOD_0F72_REG_2 */
10399     { Bad_Opcode },
10400     { "psrld",          { MS, Ib }, 0 },
10401   },
10402   {
10403     /* MOD_0F72_REG_4 */
10404     { Bad_Opcode },
10405     { "psrad",          { MS, Ib }, 0 },
10406   },
10407   {
10408     /* MOD_0F72_REG_6 */
10409     { Bad_Opcode },
10410     { "pslld",          { MS, Ib }, 0 },
10411   },
10412   {
10413     /* MOD_0F73_REG_2 */
10414     { Bad_Opcode },
10415     { "psrlq",          { MS, Ib }, 0 },
10416   },
10417   {
10418     /* MOD_0F73_REG_3 */
10419     { Bad_Opcode },
10420     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10421   },
10422   {
10423     /* MOD_0F73_REG_6 */
10424     { Bad_Opcode },
10425     { "psllq",          { MS, Ib }, 0 },
10426   },
10427   {
10428     /* MOD_0F73_REG_7 */
10429     { Bad_Opcode },
10430     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10431   },
10432   {
10433     /* MOD_0FAE_REG_0 */
10434     { "fxsave",         { FXSAVE }, 0 },
10435     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10436   },
10437   {
10438     /* MOD_0FAE_REG_1 */
10439     { "fxrstor",        { FXSAVE }, 0 },
10440     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10441   },
10442   {
10443     /* MOD_0FAE_REG_2 */
10444     { "ldmxcsr",        { Md }, 0 },
10445     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10446   },
10447   {
10448     /* MOD_0FAE_REG_3 */
10449     { "stmxcsr",        { Md }, 0 },
10450     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10451   },
10452   {
10453     /* MOD_0FAE_REG_4 */
10454     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10455     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10456   },
10457   {
10458     /* MOD_0FAE_REG_5 */
10459     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10460     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10461   },
10462   {
10463     /* MOD_0FAE_REG_6 */
10464     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10465     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10466   },
10467   {
10468     /* MOD_0FAE_REG_7 */
10469     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10470     { RM_TABLE (RM_0FAE_REG_7) },
10471   },
10472   {
10473     /* MOD_0FB2 */
10474     { "lssS",           { Gv, Mp }, 0 },
10475   },
10476   {
10477     /* MOD_0FB4 */
10478     { "lfsS",           { Gv, Mp }, 0 },
10479   },
10480   {
10481     /* MOD_0FB5 */
10482     { "lgsS",           { Gv, Mp }, 0 },
10483   },
10484   {
10485     /* MOD_0FC3 */
10486     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10487   },
10488   {
10489     /* MOD_0FC7_REG_3 */
10490     { "xrstors",        { FXSAVE }, 0 },
10491   },
10492   {
10493     /* MOD_0FC7_REG_4 */
10494     { "xsavec",         { FXSAVE }, 0 },
10495   },
10496   {
10497     /* MOD_0FC7_REG_5 */
10498     { "xsaves",         { FXSAVE }, 0 },
10499   },
10500   {
10501     /* MOD_0FC7_REG_6 */
10502     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10503     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10504   },
10505   {
10506     /* MOD_0FC7_REG_7 */
10507     { "vmptrst",        { Mq }, 0 },
10508     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10509   },
10510   {
10511     /* MOD_0FD7 */
10512     { Bad_Opcode },
10513     { "pmovmskb",       { Gdq, MS }, 0 },
10514   },
10515   {
10516     /* MOD_0FE7_PREFIX_2 */
10517     { "movntdq",        { Mx, XM }, 0 },
10518   },
10519   {
10520     /* MOD_0FF0_PREFIX_3 */
10521     { "lddqu",          { XM, M }, 0 },
10522   },
10523   {
10524     /* MOD_0F382A_PREFIX_2 */
10525     { "movntdqa",       { XM, Mx }, 0 },
10526   },
10527   {
10528     /* MOD_0F38F5_PREFIX_2 */
10529     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10530   },
10531   {
10532     /* MOD_0F38F6_PREFIX_0 */
10533     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10534   },
10535   {
10536     /* MOD_0F38F8_PREFIX_2 */
10537     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10538   },
10539   {
10540     /* MOD_0F38F9_PREFIX_0 */
10541     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10542   },
10543   {
10544     /* MOD_62_32BIT */
10545     { "bound{S|}",      { Gv, Ma }, 0 },
10546     { EVEX_TABLE (EVEX_0F) },
10547   },
10548   {
10549     /* MOD_C4_32BIT */
10550     { "lesS",           { Gv, Mp }, 0 },
10551     { VEX_C4_TABLE (VEX_0F) },
10552   },
10553   {
10554     /* MOD_C5_32BIT */
10555     { "ldsS",           { Gv, Mp }, 0 },
10556     { VEX_C5_TABLE (VEX_0F) },
10557   },
10558   {
10559     /* MOD_VEX_0F12_PREFIX_0 */
10560     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10561     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10562   },
10563   {
10564     /* MOD_VEX_0F13 */
10565     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10566   },
10567   {
10568     /* MOD_VEX_0F16_PREFIX_0 */
10569     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10570     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10571   },
10572   {
10573     /* MOD_VEX_0F17 */
10574     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10575   },
10576   {
10577     /* MOD_VEX_0F2B */
10578     { "vmovntpX",       { Mx, XM }, 0 },
10579   },
10580   {
10581     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10582     { Bad_Opcode },
10583     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10584   },
10585   {
10586     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10587     { Bad_Opcode },
10588     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10589   },
10590   {
10591     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10592     { Bad_Opcode },
10593     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10594   },
10595   {
10596     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10597     { Bad_Opcode },
10598     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10599   },
10600   {
10601     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10602     { Bad_Opcode },
10603     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10604   },
10605   {
10606     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10607     { Bad_Opcode },
10608     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10612     { Bad_Opcode },
10613     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10617     { Bad_Opcode },
10618     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10619   },
10620   {
10621     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10622     { Bad_Opcode },
10623     { "knotw",          { MaskG, MaskR }, 0 },
10624   },
10625   {
10626     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10627     { Bad_Opcode },
10628     { "knotq",          { MaskG, MaskR }, 0 },
10629   },
10630   {
10631     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10632     { Bad_Opcode },
10633     { "knotb",          { MaskG, MaskR }, 0 },
10634   },
10635   {
10636     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10637     { Bad_Opcode },
10638     { "knotd",          { MaskG, MaskR }, 0 },
10639   },
10640   {
10641     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10642     { Bad_Opcode },
10643     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10644   },
10645   {
10646     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10647     { Bad_Opcode },
10648     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10649   },
10650   {
10651     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10652     { Bad_Opcode },
10653     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10654   },
10655   {
10656     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10657     { Bad_Opcode },
10658     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10659   },
10660  {
10661     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10662     { Bad_Opcode },
10663     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10664   },
10665   {
10666     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10667     { Bad_Opcode },
10668     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10669   },
10670   {
10671     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10672     { Bad_Opcode },
10673     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10674   },
10675   {
10676     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10677     { Bad_Opcode },
10678     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10682     { Bad_Opcode },
10683     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10684   },
10685   {
10686     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10687     { Bad_Opcode },
10688     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10689   },
10690   {
10691     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10692     { Bad_Opcode },
10693     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10694   },
10695   {
10696     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10697     { Bad_Opcode },
10698     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10699   },
10700   {
10701     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10702     { Bad_Opcode },
10703     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10704   },
10705   {
10706     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10707     { Bad_Opcode },
10708     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10709   },
10710   {
10711     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10712     { Bad_Opcode },
10713     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10714   },
10715   {
10716     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10717     { Bad_Opcode },
10718     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10719   },
10720   {
10721     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10722     { Bad_Opcode },
10723     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10724   },
10725   {
10726     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10727     { Bad_Opcode },
10728     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10729   },
10730   {
10731     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10732     { Bad_Opcode },
10733     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10734   },
10735   {
10736     /* MOD_VEX_0F50 */
10737     { Bad_Opcode },
10738     { "vmovmskpX",      { Gdq, XS }, 0 },
10739   },
10740   {
10741     /* MOD_VEX_0F71_REG_2 */
10742     { Bad_Opcode },
10743     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10744   },
10745   {
10746     /* MOD_VEX_0F71_REG_4 */
10747     { Bad_Opcode },
10748     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10749   },
10750   {
10751     /* MOD_VEX_0F71_REG_6 */
10752     { Bad_Opcode },
10753     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10754   },
10755   {
10756     /* MOD_VEX_0F72_REG_2 */
10757     { Bad_Opcode },
10758     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10759   },
10760   {
10761     /* MOD_VEX_0F72_REG_4 */
10762     { Bad_Opcode },
10763     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10764   },
10765   {
10766     /* MOD_VEX_0F72_REG_6 */
10767     { Bad_Opcode },
10768     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10769   },
10770   {
10771     /* MOD_VEX_0F73_REG_2 */
10772     { Bad_Opcode },
10773     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10774   },
10775   {
10776     /* MOD_VEX_0F73_REG_3 */
10777     { Bad_Opcode },
10778     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10779   },
10780   {
10781     /* MOD_VEX_0F73_REG_6 */
10782     { Bad_Opcode },
10783     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10784   },
10785   {
10786     /* MOD_VEX_0F73_REG_7 */
10787     { Bad_Opcode },
10788     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10789   },
10790   {
10791     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10792     { "kmovw",          { Ew, MaskG }, 0 },
10793     { Bad_Opcode },
10794   },
10795   {
10796     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10797     { "kmovq",          { Eq, MaskG }, 0 },
10798     { Bad_Opcode },
10799   },
10800   {
10801     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10802     { "kmovb",          { Eb, MaskG }, 0 },
10803     { Bad_Opcode },
10804   },
10805   {
10806     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10807     { "kmovd",          { Ed, MaskG }, 0 },
10808     { Bad_Opcode },
10809   },
10810   {
10811     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10812     { Bad_Opcode },
10813     { "kmovw",          { MaskG, Rdq }, 0 },
10814   },
10815   {
10816     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10817     { Bad_Opcode },
10818     { "kmovb",          { MaskG, Rdq }, 0 },
10819   },
10820   {
10821     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
10822     { Bad_Opcode },
10823     { "kmovd",          { MaskG, Rdq }, 0 },
10824   },
10825   {
10826     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
10827     { Bad_Opcode },
10828     { "kmovq",          { MaskG, Rdq }, 0 },
10829   },
10830   {
10831     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10832     { Bad_Opcode },
10833     { "kmovw",          { Gdq, MaskR }, 0 },
10834   },
10835   {
10836     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10837     { Bad_Opcode },
10838     { "kmovb",          { Gdq, MaskR }, 0 },
10839   },
10840   {
10841     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
10842     { Bad_Opcode },
10843     { "kmovd",          { Gdq, MaskR }, 0 },
10844   },
10845   {
10846     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
10847     { Bad_Opcode },
10848     { "kmovq",          { Gdq, MaskR }, 0 },
10849   },
10850   {
10851     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10852     { Bad_Opcode },
10853     { "kortestw", { MaskG, MaskR }, 0 },
10854   },
10855   {
10856     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10857     { Bad_Opcode },
10858     { "kortestq", { MaskG, MaskR }, 0 },
10859   },
10860   {
10861     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10862     { Bad_Opcode },
10863     { "kortestb", { MaskG, MaskR }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10867     { Bad_Opcode },
10868     { "kortestd", { MaskG, MaskR }, 0 },
10869   },
10870   {
10871     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10872     { Bad_Opcode },
10873     { "ktestw", { MaskG, MaskR }, 0 },
10874   },
10875   {
10876     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10877     { Bad_Opcode },
10878     { "ktestq", { MaskG, MaskR }, 0 },
10879   },
10880   {
10881     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10882     { Bad_Opcode },
10883     { "ktestb", { MaskG, MaskR }, 0 },
10884   },
10885   {
10886     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10887     { Bad_Opcode },
10888     { "ktestd", { MaskG, MaskR }, 0 },
10889   },
10890   {
10891     /* MOD_VEX_0FAE_REG_2 */
10892     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10893   },
10894   {
10895     /* MOD_VEX_0FAE_REG_3 */
10896     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10897   },
10898   {
10899     /* MOD_VEX_0FD7_PREFIX_2 */
10900     { Bad_Opcode },
10901     { "vpmovmskb",      { Gdq, XS }, 0 },
10902   },
10903   {
10904     /* MOD_VEX_0FE7_PREFIX_2 */
10905     { "vmovntdq",       { Mx, XM }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_0FF0_PREFIX_3 */
10909     { "vlddqu",         { XM, M }, 0 },
10910   },
10911   {
10912     /* MOD_VEX_0F381A_PREFIX_2 */
10913     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10914   },
10915   {
10916     /* MOD_VEX_0F382A_PREFIX_2 */
10917     { "vmovntdqa",      { XM, Mx }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_0F382C_PREFIX_2 */
10921     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10922   },
10923   {
10924     /* MOD_VEX_0F382D_PREFIX_2 */
10925     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10926   },
10927   {
10928     /* MOD_VEX_0F382E_PREFIX_2 */
10929     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10930   },
10931   {
10932     /* MOD_VEX_0F382F_PREFIX_2 */
10933     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10934   },
10935   {
10936     /* MOD_VEX_0F385A_PREFIX_2 */
10937     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10938   },
10939   {
10940     /* MOD_VEX_0F388C_PREFIX_2 */
10941     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_0F388E_PREFIX_2 */
10945     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10946   },
10947   {
10948     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10949     { Bad_Opcode },
10950     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10951   },
10952   {
10953     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10954     { Bad_Opcode },
10955     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10956   },
10957   {
10958     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10959     { Bad_Opcode },
10960     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10961   },
10962   {
10963     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10964     { Bad_Opcode },
10965     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10966   },
10967   {
10968     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10969     { Bad_Opcode },
10970     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10971   },
10972   {
10973     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10974     { Bad_Opcode },
10975     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10976   },
10977   {
10978     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10979     { Bad_Opcode },
10980     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10981   },
10982   {
10983     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10984     { Bad_Opcode },
10985     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10986   },
10987 #define NEED_MOD_TABLE
10988 #include "i386-dis-evex.h"
10989 #undef NEED_MOD_TABLE
10990 };
10991
10992 static const struct dis386 rm_table[][8] = {
10993   {
10994     /* RM_C6_REG_7 */
10995     { "xabort",         { Skip_MODRM, Ib }, 0 },
10996   },
10997   {
10998     /* RM_C7_REG_7 */
10999     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
11000   },
11001   {
11002     /* RM_0F01_REG_0 */
11003     { "enclv",          { Skip_MODRM }, 0 },
11004     { "vmcall",         { Skip_MODRM }, 0 },
11005     { "vmlaunch",       { Skip_MODRM }, 0 },
11006     { "vmresume",       { Skip_MODRM }, 0 },
11007     { "vmxoff",         { Skip_MODRM }, 0 },
11008     { "pconfig",        { Skip_MODRM }, 0 },
11009   },
11010   {
11011     /* RM_0F01_REG_1 */
11012     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11013     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11014     { "clac",           { Skip_MODRM }, 0 },
11015     { "stac",           { Skip_MODRM }, 0 },
11016     { Bad_Opcode },
11017     { Bad_Opcode },
11018     { Bad_Opcode },
11019     { "encls",          { Skip_MODRM }, 0 },
11020   },
11021   {
11022     /* RM_0F01_REG_2 */
11023     { "xgetbv",         { Skip_MODRM }, 0 },
11024     { "xsetbv",         { Skip_MODRM }, 0 },
11025     { Bad_Opcode },
11026     { Bad_Opcode },
11027     { "vmfunc",         { Skip_MODRM }, 0 },
11028     { "xend",           { Skip_MODRM }, 0 },
11029     { "xtest",          { Skip_MODRM }, 0 },
11030     { "enclu",          { Skip_MODRM }, 0 },
11031   },
11032   {
11033     /* RM_0F01_REG_3 */
11034     { "vmrun",          { Skip_MODRM }, 0 },
11035     { "vmmcall",        { Skip_MODRM }, 0 },
11036     { "vmload",         { Skip_MODRM }, 0 },
11037     { "vmsave",         { Skip_MODRM }, 0 },
11038     { "stgi",           { Skip_MODRM }, 0 },
11039     { "clgi",           { Skip_MODRM }, 0 },
11040     { "skinit",         { Skip_MODRM }, 0 },
11041     { "invlpga",        { Skip_MODRM }, 0 },
11042   },
11043   {
11044     /* RM_0F01_REG_5 */
11045     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11046     { Bad_Opcode },
11047     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11048     { Bad_Opcode },
11049     { Bad_Opcode },
11050     { Bad_Opcode },
11051     { "rdpkru",         { Skip_MODRM }, 0 },
11052     { "wrpkru",         { Skip_MODRM }, 0 },
11053   },
11054   {
11055     /* RM_0F01_REG_7 */
11056     { "swapgs",         { Skip_MODRM }, 0  },
11057     { "rdtscp",         { Skip_MODRM }, 0  },
11058     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11059     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11060     { "clzero",         { Skip_MODRM }, 0  },
11061   },
11062   {
11063     /* RM_0F1E_MOD_3_REG_7 */
11064     { "nopQ",           { Ev }, 0 },
11065     { "nopQ",           { Ev }, 0 },
11066     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11067     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11068     { "nopQ",           { Ev }, 0 },
11069     { "nopQ",           { Ev }, 0 },
11070     { "nopQ",           { Ev }, 0 },
11071     { "nopQ",           { Ev }, 0 },
11072   },
11073   {
11074     /* RM_0FAE_REG_6 */
11075     { "mfence",         { Skip_MODRM }, 0 },
11076   },
11077   {
11078     /* RM_0FAE_REG_7 */
11079     { "sfence",         { Skip_MODRM }, 0 },
11080
11081   },
11082 };
11083
11084 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11085
11086 /* We use the high bit to indicate different name for the same
11087    prefix.  */
11088 #define REP_PREFIX      (0xf3 | 0x100)
11089 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11090 #define XRELEASE_PREFIX (0xf3 | 0x400)
11091 #define BND_PREFIX      (0xf2 | 0x400)
11092 #define NOTRACK_PREFIX  (0x3e | 0x100)
11093
11094 static int
11095 ckprefix (void)
11096 {
11097   int newrex, i, length;
11098   rex = 0;
11099   rex_ignored = 0;
11100   prefixes = 0;
11101   used_prefixes = 0;
11102   rex_used = 0;
11103   last_lock_prefix = -1;
11104   last_repz_prefix = -1;
11105   last_repnz_prefix = -1;
11106   last_data_prefix = -1;
11107   last_addr_prefix = -1;
11108   last_rex_prefix = -1;
11109   last_seg_prefix = -1;
11110   fwait_prefix = -1;
11111   active_seg_prefix = 0;
11112   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11113     all_prefixes[i] = 0;
11114   i = 0;
11115   length = 0;
11116   /* The maximum instruction length is 15bytes.  */
11117   while (length < MAX_CODE_LENGTH - 1)
11118     {
11119       FETCH_DATA (the_info, codep + 1);
11120       newrex = 0;
11121       switch (*codep)
11122         {
11123         /* REX prefixes family.  */
11124         case 0x40:
11125         case 0x41:
11126         case 0x42:
11127         case 0x43:
11128         case 0x44:
11129         case 0x45:
11130         case 0x46:
11131         case 0x47:
11132         case 0x48:
11133         case 0x49:
11134         case 0x4a:
11135         case 0x4b:
11136         case 0x4c:
11137         case 0x4d:
11138         case 0x4e:
11139         case 0x4f:
11140           if (address_mode == mode_64bit)
11141             newrex = *codep;
11142           else
11143             return 1;
11144           last_rex_prefix = i;
11145           break;
11146         case 0xf3:
11147           prefixes |= PREFIX_REPZ;
11148           last_repz_prefix = i;
11149           break;
11150         case 0xf2:
11151           prefixes |= PREFIX_REPNZ;
11152           last_repnz_prefix = i;
11153           break;
11154         case 0xf0:
11155           prefixes |= PREFIX_LOCK;
11156           last_lock_prefix = i;
11157           break;
11158         case 0x2e:
11159           prefixes |= PREFIX_CS;
11160           last_seg_prefix = i;
11161           active_seg_prefix = PREFIX_CS;
11162           break;
11163         case 0x36:
11164           prefixes |= PREFIX_SS;
11165           last_seg_prefix = i;
11166           active_seg_prefix = PREFIX_SS;
11167           break;
11168         case 0x3e:
11169           prefixes |= PREFIX_DS;
11170           last_seg_prefix = i;
11171           active_seg_prefix = PREFIX_DS;
11172           break;
11173         case 0x26:
11174           prefixes |= PREFIX_ES;
11175           last_seg_prefix = i;
11176           active_seg_prefix = PREFIX_ES;
11177           break;
11178         case 0x64:
11179           prefixes |= PREFIX_FS;
11180           last_seg_prefix = i;
11181           active_seg_prefix = PREFIX_FS;
11182           break;
11183         case 0x65:
11184           prefixes |= PREFIX_GS;
11185           last_seg_prefix = i;
11186           active_seg_prefix = PREFIX_GS;
11187           break;
11188         case 0x66:
11189           prefixes |= PREFIX_DATA;
11190           last_data_prefix = i;
11191           break;
11192         case 0x67:
11193           prefixes |= PREFIX_ADDR;
11194           last_addr_prefix = i;
11195           break;
11196         case FWAIT_OPCODE:
11197           /* fwait is really an instruction.  If there are prefixes
11198              before the fwait, they belong to the fwait, *not* to the
11199              following instruction.  */
11200           fwait_prefix = i;
11201           if (prefixes || rex)
11202             {
11203               prefixes |= PREFIX_FWAIT;
11204               codep++;
11205               /* This ensures that the previous REX prefixes are noticed
11206                  as unused prefixes, as in the return case below.  */
11207               rex_used = rex;
11208               return 1;
11209             }
11210           prefixes = PREFIX_FWAIT;
11211           break;
11212         default:
11213           return 1;
11214         }
11215       /* Rex is ignored when followed by another prefix.  */
11216       if (rex)
11217         {
11218           rex_used = rex;
11219           return 1;
11220         }
11221       if (*codep != FWAIT_OPCODE)
11222         all_prefixes[i++] = *codep;
11223       rex = newrex;
11224       codep++;
11225       length++;
11226     }
11227   return 0;
11228 }
11229
11230 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11231    prefix byte.  */
11232
11233 static const char *
11234 prefix_name (int pref, int sizeflag)
11235 {
11236   static const char *rexes [16] =
11237     {
11238       "rex",            /* 0x40 */
11239       "rex.B",          /* 0x41 */
11240       "rex.X",          /* 0x42 */
11241       "rex.XB",         /* 0x43 */
11242       "rex.R",          /* 0x44 */
11243       "rex.RB",         /* 0x45 */
11244       "rex.RX",         /* 0x46 */
11245       "rex.RXB",        /* 0x47 */
11246       "rex.W",          /* 0x48 */
11247       "rex.WB",         /* 0x49 */
11248       "rex.WX",         /* 0x4a */
11249       "rex.WXB",        /* 0x4b */
11250       "rex.WR",         /* 0x4c */
11251       "rex.WRB",        /* 0x4d */
11252       "rex.WRX",        /* 0x4e */
11253       "rex.WRXB",       /* 0x4f */
11254     };
11255
11256   switch (pref)
11257     {
11258     /* REX prefixes family.  */
11259     case 0x40:
11260     case 0x41:
11261     case 0x42:
11262     case 0x43:
11263     case 0x44:
11264     case 0x45:
11265     case 0x46:
11266     case 0x47:
11267     case 0x48:
11268     case 0x49:
11269     case 0x4a:
11270     case 0x4b:
11271     case 0x4c:
11272     case 0x4d:
11273     case 0x4e:
11274     case 0x4f:
11275       return rexes [pref - 0x40];
11276     case 0xf3:
11277       return "repz";
11278     case 0xf2:
11279       return "repnz";
11280     case 0xf0:
11281       return "lock";
11282     case 0x2e:
11283       return "cs";
11284     case 0x36:
11285       return "ss";
11286     case 0x3e:
11287       return "ds";
11288     case 0x26:
11289       return "es";
11290     case 0x64:
11291       return "fs";
11292     case 0x65:
11293       return "gs";
11294     case 0x66:
11295       return (sizeflag & DFLAG) ? "data16" : "data32";
11296     case 0x67:
11297       if (address_mode == mode_64bit)
11298         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11299       else
11300         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11301     case FWAIT_OPCODE:
11302       return "fwait";
11303     case REP_PREFIX:
11304       return "rep";
11305     case XACQUIRE_PREFIX:
11306       return "xacquire";
11307     case XRELEASE_PREFIX:
11308       return "xrelease";
11309     case BND_PREFIX:
11310       return "bnd";
11311     case NOTRACK_PREFIX:
11312       return "notrack";
11313     default:
11314       return NULL;
11315     }
11316 }
11317
11318 static char op_out[MAX_OPERANDS][100];
11319 static int op_ad, op_index[MAX_OPERANDS];
11320 static int two_source_ops;
11321 static bfd_vma op_address[MAX_OPERANDS];
11322 static bfd_vma op_riprel[MAX_OPERANDS];
11323 static bfd_vma start_pc;
11324
11325 /*
11326  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11327  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11328  *   section of the "Virtual 8086 Mode" chapter.)
11329  * 'pc' should be the address of this instruction, it will
11330  *   be used to print the target address if this is a relative jump or call
11331  * The function returns the length of this instruction in bytes.
11332  */
11333
11334 static char intel_syntax;
11335 static char intel_mnemonic = !SYSV386_COMPAT;
11336 static char open_char;
11337 static char close_char;
11338 static char separator_char;
11339 static char scale_char;
11340
11341 enum x86_64_isa
11342 {
11343   amd64 = 0,
11344   intel64
11345 };
11346
11347 static enum x86_64_isa isa64;
11348
11349 /* Here for backwards compatibility.  When gdb stops using
11350    print_insn_i386_att and print_insn_i386_intel these functions can
11351    disappear, and print_insn_i386 be merged into print_insn.  */
11352 int
11353 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11354 {
11355   intel_syntax = 0;
11356
11357   return print_insn (pc, info);
11358 }
11359
11360 int
11361 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11362 {
11363   intel_syntax = 1;
11364
11365   return print_insn (pc, info);
11366 }
11367
11368 int
11369 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11370 {
11371   intel_syntax = -1;
11372
11373   return print_insn (pc, info);
11374 }
11375
11376 void
11377 print_i386_disassembler_options (FILE *stream)
11378 {
11379   fprintf (stream, _("\n\
11380 The following i386/x86-64 specific disassembler options are supported for use\n\
11381 with the -M switch (multiple options should be separated by commas):\n"));
11382
11383   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11384   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11385   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11386   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11387   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11388   fprintf (stream, _("  att-mnemonic\n"
11389                      "              Display instruction in AT&T mnemonic\n"));
11390   fprintf (stream, _("  intel-mnemonic\n"
11391                      "              Display instruction in Intel mnemonic\n"));
11392   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11393   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11394   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11395   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11396   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11397   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11398   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11399   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11400 }
11401
11402 /* Bad opcode.  */
11403 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11404
11405 /* Get a pointer to struct dis386 with a valid name.  */
11406
11407 static const struct dis386 *
11408 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11409 {
11410   int vindex, vex_table_index;
11411
11412   if (dp->name != NULL)
11413     return dp;
11414
11415   switch (dp->op[0].bytemode)
11416     {
11417     case USE_REG_TABLE:
11418       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11419       break;
11420
11421     case USE_MOD_TABLE:
11422       vindex = modrm.mod == 0x3 ? 1 : 0;
11423       dp = &mod_table[dp->op[1].bytemode][vindex];
11424       break;
11425
11426     case USE_RM_TABLE:
11427       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11428       break;
11429
11430     case USE_PREFIX_TABLE:
11431       if (need_vex)
11432         {
11433           /* The prefix in VEX is implicit.  */
11434           switch (vex.prefix)
11435             {
11436             case 0:
11437               vindex = 0;
11438               break;
11439             case REPE_PREFIX_OPCODE:
11440               vindex = 1;
11441               break;
11442             case DATA_PREFIX_OPCODE:
11443               vindex = 2;
11444               break;
11445             case REPNE_PREFIX_OPCODE:
11446               vindex = 3;
11447               break;
11448             default:
11449               abort ();
11450               break;
11451             }
11452         }
11453       else
11454         {
11455           int last_prefix = -1;
11456           int prefix = 0;
11457           vindex = 0;
11458           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11459              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11460              last one wins.  */
11461           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11462             {
11463               if (last_repz_prefix > last_repnz_prefix)
11464                 {
11465                   vindex = 1;
11466                   prefix = PREFIX_REPZ;
11467                   last_prefix = last_repz_prefix;
11468                 }
11469               else
11470                 {
11471                   vindex = 3;
11472                   prefix = PREFIX_REPNZ;
11473                   last_prefix = last_repnz_prefix;
11474                 }
11475
11476               /* Check if prefix should be ignored.  */
11477               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11478                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11479                    & prefix) != 0)
11480                 vindex = 0;
11481             }
11482
11483           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11484             {
11485               vindex = 2;
11486               prefix = PREFIX_DATA;
11487               last_prefix = last_data_prefix;
11488             }
11489
11490           if (vindex != 0)
11491             {
11492               used_prefixes |= prefix;
11493               all_prefixes[last_prefix] = 0;
11494             }
11495         }
11496       dp = &prefix_table[dp->op[1].bytemode][vindex];
11497       break;
11498
11499     case USE_X86_64_TABLE:
11500       vindex = address_mode == mode_64bit ? 1 : 0;
11501       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11502       break;
11503
11504     case USE_3BYTE_TABLE:
11505       FETCH_DATA (info, codep + 2);
11506       vindex = *codep++;
11507       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11508       end_codep = codep;
11509       modrm.mod = (*codep >> 6) & 3;
11510       modrm.reg = (*codep >> 3) & 7;
11511       modrm.rm = *codep & 7;
11512       break;
11513
11514     case USE_VEX_LEN_TABLE:
11515       if (!need_vex)
11516         abort ();
11517
11518       switch (vex.length)
11519         {
11520         case 128:
11521           vindex = 0;
11522           break;
11523         case 256:
11524           vindex = 1;
11525           break;
11526         default:
11527           abort ();
11528           break;
11529         }
11530
11531       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11532       break;
11533
11534     case USE_EVEX_LEN_TABLE:
11535       if (!vex.evex)
11536         abort ();
11537
11538       switch (vex.length)
11539         {
11540         case 128:
11541           vindex = 0;
11542           break;
11543         case 256:
11544           vindex = 1;
11545           break;
11546         case 512:
11547           vindex = 2;
11548           break;
11549         default:
11550           abort ();
11551           break;
11552         }
11553
11554       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11555       break;
11556
11557     case USE_XOP_8F_TABLE:
11558       FETCH_DATA (info, codep + 3);
11559       /* All bits in the REX prefix are ignored.  */
11560       rex_ignored = rex;
11561       rex = ~(*codep >> 5) & 0x7;
11562
11563       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11564       switch ((*codep & 0x1f))
11565         {
11566         default:
11567           dp = &bad_opcode;
11568           return dp;
11569         case 0x8:
11570           vex_table_index = XOP_08;
11571           break;
11572         case 0x9:
11573           vex_table_index = XOP_09;
11574           break;
11575         case 0xa:
11576           vex_table_index = XOP_0A;
11577           break;
11578         }
11579       codep++;
11580       vex.w = *codep & 0x80;
11581       if (vex.w && address_mode == mode_64bit)
11582         rex |= REX_W;
11583
11584       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11585       if (address_mode != mode_64bit)
11586         {
11587           /* In 16/32-bit mode REX_B is silently ignored.  */
11588           rex &= ~REX_B;
11589         }
11590
11591       vex.length = (*codep & 0x4) ? 256 : 128;
11592       switch ((*codep & 0x3))
11593         {
11594         case 0:
11595           break;
11596         case 1:
11597           vex.prefix = DATA_PREFIX_OPCODE;
11598           break;
11599         case 2:
11600           vex.prefix = REPE_PREFIX_OPCODE;
11601           break;
11602         case 3:
11603           vex.prefix = REPNE_PREFIX_OPCODE;
11604           break;
11605         }
11606       need_vex = 1;
11607       need_vex_reg = 1;
11608       codep++;
11609       vindex = *codep++;
11610       dp = &xop_table[vex_table_index][vindex];
11611
11612       end_codep = codep;
11613       FETCH_DATA (info, codep + 1);
11614       modrm.mod = (*codep >> 6) & 3;
11615       modrm.reg = (*codep >> 3) & 7;
11616       modrm.rm = *codep & 7;
11617       break;
11618
11619     case USE_VEX_C4_TABLE:
11620       /* VEX prefix.  */
11621       FETCH_DATA (info, codep + 3);
11622       /* All bits in the REX prefix are ignored.  */
11623       rex_ignored = rex;
11624       rex = ~(*codep >> 5) & 0x7;
11625       switch ((*codep & 0x1f))
11626         {
11627         default:
11628           dp = &bad_opcode;
11629           return dp;
11630         case 0x1:
11631           vex_table_index = VEX_0F;
11632           break;
11633         case 0x2:
11634           vex_table_index = VEX_0F38;
11635           break;
11636         case 0x3:
11637           vex_table_index = VEX_0F3A;
11638           break;
11639         }
11640       codep++;
11641       vex.w = *codep & 0x80;
11642       if (address_mode == mode_64bit)
11643         {
11644           if (vex.w)
11645             rex |= REX_W;
11646         }
11647       else
11648         {
11649           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11650              is ignored, other REX bits are 0 and the highest bit in
11651              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11652           rex = 0;
11653         }
11654       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11655       vex.length = (*codep & 0x4) ? 256 : 128;
11656       switch ((*codep & 0x3))
11657         {
11658         case 0:
11659           break;
11660         case 1:
11661           vex.prefix = DATA_PREFIX_OPCODE;
11662           break;
11663         case 2:
11664           vex.prefix = REPE_PREFIX_OPCODE;
11665           break;
11666         case 3:
11667           vex.prefix = REPNE_PREFIX_OPCODE;
11668           break;
11669         }
11670       need_vex = 1;
11671       need_vex_reg = 1;
11672       codep++;
11673       vindex = *codep++;
11674       dp = &vex_table[vex_table_index][vindex];
11675       end_codep = codep;
11676       /* There is no MODRM byte for VEX0F 77.  */
11677       if (vex_table_index != VEX_0F || vindex != 0x77)
11678         {
11679           FETCH_DATA (info, codep + 1);
11680           modrm.mod = (*codep >> 6) & 3;
11681           modrm.reg = (*codep >> 3) & 7;
11682           modrm.rm = *codep & 7;
11683         }
11684       break;
11685
11686     case USE_VEX_C5_TABLE:
11687       /* VEX prefix.  */
11688       FETCH_DATA (info, codep + 2);
11689       /* All bits in the REX prefix are ignored.  */
11690       rex_ignored = rex;
11691       rex = (*codep & 0x80) ? 0 : REX_R;
11692
11693       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11694          VEX.vvvv is 1.  */
11695       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11696       vex.length = (*codep & 0x4) ? 256 : 128;
11697       switch ((*codep & 0x3))
11698         {
11699         case 0:
11700           break;
11701         case 1:
11702           vex.prefix = DATA_PREFIX_OPCODE;
11703           break;
11704         case 2:
11705           vex.prefix = REPE_PREFIX_OPCODE;
11706           break;
11707         case 3:
11708           vex.prefix = REPNE_PREFIX_OPCODE;
11709           break;
11710         }
11711       need_vex = 1;
11712       need_vex_reg = 1;
11713       codep++;
11714       vindex = *codep++;
11715       dp = &vex_table[dp->op[1].bytemode][vindex];
11716       end_codep = codep;
11717       /* There is no MODRM byte for VEX 77.  */
11718       if (vindex != 0x77)
11719         {
11720           FETCH_DATA (info, codep + 1);
11721           modrm.mod = (*codep >> 6) & 3;
11722           modrm.reg = (*codep >> 3) & 7;
11723           modrm.rm = *codep & 7;
11724         }
11725       break;
11726
11727     case USE_VEX_W_TABLE:
11728       if (!need_vex)
11729         abort ();
11730
11731       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11732       break;
11733
11734     case USE_EVEX_TABLE:
11735       two_source_ops = 0;
11736       /* EVEX prefix.  */
11737       vex.evex = 1;
11738       FETCH_DATA (info, codep + 4);
11739       /* All bits in the REX prefix are ignored.  */
11740       rex_ignored = rex;
11741       /* The first byte after 0x62.  */
11742       rex = ~(*codep >> 5) & 0x7;
11743       vex.r = *codep & 0x10;
11744       switch ((*codep & 0xf))
11745         {
11746         default:
11747           return &bad_opcode;
11748         case 0x1:
11749           vex_table_index = EVEX_0F;
11750           break;
11751         case 0x2:
11752           vex_table_index = EVEX_0F38;
11753           break;
11754         case 0x3:
11755           vex_table_index = EVEX_0F3A;
11756           break;
11757         }
11758
11759       /* The second byte after 0x62.  */
11760       codep++;
11761       vex.w = *codep & 0x80;
11762       if (vex.w && address_mode == mode_64bit)
11763         rex |= REX_W;
11764
11765       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11766
11767       /* The U bit.  */
11768       if (!(*codep & 0x4))
11769         return &bad_opcode;
11770
11771       switch ((*codep & 0x3))
11772         {
11773         case 0:
11774           break;
11775         case 1:
11776           vex.prefix = DATA_PREFIX_OPCODE;
11777           break;
11778         case 2:
11779           vex.prefix = REPE_PREFIX_OPCODE;
11780           break;
11781         case 3:
11782           vex.prefix = REPNE_PREFIX_OPCODE;
11783           break;
11784         }
11785
11786       /* The third byte after 0x62.  */
11787       codep++;
11788
11789       /* Remember the static rounding bits.  */
11790       vex.ll = (*codep >> 5) & 3;
11791       vex.b = (*codep & 0x10) != 0;
11792
11793       vex.v = *codep & 0x8;
11794       vex.mask_register_specifier = *codep & 0x7;
11795       vex.zeroing = *codep & 0x80;
11796
11797       if (address_mode != mode_64bit)
11798         {
11799           /* In 16/32-bit mode silently ignore following bits.  */
11800           rex &= ~REX_B;
11801           vex.r = 1;
11802           vex.v = 1;
11803         }
11804
11805       need_vex = 1;
11806       need_vex_reg = 1;
11807       codep++;
11808       vindex = *codep++;
11809       dp = &evex_table[vex_table_index][vindex];
11810       end_codep = codep;
11811       FETCH_DATA (info, codep + 1);
11812       modrm.mod = (*codep >> 6) & 3;
11813       modrm.reg = (*codep >> 3) & 7;
11814       modrm.rm = *codep & 7;
11815
11816       /* Set vector length.  */
11817       if (modrm.mod == 3 && vex.b)
11818         vex.length = 512;
11819       else
11820         {
11821           switch (vex.ll)
11822             {
11823             case 0x0:
11824               vex.length = 128;
11825               break;
11826             case 0x1:
11827               vex.length = 256;
11828               break;
11829             case 0x2:
11830               vex.length = 512;
11831               break;
11832             default:
11833               return &bad_opcode;
11834             }
11835         }
11836       break;
11837
11838     case 0:
11839       dp = &bad_opcode;
11840       break;
11841
11842     default:
11843       abort ();
11844     }
11845
11846   if (dp->name != NULL)
11847     return dp;
11848   else
11849     return get_valid_dis386 (dp, info);
11850 }
11851
11852 static void
11853 get_sib (disassemble_info *info, int sizeflag)
11854 {
11855   /* If modrm.mod == 3, operand must be register.  */
11856   if (need_modrm
11857       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11858       && modrm.mod != 3
11859       && modrm.rm == 4)
11860     {
11861       FETCH_DATA (info, codep + 2);
11862       sib.index = (codep [1] >> 3) & 7;
11863       sib.scale = (codep [1] >> 6) & 3;
11864       sib.base = codep [1] & 7;
11865     }
11866 }
11867
11868 static int
11869 print_insn (bfd_vma pc, disassemble_info *info)
11870 {
11871   const struct dis386 *dp;
11872   int i;
11873   char *op_txt[MAX_OPERANDS];
11874   int needcomma;
11875   int sizeflag, orig_sizeflag;
11876   const char *p;
11877   struct dis_private priv;
11878   int prefix_length;
11879
11880   priv.orig_sizeflag = AFLAG | DFLAG;
11881   if ((info->mach & bfd_mach_i386_i386) != 0)
11882     address_mode = mode_32bit;
11883   else if (info->mach == bfd_mach_i386_i8086)
11884     {
11885       address_mode = mode_16bit;
11886       priv.orig_sizeflag = 0;
11887     }
11888   else
11889     address_mode = mode_64bit;
11890
11891   if (intel_syntax == (char) -1)
11892     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11893
11894   for (p = info->disassembler_options; p != NULL; )
11895     {
11896       if (CONST_STRNEQ (p, "amd64"))
11897         isa64 = amd64;
11898       else if (CONST_STRNEQ (p, "intel64"))
11899         isa64 = intel64;
11900       else if (CONST_STRNEQ (p, "x86-64"))
11901         {
11902           address_mode = mode_64bit;
11903           priv.orig_sizeflag = AFLAG | DFLAG;
11904         }
11905       else if (CONST_STRNEQ (p, "i386"))
11906         {
11907           address_mode = mode_32bit;
11908           priv.orig_sizeflag = AFLAG | DFLAG;
11909         }
11910       else if (CONST_STRNEQ (p, "i8086"))
11911         {
11912           address_mode = mode_16bit;
11913           priv.orig_sizeflag = 0;
11914         }
11915       else if (CONST_STRNEQ (p, "intel"))
11916         {
11917           intel_syntax = 1;
11918           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11919             intel_mnemonic = 1;
11920         }
11921       else if (CONST_STRNEQ (p, "att"))
11922         {
11923           intel_syntax = 0;
11924           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11925             intel_mnemonic = 0;
11926         }
11927       else if (CONST_STRNEQ (p, "addr"))
11928         {
11929           if (address_mode == mode_64bit)
11930             {
11931               if (p[4] == '3' && p[5] == '2')
11932                 priv.orig_sizeflag &= ~AFLAG;
11933               else if (p[4] == '6' && p[5] == '4')
11934                 priv.orig_sizeflag |= AFLAG;
11935             }
11936           else
11937             {
11938               if (p[4] == '1' && p[5] == '6')
11939                 priv.orig_sizeflag &= ~AFLAG;
11940               else if (p[4] == '3' && p[5] == '2')
11941                 priv.orig_sizeflag |= AFLAG;
11942             }
11943         }
11944       else if (CONST_STRNEQ (p, "data"))
11945         {
11946           if (p[4] == '1' && p[5] == '6')
11947             priv.orig_sizeflag &= ~DFLAG;
11948           else if (p[4] == '3' && p[5] == '2')
11949             priv.orig_sizeflag |= DFLAG;
11950         }
11951       else if (CONST_STRNEQ (p, "suffix"))
11952         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11953
11954       p = strchr (p, ',');
11955       if (p != NULL)
11956         p++;
11957     }
11958
11959   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11960     {
11961       (*info->fprintf_func) (info->stream,
11962                              _("64-bit address is disabled"));
11963       return -1;
11964     }
11965
11966   if (intel_syntax)
11967     {
11968       names64 = intel_names64;
11969       names32 = intel_names32;
11970       names16 = intel_names16;
11971       names8 = intel_names8;
11972       names8rex = intel_names8rex;
11973       names_seg = intel_names_seg;
11974       names_mm = intel_names_mm;
11975       names_bnd = intel_names_bnd;
11976       names_xmm = intel_names_xmm;
11977       names_ymm = intel_names_ymm;
11978       names_zmm = intel_names_zmm;
11979       index64 = intel_index64;
11980       index32 = intel_index32;
11981       names_mask = intel_names_mask;
11982       index16 = intel_index16;
11983       open_char = '[';
11984       close_char = ']';
11985       separator_char = '+';
11986       scale_char = '*';
11987     }
11988   else
11989     {
11990       names64 = att_names64;
11991       names32 = att_names32;
11992       names16 = att_names16;
11993       names8 = att_names8;
11994       names8rex = att_names8rex;
11995       names_seg = att_names_seg;
11996       names_mm = att_names_mm;
11997       names_bnd = att_names_bnd;
11998       names_xmm = att_names_xmm;
11999       names_ymm = att_names_ymm;
12000       names_zmm = att_names_zmm;
12001       index64 = att_index64;
12002       index32 = att_index32;
12003       names_mask = att_names_mask;
12004       index16 = att_index16;
12005       open_char = '(';
12006       close_char =  ')';
12007       separator_char = ',';
12008       scale_char = ',';
12009     }
12010
12011   /* The output looks better if we put 7 bytes on a line, since that
12012      puts most long word instructions on a single line.  Use 8 bytes
12013      for Intel L1OM.  */
12014   if ((info->mach & bfd_mach_l1om) != 0)
12015     info->bytes_per_line = 8;
12016   else
12017     info->bytes_per_line = 7;
12018
12019   info->private_data = &priv;
12020   priv.max_fetched = priv.the_buffer;
12021   priv.insn_start = pc;
12022
12023   obuf[0] = 0;
12024   for (i = 0; i < MAX_OPERANDS; ++i)
12025     {
12026       op_out[i][0] = 0;
12027       op_index[i] = -1;
12028     }
12029
12030   the_info = info;
12031   start_pc = pc;
12032   start_codep = priv.the_buffer;
12033   codep = priv.the_buffer;
12034
12035   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12036     {
12037       const char *name;
12038
12039       /* Getting here means we tried for data but didn't get it.  That
12040          means we have an incomplete instruction of some sort.  Just
12041          print the first byte as a prefix or a .byte pseudo-op.  */
12042       if (codep > priv.the_buffer)
12043         {
12044           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12045           if (name != NULL)
12046             (*info->fprintf_func) (info->stream, "%s", name);
12047           else
12048             {
12049               /* Just print the first byte as a .byte instruction.  */
12050               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12051                                      (unsigned int) priv.the_buffer[0]);
12052             }
12053
12054           return 1;
12055         }
12056
12057       return -1;
12058     }
12059
12060   obufp = obuf;
12061   sizeflag = priv.orig_sizeflag;
12062
12063   if (!ckprefix () || rex_used)
12064     {
12065       /* Too many prefixes or unused REX prefixes.  */
12066       for (i = 0;
12067            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12068            i++)
12069         (*info->fprintf_func) (info->stream, "%s%s",
12070                                i == 0 ? "" : " ",
12071                                prefix_name (all_prefixes[i], sizeflag));
12072       return i;
12073     }
12074
12075   insn_codep = codep;
12076
12077   FETCH_DATA (info, codep + 1);
12078   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12079
12080   if (((prefixes & PREFIX_FWAIT)
12081        && ((*codep < 0xd8) || (*codep > 0xdf))))
12082     {
12083       /* Handle prefixes before fwait.  */
12084       for (i = 0; i < fwait_prefix && all_prefixes[i];
12085            i++)
12086         (*info->fprintf_func) (info->stream, "%s ",
12087                                prefix_name (all_prefixes[i], sizeflag));
12088       (*info->fprintf_func) (info->stream, "fwait");
12089       return i + 1;
12090     }
12091
12092   if (*codep == 0x0f)
12093     {
12094       unsigned char threebyte;
12095
12096       codep++;
12097       FETCH_DATA (info, codep + 1);
12098       threebyte = *codep;
12099       dp = &dis386_twobyte[threebyte];
12100       need_modrm = twobyte_has_modrm[*codep];
12101       codep++;
12102     }
12103   else
12104     {
12105       dp = &dis386[*codep];
12106       need_modrm = onebyte_has_modrm[*codep];
12107       codep++;
12108     }
12109
12110   /* Save sizeflag for printing the extra prefixes later before updating
12111      it for mnemonic and operand processing.  The prefix names depend
12112      only on the address mode.  */
12113   orig_sizeflag = sizeflag;
12114   if (prefixes & PREFIX_ADDR)
12115     sizeflag ^= AFLAG;
12116   if ((prefixes & PREFIX_DATA))
12117     sizeflag ^= DFLAG;
12118
12119   end_codep = codep;
12120   if (need_modrm)
12121     {
12122       FETCH_DATA (info, codep + 1);
12123       modrm.mod = (*codep >> 6) & 3;
12124       modrm.reg = (*codep >> 3) & 7;
12125       modrm.rm = *codep & 7;
12126     }
12127
12128   need_vex = 0;
12129   need_vex_reg = 0;
12130   vex_w_done = 0;
12131   memset (&vex, 0, sizeof (vex));
12132
12133   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12134     {
12135       get_sib (info, sizeflag);
12136       dofloat (sizeflag);
12137     }
12138   else
12139     {
12140       dp = get_valid_dis386 (dp, info);
12141       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12142         {
12143           get_sib (info, sizeflag);
12144           for (i = 0; i < MAX_OPERANDS; ++i)
12145             {
12146               obufp = op_out[i];
12147               op_ad = MAX_OPERANDS - 1 - i;
12148               if (dp->op[i].rtn)
12149                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12150               /* For EVEX instruction after the last operand masking
12151                  should be printed.  */
12152               if (i == 0 && vex.evex)
12153                 {
12154                   /* Don't print {%k0}.  */
12155                   if (vex.mask_register_specifier)
12156                     {
12157                       oappend ("{");
12158                       oappend (names_mask[vex.mask_register_specifier]);
12159                       oappend ("}");
12160                     }
12161                   if (vex.zeroing)
12162                     oappend ("{z}");
12163                 }
12164             }
12165         }
12166     }
12167
12168   /* Check if the REX prefix is used.  */
12169   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12170     all_prefixes[last_rex_prefix] = 0;
12171
12172   /* Check if the SEG prefix is used.  */
12173   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12174                    | PREFIX_FS | PREFIX_GS)) != 0
12175       && (used_prefixes & active_seg_prefix) != 0)
12176     all_prefixes[last_seg_prefix] = 0;
12177
12178   /* Check if the ADDR prefix is used.  */
12179   if ((prefixes & PREFIX_ADDR) != 0
12180       && (used_prefixes & PREFIX_ADDR) != 0)
12181     all_prefixes[last_addr_prefix] = 0;
12182
12183   /* Check if the DATA prefix is used.  */
12184   if ((prefixes & PREFIX_DATA) != 0
12185       && (used_prefixes & PREFIX_DATA) != 0)
12186     all_prefixes[last_data_prefix] = 0;
12187
12188   /* Print the extra prefixes.  */
12189   prefix_length = 0;
12190   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12191     if (all_prefixes[i])
12192       {
12193         const char *name;
12194         name = prefix_name (all_prefixes[i], orig_sizeflag);
12195         if (name == NULL)
12196           abort ();
12197         prefix_length += strlen (name) + 1;
12198         (*info->fprintf_func) (info->stream, "%s ", name);
12199       }
12200
12201   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12202      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12203      used by putop and MMX/SSE operand and may be overriden by the
12204      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12205      separately.  */
12206   if (dp->prefix_requirement == PREFIX_OPCODE
12207       && dp != &bad_opcode
12208       && (((prefixes
12209             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12210            && (used_prefixes
12211                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12212           || ((((prefixes
12213                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12214                 == PREFIX_DATA)
12215                && (used_prefixes & PREFIX_DATA) == 0))))
12216     {
12217       (*info->fprintf_func) (info->stream, "(bad)");
12218       return end_codep - priv.the_buffer;
12219     }
12220
12221   /* Check maximum code length.  */
12222   if ((codep - start_codep) > MAX_CODE_LENGTH)
12223     {
12224       (*info->fprintf_func) (info->stream, "(bad)");
12225       return MAX_CODE_LENGTH;
12226     }
12227
12228   obufp = mnemonicendp;
12229   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12230     oappend (" ");
12231   oappend (" ");
12232   (*info->fprintf_func) (info->stream, "%s", obuf);
12233
12234   /* The enter and bound instructions are printed with operands in the same
12235      order as the intel book; everything else is printed in reverse order.  */
12236   if (intel_syntax || two_source_ops)
12237     {
12238       bfd_vma riprel;
12239
12240       for (i = 0; i < MAX_OPERANDS; ++i)
12241         op_txt[i] = op_out[i];
12242
12243       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12244           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12245         {
12246           op_txt[2] = op_out[3];
12247           op_txt[3] = op_out[2];
12248         }
12249
12250       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12251         {
12252           op_ad = op_index[i];
12253           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12254           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12255           riprel = op_riprel[i];
12256           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12257           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12258         }
12259     }
12260   else
12261     {
12262       for (i = 0; i < MAX_OPERANDS; ++i)
12263         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12264     }
12265
12266   needcomma = 0;
12267   for (i = 0; i < MAX_OPERANDS; ++i)
12268     if (*op_txt[i])
12269       {
12270         if (needcomma)
12271           (*info->fprintf_func) (info->stream, ",");
12272         if (op_index[i] != -1 && !op_riprel[i])
12273           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12274         else
12275           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12276         needcomma = 1;
12277       }
12278
12279   for (i = 0; i < MAX_OPERANDS; i++)
12280     if (op_index[i] != -1 && op_riprel[i])
12281       {
12282         (*info->fprintf_func) (info->stream, "        # ");
12283         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12284                                                 + op_address[op_index[i]]), info);
12285         break;
12286       }
12287   return codep - priv.the_buffer;
12288 }
12289
12290 static const char *float_mem[] = {
12291   /* d8 */
12292   "fadd{s|}",
12293   "fmul{s|}",
12294   "fcom{s|}",
12295   "fcomp{s|}",
12296   "fsub{s|}",
12297   "fsubr{s|}",
12298   "fdiv{s|}",
12299   "fdivr{s|}",
12300   /* d9 */
12301   "fld{s|}",
12302   "(bad)",
12303   "fst{s|}",
12304   "fstp{s|}",
12305   "fldenvIC",
12306   "fldcw",
12307   "fNstenvIC",
12308   "fNstcw",
12309   /* da */
12310   "fiadd{l|}",
12311   "fimul{l|}",
12312   "ficom{l|}",
12313   "ficomp{l|}",
12314   "fisub{l|}",
12315   "fisubr{l|}",
12316   "fidiv{l|}",
12317   "fidivr{l|}",
12318   /* db */
12319   "fild{l|}",
12320   "fisttp{l|}",
12321   "fist{l|}",
12322   "fistp{l|}",
12323   "(bad)",
12324   "fld{t||t|}",
12325   "(bad)",
12326   "fstp{t||t|}",
12327   /* dc */
12328   "fadd{l|}",
12329   "fmul{l|}",
12330   "fcom{l|}",
12331   "fcomp{l|}",
12332   "fsub{l|}",
12333   "fsubr{l|}",
12334   "fdiv{l|}",
12335   "fdivr{l|}",
12336   /* dd */
12337   "fld{l|}",
12338   "fisttp{ll|}",
12339   "fst{l||}",
12340   "fstp{l|}",
12341   "frstorIC",
12342   "(bad)",
12343   "fNsaveIC",
12344   "fNstsw",
12345   /* de */
12346   "fiadd{s|}",
12347   "fimul{s|}",
12348   "ficom{s|}",
12349   "ficomp{s|}",
12350   "fisub{s|}",
12351   "fisubr{s|}",
12352   "fidiv{s|}",
12353   "fidivr{s|}",
12354   /* df */
12355   "fild{s|}",
12356   "fisttp{s|}",
12357   "fist{s|}",
12358   "fistp{s|}",
12359   "fbld",
12360   "fild{ll|}",
12361   "fbstp",
12362   "fistp{ll|}",
12363 };
12364
12365 static const unsigned char float_mem_mode[] = {
12366   /* d8 */
12367   d_mode,
12368   d_mode,
12369   d_mode,
12370   d_mode,
12371   d_mode,
12372   d_mode,
12373   d_mode,
12374   d_mode,
12375   /* d9 */
12376   d_mode,
12377   0,
12378   d_mode,
12379   d_mode,
12380   0,
12381   w_mode,
12382   0,
12383   w_mode,
12384   /* da */
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   d_mode,
12389   d_mode,
12390   d_mode,
12391   d_mode,
12392   d_mode,
12393   /* db */
12394   d_mode,
12395   d_mode,
12396   d_mode,
12397   d_mode,
12398   0,
12399   t_mode,
12400   0,
12401   t_mode,
12402   /* dc */
12403   q_mode,
12404   q_mode,
12405   q_mode,
12406   q_mode,
12407   q_mode,
12408   q_mode,
12409   q_mode,
12410   q_mode,
12411   /* dd */
12412   q_mode,
12413   q_mode,
12414   q_mode,
12415   q_mode,
12416   0,
12417   0,
12418   0,
12419   w_mode,
12420   /* de */
12421   w_mode,
12422   w_mode,
12423   w_mode,
12424   w_mode,
12425   w_mode,
12426   w_mode,
12427   w_mode,
12428   w_mode,
12429   /* df */
12430   w_mode,
12431   w_mode,
12432   w_mode,
12433   w_mode,
12434   t_mode,
12435   q_mode,
12436   t_mode,
12437   q_mode
12438 };
12439
12440 #define ST { OP_ST, 0 }
12441 #define STi { OP_STi, 0 }
12442
12443 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12444 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12445 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12446 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12447 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12448 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12449 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12450 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12451 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12452
12453 static const struct dis386 float_reg[][8] = {
12454   /* d8 */
12455   {
12456     { "fadd",   { ST, STi }, 0 },
12457     { "fmul",   { ST, STi }, 0 },
12458     { "fcom",   { STi }, 0 },
12459     { "fcomp",  { STi }, 0 },
12460     { "fsub",   { ST, STi }, 0 },
12461     { "fsubr",  { ST, STi }, 0 },
12462     { "fdiv",   { ST, STi }, 0 },
12463     { "fdivr",  { ST, STi }, 0 },
12464   },
12465   /* d9 */
12466   {
12467     { "fld",    { STi }, 0 },
12468     { "fxch",   { STi }, 0 },
12469     { FGRPd9_2 },
12470     { Bad_Opcode },
12471     { FGRPd9_4 },
12472     { FGRPd9_5 },
12473     { FGRPd9_6 },
12474     { FGRPd9_7 },
12475   },
12476   /* da */
12477   {
12478     { "fcmovb", { ST, STi }, 0 },
12479     { "fcmove", { ST, STi }, 0 },
12480     { "fcmovbe",{ ST, STi }, 0 },
12481     { "fcmovu", { ST, STi }, 0 },
12482     { Bad_Opcode },
12483     { FGRPda_5 },
12484     { Bad_Opcode },
12485     { Bad_Opcode },
12486   },
12487   /* db */
12488   {
12489     { "fcmovnb",{ ST, STi }, 0 },
12490     { "fcmovne",{ ST, STi }, 0 },
12491     { "fcmovnbe",{ ST, STi }, 0 },
12492     { "fcmovnu",{ ST, STi }, 0 },
12493     { FGRPdb_4 },
12494     { "fucomi", { ST, STi }, 0 },
12495     { "fcomi",  { ST, STi }, 0 },
12496     { Bad_Opcode },
12497   },
12498   /* dc */
12499   {
12500     { "fadd",   { STi, ST }, 0 },
12501     { "fmul",   { STi, ST }, 0 },
12502     { Bad_Opcode },
12503     { Bad_Opcode },
12504     { "fsub{!M|r}",     { STi, ST }, 0 },
12505     { "fsub{M|}",       { STi, ST }, 0 },
12506     { "fdiv{!M|r}",     { STi, ST }, 0 },
12507     { "fdiv{M|}",       { STi, ST }, 0 },
12508   },
12509   /* dd */
12510   {
12511     { "ffree",  { STi }, 0 },
12512     { Bad_Opcode },
12513     { "fst",    { STi }, 0 },
12514     { "fstp",   { STi }, 0 },
12515     { "fucom",  { STi }, 0 },
12516     { "fucomp", { STi }, 0 },
12517     { Bad_Opcode },
12518     { Bad_Opcode },
12519   },
12520   /* de */
12521   {
12522     { "faddp",  { STi, ST }, 0 },
12523     { "fmulp",  { STi, ST }, 0 },
12524     { Bad_Opcode },
12525     { FGRPde_3 },
12526     { "fsub{!M|r}p",    { STi, ST }, 0 },
12527     { "fsub{M|}p",      { STi, ST }, 0 },
12528     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12529     { "fdiv{M|}p",      { STi, ST }, 0 },
12530   },
12531   /* df */
12532   {
12533     { "ffreep", { STi }, 0 },
12534     { Bad_Opcode },
12535     { Bad_Opcode },
12536     { Bad_Opcode },
12537     { FGRPdf_4 },
12538     { "fucomip", { ST, STi }, 0 },
12539     { "fcomip", { ST, STi }, 0 },
12540     { Bad_Opcode },
12541   },
12542 };
12543
12544 static char *fgrps[][8] = {
12545   /* Bad opcode 0 */
12546   {
12547     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12548   },
12549
12550   /* d9_2  1 */
12551   {
12552     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12553   },
12554
12555   /* d9_4  2 */
12556   {
12557     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12558   },
12559
12560   /* d9_5  3 */
12561   {
12562     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12563   },
12564
12565   /* d9_6  4 */
12566   {
12567     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12568   },
12569
12570   /* d9_7  5 */
12571   {
12572     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12573   },
12574
12575   /* da_5  6 */
12576   {
12577     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12578   },
12579
12580   /* db_4  7 */
12581   {
12582     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12583     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12584   },
12585
12586   /* de_3  8 */
12587   {
12588     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12589   },
12590
12591   /* df_4  9 */
12592   {
12593     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12594   },
12595 };
12596
12597 static void
12598 swap_operand (void)
12599 {
12600   mnemonicendp[0] = '.';
12601   mnemonicendp[1] = 's';
12602   mnemonicendp += 2;
12603 }
12604
12605 static void
12606 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12607                int sizeflag ATTRIBUTE_UNUSED)
12608 {
12609   /* Skip mod/rm byte.  */
12610   MODRM_CHECK;
12611   codep++;
12612 }
12613
12614 static void
12615 dofloat (int sizeflag)
12616 {
12617   const struct dis386 *dp;
12618   unsigned char floatop;
12619
12620   floatop = codep[-1];
12621
12622   if (modrm.mod != 3)
12623     {
12624       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12625
12626       putop (float_mem[fp_indx], sizeflag);
12627       obufp = op_out[0];
12628       op_ad = 2;
12629       OP_E (float_mem_mode[fp_indx], sizeflag);
12630       return;
12631     }
12632   /* Skip mod/rm byte.  */
12633   MODRM_CHECK;
12634   codep++;
12635
12636   dp = &float_reg[floatop - 0xd8][modrm.reg];
12637   if (dp->name == NULL)
12638     {
12639       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12640
12641       /* Instruction fnstsw is only one with strange arg.  */
12642       if (floatop == 0xdf && codep[-1] == 0xe0)
12643         strcpy (op_out[0], names16[0]);
12644     }
12645   else
12646     {
12647       putop (dp->name, sizeflag);
12648
12649       obufp = op_out[0];
12650       op_ad = 2;
12651       if (dp->op[0].rtn)
12652         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12653
12654       obufp = op_out[1];
12655       op_ad = 1;
12656       if (dp->op[1].rtn)
12657         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12658     }
12659 }
12660
12661 /* Like oappend (below), but S is a string starting with '%'.
12662    In Intel syntax, the '%' is elided.  */
12663 static void
12664 oappend_maybe_intel (const char *s)
12665 {
12666   oappend (s + intel_syntax);
12667 }
12668
12669 static void
12670 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12671 {
12672   oappend_maybe_intel ("%st");
12673 }
12674
12675 static void
12676 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12677 {
12678   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12679   oappend_maybe_intel (scratchbuf);
12680 }
12681
12682 /* Capital letters in template are macros.  */
12683 static int
12684 putop (const char *in_template, int sizeflag)
12685 {
12686   const char *p;
12687   int alt = 0;
12688   int cond = 1;
12689   unsigned int l = 0, len = 1;
12690   char last[4];
12691
12692 #define SAVE_LAST(c)                    \
12693   if (l < len && l < sizeof (last))     \
12694     last[l++] = c;                      \
12695   else                                  \
12696     abort ();
12697
12698   for (p = in_template; *p; p++)
12699     {
12700       switch (*p)
12701         {
12702         default:
12703           *obufp++ = *p;
12704           break;
12705         case '%':
12706           len++;
12707           break;
12708         case '!':
12709           cond = 0;
12710           break;
12711         case '{':
12712           if (intel_syntax)
12713             {
12714               while (*++p != '|')
12715                 if (*p == '}' || *p == '\0')
12716                   abort ();
12717             }
12718           /* Fall through.  */
12719         case 'I':
12720           alt = 1;
12721           continue;
12722         case '|':
12723           while (*++p != '}')
12724             {
12725               if (*p == '\0')
12726                 abort ();
12727             }
12728           break;
12729         case '}':
12730           break;
12731         case 'A':
12732           if (intel_syntax)
12733             break;
12734           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12735             *obufp++ = 'b';
12736           break;
12737         case 'B':
12738           if (l == 0 && len == 1)
12739             {
12740 case_B:
12741               if (intel_syntax)
12742                 break;
12743               if (sizeflag & SUFFIX_ALWAYS)
12744                 *obufp++ = 'b';
12745             }
12746           else
12747             {
12748               if (l != 1
12749                   || len != 2
12750                   || last[0] != 'L')
12751                 {
12752                   SAVE_LAST (*p);
12753                   break;
12754                 }
12755
12756               if (address_mode == mode_64bit
12757                   && !(prefixes & PREFIX_ADDR))
12758                 {
12759                   *obufp++ = 'a';
12760                   *obufp++ = 'b';
12761                   *obufp++ = 's';
12762                 }
12763
12764               goto case_B;
12765             }
12766           break;
12767         case 'C':
12768           if (intel_syntax && !alt)
12769             break;
12770           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12771             {
12772               if (sizeflag & DFLAG)
12773                 *obufp++ = intel_syntax ? 'd' : 'l';
12774               else
12775                 *obufp++ = intel_syntax ? 'w' : 's';
12776               used_prefixes |= (prefixes & PREFIX_DATA);
12777             }
12778           break;
12779         case 'D':
12780           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12781             break;
12782           USED_REX (REX_W);
12783           if (modrm.mod == 3)
12784             {
12785               if (rex & REX_W)
12786                 *obufp++ = 'q';
12787               else
12788                 {
12789                   if (sizeflag & DFLAG)
12790                     *obufp++ = intel_syntax ? 'd' : 'l';
12791                   else
12792                     *obufp++ = 'w';
12793                   used_prefixes |= (prefixes & PREFIX_DATA);
12794                 }
12795             }
12796           else
12797             *obufp++ = 'w';
12798           break;
12799         case 'E':               /* For jcxz/jecxz */
12800           if (address_mode == mode_64bit)
12801             {
12802               if (sizeflag & AFLAG)
12803                 *obufp++ = 'r';
12804               else
12805                 *obufp++ = 'e';
12806             }
12807           else
12808             if (sizeflag & AFLAG)
12809               *obufp++ = 'e';
12810           used_prefixes |= (prefixes & PREFIX_ADDR);
12811           break;
12812         case 'F':
12813           if (intel_syntax)
12814             break;
12815           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12816             {
12817               if (sizeflag & AFLAG)
12818                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12819               else
12820                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12821               used_prefixes |= (prefixes & PREFIX_ADDR);
12822             }
12823           break;
12824         case 'G':
12825           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12826             break;
12827           if ((rex & REX_W) || (sizeflag & DFLAG))
12828             *obufp++ = 'l';
12829           else
12830             *obufp++ = 'w';
12831           if (!(rex & REX_W))
12832             used_prefixes |= (prefixes & PREFIX_DATA);
12833           break;
12834         case 'H':
12835           if (intel_syntax)
12836             break;
12837           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12838               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12839             {
12840               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12841               *obufp++ = ',';
12842               *obufp++ = 'p';
12843               if (prefixes & PREFIX_DS)
12844                 *obufp++ = 't';
12845               else
12846                 *obufp++ = 'n';
12847             }
12848           break;
12849         case 'J':
12850           if (intel_syntax)
12851             break;
12852           *obufp++ = 'l';
12853           break;
12854         case 'K':
12855           USED_REX (REX_W);
12856           if (rex & REX_W)
12857             *obufp++ = 'q';
12858           else
12859             *obufp++ = 'd';
12860           break;
12861         case 'Z':
12862           if (l != 0 || len != 1)
12863             {
12864               if (l != 1 || len != 2 || last[0] != 'X')
12865                 {
12866                   SAVE_LAST (*p);
12867                   break;
12868                 }
12869               if (!need_vex || !vex.evex)
12870                 abort ();
12871               if (intel_syntax
12872                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12873                 break;
12874               switch (vex.length)
12875                 {
12876                 case 128:
12877                   *obufp++ = 'x';
12878                   break;
12879                 case 256:
12880                   *obufp++ = 'y';
12881                   break;
12882                 case 512:
12883                   *obufp++ = 'z';
12884                   break;
12885                 default:
12886                   abort ();
12887                 }
12888               break;
12889             }
12890           if (intel_syntax)
12891             break;
12892           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12893             {
12894               *obufp++ = 'q';
12895               break;
12896             }
12897           /* Fall through.  */
12898           goto case_L;
12899         case 'L':
12900           if (l != 0 || len != 1)
12901             {
12902               SAVE_LAST (*p);
12903               break;
12904             }
12905 case_L:
12906           if (intel_syntax)
12907             break;
12908           if (sizeflag & SUFFIX_ALWAYS)
12909             *obufp++ = 'l';
12910           break;
12911         case 'M':
12912           if (intel_mnemonic != cond)
12913             *obufp++ = 'r';
12914           break;
12915         case 'N':
12916           if ((prefixes & PREFIX_FWAIT) == 0)
12917             *obufp++ = 'n';
12918           else
12919             used_prefixes |= PREFIX_FWAIT;
12920           break;
12921         case 'O':
12922           USED_REX (REX_W);
12923           if (rex & REX_W)
12924             *obufp++ = 'o';
12925           else if (intel_syntax && (sizeflag & DFLAG))
12926             *obufp++ = 'q';
12927           else
12928             *obufp++ = 'd';
12929           if (!(rex & REX_W))
12930             used_prefixes |= (prefixes & PREFIX_DATA);
12931           break;
12932         case '&':
12933           if (!intel_syntax
12934               && address_mode == mode_64bit
12935               && isa64 == intel64)
12936             {
12937               *obufp++ = 'q';
12938               break;
12939             }
12940           /* Fall through.  */
12941         case 'T':
12942           if (!intel_syntax
12943               && address_mode == mode_64bit
12944               && ((sizeflag & DFLAG) || (rex & REX_W)))
12945             {
12946               *obufp++ = 'q';
12947               break;
12948             }
12949           /* Fall through.  */
12950           goto case_P;
12951         case 'P':
12952           if (l == 0 && len == 1)
12953             {
12954 case_P:
12955               if (intel_syntax)
12956                 {
12957                   if ((rex & REX_W) == 0
12958                       && (prefixes & PREFIX_DATA))
12959                     {
12960                       if ((sizeflag & DFLAG) == 0)
12961                         *obufp++ = 'w';
12962                       used_prefixes |= (prefixes & PREFIX_DATA);
12963                     }
12964                   break;
12965                 }
12966               if ((prefixes & PREFIX_DATA)
12967                   || (rex & REX_W)
12968                   || (sizeflag & SUFFIX_ALWAYS))
12969                 {
12970                   USED_REX (REX_W);
12971                   if (rex & REX_W)
12972                     *obufp++ = 'q';
12973                   else
12974                     {
12975                       if (sizeflag & DFLAG)
12976                         *obufp++ = 'l';
12977                       else
12978                         *obufp++ = 'w';
12979                       used_prefixes |= (prefixes & PREFIX_DATA);
12980                     }
12981                 }
12982             }
12983           else
12984             {
12985               if (l != 1 || len != 2 || last[0] != 'L')
12986                 {
12987                   SAVE_LAST (*p);
12988                   break;
12989                 }
12990
12991               if ((prefixes & PREFIX_DATA)
12992                   || (rex & REX_W)
12993                   || (sizeflag & SUFFIX_ALWAYS))
12994                 {
12995                   USED_REX (REX_W);
12996                   if (rex & REX_W)
12997                     *obufp++ = 'q';
12998                   else
12999                     {
13000                       if (sizeflag & DFLAG)
13001                         *obufp++ = intel_syntax ? 'd' : 'l';
13002                       else
13003                         *obufp++ = 'w';
13004                       used_prefixes |= (prefixes & PREFIX_DATA);
13005                     }
13006                 }
13007             }
13008           break;
13009         case 'U':
13010           if (intel_syntax)
13011             break;
13012           if (address_mode == mode_64bit
13013               && ((sizeflag & DFLAG) || (rex & REX_W)))
13014             {
13015               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13016                 *obufp++ = 'q';
13017               break;
13018             }
13019           /* Fall through.  */
13020           goto case_Q;
13021         case 'Q':
13022           if (l == 0 && len == 1)
13023             {
13024 case_Q:
13025               if (intel_syntax && !alt)
13026                 break;
13027               USED_REX (REX_W);
13028               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13029                 {
13030                   if (rex & REX_W)
13031                     *obufp++ = 'q';
13032                   else
13033                     {
13034                       if (sizeflag & DFLAG)
13035                         *obufp++ = intel_syntax ? 'd' : 'l';
13036                       else
13037                         *obufp++ = 'w';
13038                       used_prefixes |= (prefixes & PREFIX_DATA);
13039                     }
13040                 }
13041             }
13042           else
13043             {
13044               if (l != 1 || len != 2 || last[0] != 'L')
13045                 {
13046                   SAVE_LAST (*p);
13047                   break;
13048                 }
13049               if (intel_syntax
13050                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13051                 break;
13052               if ((rex & REX_W))
13053                 {
13054                   USED_REX (REX_W);
13055                   *obufp++ = 'q';
13056                 }
13057               else
13058                 *obufp++ = 'l';
13059             }
13060           break;
13061         case 'R':
13062           USED_REX (REX_W);
13063           if (rex & REX_W)
13064             *obufp++ = 'q';
13065           else if (sizeflag & DFLAG)
13066             {
13067               if (intel_syntax)
13068                   *obufp++ = 'd';
13069               else
13070                   *obufp++ = 'l';
13071             }
13072           else
13073             *obufp++ = 'w';
13074           if (intel_syntax && !p[1]
13075               && ((rex & REX_W) || (sizeflag & DFLAG)))
13076             *obufp++ = 'e';
13077           if (!(rex & REX_W))
13078             used_prefixes |= (prefixes & PREFIX_DATA);
13079           break;
13080         case 'V':
13081           if (l == 0 && len == 1)
13082             {
13083               if (intel_syntax)
13084                 break;
13085               if (address_mode == mode_64bit
13086                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13087                 {
13088                   if (sizeflag & SUFFIX_ALWAYS)
13089                     *obufp++ = 'q';
13090                   break;
13091                 }
13092             }
13093           else
13094             {
13095               if (l != 1
13096                   || len != 2
13097                   || last[0] != 'L')
13098                 {
13099                   SAVE_LAST (*p);
13100                   break;
13101                 }
13102
13103               if (rex & REX_W)
13104                 {
13105                   *obufp++ = 'a';
13106                   *obufp++ = 'b';
13107                   *obufp++ = 's';
13108                 }
13109             }
13110           /* Fall through.  */
13111           goto case_S;
13112         case 'S':
13113           if (l == 0 && len == 1)
13114             {
13115 case_S:
13116               if (intel_syntax)
13117                 break;
13118               if (sizeflag & SUFFIX_ALWAYS)
13119                 {
13120                   if (rex & REX_W)
13121                     *obufp++ = 'q';
13122                   else
13123                     {
13124                       if (sizeflag & DFLAG)
13125                         *obufp++ = 'l';
13126                       else
13127                         *obufp++ = 'w';
13128                       used_prefixes |= (prefixes & PREFIX_DATA);
13129                     }
13130                 }
13131             }
13132           else
13133             {
13134               if (l != 1
13135                   || len != 2
13136                   || last[0] != 'L')
13137                 {
13138                   SAVE_LAST (*p);
13139                   break;
13140                 }
13141
13142               if (address_mode == mode_64bit
13143                   && !(prefixes & PREFIX_ADDR))
13144                 {
13145                   *obufp++ = 'a';
13146                   *obufp++ = 'b';
13147                   *obufp++ = 's';
13148                 }
13149
13150               goto case_S;
13151             }
13152           break;
13153         case 'X':
13154           if (l != 0 || len != 1)
13155             {
13156               SAVE_LAST (*p);
13157               break;
13158             }
13159           if (need_vex && vex.prefix)
13160             {
13161               if (vex.prefix == DATA_PREFIX_OPCODE)
13162                 *obufp++ = 'd';
13163               else
13164                 *obufp++ = 's';
13165             }
13166           else
13167             {
13168               if (prefixes & PREFIX_DATA)
13169                 *obufp++ = 'd';
13170               else
13171                 *obufp++ = 's';
13172               used_prefixes |= (prefixes & PREFIX_DATA);
13173             }
13174           break;
13175         case 'Y':
13176           if (l == 0 && len == 1)
13177             abort ();
13178           else
13179             {
13180               if (l != 1 || len != 2 || last[0] != 'X')
13181                 {
13182                   SAVE_LAST (*p);
13183                   break;
13184                 }
13185               if (!need_vex)
13186                 abort ();
13187               if (intel_syntax
13188                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13189                 break;
13190               switch (vex.length)
13191                 {
13192                 case 128:
13193                   *obufp++ = 'x';
13194                   break;
13195                 case 256:
13196                   *obufp++ = 'y';
13197                   break;
13198                 case 512:
13199                   if (!vex.evex)
13200                 default:
13201                     abort ();
13202                 }
13203             }
13204           break;
13205         case 'W':
13206           if (l == 0 && len == 1)
13207             {
13208               /* operand size flag for cwtl, cbtw */
13209               USED_REX (REX_W);
13210               if (rex & REX_W)
13211                 {
13212                   if (intel_syntax)
13213                     *obufp++ = 'd';
13214                   else
13215                     *obufp++ = 'l';
13216                 }
13217               else if (sizeflag & DFLAG)
13218                 *obufp++ = 'w';
13219               else
13220                 *obufp++ = 'b';
13221               if (!(rex & REX_W))
13222                 used_prefixes |= (prefixes & PREFIX_DATA);
13223             }
13224           else
13225             {
13226               if (l != 1
13227                   || len != 2
13228                   || (last[0] != 'X'
13229                       && last[0] != 'L'))
13230                 {
13231                   SAVE_LAST (*p);
13232                   break;
13233                 }
13234               if (!need_vex)
13235                 abort ();
13236               if (last[0] == 'X')
13237                 *obufp++ = vex.w ? 'd': 's';
13238               else
13239                 *obufp++ = vex.w ? 'q': 'd';
13240             }
13241           break;
13242         case '^':
13243           if (intel_syntax)
13244             break;
13245           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13246             {
13247               if (sizeflag & DFLAG)
13248                 *obufp++ = 'l';
13249               else
13250                 *obufp++ = 'w';
13251               used_prefixes |= (prefixes & PREFIX_DATA);
13252             }
13253           break;
13254         case '@':
13255           if (intel_syntax)
13256             break;
13257           if (address_mode == mode_64bit
13258               && (isa64 == intel64
13259                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13260               *obufp++ = 'q';
13261           else if ((prefixes & PREFIX_DATA))
13262             {
13263               if (!(sizeflag & DFLAG))
13264                 *obufp++ = 'w';
13265               used_prefixes |= (prefixes & PREFIX_DATA);
13266             }
13267           break;
13268         }
13269       alt = 0;
13270     }
13271   *obufp = 0;
13272   mnemonicendp = obufp;
13273   return 0;
13274 }
13275
13276 static void
13277 oappend (const char *s)
13278 {
13279   obufp = stpcpy (obufp, s);
13280 }
13281
13282 static void
13283 append_seg (void)
13284 {
13285   /* Only print the active segment register.  */
13286   if (!active_seg_prefix)
13287     return;
13288
13289   used_prefixes |= active_seg_prefix;
13290   switch (active_seg_prefix)
13291     {
13292     case PREFIX_CS:
13293       oappend_maybe_intel ("%cs:");
13294       break;
13295     case PREFIX_DS:
13296       oappend_maybe_intel ("%ds:");
13297       break;
13298     case PREFIX_SS:
13299       oappend_maybe_intel ("%ss:");
13300       break;
13301     case PREFIX_ES:
13302       oappend_maybe_intel ("%es:");
13303       break;
13304     case PREFIX_FS:
13305       oappend_maybe_intel ("%fs:");
13306       break;
13307     case PREFIX_GS:
13308       oappend_maybe_intel ("%gs:");
13309       break;
13310     default:
13311       break;
13312     }
13313 }
13314
13315 static void
13316 OP_indirE (int bytemode, int sizeflag)
13317 {
13318   if (!intel_syntax)
13319     oappend ("*");
13320   OP_E (bytemode, sizeflag);
13321 }
13322
13323 static void
13324 print_operand_value (char *buf, int hex, bfd_vma disp)
13325 {
13326   if (address_mode == mode_64bit)
13327     {
13328       if (hex)
13329         {
13330           char tmp[30];
13331           int i;
13332           buf[0] = '0';
13333           buf[1] = 'x';
13334           sprintf_vma (tmp, disp);
13335           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13336           strcpy (buf + 2, tmp + i);
13337         }
13338       else
13339         {
13340           bfd_signed_vma v = disp;
13341           char tmp[30];
13342           int i;
13343           if (v < 0)
13344             {
13345               *(buf++) = '-';
13346               v = -disp;
13347               /* Check for possible overflow on 0x8000000000000000.  */
13348               if (v < 0)
13349                 {
13350                   strcpy (buf, "9223372036854775808");
13351                   return;
13352                 }
13353             }
13354           if (!v)
13355             {
13356               strcpy (buf, "0");
13357               return;
13358             }
13359
13360           i = 0;
13361           tmp[29] = 0;
13362           while (v)
13363             {
13364               tmp[28 - i] = (v % 10) + '0';
13365               v /= 10;
13366               i++;
13367             }
13368           strcpy (buf, tmp + 29 - i);
13369         }
13370     }
13371   else
13372     {
13373       if (hex)
13374         sprintf (buf, "0x%x", (unsigned int) disp);
13375       else
13376         sprintf (buf, "%d", (int) disp);
13377     }
13378 }
13379
13380 /* Put DISP in BUF as signed hex number.  */
13381
13382 static void
13383 print_displacement (char *buf, bfd_vma disp)
13384 {
13385   bfd_signed_vma val = disp;
13386   char tmp[30];
13387   int i, j = 0;
13388
13389   if (val < 0)
13390     {
13391       buf[j++] = '-';
13392       val = -disp;
13393
13394       /* Check for possible overflow.  */
13395       if (val < 0)
13396         {
13397           switch (address_mode)
13398             {
13399             case mode_64bit:
13400               strcpy (buf + j, "0x8000000000000000");
13401               break;
13402             case mode_32bit:
13403               strcpy (buf + j, "0x80000000");
13404               break;
13405             case mode_16bit:
13406               strcpy (buf + j, "0x8000");
13407               break;
13408             }
13409           return;
13410         }
13411     }
13412
13413   buf[j++] = '0';
13414   buf[j++] = 'x';
13415
13416   sprintf_vma (tmp, (bfd_vma) val);
13417   for (i = 0; tmp[i] == '0'; i++)
13418     continue;
13419   if (tmp[i] == '\0')
13420     i--;
13421   strcpy (buf + j, tmp + i);
13422 }
13423
13424 static void
13425 intel_operand_size (int bytemode, int sizeflag)
13426 {
13427   if (vex.evex
13428       && vex.b
13429       && (bytemode == x_mode
13430           || bytemode == evex_half_bcst_xmmq_mode))
13431     {
13432       if (vex.w)
13433         oappend ("QWORD PTR ");
13434       else
13435         oappend ("DWORD PTR ");
13436       return;
13437     }
13438   switch (bytemode)
13439     {
13440     case b_mode:
13441     case b_swap_mode:
13442     case dqb_mode:
13443     case db_mode:
13444       oappend ("BYTE PTR ");
13445       break;
13446     case w_mode:
13447     case dw_mode:
13448     case dqw_mode:
13449       oappend ("WORD PTR ");
13450       break;
13451     case indir_v_mode:
13452       if (address_mode == mode_64bit && isa64 == intel64)
13453         {
13454           oappend ("QWORD PTR ");
13455           break;
13456         }
13457       /* Fall through.  */
13458     case stack_v_mode:
13459       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13460         {
13461           oappend ("QWORD PTR ");
13462           break;
13463         }
13464       /* Fall through.  */
13465     case v_mode:
13466     case v_swap_mode:
13467     case dq_mode:
13468       USED_REX (REX_W);
13469       if (rex & REX_W)
13470         oappend ("QWORD PTR ");
13471       else
13472         {
13473           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13474             oappend ("DWORD PTR ");
13475           else
13476             oappend ("WORD PTR ");
13477           used_prefixes |= (prefixes & PREFIX_DATA);
13478         }
13479       break;
13480     case z_mode:
13481       if ((rex & REX_W) || (sizeflag & DFLAG))
13482         *obufp++ = 'D';
13483       oappend ("WORD PTR ");
13484       if (!(rex & REX_W))
13485         used_prefixes |= (prefixes & PREFIX_DATA);
13486       break;
13487     case a_mode:
13488       if (sizeflag & DFLAG)
13489         oappend ("QWORD PTR ");
13490       else
13491         oappend ("DWORD PTR ");
13492       used_prefixes |= (prefixes & PREFIX_DATA);
13493       break;
13494     case d_mode:
13495     case d_scalar_mode:
13496     case d_scalar_swap_mode:
13497     case d_swap_mode:
13498     case dqd_mode:
13499       oappend ("DWORD PTR ");
13500       break;
13501     case q_mode:
13502     case q_scalar_mode:
13503     case q_scalar_swap_mode:
13504     case q_swap_mode:
13505       oappend ("QWORD PTR ");
13506       break;
13507     case dqa_mode:
13508     case m_mode:
13509       if (address_mode == mode_64bit)
13510         oappend ("QWORD PTR ");
13511       else
13512         oappend ("DWORD PTR ");
13513       break;
13514     case f_mode:
13515       if (sizeflag & DFLAG)
13516         oappend ("FWORD PTR ");
13517       else
13518         oappend ("DWORD PTR ");
13519       used_prefixes |= (prefixes & PREFIX_DATA);
13520       break;
13521     case t_mode:
13522       oappend ("TBYTE PTR ");
13523       break;
13524     case x_mode:
13525     case x_swap_mode:
13526     case evex_x_gscat_mode:
13527     case evex_x_nobcst_mode:
13528     case b_scalar_mode:
13529     case w_scalar_mode:
13530       if (need_vex)
13531         {
13532           switch (vex.length)
13533             {
13534             case 128:
13535               oappend ("XMMWORD PTR ");
13536               break;
13537             case 256:
13538               oappend ("YMMWORD PTR ");
13539               break;
13540             case 512:
13541               oappend ("ZMMWORD PTR ");
13542               break;
13543             default:
13544               abort ();
13545             }
13546         }
13547       else
13548         oappend ("XMMWORD PTR ");
13549       break;
13550     case xmm_mode:
13551       oappend ("XMMWORD PTR ");
13552       break;
13553     case ymm_mode:
13554       oappend ("YMMWORD PTR ");
13555       break;
13556     case xmmq_mode:
13557     case evex_half_bcst_xmmq_mode:
13558       if (!need_vex)
13559         abort ();
13560
13561       switch (vex.length)
13562         {
13563         case 128:
13564           oappend ("QWORD PTR ");
13565           break;
13566         case 256:
13567           oappend ("XMMWORD PTR ");
13568           break;
13569         case 512:
13570           oappend ("YMMWORD PTR ");
13571           break;
13572         default:
13573           abort ();
13574         }
13575       break;
13576     case xmm_mb_mode:
13577       if (!need_vex)
13578         abort ();
13579
13580       switch (vex.length)
13581         {
13582         case 128:
13583         case 256:
13584         case 512:
13585           oappend ("BYTE PTR ");
13586           break;
13587         default:
13588           abort ();
13589         }
13590       break;
13591     case xmm_mw_mode:
13592       if (!need_vex)
13593         abort ();
13594
13595       switch (vex.length)
13596         {
13597         case 128:
13598         case 256:
13599         case 512:
13600           oappend ("WORD PTR ");
13601           break;
13602         default:
13603           abort ();
13604         }
13605       break;
13606     case xmm_md_mode:
13607       if (!need_vex)
13608         abort ();
13609
13610       switch (vex.length)
13611         {
13612         case 128:
13613         case 256:
13614         case 512:
13615           oappend ("DWORD PTR ");
13616           break;
13617         default:
13618           abort ();
13619         }
13620       break;
13621     case xmm_mq_mode:
13622       if (!need_vex)
13623         abort ();
13624
13625       switch (vex.length)
13626         {
13627         case 128:
13628         case 256:
13629         case 512:
13630           oappend ("QWORD PTR ");
13631           break;
13632         default:
13633           abort ();
13634         }
13635       break;
13636     case xmmdw_mode:
13637       if (!need_vex)
13638         abort ();
13639
13640       switch (vex.length)
13641         {
13642         case 128:
13643           oappend ("WORD PTR ");
13644           break;
13645         case 256:
13646           oappend ("DWORD PTR ");
13647           break;
13648         case 512:
13649           oappend ("QWORD PTR ");
13650           break;
13651         default:
13652           abort ();
13653         }
13654       break;
13655     case xmmqd_mode:
13656       if (!need_vex)
13657         abort ();
13658
13659       switch (vex.length)
13660         {
13661         case 128:
13662           oappend ("DWORD PTR ");
13663           break;
13664         case 256:
13665           oappend ("QWORD PTR ");
13666           break;
13667         case 512:
13668           oappend ("XMMWORD PTR ");
13669           break;
13670         default:
13671           abort ();
13672         }
13673       break;
13674     case ymmq_mode:
13675       if (!need_vex)
13676         abort ();
13677
13678       switch (vex.length)
13679         {
13680         case 128:
13681           oappend ("QWORD PTR ");
13682           break;
13683         case 256:
13684           oappend ("YMMWORD PTR ");
13685           break;
13686         case 512:
13687           oappend ("ZMMWORD PTR ");
13688           break;
13689         default:
13690           abort ();
13691         }
13692       break;
13693     case ymmxmm_mode:
13694       if (!need_vex)
13695         abort ();
13696
13697       switch (vex.length)
13698         {
13699         case 128:
13700         case 256:
13701           oappend ("XMMWORD PTR ");
13702           break;
13703         default:
13704           abort ();
13705         }
13706       break;
13707     case o_mode:
13708       oappend ("OWORD PTR ");
13709       break;
13710     case xmm_mdq_mode:
13711     case vex_w_dq_mode:
13712     case vex_scalar_w_dq_mode:
13713       if (!need_vex)
13714         abort ();
13715
13716       if (vex.w)
13717         oappend ("QWORD PTR ");
13718       else
13719         oappend ("DWORD PTR ");
13720       break;
13721     case vex_vsib_d_w_dq_mode:
13722     case vex_vsib_q_w_dq_mode:
13723       if (!need_vex)
13724         abort ();
13725
13726       if (!vex.evex)
13727         {
13728           if (vex.w)
13729             oappend ("QWORD PTR ");
13730           else
13731             oappend ("DWORD PTR ");
13732         }
13733       else
13734         {
13735           switch (vex.length)
13736             {
13737             case 128:
13738               oappend ("XMMWORD PTR ");
13739               break;
13740             case 256:
13741               oappend ("YMMWORD PTR ");
13742               break;
13743             case 512:
13744               oappend ("ZMMWORD PTR ");
13745               break;
13746             default:
13747               abort ();
13748             }
13749         }
13750       break;
13751     case vex_vsib_q_w_d_mode:
13752     case vex_vsib_d_w_d_mode:
13753       if (!need_vex || !vex.evex)
13754         abort ();
13755
13756       switch (vex.length)
13757         {
13758         case 128:
13759           oappend ("QWORD PTR ");
13760           break;
13761         case 256:
13762           oappend ("XMMWORD PTR ");
13763           break;
13764         case 512:
13765           oappend ("YMMWORD PTR ");
13766           break;
13767         default:
13768           abort ();
13769         }
13770
13771       break;
13772     case mask_bd_mode:
13773       if (!need_vex || vex.length != 128)
13774         abort ();
13775       if (vex.w)
13776         oappend ("DWORD PTR ");
13777       else
13778         oappend ("BYTE PTR ");
13779       break;
13780     case mask_mode:
13781       if (!need_vex)
13782         abort ();
13783       if (vex.w)
13784         oappend ("QWORD PTR ");
13785       else
13786         oappend ("WORD PTR ");
13787       break;
13788     case v_bnd_mode:
13789     case v_bndmk_mode:
13790     default:
13791       break;
13792     }
13793 }
13794
13795 static void
13796 OP_E_register (int bytemode, int sizeflag)
13797 {
13798   int reg = modrm.rm;
13799   const char **names;
13800
13801   USED_REX (REX_B);
13802   if ((rex & REX_B))
13803     reg += 8;
13804
13805   if ((sizeflag & SUFFIX_ALWAYS)
13806       && (bytemode == b_swap_mode
13807           || bytemode == bnd_swap_mode
13808           || bytemode == v_swap_mode))
13809     swap_operand ();
13810
13811   switch (bytemode)
13812     {
13813     case b_mode:
13814     case b_swap_mode:
13815       USED_REX (0);
13816       if (rex)
13817         names = names8rex;
13818       else
13819         names = names8;
13820       break;
13821     case w_mode:
13822       names = names16;
13823       break;
13824     case d_mode:
13825     case dw_mode:
13826     case db_mode:
13827       names = names32;
13828       break;
13829     case q_mode:
13830       names = names64;
13831       break;
13832     case m_mode:
13833     case v_bnd_mode:
13834       names = address_mode == mode_64bit ? names64 : names32;
13835       break;
13836     case bnd_mode:
13837     case bnd_swap_mode:
13838       if (reg > 0x3)
13839         {
13840           oappend ("(bad)");
13841           return;
13842         }
13843       names = names_bnd;
13844       break;
13845     case indir_v_mode:
13846       if (address_mode == mode_64bit && isa64 == intel64)
13847         {
13848           names = names64;
13849           break;
13850         }
13851       /* Fall through.  */
13852     case stack_v_mode:
13853       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13854         {
13855           names = names64;
13856           break;
13857         }
13858       bytemode = v_mode;
13859       /* Fall through.  */
13860     case v_mode:
13861     case v_swap_mode:
13862     case dq_mode:
13863     case dqb_mode:
13864     case dqd_mode:
13865     case dqw_mode:
13866     case dqa_mode:
13867       USED_REX (REX_W);
13868       if (rex & REX_W)
13869         names = names64;
13870       else
13871         {
13872           if ((sizeflag & DFLAG)
13873               || (bytemode != v_mode
13874                   && bytemode != v_swap_mode))
13875             names = names32;
13876           else
13877             names = names16;
13878           used_prefixes |= (prefixes & PREFIX_DATA);
13879         }
13880       break;
13881     case va_mode:
13882       names = (address_mode == mode_64bit
13883                ? names64 : names32);
13884       if (!(prefixes & PREFIX_ADDR))
13885         names = (address_mode == mode_16bit
13886                      ? names16 : names);
13887       else
13888         {
13889           /* Remove "addr16/addr32".  */
13890           all_prefixes[last_addr_prefix] = 0;
13891           names = (address_mode != mode_32bit
13892                        ? names32 : names16);
13893           used_prefixes |= PREFIX_ADDR;
13894         }
13895       break;
13896     case mask_bd_mode:
13897     case mask_mode:
13898       if (reg > 0x7)
13899         {
13900           oappend ("(bad)");
13901           return;
13902         }
13903       names = names_mask;
13904       break;
13905     case 0:
13906       return;
13907     default:
13908       oappend (INTERNAL_DISASSEMBLER_ERROR);
13909       return;
13910     }
13911   oappend (names[reg]);
13912 }
13913
13914 static void
13915 OP_E_memory (int bytemode, int sizeflag)
13916 {
13917   bfd_vma disp = 0;
13918   int add = (rex & REX_B) ? 8 : 0;
13919   int riprel = 0;
13920   int shift;
13921
13922   if (vex.evex)
13923     {
13924       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13925       if (vex.b
13926           && bytemode != x_mode
13927           && bytemode != xmmq_mode
13928           && bytemode != evex_half_bcst_xmmq_mode)
13929         {
13930           BadOp ();
13931           return;
13932         }
13933       switch (bytemode)
13934         {
13935         case dqw_mode:
13936         case dw_mode:
13937           shift = 1;
13938           break;
13939         case dqb_mode:
13940         case db_mode:
13941           shift = 0;
13942           break;
13943         case dq_mode:
13944           if (address_mode != mode_64bit)
13945             {
13946               shift = 2;
13947               break;
13948             }
13949             /* fall through */
13950         case vex_vsib_d_w_dq_mode:
13951         case vex_vsib_d_w_d_mode:
13952         case vex_vsib_q_w_dq_mode:
13953         case vex_vsib_q_w_d_mode:
13954         case evex_x_gscat_mode:
13955         case xmm_mdq_mode:
13956           shift = vex.w ? 3 : 2;
13957           break;
13958         case x_mode:
13959         case evex_half_bcst_xmmq_mode:
13960         case xmmq_mode:
13961           if (vex.b)
13962             {
13963               shift = vex.w ? 3 : 2;
13964               break;
13965             }
13966           /* Fall through.  */
13967         case xmmqd_mode:
13968         case xmmdw_mode:
13969         case ymmq_mode:
13970         case evex_x_nobcst_mode:
13971         case x_swap_mode:
13972           switch (vex.length)
13973             {
13974             case 128:
13975               shift = 4;
13976               break;
13977             case 256:
13978               shift = 5;
13979               break;
13980             case 512:
13981               shift = 6;
13982               break;
13983             default:
13984               abort ();
13985             }
13986           break;
13987         case ymm_mode:
13988           shift = 5;
13989           break;
13990         case xmm_mode:
13991           shift = 4;
13992           break;
13993         case xmm_mq_mode:
13994         case q_mode:
13995         case q_scalar_mode:
13996         case q_swap_mode:
13997         case q_scalar_swap_mode:
13998           shift = 3;
13999           break;
14000         case dqd_mode:
14001         case xmm_md_mode:
14002         case d_mode:
14003         case d_scalar_mode:
14004         case d_swap_mode:
14005         case d_scalar_swap_mode:
14006           shift = 2;
14007           break;
14008         case w_scalar_mode:
14009         case xmm_mw_mode:
14010           shift = 1;
14011           break;
14012         case b_scalar_mode:
14013         case xmm_mb_mode:
14014           shift = 0;
14015           break;
14016         case dqa_mode:
14017           shift = address_mode == mode_64bit ? 3 : 2;
14018           break;
14019         default:
14020           abort ();
14021         }
14022       /* Make necessary corrections to shift for modes that need it.
14023          For these modes we currently have shift 4, 5 or 6 depending on
14024          vex.length (it corresponds to xmmword, ymmword or zmmword
14025          operand).  We might want to make it 3, 4 or 5 (e.g. for
14026          xmmq_mode).  In case of broadcast enabled the corrections
14027          aren't needed, as element size is always 32 or 64 bits.  */
14028       if (!vex.b
14029           && (bytemode == xmmq_mode
14030               || bytemode == evex_half_bcst_xmmq_mode))
14031         shift -= 1;
14032       else if (bytemode == xmmqd_mode)
14033         shift -= 2;
14034       else if (bytemode == xmmdw_mode)
14035         shift -= 3;
14036       else if (bytemode == ymmq_mode && vex.length == 128)
14037         shift -= 1;
14038     }
14039   else
14040     shift = 0;
14041
14042   USED_REX (REX_B);
14043   if (intel_syntax)
14044     intel_operand_size (bytemode, sizeflag);
14045   append_seg ();
14046
14047   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14048     {
14049       /* 32/64 bit address mode */
14050       int havedisp;
14051       int havesib;
14052       int havebase;
14053       int haveindex;
14054       int needindex;
14055       int needaddr32;
14056       int base, rbase;
14057       int vindex = 0;
14058       int scale = 0;
14059       int addr32flag = !((sizeflag & AFLAG)
14060                          || bytemode == v_bnd_mode
14061                          || bytemode == v_bndmk_mode
14062                          || bytemode == bnd_mode
14063                          || bytemode == bnd_swap_mode);
14064       const char **indexes64 = names64;
14065       const char **indexes32 = names32;
14066
14067       havesib = 0;
14068       havebase = 1;
14069       haveindex = 0;
14070       base = modrm.rm;
14071
14072       if (base == 4)
14073         {
14074           havesib = 1;
14075           vindex = sib.index;
14076           USED_REX (REX_X);
14077           if (rex & REX_X)
14078             vindex += 8;
14079           switch (bytemode)
14080             {
14081             case vex_vsib_d_w_dq_mode:
14082             case vex_vsib_d_w_d_mode:
14083             case vex_vsib_q_w_dq_mode:
14084             case vex_vsib_q_w_d_mode:
14085               if (!need_vex)
14086                 abort ();
14087               if (vex.evex)
14088                 {
14089                   if (!vex.v)
14090                     vindex += 16;
14091                 }
14092
14093               haveindex = 1;
14094               switch (vex.length)
14095                 {
14096                 case 128:
14097                   indexes64 = indexes32 = names_xmm;
14098                   break;
14099                 case 256:
14100                   if (!vex.w
14101                       || bytemode == vex_vsib_q_w_dq_mode
14102                       || bytemode == vex_vsib_q_w_d_mode)
14103                     indexes64 = indexes32 = names_ymm;
14104                   else
14105                     indexes64 = indexes32 = names_xmm;
14106                   break;
14107                 case 512:
14108                   if (!vex.w
14109                       || bytemode == vex_vsib_q_w_dq_mode
14110                       || bytemode == vex_vsib_q_w_d_mode)
14111                     indexes64 = indexes32 = names_zmm;
14112                   else
14113                     indexes64 = indexes32 = names_ymm;
14114                   break;
14115                 default:
14116                   abort ();
14117                 }
14118               break;
14119             default:
14120               haveindex = vindex != 4;
14121               break;
14122             }
14123           scale = sib.scale;
14124           base = sib.base;
14125           codep++;
14126         }
14127       rbase = base + add;
14128
14129       switch (modrm.mod)
14130         {
14131         case 0:
14132           if (base == 5)
14133             {
14134               havebase = 0;
14135               if (address_mode == mode_64bit && !havesib)
14136                 riprel = 1;
14137               disp = get32s ();
14138               if (riprel && bytemode == v_bndmk_mode)
14139                 {
14140                   oappend ("(bad)");
14141                   return;
14142                 }
14143             }
14144           break;
14145         case 1:
14146           FETCH_DATA (the_info, codep + 1);
14147           disp = *codep++;
14148           if ((disp & 0x80) != 0)
14149             disp -= 0x100;
14150           if (vex.evex && shift > 0)
14151             disp <<= shift;
14152           break;
14153         case 2:
14154           disp = get32s ();
14155           break;
14156         }
14157
14158       needindex = 0;
14159       needaddr32 = 0;
14160       if (havesib
14161           && !havebase
14162           && !haveindex
14163           && address_mode != mode_16bit)
14164         {
14165           if (address_mode == mode_64bit)
14166             {
14167               /* Display eiz instead of addr32.  */
14168               needindex = addr32flag;
14169               needaddr32 = 1;
14170             }
14171           else
14172             {
14173               /* In 32-bit mode, we need index register to tell [offset]
14174                  from [eiz*1 + offset].  */
14175               needindex = 1;
14176             }
14177         }
14178
14179       havedisp = (havebase
14180                   || needindex
14181                   || (havesib && (haveindex || scale != 0)));
14182
14183       if (!intel_syntax)
14184         if (modrm.mod != 0 || base == 5)
14185           {
14186             if (havedisp || riprel)
14187               print_displacement (scratchbuf, disp);
14188             else
14189               print_operand_value (scratchbuf, 1, disp);
14190             oappend (scratchbuf);
14191             if (riprel)
14192               {
14193                 set_op (disp, 1);
14194                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14195               }
14196           }
14197
14198       if ((havebase || haveindex || needaddr32 || riprel)
14199           && (bytemode != v_bnd_mode)
14200           && (bytemode != v_bndmk_mode)
14201           && (bytemode != bnd_mode)
14202           && (bytemode != bnd_swap_mode))
14203         used_prefixes |= PREFIX_ADDR;
14204
14205       if (havedisp || (intel_syntax && riprel))
14206         {
14207           *obufp++ = open_char;
14208           if (intel_syntax && riprel)
14209             {
14210               set_op (disp, 1);
14211               oappend (!addr32flag ? "rip" : "eip");
14212             }
14213           *obufp = '\0';
14214           if (havebase)
14215             oappend (address_mode == mode_64bit && !addr32flag
14216                      ? names64[rbase] : names32[rbase]);
14217           if (havesib)
14218             {
14219               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14220                  print index to tell base + index from base.  */
14221               if (scale != 0
14222                   || needindex
14223                   || haveindex
14224                   || (havebase && base != ESP_REG_NUM))
14225                 {
14226                   if (!intel_syntax || havebase)
14227                     {
14228                       *obufp++ = separator_char;
14229                       *obufp = '\0';
14230                     }
14231                   if (haveindex)
14232                     oappend (address_mode == mode_64bit && !addr32flag
14233                              ? indexes64[vindex] : indexes32[vindex]);
14234                   else
14235                     oappend (address_mode == mode_64bit && !addr32flag
14236                              ? index64 : index32);
14237
14238                   *obufp++ = scale_char;
14239                   *obufp = '\0';
14240                   sprintf (scratchbuf, "%d", 1 << scale);
14241                   oappend (scratchbuf);
14242                 }
14243             }
14244           if (intel_syntax
14245               && (disp || modrm.mod != 0 || base == 5))
14246             {
14247               if (!havedisp || (bfd_signed_vma) disp >= 0)
14248                 {
14249                   *obufp++ = '+';
14250                   *obufp = '\0';
14251                 }
14252               else if (modrm.mod != 1 && disp != -disp)
14253                 {
14254                   *obufp++ = '-';
14255                   *obufp = '\0';
14256                   disp = - (bfd_signed_vma) disp;
14257                 }
14258
14259               if (havedisp)
14260                 print_displacement (scratchbuf, disp);
14261               else
14262                 print_operand_value (scratchbuf, 1, disp);
14263               oappend (scratchbuf);
14264             }
14265
14266           *obufp++ = close_char;
14267           *obufp = '\0';
14268         }
14269       else if (intel_syntax)
14270         {
14271           if (modrm.mod != 0 || base == 5)
14272             {
14273               if (!active_seg_prefix)
14274                 {
14275                   oappend (names_seg[ds_reg - es_reg]);
14276                   oappend (":");
14277                 }
14278               print_operand_value (scratchbuf, 1, disp);
14279               oappend (scratchbuf);
14280             }
14281         }
14282     }
14283   else
14284     {
14285       /* 16 bit address mode */
14286       used_prefixes |= prefixes & PREFIX_ADDR;
14287       switch (modrm.mod)
14288         {
14289         case 0:
14290           if (modrm.rm == 6)
14291             {
14292               disp = get16 ();
14293               if ((disp & 0x8000) != 0)
14294                 disp -= 0x10000;
14295             }
14296           break;
14297         case 1:
14298           FETCH_DATA (the_info, codep + 1);
14299           disp = *codep++;
14300           if ((disp & 0x80) != 0)
14301             disp -= 0x100;
14302           if (vex.evex && shift > 0)
14303             disp <<= shift;
14304           break;
14305         case 2:
14306           disp = get16 ();
14307           if ((disp & 0x8000) != 0)
14308             disp -= 0x10000;
14309           break;
14310         }
14311
14312       if (!intel_syntax)
14313         if (modrm.mod != 0 || modrm.rm == 6)
14314           {
14315             print_displacement (scratchbuf, disp);
14316             oappend (scratchbuf);
14317           }
14318
14319       if (modrm.mod != 0 || modrm.rm != 6)
14320         {
14321           *obufp++ = open_char;
14322           *obufp = '\0';
14323           oappend (index16[modrm.rm]);
14324           if (intel_syntax
14325               && (disp || modrm.mod != 0 || modrm.rm == 6))
14326             {
14327               if ((bfd_signed_vma) disp >= 0)
14328                 {
14329                   *obufp++ = '+';
14330                   *obufp = '\0';
14331                 }
14332               else if (modrm.mod != 1)
14333                 {
14334                   *obufp++ = '-';
14335                   *obufp = '\0';
14336                   disp = - (bfd_signed_vma) disp;
14337                 }
14338
14339               print_displacement (scratchbuf, disp);
14340               oappend (scratchbuf);
14341             }
14342
14343           *obufp++ = close_char;
14344           *obufp = '\0';
14345         }
14346       else if (intel_syntax)
14347         {
14348           if (!active_seg_prefix)
14349             {
14350               oappend (names_seg[ds_reg - es_reg]);
14351               oappend (":");
14352             }
14353           print_operand_value (scratchbuf, 1, disp & 0xffff);
14354           oappend (scratchbuf);
14355         }
14356     }
14357   if (vex.evex && vex.b
14358       && (bytemode == x_mode
14359           || bytemode == xmmq_mode
14360           || bytemode == evex_half_bcst_xmmq_mode))
14361     {
14362       if (vex.w
14363           || bytemode == xmmq_mode
14364           || bytemode == evex_half_bcst_xmmq_mode)
14365         {
14366           switch (vex.length)
14367             {
14368             case 128:
14369               oappend ("{1to2}");
14370               break;
14371             case 256:
14372               oappend ("{1to4}");
14373               break;
14374             case 512:
14375               oappend ("{1to8}");
14376               break;
14377             default:
14378               abort ();
14379             }
14380         }
14381       else
14382         {
14383           switch (vex.length)
14384             {
14385             case 128:
14386               oappend ("{1to4}");
14387               break;
14388             case 256:
14389               oappend ("{1to8}");
14390               break;
14391             case 512:
14392               oappend ("{1to16}");
14393               break;
14394             default:
14395               abort ();
14396             }
14397         }
14398     }
14399 }
14400
14401 static void
14402 OP_E (int bytemode, int sizeflag)
14403 {
14404   /* Skip mod/rm byte.  */
14405   MODRM_CHECK;
14406   codep++;
14407
14408   if (modrm.mod == 3)
14409     OP_E_register (bytemode, sizeflag);
14410   else
14411     OP_E_memory (bytemode, sizeflag);
14412 }
14413
14414 static void
14415 OP_G (int bytemode, int sizeflag)
14416 {
14417   int add = 0;
14418   const char **names;
14419   USED_REX (REX_R);
14420   if (rex & REX_R)
14421     add += 8;
14422   switch (bytemode)
14423     {
14424     case b_mode:
14425       USED_REX (0);
14426       if (rex)
14427         oappend (names8rex[modrm.reg + add]);
14428       else
14429         oappend (names8[modrm.reg + add]);
14430       break;
14431     case w_mode:
14432       oappend (names16[modrm.reg + add]);
14433       break;
14434     case d_mode:
14435     case db_mode:
14436     case dw_mode:
14437       oappend (names32[modrm.reg + add]);
14438       break;
14439     case q_mode:
14440       oappend (names64[modrm.reg + add]);
14441       break;
14442     case bnd_mode:
14443       if (modrm.reg > 0x3)
14444         {
14445           oappend ("(bad)");
14446           return;
14447         }
14448       oappend (names_bnd[modrm.reg]);
14449       break;
14450     case v_mode:
14451     case dq_mode:
14452     case dqb_mode:
14453     case dqd_mode:
14454     case dqw_mode:
14455       USED_REX (REX_W);
14456       if (rex & REX_W)
14457         oappend (names64[modrm.reg + add]);
14458       else
14459         {
14460           if ((sizeflag & DFLAG) || bytemode != v_mode)
14461             oappend (names32[modrm.reg + add]);
14462           else
14463             oappend (names16[modrm.reg + add]);
14464           used_prefixes |= (prefixes & PREFIX_DATA);
14465         }
14466       break;
14467     case va_mode:
14468       names = (address_mode == mode_64bit
14469                ? names64 : names32);
14470       if (!(prefixes & PREFIX_ADDR))
14471         {
14472           if (address_mode == mode_16bit)
14473             names = names16;
14474         }
14475       else
14476         {
14477           /* Remove "addr16/addr32".  */
14478           all_prefixes[last_addr_prefix] = 0;
14479           names = (address_mode != mode_32bit
14480                        ? names32 : names16);
14481           used_prefixes |= PREFIX_ADDR;
14482         }
14483       oappend (names[modrm.reg + add]);
14484       break;
14485     case m_mode:
14486       if (address_mode == mode_64bit)
14487         oappend (names64[modrm.reg + add]);
14488       else
14489         oappend (names32[modrm.reg + add]);
14490       break;
14491     case mask_bd_mode:
14492     case mask_mode:
14493       if ((modrm.reg + add) > 0x7)
14494         {
14495           oappend ("(bad)");
14496           return;
14497         }
14498       oappend (names_mask[modrm.reg + add]);
14499       break;
14500     default:
14501       oappend (INTERNAL_DISASSEMBLER_ERROR);
14502       break;
14503     }
14504 }
14505
14506 static bfd_vma
14507 get64 (void)
14508 {
14509   bfd_vma x;
14510 #ifdef BFD64
14511   unsigned int a;
14512   unsigned int b;
14513
14514   FETCH_DATA (the_info, codep + 8);
14515   a = *codep++ & 0xff;
14516   a |= (*codep++ & 0xff) << 8;
14517   a |= (*codep++ & 0xff) << 16;
14518   a |= (*codep++ & 0xffu) << 24;
14519   b = *codep++ & 0xff;
14520   b |= (*codep++ & 0xff) << 8;
14521   b |= (*codep++ & 0xff) << 16;
14522   b |= (*codep++ & 0xffu) << 24;
14523   x = a + ((bfd_vma) b << 32);
14524 #else
14525   abort ();
14526   x = 0;
14527 #endif
14528   return x;
14529 }
14530
14531 static bfd_signed_vma
14532 get32 (void)
14533 {
14534   bfd_signed_vma x = 0;
14535
14536   FETCH_DATA (the_info, codep + 4);
14537   x = *codep++ & (bfd_signed_vma) 0xff;
14538   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14539   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14540   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14541   return x;
14542 }
14543
14544 static bfd_signed_vma
14545 get32s (void)
14546 {
14547   bfd_signed_vma x = 0;
14548
14549   FETCH_DATA (the_info, codep + 4);
14550   x = *codep++ & (bfd_signed_vma) 0xff;
14551   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14552   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14553   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14554
14555   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14556
14557   return x;
14558 }
14559
14560 static int
14561 get16 (void)
14562 {
14563   int x = 0;
14564
14565   FETCH_DATA (the_info, codep + 2);
14566   x = *codep++ & 0xff;
14567   x |= (*codep++ & 0xff) << 8;
14568   return x;
14569 }
14570
14571 static void
14572 set_op (bfd_vma op, int riprel)
14573 {
14574   op_index[op_ad] = op_ad;
14575   if (address_mode == mode_64bit)
14576     {
14577       op_address[op_ad] = op;
14578       op_riprel[op_ad] = riprel;
14579     }
14580   else
14581     {
14582       /* Mask to get a 32-bit address.  */
14583       op_address[op_ad] = op & 0xffffffff;
14584       op_riprel[op_ad] = riprel & 0xffffffff;
14585     }
14586 }
14587
14588 static void
14589 OP_REG (int code, int sizeflag)
14590 {
14591   const char *s;
14592   int add;
14593
14594   switch (code)
14595     {
14596     case es_reg: case ss_reg: case cs_reg:
14597     case ds_reg: case fs_reg: case gs_reg:
14598       oappend (names_seg[code - es_reg]);
14599       return;
14600     }
14601
14602   USED_REX (REX_B);
14603   if (rex & REX_B)
14604     add = 8;
14605   else
14606     add = 0;
14607
14608   switch (code)
14609     {
14610     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14611     case sp_reg: case bp_reg: case si_reg: case di_reg:
14612       s = names16[code - ax_reg + add];
14613       break;
14614     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14615     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14616       USED_REX (0);
14617       if (rex)
14618         s = names8rex[code - al_reg + add];
14619       else
14620         s = names8[code - al_reg];
14621       break;
14622     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14623     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14624       if (address_mode == mode_64bit
14625           && ((sizeflag & DFLAG) || (rex & REX_W)))
14626         {
14627           s = names64[code - rAX_reg + add];
14628           break;
14629         }
14630       code += eAX_reg - rAX_reg;
14631       /* Fall through.  */
14632     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14633     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14634       USED_REX (REX_W);
14635       if (rex & REX_W)
14636         s = names64[code - eAX_reg + add];
14637       else
14638         {
14639           if (sizeflag & DFLAG)
14640             s = names32[code - eAX_reg + add];
14641           else
14642             s = names16[code - eAX_reg + add];
14643           used_prefixes |= (prefixes & PREFIX_DATA);
14644         }
14645       break;
14646     default:
14647       s = INTERNAL_DISASSEMBLER_ERROR;
14648       break;
14649     }
14650   oappend (s);
14651 }
14652
14653 static void
14654 OP_IMREG (int code, int sizeflag)
14655 {
14656   const char *s;
14657
14658   switch (code)
14659     {
14660     case indir_dx_reg:
14661       if (intel_syntax)
14662         s = "dx";
14663       else
14664         s = "(%dx)";
14665       break;
14666     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14667     case sp_reg: case bp_reg: case si_reg: case di_reg:
14668       s = names16[code - ax_reg];
14669       break;
14670     case es_reg: case ss_reg: case cs_reg:
14671     case ds_reg: case fs_reg: case gs_reg:
14672       s = names_seg[code - es_reg];
14673       break;
14674     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14675     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14676       USED_REX (0);
14677       if (rex)
14678         s = names8rex[code - al_reg];
14679       else
14680         s = names8[code - al_reg];
14681       break;
14682     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14683     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14684       USED_REX (REX_W);
14685       if (rex & REX_W)
14686         s = names64[code - eAX_reg];
14687       else
14688         {
14689           if (sizeflag & DFLAG)
14690             s = names32[code - eAX_reg];
14691           else
14692             s = names16[code - eAX_reg];
14693           used_prefixes |= (prefixes & PREFIX_DATA);
14694         }
14695       break;
14696     case z_mode_ax_reg:
14697       if ((rex & REX_W) || (sizeflag & DFLAG))
14698         s = *names32;
14699       else
14700         s = *names16;
14701       if (!(rex & REX_W))
14702         used_prefixes |= (prefixes & PREFIX_DATA);
14703       break;
14704     default:
14705       s = INTERNAL_DISASSEMBLER_ERROR;
14706       break;
14707     }
14708   oappend (s);
14709 }
14710
14711 static void
14712 OP_I (int bytemode, int sizeflag)
14713 {
14714   bfd_signed_vma op;
14715   bfd_signed_vma mask = -1;
14716
14717   switch (bytemode)
14718     {
14719     case b_mode:
14720       FETCH_DATA (the_info, codep + 1);
14721       op = *codep++;
14722       mask = 0xff;
14723       break;
14724     case q_mode:
14725       if (address_mode == mode_64bit)
14726         {
14727           op = get32s ();
14728           break;
14729         }
14730       /* Fall through.  */
14731     case v_mode:
14732       USED_REX (REX_W);
14733       if (rex & REX_W)
14734         op = get32s ();
14735       else
14736         {
14737           if (sizeflag & DFLAG)
14738             {
14739               op = get32 ();
14740               mask = 0xffffffff;
14741             }
14742           else
14743             {
14744               op = get16 ();
14745               mask = 0xfffff;
14746             }
14747           used_prefixes |= (prefixes & PREFIX_DATA);
14748         }
14749       break;
14750     case w_mode:
14751       mask = 0xfffff;
14752       op = get16 ();
14753       break;
14754     case const_1_mode:
14755       if (intel_syntax)
14756         oappend ("1");
14757       return;
14758     default:
14759       oappend (INTERNAL_DISASSEMBLER_ERROR);
14760       return;
14761     }
14762
14763   op &= mask;
14764   scratchbuf[0] = '$';
14765   print_operand_value (scratchbuf + 1, 1, op);
14766   oappend_maybe_intel (scratchbuf);
14767   scratchbuf[0] = '\0';
14768 }
14769
14770 static void
14771 OP_I64 (int bytemode, int sizeflag)
14772 {
14773   bfd_signed_vma op;
14774   bfd_signed_vma mask = -1;
14775
14776   if (address_mode != mode_64bit)
14777     {
14778       OP_I (bytemode, sizeflag);
14779       return;
14780     }
14781
14782   switch (bytemode)
14783     {
14784     case b_mode:
14785       FETCH_DATA (the_info, codep + 1);
14786       op = *codep++;
14787       mask = 0xff;
14788       break;
14789     case v_mode:
14790       USED_REX (REX_W);
14791       if (rex & REX_W)
14792         op = get64 ();
14793       else
14794         {
14795           if (sizeflag & DFLAG)
14796             {
14797               op = get32 ();
14798               mask = 0xffffffff;
14799             }
14800           else
14801             {
14802               op = get16 ();
14803               mask = 0xfffff;
14804             }
14805           used_prefixes |= (prefixes & PREFIX_DATA);
14806         }
14807       break;
14808     case w_mode:
14809       mask = 0xfffff;
14810       op = get16 ();
14811       break;
14812     default:
14813       oappend (INTERNAL_DISASSEMBLER_ERROR);
14814       return;
14815     }
14816
14817   op &= mask;
14818   scratchbuf[0] = '$';
14819   print_operand_value (scratchbuf + 1, 1, op);
14820   oappend_maybe_intel (scratchbuf);
14821   scratchbuf[0] = '\0';
14822 }
14823
14824 static void
14825 OP_sI (int bytemode, int sizeflag)
14826 {
14827   bfd_signed_vma op;
14828
14829   switch (bytemode)
14830     {
14831     case b_mode:
14832     case b_T_mode:
14833       FETCH_DATA (the_info, codep + 1);
14834       op = *codep++;
14835       if ((op & 0x80) != 0)
14836         op -= 0x100;
14837       if (bytemode == b_T_mode)
14838         {
14839           if (address_mode != mode_64bit
14840               || !((sizeflag & DFLAG) || (rex & REX_W)))
14841             {
14842               /* The operand-size prefix is overridden by a REX prefix.  */
14843               if ((sizeflag & DFLAG) || (rex & REX_W))
14844                 op &= 0xffffffff;
14845               else
14846                 op &= 0xffff;
14847           }
14848         }
14849       else
14850         {
14851           if (!(rex & REX_W))
14852             {
14853               if (sizeflag & DFLAG)
14854                 op &= 0xffffffff;
14855               else
14856                 op &= 0xffff;
14857             }
14858         }
14859       break;
14860     case v_mode:
14861       /* The operand-size prefix is overridden by a REX prefix.  */
14862       if ((sizeflag & DFLAG) || (rex & REX_W))
14863         op = get32s ();
14864       else
14865         op = get16 ();
14866       break;
14867     default:
14868       oappend (INTERNAL_DISASSEMBLER_ERROR);
14869       return;
14870     }
14871
14872   scratchbuf[0] = '$';
14873   print_operand_value (scratchbuf + 1, 1, op);
14874   oappend_maybe_intel (scratchbuf);
14875 }
14876
14877 static void
14878 OP_J (int bytemode, int sizeflag)
14879 {
14880   bfd_vma disp;
14881   bfd_vma mask = -1;
14882   bfd_vma segment = 0;
14883
14884   switch (bytemode)
14885     {
14886     case b_mode:
14887       FETCH_DATA (the_info, codep + 1);
14888       disp = *codep++;
14889       if ((disp & 0x80) != 0)
14890         disp -= 0x100;
14891       break;
14892     case v_mode:
14893       if (isa64 == amd64)
14894         USED_REX (REX_W);
14895       if ((sizeflag & DFLAG)
14896           || (address_mode == mode_64bit
14897               && (isa64 != amd64 || (rex & REX_W))))
14898         disp = get32s ();
14899       else
14900         {
14901           disp = get16 ();
14902           if ((disp & 0x8000) != 0)
14903             disp -= 0x10000;
14904           /* In 16bit mode, address is wrapped around at 64k within
14905              the same segment.  Otherwise, a data16 prefix on a jump
14906              instruction means that the pc is masked to 16 bits after
14907              the displacement is added!  */
14908           mask = 0xffff;
14909           if ((prefixes & PREFIX_DATA) == 0)
14910             segment = ((start_pc + (codep - start_codep))
14911                        & ~((bfd_vma) 0xffff));
14912         }
14913       if (address_mode != mode_64bit
14914           || (isa64 == amd64 && !(rex & REX_W)))
14915         used_prefixes |= (prefixes & PREFIX_DATA);
14916       break;
14917     default:
14918       oappend (INTERNAL_DISASSEMBLER_ERROR);
14919       return;
14920     }
14921   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14922   set_op (disp, 0);
14923   print_operand_value (scratchbuf, 1, disp);
14924   oappend (scratchbuf);
14925 }
14926
14927 static void
14928 OP_SEG (int bytemode, int sizeflag)
14929 {
14930   if (bytemode == w_mode)
14931     oappend (names_seg[modrm.reg]);
14932   else
14933     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14934 }
14935
14936 static void
14937 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14938 {
14939   int seg, offset;
14940
14941   if (sizeflag & DFLAG)
14942     {
14943       offset = get32 ();
14944       seg = get16 ();
14945     }
14946   else
14947     {
14948       offset = get16 ();
14949       seg = get16 ();
14950     }
14951   used_prefixes |= (prefixes & PREFIX_DATA);
14952   if (intel_syntax)
14953     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14954   else
14955     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14956   oappend (scratchbuf);
14957 }
14958
14959 static void
14960 OP_OFF (int bytemode, int sizeflag)
14961 {
14962   bfd_vma off;
14963
14964   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14965     intel_operand_size (bytemode, sizeflag);
14966   append_seg ();
14967
14968   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14969     off = get32 ();
14970   else
14971     off = get16 ();
14972
14973   if (intel_syntax)
14974     {
14975       if (!active_seg_prefix)
14976         {
14977           oappend (names_seg[ds_reg - es_reg]);
14978           oappend (":");
14979         }
14980     }
14981   print_operand_value (scratchbuf, 1, off);
14982   oappend (scratchbuf);
14983 }
14984
14985 static void
14986 OP_OFF64 (int bytemode, int sizeflag)
14987 {
14988   bfd_vma off;
14989
14990   if (address_mode != mode_64bit
14991       || (prefixes & PREFIX_ADDR))
14992     {
14993       OP_OFF (bytemode, sizeflag);
14994       return;
14995     }
14996
14997   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14998     intel_operand_size (bytemode, sizeflag);
14999   append_seg ();
15000
15001   off = get64 ();
15002
15003   if (intel_syntax)
15004     {
15005       if (!active_seg_prefix)
15006         {
15007           oappend (names_seg[ds_reg - es_reg]);
15008           oappend (":");
15009         }
15010     }
15011   print_operand_value (scratchbuf, 1, off);
15012   oappend (scratchbuf);
15013 }
15014
15015 static void
15016 ptr_reg (int code, int sizeflag)
15017 {
15018   const char *s;
15019
15020   *obufp++ = open_char;
15021   used_prefixes |= (prefixes & PREFIX_ADDR);
15022   if (address_mode == mode_64bit)
15023     {
15024       if (!(sizeflag & AFLAG))
15025         s = names32[code - eAX_reg];
15026       else
15027         s = names64[code - eAX_reg];
15028     }
15029   else if (sizeflag & AFLAG)
15030     s = names32[code - eAX_reg];
15031   else
15032     s = names16[code - eAX_reg];
15033   oappend (s);
15034   *obufp++ = close_char;
15035   *obufp = 0;
15036 }
15037
15038 static void
15039 OP_ESreg (int code, int sizeflag)
15040 {
15041   if (intel_syntax)
15042     {
15043       switch (codep[-1])
15044         {
15045         case 0x6d:      /* insw/insl */
15046           intel_operand_size (z_mode, sizeflag);
15047           break;
15048         case 0xa5:      /* movsw/movsl/movsq */
15049         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15050         case 0xab:      /* stosw/stosl */
15051         case 0xaf:      /* scasw/scasl */
15052           intel_operand_size (v_mode, sizeflag);
15053           break;
15054         default:
15055           intel_operand_size (b_mode, sizeflag);
15056         }
15057     }
15058   oappend_maybe_intel ("%es:");
15059   ptr_reg (code, sizeflag);
15060 }
15061
15062 static void
15063 OP_DSreg (int code, int sizeflag)
15064 {
15065   if (intel_syntax)
15066     {
15067       switch (codep[-1])
15068         {
15069         case 0x6f:      /* outsw/outsl */
15070           intel_operand_size (z_mode, sizeflag);
15071           break;
15072         case 0xa5:      /* movsw/movsl/movsq */
15073         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15074         case 0xad:      /* lodsw/lodsl/lodsq */
15075           intel_operand_size (v_mode, sizeflag);
15076           break;
15077         default:
15078           intel_operand_size (b_mode, sizeflag);
15079         }
15080     }
15081   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15082      default segment register DS is printed.  */
15083   if (!active_seg_prefix)
15084     active_seg_prefix = PREFIX_DS;
15085   append_seg ();
15086   ptr_reg (code, sizeflag);
15087 }
15088
15089 static void
15090 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15091 {
15092   int add;
15093   if (rex & REX_R)
15094     {
15095       USED_REX (REX_R);
15096       add = 8;
15097     }
15098   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15099     {
15100       all_prefixes[last_lock_prefix] = 0;
15101       used_prefixes |= PREFIX_LOCK;
15102       add = 8;
15103     }
15104   else
15105     add = 0;
15106   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15107   oappend_maybe_intel (scratchbuf);
15108 }
15109
15110 static void
15111 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15112 {
15113   int add;
15114   USED_REX (REX_R);
15115   if (rex & REX_R)
15116     add = 8;
15117   else
15118     add = 0;
15119   if (intel_syntax)
15120     sprintf (scratchbuf, "db%d", modrm.reg + add);
15121   else
15122     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15123   oappend (scratchbuf);
15124 }
15125
15126 static void
15127 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15128 {
15129   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15130   oappend_maybe_intel (scratchbuf);
15131 }
15132
15133 static void
15134 OP_R (int bytemode, int sizeflag)
15135 {
15136   /* Skip mod/rm byte.  */
15137   MODRM_CHECK;
15138   codep++;
15139   OP_E_register (bytemode, sizeflag);
15140 }
15141
15142 static void
15143 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15144 {
15145   int reg = modrm.reg;
15146   const char **names;
15147
15148   used_prefixes |= (prefixes & PREFIX_DATA);
15149   if (prefixes & PREFIX_DATA)
15150     {
15151       names = names_xmm;
15152       USED_REX (REX_R);
15153       if (rex & REX_R)
15154         reg += 8;
15155     }
15156   else
15157     names = names_mm;
15158   oappend (names[reg]);
15159 }
15160
15161 static void
15162 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15163 {
15164   int reg = modrm.reg;
15165   const char **names;
15166
15167   USED_REX (REX_R);
15168   if (rex & REX_R)
15169     reg += 8;
15170   if (vex.evex)
15171     {
15172       if (!vex.r)
15173         reg += 16;
15174     }
15175
15176   if (need_vex
15177       && bytemode != xmm_mode
15178       && bytemode != xmmq_mode
15179       && bytemode != evex_half_bcst_xmmq_mode
15180       && bytemode != ymm_mode
15181       && bytemode != scalar_mode)
15182     {
15183       switch (vex.length)
15184         {
15185         case 128:
15186           names = names_xmm;
15187           break;
15188         case 256:
15189           if (vex.w
15190               || (bytemode != vex_vsib_q_w_dq_mode
15191                   && bytemode != vex_vsib_q_w_d_mode))
15192             names = names_ymm;
15193           else
15194             names = names_xmm;
15195           break;
15196         case 512:
15197           names = names_zmm;
15198           break;
15199         default:
15200           abort ();
15201         }
15202     }
15203   else if (bytemode == xmmq_mode
15204            || bytemode == evex_half_bcst_xmmq_mode)
15205     {
15206       switch (vex.length)
15207         {
15208         case 128:
15209         case 256:
15210           names = names_xmm;
15211           break;
15212         case 512:
15213           names = names_ymm;
15214           break;
15215         default:
15216           abort ();
15217         }
15218     }
15219   else if (bytemode == ymm_mode)
15220     names = names_ymm;
15221   else
15222     names = names_xmm;
15223   oappend (names[reg]);
15224 }
15225
15226 static void
15227 OP_EM (int bytemode, int sizeflag)
15228 {
15229   int reg;
15230   const char **names;
15231
15232   if (modrm.mod != 3)
15233     {
15234       if (intel_syntax
15235           && (bytemode == v_mode || bytemode == v_swap_mode))
15236         {
15237           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15238           used_prefixes |= (prefixes & PREFIX_DATA);
15239         }
15240       OP_E (bytemode, sizeflag);
15241       return;
15242     }
15243
15244   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15245     swap_operand ();
15246
15247   /* Skip mod/rm byte.  */
15248   MODRM_CHECK;
15249   codep++;
15250   used_prefixes |= (prefixes & PREFIX_DATA);
15251   reg = modrm.rm;
15252   if (prefixes & PREFIX_DATA)
15253     {
15254       names = names_xmm;
15255       USED_REX (REX_B);
15256       if (rex & REX_B)
15257         reg += 8;
15258     }
15259   else
15260     names = names_mm;
15261   oappend (names[reg]);
15262 }
15263
15264 /* cvt* are the only instructions in sse2 which have
15265    both SSE and MMX operands and also have 0x66 prefix
15266    in their opcode. 0x66 was originally used to differentiate
15267    between SSE and MMX instruction(operands). So we have to handle the
15268    cvt* separately using OP_EMC and OP_MXC */
15269 static void
15270 OP_EMC (int bytemode, int sizeflag)
15271 {
15272   if (modrm.mod != 3)
15273     {
15274       if (intel_syntax && bytemode == v_mode)
15275         {
15276           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15277           used_prefixes |= (prefixes & PREFIX_DATA);
15278         }
15279       OP_E (bytemode, sizeflag);
15280       return;
15281     }
15282
15283   /* Skip mod/rm byte.  */
15284   MODRM_CHECK;
15285   codep++;
15286   used_prefixes |= (prefixes & PREFIX_DATA);
15287   oappend (names_mm[modrm.rm]);
15288 }
15289
15290 static void
15291 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15292 {
15293   used_prefixes |= (prefixes & PREFIX_DATA);
15294   oappend (names_mm[modrm.reg]);
15295 }
15296
15297 static void
15298 OP_EX (int bytemode, int sizeflag)
15299 {
15300   int reg;
15301   const char **names;
15302
15303   /* Skip mod/rm byte.  */
15304   MODRM_CHECK;
15305   codep++;
15306
15307   if (modrm.mod != 3)
15308     {
15309       OP_E_memory (bytemode, sizeflag);
15310       return;
15311     }
15312
15313   reg = modrm.rm;
15314   USED_REX (REX_B);
15315   if (rex & REX_B)
15316     reg += 8;
15317   if (vex.evex)
15318     {
15319       USED_REX (REX_X);
15320       if ((rex & REX_X))
15321         reg += 16;
15322     }
15323
15324   if ((sizeflag & SUFFIX_ALWAYS)
15325       && (bytemode == x_swap_mode
15326           || bytemode == d_swap_mode
15327           || bytemode == d_scalar_swap_mode
15328           || bytemode == q_swap_mode
15329           || bytemode == q_scalar_swap_mode))
15330     swap_operand ();
15331
15332   if (need_vex
15333       && bytemode != xmm_mode
15334       && bytemode != xmmdw_mode
15335       && bytemode != xmmqd_mode
15336       && bytemode != xmm_mb_mode
15337       && bytemode != xmm_mw_mode
15338       && bytemode != xmm_md_mode
15339       && bytemode != xmm_mq_mode
15340       && bytemode != xmm_mdq_mode
15341       && bytemode != xmmq_mode
15342       && bytemode != evex_half_bcst_xmmq_mode
15343       && bytemode != ymm_mode
15344       && bytemode != d_scalar_mode
15345       && bytemode != d_scalar_swap_mode
15346       && bytemode != q_scalar_mode
15347       && bytemode != q_scalar_swap_mode
15348       && bytemode != vex_scalar_w_dq_mode)
15349     {
15350       switch (vex.length)
15351         {
15352         case 128:
15353           names = names_xmm;
15354           break;
15355         case 256:
15356           names = names_ymm;
15357           break;
15358         case 512:
15359           names = names_zmm;
15360           break;
15361         default:
15362           abort ();
15363         }
15364     }
15365   else if (bytemode == xmmq_mode
15366            || bytemode == evex_half_bcst_xmmq_mode)
15367     {
15368       switch (vex.length)
15369         {
15370         case 128:
15371         case 256:
15372           names = names_xmm;
15373           break;
15374         case 512:
15375           names = names_ymm;
15376           break;
15377         default:
15378           abort ();
15379         }
15380     }
15381   else if (bytemode == ymm_mode)
15382     names = names_ymm;
15383   else
15384     names = names_xmm;
15385   oappend (names[reg]);
15386 }
15387
15388 static void
15389 OP_MS (int bytemode, int sizeflag)
15390 {
15391   if (modrm.mod == 3)
15392     OP_EM (bytemode, sizeflag);
15393   else
15394     BadOp ();
15395 }
15396
15397 static void
15398 OP_XS (int bytemode, int sizeflag)
15399 {
15400   if (modrm.mod == 3)
15401     OP_EX (bytemode, sizeflag);
15402   else
15403     BadOp ();
15404 }
15405
15406 static void
15407 OP_M (int bytemode, int sizeflag)
15408 {
15409   if (modrm.mod == 3)
15410     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15411     BadOp ();
15412   else
15413     OP_E (bytemode, sizeflag);
15414 }
15415
15416 static void
15417 OP_0f07 (int bytemode, int sizeflag)
15418 {
15419   if (modrm.mod != 3 || modrm.rm != 0)
15420     BadOp ();
15421   else
15422     OP_E (bytemode, sizeflag);
15423 }
15424
15425 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15426    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15427
15428 static void
15429 NOP_Fixup1 (int bytemode, int sizeflag)
15430 {
15431   if ((prefixes & PREFIX_DATA) != 0
15432       || (rex != 0
15433           && rex != 0x48
15434           && address_mode == mode_64bit))
15435     OP_REG (bytemode, sizeflag);
15436   else
15437     strcpy (obuf, "nop");
15438 }
15439
15440 static void
15441 NOP_Fixup2 (int bytemode, int sizeflag)
15442 {
15443   if ((prefixes & PREFIX_DATA) != 0
15444       || (rex != 0
15445           && rex != 0x48
15446           && address_mode == mode_64bit))
15447     OP_IMREG (bytemode, sizeflag);
15448 }
15449
15450 static const char *const Suffix3DNow[] = {
15451 /* 00 */        NULL,           NULL,           NULL,           NULL,
15452 /* 04 */        NULL,           NULL,           NULL,           NULL,
15453 /* 08 */        NULL,           NULL,           NULL,           NULL,
15454 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15455 /* 10 */        NULL,           NULL,           NULL,           NULL,
15456 /* 14 */        NULL,           NULL,           NULL,           NULL,
15457 /* 18 */        NULL,           NULL,           NULL,           NULL,
15458 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15459 /* 20 */        NULL,           NULL,           NULL,           NULL,
15460 /* 24 */        NULL,           NULL,           NULL,           NULL,
15461 /* 28 */        NULL,           NULL,           NULL,           NULL,
15462 /* 2C */        NULL,           NULL,           NULL,           NULL,
15463 /* 30 */        NULL,           NULL,           NULL,           NULL,
15464 /* 34 */        NULL,           NULL,           NULL,           NULL,
15465 /* 38 */        NULL,           NULL,           NULL,           NULL,
15466 /* 3C */        NULL,           NULL,           NULL,           NULL,
15467 /* 40 */        NULL,           NULL,           NULL,           NULL,
15468 /* 44 */        NULL,           NULL,           NULL,           NULL,
15469 /* 48 */        NULL,           NULL,           NULL,           NULL,
15470 /* 4C */        NULL,           NULL,           NULL,           NULL,
15471 /* 50 */        NULL,           NULL,           NULL,           NULL,
15472 /* 54 */        NULL,           NULL,           NULL,           NULL,
15473 /* 58 */        NULL,           NULL,           NULL,           NULL,
15474 /* 5C */        NULL,           NULL,           NULL,           NULL,
15475 /* 60 */        NULL,           NULL,           NULL,           NULL,
15476 /* 64 */        NULL,           NULL,           NULL,           NULL,
15477 /* 68 */        NULL,           NULL,           NULL,           NULL,
15478 /* 6C */        NULL,           NULL,           NULL,           NULL,
15479 /* 70 */        NULL,           NULL,           NULL,           NULL,
15480 /* 74 */        NULL,           NULL,           NULL,           NULL,
15481 /* 78 */        NULL,           NULL,           NULL,           NULL,
15482 /* 7C */        NULL,           NULL,           NULL,           NULL,
15483 /* 80 */        NULL,           NULL,           NULL,           NULL,
15484 /* 84 */        NULL,           NULL,           NULL,           NULL,
15485 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15486 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15487 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15488 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15489 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15490 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15491 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15492 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15493 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15494 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15495 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15496 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15497 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15498 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15499 /* C0 */        NULL,           NULL,           NULL,           NULL,
15500 /* C4 */        NULL,           NULL,           NULL,           NULL,
15501 /* C8 */        NULL,           NULL,           NULL,           NULL,
15502 /* CC */        NULL,           NULL,           NULL,           NULL,
15503 /* D0 */        NULL,           NULL,           NULL,           NULL,
15504 /* D4 */        NULL,           NULL,           NULL,           NULL,
15505 /* D8 */        NULL,           NULL,           NULL,           NULL,
15506 /* DC */        NULL,           NULL,           NULL,           NULL,
15507 /* E0 */        NULL,           NULL,           NULL,           NULL,
15508 /* E4 */        NULL,           NULL,           NULL,           NULL,
15509 /* E8 */        NULL,           NULL,           NULL,           NULL,
15510 /* EC */        NULL,           NULL,           NULL,           NULL,
15511 /* F0 */        NULL,           NULL,           NULL,           NULL,
15512 /* F4 */        NULL,           NULL,           NULL,           NULL,
15513 /* F8 */        NULL,           NULL,           NULL,           NULL,
15514 /* FC */        NULL,           NULL,           NULL,           NULL,
15515 };
15516
15517 static void
15518 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15519 {
15520   const char *mnemonic;
15521
15522   FETCH_DATA (the_info, codep + 1);
15523   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15524      place where an 8-bit immediate would normally go.  ie. the last
15525      byte of the instruction.  */
15526   obufp = mnemonicendp;
15527   mnemonic = Suffix3DNow[*codep++ & 0xff];
15528   if (mnemonic)
15529     oappend (mnemonic);
15530   else
15531     {
15532       /* Since a variable sized modrm/sib chunk is between the start
15533          of the opcode (0x0f0f) and the opcode suffix, we need to do
15534          all the modrm processing first, and don't know until now that
15535          we have a bad opcode.  This necessitates some cleaning up.  */
15536       op_out[0][0] = '\0';
15537       op_out[1][0] = '\0';
15538       BadOp ();
15539     }
15540   mnemonicendp = obufp;
15541 }
15542
15543 static struct op simd_cmp_op[] =
15544 {
15545   { STRING_COMMA_LEN ("eq") },
15546   { STRING_COMMA_LEN ("lt") },
15547   { STRING_COMMA_LEN ("le") },
15548   { STRING_COMMA_LEN ("unord") },
15549   { STRING_COMMA_LEN ("neq") },
15550   { STRING_COMMA_LEN ("nlt") },
15551   { STRING_COMMA_LEN ("nle") },
15552   { STRING_COMMA_LEN ("ord") }
15553 };
15554
15555 static void
15556 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15557 {
15558   unsigned int cmp_type;
15559
15560   FETCH_DATA (the_info, codep + 1);
15561   cmp_type = *codep++ & 0xff;
15562   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15563     {
15564       char suffix [3];
15565       char *p = mnemonicendp - 2;
15566       suffix[0] = p[0];
15567       suffix[1] = p[1];
15568       suffix[2] = '\0';
15569       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15570       mnemonicendp += simd_cmp_op[cmp_type].len;
15571     }
15572   else
15573     {
15574       /* We have a reserved extension byte.  Output it directly.  */
15575       scratchbuf[0] = '$';
15576       print_operand_value (scratchbuf + 1, 1, cmp_type);
15577       oappend_maybe_intel (scratchbuf);
15578       scratchbuf[0] = '\0';
15579     }
15580 }
15581
15582 static void
15583 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15584           int sizeflag ATTRIBUTE_UNUSED)
15585 {
15586   /* mwaitx %eax,%ecx,%ebx */
15587   if (!intel_syntax)
15588     {
15589       const char **names = (address_mode == mode_64bit
15590                             ? names64 : names32);
15591       strcpy (op_out[0], names[0]);
15592       strcpy (op_out[1], names[1]);
15593       strcpy (op_out[2], names[3]);
15594       two_source_ops = 1;
15595     }
15596   /* Skip mod/rm byte.  */
15597   MODRM_CHECK;
15598   codep++;
15599 }
15600
15601 static void
15602 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15603           int sizeflag ATTRIBUTE_UNUSED)
15604 {
15605   /* mwait %eax,%ecx  */
15606   if (!intel_syntax)
15607     {
15608       const char **names = (address_mode == mode_64bit
15609                             ? names64 : names32);
15610       strcpy (op_out[0], names[0]);
15611       strcpy (op_out[1], names[1]);
15612       two_source_ops = 1;
15613     }
15614   /* Skip mod/rm byte.  */
15615   MODRM_CHECK;
15616   codep++;
15617 }
15618
15619 static void
15620 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15621             int sizeflag ATTRIBUTE_UNUSED)
15622 {
15623   /* monitor %eax,%ecx,%edx"  */
15624   if (!intel_syntax)
15625     {
15626       const char **op1_names;
15627       const char **names = (address_mode == mode_64bit
15628                             ? names64 : names32);
15629
15630       if (!(prefixes & PREFIX_ADDR))
15631         op1_names = (address_mode == mode_16bit
15632                      ? names16 : names);
15633       else
15634         {
15635           /* Remove "addr16/addr32".  */
15636           all_prefixes[last_addr_prefix] = 0;
15637           op1_names = (address_mode != mode_32bit
15638                        ? names32 : names16);
15639           used_prefixes |= PREFIX_ADDR;
15640         }
15641       strcpy (op_out[0], op1_names[0]);
15642       strcpy (op_out[1], names[1]);
15643       strcpy (op_out[2], names[2]);
15644       two_source_ops = 1;
15645     }
15646   /* Skip mod/rm byte.  */
15647   MODRM_CHECK;
15648   codep++;
15649 }
15650
15651 static void
15652 BadOp (void)
15653 {
15654   /* Throw away prefixes and 1st. opcode byte.  */
15655   codep = insn_codep + 1;
15656   oappend ("(bad)");
15657 }
15658
15659 static void
15660 REP_Fixup (int bytemode, int sizeflag)
15661 {
15662   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15663      lods and stos.  */
15664   if (prefixes & PREFIX_REPZ)
15665     all_prefixes[last_repz_prefix] = REP_PREFIX;
15666
15667   switch (bytemode)
15668     {
15669     case al_reg:
15670     case eAX_reg:
15671     case indir_dx_reg:
15672       OP_IMREG (bytemode, sizeflag);
15673       break;
15674     case eDI_reg:
15675       OP_ESreg (bytemode, sizeflag);
15676       break;
15677     case eSI_reg:
15678       OP_DSreg (bytemode, sizeflag);
15679       break;
15680     default:
15681       abort ();
15682       break;
15683     }
15684 }
15685
15686 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15687    "bnd".  */
15688
15689 static void
15690 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15691 {
15692   if (prefixes & PREFIX_REPNZ)
15693     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15694 }
15695
15696 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15697    "notrack".  */
15698
15699 static void
15700 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15701                int sizeflag ATTRIBUTE_UNUSED)
15702 {
15703   if (active_seg_prefix == PREFIX_DS
15704       && (address_mode != mode_64bit || last_data_prefix < 0))
15705     {
15706       /* NOTRACK prefix is only valid on indirect branch instructions.
15707          NB: DATA prefix is unsupported for Intel64.  */
15708       active_seg_prefix = 0;
15709       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15710     }
15711 }
15712
15713 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15714    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15715  */
15716
15717 static void
15718 HLE_Fixup1 (int bytemode, int sizeflag)
15719 {
15720   if (modrm.mod != 3
15721       && (prefixes & PREFIX_LOCK) != 0)
15722     {
15723       if (prefixes & PREFIX_REPZ)
15724         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15725       if (prefixes & PREFIX_REPNZ)
15726         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15727     }
15728
15729   OP_E (bytemode, sizeflag);
15730 }
15731
15732 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15733    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15734  */
15735
15736 static void
15737 HLE_Fixup2 (int bytemode, int sizeflag)
15738 {
15739   if (modrm.mod != 3)
15740     {
15741       if (prefixes & PREFIX_REPZ)
15742         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15743       if (prefixes & PREFIX_REPNZ)
15744         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15745     }
15746
15747   OP_E (bytemode, sizeflag);
15748 }
15749
15750 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15751    "xrelease" for memory operand.  No check for LOCK prefix.   */
15752
15753 static void
15754 HLE_Fixup3 (int bytemode, int sizeflag)
15755 {
15756   if (modrm.mod != 3
15757       && last_repz_prefix > last_repnz_prefix
15758       && (prefixes & PREFIX_REPZ) != 0)
15759     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15760
15761   OP_E (bytemode, sizeflag);
15762 }
15763
15764 static void
15765 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15766 {
15767   USED_REX (REX_W);
15768   if (rex & REX_W)
15769     {
15770       /* Change cmpxchg8b to cmpxchg16b.  */
15771       char *p = mnemonicendp - 2;
15772       mnemonicendp = stpcpy (p, "16b");
15773       bytemode = o_mode;
15774     }
15775   else if ((prefixes & PREFIX_LOCK) != 0)
15776     {
15777       if (prefixes & PREFIX_REPZ)
15778         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15779       if (prefixes & PREFIX_REPNZ)
15780         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15781     }
15782
15783   OP_M (bytemode, sizeflag);
15784 }
15785
15786 static void
15787 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15788 {
15789   const char **names;
15790
15791   if (need_vex)
15792     {
15793       switch (vex.length)
15794         {
15795         case 128:
15796           names = names_xmm;
15797           break;
15798         case 256:
15799           names = names_ymm;
15800           break;
15801         default:
15802           abort ();
15803         }
15804     }
15805   else
15806     names = names_xmm;
15807   oappend (names[reg]);
15808 }
15809
15810 static void
15811 CRC32_Fixup (int bytemode, int sizeflag)
15812 {
15813   /* Add proper suffix to "crc32".  */
15814   char *p = mnemonicendp;
15815
15816   switch (bytemode)
15817     {
15818     case b_mode:
15819       if (intel_syntax)
15820         goto skip;
15821
15822       *p++ = 'b';
15823       break;
15824     case v_mode:
15825       if (intel_syntax)
15826         goto skip;
15827
15828       USED_REX (REX_W);
15829       if (rex & REX_W)
15830         *p++ = 'q';
15831       else
15832         {
15833           if (sizeflag & DFLAG)
15834             *p++ = 'l';
15835           else
15836             *p++ = 'w';
15837           used_prefixes |= (prefixes & PREFIX_DATA);
15838         }
15839       break;
15840     default:
15841       oappend (INTERNAL_DISASSEMBLER_ERROR);
15842       break;
15843     }
15844   mnemonicendp = p;
15845   *p = '\0';
15846
15847 skip:
15848   if (modrm.mod == 3)
15849     {
15850       int add;
15851
15852       /* Skip mod/rm byte.  */
15853       MODRM_CHECK;
15854       codep++;
15855
15856       USED_REX (REX_B);
15857       add = (rex & REX_B) ? 8 : 0;
15858       if (bytemode == b_mode)
15859         {
15860           USED_REX (0);
15861           if (rex)
15862             oappend (names8rex[modrm.rm + add]);
15863           else
15864             oappend (names8[modrm.rm + add]);
15865         }
15866       else
15867         {
15868           USED_REX (REX_W);
15869           if (rex & REX_W)
15870             oappend (names64[modrm.rm + add]);
15871           else if ((prefixes & PREFIX_DATA))
15872             oappend (names16[modrm.rm + add]);
15873           else
15874             oappend (names32[modrm.rm + add]);
15875         }
15876     }
15877   else
15878     OP_E (bytemode, sizeflag);
15879 }
15880
15881 static void
15882 FXSAVE_Fixup (int bytemode, int sizeflag)
15883 {
15884   /* Add proper suffix to "fxsave" and "fxrstor".  */
15885   USED_REX (REX_W);
15886   if (rex & REX_W)
15887     {
15888       char *p = mnemonicendp;
15889       *p++ = '6';
15890       *p++ = '4';
15891       *p = '\0';
15892       mnemonicendp = p;
15893     }
15894   OP_M (bytemode, sizeflag);
15895 }
15896
15897 static void
15898 PCMPESTR_Fixup (int bytemode, int sizeflag)
15899 {
15900   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15901   if (!intel_syntax)
15902     {
15903       char *p = mnemonicendp;
15904
15905       USED_REX (REX_W);
15906       if (rex & REX_W)
15907         *p++ = 'q';
15908       else if (sizeflag & SUFFIX_ALWAYS)
15909         *p++ = 'l';
15910
15911       *p = '\0';
15912       mnemonicendp = p;
15913     }
15914
15915   OP_EX (bytemode, sizeflag);
15916 }
15917
15918 /* Display the destination register operand for instructions with
15919    VEX. */
15920
15921 static void
15922 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15923 {
15924   int reg;
15925   const char **names;
15926
15927   if (!need_vex)
15928     abort ();
15929
15930   if (!need_vex_reg)
15931     return;
15932
15933   reg = vex.register_specifier;
15934   if (address_mode != mode_64bit)
15935     reg &= 7;
15936   else if (vex.evex && !vex.v)
15937     reg += 16;
15938
15939   if (bytemode == vex_scalar_mode)
15940     {
15941       oappend (names_xmm[reg]);
15942       return;
15943     }
15944
15945   switch (vex.length)
15946     {
15947     case 128:
15948       switch (bytemode)
15949         {
15950         case vex_mode:
15951         case vex128_mode:
15952         case vex_vsib_q_w_dq_mode:
15953         case vex_vsib_q_w_d_mode:
15954           names = names_xmm;
15955           break;
15956         case dq_mode:
15957           if (rex & REX_W)
15958             names = names64;
15959           else
15960             names = names32;
15961           break;
15962         case mask_bd_mode:
15963         case mask_mode:
15964           if (reg > 0x7)
15965             {
15966               oappend ("(bad)");
15967               return;
15968             }
15969           names = names_mask;
15970           break;
15971         default:
15972           abort ();
15973           return;
15974         }
15975       break;
15976     case 256:
15977       switch (bytemode)
15978         {
15979         case vex_mode:
15980         case vex256_mode:
15981           names = names_ymm;
15982           break;
15983         case vex_vsib_q_w_dq_mode:
15984         case vex_vsib_q_w_d_mode:
15985           names = vex.w ? names_ymm : names_xmm;
15986           break;
15987         case mask_bd_mode:
15988         case mask_mode:
15989           if (reg > 0x7)
15990             {
15991               oappend ("(bad)");
15992               return;
15993             }
15994           names = names_mask;
15995           break;
15996         default:
15997           /* See PR binutils/20893 for a reproducer.  */
15998           oappend ("(bad)");
15999           return;
16000         }
16001       break;
16002     case 512:
16003       names = names_zmm;
16004       break;
16005     default:
16006       abort ();
16007       break;
16008     }
16009   oappend (names[reg]);
16010 }
16011
16012 /* Get the VEX immediate byte without moving codep.  */
16013
16014 static unsigned char
16015 get_vex_imm8 (int sizeflag, int opnum)
16016 {
16017   int bytes_before_imm = 0;
16018
16019   if (modrm.mod != 3)
16020     {
16021       /* There are SIB/displacement bytes.  */
16022       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16023         {
16024           /* 32/64 bit address mode */
16025           int base = modrm.rm;
16026
16027           /* Check SIB byte.  */
16028           if (base == 4)
16029             {
16030               FETCH_DATA (the_info, codep + 1);
16031               base = *codep & 7;
16032               /* When decoding the third source, don't increase
16033                  bytes_before_imm as this has already been incremented
16034                  by one in OP_E_memory while decoding the second
16035                  source operand.  */
16036               if (opnum == 0)
16037                 bytes_before_imm++;
16038             }
16039
16040           /* Don't increase bytes_before_imm when decoding the third source,
16041              it has already been incremented by OP_E_memory while decoding
16042              the second source operand.  */
16043           if (opnum == 0)
16044             {
16045               switch (modrm.mod)
16046                 {
16047                   case 0:
16048                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16049                        SIB == 5, there is a 4 byte displacement.  */
16050                     if (base != 5)
16051                       /* No displacement. */
16052                       break;
16053                     /* Fall through.  */
16054                   case 2:
16055                     /* 4 byte displacement.  */
16056                     bytes_before_imm += 4;
16057                     break;
16058                   case 1:
16059                     /* 1 byte displacement.  */
16060                     bytes_before_imm++;
16061                     break;
16062                 }
16063             }
16064         }
16065       else
16066         {
16067           /* 16 bit address mode */
16068           /* Don't increase bytes_before_imm when decoding the third source,
16069              it has already been incremented by OP_E_memory while decoding
16070              the second source operand.  */
16071           if (opnum == 0)
16072             {
16073               switch (modrm.mod)
16074                 {
16075                 case 0:
16076                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16077                   if (modrm.rm != 6)
16078                     /* No displacement. */
16079                     break;
16080                   /* Fall through.  */
16081                 case 2:
16082                   /* 2 byte displacement.  */
16083                   bytes_before_imm += 2;
16084                   break;
16085                 case 1:
16086                   /* 1 byte displacement: when decoding the third source,
16087                      don't increase bytes_before_imm as this has already
16088                      been incremented by one in OP_E_memory while decoding
16089                      the second source operand.  */
16090                   if (opnum == 0)
16091                     bytes_before_imm++;
16092
16093                   break;
16094                 }
16095             }
16096         }
16097     }
16098
16099   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16100   return codep [bytes_before_imm];
16101 }
16102
16103 static void
16104 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16105 {
16106   const char **names;
16107
16108   if (reg == -1 && modrm.mod != 3)
16109     {
16110       OP_E_memory (bytemode, sizeflag);
16111       return;
16112     }
16113   else
16114     {
16115       if (reg == -1)
16116         {
16117           reg = modrm.rm;
16118           USED_REX (REX_B);
16119           if (rex & REX_B)
16120             reg += 8;
16121         }
16122       if (address_mode != mode_64bit)
16123         reg &= 7;
16124     }
16125
16126   switch (vex.length)
16127     {
16128     case 128:
16129       names = names_xmm;
16130       break;
16131     case 256:
16132       names = names_ymm;
16133       break;
16134     default:
16135       abort ();
16136     }
16137   oappend (names[reg]);
16138 }
16139
16140 static void
16141 OP_EX_VexImmW (int bytemode, int sizeflag)
16142 {
16143   int reg = -1;
16144   static unsigned char vex_imm8;
16145
16146   if (vex_w_done == 0)
16147     {
16148       vex_w_done = 1;
16149
16150       /* Skip mod/rm byte.  */
16151       MODRM_CHECK;
16152       codep++;
16153
16154       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16155
16156       if (vex.w)
16157           reg = vex_imm8 >> 4;
16158
16159       OP_EX_VexReg (bytemode, sizeflag, reg);
16160     }
16161   else if (vex_w_done == 1)
16162     {
16163       vex_w_done = 2;
16164
16165       if (!vex.w)
16166           reg = vex_imm8 >> 4;
16167
16168       OP_EX_VexReg (bytemode, sizeflag, reg);
16169     }
16170   else
16171     {
16172       /* Output the imm8 directly.  */
16173       scratchbuf[0] = '$';
16174       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16175       oappend_maybe_intel (scratchbuf);
16176       scratchbuf[0] = '\0';
16177       codep++;
16178     }
16179 }
16180
16181 static void
16182 OP_Vex_2src (int bytemode, int sizeflag)
16183 {
16184   if (modrm.mod == 3)
16185     {
16186       int reg = modrm.rm;
16187       USED_REX (REX_B);
16188       if (rex & REX_B)
16189         reg += 8;
16190       oappend (names_xmm[reg]);
16191     }
16192   else
16193     {
16194       if (intel_syntax
16195           && (bytemode == v_mode || bytemode == v_swap_mode))
16196         {
16197           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16198           used_prefixes |= (prefixes & PREFIX_DATA);
16199         }
16200       OP_E (bytemode, sizeflag);
16201     }
16202 }
16203
16204 static void
16205 OP_Vex_2src_1 (int bytemode, int sizeflag)
16206 {
16207   if (modrm.mod == 3)
16208     {
16209       /* Skip mod/rm byte.   */
16210       MODRM_CHECK;
16211       codep++;
16212     }
16213
16214   if (vex.w)
16215     {
16216       unsigned int reg = vex.register_specifier;
16217
16218       if (address_mode != mode_64bit)
16219         reg &= 7;
16220       oappend (names_xmm[reg]);
16221     }
16222   else
16223     OP_Vex_2src (bytemode, sizeflag);
16224 }
16225
16226 static void
16227 OP_Vex_2src_2 (int bytemode, int sizeflag)
16228 {
16229   if (vex.w)
16230     OP_Vex_2src (bytemode, sizeflag);
16231   else
16232     {
16233       unsigned int reg = vex.register_specifier;
16234
16235       if (address_mode != mode_64bit)
16236         reg &= 7;
16237       oappend (names_xmm[reg]);
16238     }
16239 }
16240
16241 static void
16242 OP_EX_VexW (int bytemode, int sizeflag)
16243 {
16244   int reg = -1;
16245
16246   if (!vex_w_done)
16247     {
16248       /* Skip mod/rm byte.  */
16249       MODRM_CHECK;
16250       codep++;
16251
16252       if (vex.w)
16253         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16254     }
16255   else
16256     {
16257       if (!vex.w)
16258         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16259     }
16260
16261   OP_EX_VexReg (bytemode, sizeflag, reg);
16262
16263   if (vex_w_done)
16264     codep++;
16265   vex_w_done = 1;
16266 }
16267
16268 static void
16269 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16270 {
16271   int reg;
16272   const char **names;
16273
16274   FETCH_DATA (the_info, codep + 1);
16275   reg = *codep++;
16276
16277   if (bytemode != x_mode)
16278     abort ();
16279
16280   reg >>= 4;
16281   if (address_mode != mode_64bit)
16282     reg &= 7;
16283
16284   switch (vex.length)
16285     {
16286     case 128:
16287       names = names_xmm;
16288       break;
16289     case 256:
16290       names = names_ymm;
16291       break;
16292     default:
16293       abort ();
16294     }
16295   oappend (names[reg]);
16296 }
16297
16298 static void
16299 OP_XMM_VexW (int bytemode, int sizeflag)
16300 {
16301   /* Turn off the REX.W bit since it is used for swapping operands
16302      now.  */
16303   rex &= ~REX_W;
16304   OP_XMM (bytemode, sizeflag);
16305 }
16306
16307 static void
16308 OP_EX_Vex (int bytemode, int sizeflag)
16309 {
16310   if (modrm.mod != 3)
16311     {
16312       if (vex.register_specifier != 0)
16313         BadOp ();
16314       need_vex_reg = 0;
16315     }
16316   OP_EX (bytemode, sizeflag);
16317 }
16318
16319 static void
16320 OP_XMM_Vex (int bytemode, int sizeflag)
16321 {
16322   if (modrm.mod != 3)
16323     {
16324       if (vex.register_specifier != 0)
16325         BadOp ();
16326       need_vex_reg = 0;
16327     }
16328   OP_XMM (bytemode, sizeflag);
16329 }
16330
16331 static struct op vex_cmp_op[] =
16332 {
16333   { STRING_COMMA_LEN ("eq") },
16334   { STRING_COMMA_LEN ("lt") },
16335   { STRING_COMMA_LEN ("le") },
16336   { STRING_COMMA_LEN ("unord") },
16337   { STRING_COMMA_LEN ("neq") },
16338   { STRING_COMMA_LEN ("nlt") },
16339   { STRING_COMMA_LEN ("nle") },
16340   { STRING_COMMA_LEN ("ord") },
16341   { STRING_COMMA_LEN ("eq_uq") },
16342   { STRING_COMMA_LEN ("nge") },
16343   { STRING_COMMA_LEN ("ngt") },
16344   { STRING_COMMA_LEN ("false") },
16345   { STRING_COMMA_LEN ("neq_oq") },
16346   { STRING_COMMA_LEN ("ge") },
16347   { STRING_COMMA_LEN ("gt") },
16348   { STRING_COMMA_LEN ("true") },
16349   { STRING_COMMA_LEN ("eq_os") },
16350   { STRING_COMMA_LEN ("lt_oq") },
16351   { STRING_COMMA_LEN ("le_oq") },
16352   { STRING_COMMA_LEN ("unord_s") },
16353   { STRING_COMMA_LEN ("neq_us") },
16354   { STRING_COMMA_LEN ("nlt_uq") },
16355   { STRING_COMMA_LEN ("nle_uq") },
16356   { STRING_COMMA_LEN ("ord_s") },
16357   { STRING_COMMA_LEN ("eq_us") },
16358   { STRING_COMMA_LEN ("nge_uq") },
16359   { STRING_COMMA_LEN ("ngt_uq") },
16360   { STRING_COMMA_LEN ("false_os") },
16361   { STRING_COMMA_LEN ("neq_os") },
16362   { STRING_COMMA_LEN ("ge_oq") },
16363   { STRING_COMMA_LEN ("gt_oq") },
16364   { STRING_COMMA_LEN ("true_us") },
16365 };
16366
16367 static void
16368 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16369 {
16370   unsigned int cmp_type;
16371
16372   FETCH_DATA (the_info, codep + 1);
16373   cmp_type = *codep++ & 0xff;
16374   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16375     {
16376       char suffix [3];
16377       char *p = mnemonicendp - 2;
16378       suffix[0] = p[0];
16379       suffix[1] = p[1];
16380       suffix[2] = '\0';
16381       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16382       mnemonicendp += vex_cmp_op[cmp_type].len;
16383     }
16384   else
16385     {
16386       /* We have a reserved extension byte.  Output it directly.  */
16387       scratchbuf[0] = '$';
16388       print_operand_value (scratchbuf + 1, 1, cmp_type);
16389       oappend_maybe_intel (scratchbuf);
16390       scratchbuf[0] = '\0';
16391     }
16392 }
16393
16394 static void
16395 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16396              int sizeflag ATTRIBUTE_UNUSED)
16397 {
16398   unsigned int cmp_type;
16399
16400   if (!vex.evex)
16401     abort ();
16402
16403   FETCH_DATA (the_info, codep + 1);
16404   cmp_type = *codep++ & 0xff;
16405   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16406      If it's the case, print suffix, otherwise - print the immediate.  */
16407   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16408       && cmp_type != 3
16409       && cmp_type != 7)
16410     {
16411       char suffix [3];
16412       char *p = mnemonicendp - 2;
16413
16414       /* vpcmp* can have both one- and two-lettered suffix.  */
16415       if (p[0] == 'p')
16416         {
16417           p++;
16418           suffix[0] = p[0];
16419           suffix[1] = '\0';
16420         }
16421       else
16422         {
16423           suffix[0] = p[0];
16424           suffix[1] = p[1];
16425           suffix[2] = '\0';
16426         }
16427
16428       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16429       mnemonicendp += simd_cmp_op[cmp_type].len;
16430     }
16431   else
16432     {
16433       /* We have a reserved extension byte.  Output it directly.  */
16434       scratchbuf[0] = '$';
16435       print_operand_value (scratchbuf + 1, 1, cmp_type);
16436       oappend_maybe_intel (scratchbuf);
16437       scratchbuf[0] = '\0';
16438     }
16439 }
16440
16441 static const struct op xop_cmp_op[] =
16442 {
16443   { STRING_COMMA_LEN ("lt") },
16444   { STRING_COMMA_LEN ("le") },
16445   { STRING_COMMA_LEN ("gt") },
16446   { STRING_COMMA_LEN ("ge") },
16447   { STRING_COMMA_LEN ("eq") },
16448   { STRING_COMMA_LEN ("neq") },
16449   { STRING_COMMA_LEN ("false") },
16450   { STRING_COMMA_LEN ("true") }
16451 };
16452
16453 static void
16454 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16455              int sizeflag ATTRIBUTE_UNUSED)
16456 {
16457   unsigned int cmp_type;
16458
16459   FETCH_DATA (the_info, codep + 1);
16460   cmp_type = *codep++ & 0xff;
16461   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16462     {
16463       char suffix[3];
16464       char *p = mnemonicendp - 2;
16465
16466       /* vpcom* can have both one- and two-lettered suffix.  */
16467       if (p[0] == 'm')
16468         {
16469           p++;
16470           suffix[0] = p[0];
16471           suffix[1] = '\0';
16472         }
16473       else
16474         {
16475           suffix[0] = p[0];
16476           suffix[1] = p[1];
16477           suffix[2] = '\0';
16478         }
16479
16480       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16481       mnemonicendp += xop_cmp_op[cmp_type].len;
16482     }
16483   else
16484     {
16485       /* We have a reserved extension byte.  Output it directly.  */
16486       scratchbuf[0] = '$';
16487       print_operand_value (scratchbuf + 1, 1, cmp_type);
16488       oappend_maybe_intel (scratchbuf);
16489       scratchbuf[0] = '\0';
16490     }
16491 }
16492
16493 static const struct op pclmul_op[] =
16494 {
16495   { STRING_COMMA_LEN ("lql") },
16496   { STRING_COMMA_LEN ("hql") },
16497   { STRING_COMMA_LEN ("lqh") },
16498   { STRING_COMMA_LEN ("hqh") }
16499 };
16500
16501 static void
16502 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16503               int sizeflag ATTRIBUTE_UNUSED)
16504 {
16505   unsigned int pclmul_type;
16506
16507   FETCH_DATA (the_info, codep + 1);
16508   pclmul_type = *codep++ & 0xff;
16509   switch (pclmul_type)
16510     {
16511     case 0x10:
16512       pclmul_type = 2;
16513       break;
16514     case 0x11:
16515       pclmul_type = 3;
16516       break;
16517     default:
16518       break;
16519     }
16520   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16521     {
16522       char suffix [4];
16523       char *p = mnemonicendp - 3;
16524       suffix[0] = p[0];
16525       suffix[1] = p[1];
16526       suffix[2] = p[2];
16527       suffix[3] = '\0';
16528       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16529       mnemonicendp += pclmul_op[pclmul_type].len;
16530     }
16531   else
16532     {
16533       /* We have a reserved extension byte.  Output it directly.  */
16534       scratchbuf[0] = '$';
16535       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16536       oappend_maybe_intel (scratchbuf);
16537       scratchbuf[0] = '\0';
16538     }
16539 }
16540
16541 static void
16542 MOVBE_Fixup (int bytemode, int sizeflag)
16543 {
16544   /* Add proper suffix to "movbe".  */
16545   char *p = mnemonicendp;
16546
16547   switch (bytemode)
16548     {
16549     case v_mode:
16550       if (intel_syntax)
16551         goto skip;
16552
16553       USED_REX (REX_W);
16554       if (sizeflag & SUFFIX_ALWAYS)
16555         {
16556           if (rex & REX_W)
16557             *p++ = 'q';
16558           else
16559             {
16560               if (sizeflag & DFLAG)
16561                 *p++ = 'l';
16562               else
16563                 *p++ = 'w';
16564               used_prefixes |= (prefixes & PREFIX_DATA);
16565             }
16566         }
16567       break;
16568     default:
16569       oappend (INTERNAL_DISASSEMBLER_ERROR);
16570       break;
16571     }
16572   mnemonicendp = p;
16573   *p = '\0';
16574
16575 skip:
16576   OP_M (bytemode, sizeflag);
16577 }
16578
16579 static void
16580 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16581 {
16582   int reg;
16583   const char **names;
16584
16585   /* Skip mod/rm byte.  */
16586   MODRM_CHECK;
16587   codep++;
16588
16589   if (rex & REX_W)
16590     names = names64;
16591   else
16592     names = names32;
16593
16594   reg = modrm.rm;
16595   USED_REX (REX_B);
16596   if (rex & REX_B)
16597     reg += 8;
16598
16599   oappend (names[reg]);
16600 }
16601
16602 static void
16603 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16604 {
16605   const char **names;
16606   unsigned int reg = vex.register_specifier;
16607
16608   if (rex & REX_W)
16609     names = names64;
16610   else
16611     names = names32;
16612
16613   if (address_mode != mode_64bit)
16614     reg &= 7;
16615   oappend (names[reg]);
16616 }
16617
16618 static void
16619 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16620 {
16621   if (!vex.evex
16622       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16623     abort ();
16624
16625   USED_REX (REX_R);
16626   if ((rex & REX_R) != 0 || !vex.r)
16627     {
16628       BadOp ();
16629       return;
16630     }
16631
16632   oappend (names_mask [modrm.reg]);
16633 }
16634
16635 static void
16636 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16637 {
16638   if (!vex.evex
16639       || (bytemode != evex_rounding_mode
16640           && bytemode != evex_rounding_64_mode
16641           && bytemode != evex_sae_mode))
16642     abort ();
16643   if (modrm.mod == 3 && vex.b)
16644     switch (bytemode)
16645       {
16646       case evex_rounding_64_mode:
16647         if (address_mode != mode_64bit)
16648           {
16649             oappend ("(bad)");
16650             break;
16651           }
16652         /* Fall through.  */
16653       case evex_rounding_mode:
16654         oappend (names_rounding[vex.ll]);
16655         break;
16656       case evex_sae_mode:
16657         oappend ("{sae}");
16658         break;
16659       default:
16660         break;
16661       }
16662 }