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x86: adjust st(<N>) parsing
2021-03-30  Jan Beulichx86: adjust st(<N>) parsing
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2021-03-30  Jan Beulichx86: integrate rc_op into struct _i386_insn
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2021-03-30  Jan Beulichx86: integrate broadcast_op into struct _i386_insn
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2021-03-30  Jan Beulichx86: integrate mask_op into struct _i386_insn
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2021-03-30  Jan Beulichx86: make swap_2_operands() have unsigned parameters
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2021-03-29  Jan Beulichx86: move some opcode table entries
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2021-03-29  Jan Beulichx86: VPSADBW's source operands are also commutative
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2021-03-29  Jan Beulichx86: fold SSE2AVX and their base MMX/SSE templates
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2021-03-29  Jan Beulichx86: undo Prefix_0X<nn> use in opcode table
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2021-03-29  Jan Beulichx86: shrink some struct insn_template fields
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2021-03-29  Jan Beulichx86: derive opcode encoding space attribute from base...
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2021-03-26  Jan Beulichx86-64: don't accept supposedly disabled MOVQ forms
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2021-03-25  Jan Beulichx86: fix CMPXCHG8B special case when disallowing q...
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2021-03-25  Jan Beulichx86: flag bad S/G insn operand combinations
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2021-03-25  Jan Beulichx86: flag as bad AVX512 insns with EVEX.z set but EVEX...
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2021-03-25  Jan Beulichx86: fix AMD Zen3 insns
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2021-03-25  Jan Beulichx86-64: limit breakage from gcc movdir64b et al workaround
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2021-03-24  Jan Beulichx86: derive opcode length from opcode value
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2021-03-24  Jan Beulichx86: derive mandatory prefix attribute from base opcode
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2021-03-24  Jan Beulichx86: don't use opcode_length to identify pseudo prefixes
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2021-03-23  Jan Beulichx86: re-number PREFIX_0X<nn>
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2021-03-23  Jan Beulichx86: re-order two fields of struct insn_template
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2021-03-23  Jan Beulichx86: split opcode prefix and opcode space representation
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2021-03-23  Jan Beulichx86: don't open-code PREFIX_NONE
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2021-03-23  Jan Beulichx86: unbreak certain MPX insn operand forms
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2021-03-23  Jan Beulichbfd: avoid "shadowing" of glibc function name
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2021-03-22  Jan Beulichbfd: add translation wrappers to PE image section RVA...
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2021-03-15  Jan Beulichld: don't chance overrunning PE .reloc section content
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2021-03-11  Jan Beulichx86: re-order logic in OP_XMM()
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2021-03-11  Jan Beulichx86: drop a few redundant EVEX-related checks
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2021-03-11  Jan Beulichx86: remove stray uses of xmmq_mode
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2021-03-10  Jan Beulichx86/Intel: correct AVX512 S/G disassembly
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2021-03-10  Jan Beulichx86: re-arrange enumerator and table entry order
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2021-03-10  Jan Beulichx86: reuse further VEX entries for EVEX
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2021-03-10  Jan Beulichx86: reuse VEX entries for EVEX vperm{q,pd}
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2021-03-10  Jan Beulichx86: re-arrange order of decode for various EVEX opcodes
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2021-03-10  Jan Beulichx86: re-arrange order of decode for various mask reg...
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2021-03-10  Jan Beulichx86: re-arrange order of decode for various VEX opcodes
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2021-03-10  Jan Beulichx86: re-arrange order of decode for various legacy...
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2021-03-10  Jan Beulichx86: correct decoding of nop/reserved space (0f18 ...
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2021-03-10  Jan Beulichbfd: strip symbols not representable in COFF/PE symbol...
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2021-03-09  Jan Beulichld: adjust PE base relocations testcase
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2021-03-09  Jan Beulichx86: fold some prefix related attributes into a single one
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2021-03-09  Jan Beulichx86-64: make SYSEXIT handling similar to SYSRET's
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2021-03-09  Jan Beulichbfd: don't silently wrap or truncate PE image section...
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2021-03-04  Jan Beulichld: adjust ld-scripts/map-address.*
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2021-03-04  Jan Beulichbfd: prune COFF/PE section flags setting
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2021-03-04  Jan Beulichld: don't generate base relocations in PE output for...
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2021-03-03  Jan Beulichx86: infer operand count of templates
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2021-02-25  Jan Beulichld: correct description of behavior for symbols redefined...
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2021-02-16  Jan Beulichx86: CVTPI2PD has special behavior
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2021-02-16  Jan Beulichx86: honor template rather than actual operands when...
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2021-02-16  Jan Beulichx86: record register use for SIMD insns without respective...
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2021-02-16  Jan Beulichx86: make common property tests common
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2021-02-16  Jan Beulichx86: have preprocessor expand macros
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2021-02-16  Jan Beulichx86: make 16-bit ENQCMD test actually test ENQCMD
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2021-02-16  Jan BeulichDwarf: fix build with old gcc
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2021-02-15  Jan Beulichbfd: use $(LN_S) in favor of "cp -p" when populating...
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2020-08-21  Jan Beulichfix objcopy of PE images with .buildid section
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2020-07-21  Jan BeulichRevert "x86: Don't display eiz with no scale"
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2020-07-21  Jan BeulichRevert "x86: Replace evex-no-scale.s with evex-no-scale...
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2020-07-20  Jan Beulichx86: handle SVR4 escaped binary operators
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2020-07-20  Jan Beulichgas: generalize comment character escaping recognition
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2020-07-20  Jan Beulichx86: honor absolute section when emitting code
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2020-07-20  Jan Beulichix86: enable more ELF tests for VxWorks
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2020-07-15  Jan Beulichx86: move putop() case labels to restore alphabetic...
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2020-07-15  Jan Beulichx86: make PUSH/POP disassembly uniform
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2020-07-15  Jan Beulichx86-64: adjust stack insn test case
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2020-07-15  Jan Beulichx86: avoid attaching suffixes to unambiguous insns
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2020-07-14  Jan Beulichx86/Intel: debug registers are named DRn
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2020-07-14  Jan Beulichx86: drop Rm and the 'L' macro
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2020-07-14  Jan Beulichx86: drop Rdq, Rd, and MaskR
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2020-07-14  Jan Beulichx86: simplify decode of opcodes valid only without...
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2020-07-14  Jan Beulichx86: also use %BW / %DQ for kshift*
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2020-07-14  Jan Beulichx86: simplify decode of opcodes valid with (embedded...
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2020-07-14  Jan Beulichx86: drop further EVEX table entries that can be served...
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2020-07-14  Jan Beulichx86: drop need_vex_reg
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2020-07-14  Jan Beulichx86: drop Vex128 and Vex256
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2020-07-14  Jan Beulichx86: replace %LW by %DQ
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2020-07-14  Jan Beulichx86: merge/move logic determining the EVEX disp8 shift
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2020-07-14  Jan Beulichx86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}
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2020-07-14  Jan Beulichx86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel...
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2020-07-14  Jan Beulichx86: fold VCMP_Fixup() into CMP_Fixup()
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2020-07-14  Jan Beulichx86: don't disassemble MOVBE with two suffixes
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2020-07-14  Jan Beulichx86: avoid attaching suffix to register-only CRC32
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2020-07-14  Jan Beulichx86-64: don't hide an empty but meaningless REX prefix
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2020-07-14  Jan Beulichx86: drop dead code from OP_IMREG()
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2020-07-14  Jan Beulichx86-64: fold ILP32 test expectations
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2020-07-08  Jan Beulichx86: various XOP insns lack L and/or W bit decoding
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2020-07-08  Jan Beulichx86: FMA4 scalar insns ignore VEX.L
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2020-07-08  Jan Beulichx86: re-work operand swapping for XOP shift/rotate...
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2020-07-08  Jan Beulichx86: re-work operand handling for 5-operand XOP insns
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2020-07-08  Jan Beulichx86: re-work operand swapping for FMA4 and 4-operand...
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2020-07-07  Jan Beulichx86: introduce %BW to avoid going through vex_w_table[]
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2020-07-06  Jan Beulichx86: adjust/correct VFRCZ{P,S}{S,D} decoding
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2020-07-06  Jan Beulichx86: use %LW / %XW instead of going through vex_w_table[]
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2020-07-06  Jan Beulichx86: most VBROADCAST{F,I}{32,64}x* only accept memory...
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2020-07-06  Jan Beulichx86: adjust/correct V*{F,I}{32x8,64x4}
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2020-07-06  Jan Beulichx86: drop EVEX table entries that can be made served...
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2020-07-06  Jan Beulichx86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'L
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GDB Binutils - Deliverables
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