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* elflink.c (_bfd_elf_merge_symbol): Skip weak redefinition
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
3b22753a 308static void handle_large_common (int small ATTRIBUTE_UNUSED);
eecb386c 309
12b55ccc
L		 310/* Non-zero to optimize code alignment. */
311int optimize_align_code = 1;
312
47926f60
KH		 313/* Non-zero to quieten some warnings. */
314static int quiet_warnings = 0;
a38cf1db 315
47926f60
KH		 316/* CPU name. */
317static const char *cpu_arch_name = NULL;
5c6af06e 318static const char *cpu_sub_arch_name = NULL;
a38cf1db 319
47926f60 320/* CPU feature flags. */
29b0f896 321static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 322
fddf5b5b
AM		 323/* If set, conditional jumps are not automatically promoted to handle
324 larger than a byte offset. */
325static unsigned int no_cond_jump_promotion = 0;
326
29b0f896 327/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 328static symbolS *GOT_symbol;
29b0f896 329
a4447b93
RH		 330/* The dwarf2 return column, adjusted for 32 or 64 bit. */
331unsigned int x86_dwarf2_return_column;
332
333/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
334int x86_cie_data_alignment;
335
252b5132 336/* Interface to relax_segment.
fddf5b5b
AM		 337 There are 3 major relax states for 386 jump insns because the
338 different types of jumps add different sizes to frags when we're
339 figuring out what sort of jump to choose to reach a given label. */
252b5132 340
47926f60 341/* Types. */
93c2a809
AM		 342#define UNCOND_JUMP 0
343#define COND_JUMP 1
344#define COND_JUMP86 2
fddf5b5b 345
47926f60 346/* Sizes. */
252b5132
RH		 347#define CODE16 1
348#define SMALL 0
29b0f896 349#define SMALL16 (SMALL | CODE16)
252b5132 350#define BIG 2
29b0f896 351#define BIG16 (BIG | CODE16)
252b5132
RH		 352
353#ifndef INLINE
354#ifdef __GNUC__
355#define INLINE __inline__
356#else
357#define INLINE
358#endif
359#endif
360
fddf5b5b
AM		 361#define ENCODE_RELAX_STATE(type, size) \
362 ((relax_substateT) (((type) << 2) | (size)))
363#define TYPE_FROM_RELAX_STATE(s) \
364 ((s) >> 2)
365#define DISP_SIZE_FROM_RELAX_STATE(s) \
366 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 367
368/* This table is used by relax_frag to promote short jumps to long
369 ones where necessary. SMALL (short) jumps may be promoted to BIG
370 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
371 don't allow a short jump in a 32 bit code segment to be promoted to
372 a 16 bit offset jump because it's slower (requires data size
373 prefix), and doesn't work, unless the destination is in the bottom
374 64k of the code segment (The top 16 bits of eip are zeroed). */
375
376const relax_typeS md_relax_table[] =
377{
24eab124
AM		 378 /* The fields are:
379 1) most positive reach of this state,
380 2) most negative reach of this state,
93c2a809 381 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 382 4) which index into the table to try if we can't fit into this one. */
252b5132 383
fddf5b5b 384 /* UNCOND_JUMP states. */
93c2a809
AM		 385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
387 /* dword jmp adds 4 bytes to frag:
388 0 extra opcode bytes, 4 displacement bytes. */
252b5132 389 {0, 0, 4, 0},
93c2a809
AM		 390 /* word jmp adds 2 byte2 to frag:
391 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 392 {0, 0, 2, 0},
393
93c2a809
AM		 394 /* COND_JUMP states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
397 /* dword conditionals adds 5 bytes to frag:
398 1 extra opcode byte, 4 displacement bytes. */
399 {0, 0, 5, 0},
fddf5b5b 400 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 401 1 extra opcode byte, 2 displacement bytes. */
402 {0, 0, 3, 0},
403
404 /* COND_JUMP86 states. */
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
406 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
407 /* dword conditionals adds 5 bytes to frag:
408 1 extra opcode byte, 4 displacement bytes. */
409 {0, 0, 5, 0},
410 /* word conditionals add 4 bytes to frag:
411 1 displacement byte and a 3 byte long branch insn. */
412 {0, 0, 4, 0}
252b5132
RH		 413};
414
e413e4e9
AM		 415static const arch_entry cpu_arch[] = {
416 {"i8086", Cpu086 },
417 {"i186", Cpu086|Cpu186 },
418 {"i286", Cpu086|Cpu186|Cpu286 },
419 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
420 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 421 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
422 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
423 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
424 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
425 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
426 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
427 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
428 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
429 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
430 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
431 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
432 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 433 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 434 {".mmx", CpuMMX },
435 {".sse", CpuMMX|CpuMMX2|CpuSSE },
436 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 437 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 438 {".3dnow", CpuMMX|Cpu3dnow },
439 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
440 {".padlock", CpuPadLock },
30123838
JB		 441 {".pacifica", CpuSVME },
442 {".svme", CpuSVME },
e413e4e9
AM		 443 {NULL, 0 }
444};
445
29b0f896
AM		 446const pseudo_typeS md_pseudo_table[] =
447{
448#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
449 {"align", s_align_bytes, 0},
450#else
451 {"align", s_align_ptwo, 0},
452#endif
453 {"arch", set_cpu_arch, 0},
454#ifndef I386COFF
455 {"bss", s_bss, 0},
456#endif
457 {"ffloat", float_cons, 'f'},
458 {"dfloat", float_cons, 'd'},
459 {"tfloat", float_cons, 'x'},
460 {"value", cons, 2},
461 {"noopt", s_ignore, 0},
462 {"optim", s_ignore, 0},
463 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
464 {"code16", set_code_flag, CODE_16BIT},
465 {"code32", set_code_flag, CODE_32BIT},
466 {"code64", set_code_flag, CODE_64BIT},
467 {"intel_syntax", set_intel_syntax, 1},
468 {"att_syntax", set_intel_syntax, 0},
c6682705 469 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 470 {"loc", dwarf2_directive_loc, 0},
3b22753a
L		 471#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
472 {"largecomm", handle_large_common, 0},
473#endif
6482c264
NC		 474#ifdef TE_PE
475 {"secrel32", pe_directive_secrel, 0},
476#endif
29b0f896
AM		 477 {0, 0, 0}
478};
479
480/* For interface with expression (). */
481extern char *input_line_pointer;
482
483/* Hash table for instruction mnemonic lookup. */
484static struct hash_control *op_hash;
485
486/* Hash table for register lookup. */
487static struct hash_control *reg_hash;
488\f
252b5132
RH		 489void
490i386_align_code (fragP, count)
491 fragS *fragP;
492 int count;
493{
ce8a8b2f
AM		 494 /* Various efficient no-op patterns for aligning code labels.
495 Note: Don't try to assemble the instructions in the comments.
496 0L and 0w are not legal. */
252b5132
RH		 497 static const char f32_1[] =
498 {0x90}; /* nop */
499 static const char f32_2[] =
500 {0x89,0xf6}; /* movl %esi,%esi */
501 static const char f32_3[] =
502 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
503 static const char f32_4[] =
504 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
505 static const char f32_5[] =
506 {0x90, /* nop */
507 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
508 static const char f32_6[] =
509 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
510 static const char f32_7[] =
511 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
512 static const char f32_8[] =
513 {0x90, /* nop */
514 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
515 static const char f32_9[] =
516 {0x89,0xf6, /* movl %esi,%esi */
517 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
518 static const char f32_10[] =
519 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
520 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
521 static const char f32_11[] =
522 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_12[] =
525 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
526 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
527 static const char f32_13[] =
528 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_14[] =
531 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
532 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
533 static const char f32_15[] =
534 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
535 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 536 static const char f16_3[] =
537 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 538 static const char f16_4[] =
539 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
540 static const char f16_5[] =
541 {0x90, /* nop */
542 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
543 static const char f16_6[] =
544 {0x89,0xf6, /* mov %si,%si */
545 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
546 static const char f16_7[] =
547 {0x8d,0x74,0x00, /* lea 0(%si),%si */
548 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
549 static const char f16_8[] =
550 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char *const f32_patt[] = {
553 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
554 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
555 };
556 static const char *const f16_patt[] = {
c3332e24 557 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 558 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
559 };
560
33fef721
JH		 561 if (count <= 0 || count > 15)
562 return;
3e73aa7c 563
33fef721
JH		 564 /* The recommended way to pad 64bit code is to use NOPs preceded by
565 maximally four 0x66 prefixes. Balance the size of nops. */
566 if (flag_code == CODE_64BIT)
252b5132 567 {
33fef721
JH		 568 int i;
569 int nnops = (count + 3) / 4;
570 int len = count / nnops;
571 int remains = count - nnops * len;
572 int pos = 0;
573
574 for (i = 0; i < remains; i++)
252b5132 575 {
33fef721
JH		 576 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
577 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
578 pos += len + 1;
579 }
580 for (; i < nnops; i++)
581 {
582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
583 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
584 pos += len;
252b5132 585 }
252b5132 586 }
33fef721
JH		 587 else
588 if (flag_code == CODE_16BIT)
589 {
590 memcpy (fragP->fr_literal + fragP->fr_fix,
591 f16_patt[count - 1], count);
592 if (count > 8)
593 /* Adjust jump offset. */
594 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
595 }
596 else
597 memcpy (fragP->fr_literal + fragP->fr_fix,
598 f32_patt[count - 1], count);
599 fragP->fr_var = count;
252b5132
RH		 600}
601
252b5132
RH		 602static INLINE unsigned int
603mode_from_disp_size (t)
604 unsigned int t;
605{
3e73aa7c 606 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 607}
608
609static INLINE int
610fits_in_signed_byte (num)
847f7ad4 611 offsetT num;
252b5132
RH		 612{
613 return (num >= -128) && (num <= 127);
47926f60 614}
252b5132
RH		 615
616static INLINE int
617fits_in_unsigned_byte (num)
847f7ad4 618 offsetT num;
252b5132
RH		 619{
620 return (num & 0xff) == num;
47926f60 621}
252b5132
RH		 622
623static INLINE int
624fits_in_unsigned_word (num)
847f7ad4 625 offsetT num;
252b5132
RH		 626{
627 return (num & 0xffff) == num;
47926f60 628}
252b5132
RH		 629
630static INLINE int
631fits_in_signed_word (num)
847f7ad4 632 offsetT num;
252b5132
RH		 633{
634 return (-32768 <= num) && (num <= 32767);
47926f60 635}
3e73aa7c
JH		 636static INLINE int
637fits_in_signed_long (num)
638 offsetT num ATTRIBUTE_UNUSED;
639{
640#ifndef BFD64
641 return 1;
642#else
643 return (!(((offsetT) -1 << 31) & num)
644 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
645#endif
646} /* fits_in_signed_long() */
647static INLINE int
648fits_in_unsigned_long (num)
649 offsetT num ATTRIBUTE_UNUSED;
650{
651#ifndef BFD64
652 return 1;
653#else
654 return (num & (((offsetT) 2 << 31) - 1)) == num;
655#endif
656} /* fits_in_unsigned_long() */
252b5132
RH		 657
658static int
659smallest_imm_type (num)
847f7ad4 660 offsetT num;
252b5132 661{
a847613f 662 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 663 {
664 /* This code is disabled on the 486 because all the Imm1 forms
665 in the opcode table are slower on the i486. They're the
666 versions with the implicitly specified single-position
667 displacement, which has another syntax if you really want to
668 use that form. */
669 if (num == 1)
3e73aa7c 670 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 671 }
252b5132 672 return (fits_in_signed_byte (num)
3e73aa7c 673 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 674 : fits_in_unsigned_byte (num)
3e73aa7c 675 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 676 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 677 ? (Imm16 | Imm32 | Imm32S | Imm64)
678 : fits_in_signed_long (num)
679 ? (Imm32 | Imm32S | Imm64)
680 : fits_in_unsigned_long (num)
681 ? (Imm32 | Imm64)
682 : Imm64);
47926f60 683}
252b5132 684
847f7ad4
AM		 685static offsetT
686offset_in_range (val, size)
687 offsetT val;
688 int size;
689{
508866be 690 addressT mask;
ba2adb93 691
847f7ad4
AM		 692 switch (size)
693 {
508866be
L		 694 case 1: mask = ((addressT) 1 << 8) - 1; break;
695 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 696 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 697#ifdef BFD64
698 case 8: mask = ((addressT) 2 << 63) - 1; break;
699#endif
47926f60 700 default: abort ();
847f7ad4
AM		 701 }
702
ba2adb93 703 /* If BFD64, sign extend val. */
3e73aa7c
JH		 704 if (!use_rela_relocations)
705 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
706 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 707
47926f60 708 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 709 {
710 char buf1[40], buf2[40];
711
712 sprint_value (buf1, val);
713 sprint_value (buf2, val & mask);
714 as_warn (_("%s shortened to %s"), buf1, buf2);
715 }
716 return val & mask;
717}
718
252b5132
RH		 719/* Returns 0 if attempting to add a prefix where one from the same
720 class already exists, 1 if non rep/repne added, 2 if rep/repne
721 added. */
722static int
723add_prefix (prefix)
724 unsigned int prefix;
725{
726 int ret = 1;
727 int q;
728
29b0f896
AM		 729 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
730 && flag_code == CODE_64BIT)
3e73aa7c
JH		 731 q = REX_PREFIX;
732 else
733 switch (prefix)
734 {
735 default:
736 abort ();
737
738 case CS_PREFIX_OPCODE:
739 case DS_PREFIX_OPCODE:
740 case ES_PREFIX_OPCODE:
741 case FS_PREFIX_OPCODE:
742 case GS_PREFIX_OPCODE:
743 case SS_PREFIX_OPCODE:
744 q = SEG_PREFIX;
745 break;
252b5132 746
3e73aa7c
JH		 747 case REPNE_PREFIX_OPCODE:
748 case REPE_PREFIX_OPCODE:
749 ret = 2;
750 /* fall thru */
751 case LOCK_PREFIX_OPCODE:
752 q = LOCKREP_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case FWAIT_OPCODE:
756 q = WAIT_PREFIX;
757 break;
252b5132 758
3e73aa7c
JH		 759 case ADDR_PREFIX_OPCODE:
760 q = ADDR_PREFIX;
761 break;
252b5132 762
3e73aa7c
JH		 763 case DATA_PREFIX_OPCODE:
764 q = DATA_PREFIX;
765 break;
766 }
252b5132 767
29b0f896 768 if (i.prefix[q] != 0)
252b5132
RH		 769 {
770 as_bad (_("same type of prefix used twice"));
771 return 0;
772 }
773
774 i.prefixes += 1;
775 i.prefix[q] = prefix;
776 return ret;
777}
778
779static void
3e73aa7c 780set_code_flag (value)
e5cb08ac 781 int value;
eecb386c 782{
3e73aa7c
JH		 783 flag_code = value;
784 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
785 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
786 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
787 {
788 as_bad (_("64bit mode not supported on this CPU."));
789 }
790 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
791 {
792 as_bad (_("32bit mode not supported on this CPU."));
793 }
eecb386c
AM		 794 stackop_size = '\0';
795}
796
797static void
3e73aa7c
JH		 798set_16bit_gcc_code_flag (new_code_flag)
799 int new_code_flag;
252b5132 800{
3e73aa7c
JH		 801 flag_code = new_code_flag;
802 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
803 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 804 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 805}
806
807static void
808set_intel_syntax (syntax_flag)
eecb386c 809 int syntax_flag;
252b5132
RH		 810{
811 /* Find out if register prefixing is specified. */
812 int ask_naked_reg = 0;
813
814 SKIP_WHITESPACE ();
29b0f896 815 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 816 {
817 char *string = input_line_pointer;
818 int e = get_symbol_end ();
819
47926f60 820 if (strcmp (string, "prefix") == 0)
252b5132 821 ask_naked_reg = 1;
47926f60 822 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 823 ask_naked_reg = -1;
824 else
d0b47220 825 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 826 *input_line_pointer = e;
827 }
828 demand_empty_rest_of_line ();
c3332e24 829
252b5132
RH		 830 intel_syntax = syntax_flag;
831
832 if (ask_naked_reg == 0)
f86103b7
AM		 833 allow_naked_reg = (intel_syntax
834 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 835 else
836 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 837
838 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
839 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 840}
841
e413e4e9
AM		 842static void
843set_cpu_arch (dummy)
47926f60 844 int dummy ATTRIBUTE_UNUSED;
e413e4e9 845{
47926f60 846 SKIP_WHITESPACE ();
e413e4e9 847
29b0f896 848 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 849 {
850 char *string = input_line_pointer;
851 int e = get_symbol_end ();
852 int i;
853
854 for (i = 0; cpu_arch[i].name; i++)
855 {
856 if (strcmp (string, cpu_arch[i].name) == 0)
857 {
5c6af06e
JB		 858 if (*string != '.')
859 {
860 cpu_arch_name = cpu_arch[i].name;
861 cpu_sub_arch_name = NULL;
862 cpu_arch_flags = (cpu_arch[i].flags
863 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
864 break;
865 }
866 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
867 {
868 cpu_sub_arch_name = cpu_arch[i].name;
869 cpu_arch_flags |= cpu_arch[i].flags;
870 }
871 *input_line_pointer = e;
872 demand_empty_rest_of_line ();
873 return;
e413e4e9
AM		 874 }
875 }
876 if (!cpu_arch[i].name)
877 as_bad (_("no such architecture: `%s'"), string);
878
879 *input_line_pointer = e;
880 }
881 else
882 as_bad (_("missing cpu architecture"));
883
fddf5b5b
AM		 884 no_cond_jump_promotion = 0;
885 if (*input_line_pointer == ','
29b0f896 886 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 887 {
888 char *string = ++input_line_pointer;
889 int e = get_symbol_end ();
890
891 if (strcmp (string, "nojumps") == 0)
892 no_cond_jump_promotion = 1;
893 else if (strcmp (string, "jumps") == 0)
894 ;
895 else
896 as_bad (_("no such architecture modifier: `%s'"), string);
897
898 *input_line_pointer = e;
899 }
900
e413e4e9
AM		 901 demand_empty_rest_of_line ();
902}
903
b9d79e03
JH		 904unsigned long
905i386_mach ()
906{
907 if (!strcmp (default_arch, "x86_64"))
908 return bfd_mach_x86_64;
909 else if (!strcmp (default_arch, "i386"))
910 return bfd_mach_i386_i386;
911 else
912 as_fatal (_("Unknown architecture"));
913}
b9d79e03 914\f
252b5132
RH		 915void
916md_begin ()
917{
918 const char *hash_err;
919
47926f60 920 /* Initialize op_hash hash table. */
252b5132
RH		 921 op_hash = hash_new ();
922
923 {
29b0f896
AM		 924 const template *optab;
925 templates *core_optab;
252b5132 926
47926f60
KH		 927 /* Setup for loop. */
928 optab = i386_optab;
252b5132
RH		 929 core_optab = (templates *) xmalloc (sizeof (templates));
930 core_optab->start = optab;
931
932 while (1)
933 {
934 ++optab;
935 if (optab->name == NULL
936 || strcmp (optab->name, (optab - 1)->name) != 0)
937 {
938 /* different name --> ship out current template list;
47926f60 939 add to hash table; & begin anew. */
252b5132
RH		 940 core_optab->end = optab;
941 hash_err = hash_insert (op_hash,
942 (optab - 1)->name,
943 (PTR) core_optab);
944 if (hash_err)
945 {
252b5132
RH		 946 as_fatal (_("Internal Error: Can't hash %s: %s"),
947 (optab - 1)->name,
948 hash_err);
949 }
950 if (optab->name == NULL)
951 break;
952 core_optab = (templates *) xmalloc (sizeof (templates));
953 core_optab->start = optab;
954 }
955 }
956 }
957
47926f60 958 /* Initialize reg_hash hash table. */
252b5132
RH		 959 reg_hash = hash_new ();
960 {
29b0f896 961 const reg_entry *regtab;
252b5132
RH		 962
963 for (regtab = i386_regtab;
964 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
965 regtab++)
966 {
967 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
968 if (hash_err)
3e73aa7c
JH		 969 as_fatal (_("Internal Error: Can't hash %s: %s"),
970 regtab->reg_name,
971 hash_err);
252b5132
RH		 972 }
973 }
974
47926f60 975 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 976 {
29b0f896
AM		 977 int c;
978 char *p;
252b5132
RH		 979
980 for (c = 0; c < 256; c++)
981 {
3882b010 982 if (ISDIGIT (c))
252b5132
RH		 983 {
984 digit_chars[c] = c;
985 mnemonic_chars[c] = c;
986 register_chars[c] = c;
987 operand_chars[c] = c;
988 }
3882b010 989 else if (ISLOWER (c))
252b5132
RH		 990 {
991 mnemonic_chars[c] = c;
992 register_chars[c] = c;
993 operand_chars[c] = c;
994 }
3882b010 995 else if (ISUPPER (c))
252b5132 996 {
3882b010 997 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 998 register_chars[c] = mnemonic_chars[c];
999 operand_chars[c] = c;
1000 }
1001
3882b010 1002 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1003 identifier_chars[c] = c;
1004 else if (c >= 128)
1005 {
1006 identifier_chars[c] = c;
1007 operand_chars[c] = c;
1008 }
1009 }
1010
1011#ifdef LEX_AT
1012 identifier_chars['@'] = '@';
32137342
NC		 1013#endif
1014#ifdef LEX_QM
1015 identifier_chars['?'] = '?';
1016 operand_chars['?'] = '?';
252b5132 1017#endif
252b5132 1018 digit_chars['-'] = '-';
791fe849 1019 mnemonic_chars['-'] = '-';
252b5132
RH		 1020 identifier_chars['_'] = '_';
1021 identifier_chars['.'] = '.';
1022
1023 for (p = operand_special_chars; *p != '\0'; p++)
1024 operand_chars[(unsigned char) *p] = *p;
1025 }
1026
1027#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1028 if (IS_ELF)
252b5132
RH		 1029 {
1030 record_alignment (text_section, 2);
1031 record_alignment (data_section, 2);
1032 record_alignment (bss_section, 2);
1033 }
1034#endif
a4447b93
RH		 1035
1036 if (flag_code == CODE_64BIT)
1037 {
1038 x86_dwarf2_return_column = 16;
1039 x86_cie_data_alignment = -8;
1040 }
1041 else
1042 {
1043 x86_dwarf2_return_column = 8;
1044 x86_cie_data_alignment = -4;
1045 }
252b5132
RH		 1046}
1047
1048void
1049i386_print_statistics (file)
1050 FILE *file;
1051{
1052 hash_print_statistics (file, "i386 opcode", op_hash);
1053 hash_print_statistics (file, "i386 register", reg_hash);
1054}
1055\f
252b5132
RH		 1056#ifdef DEBUG386
1057
ce8a8b2f 1058/* Debugging routines for md_assemble. */
252b5132
RH		 1059static void pi PARAMS ((char *, i386_insn *));
1060static void pte PARAMS ((template *));
1061static void pt PARAMS ((unsigned int));
1062static void pe PARAMS ((expressionS *));
1063static void ps PARAMS ((symbolS *));
1064
1065static void
1066pi (line, x)
1067 char *line;
1068 i386_insn *x;
1069{
09f131f2 1070 unsigned int i;
252b5132
RH		 1071
1072 fprintf (stdout, "%s: template ", line);
1073 pte (&x->tm);
09f131f2
JH		 1074 fprintf (stdout, " address: base %s index %s scale %x\n",
1075 x->base_reg ? x->base_reg->reg_name : "none",
1076 x->index_reg ? x->index_reg->reg_name : "none",
1077 x->log2_scale_factor);
1078 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1079 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1080 fprintf (stdout, " sib: base %x index %x scale %x\n",
1081 x->sib.base, x->sib.index, x->sib.scale);
1082 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1083 (x->rex & REX_MODE64) != 0,
1084 (x->rex & REX_EXTX) != 0,
1085 (x->rex & REX_EXTY) != 0,
1086 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1087 for (i = 0; i < x->operands; i++)
1088 {
1089 fprintf (stdout, " #%d: ", i + 1);
1090 pt (x->types[i]);
1091 fprintf (stdout, "\n");
1092 if (x->types[i]
3f4438ab 1093 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1094 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1095 if (x->types[i] & Imm)
520dc8e8 1096 pe (x->op[i].imms);
252b5132 1097 if (x->types[i] & Disp)
520dc8e8 1098 pe (x->op[i].disps);
252b5132
RH		 1099 }
1100}
1101
1102static void
1103pte (t)
1104 template *t;
1105{
09f131f2 1106 unsigned int i;
252b5132 1107 fprintf (stdout, " %d operands ", t->operands);
47926f60 1108 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1109 if (t->extension_opcode != None)
1110 fprintf (stdout, "ext %x ", t->extension_opcode);
1111 if (t->opcode_modifier & D)
1112 fprintf (stdout, "D");
1113 if (t->opcode_modifier & W)
1114 fprintf (stdout, "W");
1115 fprintf (stdout, "\n");
1116 for (i = 0; i < t->operands; i++)
1117 {
1118 fprintf (stdout, " #%d type ", i + 1);
1119 pt (t->operand_types[i]);
1120 fprintf (stdout, "\n");
1121 }
1122}
1123
1124static void
1125pe (e)
1126 expressionS *e;
1127{
24eab124 1128 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1129 fprintf (stdout, " add_number %ld (%lx)\n",
1130 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1131 if (e->X_add_symbol)
1132 {
1133 fprintf (stdout, " add_symbol ");
1134 ps (e->X_add_symbol);
1135 fprintf (stdout, "\n");
1136 }
1137 if (e->X_op_symbol)
1138 {
1139 fprintf (stdout, " op_symbol ");
1140 ps (e->X_op_symbol);
1141 fprintf (stdout, "\n");
1142 }
1143}
1144
1145static void
1146ps (s)
1147 symbolS *s;
1148{
1149 fprintf (stdout, "%s type %s%s",
1150 S_GET_NAME (s),
1151 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1152 segment_name (S_GET_SEGMENT (s)));
1153}
1154
1155struct type_name
1156 {
1157 unsigned int mask;
1158 char *tname;
1159 }
1160
29b0f896 1161static const type_names[] =
252b5132
RH		 1162{
1163 { Reg8, "r8" },
1164 { Reg16, "r16" },
1165 { Reg32, "r32" },
09f131f2 1166 { Reg64, "r64" },
252b5132
RH		 1167 { Imm8, "i8" },
1168 { Imm8S, "i8s" },
1169 { Imm16, "i16" },
1170 { Imm32, "i32" },
09f131f2
JH		 1171 { Imm32S, "i32s" },
1172 { Imm64, "i64" },
252b5132
RH		 1173 { Imm1, "i1" },
1174 { BaseIndex, "BaseIndex" },
1175 { Disp8, "d8" },
1176 { Disp16, "d16" },
1177 { Disp32, "d32" },
09f131f2
JH		 1178 { Disp32S, "d32s" },
1179 { Disp64, "d64" },
252b5132
RH		 1180 { InOutPortReg, "InOutPortReg" },
1181 { ShiftCount, "ShiftCount" },
1182 { Control, "control reg" },
1183 { Test, "test reg" },
1184 { Debug, "debug reg" },
1185 { FloatReg, "FReg" },
1186 { FloatAcc, "FAcc" },
1187 { SReg2, "SReg2" },
1188 { SReg3, "SReg3" },
1189 { Acc, "Acc" },
1190 { JumpAbsolute, "Jump Absolute" },
1191 { RegMMX, "rMMX" },
3f4438ab 1192 { RegXMM, "rXMM" },
252b5132
RH		 1193 { EsSeg, "es" },
1194 { 0, "" }
1195};
1196
1197static void
1198pt (t)
1199 unsigned int t;
1200{
29b0f896 1201 const struct type_name *ty;
252b5132 1202
09f131f2
JH		 1203 for (ty = type_names; ty->mask; ty++)
1204 if (t & ty->mask)
1205 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1206 fflush (stdout);
1207}
1208
1209#endif /* DEBUG386 */
1210\f
252b5132 1211static bfd_reloc_code_real_type
3956db08
JB		 1212reloc (unsigned int size,
1213 int pcrel,
1214 int sign,
1215 bfd_reloc_code_real_type other)
252b5132 1216{
47926f60 1217 if (other != NO_RELOC)
3956db08
JB		 1218 {
1219 reloc_howto_type *reloc;
1220
1221 if (size == 8)
1222 switch (other)
1223 {
1224 case BFD_RELOC_X86_64_TPOFF32:
1225 other = BFD_RELOC_X86_64_TPOFF64;
1226 break;
1227 case BFD_RELOC_X86_64_DTPOFF32:
1228 other = BFD_RELOC_X86_64_DTPOFF64;
1229 break;
1230 default:
1231 break;
1232 }
1233 reloc = bfd_reloc_type_lookup (stdoutput, other);
1234 if (!reloc)
1235 as_bad (_("unknown relocation (%u)"), other);
1236 else if (size != bfd_get_reloc_size (reloc))
1237 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1238 bfd_get_reloc_size (reloc),
1239 size);
1240 else if (pcrel && !reloc->pc_relative)
1241 as_bad (_("non-pc-relative relocation for pc-relative field"));
1242 else if ((reloc->complain_on_overflow == complain_overflow_signed
1243 && !sign)
1244 || (reloc->complain_on_overflow == complain_overflow_unsigned
1245 && sign > 0))
1246 as_bad (_("relocated field and relocation type differ in signedness"));
1247 else
1248 return other;
1249 return NO_RELOC;
1250 }
252b5132
RH		 1251
1252 if (pcrel)
1253 {
3e73aa7c 1254 if (!sign)
3956db08 1255 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1256 switch (size)
1257 {
1258 case 1: return BFD_RELOC_8_PCREL;
1259 case 2: return BFD_RELOC_16_PCREL;
1260 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1261 case 8: return BFD_RELOC_64_PCREL;
252b5132 1262 }
3956db08 1263 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1264 }
1265 else
1266 {
3956db08 1267 if (sign > 0)
e5cb08ac 1268 switch (size)
3e73aa7c
JH		 1269 {
1270 case 4: return BFD_RELOC_X86_64_32S;
1271 }
1272 else
1273 switch (size)
1274 {
1275 case 1: return BFD_RELOC_8;
1276 case 2: return BFD_RELOC_16;
1277 case 4: return BFD_RELOC_32;
1278 case 8: return BFD_RELOC_64;
1279 }
3956db08
JB		 1280 as_bad (_("cannot do %s %u byte relocation"),
1281 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1282 }
1283
bfb32b52 1284 abort ();
252b5132
RH		 1285 return BFD_RELOC_NONE;
1286}
1287
47926f60
KH		 1288/* Here we decide which fixups can be adjusted to make them relative to
1289 the beginning of the section instead of the symbol. Basically we need
1290 to make sure that the dynamic relocations are done correctly, so in
1291 some cases we force the original symbol to be used. */
1292
252b5132 1293int
c0c949c7 1294tc_i386_fix_adjustable (fixP)
31312f95 1295 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1296{
6d249963 1297#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1298 if (!IS_ELF)
31312f95
AM		 1299 return 1;
1300
a161fe53
AM		 1301 /* Don't adjust pc-relative references to merge sections in 64-bit
1302 mode. */
1303 if (use_rela_relocations
1304 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1305 && fixP->fx_pcrel)
252b5132 1306 return 0;
31312f95 1307
8d01d9a9
AJ		 1308 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1309 and changed later by validate_fix. */
1310 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1311 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1312 return 0;
1313
ce8a8b2f 1314 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1315 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1316 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1317 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1318 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1319 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1320 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1321 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1322 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1324 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1325 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1326 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1328 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1330 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1332 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1333 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1335 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1337 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1338 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1339 return 0;
31312f95 1340#endif
252b5132
RH		 1341 return 1;
1342}
252b5132 1343
29b0f896 1344static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1345
1346static int
252b5132 1347intel_float_operand (mnemonic)
29b0f896 1348 const char *mnemonic;
252b5132 1349{
9306ca4a
JB		 1350 /* Note that the value returned is meaningful only for opcodes with (memory)
1351 operands, hence the code here is free to improperly handle opcodes that
1352 have no operands (for better performance and smaller code). */
1353
1354 if (mnemonic[0] != 'f')
1355 return 0; /* non-math */
1356
1357 switch (mnemonic[1])
1358 {
1359 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1360 the fs segment override prefix not currently handled because no
1361 call path can make opcodes without operands get here */
1362 case 'i':
1363 return 2 /* integer op */;
1364 case 'l':
1365 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1366 return 3; /* fldcw/fldenv */
1367 break;
1368 case 'n':
1369 if (mnemonic[2] != 'o' /* fnop */)
1370 return 3; /* non-waiting control op */
1371 break;
1372 case 'r':
1373 if (mnemonic[2] == 's')
1374 return 3; /* frstor/frstpm */
1375 break;
1376 case 's':
1377 if (mnemonic[2] == 'a')
1378 return 3; /* fsave */
1379 if (mnemonic[2] == 't')
1380 {
1381 switch (mnemonic[3])
1382 {
1383 case 'c': /* fstcw */
1384 case 'd': /* fstdw */
1385 case 'e': /* fstenv */
1386 case 's': /* fsts[gw] */
1387 return 3;
1388 }
1389 }
1390 break;
1391 case 'x':
1392 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1393 return 0; /* fxsave/fxrstor are not really math ops */
1394 break;
1395 }
252b5132 1396
9306ca4a 1397 return 1;
252b5132
RH		 1398}
1399
1400/* This is the guts of the machine-dependent assembler. LINE points to a
1401 machine dependent instruction. This function is supposed to emit
1402 the frags/bytes it assembles to. */
1403
1404void
1405md_assemble (line)
1406 char *line;
1407{
252b5132 1408 int j;
252b5132
RH		 1409 char mnemonic[MAX_MNEM_SIZE];
1410
47926f60 1411 /* Initialize globals. */
252b5132
RH		 1412 memset (&i, '\0', sizeof (i));
1413 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1414 i.reloc[j] = NO_RELOC;
252b5132
RH		 1415 memset (disp_expressions, '\0', sizeof (disp_expressions));
1416 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1417 save_stack_p = save_stack;
252b5132
RH		 1418
1419 /* First parse an instruction mnemonic & call i386_operand for the operands.
1420 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1421 start of a (possibly prefixed) mnemonic. */
252b5132 1422
29b0f896
AM		 1423 line = parse_insn (line, mnemonic);
1424 if (line == NULL)
1425 return;
252b5132 1426
29b0f896
AM		 1427 line = parse_operands (line, mnemonic);
1428 if (line == NULL)
1429 return;
252b5132 1430
29b0f896
AM		 1431 /* Now we've parsed the mnemonic into a set of templates, and have the
1432 operands at hand. */
1433
1434 /* All intel opcodes have reversed operands except for "bound" and
1435 "enter". We also don't reverse intersegment "jmp" and "call"
1436 instructions with 2 immediate operands so that the immediate segment
1437 precedes the offset, as it does when in AT&T mode. "enter" and the
1438 intersegment "jmp" and "call" instructions are the only ones that
1439 have two immediate operands. */
1440 if (intel_syntax && i.operands > 1
1441 && (strcmp (mnemonic, "bound") != 0)
30123838 1442 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1443 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1444 swap_operands ();
1445
1446 if (i.imm_operands)
1447 optimize_imm ();
1448
b300c311
L		 1449 /* Don't optimize displacement for movabs since it only takes 64bit
1450 displacement. */
1451 if (i.disp_operands
1452 && (flag_code != CODE_64BIT
1453 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1454 optimize_disp ();
1455
1456 /* Next, we find a template that matches the given insn,
1457 making sure the overlap of the given operands types is consistent
1458 with the template operand types. */
252b5132 1459
29b0f896
AM		 1460 if (!match_template ())
1461 return;
252b5132 1462
cd61ebfe
AM		 1463 if (intel_syntax)
1464 {
1465 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1466 if (SYSV386_COMPAT
1467 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1468 i.tm.base_opcode ^= FloatR;
1469
1470 /* Zap movzx and movsx suffix. The suffix may have been set from
1471 "word ptr" or "byte ptr" on the source operand, but we'll use
1472 the suffix later to choose the destination register. */
1473 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1474 {
1475 if (i.reg_operands < 2
1476 && !i.suffix
1477 && (~i.tm.opcode_modifier
1478 & (No_bSuf
1479 | No_wSuf
1480 | No_lSuf
1481 | No_sSuf
1482 | No_xSuf
1483 | No_qSuf)))
1484 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1485
1486 i.suffix = 0;
1487 }
cd61ebfe 1488 }
24eab124 1489
29b0f896
AM		 1490 if (i.tm.opcode_modifier & FWait)
1491 if (!add_prefix (FWAIT_OPCODE))
1492 return;
252b5132 1493
29b0f896
AM		 1494 /* Check string instruction segment overrides. */
1495 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1496 {
1497 if (!check_string ())
5dd0794d 1498 return;
29b0f896 1499 }
5dd0794d 1500
29b0f896
AM		 1501 if (!process_suffix ())
1502 return;
e413e4e9 1503
29b0f896
AM		 1504 /* Make still unresolved immediate matches conform to size of immediate
1505 given in i.suffix. */
1506 if (!finalize_imm ())
1507 return;
252b5132 1508
29b0f896
AM		 1509 if (i.types[0] & Imm1)
1510 i.imm_operands = 0; /* kludge for shift insns. */
1511 if (i.types[0] & ImplicitRegister)
1512 i.reg_operands--;
1513 if (i.types[1] & ImplicitRegister)
1514 i.reg_operands--;
1515 if (i.types[2] & ImplicitRegister)
1516 i.reg_operands--;
252b5132 1517
29b0f896
AM		 1518 if (i.tm.opcode_modifier & ImmExt)
1519 {
02fc3089
L		 1520 expressionS *exp;
1521
ca164297
L		 1522 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1523 {
67c1ffbe 1524 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1525 operands with an opcode suffix which is coded in the same
1526 place as an 8-bit immediate field would be. Here we check
1527 those operands and remove them afterwards. */
1528 unsigned int x;
1529
a4622f40 1530 for (x = 0; x < i.operands; x++)
ca164297
L		 1531 if (i.op[x].regs->reg_num != x)
1532 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1533 i.op[x].regs->reg_name, x + 1, i.tm.name);
1534 i.operands = 0;
1535 }
1536
29b0f896
AM		 1537 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1538 opcode suffix which is coded in the same place as an 8-bit
1539 immediate field would be. Here we fake an 8-bit immediate
1540 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1541
29b0f896 1542 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1543
29b0f896
AM		 1544 exp = &im_expressions[i.imm_operands++];
1545 i.op[i.operands].imms = exp;
1546 i.types[i.operands++] = Imm8;
1547 exp->X_op = O_constant;
1548 exp->X_add_number = i.tm.extension_opcode;
1549 i.tm.extension_opcode = None;
1550 }
252b5132 1551
29b0f896
AM		 1552 /* For insns with operands there are more diddles to do to the opcode. */
1553 if (i.operands)
1554 {
1555 if (!process_operands ())
1556 return;
1557 }
1558 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1559 {
1560 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1561 as_warn (_("translating to `%sp'"), i.tm.name);
1562 }
252b5132 1563
29b0f896
AM		 1564 /* Handle conversion of 'int $3' --> special int3 insn. */
1565 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1566 {
1567 i.tm.base_opcode = INT3_OPCODE;
1568 i.imm_operands = 0;
1569 }
252b5132 1570
29b0f896
AM		 1571 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1572 && i.op[0].disps->X_op == O_constant)
1573 {
1574 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1575 the absolute address given by the constant. Since ix86 jumps and
1576 calls are pc relative, we need to generate a reloc. */
1577 i.op[0].disps->X_add_symbol = &abs_symbol;
1578 i.op[0].disps->X_op = O_symbol;
1579 }
252b5132 1580
29b0f896
AM		 1581 if ((i.tm.opcode_modifier & Rex64) != 0)
1582 i.rex |= REX_MODE64;
252b5132 1583
29b0f896
AM		 1584 /* For 8 bit registers we need an empty rex prefix. Also if the
1585 instruction already has a prefix, we need to convert old
1586 registers to new ones. */
773f551c 1587
29b0f896
AM		 1588 if (((i.types[0] & Reg8) != 0
1589 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1590 || ((i.types[1] & Reg8) != 0
1591 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1592 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1593 && i.rex != 0))
1594 {
1595 int x;
726c5dcd 1596
29b0f896
AM		 1597 i.rex |= REX_OPCODE;
1598 for (x = 0; x < 2; x++)
1599 {
1600 /* Look for 8 bit operand that uses old registers. */
1601 if ((i.types[x] & Reg8) != 0
1602 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1603 {
29b0f896
AM		 1604 /* In case it is "hi" register, give up. */
1605 if (i.op[x].regs->reg_num > 3)
0477af35 1606 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1607 i.op[x].regs->reg_name);
773f551c 1608
29b0f896
AM		 1609 /* Otherwise it is equivalent to the extended register.
1610 Since the encoding doesn't change this is merely
1611 cosmetic cleanup for debug output. */
1612
1613 i.op[x].regs = i.op[x].regs + 8;
773f551c 1614 }
29b0f896
AM		 1615 }
1616 }
773f551c 1617
29b0f896
AM		 1618 if (i.rex != 0)
1619 add_prefix (REX_OPCODE | i.rex);
1620
1621 /* We are ready to output the insn. */
1622 output_insn ();
1623}
1624
1625static char *
1626parse_insn (line, mnemonic)
1627 char *line;
1628 char *mnemonic;
1629{
1630 char *l = line;
1631 char *token_start = l;
1632 char *mnem_p;
5c6af06e
JB		 1633 int supported;
1634 const template *t;
29b0f896
AM		 1635
1636 /* Non-zero if we found a prefix only acceptable with string insns. */
1637 const char *expecting_string_instruction = NULL;
45288df1 1638
29b0f896
AM		 1639 while (1)
1640 {
1641 mnem_p = mnemonic;
1642 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1643 {
1644 mnem_p++;
1645 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1646 {
29b0f896
AM		 1647 as_bad (_("no such instruction: `%s'"), token_start);
1648 return NULL;
1649 }
1650 l++;
1651 }
1652 if (!is_space_char (*l)
1653 && *l != END_OF_INSN
e44823cf
JB		 1654 && (intel_syntax
1655 || (*l != PREFIX_SEPARATOR
1656 && *l != ',')))
29b0f896
AM		 1657 {
1658 as_bad (_("invalid character %s in mnemonic"),
1659 output_invalid (*l));
1660 return NULL;
1661 }
1662 if (token_start == l)
1663 {
e44823cf 1664 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1665 as_bad (_("expecting prefix; got nothing"));
1666 else
1667 as_bad (_("expecting mnemonic; got nothing"));
1668 return NULL;
1669 }
45288df1 1670
29b0f896
AM		 1671 /* Look up instruction (or prefix) via hash table. */
1672 current_templates = hash_find (op_hash, mnemonic);
47926f60 1673
29b0f896
AM		 1674 if (*l != END_OF_INSN
1675 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1676 && current_templates
1677 && (current_templates->start->opcode_modifier & IsPrefix))
1678 {
2dd88dca
JB		 1679 if (current_templates->start->cpu_flags
1680 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1681 {
1682 as_bad ((flag_code != CODE_64BIT
1683 ? _("`%s' is only supported in 64-bit mode")
1684 : _("`%s' is not supported in 64-bit mode")),
1685 current_templates->start->name);
1686 return NULL;
1687 }
29b0f896
AM		 1688 /* If we are in 16-bit mode, do not allow addr16 or data16.
1689 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1690 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1691 && flag_code != CODE_64BIT
1692 && (((current_templates->start->opcode_modifier & Size32) != 0)
1693 ^ (flag_code == CODE_16BIT)))
1694 {
1695 as_bad (_("redundant %s prefix"),
1696 current_templates->start->name);
1697 return NULL;
45288df1 1698 }
29b0f896
AM		 1699 /* Add prefix, checking for repeated prefixes. */
1700 switch (add_prefix (current_templates->start->base_opcode))
1701 {
1702 case 0:
1703 return NULL;
1704 case 2:
1705 expecting_string_instruction = current_templates->start->name;
1706 break;
1707 }
1708 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1709 token_start = ++l;
1710 }
1711 else
1712 break;
1713 }
45288df1 1714
29b0f896
AM		 1715 if (!current_templates)
1716 {
1717 /* See if we can get a match by trimming off a suffix. */
1718 switch (mnem_p[-1])
1719 {
1720 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1721 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1722 i.suffix = SHORT_MNEM_SUFFIX;
1723 else
29b0f896
AM		 1724 case BYTE_MNEM_SUFFIX:
1725 case QWORD_MNEM_SUFFIX:
1726 i.suffix = mnem_p[-1];
1727 mnem_p[-1] = '\0';
1728 current_templates = hash_find (op_hash, mnemonic);
1729 break;
1730 case SHORT_MNEM_SUFFIX:
1731 case LONG_MNEM_SUFFIX:
1732 if (!intel_syntax)
1733 {
1734 i.suffix = mnem_p[-1];
1735 mnem_p[-1] = '\0';
1736 current_templates = hash_find (op_hash, mnemonic);
1737 }
1738 break;
252b5132 1739
29b0f896
AM		 1740 /* Intel Syntax. */
1741 case 'd':
1742 if (intel_syntax)
1743 {
9306ca4a 1744 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1745 i.suffix = SHORT_MNEM_SUFFIX;
1746 else
1747 i.suffix = LONG_MNEM_SUFFIX;
1748 mnem_p[-1] = '\0';
1749 current_templates = hash_find (op_hash, mnemonic);
1750 }
1751 break;
1752 }
1753 if (!current_templates)
1754 {
1755 as_bad (_("no such instruction: `%s'"), token_start);
1756 return NULL;
1757 }
1758 }
252b5132 1759
29b0f896
AM		 1760 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1761 {
1762 /* Check for a branch hint. We allow ",pt" and ",pn" for
1763 predict taken and predict not taken respectively.
1764 I'm not sure that branch hints actually do anything on loop
1765 and jcxz insns (JumpByte) for current Pentium4 chips. They
1766 may work in the future and it doesn't hurt to accept them
1767 now. */
1768 if (l[0] == ',' && l[1] == 'p')
1769 {
1770 if (l[2] == 't')
1771 {
1772 if (!add_prefix (DS_PREFIX_OPCODE))
1773 return NULL;
1774 l += 3;
1775 }
1776 else if (l[2] == 'n')
1777 {
1778 if (!add_prefix (CS_PREFIX_OPCODE))
1779 return NULL;
1780 l += 3;
1781 }
1782 }
1783 }
1784 /* Any other comma loses. */
1785 if (*l == ',')
1786 {
1787 as_bad (_("invalid character %s in mnemonic"),
1788 output_invalid (*l));
1789 return NULL;
1790 }
252b5132 1791
29b0f896 1792 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1793 supported = 0;
1794 for (t = current_templates->start; t < current_templates->end; ++t)
1795 {
1796 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1797 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1798 supported |= 1;
1799 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1800 supported |= 2;
1801 }
1802 if (!(supported & 2))
1803 {
1804 as_bad (flag_code == CODE_64BIT
1805 ? _("`%s' is not supported in 64-bit mode")
1806 : _("`%s' is only supported in 64-bit mode"),
1807 current_templates->start->name);
1808 return NULL;
1809 }
1810 if (!(supported & 1))
29b0f896 1811 {
5c6af06e
JB		 1812 as_warn (_("`%s' is not supported on `%s%s'"),
1813 current_templates->start->name,
1814 cpu_arch_name,
1815 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1816 }
1817 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1818 {
1819 as_warn (_("use .code16 to ensure correct addressing mode"));
1820 }
252b5132 1821
29b0f896 1822 /* Check for rep/repne without a string instruction. */
f41bbced 1823 if (expecting_string_instruction)
29b0f896 1824 {
f41bbced
JB		 1825 static templates override;
1826
1827 for (t = current_templates->start; t < current_templates->end; ++t)
1828 if (t->opcode_modifier & IsString)
1829 break;
1830 if (t >= current_templates->end)
1831 {
1832 as_bad (_("expecting string instruction after `%s'"),
1833 expecting_string_instruction);
1834 return NULL;
1835 }
1836 for (override.start = t; t < current_templates->end; ++t)
1837 if (!(t->opcode_modifier & IsString))
1838 break;
1839 override.end = t;
1840 current_templates = &override;
29b0f896 1841 }
252b5132 1842
29b0f896
AM		 1843 return l;
1844}
252b5132 1845
29b0f896
AM		 1846static char *
1847parse_operands (l, mnemonic)
1848 char *l;
1849 const char *mnemonic;
1850{
1851 char *token_start;
3138f287 1852
29b0f896
AM		 1853 /* 1 if operand is pending after ','. */
1854 unsigned int expecting_operand = 0;
252b5132 1855
29b0f896
AM		 1856 /* Non-zero if operand parens not balanced. */
1857 unsigned int paren_not_balanced;
1858
1859 while (*l != END_OF_INSN)
1860 {
1861 /* Skip optional white space before operand. */
1862 if (is_space_char (*l))
1863 ++l;
1864 if (!is_operand_char (*l) && *l != END_OF_INSN)
1865 {
1866 as_bad (_("invalid character %s before operand %d"),
1867 output_invalid (*l),
1868 i.operands + 1);
1869 return NULL;
1870 }
1871 token_start = l; /* after white space */
1872 paren_not_balanced = 0;
1873 while (paren_not_balanced || *l != ',')
1874 {
1875 if (*l == END_OF_INSN)
1876 {
1877 if (paren_not_balanced)
1878 {
1879 if (!intel_syntax)
1880 as_bad (_("unbalanced parenthesis in operand %d."),
1881 i.operands + 1);
1882 else
1883 as_bad (_("unbalanced brackets in operand %d."),
1884 i.operands + 1);
1885 return NULL;
1886 }
1887 else
1888 break; /* we are done */
1889 }
1890 else if (!is_operand_char (*l) && !is_space_char (*l))
1891 {
1892 as_bad (_("invalid character %s in operand %d"),
1893 output_invalid (*l),
1894 i.operands + 1);
1895 return NULL;
1896 }
1897 if (!intel_syntax)
1898 {
1899 if (*l == '(')
1900 ++paren_not_balanced;
1901 if (*l == ')')
1902 --paren_not_balanced;
1903 }
1904 else
1905 {
1906 if (*l == '[')
1907 ++paren_not_balanced;
1908 if (*l == ']')
1909 --paren_not_balanced;
1910 }
1911 l++;
1912 }
1913 if (l != token_start)
1914 { /* Yes, we've read in another operand. */
1915 unsigned int operand_ok;
1916 this_operand = i.operands++;
1917 if (i.operands > MAX_OPERANDS)
1918 {
1919 as_bad (_("spurious operands; (%d operands/instruction max)"),
1920 MAX_OPERANDS);
1921 return NULL;
1922 }
1923 /* Now parse operand adding info to 'i' as we go along. */
1924 END_STRING_AND_SAVE (l);
1925
1926 if (intel_syntax)
1927 operand_ok =
1928 i386_intel_operand (token_start,
1929 intel_float_operand (mnemonic));
1930 else
1931 operand_ok = i386_operand (token_start);
1932
1933 RESTORE_END_STRING (l);
1934 if (!operand_ok)
1935 return NULL;
1936 }
1937 else
1938 {
1939 if (expecting_operand)
1940 {
1941 expecting_operand_after_comma:
1942 as_bad (_("expecting operand after ','; got nothing"));
1943 return NULL;
1944 }
1945 if (*l == ',')
1946 {
1947 as_bad (_("expecting operand before ','; got nothing"));
1948 return NULL;
1949 }
1950 }
7f3f1ea2 1951
29b0f896
AM		 1952 /* Now *l must be either ',' or END_OF_INSN. */
1953 if (*l == ',')
1954 {
1955 if (*++l == END_OF_INSN)
1956 {
1957 /* Just skip it, if it's \n complain. */
1958 goto expecting_operand_after_comma;
1959 }
1960 expecting_operand = 1;
1961 }
1962 }
1963 return l;
1964}
7f3f1ea2 1965
29b0f896
AM		 1966static void
1967swap_operands ()
1968{
1969 union i386_op temp_op;
1970 unsigned int temp_type;
f86103b7 1971 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1972 int xchg1 = 0;
1973 int xchg2 = 0;
252b5132 1974
29b0f896
AM		 1975 if (i.operands == 2)
1976 {
1977 xchg1 = 0;
1978 xchg2 = 1;
1979 }
1980 else if (i.operands == 3)
1981 {
1982 xchg1 = 0;
1983 xchg2 = 2;
1984 }
1985 temp_type = i.types[xchg2];
1986 i.types[xchg2] = i.types[xchg1];
1987 i.types[xchg1] = temp_type;
1988 temp_op = i.op[xchg2];
1989 i.op[xchg2] = i.op[xchg1];
1990 i.op[xchg1] = temp_op;
1991 temp_reloc = i.reloc[xchg2];
1992 i.reloc[xchg2] = i.reloc[xchg1];
1993 i.reloc[xchg1] = temp_reloc;
1994
1995 if (i.mem_operands == 2)
1996 {
1997 const seg_entry *temp_seg;
1998 temp_seg = i.seg[0];
1999 i.seg[0] = i.seg[1];
2000 i.seg[1] = temp_seg;
2001 }
2002}
252b5132 2003
29b0f896
AM		 2004/* Try to ensure constant immediates are represented in the smallest
2005 opcode possible. */
2006static void
2007optimize_imm ()
2008{
2009 char guess_suffix = 0;
2010 int op;
252b5132 2011
29b0f896
AM		 2012 if (i.suffix)
2013 guess_suffix = i.suffix;
2014 else if (i.reg_operands)
2015 {
2016 /* Figure out a suffix from the last register operand specified.
2017 We can't do this properly yet, ie. excluding InOutPortReg,
2018 but the following works for instructions with immediates.
2019 In any case, we can't set i.suffix yet. */
2020 for (op = i.operands; --op >= 0;)
2021 if (i.types[op] & Reg)
252b5132 2022 {
29b0f896
AM		 2023 if (i.types[op] & Reg8)
2024 guess_suffix = BYTE_MNEM_SUFFIX;
2025 else if (i.types[op] & Reg16)
2026 guess_suffix = WORD_MNEM_SUFFIX;
2027 else if (i.types[op] & Reg32)
2028 guess_suffix = LONG_MNEM_SUFFIX;
2029 else if (i.types[op] & Reg64)
2030 guess_suffix = QWORD_MNEM_SUFFIX;
2031 break;
252b5132 2032 }
29b0f896
AM		 2033 }
2034 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2035 guess_suffix = WORD_MNEM_SUFFIX;
2036
2037 for (op = i.operands; --op >= 0;)
2038 if (i.types[op] & Imm)
2039 {
2040 switch (i.op[op].imms->X_op)
252b5132 2041 {
29b0f896
AM		 2042 case O_constant:
2043 /* If a suffix is given, this operand may be shortened. */
2044 switch (guess_suffix)
252b5132 2045 {
29b0f896
AM		 2046 case LONG_MNEM_SUFFIX:
2047 i.types[op] |= Imm32 | Imm64;
2048 break;
2049 case WORD_MNEM_SUFFIX:
2050 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2051 break;
2052 case BYTE_MNEM_SUFFIX:
2053 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2054 break;
252b5132 2055 }
252b5132 2056
29b0f896
AM		 2057 /* If this operand is at most 16 bits, convert it
2058 to a signed 16 bit number before trying to see
2059 whether it will fit in an even smaller size.
2060 This allows a 16-bit operand such as $0xffe0 to
2061 be recognised as within Imm8S range. */
2062 if ((i.types[op] & Imm16)
2063 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2064 {
29b0f896
AM		 2065 i.op[op].imms->X_add_number =
2066 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2067 }
2068 if ((i.types[op] & Imm32)
2069 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2070 == 0))
2071 {
2072 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2073 ^ ((offsetT) 1 << 31))
2074 - ((offsetT) 1 << 31));
2075 }
2076 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2077
29b0f896
AM		 2078 /* We must avoid matching of Imm32 templates when 64bit
2079 only immediate is available. */
2080 if (guess_suffix == QWORD_MNEM_SUFFIX)
2081 i.types[op] &= ~Imm32;
2082 break;
252b5132 2083
29b0f896
AM		 2084 case O_absent:
2085 case O_register:
2086 abort ();
2087
2088 /* Symbols and expressions. */
2089 default:
2090 /* Convert symbolic operand to proper sizes for matching. */
2091 switch (guess_suffix)
2092 {
2093 case QWORD_MNEM_SUFFIX:
3956db08 2094 i.types[op] &= Imm64 | Imm32S;
29b0f896
AM		 2095 break;
2096 case LONG_MNEM_SUFFIX:
3956db08 2097 i.types[op] &= Imm32;
29b0f896
AM		 2098 break;
2099 case WORD_MNEM_SUFFIX:
3956db08 2100 i.types[op] &= Imm16;
29b0f896
AM		 2101 break;
2102 case BYTE_MNEM_SUFFIX:
3956db08 2103 i.types[op] &= Imm8 | Imm8S;
29b0f896 2104 break;
252b5132 2105 }
29b0f896 2106 break;
252b5132 2107 }
29b0f896
AM		 2108 }
2109}
47926f60 2110
29b0f896
AM		 2111/* Try to use the smallest displacement type too. */
2112static void
2113optimize_disp ()
2114{
2115 int op;
3e73aa7c 2116
29b0f896 2117 for (op = i.operands; --op >= 0;)
b300c311 2118 if (i.types[op] & Disp)
252b5132 2119 {
b300c311 2120 if (i.op[op].disps->X_op == O_constant)
252b5132 2121 {
b300c311 2122 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2123
b300c311
L		 2124 if ((i.types[op] & Disp16)
2125 && (disp & ~(offsetT) 0xffff) == 0)
2126 {
2127 /* If this operand is at most 16 bits, convert
2128 to a signed 16 bit number and don't use 64bit
2129 displacement. */
2130 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2131 i.types[op] &= ~Disp64;
2132 }
2133 if ((i.types[op] & Disp32)
2134 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2135 {
2136 /* If this operand is at most 32 bits, convert
2137 to a signed 32 bit number and don't use 64bit
2138 displacement. */
2139 disp &= (((offsetT) 2 << 31) - 1);
2140 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2141 i.types[op] &= ~Disp64;
2142 }
2143 if (!disp && (i.types[op] & BaseIndex))
2144 {
2145 i.types[op] &= ~Disp;
2146 i.op[op].disps = 0;
2147 i.disp_operands--;
2148 }
2149 else if (flag_code == CODE_64BIT)
2150 {
2151 if (fits_in_signed_long (disp))
28a9d8f5
L		 2152 {
2153 i.types[op] &= ~Disp64;
2154 i.types[op] |= Disp32S;
2155 }
b300c311
L		 2156 if (fits_in_unsigned_long (disp))
2157 i.types[op] |= Disp32;
2158 }
2159 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2160 && fits_in_signed_byte (disp))
2161 i.types[op] |= Disp8;
252b5132 2162 }
b300c311
L		 2163 else
2164 /* We only support 64bit displacement on constants. */
2165 i.types[op] &= ~Disp64;
252b5132 2166 }
29b0f896
AM		 2167}
2168
2169static int
2170match_template ()
2171{
2172 /* Points to template once we've found it. */
2173 const template *t;
2174 unsigned int overlap0, overlap1, overlap2;
2175 unsigned int found_reverse_match;
2176 int suffix_check;
2177
2178#define MATCH(overlap, given, template) \
2179 ((overlap & ~JumpAbsolute) \
2180 && (((given) & (BaseIndex | JumpAbsolute)) \
2181 == ((overlap) & (BaseIndex | JumpAbsolute))))
2182
2183 /* If given types r0 and r1 are registers they must be of the same type
2184 unless the expected operand type register overlap is null.
2185 Note that Acc in a template matches every size of reg. */
2186#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2187 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2188 || ((g0) & Reg) == ((g1) & Reg) \
2189 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2190
2191 overlap0 = 0;
2192 overlap1 = 0;
2193 overlap2 = 0;
2194 found_reverse_match = 0;
2195 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2196 ? No_bSuf
2197 : (i.suffix == WORD_MNEM_SUFFIX
2198 ? No_wSuf
2199 : (i.suffix == SHORT_MNEM_SUFFIX
2200 ? No_sSuf
2201 : (i.suffix == LONG_MNEM_SUFFIX
2202 ? No_lSuf
2203 : (i.suffix == QWORD_MNEM_SUFFIX
2204 ? No_qSuf
2205 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2206 ? No_xSuf : 0))))));
2207
20f0a1fc
NC		 2208 t = current_templates->start;
2209 if (i.suffix == QWORD_MNEM_SUFFIX
2210 && flag_code != CODE_64BIT
9306ca4a
JB		 2211 && (intel_syntax
2212 ? !(t->opcode_modifier & IgnoreSize)
2213 && !intel_float_operand (t->name)
2214 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2215 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2216 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2217 && (t->base_opcode != 0x0fc7
2218 || t->extension_opcode != 1 /* cmpxchg8b */))
2219 t = current_templates->end;
2220 for (; t < current_templates->end; t++)
29b0f896
AM		 2221 {
2222 /* Must have right number of operands. */
2223 if (i.operands != t->operands)
2224 continue;
2225
2226 /* Check the suffix, except for some instructions in intel mode. */
2227 if ((t->opcode_modifier & suffix_check)
2228 && !(intel_syntax
9306ca4a 2229 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2230 continue;
2231
2232 /* Do not verify operands when there are none. */
2233 else if (!t->operands)
2234 {
2235 if (t->cpu_flags & ~cpu_arch_flags)
2236 continue;
2237 /* We've found a match; break out of loop. */
2238 break;
2239 }
252b5132 2240
29b0f896
AM		 2241 overlap0 = i.types[0] & t->operand_types[0];
2242 switch (t->operands)
2243 {
2244 case 1:
2245 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2246 continue;
2247 break;
2248 case 2:
2249 case 3:
2250 overlap1 = i.types[1] & t->operand_types[1];
2251 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2252 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2253 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2254 t->operand_types[0],
2255 overlap1, i.types[1],
2256 t->operand_types[1]))
2257 {
2258 /* Check if other direction is valid ... */
2259 if ((t->opcode_modifier & (D | FloatD)) == 0)
2260 continue;
2261
2262 /* Try reversing direction of operands. */
2263 overlap0 = i.types[0] & t->operand_types[1];
2264 overlap1 = i.types[1] & t->operand_types[0];
2265 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2266 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2267 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2268 t->operand_types[1],
2269 overlap1, i.types[1],
2270 t->operand_types[0]))
2271 {
2272 /* Does not match either direction. */
2273 continue;
2274 }
2275 /* found_reverse_match holds which of D or FloatDR
2276 we've found. */
2277 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2278 }
2279 /* Found a forward 2 operand match here. */
2280 else if (t->operands == 3)
2281 {
2282 /* Here we make use of the fact that there are no
2283 reverse match 3 operand instructions, and all 3
2284 operand instructions only need to be checked for
2285 register consistency between operands 2 and 3. */
2286 overlap2 = i.types[2] & t->operand_types[2];
2287 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2288 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2289 t->operand_types[1],
2290 overlap2, i.types[2],
2291 t->operand_types[2]))
2292
2293 continue;
2294 }
2295 /* Found either forward/reverse 2 or 3 operand match here:
2296 slip through to break. */
2297 }
2298 if (t->cpu_flags & ~cpu_arch_flags)
2299 {
2300 found_reverse_match = 0;
2301 continue;
2302 }
2303 /* We've found a match; break out of loop. */
2304 break;
2305 }
2306
2307 if (t == current_templates->end)
2308 {
2309 /* We found no match. */
2310 as_bad (_("suffix or operands invalid for `%s'"),
2311 current_templates->start->name);
2312 return 0;
2313 }
252b5132 2314
29b0f896
AM		 2315 if (!quiet_warnings)
2316 {
2317 if (!intel_syntax
2318 && ((i.types[0] & JumpAbsolute)
2319 != (t->operand_types[0] & JumpAbsolute)))
2320 {
2321 as_warn (_("indirect %s without `*'"), t->name);
2322 }
2323
2324 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2325 == (IsPrefix | IgnoreSize))
2326 {
2327 /* Warn them that a data or address size prefix doesn't
2328 affect assembly of the next line of code. */
2329 as_warn (_("stand-alone `%s' prefix"), t->name);
2330 }
2331 }
2332
2333 /* Copy the template we found. */
2334 i.tm = *t;
2335 if (found_reverse_match)
2336 {
2337 /* If we found a reverse match we must alter the opcode
2338 direction bit. found_reverse_match holds bits to change
2339 (different for int & float insns). */
2340
2341 i.tm.base_opcode ^= found_reverse_match;
2342
2343 i.tm.operand_types[0] = t->operand_types[1];
2344 i.tm.operand_types[1] = t->operand_types[0];
2345 }
2346
2347 return 1;
2348}
2349
2350static int
2351check_string ()
2352{
2353 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2354 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2355 {
2356 if (i.seg[0] != NULL && i.seg[0] != &es)
2357 {
2358 as_bad (_("`%s' operand %d must use `%%es' segment"),
2359 i.tm.name,
2360 mem_op + 1);
2361 return 0;
2362 }
2363 /* There's only ever one segment override allowed per instruction.
2364 This instruction possibly has a legal segment override on the
2365 second operand, so copy the segment to where non-string
2366 instructions store it, allowing common code. */
2367 i.seg[0] = i.seg[1];
2368 }
2369 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2370 {
2371 if (i.seg[1] != NULL && i.seg[1] != &es)
2372 {
2373 as_bad (_("`%s' operand %d must use `%%es' segment"),
2374 i.tm.name,
2375 mem_op + 2);
2376 return 0;
2377 }
2378 }
2379 return 1;
2380}
2381
2382static int
543613e9 2383process_suffix (void)
29b0f896
AM		 2384{
2385 /* If matched instruction specifies an explicit instruction mnemonic
2386 suffix, use it. */
2387 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2388 {
2389 if (i.tm.opcode_modifier & Size16)
2390 i.suffix = WORD_MNEM_SUFFIX;
2391 else if (i.tm.opcode_modifier & Size64)
2392 i.suffix = QWORD_MNEM_SUFFIX;
2393 else
2394 i.suffix = LONG_MNEM_SUFFIX;
2395 }
2396 else if (i.reg_operands)
2397 {
2398 /* If there's no instruction mnemonic suffix we try to invent one
2399 based on register operands. */
2400 if (!i.suffix)
2401 {
2402 /* We take i.suffix from the last register operand specified,
2403 Destination register type is more significant than source
2404 register type. */
2405 int op;
543613e9 2406
29b0f896
AM		 2407 for (op = i.operands; --op >= 0;)
2408 if ((i.types[op] & Reg)
2409 && !(i.tm.operand_types[op] & InOutPortReg))
2410 {
2411 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2412 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2413 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2414 LONG_MNEM_SUFFIX);
2415 break;
2416 }
2417 }
2418 else if (i.suffix == BYTE_MNEM_SUFFIX)
2419 {
2420 if (!check_byte_reg ())
2421 return 0;
2422 }
2423 else if (i.suffix == LONG_MNEM_SUFFIX)
2424 {
2425 if (!check_long_reg ())
2426 return 0;
2427 }
2428 else if (i.suffix == QWORD_MNEM_SUFFIX)
2429 {
2430 if (!check_qword_reg ())
2431 return 0;
2432 }
2433 else if (i.suffix == WORD_MNEM_SUFFIX)
2434 {
2435 if (!check_word_reg ())
2436 return 0;
2437 }
2438 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2439 /* Do nothing if the instruction is going to ignore the prefix. */
2440 ;
2441 else
2442 abort ();
2443 }
9306ca4a
JB		 2444 else if ((i.tm.opcode_modifier & DefaultSize)
2445 && !i.suffix
2446 /* exclude fldenv/frstor/fsave/fstenv */
2447 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2448 {
2449 i.suffix = stackop_size;
2450 }
9306ca4a
JB		 2451 else if (intel_syntax
2452 && !i.suffix
2453 && ((i.tm.operand_types[0] & JumpAbsolute)
2454 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2455 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2456 && i.tm.extension_opcode <= 3)))
2457 {
2458 switch (flag_code)
2459 {
2460 case CODE_64BIT:
2461 if (!(i.tm.opcode_modifier & No_qSuf))
2462 {
2463 i.suffix = QWORD_MNEM_SUFFIX;
2464 break;
2465 }
2466 case CODE_32BIT:
2467 if (!(i.tm.opcode_modifier & No_lSuf))
2468 i.suffix = LONG_MNEM_SUFFIX;
2469 break;
2470 case CODE_16BIT:
2471 if (!(i.tm.opcode_modifier & No_wSuf))
2472 i.suffix = WORD_MNEM_SUFFIX;
2473 break;
2474 }
2475 }
252b5132 2476
9306ca4a 2477 if (!i.suffix)
29b0f896 2478 {
9306ca4a
JB		 2479 if (!intel_syntax)
2480 {
2481 if (i.tm.opcode_modifier & W)
2482 {
2483 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2484 return 0;
2485 }
2486 }
2487 else
2488 {
2489 unsigned int suffixes = ~i.tm.opcode_modifier
2490 & (No_bSuf
2491 | No_wSuf
2492 | No_lSuf
2493 | No_sSuf
2494 | No_xSuf
2495 | No_qSuf);
2496
2497 if ((i.tm.opcode_modifier & W)
2498 || ((suffixes & (suffixes - 1))
2499 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2500 {
2501 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2502 return 0;
2503 }
2504 }
29b0f896 2505 }
252b5132 2506
9306ca4a
JB		 2507 /* Change the opcode based on the operand size given by i.suffix;
2508 We don't need to change things for byte insns. */
2509
29b0f896
AM		 2510 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2511 {
2512 /* It's not a byte, select word/dword operation. */
2513 if (i.tm.opcode_modifier & W)
2514 {
2515 if (i.tm.opcode_modifier & ShortForm)
2516 i.tm.base_opcode |= 8;
2517 else
2518 i.tm.base_opcode |= 1;
2519 }
0f3f3d8b 2520
29b0f896
AM		 2521 /* Now select between word & dword operations via the operand
2522 size prefix, except for instructions that will ignore this
2523 prefix anyway. */
2524 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2525 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2526 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2527 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2528 || (flag_code == CODE_64BIT
2529 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2530 {
2531 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2532
29b0f896
AM		 2533 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2534 prefix = ADDR_PREFIX_OPCODE;
252b5132 2535
29b0f896
AM		 2536 if (!add_prefix (prefix))
2537 return 0;
24eab124 2538 }
252b5132 2539
29b0f896
AM		 2540 /* Set mode64 for an operand. */
2541 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2542 && flag_code == CODE_64BIT
29b0f896 2543 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2544 i.rex |= REX_MODE64;
3e73aa7c 2545
29b0f896
AM		 2546 /* Size floating point instruction. */
2547 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2548 if (i.tm.opcode_modifier & FloatMF)
2549 i.tm.base_opcode ^= 4;
29b0f896 2550 }
7ecd2f8b 2551
29b0f896
AM		 2552 return 1;
2553}
3e73aa7c 2554
29b0f896 2555static int
543613e9 2556check_byte_reg (void)
29b0f896
AM		 2557{
2558 int op;
543613e9 2559
29b0f896
AM		 2560 for (op = i.operands; --op >= 0;)
2561 {
2562 /* If this is an eight bit register, it's OK. If it's the 16 or
2563 32 bit version of an eight bit register, we will just use the
2564 low portion, and that's OK too. */
2565 if (i.types[op] & Reg8)
2566 continue;
2567
2568 /* movzx and movsx should not generate this warning. */
2569 if (intel_syntax
2570 && (i.tm.base_opcode == 0xfb7
2571 || i.tm.base_opcode == 0xfb6
2572 || i.tm.base_opcode == 0x63
2573 || i.tm.base_opcode == 0xfbe
2574 || i.tm.base_opcode == 0xfbf))
2575 continue;
2576
65ec77d2 2577 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2578 {
2579 /* Prohibit these changes in the 64bit mode, since the
2580 lowering is more complicated. */
2581 if (flag_code == CODE_64BIT
2582 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2583 {
0f3f3d8b 2584 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2585 i.op[op].regs->reg_name,
2586 i.suffix);
2587 return 0;
2588 }
2589#if REGISTER_WARNINGS
2590 if (!quiet_warnings
2591 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2592 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2593 (i.op[op].regs + (i.types[op] & Reg16
2594 ? REGNAM_AL - REGNAM_AX
2595 : REGNAM_AL - REGNAM_EAX))->reg_name,
2596 i.op[op].regs->reg_name,
2597 i.suffix);
2598#endif
2599 continue;
2600 }
2601 /* Any other register is bad. */
2602 if (i.types[op] & (Reg | RegMMX | RegXMM
2603 | SReg2 | SReg3
2604 | Control | Debug | Test
2605 | FloatReg | FloatAcc))
2606 {
2607 as_bad (_("`%%%s' not allowed with `%s%c'"),
2608 i.op[op].regs->reg_name,
2609 i.tm.name,
2610 i.suffix);
2611 return 0;
2612 }
2613 }
2614 return 1;
2615}
2616
2617static int
2618check_long_reg ()
2619{
2620 int op;
2621
2622 for (op = i.operands; --op >= 0;)
2623 /* Reject eight bit registers, except where the template requires
2624 them. (eg. movzb) */
2625 if ((i.types[op] & Reg8) != 0
2626 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2627 {
2628 as_bad (_("`%%%s' not allowed with `%s%c'"),
2629 i.op[op].regs->reg_name,
2630 i.tm.name,
2631 i.suffix);
2632 return 0;
2633 }
2634 /* Warn if the e prefix on a general reg is missing. */
2635 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2636 && (i.types[op] & Reg16) != 0
2637 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2638 {
2639 /* Prohibit these changes in the 64bit mode, since the
2640 lowering is more complicated. */
2641 if (flag_code == CODE_64BIT)
252b5132 2642 {
0f3f3d8b 2643 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2644 i.op[op].regs->reg_name,
2645 i.suffix);
2646 return 0;
252b5132 2647 }
29b0f896
AM		 2648#if REGISTER_WARNINGS
2649 else
2650 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2651 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2652 i.op[op].regs->reg_name,
2653 i.suffix);
2654#endif
252b5132 2655 }
29b0f896
AM		 2656 /* Warn if the r prefix on a general reg is missing. */
2657 else if ((i.types[op] & Reg64) != 0
2658 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2659 {
0f3f3d8b 2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2661 i.op[op].regs->reg_name,
2662 i.suffix);
2663 return 0;
2664 }
2665 return 1;
2666}
252b5132 2667
29b0f896
AM		 2668static int
2669check_qword_reg ()
2670{
2671 int op;
252b5132 2672
29b0f896
AM		 2673 for (op = i.operands; --op >= 0; )
2674 /* Reject eight bit registers, except where the template requires
2675 them. (eg. movzb) */
2676 if ((i.types[op] & Reg8) != 0
2677 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2678 {
2679 as_bad (_("`%%%s' not allowed with `%s%c'"),
2680 i.op[op].regs->reg_name,
2681 i.tm.name,
2682 i.suffix);
2683 return 0;
2684 }
2685 /* Warn if the e prefix on a general reg is missing. */
2686 else if (((i.types[op] & Reg16) != 0
2687 || (i.types[op] & Reg32) != 0)
2688 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2689 {
2690 /* Prohibit these changes in the 64bit mode, since the
2691 lowering is more complicated. */
0f3f3d8b 2692 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2693 i.op[op].regs->reg_name,
2694 i.suffix);
2695 return 0;
252b5132 2696 }
29b0f896
AM		 2697 return 1;
2698}
252b5132 2699
29b0f896
AM		 2700static int
2701check_word_reg ()
2702{
2703 int op;
2704 for (op = i.operands; --op >= 0;)
2705 /* Reject eight bit registers, except where the template requires
2706 them. (eg. movzb) */
2707 if ((i.types[op] & Reg8) != 0
2708 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2709 {
2710 as_bad (_("`%%%s' not allowed with `%s%c'"),
2711 i.op[op].regs->reg_name,
2712 i.tm.name,
2713 i.suffix);
2714 return 0;
2715 }
2716 /* Warn if the e prefix on a general reg is present. */
2717 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2718 && (i.types[op] & Reg32) != 0
2719 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2720 {
29b0f896
AM		 2721 /* Prohibit these changes in the 64bit mode, since the
2722 lowering is more complicated. */
2723 if (flag_code == CODE_64BIT)
252b5132 2724 {
0f3f3d8b 2725 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2726 i.op[op].regs->reg_name,
2727 i.suffix);
2728 return 0;
252b5132 2729 }
29b0f896
AM		 2730 else
2731#if REGISTER_WARNINGS
2732 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2733 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2734 i.op[op].regs->reg_name,
2735 i.suffix);
2736#endif
2737 }
2738 return 1;
2739}
252b5132 2740
29b0f896
AM		 2741static int
2742finalize_imm ()
2743{
2744 unsigned int overlap0, overlap1, overlap2;
2745
2746 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2747 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2748 && overlap0 != Imm8 && overlap0 != Imm8S
2749 && overlap0 != Imm16 && overlap0 != Imm32S
2750 && overlap0 != Imm32 && overlap0 != Imm64)
2751 {
2752 if (i.suffix)
2753 {
2754 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2755 ? Imm8 | Imm8S
2756 : (i.suffix == WORD_MNEM_SUFFIX
2757 ? Imm16
2758 : (i.suffix == QWORD_MNEM_SUFFIX
2759 ? Imm64 | Imm32S
2760 : Imm32)));
2761 }
2762 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2763 || overlap0 == (Imm16 | Imm32)
2764 || overlap0 == (Imm16 | Imm32S))
2765 {
2766 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2767 ? Imm16 : Imm32S);
2768 }
2769 if (overlap0 != Imm8 && overlap0 != Imm8S
2770 && overlap0 != Imm16 && overlap0 != Imm32S
2771 && overlap0 != Imm32 && overlap0 != Imm64)
2772 {
2773 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2774 return 0;
2775 }
2776 }
2777 i.types[0] = overlap0;
2778
2779 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2780 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2781 && overlap1 != Imm8 && overlap1 != Imm8S
2782 && overlap1 != Imm16 && overlap1 != Imm32S
2783 && overlap1 != Imm32 && overlap1 != Imm64)
2784 {
2785 if (i.suffix)
2786 {
2787 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2788 ? Imm8 | Imm8S
2789 : (i.suffix == WORD_MNEM_SUFFIX
2790 ? Imm16
2791 : (i.suffix == QWORD_MNEM_SUFFIX
2792 ? Imm64 | Imm32S
2793 : Imm32)));
2794 }
2795 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2796 || overlap1 == (Imm16 | Imm32)
2797 || overlap1 == (Imm16 | Imm32S))
2798 {
2799 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2800 ? Imm16 : Imm32S);
2801 }
2802 if (overlap1 != Imm8 && overlap1 != Imm8S
2803 && overlap1 != Imm16 && overlap1 != Imm32S
2804 && overlap1 != Imm32 && overlap1 != Imm64)
2805 {
2806 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2807 return 0;
2808 }
2809 }
2810 i.types[1] = overlap1;
2811
2812 overlap2 = i.types[2] & i.tm.operand_types[2];
2813 assert ((overlap2 & Imm) == 0);
2814 i.types[2] = overlap2;
2815
2816 return 1;
2817}
2818
2819static int
2820process_operands ()
2821{
2822 /* Default segment register this instruction will use for memory
2823 accesses. 0 means unknown. This is only for optimizing out
2824 unnecessary segment overrides. */
2825 const seg_entry *default_seg = 0;
2826
2827 /* The imul $imm, %reg instruction is converted into
2828 imul $imm, %reg, %reg, and the clr %reg instruction
2829 is converted into xor %reg, %reg. */
2830 if (i.tm.opcode_modifier & regKludge)
2831 {
2832 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2833 /* Pretend we saw the extra register operand. */
2834 assert (i.op[first_reg_op + 1].regs == 0);
2835 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2836 i.types[first_reg_op + 1] = i.types[first_reg_op];
2837 i.reg_operands = 2;
2838 }
2839
2840 if (i.tm.opcode_modifier & ShortForm)
2841 {
2842 /* The register or float register operand is in operand 0 or 1. */
2843 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2844 /* Register goes in low 3 bits of opcode. */
2845 i.tm.base_opcode |= i.op[op].regs->reg_num;
2846 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2847 i.rex |= REX_EXTZ;
2848 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2849 {
2850 /* Warn about some common errors, but press on regardless.
2851 The first case can be generated by gcc (<= 2.8.1). */
2852 if (i.operands == 2)
2853 {
2854 /* Reversed arguments on faddp, fsubp, etc. */
2855 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2856 i.op[1].regs->reg_name,
2857 i.op[0].regs->reg_name);
2858 }
2859 else
2860 {
2861 /* Extraneous `l' suffix on fp insn. */
2862 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2863 i.op[0].regs->reg_name);
2864 }
2865 }
2866 }
2867 else if (i.tm.opcode_modifier & Modrm)
2868 {
2869 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2870 must be put into the modrm byte). Now, we make the modrm and
2871 index base bytes based on all the info we've collected. */
29b0f896
AM		 2872
2873 default_seg = build_modrm_byte ();
2874 }
2875 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2876 {
2877 if (i.tm.base_opcode == POP_SEG_SHORT
2878 && i.op[0].regs->reg_num == 1)
2879 {
2880 as_bad (_("you can't `pop %%cs'"));
2881 return 0;
2882 }
2883 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2884 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2885 i.rex |= REX_EXTZ;
2886 }
2887 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2888 {
2889 default_seg = &ds;
2890 }
2891 else if ((i.tm.opcode_modifier & IsString) != 0)
2892 {
2893 /* For the string instructions that allow a segment override
2894 on one of their operands, the default segment is ds. */
2895 default_seg = &ds;
2896 }
2897
30123838
JB		 2898 if ((i.tm.base_opcode == 0x8d /* lea */
2899 || (i.tm.cpu_flags & CpuSVME))
2900 && i.seg[0] && !quiet_warnings)
2901 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2902
2903 /* If a segment was explicitly specified, and the specified segment
2904 is not the default, use an opcode prefix to select it. If we
2905 never figured out what the default segment is, then default_seg
2906 will be zero at this point, and the specified segment prefix will
2907 always be used. */
29b0f896
AM		 2908 if ((i.seg[0]) && (i.seg[0] != default_seg))
2909 {
2910 if (!add_prefix (i.seg[0]->seg_prefix))
2911 return 0;
2912 }
2913 return 1;
2914}
2915
2916static const seg_entry *
2917build_modrm_byte ()
2918{
2919 const seg_entry *default_seg = 0;
2920
2921 /* i.reg_operands MUST be the number of real register operands;
2922 implicit registers do not count. */
2923 if (i.reg_operands == 2)
2924 {
2925 unsigned int source, dest;
2926 source = ((i.types[0]
2927 & (Reg | RegMMX | RegXMM
2928 | SReg2 | SReg3
2929 | Control | Debug | Test))
2930 ? 0 : 1);
2931 dest = source + 1;
2932
2933 i.rm.mode = 3;
2934 /* One of the register operands will be encoded in the i.tm.reg
2935 field, the other in the combined i.tm.mode and i.tm.regmem
2936 fields. If no form of this instruction supports a memory
2937 destination operand, then we assume the source operand may
2938 sometimes be a memory operand and so we need to store the
2939 destination in the i.rm.reg field. */
2940 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2941 {
2942 i.rm.reg = i.op[dest].regs->reg_num;
2943 i.rm.regmem = i.op[source].regs->reg_num;
2944 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2945 i.rex |= REX_EXTX;
2946 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2947 i.rex |= REX_EXTZ;
2948 }
2949 else
2950 {
2951 i.rm.reg = i.op[source].regs->reg_num;
2952 i.rm.regmem = i.op[dest].regs->reg_num;
2953 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2954 i.rex |= REX_EXTZ;
2955 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2956 i.rex |= REX_EXTX;
2957 }
c4a530c5
JB		 2958 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2959 {
2960 if (!((i.types[0] | i.types[1]) & Control))
2961 abort ();
2962 i.rex &= ~(REX_EXTX | REX_EXTZ);
2963 add_prefix (LOCK_PREFIX_OPCODE);
2964 }
29b0f896
AM		 2965 }
2966 else
2967 { /* If it's not 2 reg operands... */
2968 if (i.mem_operands)
2969 {
2970 unsigned int fake_zero_displacement = 0;
2971 unsigned int op = ((i.types[0] & AnyMem)
2972 ? 0
2973 : (i.types[1] & AnyMem) ? 1 : 2);
2974
2975 default_seg = &ds;
2976
2977 if (i.base_reg == 0)
2978 {
2979 i.rm.mode = 0;
2980 if (!i.disp_operands)
2981 fake_zero_displacement = 1;
2982 if (i.index_reg == 0)
2983 {
2984 /* Operand is just <disp> */
20f0a1fc 2985 if (flag_code == CODE_64BIT)
29b0f896
AM		 2986 {
2987 /* 64bit mode overwrites the 32bit absolute
2988 addressing by RIP relative addressing and
2989 absolute addressing is encoded by one of the
2990 redundant SIB forms. */
2991 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2992 i.sib.base = NO_BASE_REGISTER;
2993 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 2994 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2995 }
2996 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2997 {
2998 i.rm.regmem = NO_BASE_REGISTER_16;
2999 i.types[op] = Disp16;
3000 }
3001 else
3002 {
3003 i.rm.regmem = NO_BASE_REGISTER;
3004 i.types[op] = Disp32;
29b0f896
AM		 3005 }
3006 }
3007 else /* !i.base_reg && i.index_reg */
3008 {
3009 i.sib.index = i.index_reg->reg_num;
3010 i.sib.base = NO_BASE_REGISTER;
3011 i.sib.scale = i.log2_scale_factor;
3012 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3013 i.types[op] &= ~Disp;
3014 if (flag_code != CODE_64BIT)
3015 i.types[op] |= Disp32; /* Must be 32 bit */
3016 else
3017 i.types[op] |= Disp32S;
3018 if ((i.index_reg->reg_flags & RegRex) != 0)
3019 i.rex |= REX_EXTY;
3020 }
3021 }
3022 /* RIP addressing for 64bit mode. */
3023 else if (i.base_reg->reg_type == BaseIndex)
3024 {
3025 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3026 i.types[op] &= ~ Disp;
29b0f896
AM		 3027 i.types[op] |= Disp32S;
3028 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3029 if (! i.disp_operands)
3030 fake_zero_displacement = 1;
29b0f896
AM		 3031 }
3032 else if (i.base_reg->reg_type & Reg16)
3033 {
3034 switch (i.base_reg->reg_num)
3035 {
3036 case 3: /* (%bx) */
3037 if (i.index_reg == 0)
3038 i.rm.regmem = 7;
3039 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3040 i.rm.regmem = i.index_reg->reg_num - 6;
3041 break;
3042 case 5: /* (%bp) */
3043 default_seg = &ss;
3044 if (i.index_reg == 0)
3045 {
3046 i.rm.regmem = 6;
3047 if ((i.types[op] & Disp) == 0)
3048 {
3049 /* fake (%bp) into 0(%bp) */
3050 i.types[op] |= Disp8;
252b5132 3051 fake_zero_displacement = 1;
29b0f896
AM		 3052 }
3053 }
3054 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3055 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3056 break;
3057 default: /* (%si) -> 4 or (%di) -> 5 */
3058 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3059 }
3060 i.rm.mode = mode_from_disp_size (i.types[op]);
3061 }
3062 else /* i.base_reg and 32/64 bit mode */
3063 {
3064 if (flag_code == CODE_64BIT
3065 && (i.types[op] & Disp))
20f0a1fc
NC		 3066 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3067
29b0f896
AM		 3068 i.rm.regmem = i.base_reg->reg_num;
3069 if ((i.base_reg->reg_flags & RegRex) != 0)
3070 i.rex |= REX_EXTZ;
3071 i.sib.base = i.base_reg->reg_num;
3072 /* x86-64 ignores REX prefix bit here to avoid decoder
3073 complications. */
3074 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3075 {
3076 default_seg = &ss;
3077 if (i.disp_operands == 0)
3078 {
3079 fake_zero_displacement = 1;
3080 i.types[op] |= Disp8;
3081 }
3082 }
3083 else if (i.base_reg->reg_num == ESP_REG_NUM)
3084 {
3085 default_seg = &ss;
3086 }
3087 i.sib.scale = i.log2_scale_factor;
3088 if (i.index_reg == 0)
3089 {
3090 /* <disp>(%esp) becomes two byte modrm with no index
3091 register. We've already stored the code for esp
3092 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3093 Any base register besides %esp will not use the
3094 extra modrm byte. */
3095 i.sib.index = NO_INDEX_REGISTER;
3096#if !SCALE1_WHEN_NO_INDEX
3097 /* Another case where we force the second modrm byte. */
3098 if (i.log2_scale_factor)
3099 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3100#endif
29b0f896
AM		 3101 }
3102 else
3103 {
3104 i.sib.index = i.index_reg->reg_num;
3105 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3106 if ((i.index_reg->reg_flags & RegRex) != 0)
3107 i.rex |= REX_EXTY;
3108 }
3109 i.rm.mode = mode_from_disp_size (i.types[op]);
3110 }
252b5132 3111
29b0f896
AM		 3112 if (fake_zero_displacement)
3113 {
3114 /* Fakes a zero displacement assuming that i.types[op]
3115 holds the correct displacement size. */
3116 expressionS *exp;
3117
3118 assert (i.op[op].disps == 0);
3119 exp = &disp_expressions[i.disp_operands++];
3120 i.op[op].disps = exp;
3121 exp->X_op = O_constant;
3122 exp->X_add_number = 0;
3123 exp->X_add_symbol = (symbolS *) 0;
3124 exp->X_op_symbol = (symbolS *) 0;
3125 }
3126 }
252b5132 3127
29b0f896
AM		 3128 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3129 (if any) based on i.tm.extension_opcode. Again, we must be
3130 careful to make sure that segment/control/debug/test/MMX
3131 registers are coded into the i.rm.reg field. */
3132 if (i.reg_operands)
3133 {
3134 unsigned int op =
3135 ((i.types[0]
3136 & (Reg | RegMMX | RegXMM
3137 | SReg2 | SReg3
3138 | Control | Debug | Test))
3139 ? 0
3140 : ((i.types[1]
3141 & (Reg | RegMMX | RegXMM
3142 | SReg2 | SReg3
3143 | Control | Debug | Test))
3144 ? 1
3145 : 2));
3146 /* If there is an extension opcode to put here, the register
3147 number must be put into the regmem field. */
3148 if (i.tm.extension_opcode != None)
3149 {
3150 i.rm.regmem = i.op[op].regs->reg_num;
3151 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3152 i.rex |= REX_EXTZ;
3153 }
3154 else
3155 {
3156 i.rm.reg = i.op[op].regs->reg_num;
3157 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3158 i.rex |= REX_EXTX;
3159 }
252b5132 3160
29b0f896
AM		 3161 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3162 must set it to 3 to indicate this is a register operand
3163 in the regmem field. */
3164 if (!i.mem_operands)
3165 i.rm.mode = 3;
3166 }
252b5132 3167
29b0f896
AM		 3168 /* Fill in i.rm.reg field with extension opcode (if any). */
3169 if (i.tm.extension_opcode != None)
3170 i.rm.reg = i.tm.extension_opcode;
3171 }
3172 return default_seg;
3173}
252b5132 3174
29b0f896
AM		 3175static void
3176output_branch ()
3177{
3178 char *p;
3179 int code16;
3180 int prefix;
3181 relax_substateT subtype;
3182 symbolS *sym;
3183 offsetT off;
3184
3185 code16 = 0;
3186 if (flag_code == CODE_16BIT)
3187 code16 = CODE16;
3188
3189 prefix = 0;
3190 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3191 {
29b0f896
AM		 3192 prefix = 1;
3193 i.prefixes -= 1;
3194 code16 ^= CODE16;
252b5132 3195 }
29b0f896
AM		 3196 /* Pentium4 branch hints. */
3197 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3198 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3199 {
29b0f896
AM		 3200 prefix++;
3201 i.prefixes--;
3202 }
3203 if (i.prefix[REX_PREFIX] != 0)
3204 {
3205 prefix++;
3206 i.prefixes--;
2f66722d
AM		 3207 }
3208
29b0f896
AM		 3209 if (i.prefixes != 0 && !intel_syntax)
3210 as_warn (_("skipping prefixes on this instruction"));
3211
3212 /* It's always a symbol; End frag & setup for relax.
3213 Make sure there is enough room in this frag for the largest
3214 instruction we may generate in md_convert_frag. This is 2
3215 bytes for the opcode and room for the prefix and largest
3216 displacement. */
3217 frag_grow (prefix + 2 + 4);
3218 /* Prefix and 1 opcode byte go in fr_fix. */
3219 p = frag_more (prefix + 1);
3220 if (i.prefix[DATA_PREFIX] != 0)
3221 *p++ = DATA_PREFIX_OPCODE;
3222 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3223 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3224 *p++ = i.prefix[SEG_PREFIX];
3225 if (i.prefix[REX_PREFIX] != 0)
3226 *p++ = i.prefix[REX_PREFIX];
3227 *p = i.tm.base_opcode;
3228
3229 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3230 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3231 else if ((cpu_arch_flags & Cpu386) != 0)
3232 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3233 else
3234 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3235 subtype |= code16;
3e73aa7c 3236
29b0f896
AM		 3237 sym = i.op[0].disps->X_add_symbol;
3238 off = i.op[0].disps->X_add_number;
3e73aa7c 3239
29b0f896
AM		 3240 if (i.op[0].disps->X_op != O_constant
3241 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3242 {
29b0f896
AM		 3243 /* Handle complex expressions. */
3244 sym = make_expr_symbol (i.op[0].disps);
3245 off = 0;
3246 }
3e73aa7c 3247
29b0f896
AM		 3248 /* 1 possible extra opcode + 4 byte displacement go in var part.
3249 Pass reloc in fr_var. */
3250 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3251}
3e73aa7c 3252
29b0f896
AM		 3253static void
3254output_jump ()
3255{
3256 char *p;
3257 int size;
3e02c1cc 3258 fixS *fixP;
29b0f896
AM		 3259
3260 if (i.tm.opcode_modifier & JumpByte)
3261 {
3262 /* This is a loop or jecxz type instruction. */
3263 size = 1;
3264 if (i.prefix[ADDR_PREFIX] != 0)
3265 {
3266 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3267 i.prefixes -= 1;
3268 }
3269 /* Pentium4 branch hints. */
3270 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3271 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3272 {
3273 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3274 i.prefixes--;
3e73aa7c
JH		 3275 }
3276 }
29b0f896
AM		 3277 else
3278 {
3279 int code16;
3e73aa7c 3280
29b0f896
AM		 3281 code16 = 0;
3282 if (flag_code == CODE_16BIT)
3283 code16 = CODE16;
3e73aa7c 3284
29b0f896
AM		 3285 if (i.prefix[DATA_PREFIX] != 0)
3286 {
3287 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3288 i.prefixes -= 1;
3289 code16 ^= CODE16;
3290 }
252b5132 3291
29b0f896
AM		 3292 size = 4;
3293 if (code16)
3294 size = 2;
3295 }
9fcc94b6 3296
29b0f896
AM		 3297 if (i.prefix[REX_PREFIX] != 0)
3298 {
3299 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3300 i.prefixes -= 1;
3301 }
252b5132 3302
29b0f896
AM		 3303 if (i.prefixes != 0 && !intel_syntax)
3304 as_warn (_("skipping prefixes on this instruction"));
e0890092 3305
29b0f896
AM		 3306 p = frag_more (1 + size);
3307 *p++ = i.tm.base_opcode;
e0890092 3308
3e02c1cc
AM		 3309 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3310 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3311
3312 /* All jumps handled here are signed, but don't use a signed limit
3313 check for 32 and 16 bit jumps as we want to allow wrap around at
3314 4G and 64k respectively. */
3315 if (size == 1)
3316 fixP->fx_signed = 1;
29b0f896 3317}
e0890092 3318
29b0f896
AM		 3319static void
3320output_interseg_jump ()
3321{
3322 char *p;
3323 int size;
3324 int prefix;
3325 int code16;
252b5132 3326
29b0f896
AM		 3327 code16 = 0;
3328 if (flag_code == CODE_16BIT)
3329 code16 = CODE16;
a217f122 3330
29b0f896
AM		 3331 prefix = 0;
3332 if (i.prefix[DATA_PREFIX] != 0)
3333 {
3334 prefix = 1;
3335 i.prefixes -= 1;
3336 code16 ^= CODE16;
3337 }
3338 if (i.prefix[REX_PREFIX] != 0)
3339 {
3340 prefix++;
3341 i.prefixes -= 1;
3342 }
252b5132 3343
29b0f896
AM		 3344 size = 4;
3345 if (code16)
3346 size = 2;
252b5132 3347
29b0f896
AM		 3348 if (i.prefixes != 0 && !intel_syntax)
3349 as_warn (_("skipping prefixes on this instruction"));
252b5132 3350
29b0f896
AM		 3351 /* 1 opcode; 2 segment; offset */
3352 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3353
29b0f896
AM		 3354 if (i.prefix[DATA_PREFIX] != 0)
3355 *p++ = DATA_PREFIX_OPCODE;
252b5132 3356
29b0f896
AM		 3357 if (i.prefix[REX_PREFIX] != 0)
3358 *p++ = i.prefix[REX_PREFIX];
252b5132 3359
29b0f896
AM		 3360 *p++ = i.tm.base_opcode;
3361 if (i.op[1].imms->X_op == O_constant)
3362 {
3363 offsetT n = i.op[1].imms->X_add_number;
252b5132 3364
29b0f896
AM		 3365 if (size == 2
3366 && !fits_in_unsigned_word (n)
3367 && !fits_in_signed_word (n))
3368 {
3369 as_bad (_("16-bit jump out of range"));
3370 return;
3371 }
3372 md_number_to_chars (p, n, size);
3373 }
3374 else
3375 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3376 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3377 if (i.op[0].imms->X_op != O_constant)
3378 as_bad (_("can't handle non absolute segment in `%s'"),
3379 i.tm.name);
3380 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3381}
a217f122 3382
29b0f896
AM		 3383static void
3384output_insn ()
3385{
2bbd9c25
JJ		 3386 fragS *insn_start_frag;
3387 offsetT insn_start_off;
3388
29b0f896
AM		 3389 /* Tie dwarf2 debug info to the address at the start of the insn.
3390 We can't do this after the insn has been output as the current
3391 frag may have been closed off. eg. by frag_var. */
3392 dwarf2_emit_insn (0);
3393
2bbd9c25
JJ		 3394 insn_start_frag = frag_now;
3395 insn_start_off = frag_now_fix ();
3396
29b0f896
AM		 3397 /* Output jumps. */
3398 if (i.tm.opcode_modifier & Jump)
3399 output_branch ();
3400 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3401 output_jump ();
3402 else if (i.tm.opcode_modifier & JumpInterSegment)
3403 output_interseg_jump ();
3404 else
3405 {
3406 /* Output normal instructions here. */
3407 char *p;
3408 unsigned char *q;
252b5132 3409
bc4bd9ab
MK		 3410 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3411 more higher byte to specify a prefix the instruction
3412 requires. */
3413 if ((i.tm.base_opcode & 0xff0000) != 0)
3414 {
3415 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3416 {
3417 unsigned int prefix;
3418 prefix = (i.tm.base_opcode >> 16) & 0xff;
3419
3420 if (prefix != REPE_PREFIX_OPCODE
3421 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3422 add_prefix (prefix);
3423 }
3424 else
3425 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3426 }
252b5132 3427
29b0f896
AM		 3428 /* The prefix bytes. */
3429 for (q = i.prefix;
3430 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3431 q++)
3432 {
3433 if (*q)
3434 {
3435 p = frag_more (1);
3436 md_number_to_chars (p, (valueT) *q, 1);
3437 }
3438 }
252b5132 3439
29b0f896
AM		 3440 /* Now the opcode; be careful about word order here! */
3441 if (fits_in_unsigned_byte (i.tm.base_opcode))
3442 {
3443 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3444 }
3445 else
3446 {
bc4bd9ab 3447 p = frag_more (2);
0f10071e 3448
29b0f896
AM		 3449 /* Put out high byte first: can't use md_number_to_chars! */
3450 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3451 *p = i.tm.base_opcode & 0xff;
3452 }
3e73aa7c 3453
29b0f896
AM		 3454 /* Now the modrm byte and sib byte (if present). */
3455 if (i.tm.opcode_modifier & Modrm)
3456 {
3457 p = frag_more (1);
3458 md_number_to_chars (p,
3459 (valueT) (i.rm.regmem << 0
3460 | i.rm.reg << 3
3461 | i.rm.mode << 6),
3462 1);
3463 /* If i.rm.regmem == ESP (4)
3464 && i.rm.mode != (Register mode)
3465 && not 16 bit
3466 ==> need second modrm byte. */
3467 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3468 && i.rm.mode != 3
3469 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3470 {
3471 p = frag_more (1);
3472 md_number_to_chars (p,
3473 (valueT) (i.sib.base << 0
3474 | i.sib.index << 3
3475 | i.sib.scale << 6),
3476 1);
3477 }
3478 }
3e73aa7c 3479
29b0f896 3480 if (i.disp_operands)
2bbd9c25 3481 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3482
29b0f896 3483 if (i.imm_operands)
2bbd9c25 3484 output_imm (insn_start_frag, insn_start_off);
29b0f896 3485 }
252b5132 3486
29b0f896
AM		 3487#ifdef DEBUG386
3488 if (flag_debug)
3489 {
3490 pi (line, &i);
3491 }
3492#endif /* DEBUG386 */
3493}
252b5132 3494
29b0f896 3495static void
2bbd9c25
JJ		 3496output_disp (insn_start_frag, insn_start_off)
3497 fragS *insn_start_frag;
3498 offsetT insn_start_off;
29b0f896
AM		 3499{
3500 char *p;
3501 unsigned int n;
252b5132 3502
29b0f896
AM		 3503 for (n = 0; n < i.operands; n++)
3504 {
3505 if (i.types[n] & Disp)
3506 {
3507 if (i.op[n].disps->X_op == O_constant)
3508 {
3509 int size;
3510 offsetT val;
252b5132 3511
29b0f896
AM		 3512 size = 4;
3513 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3514 {
3515 size = 2;
3516 if (i.types[n] & Disp8)
3517 size = 1;
3518 if (i.types[n] & Disp64)
3519 size = 8;
3520 }
3521 val = offset_in_range (i.op[n].disps->X_add_number,
3522 size);
3523 p = frag_more (size);
3524 md_number_to_chars (p, val, size);
3525 }
3526 else
3527 {
f86103b7 3528 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3529 int size = 4;
3530 int sign = 0;
3531 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3532
3533 /* The PC relative address is computed relative
3534 to the instruction boundary, so in case immediate
3535 fields follows, we need to adjust the value. */
3536 if (pcrel && i.imm_operands)
3537 {
3538 int imm_size = 4;
3539 unsigned int n1;
252b5132 3540
29b0f896
AM		 3541 for (n1 = 0; n1 < i.operands; n1++)
3542 if (i.types[n1] & Imm)
252b5132 3543 {
29b0f896 3544 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3545 {
29b0f896
AM		 3546 imm_size = 2;
3547 if (i.types[n1] & (Imm8 | Imm8S))
3548 imm_size = 1;
3549 if (i.types[n1] & Imm64)
3550 imm_size = 8;
252b5132 3551 }
29b0f896 3552 break;
252b5132 3553 }
29b0f896
AM		 3554 /* We should find the immediate. */
3555 if (n1 == i.operands)
3556 abort ();
3557 i.op[n].disps->X_add_number -= imm_size;
3558 }
520dc8e8 3559
29b0f896
AM		 3560 if (i.types[n] & Disp32S)
3561 sign = 1;
3e73aa7c 3562
29b0f896
AM		 3563 if (i.types[n] & (Disp16 | Disp64))
3564 {
3565 size = 2;
3566 if (i.types[n] & Disp64)
3567 size = 8;
3568 }
520dc8e8 3569
29b0f896 3570 p = frag_more (size);
2bbd9c25 3571 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3572 if (GOT_symbol
2bbd9c25 3573 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3574 && (((reloc_type == BFD_RELOC_32
3575 || reloc_type == BFD_RELOC_X86_64_32S)
3576 && (i.op[n].disps->X_op == O_symbol
3577 || (i.op[n].disps->X_op == O_add
3578 && ((symbol_get_value_expression
3579 (i.op[n].disps->X_op_symbol)->X_op)
3580 == O_subtract))))
3581 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3582 {
3583 offsetT add;
3584
3585 if (insn_start_frag == frag_now)
3586 add = (p - frag_now->fr_literal) - insn_start_off;
3587 else
3588 {
3589 fragS *fr;
3590
3591 add = insn_start_frag->fr_fix - insn_start_off;
3592 for (fr = insn_start_frag->fr_next;
3593 fr && fr != frag_now; fr = fr->fr_next)
3594 add += fr->fr_fix;
3595 add += p - frag_now->fr_literal;
3596 }
3597
d6ab8113
JB		 3598 if (flag_code != CODE_64BIT)
3599 reloc_type = BFD_RELOC_386_GOTPC;
3600 else
3601 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3602 i.op[n].disps->X_add_number += add;
3603 }
062cd5e7 3604 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3605 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3606 }
3607 }
3608 }
3609}
252b5132 3610
29b0f896 3611static void
2bbd9c25
JJ		 3612output_imm (insn_start_frag, insn_start_off)
3613 fragS *insn_start_frag;
3614 offsetT insn_start_off;
29b0f896
AM		 3615{
3616 char *p;
3617 unsigned int n;
252b5132 3618
29b0f896
AM		 3619 for (n = 0; n < i.operands; n++)
3620 {
3621 if (i.types[n] & Imm)
3622 {
3623 if (i.op[n].imms->X_op == O_constant)
3624 {
3625 int size;
3626 offsetT val;
b4cac588 3627
29b0f896
AM		 3628 size = 4;
3629 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3630 {
3631 size = 2;
3632 if (i.types[n] & (Imm8 | Imm8S))
3633 size = 1;
3634 else if (i.types[n] & Imm64)
3635 size = 8;
3636 }
3637 val = offset_in_range (i.op[n].imms->X_add_number,
3638 size);
3639 p = frag_more (size);
3640 md_number_to_chars (p, val, size);
3641 }
3642 else
3643 {
3644 /* Not absolute_section.
3645 Need a 32-bit fixup (don't support 8bit
3646 non-absolute imms). Try to support other
3647 sizes ... */
f86103b7 3648 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3649 int size = 4;
3650 int sign = 0;
3651
3652 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3653 && (i.suffix == QWORD_MNEM_SUFFIX
3654 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3655 sign = 1;
3656 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3657 {
3658 size = 2;
3659 if (i.types[n] & (Imm8 | Imm8S))
3660 size = 1;
3661 if (i.types[n] & Imm64)
3662 size = 8;
3663 }
520dc8e8 3664
29b0f896
AM		 3665 p = frag_more (size);
3666 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3667
2bbd9c25
JJ		 3668 /* This is tough to explain. We end up with this one if we
3669 * have operands that look like
3670 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3671 * obtain the absolute address of the GOT, and it is strongly
3672 * preferable from a performance point of view to avoid using
3673 * a runtime relocation for this. The actual sequence of
3674 * instructions often look something like:
3675 *
3676 * call .L66
3677 * .L66:
3678 * popl %ebx
3679 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3680 *
3681 * The call and pop essentially return the absolute address
3682 * of the label .L66 and store it in %ebx. The linker itself
3683 * will ultimately change the first operand of the addl so
3684 * that %ebx points to the GOT, but to keep things simple, the
3685 * .o file must have this operand set so that it generates not
3686 * the absolute address of .L66, but the absolute address of
3687 * itself. This allows the linker itself simply treat a GOTPC
3688 * relocation as asking for a pcrel offset to the GOT to be
3689 * added in, and the addend of the relocation is stored in the
3690 * operand field for the instruction itself.
3691 *
3692 * Our job here is to fix the operand so that it would add
3693 * the correct offset so that %ebx would point to itself. The
3694 * thing that is tricky is that .-.L66 will point to the
3695 * beginning of the instruction, so we need to further modify
3696 * the operand so that it will point to itself. There are
3697 * other cases where you have something like:
3698 *
3699 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3700 *
3701 * and here no correction would be required. Internally in
3702 * the assembler we treat operands of this form as not being
3703 * pcrel since the '.' is explicitly mentioned, and I wonder
3704 * whether it would simplify matters to do it this way. Who
3705 * knows. In earlier versions of the PIC patches, the
3706 * pcrel_adjust field was used to store the correction, but
3707 * since the expression is not pcrel, I felt it would be
3708 * confusing to do it this way. */
3709
d6ab8113
JB		 3710 if ((reloc_type == BFD_RELOC_32
3711 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3712 && GOT_symbol
3713 && GOT_symbol == i.op[n].imms->X_add_symbol
3714 && (i.op[n].imms->X_op == O_symbol
3715 || (i.op[n].imms->X_op == O_add
3716 && ((symbol_get_value_expression
3717 (i.op[n].imms->X_op_symbol)->X_op)
3718 == O_subtract))))
3719 {
2bbd9c25
JJ		 3720 offsetT add;
3721
3722 if (insn_start_frag == frag_now)
3723 add = (p - frag_now->fr_literal) - insn_start_off;
3724 else
3725 {
3726 fragS *fr;
3727
3728 add = insn_start_frag->fr_fix - insn_start_off;
3729 for (fr = insn_start_frag->fr_next;
3730 fr && fr != frag_now; fr = fr->fr_next)
3731 add += fr->fr_fix;
3732 add += p - frag_now->fr_literal;
3733 }
3734
d6ab8113
JB		 3735 if (flag_code != CODE_64BIT)
3736 reloc_type = BFD_RELOC_386_GOTPC;
3737 else
3738 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3739 i.op[n].imms->X_add_number += add;
29b0f896 3740 }
29b0f896
AM		 3741 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3742 i.op[n].imms, 0, reloc_type);
3743 }
3744 }
3745 }
252b5132
RH		 3746}
3747\f
718ddfc0
JB		 3748#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3749# define lex_got(reloc, adjust, types) NULL
3750#else
f3c180ae
AM		 3751/* Parse operands of the form
3752 <symbol>@GOTOFF+<nnn>
3753 and similar .plt or .got references.
3754
3755 If we find one, set up the correct relocation in RELOC and copy the
3756 input string, minus the `@GOTOFF' into a malloc'd buffer for
3757 parsing by the calling routine. Return this buffer, and if ADJUST
3758 is non-null set it to the length of the string we removed from the
3759 input line. Otherwise return NULL. */
3760static char *
3956db08
JB		 3761lex_got (enum bfd_reloc_code_real *reloc,
3762 int *adjust,
3763 unsigned int *types)
f3c180ae
AM		 3764{
3765 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3766 static const struct {
3767 const char *str;
f86103b7 3768 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3956db08 3769 const unsigned int types64;
f3c180ae 3770 } gotrel[] = {
3956db08
JB		 3771 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3772 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3773 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3774 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3775 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 }, 0 },
3776 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3777 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3778 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3779 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 }, 0 },
3780 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3781 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 }, 0 },
3782 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 }, 0 },
3783 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3784 };
3785 char *cp;
3786 unsigned int j;
3787
718ddfc0
JB		 3788 if (!IS_ELF)
3789 return NULL;
3790
f3c180ae
AM		 3791 for (cp = input_line_pointer; *cp != '@'; cp++)
3792 if (is_end_of_line[(unsigned char) *cp])
3793 return NULL;
3794
3795 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3796 {
3797 int len;
3798
3799 len = strlen (gotrel[j].str);
28f81592 3800 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3801 {
3802 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3803 {
28f81592
AM		 3804 int first, second;
3805 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3806
3807 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3808 if (adjust)
3809 *adjust = len;
f3c180ae 3810
3956db08
JB		 3811 if (types)
3812 {
3813 if (flag_code != CODE_64BIT)
3814 *types = Imm32|Disp32;
3815 else
3816 *types = gotrel[j].types64;
3817 }
3818
f3c180ae
AM		 3819 if (GOT_symbol == NULL)
3820 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3821
3822 /* Replace the relocation token with ' ', so that
3823 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3824
3825 /* The length of the first part of our input line. */
f3c180ae 3826 first = cp - input_line_pointer;
28f81592
AM		 3827
3828 /* The second part goes from after the reloc token until
3829 (and including) an end_of_line char. Don't use strlen
3830 here as the end_of_line char may not be a NUL. */
3831 past_reloc = cp + 1 + len;
3832 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3833 ;
3834 second = cp - past_reloc;
3835
3836 /* Allocate and copy string. The trailing NUL shouldn't
3837 be necessary, but be safe. */
3838 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3839 memcpy (tmpbuf, input_line_pointer, first);
3840 tmpbuf[first] = ' ';
28f81592
AM		 3841 memcpy (tmpbuf + first + 1, past_reloc, second);
3842 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3843 return tmpbuf;
3844 }
3845
3846 as_bad (_("@%s reloc is not supported in %s bit mode"),
3847 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3848 return NULL;
3849 }
3850 }
3851
3852 /* Might be a symbol version string. Don't as_bad here. */
3853 return NULL;
3854}
3855
3856/* x86_cons_fix_new is called via the expression parsing code when a
3857 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3858static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3859
3860void
3861x86_cons_fix_new (frag, off, len, exp)
3862 fragS *frag;
3863 unsigned int off;
3864 unsigned int len;
3865 expressionS *exp;
3866{
3956db08 3867 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3868 got_reloc = NO_RELOC;
3869 fix_new_exp (frag, off, len, exp, 0, r);
3870}
3871
3872void
3873x86_cons (exp, size)
3874 expressionS *exp;
3875 int size;
3876{
d6ab8113 3877 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
f3c180ae
AM		 3878 {
3879 /* Handle @GOTOFF and the like in an expression. */
3880 char *save;
3881 char *gotfree_input_line;
3882 int adjust;
3883
3884 save = input_line_pointer;
3956db08 3885 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3886 if (gotfree_input_line)
3887 input_line_pointer = gotfree_input_line;
3888
3889 expression (exp);
3890
3891 if (gotfree_input_line)
3892 {
3893 /* expression () has merrily parsed up to the end of line,
3894 or a comma - in the wrong buffer. Transfer how far
3895 input_line_pointer has moved to the right buffer. */
3896 input_line_pointer = (save
3897 + (input_line_pointer - gotfree_input_line)
3898 + adjust);
3899 free (gotfree_input_line);
3900 }
3901 }
3902 else
3903 expression (exp);
3904}
3905#endif
3906
6482c264
NC		 3907#ifdef TE_PE
3908
6482c264
NC		 3909void
3910x86_pe_cons_fix_new (frag, off, len, exp)
3911 fragS *frag;
3912 unsigned int off;
3913 unsigned int len;
3914 expressionS *exp;
3915{
3956db08 3916 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3917
3918 if (exp->X_op == O_secrel)
3919 {
3920 exp->X_op = O_symbol;
3921 r = BFD_RELOC_32_SECREL;
3922 }
3923
3924 fix_new_exp (frag, off, len, exp, 0, r);
3925}
3926
3927static void
3928pe_directive_secrel (dummy)
3929 int dummy ATTRIBUTE_UNUSED;
3930{
3931 expressionS exp;
3932
3933 do
3934 {
3935 expression (&exp);
3936 if (exp.X_op == O_symbol)
3937 exp.X_op = O_secrel;
3938
3939 emit_expr (&exp, 4);
3940 }
3941 while (*input_line_pointer++ == ',');
3942
3943 input_line_pointer--;
3944 demand_empty_rest_of_line ();
3945}
3946
3947#endif
3948
252b5132
RH		 3949static int i386_immediate PARAMS ((char *));
3950
3951static int
3952i386_immediate (imm_start)
3953 char *imm_start;
3954{
3955 char *save_input_line_pointer;
f3c180ae 3956 char *gotfree_input_line;
252b5132 3957 segT exp_seg = 0;
47926f60 3958 expressionS *exp;
3956db08 3959 unsigned int types = ~0U;
252b5132
RH		 3960
3961 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3962 {
d0b47220 3963 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3964 return 0;
3965 }
3966
3967 exp = &im_expressions[i.imm_operands++];
520dc8e8 3968 i.op[this_operand].imms = exp;
252b5132
RH		 3969
3970 if (is_space_char (*imm_start))
3971 ++imm_start;
3972
3973 save_input_line_pointer = input_line_pointer;
3974 input_line_pointer = imm_start;
3975
3956db08 3976 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3977 if (gotfree_input_line)
3978 input_line_pointer = gotfree_input_line;
252b5132
RH		 3979
3980 exp_seg = expression (exp);
3981
83183c0c 3982 SKIP_WHITESPACE ();
252b5132 3983 if (*input_line_pointer)
f3c180ae 3984 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3985
3986 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3987 if (gotfree_input_line)
3988 free (gotfree_input_line);
252b5132 3989
2daf4fd8 3990 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3991 {
47926f60 3992 /* Missing or bad expr becomes absolute 0. */
d0b47220 3993 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3994 imm_start);
252b5132
RH		 3995 exp->X_op = O_constant;
3996 exp->X_add_number = 0;
3997 exp->X_add_symbol = (symbolS *) 0;
3998 exp->X_op_symbol = (symbolS *) 0;
252b5132 3999 }
3e73aa7c 4000 else if (exp->X_op == O_constant)
252b5132 4001 {
47926f60 4002 /* Size it properly later. */
3e73aa7c
JH		 4003 i.types[this_operand] |= Imm64;
4004 /* If BFD64, sign extend val. */
4005 if (!use_rela_relocations)
4006 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4007 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4008 }
4c63da97 4009#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4010 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4011 && exp_seg != absolute_section
47926f60 4012 && exp_seg != text_section
24eab124
AM		 4013 && exp_seg != data_section
4014 && exp_seg != bss_section
4015 && exp_seg != undefined_section
f86103b7 4016 && !bfd_is_com_section (exp_seg))
252b5132 4017 {
d0b47220 4018 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4019 return 0;
4020 }
4021#endif
4022 else
4023 {
4024 /* This is an address. The size of the address will be
24eab124 4025 determined later, depending on destination register,
3e73aa7c
JH		 4026 suffix, or the default for the section. */
4027 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4028 i.types[this_operand] &= types;
252b5132
RH		 4029 }
4030
4031 return 1;
4032}
4033
551c1ca1 4034static char *i386_scale PARAMS ((char *));
252b5132 4035
551c1ca1 4036static char *
252b5132
RH		 4037i386_scale (scale)
4038 char *scale;
4039{
551c1ca1
AM		 4040 offsetT val;
4041 char *save = input_line_pointer;
252b5132 4042
551c1ca1
AM		 4043 input_line_pointer = scale;
4044 val = get_absolute_expression ();
4045
4046 switch (val)
252b5132 4047 {
551c1ca1 4048 case 1:
252b5132
RH		 4049 i.log2_scale_factor = 0;
4050 break;
551c1ca1 4051 case 2:
252b5132
RH		 4052 i.log2_scale_factor = 1;
4053 break;
551c1ca1 4054 case 4:
252b5132
RH		 4055 i.log2_scale_factor = 2;
4056 break;
551c1ca1 4057 case 8:
252b5132
RH		 4058 i.log2_scale_factor = 3;
4059 break;
4060 default:
a724f0f4
JB		 4061 {
4062 char sep = *input_line_pointer;
4063
4064 *input_line_pointer = '\0';
4065 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4066 scale);
4067 *input_line_pointer = sep;
4068 input_line_pointer = save;
4069 return NULL;
4070 }
252b5132 4071 }
29b0f896 4072 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4073 {
4074 as_warn (_("scale factor of %d without an index register"),
24eab124 4075 1 << i.log2_scale_factor);
252b5132
RH		 4076#if SCALE1_WHEN_NO_INDEX
4077 i.log2_scale_factor = 0;
4078#endif
4079 }
551c1ca1
AM		 4080 scale = input_line_pointer;
4081 input_line_pointer = save;
4082 return scale;
252b5132
RH		 4083}
4084
4085static int i386_displacement PARAMS ((char *, char *));
4086
4087static int
4088i386_displacement (disp_start, disp_end)
4089 char *disp_start;
4090 char *disp_end;
4091{
29b0f896 4092 expressionS *exp;
252b5132
RH		 4093 segT exp_seg = 0;
4094 char *save_input_line_pointer;
f3c180ae 4095 char *gotfree_input_line;
252b5132 4096 int bigdisp = Disp32;
3956db08 4097 unsigned int types = Disp;
252b5132 4098
3e73aa7c 4099 if (flag_code == CODE_64BIT)
7ecd2f8b 4100 {
29b0f896 4101 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4102 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4103 }
4104 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4105 bigdisp = Disp16;
252b5132
RH		 4106 i.types[this_operand] |= bigdisp;
4107
4108 exp = &disp_expressions[i.disp_operands];
520dc8e8 4109 i.op[this_operand].disps = exp;
252b5132
RH		 4110 i.disp_operands++;
4111 save_input_line_pointer = input_line_pointer;
4112 input_line_pointer = disp_start;
4113 END_STRING_AND_SAVE (disp_end);
4114
4115#ifndef GCC_ASM_O_HACK
4116#define GCC_ASM_O_HACK 0
4117#endif
4118#if GCC_ASM_O_HACK
4119 END_STRING_AND_SAVE (disp_end + 1);
4120 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4121 && displacement_string_end[-1] == '+')
252b5132
RH		 4122 {
4123 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4124 constraint within gcc asm statements.
4125 For instance:
4126
4127 #define _set_tssldt_desc(n,addr,limit,type) \
4128 __asm__ __volatile__ ( \
4129 "movw %w2,%0\n\t" \
4130 "movw %w1,2+%0\n\t" \
4131 "rorl $16,%1\n\t" \
4132 "movb %b1,4+%0\n\t" \
4133 "movb %4,5+%0\n\t" \
4134 "movb $0,6+%0\n\t" \
4135 "movb %h1,7+%0\n\t" \
4136 "rorl $16,%1" \
4137 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4138
4139 This works great except that the output assembler ends
4140 up looking a bit weird if it turns out that there is
4141 no offset. You end up producing code that looks like:
4142
4143 #APP
4144 movw $235,(%eax)
4145 movw %dx,2+(%eax)
4146 rorl $16,%edx
4147 movb %dl,4+(%eax)
4148 movb $137,5+(%eax)
4149 movb $0,6+(%eax)
4150 movb %dh,7+(%eax)
4151 rorl $16,%edx
4152 #NO_APP
4153
47926f60 4154 So here we provide the missing zero. */
24eab124
AM		 4155
4156 *displacement_string_end = '0';
252b5132
RH		 4157 }
4158#endif
3956db08 4159 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4160 if (gotfree_input_line)
4161 input_line_pointer = gotfree_input_line;
252b5132 4162
24eab124 4163 exp_seg = expression (exp);
252b5132 4164
636c26b0
AM		 4165 SKIP_WHITESPACE ();
4166 if (*input_line_pointer)
4167 as_bad (_("junk `%s' after expression"), input_line_pointer);
4168#if GCC_ASM_O_HACK
4169 RESTORE_END_STRING (disp_end + 1);
4170#endif
4171 RESTORE_END_STRING (disp_end);
4172 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4173 if (gotfree_input_line)
4174 free (gotfree_input_line);
636c26b0 4175
24eab124
AM		 4176 /* We do this to make sure that the section symbol is in
4177 the symbol table. We will ultimately change the relocation
47926f60 4178 to be relative to the beginning of the section. */
1ae12ab7 4179 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4180 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4181 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4182 {
636c26b0
AM		 4183 if (exp->X_op != O_symbol)
4184 {
4185 as_bad (_("bad expression used with @%s"),
4186 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4187 ? "GOTPCREL"
4188 : "GOTOFF"));
4189 return 0;
4190 }
4191
e5cb08ac 4192 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4193 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4194 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4195 exp->X_op = O_subtract;
4196 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4197 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4198 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4199 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4200 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4201 else
29b0f896 4202 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4203 }
252b5132 4204
2daf4fd8
AM		 4205 if (exp->X_op == O_absent || exp->X_op == O_big)
4206 {
47926f60 4207 /* Missing or bad expr becomes absolute 0. */
d0b47220 4208 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4209 disp_start);
4210 exp->X_op = O_constant;
4211 exp->X_add_number = 0;
4212 exp->X_add_symbol = (symbolS *) 0;
4213 exp->X_op_symbol = (symbolS *) 0;
4214 }
4215
4c63da97 4216#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4217 if (exp->X_op != O_constant
45288df1 4218 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4219 && exp_seg != absolute_section
45288df1
AM		 4220 && exp_seg != text_section
4221 && exp_seg != data_section
4222 && exp_seg != bss_section
31312f95 4223 && exp_seg != undefined_section
f86103b7 4224 && !bfd_is_com_section (exp_seg))
24eab124 4225 {
d0b47220 4226 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4227 return 0;
4228 }
252b5132 4229#endif
3956db08
JB		 4230
4231 if (!(i.types[this_operand] & ~Disp))
4232 i.types[this_operand] &= types;
4233
252b5132
RH		 4234 return 1;
4235}
4236
e5cb08ac 4237static int i386_index_check PARAMS ((const char *));
252b5132 4238
eecb386c 4239/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4240 Return 1 on success, 0 on a failure. */
4241
252b5132 4242static int
eecb386c
AM		 4243i386_index_check (operand_string)
4244 const char *operand_string;
252b5132 4245{
3e73aa7c 4246 int ok;
24eab124 4247#if INFER_ADDR_PREFIX
eecb386c
AM		 4248 int fudged = 0;
4249
24eab124
AM		 4250 tryprefix:
4251#endif
3e73aa7c 4252 ok = 1;
30123838
JB		 4253 if ((current_templates->start->cpu_flags & CpuSVME)
4254 && current_templates->end[-1].operand_types[0] == AnyMem)
4255 {
4256 /* Memory operands of SVME insns are special in that they only allow
4257 rAX as their memory address and ignore any segment override. */
4258 unsigned RegXX;
4259
4260 /* SKINIT is even more restrictive: it always requires EAX. */
4261 if (strcmp (current_templates->start->name, "skinit") == 0)
4262 RegXX = Reg32;
4263 else if (flag_code == CODE_64BIT)
4264 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4265 else
4266 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4267 ? Reg16
4268 : Reg32;
4269 if (!i.base_reg
4270 || !(i.base_reg->reg_type & Acc)
4271 || !(i.base_reg->reg_type & RegXX)
4272 || i.index_reg
4273 || (i.types[0] & Disp))
4274 ok = 0;
4275 }
4276 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4277 {
4278 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4279
4280 if ((i.base_reg
4281 && ((i.base_reg->reg_type & RegXX) == 0)
4282 && (i.base_reg->reg_type != BaseIndex
4283 || i.index_reg))
4284 || (i.index_reg
4285 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4286 != (RegXX | BaseIndex))))
4287 ok = 0;
3e73aa7c
JH		 4288 }
4289 else
4290 {
4291 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4292 {
4293 /* 16bit checks. */
4294 if ((i.base_reg
29b0f896
AM		 4295 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4296 != (Reg16 | BaseIndex)))
3e73aa7c 4297 || (i.index_reg
29b0f896
AM		 4298 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4299 != (Reg16 | BaseIndex))
4300 || !(i.base_reg
4301 && i.base_reg->reg_num < 6
4302 && i.index_reg->reg_num >= 6
4303 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4304 ok = 0;
4305 }
4306 else
e5cb08ac 4307 {
3e73aa7c
JH		 4308 /* 32bit checks. */
4309 if ((i.base_reg
4310 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4311 || (i.index_reg
29b0f896
AM		 4312 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4313 != (Reg32 | BaseIndex))))
e5cb08ac 4314 ok = 0;
3e73aa7c
JH		 4315 }
4316 }
4317 if (!ok)
24eab124
AM		 4318 {
4319#if INFER_ADDR_PREFIX
20f0a1fc 4320 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4321 {
4322 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4323 i.prefixes += 1;
b23bac36
AM		 4324 /* Change the size of any displacement too. At most one of
4325 Disp16 or Disp32 is set.
4326 FIXME. There doesn't seem to be any real need for separate
4327 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4328 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4329 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4330 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4331 fudged = 1;
24eab124
AM		 4332 goto tryprefix;
4333 }
eecb386c
AM		 4334 if (fudged)
4335 as_bad (_("`%s' is not a valid base/index expression"),
4336 operand_string);
4337 else
c388dee8 4338#endif
eecb386c
AM		 4339 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4340 operand_string,
3e73aa7c 4341 flag_code_names[flag_code]);
24eab124 4342 }
20f0a1fc 4343 return ok;
24eab124 4344}
252b5132 4345
252b5132 4346/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4347 on error. */
252b5132 4348
252b5132
RH		 4349static int
4350i386_operand (operand_string)
4351 char *operand_string;
4352{
af6bdddf
AM		 4353 const reg_entry *r;
4354 char *end_op;
24eab124 4355 char *op_string = operand_string;
252b5132 4356
24eab124 4357 if (is_space_char (*op_string))
252b5132
RH		 4358 ++op_string;
4359
24eab124 4360 /* We check for an absolute prefix (differentiating,
47926f60 4361 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4362 if (*op_string == ABSOLUTE_PREFIX)
4363 {
4364 ++op_string;
4365 if (is_space_char (*op_string))
4366 ++op_string;
4367 i.types[this_operand] |= JumpAbsolute;
4368 }
252b5132 4369
47926f60 4370 /* Check if operand is a register. */
af6bdddf
AM		 4371 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4372 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4373 {
24eab124
AM		 4374 /* Check for a segment override by searching for ':' after a
4375 segment register. */
4376 op_string = end_op;
4377 if (is_space_char (*op_string))
4378 ++op_string;
4379 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4380 {
4381 switch (r->reg_num)
4382 {
4383 case 0:
4384 i.seg[i.mem_operands] = &es;
4385 break;
4386 case 1:
4387 i.seg[i.mem_operands] = &cs;
4388 break;
4389 case 2:
4390 i.seg[i.mem_operands] = &ss;
4391 break;
4392 case 3:
4393 i.seg[i.mem_operands] = &ds;
4394 break;
4395 case 4:
4396 i.seg[i.mem_operands] = &fs;
4397 break;
4398 case 5:
4399 i.seg[i.mem_operands] = &gs;
4400 break;
4401 }
252b5132 4402
24eab124 4403 /* Skip the ':' and whitespace. */
252b5132
RH		 4404 ++op_string;
4405 if (is_space_char (*op_string))
24eab124 4406 ++op_string;
252b5132 4407
24eab124
AM		 4408 if (!is_digit_char (*op_string)
4409 && !is_identifier_char (*op_string)
4410 && *op_string != '('
4411 && *op_string != ABSOLUTE_PREFIX)
4412 {
4413 as_bad (_("bad memory operand `%s'"), op_string);
4414 return 0;
4415 }
47926f60 4416 /* Handle case of %es:*foo. */
24eab124
AM		 4417 if (*op_string == ABSOLUTE_PREFIX)
4418 {
4419 ++op_string;
4420 if (is_space_char (*op_string))
4421 ++op_string;
4422 i.types[this_operand] |= JumpAbsolute;
4423 }
4424 goto do_memory_reference;
4425 }
4426 if (*op_string)
4427 {
d0b47220 4428 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4429 return 0;
4430 }
4431 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4432 i.op[this_operand].regs = r;
24eab124
AM		 4433 i.reg_operands++;
4434 }
af6bdddf
AM		 4435 else if (*op_string == REGISTER_PREFIX)
4436 {
4437 as_bad (_("bad register name `%s'"), op_string);
4438 return 0;
4439 }
24eab124 4440 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4441 {
24eab124
AM		 4442 ++op_string;
4443 if (i.types[this_operand] & JumpAbsolute)
4444 {
d0b47220 4445 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4446 return 0;
4447 }
4448 if (!i386_immediate (op_string))
4449 return 0;
4450 }
4451 else if (is_digit_char (*op_string)
4452 || is_identifier_char (*op_string)
e5cb08ac 4453 || *op_string == '(')
24eab124 4454 {
47926f60 4455 /* This is a memory reference of some sort. */
af6bdddf 4456 char *base_string;
252b5132 4457
47926f60 4458 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4459 char *displacement_string_start;
4460 char *displacement_string_end;
252b5132 4461
24eab124 4462 do_memory_reference:
24eab124
AM		 4463 if ((i.mem_operands == 1
4464 && (current_templates->start->opcode_modifier & IsString) == 0)
4465 || i.mem_operands == 2)
4466 {
4467 as_bad (_("too many memory references for `%s'"),
4468 current_templates->start->name);
4469 return 0;
4470 }
252b5132 4471
24eab124
AM		 4472 /* Check for base index form. We detect the base index form by
4473 looking for an ')' at the end of the operand, searching
4474 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4475 after the '('. */
af6bdddf 4476 base_string = op_string + strlen (op_string);
c3332e24 4477
af6bdddf
AM		 4478 --base_string;
4479 if (is_space_char (*base_string))
4480 --base_string;
252b5132 4481
47926f60 4482 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4483 displacement_string_start = op_string;
4484 displacement_string_end = base_string + 1;
252b5132 4485
24eab124
AM		 4486 if (*base_string == ')')
4487 {
af6bdddf 4488 char *temp_string;
24eab124
AM		 4489 unsigned int parens_balanced = 1;
4490 /* We've already checked that the number of left & right ()'s are
47926f60 4491 equal, so this loop will not be infinite. */
24eab124
AM		 4492 do
4493 {
4494 base_string--;
4495 if (*base_string == ')')
4496 parens_balanced++;
4497 if (*base_string == '(')
4498 parens_balanced--;
4499 }
4500 while (parens_balanced);
c3332e24 4501
af6bdddf 4502 temp_string = base_string;
c3332e24 4503
24eab124 4504 /* Skip past '(' and whitespace. */
252b5132
RH		 4505 ++base_string;
4506 if (is_space_char (*base_string))
24eab124 4507 ++base_string;
252b5132 4508
af6bdddf
AM		 4509 if (*base_string == ','
4510 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4511 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4512 {
af6bdddf 4513 displacement_string_end = temp_string;
252b5132 4514
af6bdddf 4515 i.types[this_operand] |= BaseIndex;
252b5132 4516
af6bdddf 4517 if (i.base_reg)
24eab124 4518 {
24eab124
AM		 4519 base_string = end_op;
4520 if (is_space_char (*base_string))
4521 ++base_string;
af6bdddf
AM		 4522 }
4523
4524 /* There may be an index reg or scale factor here. */
4525 if (*base_string == ',')
4526 {
4527 ++base_string;
4528 if (is_space_char (*base_string))
4529 ++base_string;
4530
4531 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4532 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4533 {
af6bdddf 4534 base_string = end_op;
24eab124
AM		 4535 if (is_space_char (*base_string))
4536 ++base_string;
af6bdddf
AM		 4537 if (*base_string == ',')
4538 {
4539 ++base_string;
4540 if (is_space_char (*base_string))
4541 ++base_string;
4542 }
e5cb08ac 4543 else if (*base_string != ')')
af6bdddf
AM		 4544 {
4545 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4546 operand_string);
4547 return 0;
4548 }
24eab124 4549 }
af6bdddf 4550 else if (*base_string == REGISTER_PREFIX)
24eab124 4551 {
af6bdddf 4552 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4553 return 0;
4554 }
252b5132 4555
47926f60 4556 /* Check for scale factor. */
551c1ca1 4557 if (*base_string != ')')
af6bdddf 4558 {
551c1ca1
AM		 4559 char *end_scale = i386_scale (base_string);
4560
4561 if (!end_scale)
af6bdddf 4562 return 0;
24eab124 4563
551c1ca1 4564 base_string = end_scale;
af6bdddf
AM		 4565 if (is_space_char (*base_string))
4566 ++base_string;
4567 if (*base_string != ')')
4568 {
4569 as_bad (_("expecting `)' after scale factor in `%s'"),
4570 operand_string);
4571 return 0;
4572 }
4573 }
4574 else if (!i.index_reg)
24eab124 4575 {
af6bdddf
AM		 4576 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4577 *base_string);
24eab124
AM		 4578 return 0;
4579 }
4580 }
af6bdddf 4581 else if (*base_string != ')')
24eab124 4582 {
af6bdddf
AM		 4583 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4584 operand_string);
24eab124
AM		 4585 return 0;
4586 }
c3332e24 4587 }
af6bdddf 4588 else if (*base_string == REGISTER_PREFIX)
c3332e24 4589 {
af6bdddf 4590 as_bad (_("bad register name `%s'"), base_string);
24eab124 4591 return 0;
c3332e24 4592 }
24eab124
AM		 4593 }
4594
4595 /* If there's an expression beginning the operand, parse it,
4596 assuming displacement_string_start and
4597 displacement_string_end are meaningful. */
4598 if (displacement_string_start != displacement_string_end)
4599 {
4600 if (!i386_displacement (displacement_string_start,
4601 displacement_string_end))
4602 return 0;
4603 }
4604
4605 /* Special case for (%dx) while doing input/output op. */
4606 if (i.base_reg
4607 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4608 && i.index_reg == 0
4609 && i.log2_scale_factor == 0
4610 && i.seg[i.mem_operands] == 0
4611 && (i.types[this_operand] & Disp) == 0)
4612 {
4613 i.types[this_operand] = InOutPortReg;
4614 return 1;
4615 }
4616
eecb386c
AM		 4617 if (i386_index_check (operand_string) == 0)
4618 return 0;
24eab124
AM		 4619 i.mem_operands++;
4620 }
4621 else
ce8a8b2f
AM		 4622 {
4623 /* It's not a memory operand; argh! */
24eab124
AM		 4624 as_bad (_("invalid char %s beginning operand %d `%s'"),
4625 output_invalid (*op_string),
4626 this_operand + 1,
4627 op_string);
4628 return 0;
4629 }
47926f60 4630 return 1; /* Normal return. */
252b5132
RH		 4631}
4632\f
ee7fcc42
AM		 4633/* md_estimate_size_before_relax()
4634
4635 Called just before relax() for rs_machine_dependent frags. The x86
4636 assembler uses these frags to handle variable size jump
4637 instructions.
4638
4639 Any symbol that is now undefined will not become defined.
4640 Return the correct fr_subtype in the frag.
4641 Return the initial "guess for variable size of frag" to caller.
4642 The guess is actually the growth beyond the fixed part. Whatever
4643 we do to grow the fixed or variable part contributes to our
4644 returned value. */
4645
252b5132
RH		 4646int
4647md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4648 fragS *fragP;
4649 segT segment;
252b5132 4650{
252b5132 4651 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4652 check for un-relaxable symbols. On an ELF system, we can't relax
4653 an externally visible symbol, because it may be overridden by a
4654 shared library. */
4655 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4656#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4657 || (IS_ELF
31312f95
AM		 4658 && (S_IS_EXTERNAL (fragP->fr_symbol)
4659 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4660#endif
4661 )
252b5132 4662 {
b98ef147
AM		 4663 /* Symbol is undefined in this segment, or we need to keep a
4664 reloc so that weak symbols can be overridden. */
4665 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4666 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4667 unsigned char *opcode;
4668 int old_fr_fix;
f6af82bd 4669
ee7fcc42
AM		 4670 if (fragP->fr_var != NO_RELOC)
4671 reloc_type = fragP->fr_var;
b98ef147 4672 else if (size == 2)
f6af82bd
AM		 4673 reloc_type = BFD_RELOC_16_PCREL;
4674 else
4675 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4676
ee7fcc42
AM		 4677 old_fr_fix = fragP->fr_fix;
4678 opcode = (unsigned char *) fragP->fr_opcode;
4679
fddf5b5b 4680 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4681 {
fddf5b5b
AM		 4682 case UNCOND_JUMP:
4683 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4684 opcode[0] = 0xe9;
252b5132 4685 fragP->fr_fix += size;
062cd5e7
AS		 4686 fix_new (fragP, old_fr_fix, size,
4687 fragP->fr_symbol,
4688 fragP->fr_offset, 1,
4689 reloc_type);
252b5132
RH		 4690 break;
4691
fddf5b5b 4692 case COND_JUMP86:
412167cb
AM		 4693 if (size == 2
4694 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4695 {
4696 /* Negate the condition, and branch past an
4697 unconditional jump. */
4698 opcode[0] ^= 1;
4699 opcode[1] = 3;
4700 /* Insert an unconditional jump. */
4701 opcode[2] = 0xe9;
4702 /* We added two extra opcode bytes, and have a two byte
4703 offset. */
4704 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4705 fix_new (fragP, old_fr_fix + 2, 2,
4706 fragP->fr_symbol,
4707 fragP->fr_offset, 1,
4708 reloc_type);
fddf5b5b
AM		 4709 break;
4710 }
4711 /* Fall through. */
4712
4713 case COND_JUMP:
412167cb
AM		 4714 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4715 {
3e02c1cc
AM		 4716 fixS *fixP;
4717
412167cb 4718 fragP->fr_fix += 1;
3e02c1cc
AM		 4719 fixP = fix_new (fragP, old_fr_fix, 1,
4720 fragP->fr_symbol,
4721 fragP->fr_offset, 1,
4722 BFD_RELOC_8_PCREL);
4723 fixP->fx_signed = 1;
412167cb
AM		 4724 break;
4725 }
93c2a809 4726
24eab124 4727 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4728 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4729 opcode[1] = opcode[0] + 0x10;
f6af82bd 4730 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4731 /* We've added an opcode byte. */
4732 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4733 fix_new (fragP, old_fr_fix + 1, size,
4734 fragP->fr_symbol,
4735 fragP->fr_offset, 1,
4736 reloc_type);
252b5132 4737 break;
fddf5b5b
AM		 4738
4739 default:
4740 BAD_CASE (fragP->fr_subtype);
4741 break;
252b5132
RH		 4742 }
4743 frag_wane (fragP);
ee7fcc42 4744 return fragP->fr_fix - old_fr_fix;
252b5132 4745 }
93c2a809 4746
93c2a809
AM		 4747 /* Guess size depending on current relax state. Initially the relax
4748 state will correspond to a short jump and we return 1, because
4749 the variable part of the frag (the branch offset) is one byte
4750 long. However, we can relax a section more than once and in that
4751 case we must either set fr_subtype back to the unrelaxed state,
4752 or return the value for the appropriate branch. */
4753 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4754}
4755
47926f60
KH		 4756/* Called after relax() is finished.
4757
4758 In: Address of frag.
4759 fr_type == rs_machine_dependent.
4760 fr_subtype is what the address relaxed to.
4761
4762 Out: Any fixSs and constants are set up.
4763 Caller will turn frag into a ".space 0". */
4764
252b5132
RH		 4765void
4766md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4767 bfd *abfd ATTRIBUTE_UNUSED;
4768 segT sec ATTRIBUTE_UNUSED;
29b0f896 4769 fragS *fragP;
252b5132 4770{
29b0f896 4771 unsigned char *opcode;
252b5132 4772 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4773 offsetT target_address;
4774 offsetT opcode_address;
252b5132 4775 unsigned int extension = 0;
847f7ad4 4776 offsetT displacement_from_opcode_start;
252b5132
RH		 4777
4778 opcode = (unsigned char *) fragP->fr_opcode;
4779
47926f60 4780 /* Address we want to reach in file space. */
252b5132 4781 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4782
47926f60 4783 /* Address opcode resides at in file space. */
252b5132
RH		 4784 opcode_address = fragP->fr_address + fragP->fr_fix;
4785
47926f60 4786 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4787 displacement_from_opcode_start = target_address - opcode_address;
4788
fddf5b5b 4789 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4790 {
47926f60
KH		 4791 /* Don't have to change opcode. */
4792 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4793 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4794 }
4795 else
4796 {
4797 if (no_cond_jump_promotion
4798 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4799 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4800
fddf5b5b
AM		 4801 switch (fragP->fr_subtype)
4802 {
4803 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4804 extension = 4; /* 1 opcode + 4 displacement */
4805 opcode[0] = 0xe9;
4806 where_to_put_displacement = &opcode[1];
4807 break;
252b5132 4808
fddf5b5b
AM		 4809 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4810 extension = 2; /* 1 opcode + 2 displacement */
4811 opcode[0] = 0xe9;
4812 where_to_put_displacement = &opcode[1];
4813 break;
252b5132 4814
fddf5b5b
AM		 4815 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4816 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4817 extension = 5; /* 2 opcode + 4 displacement */
4818 opcode[1] = opcode[0] + 0x10;
4819 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4820 where_to_put_displacement = &opcode[2];
4821 break;
252b5132 4822
fddf5b5b
AM		 4823 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4824 extension = 3; /* 2 opcode + 2 displacement */
4825 opcode[1] = opcode[0] + 0x10;
4826 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4827 where_to_put_displacement = &opcode[2];
4828 break;
252b5132 4829
fddf5b5b
AM		 4830 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4831 extension = 4;
4832 opcode[0] ^= 1;
4833 opcode[1] = 3;
4834 opcode[2] = 0xe9;
4835 where_to_put_displacement = &opcode[3];
4836 break;
4837
4838 default:
4839 BAD_CASE (fragP->fr_subtype);
4840 break;
4841 }
252b5132 4842 }
fddf5b5b 4843
47926f60 4844 /* Now put displacement after opcode. */
252b5132
RH		 4845 md_number_to_chars ((char *) where_to_put_displacement,
4846 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4847 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4848 fragP->fr_fix += extension;
4849}
4850\f
47926f60
KH		 4851/* Size of byte displacement jmp. */
4852int md_short_jump_size = 2;
4853
4854/* Size of dword displacement jmp. */
4855int md_long_jump_size = 5;
252b5132 4856
47926f60
KH		 4857/* Size of relocation record. */
4858const int md_reloc_size = 8;
252b5132
RH		 4859
4860void
4861md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4862 char *ptr;
4863 addressT from_addr, to_addr;
ab9da554
ILT		 4864 fragS *frag ATTRIBUTE_UNUSED;
4865 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4866{
847f7ad4 4867 offsetT offset;
252b5132
RH		 4868
4869 offset = to_addr - (from_addr + 2);
47926f60
KH		 4870 /* Opcode for byte-disp jump. */
4871 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4872 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4873}
4874
4875void
4876md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4877 char *ptr;
4878 addressT from_addr, to_addr;
a38cf1db
AM		 4879 fragS *frag ATTRIBUTE_UNUSED;
4880 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4881{
847f7ad4 4882 offsetT offset;
252b5132 4883
a38cf1db
AM		 4884 offset = to_addr - (from_addr + 5);
4885 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4886 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4887}
4888\f
4889/* Apply a fixup (fixS) to segment data, once it has been determined
4890 by our caller that we have all the info we need to fix it up.
4891
4892 On the 386, immediates, displacements, and data pointers are all in
4893 the same (little-endian) format, so we don't need to care about which
4894 we are handling. */
4895
94f592af 4896void
55cf6793 4897md_apply_fix (fixP, valP, seg)
47926f60
KH		 4898 /* The fix we're to put in. */
4899 fixS *fixP;
47926f60 4900 /* Pointer to the value of the bits. */
c6682705 4901 valueT *valP;
47926f60
KH		 4902 /* Segment fix is from. */
4903 segT seg ATTRIBUTE_UNUSED;
252b5132 4904{
94f592af 4905 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4906 valueT value = *valP;
252b5132 4907
f86103b7 4908#if !defined (TE_Mach)
93382f6d
AM		 4909 if (fixP->fx_pcrel)
4910 {
4911 switch (fixP->fx_r_type)
4912 {
5865bb77
ILT		 4913 default:
4914 break;
4915
d6ab8113
JB		 4916 case BFD_RELOC_64:
4917 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4918 break;
93382f6d 4919 case BFD_RELOC_32:
ae8887b5 4920 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4921 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4922 break;
4923 case BFD_RELOC_16:
4924 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4925 break;
4926 case BFD_RELOC_8:
4927 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4928 break;
4929 }
4930 }
252b5132 4931
a161fe53 4932 if (fixP->fx_addsy != NULL
31312f95 4933 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4934 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4935 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4936 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4937 && !use_rela_relocations)
252b5132 4938 {
31312f95
AM		 4939 /* This is a hack. There should be a better way to handle this.
4940 This covers for the fact that bfd_install_relocation will
4941 subtract the current location (for partial_inplace, PC relative
4942 relocations); see more below. */
252b5132 4943#ifndef OBJ_AOUT
718ddfc0 4944 if (IS_ELF
252b5132
RH		 4945#ifdef TE_PE
4946 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4947#endif
4948 )
4949 value += fixP->fx_where + fixP->fx_frag->fr_address;
4950#endif
4951#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4952 if (IS_ELF)
252b5132 4953 {
6539b54b 4954 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4955
6539b54b 4956 if ((sym_seg == seg
2f66722d 4957 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4958 && sym_seg != absolute_section))
ae6063d4 4959 && !generic_force_reloc (fixP))
2f66722d
AM		 4960 {
4961 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4962 bfd_install_relocation subtracts them out again. I think
4963 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4964 it. FIXME. */
4965 value += fixP->fx_where + fixP->fx_frag->fr_address;
4966 }
252b5132
RH		 4967 }
4968#endif
4969#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4970 /* For some reason, the PE format does not store a
4971 section address offset for a PC relative symbol. */
4972 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4973#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4974 || S_IS_WEAK (fixP->fx_addsy)
4975#endif
4976 )
252b5132
RH		 4977 value += md_pcrel_from (fixP);
4978#endif
4979 }
4980
4981 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4982 and we must not disappoint it. */
252b5132 4983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4984 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 4985 switch (fixP->fx_r_type)
4986 {
4987 case BFD_RELOC_386_PLT32:
3e73aa7c 4988 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4989 /* Make the jump instruction point to the address of the operand. At
4990 runtime we merely add the offset to the actual PLT entry. */
4991 value = -4;
4992 break;
31312f95 4993
13ae64f3
JJ		 4994 case BFD_RELOC_386_TLS_GD:
4995 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4996 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4997 case BFD_RELOC_386_TLS_IE:
4998 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4999 case BFD_RELOC_X86_64_TLSGD:
5000 case BFD_RELOC_X86_64_TLSLD:
5001 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5002 value = 0; /* Fully resolved at runtime. No addend. */
5003 /* Fallthrough */
5004 case BFD_RELOC_386_TLS_LE:
5005 case BFD_RELOC_386_TLS_LDO_32:
5006 case BFD_RELOC_386_TLS_LE_32:
5007 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5008 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5009 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5010 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5011 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5012 break;
5013
5014 case BFD_RELOC_386_GOT32:
5015 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5016 value = 0; /* Fully resolved at runtime. No addend. */
5017 break;
47926f60
KH		 5018
5019 case BFD_RELOC_VTABLE_INHERIT:
5020 case BFD_RELOC_VTABLE_ENTRY:
5021 fixP->fx_done = 0;
94f592af 5022 return;
47926f60
KH		 5023
5024 default:
5025 break;
5026 }
5027#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5028 *valP = value;
f86103b7 5029#endif /* !defined (TE_Mach) */
3e73aa7c 5030
3e73aa7c 5031 /* Are we finished with this relocation now? */
c6682705 5032 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5033 fixP->fx_done = 1;
5034 else if (use_rela_relocations)
5035 {
5036 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5037 /* Remember value for tc_gen_reloc. */
5038 fixP->fx_addnumber = value;
3e73aa7c
JH		 5039 value = 0;
5040 }
f86103b7 5041
94f592af 5042 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5043}
252b5132 5044\f
252b5132
RH		 5045#define MAX_LITTLENUMS 6
5046
47926f60
KH		 5047/* Turn the string pointed to by litP into a floating point constant
5048 of type TYPE, and emit the appropriate bytes. The number of
5049 LITTLENUMS emitted is stored in *SIZEP. An error message is
5050 returned, or NULL on OK. */
5051
252b5132
RH		 5052char *
5053md_atof (type, litP, sizeP)
2ab9b79e 5054 int type;
252b5132
RH		 5055 char *litP;
5056 int *sizeP;
5057{
5058 int prec;
5059 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5060 LITTLENUM_TYPE *wordP;
5061 char *t;
5062
5063 switch (type)
5064 {
5065 case 'f':
5066 case 'F':
5067 prec = 2;
5068 break;
5069
5070 case 'd':
5071 case 'D':
5072 prec = 4;
5073 break;
5074
5075 case 'x':
5076 case 'X':
5077 prec = 5;
5078 break;
5079
5080 default:
5081 *sizeP = 0;
5082 return _("Bad call to md_atof ()");
5083 }
5084 t = atof_ieee (input_line_pointer, type, words);
5085 if (t)
5086 input_line_pointer = t;
5087
5088 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5089 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5090 the bigendian 386. */
5091 for (wordP = words + prec - 1; prec--;)
5092 {
5093 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5094 litP += sizeof (LITTLENUM_TYPE);
5095 }
5096 return 0;
5097}
5098\f
87c245cc 5099static char output_invalid_buf[8];
252b5132 5100
252b5132
RH		 5101static char *
5102output_invalid (c)
5103 int c;
5104{
3882b010 5105 if (ISPRINT (c))
252b5132
RH		 5106 sprintf (output_invalid_buf, "'%c'", c);
5107 else
5108 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5109 return output_invalid_buf;
5110}
5111
af6bdddf 5112/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5113
5114static const reg_entry *
5115parse_register (reg_string, end_op)
5116 char *reg_string;
5117 char **end_op;
5118{
af6bdddf
AM		 5119 char *s = reg_string;
5120 char *p;
252b5132
RH		 5121 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5122 const reg_entry *r;
5123
5124 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5125 if (*s == REGISTER_PREFIX)
5126 ++s;
5127
5128 if (is_space_char (*s))
5129 ++s;
5130
5131 p = reg_name_given;
af6bdddf 5132 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5133 {
5134 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5135 return (const reg_entry *) NULL;
5136 s++;
252b5132
RH		 5137 }
5138
6588847e
DN		 5139 /* For naked regs, make sure that we are not dealing with an identifier.
5140 This prevents confusing an identifier like `eax_var' with register
5141 `eax'. */
5142 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5143 return (const reg_entry *) NULL;
5144
af6bdddf 5145 *end_op = s;
252b5132
RH		 5146
5147 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5148
5f47d35b 5149 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5150 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5151 {
5f47d35b
AM		 5152 if (is_space_char (*s))
5153 ++s;
5154 if (*s == '(')
5155 {
af6bdddf 5156 ++s;
5f47d35b
AM		 5157 if (is_space_char (*s))
5158 ++s;
5159 if (*s >= '0' && *s <= '7')
5160 {
5161 r = &i386_float_regtab[*s - '0'];
af6bdddf 5162 ++s;
5f47d35b
AM		 5163 if (is_space_char (*s))
5164 ++s;
5165 if (*s == ')')
5166 {
5167 *end_op = s + 1;
5168 return r;
5169 }
5f47d35b 5170 }
47926f60 5171 /* We have "%st(" then garbage. */
5f47d35b
AM		 5172 return (const reg_entry *) NULL;
5173 }
5174 }
5175
1ae00879 5176 if (r != NULL
20f0a1fc 5177 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5178 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5179 && flag_code != CODE_64BIT)
20f0a1fc 5180 return (const reg_entry *) NULL;
1ae00879 5181
252b5132
RH		 5182 return r;
5183}
5184\f
4cc782b5 5185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5186const char *md_shortopts = "kVQ:sqn";
252b5132 5187#else
12b55ccc 5188const char *md_shortopts = "qn";
252b5132 5189#endif
6e0b89ee 5190
252b5132 5191struct option md_longopts[] = {
3e73aa7c
JH		 5192#define OPTION_32 (OPTION_MD_BASE + 0)
5193 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5194#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5195#define OPTION_64 (OPTION_MD_BASE + 1)
5196 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5197#endif
252b5132
RH		 5198 {NULL, no_argument, NULL, 0}
5199};
5200size_t md_longopts_size = sizeof (md_longopts);
5201
5202int
5203md_parse_option (c, arg)
5204 int c;
ab9da554 5205 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5206{
5207 switch (c)
5208 {
12b55ccc
L		 5209 case 'n':
5210 optimize_align_code = 0;
5211 break;
5212
a38cf1db
AM		 5213 case 'q':
5214 quiet_warnings = 1;
252b5132
RH		 5215 break;
5216
5217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5218 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5219 should be emitted or not. FIXME: Not implemented. */
5220 case 'Q':
252b5132
RH		 5221 break;
5222
5223 /* -V: SVR4 argument to print version ID. */
5224 case 'V':
5225 print_version_id ();
5226 break;
5227
a38cf1db
AM		 5228 /* -k: Ignore for FreeBSD compatibility. */
5229 case 'k':
252b5132 5230 break;
4cc782b5
ILT		 5231
5232 case 's':
5233 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5234 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5235 break;
6e0b89ee 5236
3e73aa7c
JH		 5237 case OPTION_64:
5238 {
5239 const char **list, **l;
5240
3e73aa7c
JH		 5241 list = bfd_target_list ();
5242 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5243 if (strcmp (*l, "elf64-x86-64") == 0)
5244 {
5245 default_arch = "x86_64";
5246 break;
5247 }
3e73aa7c 5248 if (*l == NULL)
6e0b89ee 5249 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5250 free (list);
5251 }
5252 break;
5253#endif
252b5132 5254
6e0b89ee
AM		 5255 case OPTION_32:
5256 default_arch = "i386";
5257 break;
5258
252b5132
RH		 5259 default:
5260 return 0;
5261 }
5262 return 1;
5263}
5264
5265void
5266md_show_usage (stream)
5267 FILE *stream;
5268{
4cc782b5
ILT		 5269#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5270 fprintf (stream, _("\
a38cf1db
AM		 5271 -Q ignored\n\
5272 -V print assembler version number\n\
5273 -k ignored\n\
12b55ccc 5274 -n Do not optimize code alignment\n\
a38cf1db
AM		 5275 -q quieten some warnings\n\
5276 -s ignored\n"));
5277#else
5278 fprintf (stream, _("\
12b55ccc 5279 -n Do not optimize code alignment\n\
a38cf1db 5280 -q quieten some warnings\n"));
4cc782b5 5281#endif
252b5132
RH		 5282}
5283
3e73aa7c
JH		 5284#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5285 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5286
5287/* Pick the target format to use. */
5288
47926f60 5289const char *
252b5132
RH		 5290i386_target_format ()
5291{
3e73aa7c
JH		 5292 if (!strcmp (default_arch, "x86_64"))
5293 set_code_flag (CODE_64BIT);
5294 else if (!strcmp (default_arch, "i386"))
5295 set_code_flag (CODE_32BIT);
5296 else
5297 as_fatal (_("Unknown architecture"));
252b5132
RH		 5298 switch (OUTPUT_FLAVOR)
5299 {
4c63da97
AM		 5300#ifdef OBJ_MAYBE_AOUT
5301 case bfd_target_aout_flavour:
47926f60 5302 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5303#endif
5304#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5305 case bfd_target_coff_flavour:
5306 return "coff-i386";
4c63da97 5307#endif
3e73aa7c 5308#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5309 case bfd_target_elf_flavour:
3e73aa7c 5310 {
e5cb08ac
KH		 5311 if (flag_code == CODE_64BIT)
5312 use_rela_relocations = 1;
4ada7262 5313 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5314 }
4c63da97 5315#endif
252b5132
RH		 5316 default:
5317 abort ();
5318 return NULL;
5319 }
5320}
5321
47926f60 5322#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5323
5324#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5325void i386_elf_emit_arch_note ()
5326{
718ddfc0 5327 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5328 {
5329 char *p;
5330 asection *seg = now_seg;
5331 subsegT subseg = now_subseg;
5332 Elf_Internal_Note i_note;
5333 Elf_External_Note e_note;
5334 asection *note_secp;
5335 int len;
5336
5337 /* Create the .note section. */
5338 note_secp = subseg_new (".note", 0);
5339 bfd_set_section_flags (stdoutput,
5340 note_secp,
5341 SEC_HAS_CONTENTS | SEC_READONLY);
5342
5343 /* Process the arch string. */
5344 len = strlen (cpu_arch_name);
5345
5346 i_note.namesz = len + 1;
5347 i_note.descsz = 0;
5348 i_note.type = NT_ARCH;
5349 p = frag_more (sizeof (e_note.namesz));
5350 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5351 p = frag_more (sizeof (e_note.descsz));
5352 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5353 p = frag_more (sizeof (e_note.type));
5354 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5355 p = frag_more (len + 1);
5356 strcpy (p, cpu_arch_name);
5357
5358 frag_align (2, 0, 0);
5359
5360 subseg_set (seg, subseg);
5361 }
5362}
5363#endif
252b5132 5364\f
252b5132
RH		 5365symbolS *
5366md_undefined_symbol (name)
5367 char *name;
5368{
18dc2407
ILT		 5369 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5370 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5371 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5372 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5373 {
5374 if (!GOT_symbol)
5375 {
5376 if (symbol_find (name))
5377 as_bad (_("GOT already in symbol table"));
5378 GOT_symbol = symbol_new (name, undefined_section,
5379 (valueT) 0, &zero_address_frag);
5380 };
5381 return GOT_symbol;
5382 }
252b5132
RH		 5383 return 0;
5384}
5385
5386/* Round up a section size to the appropriate boundary. */
47926f60 5387
252b5132
RH		 5388valueT
5389md_section_align (segment, size)
ab9da554 5390 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5391 valueT size;
5392{
4c63da97
AM		 5393#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5394 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5395 {
5396 /* For a.out, force the section size to be aligned. If we don't do
5397 this, BFD will align it for us, but it will not write out the
5398 final bytes of the section. This may be a bug in BFD, but it is
5399 easier to fix it here since that is how the other a.out targets
5400 work. */
5401 int align;
5402
5403 align = bfd_get_section_alignment (stdoutput, segment);
5404 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5405 }
252b5132
RH		 5406#endif
5407
5408 return size;
5409}
5410
5411/* On the i386, PC-relative offsets are relative to the start of the
5412 next instruction. That is, the address of the offset, plus its
5413 size, since the offset is always the last part of the insn. */
5414
5415long
5416md_pcrel_from (fixP)
5417 fixS *fixP;
5418{
5419 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5420}
5421
5422#ifndef I386COFF
5423
5424static void
5425s_bss (ignore)
ab9da554 5426 int ignore ATTRIBUTE_UNUSED;
252b5132 5427{
29b0f896 5428 int temp;
252b5132 5429
8a75718c
JB		 5430#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5431 if (IS_ELF)
5432 obj_elf_section_change_hook ();
5433#endif
252b5132
RH		 5434 temp = get_absolute_expression ();
5435 subseg_set (bss_section, (subsegT) temp);
5436 demand_empty_rest_of_line ();
5437}
5438
5439#endif
5440
252b5132
RH		 5441void
5442i386_validate_fix (fixp)
5443 fixS *fixp;
5444{
5445 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5446 {
23df1078
JH		 5447 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5448 {
5449 if (flag_code != CODE_64BIT)
5450 abort ();
5451 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5452 }
5453 else
5454 {
d6ab8113
JB		 5455 if (flag_code != CODE_64BIT)
5456 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5457 else
5458 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5459 }
252b5132
RH		 5460 fixp->fx_subsy = 0;
5461 }
5462}
5463
252b5132
RH		 5464arelent *
5465tc_gen_reloc (section, fixp)
ab9da554 5466 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5467 fixS *fixp;
5468{
5469 arelent *rel;
5470 bfd_reloc_code_real_type code;
5471
5472 switch (fixp->fx_r_type)
5473 {
3e73aa7c
JH		 5474 case BFD_RELOC_X86_64_PLT32:
5475 case BFD_RELOC_X86_64_GOT32:
5476 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5477 case BFD_RELOC_386_PLT32:
5478 case BFD_RELOC_386_GOT32:
5479 case BFD_RELOC_386_GOTOFF:
5480 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5481 case BFD_RELOC_386_TLS_GD:
5482 case BFD_RELOC_386_TLS_LDM:
5483 case BFD_RELOC_386_TLS_LDO_32:
5484 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5485 case BFD_RELOC_386_TLS_IE:
5486 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5487 case BFD_RELOC_386_TLS_LE_32:
5488 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5489 case BFD_RELOC_X86_64_TLSGD:
5490 case BFD_RELOC_X86_64_TLSLD:
5491 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5492 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5493 case BFD_RELOC_X86_64_GOTTPOFF:
5494 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5495 case BFD_RELOC_X86_64_TPOFF64:
5496 case BFD_RELOC_X86_64_GOTOFF64:
5497 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5498 case BFD_RELOC_RVA:
5499 case BFD_RELOC_VTABLE_ENTRY:
5500 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5501#ifdef TE_PE
5502 case BFD_RELOC_32_SECREL:
5503#endif
252b5132
RH		 5504 code = fixp->fx_r_type;
5505 break;
dbbaec26
L		 5506 case BFD_RELOC_X86_64_32S:
5507 if (!fixp->fx_pcrel)
5508 {
5509 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5510 code = fixp->fx_r_type;
5511 break;
5512 }
252b5132 5513 default:
93382f6d 5514 if (fixp->fx_pcrel)
252b5132 5515 {
93382f6d
AM		 5516 switch (fixp->fx_size)
5517 {
5518 default:
b091f402
AM		 5519 as_bad_where (fixp->fx_file, fixp->fx_line,
5520 _("can not do %d byte pc-relative relocation"),
5521 fixp->fx_size);
93382f6d
AM		 5522 code = BFD_RELOC_32_PCREL;
5523 break;
5524 case 1: code = BFD_RELOC_8_PCREL; break;
5525 case 2: code = BFD_RELOC_16_PCREL; break;
5526 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5527#ifdef BFD64
5528 case 8: code = BFD_RELOC_64_PCREL; break;
5529#endif
93382f6d
AM		 5530 }
5531 }
5532 else
5533 {
5534 switch (fixp->fx_size)
5535 {
5536 default:
b091f402
AM		 5537 as_bad_where (fixp->fx_file, fixp->fx_line,
5538 _("can not do %d byte relocation"),
5539 fixp->fx_size);
93382f6d
AM		 5540 code = BFD_RELOC_32;
5541 break;
5542 case 1: code = BFD_RELOC_8; break;
5543 case 2: code = BFD_RELOC_16; break;
5544 case 4: code = BFD_RELOC_32; break;
937149dd 5545#ifdef BFD64
3e73aa7c 5546 case 8: code = BFD_RELOC_64; break;
937149dd 5547#endif
93382f6d 5548 }
252b5132
RH		 5549 }
5550 break;
5551 }
252b5132 5552
d6ab8113 5553 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5554 && GOT_symbol
5555 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5556 {
d6ab8113
JB		 5557 if (flag_code != CODE_64BIT)
5558 code = BFD_RELOC_386_GOTPC;
5559 else
5560 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5561 }
252b5132
RH		 5562
5563 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5564 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5565 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5566
5567 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5568
3e73aa7c
JH		 5569 if (!use_rela_relocations)
5570 {
5571 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5572 vtable entry to be used in the relocation's section offset. */
5573 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5574 rel->address = fixp->fx_offset;
252b5132 5575
c6682705 5576 rel->addend = 0;
3e73aa7c
JH		 5577 }
5578 /* Use the rela in 64bit mode. */
252b5132 5579 else
3e73aa7c 5580 {
062cd5e7
AS		 5581 if (!fixp->fx_pcrel)
5582 rel->addend = fixp->fx_offset;
5583 else
5584 switch (code)
5585 {
5586 case BFD_RELOC_X86_64_PLT32:
5587 case BFD_RELOC_X86_64_GOT32:
5588 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5589 case BFD_RELOC_X86_64_TLSGD:
5590 case BFD_RELOC_X86_64_TLSLD:
5591 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5592 rel->addend = fixp->fx_offset - fixp->fx_size;
5593 break;
5594 default:
5595 rel->addend = (section->vma
5596 - fixp->fx_size
5597 + fixp->fx_addnumber
5598 + md_pcrel_from (fixp));
5599 break;
5600 }
3e73aa7c
JH		 5601 }
5602
252b5132
RH		 5603 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5604 if (rel->howto == NULL)
5605 {
5606 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5607 _("cannot represent relocation type %s"),
252b5132
RH		 5608 bfd_get_reloc_code_name (code));
5609 /* Set howto to a garbage value so that we can keep going. */
5610 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5611 assert (rel->howto != NULL);
5612 }
5613
5614 return rel;
5615}
5616
64a0c779
DN		 5617\f
5618/* Parse operands using Intel syntax. This implements a recursive descent
5619 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5620 Programmer's Guide.
5621
5622 FIXME: We do not recognize the full operand grammar defined in the MASM
5623 documentation. In particular, all the structure/union and
5624 high-level macro operands are missing.
5625
5626 Uppercase words are terminals, lower case words are non-terminals.
5627 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5628 bars '|' denote choices. Most grammar productions are implemented in
5629 functions called 'intel_<production>'.
5630
5631 Initial production is 'expr'.
5632
9306ca4a 5633 addOp + | -
64a0c779
DN		 5634
5635 alpha [a-zA-Z]
5636
9306ca4a
JB		 5637 binOp & | AND | \| | OR | ^ | XOR
5638
64a0c779
DN		 5639 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5640
5641 constant digits [[ radixOverride ]]
5642
9306ca4a 5643 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5644
5645 digits decdigit
b77a7acd
AJ		 5646 | digits decdigit
5647 | digits hexdigit
64a0c779
DN		 5648
5649 decdigit [0-9]
5650
9306ca4a
JB		 5651 e04 e04 addOp e05
5652 | e05
5653
5654 e05 e05 binOp e06
b77a7acd 5655 | e06
64a0c779
DN		 5656
5657 e06 e06 mulOp e09
b77a7acd 5658 | e09
64a0c779
DN		 5659
5660 e09 OFFSET e10
a724f0f4
JB		 5661 | SHORT e10
5662 | + e10
5663 | - e10
9306ca4a
JB		 5664 | ~ e10
5665 | NOT e10
64a0c779
DN		 5666 | e09 PTR e10
5667 | e09 : e10
5668 | e10
5669
5670 e10 e10 [ expr ]
b77a7acd 5671 | e11
64a0c779
DN		 5672
5673 e11 ( expr )
b77a7acd 5674 | [ expr ]
64a0c779
DN		 5675 | constant
5676 | dataType
5677 | id
5678 | $
5679 | register
5680
a724f0f4 5681 => expr expr cmpOp e04
9306ca4a 5682 | e04
64a0c779
DN		 5683
5684 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5685 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5686
5687 hexdigit a | b | c | d | e | f
b77a7acd 5688 | A | B | C | D | E | F
64a0c779
DN		 5689
5690 id alpha
b77a7acd 5691 | id alpha
64a0c779
DN		 5692 | id decdigit
5693
9306ca4a 5694 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5695
5696 quote " | '
5697
5698 register specialRegister
b77a7acd 5699 | gpRegister
64a0c779
DN		 5700 | byteRegister
5701
5702 segmentRegister CS | DS | ES | FS | GS | SS
5703
9306ca4a 5704 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5705 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5706 | TR3 | TR4 | TR5 | TR6 | TR7
5707
64a0c779
DN		 5708 We simplify the grammar in obvious places (e.g., register parsing is
5709 done by calling parse_register) and eliminate immediate left recursion
5710 to implement a recursive-descent parser.
5711
a724f0f4
JB		 5712 expr e04 expr'
5713
5714 expr' cmpOp e04 expr'
5715 | Empty
9306ca4a
JB		 5716
5717 e04 e05 e04'
5718
5719 e04' addOp e05 e04'
5720 | Empty
64a0c779
DN		 5721
5722 e05 e06 e05'
5723
9306ca4a 5724 e05' binOp e06 e05'
b77a7acd 5725 | Empty
64a0c779
DN		 5726
5727 e06 e09 e06'
5728
5729 e06' mulOp e09 e06'
b77a7acd 5730 | Empty
64a0c779
DN		 5731
5732 e09 OFFSET e10 e09'
a724f0f4
JB		 5733 | SHORT e10'
5734 | + e10'
5735 | - e10'
5736 | ~ e10'
5737 | NOT e10'
b77a7acd 5738 | e10 e09'
64a0c779
DN		 5739
5740 e09' PTR e10 e09'
b77a7acd 5741 | : e10 e09'
64a0c779
DN		 5742 | Empty
5743
5744 e10 e11 e10'
5745
5746 e10' [ expr ] e10'
b77a7acd 5747 | Empty
64a0c779
DN		 5748
5749 e11 ( expr )
b77a7acd 5750 | [ expr ]
64a0c779
DN		 5751 | BYTE
5752 | WORD
5753 | DWORD
9306ca4a 5754 | FWORD
64a0c779 5755 | QWORD
9306ca4a
JB		 5756 | TBYTE
5757 | OWORD
5758 | XMMWORD
64a0c779
DN		 5759 | .
5760 | $
5761 | register
5762 | id
5763 | constant */
5764
5765/* Parsing structure for the intel syntax parser. Used to implement the
5766 semantic actions for the operand grammar. */
5767struct intel_parser_s
5768 {
5769 char *op_string; /* The string being parsed. */
5770 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5771 int op_modifier; /* Operand modifier. */
64a0c779 5772 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5773 int in_offset; /* >=1 if parsing operand of offset. */
5774 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5775 const reg_entry *reg; /* Last register reference found. */
5776 char *disp; /* Displacement string being built. */
a724f0f4 5777 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5778 };
5779
5780static struct intel_parser_s intel_parser;
5781
5782/* Token structure for parsing intel syntax. */
5783struct intel_token
5784 {
5785 int code; /* Token code. */
5786 const reg_entry *reg; /* Register entry for register tokens. */
5787 char *str; /* String representation. */
5788 };
5789
5790static struct intel_token cur_token, prev_token;
5791
50705ef4
AM		 5792/* Token codes for the intel parser. Since T_SHORT is already used
5793 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5794#define T_NIL -1
5795#define T_CONST 1
5796#define T_REG 2
5797#define T_BYTE 3
5798#define T_WORD 4
9306ca4a
JB		 5799#define T_DWORD 5
5800#define T_FWORD 6
5801#define T_QWORD 7
5802#define T_TBYTE 8
5803#define T_XMMWORD 9
50705ef4 5804#undef T_SHORT
9306ca4a
JB		 5805#define T_SHORT 10
5806#define T_OFFSET 11
5807#define T_PTR 12
5808#define T_ID 13
5809#define T_SHL 14
5810#define T_SHR 15
64a0c779
DN		 5811
5812/* Prototypes for intel parser functions. */
5813static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5814static void intel_get_token PARAMS ((void));
5815static void intel_putback_token PARAMS ((void));
5816static int intel_expr PARAMS ((void));
9306ca4a 5817static int intel_e04 PARAMS ((void));
cce0cbdc 5818static int intel_e05 PARAMS ((void));
cce0cbdc 5819static int intel_e06 PARAMS ((void));
cce0cbdc 5820static int intel_e09 PARAMS ((void));
a724f0f4 5821static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5822static int intel_e10 PARAMS ((void));
cce0cbdc 5823static int intel_e11 PARAMS ((void));
64a0c779 5824
64a0c779
DN		 5825static int
5826i386_intel_operand (operand_string, got_a_float)
5827 char *operand_string;
5828 int got_a_float;
5829{
5830 int ret;
5831 char *p;
5832
a724f0f4
JB		 5833 p = intel_parser.op_string = xstrdup (operand_string);
5834 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5835
5836 for (;;)
64a0c779 5837 {
a724f0f4
JB		 5838 /* Initialize token holders. */
5839 cur_token.code = prev_token.code = T_NIL;
5840 cur_token.reg = prev_token.reg = NULL;
5841 cur_token.str = prev_token.str = NULL;
5842
5843 /* Initialize parser structure. */
5844 intel_parser.got_a_float = got_a_float;
5845 intel_parser.op_modifier = 0;
5846 intel_parser.is_mem = 0;
5847 intel_parser.in_offset = 0;
5848 intel_parser.in_bracket = 0;
5849 intel_parser.reg = NULL;
5850 intel_parser.disp[0] = '\0';
5851 intel_parser.next_operand = NULL;
5852
5853 /* Read the first token and start the parser. */
5854 intel_get_token ();
5855 ret = intel_expr ();
5856
5857 if (!ret)
5858 break;
5859
9306ca4a
JB		 5860 if (cur_token.code != T_NIL)
5861 {
5862 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5863 current_templates->start->name, cur_token.str);
5864 ret = 0;
5865 }
64a0c779
DN		 5866 /* If we found a memory reference, hand it over to i386_displacement
5867 to fill in the rest of the operand fields. */
9306ca4a 5868 else if (intel_parser.is_mem)
64a0c779
DN		 5869 {
5870 if ((i.mem_operands == 1
5871 && (current_templates->start->opcode_modifier & IsString) == 0)
5872 || i.mem_operands == 2)
5873 {
5874 as_bad (_("too many memory references for '%s'"),
5875 current_templates->start->name);
5876 ret = 0;
5877 }
5878 else
5879 {
5880 char *s = intel_parser.disp;
5881 i.mem_operands++;
5882
a724f0f4
JB		 5883 if (!quiet_warnings && intel_parser.is_mem < 0)
5884 /* See the comments in intel_bracket_expr. */
5885 as_warn (_("Treating `%s' as memory reference"), operand_string);
5886
64a0c779
DN		 5887 /* Add the displacement expression. */
5888 if (*s != '\0')
a4622f40
AM		 5889 ret = i386_displacement (s, s + strlen (s));
5890 if (ret)
a724f0f4
JB		 5891 {
5892 /* Swap base and index in 16-bit memory operands like
5893 [si+bx]. Since i386_index_check is also used in AT&T
5894 mode we have to do that here. */
5895 if (i.base_reg
5896 && i.index_reg
5897 && (i.base_reg->reg_type & Reg16)
5898 && (i.index_reg->reg_type & Reg16)
5899 && i.base_reg->reg_num >= 6
5900 && i.index_reg->reg_num < 6)
5901 {
5902 const reg_entry *base = i.index_reg;
5903
5904 i.index_reg = i.base_reg;
5905 i.base_reg = base;
5906 }
5907 ret = i386_index_check (operand_string);
5908 }
64a0c779
DN		 5909 }
5910 }
5911
5912 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5913 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5914 || intel_parser.reg == NULL)
5915 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5916
5917 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5918 ret = 0;
5919 if (!ret || !intel_parser.next_operand)
5920 break;
5921 intel_parser.op_string = intel_parser.next_operand;
5922 this_operand = i.operands++;
64a0c779
DN		 5923 }
5924
5925 free (p);
5926 free (intel_parser.disp);
5927
5928 return ret;
5929}
5930
a724f0f4
JB		 5931#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5932
5933/* expr e04 expr'
5934
5935 expr' cmpOp e04 expr'
5936 | Empty */
64a0c779
DN		 5937static int
5938intel_expr ()
5939{
a724f0f4
JB		 5940 /* XXX Implement the comparison operators. */
5941 return intel_e04 ();
9306ca4a
JB		 5942}
5943
a724f0f4 5944/* e04 e05 e04'
9306ca4a 5945
a724f0f4 5946 e04' addOp e05 e04'
9306ca4a
JB		 5947 | Empty */
5948static int
5949intel_e04 ()
5950{
a724f0f4 5951 int nregs = -1;
9306ca4a 5952
a724f0f4 5953 for (;;)
9306ca4a 5954 {
a724f0f4
JB		 5955 if (!intel_e05())
5956 return 0;
9306ca4a 5957
a724f0f4
JB		 5958 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5959 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5960
a724f0f4
JB		 5961 if (cur_token.code == '+')
5962 nregs = -1;
5963 else if (cur_token.code == '-')
5964 nregs = NUM_ADDRESS_REGS;
5965 else
5966 return 1;
64a0c779 5967
a724f0f4
JB		 5968 strcat (intel_parser.disp, cur_token.str);
5969 intel_match_token (cur_token.code);
5970 }
64a0c779
DN		 5971}
5972
64a0c779
DN		 5973/* e05 e06 e05'
5974
9306ca4a 5975 e05' binOp e06 e05'
64a0c779
DN		 5976 | Empty */
5977static int
5978intel_e05 ()
5979{
a724f0f4 5980 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5981
a724f0f4 5982 for (;;)
64a0c779 5983 {
a724f0f4
JB		 5984 if (!intel_e06())
5985 return 0;
5986
5987 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5988 {
5989 char str[2];
5990
5991 str[0] = cur_token.code;
5992 str[1] = 0;
5993 strcat (intel_parser.disp, str);
5994 }
5995 else
5996 break;
9306ca4a 5997
64a0c779
DN		 5998 intel_match_token (cur_token.code);
5999
a724f0f4
JB		 6000 if (nregs < 0)
6001 nregs = ~nregs;
64a0c779 6002 }
a724f0f4
JB		 6003 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6004 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6005 return 1;
4a1805b1 6006}
64a0c779
DN		 6007
6008/* e06 e09 e06'
6009
6010 e06' mulOp e09 e06'
b77a7acd 6011 | Empty */
64a0c779
DN		 6012static int
6013intel_e06 ()
6014{
a724f0f4 6015 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6016
a724f0f4 6017 for (;;)
64a0c779 6018 {
a724f0f4
JB		 6019 if (!intel_e09())
6020 return 0;
9306ca4a 6021
a724f0f4
JB		 6022 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6023 {
6024 char str[2];
9306ca4a 6025
a724f0f4
JB		 6026 str[0] = cur_token.code;
6027 str[1] = 0;
6028 strcat (intel_parser.disp, str);
6029 }
6030 else if (cur_token.code == T_SHL)
6031 strcat (intel_parser.disp, "<<");
6032 else if (cur_token.code == T_SHR)
6033 strcat (intel_parser.disp, ">>");
6034 else
6035 break;
9306ca4a 6036
a724f0f4 6037 intel_match_token (cur_token.code);
64a0c779 6038
a724f0f4
JB		 6039 if (nregs < 0)
6040 nregs = ~nregs;
64a0c779 6041 }
a724f0f4
JB		 6042 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6043 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6044 return 1;
64a0c779
DN		 6045}
6046
a724f0f4
JB		 6047/* e09 OFFSET e09
6048 | SHORT e09
6049 | + e09
6050 | - e09
6051 | ~ e09
6052 | NOT e09
9306ca4a
JB		 6053 | e10 e09'
6054
64a0c779 6055 e09' PTR e10 e09'
b77a7acd 6056 | : e10 e09'
64a0c779
DN		 6057 | Empty */
6058static int
6059intel_e09 ()
6060{
a724f0f4
JB		 6061 int nregs = ~NUM_ADDRESS_REGS;
6062 int in_offset = 0;
6063
6064 for (;;)
64a0c779 6065 {
a724f0f4
JB		 6066 /* Don't consume constants here. */
6067 if (cur_token.code == '+' || cur_token.code == '-')
6068 {
6069 /* Need to look one token ahead - if the next token
6070 is a constant, the current token is its sign. */
6071 int next_code;
6072
6073 intel_match_token (cur_token.code);
6074 next_code = cur_token.code;
6075 intel_putback_token ();
6076 if (next_code == T_CONST)
6077 break;
6078 }
6079
6080 /* e09 OFFSET e09 */
6081 if (cur_token.code == T_OFFSET)
6082 {
6083 if (!in_offset++)
6084 ++intel_parser.in_offset;
6085 }
6086
6087 /* e09 SHORT e09 */
6088 else if (cur_token.code == T_SHORT)
6089 intel_parser.op_modifier |= 1 << T_SHORT;
6090
6091 /* e09 + e09 */
6092 else if (cur_token.code == '+')
6093 strcat (intel_parser.disp, "+");
6094
6095 /* e09 - e09
6096 | ~ e09
6097 | NOT e09 */
6098 else if (cur_token.code == '-' || cur_token.code == '~')
6099 {
6100 char str[2];
64a0c779 6101
a724f0f4
JB		 6102 if (nregs < 0)
6103 nregs = ~nregs;
6104 str[0] = cur_token.code;
6105 str[1] = 0;
6106 strcat (intel_parser.disp, str);
6107 }
6108
6109 /* e09 e10 e09' */
6110 else
6111 break;
6112
6113 intel_match_token (cur_token.code);
64a0c779
DN		 6114 }
6115
a724f0f4 6116 for (;;)
9306ca4a 6117 {
a724f0f4
JB		 6118 if (!intel_e10 ())
6119 return 0;
9306ca4a 6120
a724f0f4
JB		 6121 /* e09' PTR e10 e09' */
6122 if (cur_token.code == T_PTR)
6123 {
6124 char suffix;
9306ca4a 6125
a724f0f4
JB		 6126 if (prev_token.code == T_BYTE)
6127 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6128
a724f0f4
JB		 6129 else if (prev_token.code == T_WORD)
6130 {
6131 if (current_templates->start->name[0] == 'l'
6132 && current_templates->start->name[2] == 's'
6133 && current_templates->start->name[3] == 0)
6134 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6135 else if (intel_parser.got_a_float == 2) /* "fi..." */
6136 suffix = SHORT_MNEM_SUFFIX;
6137 else
6138 suffix = WORD_MNEM_SUFFIX;
6139 }
64a0c779 6140
a724f0f4
JB		 6141 else if (prev_token.code == T_DWORD)
6142 {
6143 if (current_templates->start->name[0] == 'l'
6144 && current_templates->start->name[2] == 's'
6145 && current_templates->start->name[3] == 0)
6146 suffix = WORD_MNEM_SUFFIX;
6147 else if (flag_code == CODE_16BIT
6148 && (current_templates->start->opcode_modifier
6149 & (Jump|JumpDword|JumpInterSegment)))
6150 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6151 else if (intel_parser.got_a_float == 1) /* "f..." */
6152 suffix = SHORT_MNEM_SUFFIX;
6153 else
6154 suffix = LONG_MNEM_SUFFIX;
6155 }
9306ca4a 6156
a724f0f4
JB		 6157 else if (prev_token.code == T_FWORD)
6158 {
6159 if (current_templates->start->name[0] == 'l'
6160 && current_templates->start->name[2] == 's'
6161 && current_templates->start->name[3] == 0)
6162 suffix = LONG_MNEM_SUFFIX;
6163 else if (!intel_parser.got_a_float)
6164 {
6165 if (flag_code == CODE_16BIT)
6166 add_prefix (DATA_PREFIX_OPCODE);
6167 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6168 }
6169 else
6170 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6171 }
64a0c779 6172
a724f0f4
JB		 6173 else if (prev_token.code == T_QWORD)
6174 {
6175 if (intel_parser.got_a_float == 1) /* "f..." */
6176 suffix = LONG_MNEM_SUFFIX;
6177 else
6178 suffix = QWORD_MNEM_SUFFIX;
6179 }
64a0c779 6180
a724f0f4
JB		 6181 else if (prev_token.code == T_TBYTE)
6182 {
6183 if (intel_parser.got_a_float == 1)
6184 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6185 else
6186 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6187 }
9306ca4a 6188
a724f0f4 6189 else if (prev_token.code == T_XMMWORD)
9306ca4a 6190 {
a724f0f4
JB		 6191 /* XXX ignored for now, but accepted since gcc uses it */
6192 suffix = 0;
9306ca4a 6193 }
64a0c779 6194
f16b83df 6195 else
a724f0f4
JB		 6196 {
6197 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6198 return 0;
6199 }
6200
6201 if (current_templates->start->base_opcode == 0x8d /* lea */)
6202 ;
6203 else if (!i.suffix)
6204 i.suffix = suffix;
6205 else if (i.suffix != suffix)
6206 {
6207 as_bad (_("Conflicting operand modifiers"));
6208 return 0;
6209 }
64a0c779 6210
9306ca4a
JB		 6211 }
6212
a724f0f4
JB		 6213 /* e09' : e10 e09' */
6214 else if (cur_token.code == ':')
9306ca4a 6215 {
a724f0f4
JB		 6216 if (prev_token.code != T_REG)
6217 {
6218 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6219 segment/group identifier (which we don't have), using comma
6220 as the operand separator there is even less consistent, since
6221 there all branches only have a single operand. */
6222 if (this_operand != 0
6223 || intel_parser.in_offset
6224 || intel_parser.in_bracket
6225 || (!(current_templates->start->opcode_modifier
6226 & (Jump|JumpDword|JumpInterSegment))
6227 && !(current_templates->start->operand_types[0]
6228 & JumpAbsolute)))
6229 return intel_match_token (T_NIL);
6230 /* Remember the start of the 2nd operand and terminate 1st
6231 operand here.
6232 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6233 another expression), but it gets at least the simplest case
6234 (a plain number or symbol on the left side) right. */
6235 intel_parser.next_operand = intel_parser.op_string;
6236 *--intel_parser.op_string = '\0';
6237 return intel_match_token (':');
6238 }
9306ca4a 6239 }
64a0c779 6240
a724f0f4 6241 /* e09' Empty */
64a0c779 6242 else
a724f0f4 6243 break;
64a0c779 6244
a724f0f4
JB		 6245 intel_match_token (cur_token.code);
6246
6247 }
6248
6249 if (in_offset)
6250 {
6251 --intel_parser.in_offset;
6252 if (nregs < 0)
6253 nregs = ~nregs;
6254 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6255 {
a724f0f4 6256 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6257 return 0;
6258 }
a724f0f4
JB		 6259 intel_parser.op_modifier |= 1 << T_OFFSET;
6260 }
9306ca4a 6261
a724f0f4
JB		 6262 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6263 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6264 return 1;
6265}
64a0c779 6266
a724f0f4
JB		 6267static int
6268intel_bracket_expr ()
6269{
6270 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6271 const char *start = intel_parser.op_string;
6272 int len;
6273
6274 if (i.op[this_operand].regs)
6275 return intel_match_token (T_NIL);
6276
6277 intel_match_token ('[');
6278
6279 /* Mark as a memory operand only if it's not already known to be an
6280 offset expression. If it's an offset expression, we need to keep
6281 the brace in. */
6282 if (!intel_parser.in_offset)
6283 {
6284 ++intel_parser.in_bracket;
6285 /* Unfortunately gas always diverged from MASM in a respect that can't
6286 be easily fixed without risking to break code sequences likely to be
6287 encountered (the testsuite even check for this): MASM doesn't consider
6288 an expression inside brackets unconditionally as a memory reference.
6289 When that is e.g. a constant, an offset expression, or the sum of the
6290 two, this is still taken as a constant load. gas, however, always
6291 treated these as memory references. As a compromise, we'll try to make
6292 offset expressions inside brackets work the MASM way (since that's
6293 less likely to be found in real world code), but make constants alone
6294 continue to work the traditional gas way. In either case, issue a
6295 warning. */
6296 intel_parser.op_modifier &= ~was_offset;
64a0c779 6297 }
a724f0f4
JB		 6298 else
6299 strcat (intel_parser.disp, "[");
6300
6301 /* Add a '+' to the displacement string if necessary. */
6302 if (*intel_parser.disp != '\0'
6303 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6304 strcat (intel_parser.disp, "+");
64a0c779 6305
a724f0f4
JB		 6306 if (intel_expr ()
6307 && (len = intel_parser.op_string - start - 1,
6308 intel_match_token (']')))
64a0c779 6309 {
a724f0f4
JB		 6310 /* Preserve brackets when the operand is an offset expression. */
6311 if (intel_parser.in_offset)
6312 strcat (intel_parser.disp, "]");
6313 else
6314 {
6315 --intel_parser.in_bracket;
6316 if (i.base_reg || i.index_reg)
6317 intel_parser.is_mem = 1;
6318 if (!intel_parser.is_mem)
6319 {
6320 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6321 /* Defer the warning until all of the operand was parsed. */
6322 intel_parser.is_mem = -1;
6323 else if (!quiet_warnings)
6324 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6325 }
6326 }
6327 intel_parser.op_modifier |= was_offset;
64a0c779 6328
a724f0f4 6329 return 1;
64a0c779 6330 }
a724f0f4 6331 return 0;
64a0c779
DN		 6332}
6333
6334/* e10 e11 e10'
6335
6336 e10' [ expr ] e10'
b77a7acd 6337 | Empty */
64a0c779
DN		 6338static int
6339intel_e10 ()
6340{
a724f0f4
JB		 6341 if (!intel_e11 ())
6342 return 0;
64a0c779 6343
a724f0f4 6344 while (cur_token.code == '[')
64a0c779 6345 {
a724f0f4 6346 if (!intel_bracket_expr ())
21d6c4af 6347 return 0;
64a0c779
DN		 6348 }
6349
a724f0f4 6350 return 1;
64a0c779
DN		 6351}
6352
64a0c779 6353/* e11 ( expr )
b77a7acd 6354 | [ expr ]
64a0c779
DN		 6355 | BYTE
6356 | WORD
6357 | DWORD
9306ca4a 6358 | FWORD
64a0c779 6359 | QWORD
9306ca4a
JB		 6360 | TBYTE
6361 | OWORD
6362 | XMMWORD
4a1805b1 6363 | $
64a0c779
DN		 6364 | .
6365 | register
6366 | id
6367 | constant */
6368static int
6369intel_e11 ()
6370{
a724f0f4 6371 switch (cur_token.code)
64a0c779 6372 {
a724f0f4
JB		 6373 /* e11 ( expr ) */
6374 case '(':
64a0c779
DN		 6375 intel_match_token ('(');
6376 strcat (intel_parser.disp, "(");
6377
6378 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6379 {
6380 strcat (intel_parser.disp, ")");
6381 return 1;
6382 }
a724f0f4 6383 return 0;
4a1805b1 6384
a724f0f4
JB		 6385 /* e11 [ expr ] */
6386 case '[':
6387 /* Operands for jump/call inside brackets denote absolute addresses.
6388 XXX This shouldn't be needed anymore (or if it should rather live
6389 in intel_bracket_expr). */
9306ca4a
JB		 6390 if (current_templates->start->opcode_modifier
6391 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6392 i.types[this_operand] |= JumpAbsolute;
6393
a724f0f4 6394 return intel_bracket_expr ();
64a0c779 6395
a724f0f4
JB		 6396 /* e11 $
6397 | . */
6398 case '.':
64a0c779
DN		 6399 strcat (intel_parser.disp, cur_token.str);
6400 intel_match_token (cur_token.code);
21d6c4af
DN		 6401
6402 /* Mark as a memory operand only if it's not already known to be an
6403 offset expression. */
a724f0f4 6404 if (!intel_parser.in_offset)
21d6c4af 6405 intel_parser.is_mem = 1;
64a0c779
DN		 6406
6407 return 1;
64a0c779 6408
a724f0f4
JB		 6409 /* e11 register */
6410 case T_REG:
6411 {
6412 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6413
a724f0f4 6414 intel_match_token (T_REG);
64a0c779 6415
a724f0f4
JB		 6416 /* Check for segment change. */
6417 if (cur_token.code == ':')
6418 {
6419 if (!(reg->reg_type & (SReg2 | SReg3)))
6420 {
6421 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6422 return 0;
6423 }
6424 else if (i.seg[i.mem_operands])
6425 as_warn (_("Extra segment override ignored"));
6426 else
6427 {
6428 if (!intel_parser.in_offset)
6429 intel_parser.is_mem = 1;
6430 switch (reg->reg_num)
6431 {
6432 case 0:
6433 i.seg[i.mem_operands] = &es;
6434 break;
6435 case 1:
6436 i.seg[i.mem_operands] = &cs;
6437 break;
6438 case 2:
6439 i.seg[i.mem_operands] = &ss;
6440 break;
6441 case 3:
6442 i.seg[i.mem_operands] = &ds;
6443 break;
6444 case 4:
6445 i.seg[i.mem_operands] = &fs;
6446 break;
6447 case 5:
6448 i.seg[i.mem_operands] = &gs;
6449 break;
6450 }
6451 }
6452 }
64a0c779 6453
a724f0f4
JB		 6454 /* Not a segment register. Check for register scaling. */
6455 else if (cur_token.code == '*')
6456 {
6457 if (!intel_parser.in_bracket)
6458 {
6459 as_bad (_("Register scaling only allowed in memory operands"));
6460 return 0;
6461 }
64a0c779 6462
a724f0f4
JB		 6463 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6464 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6465 else if (i.index_reg)
6466 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6467
a724f0f4
JB		 6468 /* What follows must be a valid scale. */
6469 intel_match_token ('*');
6470 i.index_reg = reg;
6471 i.types[this_operand] |= BaseIndex;
64a0c779 6472
a724f0f4
JB		 6473 /* Set the scale after setting the register (otherwise,
6474 i386_scale will complain) */
6475 if (cur_token.code == '+' || cur_token.code == '-')
6476 {
6477 char *str, sign = cur_token.code;
6478 intel_match_token (cur_token.code);
6479 if (cur_token.code != T_CONST)
6480 {
6481 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6482 cur_token.str);
6483 return 0;
6484 }
6485 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6486 strcpy (str + 1, cur_token.str);
6487 *str = sign;
6488 if (!i386_scale (str))
6489 return 0;
6490 free (str);
6491 }
6492 else if (!i386_scale (cur_token.str))
64a0c779 6493 return 0;
a724f0f4
JB		 6494 intel_match_token (cur_token.code);
6495 }
64a0c779 6496
a724f0f4
JB		 6497 /* No scaling. If this is a memory operand, the register is either a
6498 base register (first occurrence) or an index register (second
6499 occurrence). */
6500 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6501 {
64a0c779 6502
a724f0f4
JB		 6503 if (!i.base_reg)
6504 i.base_reg = reg;
6505 else if (!i.index_reg)
6506 i.index_reg = reg;
6507 else
6508 {
6509 as_bad (_("Too many register references in memory operand"));
6510 return 0;
6511 }
64a0c779 6512
a724f0f4
JB		 6513 i.types[this_operand] |= BaseIndex;
6514 }
4a1805b1 6515
a724f0f4
JB		 6516 /* Offset modifier. Add the register to the displacement string to be
6517 parsed as an immediate expression after we're done. */
6518 else if (intel_parser.in_offset)
6519 {
6520 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6521 strcat (intel_parser.disp, reg->reg_name);
6522 }
64a0c779 6523
a724f0f4
JB		 6524 /* It's neither base nor index nor offset. */
6525 else if (!intel_parser.is_mem)
6526 {
6527 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6528 i.op[this_operand].regs = reg;
6529 i.reg_operands++;
6530 }
6531 else
6532 {
6533 as_bad (_("Invalid use of register"));
6534 return 0;
6535 }
64a0c779 6536
a724f0f4
JB		 6537 /* Since registers are not part of the displacement string (except
6538 when we're parsing offset operands), we may need to remove any
6539 preceding '+' from the displacement string. */
6540 if (*intel_parser.disp != '\0'
6541 && !intel_parser.in_offset)
6542 {
6543 char *s = intel_parser.disp;
6544 s += strlen (s) - 1;
6545 if (*s == '+')
6546 *s = '\0';
6547 }
4a1805b1 6548
a724f0f4
JB		 6549 return 1;
6550 }
6551
6552 /* e11 BYTE
6553 | WORD
6554 | DWORD
6555 | FWORD
6556 | QWORD
6557 | TBYTE
6558 | OWORD
6559 | XMMWORD */
6560 case T_BYTE:
6561 case T_WORD:
6562 case T_DWORD:
6563 case T_FWORD:
6564 case T_QWORD:
6565 case T_TBYTE:
6566 case T_XMMWORD:
6567 intel_match_token (cur_token.code);
64a0c779 6568
a724f0f4
JB		 6569 if (cur_token.code == T_PTR)
6570 return 1;
6571
6572 /* It must have been an identifier. */
6573 intel_putback_token ();
6574 cur_token.code = T_ID;
6575 /* FALLTHRU */
6576
6577 /* e11 id
6578 | constant */
6579 case T_ID:
6580 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6581 {
6582 symbolS *symbolP;
6583
a724f0f4
JB		 6584 /* The identifier represents a memory reference only if it's not
6585 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6586 symbolP = symbol_find(cur_token.str);
6587 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6588 intel_parser.is_mem = 1;
6589 }
a724f0f4 6590 /* FALLTHRU */
64a0c779 6591
a724f0f4
JB		 6592 case T_CONST:
6593 case '-':
6594 case '+':
6595 {
6596 char *save_str, sign = 0;
64a0c779 6597
a724f0f4
JB		 6598 /* Allow constants that start with `+' or `-'. */
6599 if (cur_token.code == '-' || cur_token.code == '+')
6600 {
6601 sign = cur_token.code;
6602 intel_match_token (cur_token.code);
6603 if (cur_token.code != T_CONST)
6604 {
6605 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6606 cur_token.str);
6607 return 0;
6608 }
6609 }
64a0c779 6610
a724f0f4
JB		 6611 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6612 strcpy (save_str + !!sign, cur_token.str);
6613 if (sign)
6614 *save_str = sign;
64a0c779 6615
a724f0f4
JB		 6616 /* Get the next token to check for register scaling. */
6617 intel_match_token (cur_token.code);
64a0c779 6618
a724f0f4
JB		 6619 /* Check if this constant is a scaling factor for an index register. */
6620 if (cur_token.code == '*')
6621 {
6622 if (intel_match_token ('*') && cur_token.code == T_REG)
6623 {
6624 const reg_entry *reg = cur_token.reg;
6625
6626 if (!intel_parser.in_bracket)
6627 {
6628 as_bad (_("Register scaling only allowed in memory operands"));
6629 return 0;
6630 }
6631
6632 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6633 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6634 else if (i.index_reg)
6635 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6636
6637 /* The constant is followed by `* reg', so it must be
6638 a valid scale. */
6639 i.index_reg = reg;
6640 i.types[this_operand] |= BaseIndex;
6641
6642 /* Set the scale after setting the register (otherwise,
6643 i386_scale will complain) */
6644 if (!i386_scale (save_str))
64a0c779 6645 return 0;
a724f0f4
JB		 6646 intel_match_token (T_REG);
6647
6648 /* Since registers are not part of the displacement
6649 string, we may need to remove any preceding '+' from
6650 the displacement string. */
6651 if (*intel_parser.disp != '\0')
6652 {
6653 char *s = intel_parser.disp;
6654 s += strlen (s) - 1;
6655 if (*s == '+')
6656 *s = '\0';
6657 }
6658
6659 free (save_str);
6660
6661 return 1;
6662 }
64a0c779 6663
a724f0f4
JB		 6664 /* The constant was not used for register scaling. Since we have
6665 already consumed the token following `*' we now need to put it
6666 back in the stream. */
64a0c779 6667 intel_putback_token ();
a724f0f4 6668 }
64a0c779 6669
a724f0f4
JB		 6670 /* Add the constant to the displacement string. */
6671 strcat (intel_parser.disp, save_str);
6672 free (save_str);
64a0c779 6673
a724f0f4
JB		 6674 return 1;
6675 }
64a0c779
DN		 6676 }
6677
64a0c779
DN		 6678 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6679 return 0;
6680}
6681
64a0c779
DN		 6682/* Match the given token against cur_token. If they match, read the next
6683 token from the operand string. */
6684static int
6685intel_match_token (code)
e5cb08ac 6686 int code;
64a0c779
DN		 6687{
6688 if (cur_token.code == code)
6689 {
6690 intel_get_token ();
6691 return 1;
6692 }
6693 else
6694 {
0477af35 6695 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6696 return 0;
6697 }
6698}
6699
64a0c779
DN		 6700/* Read a new token from intel_parser.op_string and store it in cur_token. */
6701static void
6702intel_get_token ()
6703{
6704 char *end_op;
6705 const reg_entry *reg;
6706 struct intel_token new_token;
6707
6708 new_token.code = T_NIL;
6709 new_token.reg = NULL;
6710 new_token.str = NULL;
6711
4a1805b1 6712 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6713 cur_token to prev_token. */
6714 if (prev_token.str)
6715 free (prev_token.str);
6716
6717 prev_token = cur_token;
6718
6719 /* Skip whitespace. */
6720 while (is_space_char (*intel_parser.op_string))
6721 intel_parser.op_string++;
6722
6723 /* Return an empty token if we find nothing else on the line. */
6724 if (*intel_parser.op_string == '\0')
6725 {
6726 cur_token = new_token;
6727 return;
6728 }
6729
6730 /* The new token cannot be larger than the remainder of the operand
6731 string. */
a724f0f4 6732 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6733 new_token.str[0] = '\0';
6734
6735 if (strchr ("0123456789", *intel_parser.op_string))
6736 {
6737 char *p = new_token.str;
6738 char *q = intel_parser.op_string;
6739 new_token.code = T_CONST;
6740
6741 /* Allow any kind of identifier char to encompass floating point and
6742 hexadecimal numbers. */
6743 while (is_identifier_char (*q))
6744 *p++ = *q++;
6745 *p = '\0';
6746
6747 /* Recognize special symbol names [0-9][bf]. */
6748 if (strlen (intel_parser.op_string) == 2
4a1805b1 6749 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6750 || intel_parser.op_string[1] == 'f'))
6751 new_token.code = T_ID;
6752 }
6753
64a0c779
DN		 6754 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6755 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6756 {
6757 new_token.code = T_REG;
6758 new_token.reg = reg;
6759
6760 if (*intel_parser.op_string == REGISTER_PREFIX)
6761 {
6762 new_token.str[0] = REGISTER_PREFIX;
6763 new_token.str[1] = '\0';
6764 }
6765
6766 strcat (new_token.str, reg->reg_name);
6767 }
6768
6769 else if (is_identifier_char (*intel_parser.op_string))
6770 {
6771 char *p = new_token.str;
6772 char *q = intel_parser.op_string;
6773
6774 /* A '.' or '$' followed by an identifier char is an identifier.
6775 Otherwise, it's operator '.' followed by an expression. */
6776 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6777 {
9306ca4a
JB		 6778 new_token.code = '.';
6779 new_token.str[0] = '.';
64a0c779
DN		 6780 new_token.str[1] = '\0';
6781 }
6782 else
6783 {
6784 while (is_identifier_char (*q) || *q == '@')
6785 *p++ = *q++;
6786 *p = '\0';
6787
9306ca4a
JB		 6788 if (strcasecmp (new_token.str, "NOT") == 0)
6789 new_token.code = '~';
6790
6791 else if (strcasecmp (new_token.str, "MOD") == 0)
6792 new_token.code = '%';
6793
6794 else if (strcasecmp (new_token.str, "AND") == 0)
6795 new_token.code = '&';
6796
6797 else if (strcasecmp (new_token.str, "OR") == 0)
6798 new_token.code = '|';
6799
6800 else if (strcasecmp (new_token.str, "XOR") == 0)
6801 new_token.code = '^';
6802
6803 else if (strcasecmp (new_token.str, "SHL") == 0)
6804 new_token.code = T_SHL;
6805
6806 else if (strcasecmp (new_token.str, "SHR") == 0)
6807 new_token.code = T_SHR;
6808
6809 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6810 new_token.code = T_BYTE;
6811
6812 else if (strcasecmp (new_token.str, "WORD") == 0)
6813 new_token.code = T_WORD;
6814
6815 else if (strcasecmp (new_token.str, "DWORD") == 0)
6816 new_token.code = T_DWORD;
6817
9306ca4a
JB		 6818 else if (strcasecmp (new_token.str, "FWORD") == 0)
6819 new_token.code = T_FWORD;
6820
64a0c779
DN		 6821 else if (strcasecmp (new_token.str, "QWORD") == 0)
6822 new_token.code = T_QWORD;
6823
9306ca4a
JB		 6824 else if (strcasecmp (new_token.str, "TBYTE") == 0
6825 /* XXX remove (gcc still uses it) */
6826 || strcasecmp (new_token.str, "XWORD") == 0)
6827 new_token.code = T_TBYTE;
6828
6829 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6830 || strcasecmp (new_token.str, "OWORD") == 0)
6831 new_token.code = T_XMMWORD;
64a0c779
DN		 6832
6833 else if (strcasecmp (new_token.str, "PTR") == 0)
6834 new_token.code = T_PTR;
6835
6836 else if (strcasecmp (new_token.str, "SHORT") == 0)
6837 new_token.code = T_SHORT;
6838
6839 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6840 {
6841 new_token.code = T_OFFSET;
6842
6843 /* ??? This is not mentioned in the MASM grammar but gcc
6844 makes use of it with -mintel-syntax. OFFSET may be
6845 followed by FLAT: */
6846 if (strncasecmp (q, " FLAT:", 6) == 0)
6847 strcat (new_token.str, " FLAT:");
6848 }
6849
6850 /* ??? This is not mentioned in the MASM grammar. */
6851 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6852 {
6853 new_token.code = T_OFFSET;
6854 if (*q == ':')
6855 strcat (new_token.str, ":");
6856 else
6857 as_bad (_("`:' expected"));
6858 }
64a0c779
DN		 6859
6860 else
6861 new_token.code = T_ID;
6862 }
6863 }
6864
9306ca4a
JB		 6865 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6866 {
6867 new_token.code = *intel_parser.op_string;
6868 new_token.str[0] = *intel_parser.op_string;
6869 new_token.str[1] = '\0';
6870 }
6871
6872 else if (strchr ("<>", *intel_parser.op_string)
6873 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6874 {
6875 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6876 new_token.str[0] = *intel_parser.op_string;
6877 new_token.str[1] = *intel_parser.op_string;
6878 new_token.str[2] = '\0';
6879 }
6880
64a0c779 6881 else
0477af35 6882 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6883
6884 intel_parser.op_string += strlen (new_token.str);
6885 cur_token = new_token;
6886}
6887
64a0c779
DN		 6888/* Put cur_token back into the token stream and make cur_token point to
6889 prev_token. */
6890static void
6891intel_putback_token ()
6892{
a724f0f4
JB		 6893 if (cur_token.code != T_NIL)
6894 {
6895 intel_parser.op_string -= strlen (cur_token.str);
6896 free (cur_token.str);
6897 }
64a0c779 6898 cur_token = prev_token;
4a1805b1 6899
64a0c779
DN		 6900 /* Forget prev_token. */
6901 prev_token.code = T_NIL;
6902 prev_token.reg = NULL;
6903 prev_token.str = NULL;
6904}
54cfded0 6905
a4447b93 6906int
54cfded0
AM		 6907tc_x86_regname_to_dw2regnum (const char *regname)
6908{
6909 unsigned int regnum;
6910 unsigned int regnames_count;
089dfecd 6911 static const char *const regnames_32[] =
54cfded0 6912 {
a4447b93
RH		 6913 "eax", "ecx", "edx", "ebx",
6914 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6915 "eip", "eflags", NULL,
6916 "st0", "st1", "st2", "st3",
6917 "st4", "st5", "st6", "st7",
6918 NULL, NULL,
6919 "xmm0", "xmm1", "xmm2", "xmm3",
6920 "xmm4", "xmm5", "xmm6", "xmm7",
6921 "mm0", "mm1", "mm2", "mm3",
6922 "mm4", "mm5", "mm6", "mm7"
54cfded0 6923 };
089dfecd 6924 static const char *const regnames_64[] =
54cfded0 6925 {
089dfecd
JB		 6926 "rax", "rdx", "rcx", "rbx",
6927 "rsi", "rdi", "rbp", "rsp",
6928 "r8", "r9", "r10", "r11",
54cfded0 6929 "r12", "r13", "r14", "r15",
089dfecd
JB		 6930 "rip",
6931 "xmm0", "xmm1", "xmm2", "xmm3",
6932 "xmm4", "xmm5", "xmm6", "xmm7",
6933 "xmm8", "xmm9", "xmm10", "xmm11",
6934 "xmm12", "xmm13", "xmm14", "xmm15",
6935 "st0", "st1", "st2", "st3",
6936 "st4", "st5", "st6", "st7",
6937 "mm0", "mm1", "mm2", "mm3",
6938 "mm4", "mm5", "mm6", "mm7"
54cfded0 6939 };
089dfecd 6940 const char *const *regnames;
54cfded0
AM		 6941
6942 if (flag_code == CODE_64BIT)
6943 {
6944 regnames = regnames_64;
0cea6190 6945 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6946 }
6947 else
6948 {
6949 regnames = regnames_32;
0cea6190 6950 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6951 }
6952
6953 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6954 if (regnames[regnum] != NULL
6955 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6956 return regnum;
6957
54cfded0
AM		 6958 return -1;
6959}
6960
6961void
6962tc_x86_frame_initial_instructions (void)
6963{
a4447b93
RH		 6964 static unsigned int sp_regno;
6965
6966 if (!sp_regno)
6967 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6968 ? "rsp" : "esp");
6969
6970 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6971 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6972}
d2b2c203
DJ		 6973
6974int
6975i386_elf_section_type (const char *str, size_t len)
6976{
6977 if (flag_code == CODE_64BIT
6978 && len == sizeof ("unwind") - 1
6979 && strncmp (str, "unwind", 6) == 0)
6980 return SHT_X86_64_UNWIND;
6981
6982 return -1;
6983}
bb41ade5
AM		 6984
6985#ifdef TE_PE
6986void
6987tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6988{
6989 expressionS expr;
6990
6991 expr.X_op = O_secrel;
6992 expr.X_add_symbol = symbol;
6993 expr.X_add_number = 0;
6994 emit_expr (&expr, size);
6995}
6996#endif
3b22753a
L		 6997
6998#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6999/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7000
7001int
7002x86_64_section_letter (int letter, char **ptr_msg)
7003{
7004 if (flag_code == CODE_64BIT)
7005 {
7006 if (letter == 'l')
7007 return SHF_X86_64_LARGE;
7008
7009 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7010 }
7011 else
7012 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7013 return -1;
7014}
7015
7016int
7017x86_64_section_word (char *str, size_t len)
7018{
7019 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7020 return SHF_X86_64_LARGE;
7021
7022 return -1;
7023}
7024
7025static void
7026handle_large_common (int small ATTRIBUTE_UNUSED)
7027{
7028 if (flag_code != CODE_64BIT)
7029 {
7030 s_comm_internal (0, elf_common_parse);
7031 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7032 }
7033 else
7034 {
7035 static segT lbss_section;
7036 asection *saved_com_section_ptr = elf_com_section_ptr;
7037 asection *saved_bss_section = bss_section;
7038
7039 if (lbss_section == NULL)
7040 {
7041 flagword applicable;
7042 segT seg = now_seg;
7043 subsegT subseg = now_subseg;
7044
7045 /* The .lbss section is for local .largecomm symbols. */
7046 lbss_section = subseg_new (".lbss", 0);
7047 applicable = bfd_applicable_section_flags (stdoutput);
7048 bfd_set_section_flags (stdoutput, lbss_section,
7049 applicable & SEC_ALLOC);
7050 seg_info (lbss_section)->bss = 1;
7051
7052 subseg_set (seg, subseg);
7053 }
7054
7055 elf_com_section_ptr = &_bfd_elf_large_com_section;
7056 bss_section = lbss_section;
7057
7058 s_comm_internal (0, elf_common_parse);
7059
7060 elf_com_section_ptr = saved_com_section_ptr;
7061 bss_section = saved_bss_section;
7062 }
7063}
7064#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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