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[ARC] Add linker relaxation.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a028026d
KT		 12019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
4 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
5
ac79ff9e
NC		 62019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
7
8 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
9 instructions as UNPREDICTABLE.
10
231097b0
JM		 112019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
12
13 * bpf-desc.c: Regenerated.
14
1d942ae9
JB		 152019-07-17 Jan Beulich <jbeulich@suse.com>
16
17 * i386-gen.c (static_assert): Define.
18 (main): Use it.
19 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
20 (Opcode_Modifier_Num): ... this.
21 (Mem): Delete.
22
dfd69174
JB		 232019-07-16 Jan Beulich <jbeulich@suse.com>
24
25 * i386-gen.c (operand_types): Move RegMem ...
26 (opcode_modifiers): ... here.
27 * i386-opc.h (RegMem): Move to opcode modifer enum.
28 (union i386_operand_type): Move regmem field ...
29 (struct i386_opcode_modifier): ... here.
30 * i386-opc.tbl (RegMem): Define.
31 (mov, movq): Move RegMem on segment, control, debug, and test
32 register flavors.
33 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
34 to non-SSE2AVX flavor.
35 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
36 Move RegMem on register only flavors. Drop IgnoreSize from
37 legacy encoding flavors.
38 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
39 flavors.
40 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
41 register only flavors.
42 (vmovd): Move RegMem and drop IgnoreSize on register only
43 flavor. Change opcode and operand order to store form.
44 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
45
21df382b
JB		 462019-07-16 Jan Beulich <jbeulich@suse.com>
47
48 * i386-gen.c (operand_type_init, operand_types): Replace SReg
49 entries.
50 * i386-opc.h (SReg2, SReg3): Replace by ...
51 (SReg): ... this.
52 (union i386_operand_type): Replace sreg fields.
53 * i386-opc.tbl (mov, ): Use SReg.
54 (push, pop): Likewies. Drop i386 and x86-64 specific segment
55 register flavors.
56 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
57 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
58
3719fd55
JM		 592019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
60
61 * bpf-desc.c: Regenerate.
62 * bpf-opc.c: Likewise.
63 * bpf-opc.h: Likewise.
64
92434a14
JM		 652019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
66
67 * bpf-desc.c: Regenerate.
68 * bpf-opc.c: Likewise.
69
43dd7626
HPN		 702019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
71
72 * arm-dis.c (print_insn_coprocessor): Rename index to
73 index_operand.
74
98602811
JW		 752019-07-05 Kito Cheng <kito.cheng@sifive.com>
76
77 * riscv-opc.c (riscv_insn_types): Add r4 type.
78
79 * riscv-opc.c (riscv_insn_types): Add b and j type.
80
81 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
82 format for sb type and correct s type.
83
01c1ee4a
RS		 842019-07-02 Richard Sandiford <richard.sandiford@arm.com>
85
86 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
87 SVE FMOV alias of FCPY.
88
83adff69
RS		 892019-07-02 Richard Sandiford <richard.sandiford@arm.com>
90
91 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
92 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
93
89418844
RS		 942019-07-02 Richard Sandiford <richard.sandiford@arm.com>
95
96 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
97 registers in an instruction prefixed by MOVPRFX.
98
41be57ca
MM		 992019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
100
101 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
102 sve_size_13 icode to account for variant behaviour of
103 pmull{t,b}.
104 * aarch64-dis-2.c: Regenerate.
105 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
106 sve_size_13 icode to account for variant behaviour of
107 pmull{t,b}.
108 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
109 (OP_SVE_VVV_Q_D): Add new qualifier.
110 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
111 (struct aarch64_opcode): Split pmull{t,b} into those requiring
112 AES and those not.
113
9d3bf266
JB		 1142019-07-01 Jan Beulich <jbeulich@suse.com>
115
116 * opcodes/i386-gen.c (operand_type_init): Remove
117 OPERAND_TYPE_VEC_IMM4 entry.
118 (operand_types): Remove Vec_Imm4.
119 * opcodes/i386-opc.h (Vec_Imm4): Delete.
120 (union i386_operand_type): Remove vec_imm4.
121 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
122 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
123
c3949f43
JB		 1242019-07-01 Jan Beulich <jbeulich@suse.com>
125
126 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
127 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
128 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
129 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
130 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
131 monitorx, mwaitx): Drop ImmExt from operand-less forms.
132 * i386-tbl.h: Re-generate.
133
5641ec01
JB		 1342019-07-01 Jan Beulich <jbeulich@suse.com>
135
136 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
137 register operands.
138 * i386-tbl.h: Re-generate.
139
79dec6b7
JB		 1402019-07-01 Jan Beulich <jbeulich@suse.com>
141
142 * i386-opc.tbl (C): New.
143 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
144 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
145 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
146 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
147 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
148 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
149 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
150 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
151 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
152 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
153 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
154 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
155 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
156 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
157 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
158 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
159 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
160 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
161 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
162 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
163 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
164 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
165 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
166 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
167 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
168 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
169 flavors.
170 * i386-tbl.h: Re-generate.
171
a0a1771e
JB		 1722019-07-01 Jan Beulich <jbeulich@suse.com>
173
174 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
175 register operands.
176 * i386-tbl.h: Re-generate.
177
cd546e7b
JB		 1782019-07-01 Jan Beulich <jbeulich@suse.com>
179
180 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
181 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
182 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
183 * i386-tbl.h: Re-generate.
184
e3bba3fc
JB		 1852019-07-01 Jan Beulich <jbeulich@suse.com>
186
187 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
188 Disp8MemShift from register only templates.
189 * i386-tbl.h: Re-generate.
190
36cc073e
JB		 1912019-07-01 Jan Beulich <jbeulich@suse.com>
192
193 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
194 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
195 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
196 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
197 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
198 EVEX_W_0F11_P_3_M_1): Delete.
199 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
200 EVEX_W_0F11_P_3): New.
201 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
202 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
203 MOD_EVEX_0F11_PREFIX_3 table entries.
204 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
205 PREFIX_EVEX_0F11 table entries.
206 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
207 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
208 EVEX_W_0F11_P_3_M_{0,1} table entries.
209
219920a7
JB		 2102019-07-01 Jan Beulich <jbeulich@suse.com>
211
212 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
213 Delete.
214
e395f487
L		 2152019-06-27 H.J. Lu <hongjiu.lu@intel.com>
216
217 PR binutils/24719
218 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
219 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
220 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
221 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
222 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
223 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
224 EVEX_LEN_0F38C7_R_6_P_2_W_1.
225 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
226 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
227 PREFIX_EVEX_0F38C6_REG_6 entries.
228 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
229 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
230 EVEX_W_0F38C7_R_6_P_2 entries.
231 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
232 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
233 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
234 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
235 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
236 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
237 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
238
2b7bcc87
JB		 2392019-06-27 Jan Beulich <jbeulich@suse.com>
240
241 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
242 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
243 VEX_LEN_0F2D_P_3): Delete.
244 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
245 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
246 (prefix_table): ... here.
247
c1dc7af5
JB		 2482019-06-27 Jan Beulich <jbeulich@suse.com>
249
250 * i386-dis.c (Iq): Delete.
251 (Id): New.
252 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
253 TBM insns.
254 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
255 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
256 (OP_E_memory): Also honor needindex when deciding whether an
257 address size prefix needs printing.
258 (OP_I): Remove handling of q_mode. Add handling of d_mode.
259
d7560e2d
JW		 2602019-06-26 Jim Wilson <jimw@sifive.com>
261
262 PR binutils/24739
263 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
264 Set info->display_endian to info->endian_code.
265
2c703856
JB		 2662019-06-25 Jan Beulich <jbeulich@suse.com>
267
268 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
269 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
270 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
271 OPERAND_TYPE_ACC64 entries.
272 * i386-init.h: Re-generate.
273
54fbadc0
JB		 2742019-06-25 Jan Beulich <jbeulich@suse.com>
275
276 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
277 Delete.
278 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
279 of dqa_mode.
280 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
281 entries here.
282 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
283 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
284
a280ab8e
JB		 2852019-06-25 Jan Beulich <jbeulich@suse.com>
286
287 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
288 variables.
289
e1a1babd
JB		 2902019-06-25 Jan Beulich <jbeulich@suse.com>
291
292 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
293 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
294 movnti.
d7560e2d 295 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 296 * i386-tbl.h: Re-generate.
297
b8364fa7
JB		 2982019-06-25 Jan Beulich <jbeulich@suse.com>
299
300 * i386-opc.tbl (and): Mark Imm8S form for optimization.
301 * i386-tbl.h: Re-generate.
302
ad692897
L		 3032019-06-21 H.J. Lu <hongjiu.lu@intel.com>
304
305 * i386-dis-evex.h: Break into ...
306 * i386-dis-evex-len.h: New file.
307 * i386-dis-evex-mod.h: Likewise.
308 * i386-dis-evex-prefix.h: Likewise.
309 * i386-dis-evex-reg.h: Likewise.
310 * i386-dis-evex-w.h: Likewise.
311 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
312 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
313 i386-dis-evex-mod.h.
314
f0a6222e
L		 3152019-06-19 H.J. Lu <hongjiu.lu@intel.com>
316
317 PR binutils/24700
318 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
319 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
320 EVEX_W_0F385B_P_2.
321 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
322 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
323 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
324 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
325 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
326 EVEX_LEN_0F385B_P_2_W_1.
327 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
328 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
329 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
330 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
331 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
332 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
333 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
334 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
335 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
336 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
337
6e1c90b7
L		 3382019-06-17 H.J. Lu <hongjiu.lu@intel.com>
339
340 PR binutils/24691
341 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
342 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
343 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
344 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
345 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
346 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
347 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
348 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
349 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
350 EVEX_LEN_0F3A43_P_2_W_1.
351 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
352 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
353 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
354 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
355 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
356 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
357 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
358 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
359 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
360 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
361 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
362 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
363
bcc5a6eb
NC		 3642019-06-14 Nick Clifton <nickc@redhat.com>
365
366 * po/fr.po; Updated French translation.
367
e4c4ac46
SH		 3682019-06-13 Stafford Horne <shorne@gmail.com>
369
370 * or1k-asm.c: Regenerated.
371 * or1k-desc.c: Regenerated.
372 * or1k-desc.h: Regenerated.
373 * or1k-dis.c: Regenerated.
374 * or1k-ibld.c: Regenerated.
375 * or1k-opc.c: Regenerated.
376 * or1k-opc.h: Regenerated.
377 * or1k-opinst.c: Regenerated.
378
a0e44ef5
PB		 3792019-06-12 Peter Bergner <bergner@linux.ibm.com>
380
381 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
382
12efd68d
L		 3832019-06-05 H.J. Lu <hongjiu.lu@intel.com>
384
385 PR binutils/24633
386 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
387 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
388 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
389 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
390 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
391 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
392 EVEX_LEN_0F3A1B_P_2_W_1.
393 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
394 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
395 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
396 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
397 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
398 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
399 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
400 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
401
63c6fc6c
L		 4022019-06-04 H.J. Lu <hongjiu.lu@intel.com>
403
404 PR binutils/24626
405 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
406 EVEX.vvvv when disassembling VEX and EVEX instructions.
407 (OP_VEX): Set vex.register_specifier to 0 after readding
408 vex.register_specifier.
409 (OP_Vex_2src_1): Likewise.
410 (OP_Vex_2src_2): Likewise.
411 (OP_LWP_E): Likewise.
412 (OP_EX_Vex): Don't check vex.register_specifier.
413 (OP_XMM_Vex): Likewise.
414
9186c494
L		 4152019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
416 Lili Cui <lili.cui@intel.com>
417
418 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
419 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
420 instructions.
421 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
422 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
423 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
424 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
425 (i386_cpu_flags): Add cpuavx512_vp2intersect.
426 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
427 * i386-init.h: Regenerated.
428 * i386-tbl.h: Likewise.
429
5d79adc4
L		 4302019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
431 Lili Cui <lili.cui@intel.com>
432
433 * doc/c-i386.texi: Document enqcmd.
434 * testsuite/gas/i386/enqcmd-intel.d: New file.
435 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
436 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
437 * testsuite/gas/i386/enqcmd.d: Likewise.
438 * testsuite/gas/i386/enqcmd.s: Likewise.
439 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
440 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
441 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
442 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
443 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
444 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
445 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
446 and x86-64-enqcmd.
447
a9d96ab9
AH		 4482019-06-04 Alan Hayward <alan.hayward@arm.com>
449
450 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
451
4f6d070a
AM		 4522019-06-03 Alan Modra <amodra@gmail.com>
453
454 * ppc-dis.c (prefix_opcd_indices): Correct size.
455
a2f4b66c
L		 4562019-05-28 H.J. Lu <hongjiu.lu@intel.com>
457
458 PR gas/24625
459 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
460 Disp8ShiftVL.
461 * i386-tbl.h: Regenerated.
462
405b5bd8
AM		 4632019-05-24 Alan Modra <amodra@gmail.com>
464
465 * po/POTFILES.in: Regenerate.
466
8acf1435
PB		 4672019-05-24 Peter Bergner <bergner@linux.ibm.com>
468 Alan Modra <amodra@gmail.com>
469
470 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
471 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
472 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
473 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
474 XTOP>): Define and add entries.
475 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
476 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
477 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
478 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
479
dd7efa79
PB		 4802019-05-24 Peter Bergner <bergner@linux.ibm.com>
481 Alan Modra <amodra@gmail.com>
482
483 * ppc-dis.c (ppc_opts): Add "future" entry.
484 (PREFIX_OPCD_SEGS): Define.
485 (prefix_opcd_indices): New array.
486 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
487 (lookup_prefix): New function.
488 (print_insn_powerpc): Handle 64-bit prefix instructions.
489 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
490 (PMRR, POWERXX): Define.
491 (prefix_opcodes): New instruction table.
492 (prefix_num_opcodes): New constant.
493
79472b45
JM		 4942019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
495
496 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
497 * configure: Regenerated.
498 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
499 and cpu/bpf.opc.
500 (HFILES): Add bpf-desc.h and bpf-opc.h.
501 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
502 bpf-ibld.c and bpf-opc.c.
503 (BPF_DEPS): Define.
504 * Makefile.in: Regenerated.
505 * disassemble.c (ARCH_bpf): Define.
506 (disassembler): Add case for bfd_arch_bpf.
507 (disassemble_init_for_target): Likewise.
508 (enum epbf_isa_attr): Define.
509 * disassemble.h: extern print_insn_bpf.
510 * bpf-asm.c: Generated.
511 * bpf-opc.h: Likewise.
512 * bpf-opc.c: Likewise.
513 * bpf-ibld.c: Likewise.
514 * bpf-dis.c: Likewise.
515 * bpf-desc.h: Likewise.
516 * bpf-desc.c: Likewise.
517
ba6cd17f
SD		 5182019-05-21 Sudakshina Das <sudi.das@arm.com>
519
520 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
521 and VMSR with the new operands.
522
e39c1607
SD		 5232019-05-21 Sudakshina Das <sudi.das@arm.com>
524
525 * arm-dis.c (enum mve_instructions): New enum
526 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
527 and cneg.
528 (mve_opcodes): New instructions as above.
529 (is_mve_encoding_conflict): Add cases for csinc, csinv,
530 csneg and csel.
531 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
532
23d00a41
SD		 5332019-05-21 Sudakshina Das <sudi.das@arm.com>
534
535 * arm-dis.c (emun mve_instructions): Updated for new instructions.
536 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
537 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
538 uqshl, urshrl and urshr.
539 (is_mve_okay_in_it): Add new instructions to TRUE list.
540 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
541 (print_insn_mve): Updated to accept new %j,
542 %<bitfield>m and %<bitfield>n patterns.
543
cd4797ee
FS		 5442019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
545
546 * mips-opc.c (mips_builtin_opcodes): Change source register
547 constraint for DAUI.
548
999b073b
NC		 5492019-05-20 Nick Clifton <nickc@redhat.com>
550
551 * po/fr.po: Updated French translation.
552
14b456f2
AV		 5532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
554 Michael Collison <michael.collison@arm.com>
555
556 * arm-dis.c (thumb32_opcodes): Add new instructions.
557 (enum mve_instructions): Likewise.
558 (enum mve_undefined): Add new reasons.
559 (is_mve_encoding_conflict): Handle new instructions.
560 (is_mve_undefined): Likewise.
561 (is_mve_unpredictable): Likewise.
562 (print_mve_undefined): Likewise.
563 (print_mve_size): Likewise.
564
f49bb598
AV		 5652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
566 Michael Collison <michael.collison@arm.com>
567
568 * arm-dis.c (thumb32_opcodes): Add new instructions.
569 (enum mve_instructions): Likewise.
570 (is_mve_encoding_conflict): Handle new instructions.
571 (is_mve_undefined): Likewise.
572 (is_mve_unpredictable): Likewise.
573 (print_mve_size): Likewise.
574
56858bea
AV		 5752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
576 Michael Collison <michael.collison@arm.com>
577
578 * arm-dis.c (thumb32_opcodes): Add new instructions.
579 (enum mve_instructions): Likewise.
580 (is_mve_encoding_conflict): Likewise.
581 (is_mve_unpredictable): Likewise.
582 (print_mve_size): Likewise.
583
e523f101
AV		 5842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
585 Michael Collison <michael.collison@arm.com>
586
587 * arm-dis.c (thumb32_opcodes): Add new instructions.
588 (enum mve_instructions): Likewise.
589 (is_mve_encoding_conflict): Handle new instructions.
590 (is_mve_undefined): Likewise.
591 (is_mve_unpredictable): Likewise.
592 (print_mve_size): Likewise.
593
66dcaa5d
AV		 5942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
595 Michael Collison <michael.collison@arm.com>
596
597 * arm-dis.c (thumb32_opcodes): Add new instructions.
598 (enum mve_instructions): Likewise.
599 (is_mve_encoding_conflict): Handle new instructions.
600 (is_mve_undefined): Likewise.
601 (is_mve_unpredictable): Likewise.
602 (print_mve_size): Likewise.
603 (print_insn_mve): Likewise.
604
d052b9b7
AV		 6052019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
606 Michael Collison <michael.collison@arm.com>
607
608 * arm-dis.c (thumb32_opcodes): Add new instructions.
609 (print_insn_thumb32): Handle new instructions.
610
ed63aa17
AV		 6112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
612 Michael Collison <michael.collison@arm.com>
613
614 * arm-dis.c (enum mve_instructions): Add new instructions.
615 (enum mve_undefined): Add new reasons.
616 (is_mve_encoding_conflict): Handle new instructions.
617 (is_mve_undefined): Likewise.
618 (is_mve_unpredictable): Likewise.
619 (print_mve_undefined): Likewise.
620 (print_mve_size): Likewise.
621 (print_mve_shift_n): Likewise.
622 (print_insn_mve): Likewise.
623
897b9bbc
AV		 6242019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
625 Michael Collison <michael.collison@arm.com>
626
627 * arm-dis.c (enum mve_instructions): Add new instructions.
628 (is_mve_encoding_conflict): Handle new instructions.
629 (is_mve_unpredictable): Likewise.
630 (print_mve_rotate): Likewise.
631 (print_mve_size): Likewise.
632 (print_insn_mve): Likewise.
633
1c8f2df8
AV		 6342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
635 Michael Collison <michael.collison@arm.com>
636
637 * arm-dis.c (enum mve_instructions): Add new instructions.
638 (is_mve_encoding_conflict): Handle new instructions.
639 (is_mve_unpredictable): Likewise.
640 (print_mve_size): Likewise.
641 (print_insn_mve): Likewise.
642
d3b63143
AV		 6432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
644 Michael Collison <michael.collison@arm.com>
645
646 * arm-dis.c (enum mve_instructions): Add new instructions.
647 (enum mve_undefined): Add new reasons.
648 (is_mve_encoding_conflict): Handle new instructions.
649 (is_mve_undefined): Likewise.
650 (is_mve_unpredictable): Likewise.
651 (print_mve_undefined): Likewise.
652 (print_mve_size): Likewise.
653 (print_insn_mve): Likewise.
654
14925797
AV		 6552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
656 Michael Collison <michael.collison@arm.com>
657
658 * arm-dis.c (enum mve_instructions): Add new instructions.
659 (is_mve_encoding_conflict): Handle new instructions.
660 (is_mve_undefined): Likewise.
661 (is_mve_unpredictable): Likewise.
662 (print_mve_size): Likewise.
663 (print_insn_mve): Likewise.
664
c507f10b
AV		 6652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
666 Michael Collison <michael.collison@arm.com>
667
668 * arm-dis.c (enum mve_instructions): Add new instructions.
669 (enum mve_unpredictable): Add new reasons.
670 (enum mve_undefined): Likewise.
671 (is_mve_okay_in_it): Handle new isntructions.
672 (is_mve_encoding_conflict): Likewise.
673 (is_mve_undefined): Likewise.
674 (is_mve_unpredictable): Likewise.
675 (print_mve_vmov_index): Likewise.
676 (print_simd_imm8): Likewise.
677 (print_mve_undefined): Likewise.
678 (print_mve_unpredictable): Likewise.
679 (print_mve_size): Likewise.
680 (print_insn_mve): Likewise.
681
bf0b396d
AV		 6822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
683 Michael Collison <michael.collison@arm.com>
684
685 * arm-dis.c (enum mve_instructions): Add new instructions.
686 (enum mve_unpredictable): Add new reasons.
687 (enum mve_undefined): Likewise.
688 (is_mve_encoding_conflict): Handle new instructions.
689 (is_mve_undefined): Likewise.
690 (is_mve_unpredictable): Likewise.
691 (print_mve_undefined): Likewise.
692 (print_mve_unpredictable): Likewise.
693 (print_mve_rounding_mode): Likewise.
694 (print_mve_vcvt_size): Likewise.
695 (print_mve_size): Likewise.
696 (print_insn_mve): Likewise.
697
ef1576a1
AV		 6982019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
699 Michael Collison <michael.collison@arm.com>
700
701 * arm-dis.c (enum mve_instructions): Add new instructions.
702 (enum mve_unpredictable): Add new reasons.
703 (enum mve_undefined): Likewise.
704 (is_mve_undefined): Handle new instructions.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_undefined): Likewise.
707 (print_mve_unpredictable): Likewise.
708 (print_mve_size): Likewise.
709 (print_insn_mve): Likewise.
710
aef6d006
AV		 7112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
712 Michael Collison <michael.collison@arm.com>
713
714 * arm-dis.c (enum mve_instructions): Add new instructions.
715 (enum mve_undefined): Add new reasons.
716 (insns): Add new instructions.
717 (is_mve_encoding_conflict):
718 (print_mve_vld_str_addr): New print function.
719 (is_mve_undefined): Handle new instructions.
720 (is_mve_unpredictable): Likewise.
721 (print_mve_undefined): Likewise.
722 (print_mve_size): Likewise.
723 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
724 (print_insn_mve): Handle new operands.
725
04d54ace
AV		 7262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
727 Michael Collison <michael.collison@arm.com>
728
729 * arm-dis.c (enum mve_instructions): Add new instructions.
730 (enum mve_unpredictable): Add new reasons.
731 (is_mve_encoding_conflict): Handle new instructions.
732 (is_mve_unpredictable): Likewise.
733 (mve_opcodes): Add new instructions.
734 (print_mve_unpredictable): Handle new reasons.
735 (print_mve_register_blocks): New print function.
736 (print_mve_size): Handle new instructions.
737 (print_insn_mve): Likewise.
738
9743db03
AV		 7392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
740 Michael Collison <michael.collison@arm.com>
741
742 * arm-dis.c (enum mve_instructions): Add new instructions.
743 (enum mve_unpredictable): Add new reasons.
744 (enum mve_undefined): Likewise.
745 (is_mve_encoding_conflict): Handle new instructions.
746 (is_mve_undefined): Likewise.
747 (is_mve_unpredictable): Likewise.
748 (coprocessor_opcodes): Move NEON VDUP from here...
749 (neon_opcodes): ... to here.
750 (mve_opcodes): Add new instructions.
751 (print_mve_undefined): Handle new reasons.
752 (print_mve_unpredictable): Likewise.
753 (print_mve_size): Handle new instructions.
754 (print_insn_neon): Handle vdup.
755 (print_insn_mve): Handle new operands.
756
143275ea
AV		 7572019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
758 Michael Collison <michael.collison@arm.com>
759
760 * arm-dis.c (enum mve_instructions): Add new instructions.
761 (enum mve_unpredictable): Add new values.
762 (mve_opcodes): Add new instructions.
763 (vec_condnames): New array with vector conditions.
764 (mve_predicatenames): New array with predicate suffixes.
765 (mve_vec_sizename): New array with vector sizes.
766 (enum vpt_pred_state): New enum with vector predication states.
767 (struct vpt_block): New struct type for vpt blocks.
768 (vpt_block_state): Global struct to keep track of state.
769 (mve_extract_pred_mask): New helper function.
770 (num_instructions_vpt_block): Likewise.
771 (mark_outside_vpt_block): Likewise.
772 (mark_inside_vpt_block): Likewise.
773 (invert_next_predicate_state): Likewise.
774 (update_next_predicate_state): Likewise.
775 (update_vpt_block_state): Likewise.
776 (is_vpt_instruction): Likewise.
777 (is_mve_encoding_conflict): Add entries for new instructions.
778 (is_mve_unpredictable): Likewise.
779 (print_mve_unpredictable): Handle new cases.
780 (print_instruction_predicate): Likewise.
781 (print_mve_size): New function.
782 (print_vec_condition): New function.
783 (print_insn_mve): Handle vpt blocks and new print operands.
784
f08d8ce3
AV		 7852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
786
787 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
788 8, 14 and 15 for Armv8.1-M Mainline.
789
73cd51e5
AV		 7902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
791 Michael Collison <michael.collison@arm.com>
792
793 * arm-dis.c (enum mve_instructions): New enum.
794 (enum mve_unpredictable): Likewise.
795 (enum mve_undefined): Likewise.
796 (struct mopcode32): New struct.
797 (is_mve_okay_in_it): New function.
798 (is_mve_architecture): Likewise.
799 (arm_decode_field): Likewise.
800 (arm_decode_field_multiple): Likewise.
801 (is_mve_encoding_conflict): Likewise.
802 (is_mve_undefined): Likewise.
803 (is_mve_unpredictable): Likewise.
804 (print_mve_undefined): Likewise.
805 (print_mve_unpredictable): Likewise.
806 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
807 (print_insn_mve): New function.
808 (print_insn_thumb32): Handle MVE architecture.
809 (select_arm_features): Force thumb for Armv8.1-m Mainline.
810
3076e594
NC		 8112019-05-10 Nick Clifton <nickc@redhat.com>
812
813 PR 24538
814 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
815 end of the table prematurely.
816
387e7624
FS		 8172019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
818
819 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
820 macros for R6.
821
0067be51
AM		 8222019-05-11 Alan Modra <amodra@gmail.com>
823
824 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
825 when -Mraw is in effect.
826
42e6288f
MM		 8272019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
828
829 * aarch64-dis-2.c: Regenerate.
830 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
831 (OP_SVE_BBB): New variant set.
832 (OP_SVE_DDDD): New variant set.
833 (OP_SVE_HHH): New variant set.
834 (OP_SVE_HHHU): New variant set.
835 (OP_SVE_SSS): New variant set.
836 (OP_SVE_SSSU): New variant set.
837 (OP_SVE_SHH): New variant set.
838 (OP_SVE_SBBU): New variant set.
839 (OP_SVE_DSS): New variant set.
840 (OP_SVE_DHHU): New variant set.
841 (OP_SVE_VMV_HSD_BHS): New variant set.
842 (OP_SVE_VVU_HSD_BHS): New variant set.
843 (OP_SVE_VVVU_SD_BH): New variant set.
844 (OP_SVE_VVVU_BHSD): New variant set.
845 (OP_SVE_VVV_QHD_DBS): New variant set.
846 (OP_SVE_VVV_HSD_BHS): New variant set.
847 (OP_SVE_VVV_HSD_BHS2): New variant set.
848 (OP_SVE_VVV_BHS_HSD): New variant set.
849 (OP_SVE_VV_BHS_HSD): New variant set.
850 (OP_SVE_VVV_SD): New variant set.
851 (OP_SVE_VVU_BHS_HSD): New variant set.
852 (OP_SVE_VZVV_SD): New variant set.
853 (OP_SVE_VZVV_BH): New variant set.
854 (OP_SVE_VZV_SD): New variant set.
855 (aarch64_opcode_table): Add sve2 instructions.
856
28ed815a
MM		 8572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
858
859 * aarch64-asm-2.c: Regenerated.
860 * aarch64-dis-2.c: Regenerated.
861 * aarch64-opc-2.c: Regenerated.
862 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
863 for SVE_SHLIMM_UNPRED_22.
864 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
865 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
866 operand.
867
fd1dc4a0
MM		 8682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
869
870 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
871 sve_size_tsz_bhs iclass encode.
872 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
873 sve_size_tsz_bhs iclass decode.
874
31e36ab3
MM		 8752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
876
877 * aarch64-asm-2.c: Regenerated.
878 * aarch64-dis-2.c: Regenerated.
879 * aarch64-opc-2.c: Regenerated.
880 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
881 for SVE_Zm4_11_INDEX.
882 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
883 (fields): Handle SVE_i2h field.
884 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
885 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
886
1be5f94f
MM		 8872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
888
889 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
890 sve_shift_tsz_bhsd iclass encode.
891 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
892 sve_shift_tsz_bhsd iclass decode.
893
3c17238b
MM		 8942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
895
896 * aarch64-asm-2.c: Regenerated.
897 * aarch64-dis-2.c: Regenerated.
898 * aarch64-opc-2.c: Regenerated.
899 * aarch64-asm.c (aarch64_ins_sve_shrimm):
900 (aarch64_encode_variant_using_iclass): Handle
901 sve_shift_tsz_hsd iclass encode.
902 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
903 sve_shift_tsz_hsd iclass decode.
904 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
905 for SVE_SHRIMM_UNPRED_22.
906 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
907 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
908 operand.
909
cd50a87a
MM		 9102019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
911
912 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
913 sve_size_013 iclass encode.
914 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
915 sve_size_013 iclass decode.
916
3c705960
MM		 9172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
918
919 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
920 sve_size_bh iclass encode.
921 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
922 sve_size_bh iclass decode.
923
0a57e14f
MM		 9242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
925
926 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
927 sve_size_sd2 iclass encode.
928 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
929 sve_size_sd2 iclass decode.
930 * aarch64-opc.c (fields): Handle SVE_sz2 field.
931 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
932
c469c864
MM		 9332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
934
935 * aarch64-asm-2.c: Regenerated.
936 * aarch64-dis-2.c: Regenerated.
937 * aarch64-opc-2.c: Regenerated.
938 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
939 for SVE_ADDR_ZX.
940 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
941 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
942
116adc27
MM		 9432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
944
945 * aarch64-asm-2.c: Regenerated.
946 * aarch64-dis-2.c: Regenerated.
947 * aarch64-opc-2.c: Regenerated.
948 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
949 for SVE_Zm3_11_INDEX.
950 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
951 (fields): Handle SVE_i3l and SVE_i3h2 fields.
952 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
953 fields.
954 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
955
3bd82c86
MM		 9562019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
957
958 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
959 sve_size_hsd2 iclass encode.
960 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
961 sve_size_hsd2 iclass decode.
962 * aarch64-opc.c (fields): Handle SVE_size field.
963 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
964
adccc507
MM		 9652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
966
967 * aarch64-asm-2.c: Regenerated.
968 * aarch64-dis-2.c: Regenerated.
969 * aarch64-opc-2.c: Regenerated.
970 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
971 for SVE_IMM_ROT3.
972 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
973 (fields): Handle SVE_rot3 field.
974 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
975 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
976
5cd99750
MM		 9772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
978
979 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
980 instructions.
981
7ce2460a
MM		 9822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
983
984 * aarch64-tbl.h
985 (aarch64_feature_sve2, aarch64_feature_sve2aes,
986 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
987 aarch64_feature_sve2bitperm): New feature sets.
988 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
989 for feature set addresses.
990 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
991 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
992
41cee089
FS		 9932019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
994 Faraz Shahbazker <fshahbazker@wavecomp.com>
995
996 * mips-dis.c (mips_calculate_combination_ases): Add ISA
997 argument and set ASE_EVA_R6 appropriately.
998 (set_default_mips_dis_options): Pass ISA to above.
999 (parse_mips_dis_option): Likewise.
1000 * mips-opc.c (EVAR6): New macro.
1001 (mips_builtin_opcodes): Add llwpe, scwpe.
1002
b83b4b13
SD		 10032019-05-01 Sudakshina Das <sudi.das@arm.com>
1004
1005 * aarch64-asm-2.c: Regenerated.
1006 * aarch64-dis-2.c: Regenerated.
1007 * aarch64-opc-2.c: Regenerated.
1008 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1009 AARCH64_OPND_TME_UIMM16.
1010 (aarch64_print_operand): Likewise.
1011 * aarch64-tbl.h (QL_IMM_NIL): New.
1012 (TME): New.
1013 (_TME_INSN): New.
1014 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1015
4a90ce95
JD		 10162019-04-29 John Darrington <john@darrington.wattle.id.au>
1017
1018 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1019
a45328b9
AB		 10202019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1021 Faraz Shahbazker <fshahbazker@wavecomp.com>
1022
1023 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1024
d10be0cb
JD		 10252019-04-24 John Darrington <john@darrington.wattle.id.au>
1026
1027 * s12z-opc.h: Add extern "C" bracketing to help
1028 users who wish to use this interface in c++ code.
1029
a679f24e
JD		 10302019-04-24 John Darrington <john@darrington.wattle.id.au>
1031
1032 * s12z-opc.c (bm_decode): Handle bit map operations with the
1033 "reserved0" mode.
1034
32c36c3c
AV		 10352019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1036
1037 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1038 specifier. Add entries for VLDR and VSTR of system registers.
1039 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1040 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1041 of %J and %K format specifier.
1042
efd6b359
AV		 10432019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1044
1045 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1046 Add new entries for VSCCLRM instruction.
1047 (print_insn_coprocessor): Handle new %C format control code.
1048
6b0dd094
AV		 10492019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1050
1051 * arm-dis.c (enum isa): New enum.
1052 (struct sopcode32): New structure.
1053 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1054 set isa field of all current entries to ANY.
1055 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1056 Only match an entry if its isa field allows the current mode.
1057
4b5a202f
AV		 10582019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1059
1060 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1061 CLRM.
1062 (print_insn_thumb32): Add logic to print %n CLRM register list.
1063
60f993ce
AV		 10642019-04-15 Sudakshina Das <sudi.das@arm.com>
1065
1066 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1067 and %Q patterns.
1068
f6b2b12d
AV		 10692019-04-15 Sudakshina Das <sudi.das@arm.com>
1070
1071 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1072 (print_insn_thumb32): Edit the switch case for %Z.
1073
1889da70
AV		 10742019-04-15 Sudakshina Das <sudi.das@arm.com>
1075
1076 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1077
65d1bc05
AV		 10782019-04-15 Sudakshina Das <sudi.das@arm.com>
1079
1080 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1081
1caf72a5
AV		 10822019-04-15 Sudakshina Das <sudi.das@arm.com>
1083
1084 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1085
f1c7f421
AV		 10862019-04-15 Sudakshina Das <sudi.das@arm.com>
1087
1088 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1089 Arm register with r13 and r15 unpredictable.
1090 (thumb32_opcodes): New instructions for bfx and bflx.
1091
4389b29a
AV		 10922019-04-15 Sudakshina Das <sudi.das@arm.com>
1093
1094 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1095
e5d6e09e
AV		 10962019-04-15 Sudakshina Das <sudi.das@arm.com>
1097
1098 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1099
e12437dc
AV		 11002019-04-15 Sudakshina Das <sudi.das@arm.com>
1101
1102 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1103
031254f2
AV		 11042019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1105
1106 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1107
e5a557ac
JD		 11082019-04-12 John Darrington <john@darrington.wattle.id.au>
1109
1110 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1111 "optr". ("operator" is a reserved word in c++).
1112
bd7ceb8d
SD		 11132019-04-11 Sudakshina Das <sudi.das@arm.com>
1114
1115 * aarch64-opc.c (aarch64_print_operand): Add case for
1116 AARCH64_OPND_Rt_SP.
1117 (verify_constraints): Likewise.
1118 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1119 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1120 to accept Rt|SP as first operand.
1121 (AARCH64_OPERANDS): Add new Rt_SP.
1122 * aarch64-asm-2.c: Regenerated.
1123 * aarch64-dis-2.c: Regenerated.
1124 * aarch64-opc-2.c: Regenerated.
1125
e54010f1
SD		 11262019-04-11 Sudakshina Das <sudi.das@arm.com>
1127
1128 * aarch64-asm-2.c: Regenerated.
1129 * aarch64-dis-2.c: Likewise.
1130 * aarch64-opc-2.c: Likewise.
1131 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1132
7e96e219
RS		 11332019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1134
1135 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1136
6f2791d5
L		 11372019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1138
1139 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1140 * i386-init.h: Regenerated.
1141
e392bad3
AM		 11422019-04-07 Alan Modra <amodra@gmail.com>
1143
1144 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1145 op_separator to control printing of spaces, comma and parens
1146 rather than need_comma, need_paren and spaces vars.
1147
dffaa15c
AM		 11482019-04-07 Alan Modra <amodra@gmail.com>
1149
1150 PR 24421
1151 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1152 (print_insn_neon, print_insn_arm): Likewise.
1153
d6aab7a1
XG		 11542019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1155
1156 * i386-dis-evex.h (evex_table): Updated to support BF16
1157 instructions.
1158 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1159 and EVEX_W_0F3872_P_3.
1160 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1161 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1162 * i386-opc.h (enum): Add CpuAVX512_BF16.
1163 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1164 * i386-opc.tbl: Add AVX512 BF16 instructions.
1165 * i386-init.h: Regenerated.
1166 * i386-tbl.h: Likewise.
1167
66e85460
AM		 11682019-04-05 Alan Modra <amodra@gmail.com>
1169
1170 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1171 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1172 to favour printing of "-" branch hint when using the "y" bit.
1173 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1174
c2b1c275
AM		 11752019-04-05 Alan Modra <amodra@gmail.com>
1176
1177 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1178 opcode until first operand is output.
1179
aae9718e
PB		 11802019-04-04 Peter Bergner <bergner@linux.ibm.com>
1181
1182 PR gas/24349
1183 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1184 (valid_bo_post_v2): Add support for 'at' branch hints.
1185 (insert_bo): Only error on branch on ctr.
1186 (get_bo_hint_mask): New function.
1187 (insert_boe): Add new 'branch_taken' formal argument. Add support
1188 for inserting 'at' branch hints.
1189 (extract_boe): Add new 'branch_taken' formal argument. Add support
1190 for extracting 'at' branch hints.
1191 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1192 (BOE): Delete operand.
1193 (BOM, BOP): New operands.
1194 (RM): Update value.
1195 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1196 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1197 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1198 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1199 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1200 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1201 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1202 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1203 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1204 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1205 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1206 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1207 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1208 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1209 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1210 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1211 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1212 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1213 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1214 bttarl+>: New extended mnemonics.
1215
96a86c01
AM		 12162019-03-28 Alan Modra <amodra@gmail.com>
1217
1218 PR 24390
1219 * ppc-opc.c (BTF): Define.
1220 (powerpc_opcodes): Use for mtfsb*.
1221 * ppc-dis.c (print_insn_powerpc): Print fields with both
1222 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1223
796d6298
TC		 12242019-03-25 Tamar Christina <tamar.christina@arm.com>
1225
1226 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1227 (mapping_symbol_for_insn): Implement new algorithm.
1228 (print_insn): Remove duplicate code.
1229
60df3720
TC		 12302019-03-25 Tamar Christina <tamar.christina@arm.com>
1231
1232 * aarch64-dis.c (print_insn_aarch64):
1233 Implement override.
1234
51457761
TC		 12352019-03-25 Tamar Christina <tamar.christina@arm.com>
1236
1237 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1238 order.
1239
53b2f36b
TC		 12402019-03-25 Tamar Christina <tamar.christina@arm.com>
1241
1242 * aarch64-dis.c (last_stop_offset): New.
1243 (print_insn_aarch64): Use stop_offset.
1244
89199bb5
L		 12452019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1246
1247 PR gas/24359
1248 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1249 CPU_ANY_AVX2_FLAGS.
1250 * i386-init.h: Regenerated.
1251
97ed31ae
L		 12522019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 PR gas/24348
1255 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1256 vmovdqu16, vmovdqu32 and vmovdqu64.
1257 * i386-tbl.h: Regenerated.
1258
0919bfe9
AK		 12592019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1260
1261 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1262 from vstrszb, vstrszh, and vstrszf.
1263
12642019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1265
1266 * s390-opc.txt: Add instruction descriptions.
1267
21820ebe
JW		 12682019-02-08 Jim Wilson <jimw@sifive.com>
1269
1270 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1271 <bne>: Likewise.
1272
f7dd2fb2
TC		 12732019-02-07 Tamar Christina <tamar.christina@arm.com>
1274
1275 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1276
6456d318
TC		 12772019-02-07 Tamar Christina <tamar.christina@arm.com>
1278
1279 PR binutils/23212
1280 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1281 * aarch64-opc.c (verify_elem_sd): New.
1282 (fields): Add FLD_sz entr.
1283 * aarch64-tbl.h (_SIMD_INSN): New.
1284 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1285 fmulx scalar and vector by element isns.
1286
4a83b610
NC		 12872019-02-07 Nick Clifton <nickc@redhat.com>
1288
1289 * po/sv.po: Updated Swedish translation.
1290
fc60b8c8
AK		 12912019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1292
1293 * s390-mkopc.c (main): Accept arch13 as cpu string.
1294 * s390-opc.c: Add new instruction formats and instruction opcode
1295 masks.
1296 * s390-opc.txt: Add new arch13 instructions.
1297
e10620d3
TC		 12982019-01-25 Sudakshina Das <sudi.das@arm.com>
1299
1300 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1301 (aarch64_opcode): Change encoding for stg, stzg
1302 st2g and st2zg.
1303 * aarch64-asm-2.c: Regenerated.
1304 * aarch64-dis-2.c: Regenerated.
1305 * aarch64-opc-2.c: Regenerated.
1306
20a4ca55
SD		 13072019-01-25 Sudakshina Das <sudi.das@arm.com>
1308
1309 * aarch64-asm-2.c: Regenerated.
1310 * aarch64-dis-2.c: Likewise.
1311 * aarch64-opc-2.c: Likewise.
1312 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1313
550fd7bf
SD		 13142019-01-25 Sudakshina Das <sudi.das@arm.com>
1315 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1316
1317 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1318 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1319 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1320 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1321 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1322 case for ldstgv_indexed.
1323 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1324 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1325 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1326 * aarch64-asm-2.c: Regenerated.
1327 * aarch64-dis-2.c: Regenerated.
1328 * aarch64-opc-2.c: Regenerated.
1329
d9938630
NC		 13302019-01-23 Nick Clifton <nickc@redhat.com>
1331
1332 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1333
375cd423
NC		 13342019-01-21 Nick Clifton <nickc@redhat.com>
1335
1336 * po/de.po: Updated German translation.
1337 * po/uk.po: Updated Ukranian translation.
1338
57299f48
CX		 13392019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1340 * mips-dis.c (mips_arch_choices): Fix typo in
1341 gs464, gs464e and gs264e descriptors.
1342
f48dfe41
NC		 13432019-01-19 Nick Clifton <nickc@redhat.com>
1344
1345 * configure: Regenerate.
1346 * po/opcodes.pot: Regenerate.
1347
f974f26c
NC		 13482018-06-24 Nick Clifton <nickc@redhat.com>
1349
1350 2.32 branch created.
1351
39f286cd
JD		 13522019-01-09 John Darrington <john@darrington.wattle.id.au>
1353
448b8ca8
JD		 1354 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1355 if it is null.
1356 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1357 zero.
1358
3107326d
AP		 13592019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1360
1361 * configure: Regenerate.
1362
7e9ca91e
AM		 13632019-01-07 Alan Modra <amodra@gmail.com>
1364
1365 * configure: Regenerate.
1366 * po/POTFILES.in: Regenerate.
1367
ef1ad42b
JD		 13682019-01-03 John Darrington <john@darrington.wattle.id.au>
1369
1370 * s12z-opc.c: New file.
1371 * s12z-opc.h: New file.
1372 * s12z-dis.c: Removed all code not directly related to display
1373 of instructions. Used the interface provided by the new files
1374 instead.
1375 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1376 * Makefile.in: Regenerate.
ef1ad42b 1377 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1378 * configure: Regenerate.
ef1ad42b 1379
82704155
AM		 13802019-01-01 Alan Modra <amodra@gmail.com>
1381
1382 Update year range in copyright notice of all files.
1383
d5c04e1b 1384For older changes see ChangeLog-2018
3499769a 1385\f
d5c04e1b 1386Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1387
1388Copying and distribution of this file, with or without modification,
1389are permitted in any medium without royalty provided the copyright
1390notice and this notice are preserved.
1391
1392Local Variables:
1393mode: change-log
1394left-margin: 8
1395fill-column: 74
1396version-control: never
1397End:
GDB Binutils - Deliverables
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