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gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
CommitLineData
252b5132 1/* Instruction printing code for the ARM
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
e16bb312 6 This file is part of libopcodes.
252b5132 7
9b201bb5
NC		 8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
252b5132 12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132 17
e16bb312
NC		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
9b201bb5
NC		 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
252b5132 22
cb6a5892 23#include "sysdep.h"
143275ea 24#include <assert.h>
2fbad815 25
6394c606 26#include "disassemble.h"
2fbad815 27#include "opcode/arm.h"
252b5132 28#include "opintl.h"
31e0f3cd 29#include "safe-ctype.h"
65b48a81 30#include "libiberty.h"
0dbde4cf 31#include "floatformat.h"
252b5132 32
baf0cc5e 33/* FIXME: This shouldn't be done here. */
6b5d3a4d
ZW		 34#include "coff/internal.h"
35#include "libcoff.h"
2d5d5a8f 36#include "bfd.h"
252b5132
RH		 37#include "elf-bfd.h"
38#include "elf/internal.h"
39#include "elf/arm.h"
e49d43ff 40#include "mach-o.h"
252b5132 41
6b5d3a4d 42/* FIXME: Belongs in global header. */
01c7f630 43#ifndef strneq
58efb6c0
NC		 44#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
45#endif
46
1fbaefec
PB		 47/* Cached mapping symbol state. */
48enum map_type
49{
50 MAP_ARM,
51 MAP_THUMB,
52 MAP_DATA
53};
54
b0e28b39
DJ		 55struct arm_private_data
56{
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features;
59
1fbaefec
PB		 60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type;
62
63 /* Tracking symbol table information */
64 int last_mapping_sym;
796d6298
TC		 65
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset;
1fbaefec 68 bfd_vma last_mapping_addr;
b0e28b39
DJ		 69};
70
73cd51e5
AV		 71enum mve_instructions
72{
143275ea
AV		 73 MVE_VPST,
74 MVE_VPT_FP_T1,
75 MVE_VPT_FP_T2,
76 MVE_VPT_VEC_T1,
77 MVE_VPT_VEC_T2,
78 MVE_VPT_VEC_T3,
79 MVE_VPT_VEC_T4,
80 MVE_VPT_VEC_T5,
81 MVE_VPT_VEC_T6,
82 MVE_VCMP_FP_T1,
83 MVE_VCMP_FP_T2,
84 MVE_VCMP_VEC_T1,
85 MVE_VCMP_VEC_T2,
86 MVE_VCMP_VEC_T3,
87 MVE_VCMP_VEC_T4,
88 MVE_VCMP_VEC_T5,
89 MVE_VCMP_VEC_T6,
9743db03
AV		 90 MVE_VDUP,
91 MVE_VEOR,
92 MVE_VFMAS_FP_SCALAR,
93 MVE_VFMA_FP_SCALAR,
94 MVE_VFMA_FP,
95 MVE_VFMS_FP,
96 MVE_VHADD_T1,
97 MVE_VHADD_T2,
98 MVE_VHSUB_T1,
99 MVE_VHSUB_T2,
100 MVE_VRHADD,
04d54ace
AV		 101 MVE_VLD2,
102 MVE_VLD4,
103 MVE_VST2,
104 MVE_VST4,
aef6d006
AV		 105 MVE_VLDRB_T1,
106 MVE_VLDRH_T2,
107 MVE_VLDRB_T5,
108 MVE_VLDRH_T6,
109 MVE_VLDRW_T7,
110 MVE_VSTRB_T1,
111 MVE_VSTRH_T2,
112 MVE_VSTRB_T5,
113 MVE_VSTRH_T6,
114 MVE_VSTRW_T7,
ef1576a1
AV		 115 MVE_VLDRB_GATHER_T1,
116 MVE_VLDRH_GATHER_T2,
117 MVE_VLDRW_GATHER_T3,
118 MVE_VLDRD_GATHER_T4,
119 MVE_VLDRW_GATHER_T5,
120 MVE_VLDRD_GATHER_T6,
121 MVE_VSTRB_SCATTER_T1,
122 MVE_VSTRH_SCATTER_T2,
123 MVE_VSTRW_SCATTER_T3,
124 MVE_VSTRD_SCATTER_T4,
125 MVE_VSTRW_SCATTER_T5,
126 MVE_VSTRD_SCATTER_T6,
bf0b396d
AV		 127 MVE_VCVT_FP_FIX_VEC,
128 MVE_VCVT_BETWEEN_FP_INT,
129 MVE_VCVT_FP_HALF_FP,
130 MVE_VCVT_FROM_FP_TO_INT,
131 MVE_VRINT_FP,
c507f10b
AV		 132 MVE_VMOV_HFP_TO_GP,
133 MVE_VMOV_GP_TO_VEC_LANE,
134 MVE_VMOV_IMM_TO_VEC,
135 MVE_VMOV_VEC_TO_VEC,
136 MVE_VMOV2_VEC_LANE_TO_GP,
137 MVE_VMOV2_GP_TO_VEC_LANE,
138 MVE_VMOV_VEC_LANE_TO_GP,
139 MVE_VMVN_IMM,
140 MVE_VMVN_REG,
141 MVE_VORR_IMM,
142 MVE_VORR_REG,
143 MVE_VORN,
144 MVE_VBIC_IMM,
145 MVE_VBIC_REG,
146 MVE_VMOVX,
14925797
AV		 147 MVE_VMOVL,
148 MVE_VMOVN,
149 MVE_VMULL_INT,
150 MVE_VMULL_POLY,
151 MVE_VQDMULL_T1,
152 MVE_VQDMULL_T2,
153 MVE_VQMOVN,
154 MVE_VQMOVUN,
d3b63143
AV		 155 MVE_VADDV,
156 MVE_VMLADAV_T1,
157 MVE_VMLADAV_T2,
158 MVE_VMLALDAV,
159 MVE_VMLAS,
160 MVE_VADDLV,
161 MVE_VMLSDAV_T1,
162 MVE_VMLSDAV_T2,
163 MVE_VMLSLDAV,
164 MVE_VRMLALDAVH,
165 MVE_VRMLSLDAVH,
166 MVE_VQDMLADH,
167 MVE_VQRDMLADH,
168 MVE_VQDMLAH,
169 MVE_VQRDMLAH,
170 MVE_VQDMLASH,
171 MVE_VQRDMLASH,
172 MVE_VQDMLSDH,
173 MVE_VQRDMLSDH,
174 MVE_VQDMULH_T1,
175 MVE_VQRDMULH_T2,
176 MVE_VQDMULH_T3,
177 MVE_VQRDMULH_T4,
1c8f2df8
AV		 178 MVE_VDDUP,
179 MVE_VDWDUP,
180 MVE_VIWDUP,
181 MVE_VIDUP,
897b9bbc
AV		 182 MVE_VCADD_FP,
183 MVE_VCADD_VEC,
184 MVE_VHCADD,
185 MVE_VCMLA_FP,
186 MVE_VCMUL_FP,
ed63aa17
AV		 187 MVE_VQRSHL_T1,
188 MVE_VQRSHL_T2,
189 MVE_VQRSHRN,
190 MVE_VQRSHRUN,
191 MVE_VQSHL_T1,
192 MVE_VQSHL_T2,
193 MVE_VQSHLU_T3,
194 MVE_VQSHL_T4,
195 MVE_VQSHRN,
196 MVE_VQSHRUN,
197 MVE_VRSHL_T1,
198 MVE_VRSHL_T2,
199 MVE_VRSHR,
200 MVE_VRSHRN,
201 MVE_VSHL_T1,
202 MVE_VSHL_T2,
203 MVE_VSHL_T3,
204 MVE_VSHLC,
205 MVE_VSHLL_T1,
206 MVE_VSHLL_T2,
207 MVE_VSHR,
208 MVE_VSHRN,
209 MVE_VSLI,
210 MVE_VSRI,
66dcaa5d
AV		 211 MVE_VADC,
212 MVE_VABAV,
213 MVE_VABD_FP,
214 MVE_VABD_VEC,
215 MVE_VABS_FP,
216 MVE_VABS_VEC,
217 MVE_VADD_FP_T1,
218 MVE_VADD_FP_T2,
219 MVE_VADD_VEC_T1,
220 MVE_VADD_VEC_T2,
221 MVE_VSBC,
222 MVE_VSUB_FP_T1,
223 MVE_VSUB_FP_T2,
224 MVE_VSUB_VEC_T1,
225 MVE_VSUB_VEC_T2,
e523f101
AV		 226 MVE_VAND,
227 MVE_VBRSR,
228 MVE_VCLS,
229 MVE_VCLZ,
230 MVE_VCTP,
56858bea
AV		 231 MVE_VMAX,
232 MVE_VMAXA,
233 MVE_VMAXNM_FP,
234 MVE_VMAXNMA_FP,
235 MVE_VMAXNMV_FP,
236 MVE_VMAXNMAV_FP,
237 MVE_VMAXV,
238 MVE_VMAXAV,
239 MVE_VMIN,
240 MVE_VMINA,
241 MVE_VMINNM_FP,
242 MVE_VMINNMA_FP,
243 MVE_VMINNMV_FP,
244 MVE_VMINNMAV_FP,
245 MVE_VMINV,
246 MVE_VMINAV,
247 MVE_VMLA,
f49bb598
AV		 248 MVE_VMUL_FP_T1,
249 MVE_VMUL_FP_T2,
250 MVE_VMUL_VEC_T1,
251 MVE_VMUL_VEC_T2,
252 MVE_VMULH,
253 MVE_VRMULH,
254 MVE_VNEG_FP,
255 MVE_VNEG_VEC,
14b456f2
AV		 256 MVE_VPNOT,
257 MVE_VPSEL,
258 MVE_VQABS,
259 MVE_VQADD_T1,
260 MVE_VQADD_T2,
261 MVE_VQSUB_T1,
262 MVE_VQSUB_T2,
263 MVE_VQNEG,
264 MVE_VREV16,
265 MVE_VREV32,
266 MVE_VREV64,
23d00a41
SD		 267 MVE_LSLL,
268 MVE_LSLLI,
269 MVE_LSRL,
270 MVE_ASRL,
271 MVE_ASRLI,
272 MVE_SQRSHRL,
273 MVE_SQRSHR,
274 MVE_UQRSHL,
275 MVE_UQRSHLL,
276 MVE_UQSHL,
277 MVE_UQSHLL,
278 MVE_URSHRL,
279 MVE_URSHR,
280 MVE_SRSHRL,
281 MVE_SRSHR,
282 MVE_SQSHLL,
283 MVE_SQSHL,
e39c1607
SD		 284 MVE_CINC,
285 MVE_CINV,
286 MVE_CNEG,
287 MVE_CSINC,
288 MVE_CSINV,
289 MVE_CSET,
290 MVE_CSETM,
291 MVE_CSNEG,
292 MVE_CSEL,
73cd51e5
AV		 293 MVE_NONE
294};
295
296enum mve_unpredictable
297{
298 UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
299 */
143275ea
AV		 300 UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
301 fcB = 1 (vpt). */
302 UNPRED_R13, /* Unpredictable because r13 (sp) or
303 r15 (sp) used. */
9743db03 304 UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
04d54ace
AV		 305 UNPRED_Q_GT_4, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
310 and WB bit = 1. */
ef1576a1
AV		 311 UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
312 equal. */
313 UNPRED_OS, /* Unpredictable because offset scaled == 1. */
bf0b396d
AV		 314 UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
315 same. */
c507f10b
AV		 316 UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
317 size = 1. */
318 UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
319 size = 2. */
73cd51e5
AV		 320 UNPRED_NONE /* No unpredictable behavior. */
321};
322
323enum mve_undefined
324{
ed63aa17 325 UNDEF_SIZE, /* undefined size. */
bf0b396d 326 UNDEF_SIZE_0, /* undefined because size == 0. */
c507f10b 327 UNDEF_SIZE_2, /* undefined because size == 2. */
aef6d006
AV		 328 UNDEF_SIZE_3, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
14b456f2 330 UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
ef1576a1
AV		 331 UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
334 size == 0. */
335 UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
336 size == 1. */
337 UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
bf0b396d
AV		 338 UNDEF_VCVT_IMM6, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
c507f10b
AV		 340 UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
341 op1 == (0 or 1). */
342 UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
345 in {0xx1, x0x1}. */
d3b63143 346 UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
73cd51e5
AV		 347 UNDEF_NONE /* no undefined behavior. */
348};
349
6b5d3a4d
ZW		 350struct opcode32
351{
823d2571
TG		 352 arm_feature_set arch; /* Architecture defining this insn. */
353 unsigned long value; /* If arch is 0 then value is a sentinel. */
fe56b6ce 354 unsigned long mask; /* Recognise insn if (op & mask) == value. */
05413229 355 const char * assembler; /* How to disassemble this insn. */
6b5d3a4d
ZW		 356};
357
4934a27c
MM		 358struct cdeopcode32
359{
360 arm_feature_set arch; /* Architecture defining this insn. */
361 uint8_t coproc_shift; /* coproc is this far into op. */
362 uint16_t coproc_mask; /* Length of coproc field in op. */
363 unsigned long value; /* If arch is 0 then value is a sentinel. */
364 unsigned long mask; /* Recognise insn if (op & mask) == value. */
365 const char * assembler; /* How to disassemble this insn. */
366};
367
73cd51e5
AV		 368/* MVE opcodes. */
369
370struct mopcode32
371{
372 arm_feature_set arch; /* Architecture defining this insn. */
373 enum mve_instructions mve_op; /* Specific mve instruction for faster
374 decoding. */
375 unsigned long value; /* If arch is 0 then value is a sentinel. */
376 unsigned long mask; /* Recognise insn if (op & mask) == value. */
377 const char * assembler; /* How to disassemble this insn. */
378};
379
6b0dd094
AV		 380enum isa {
381 ANY,
382 T32,
383 ARM
384};
385
386
387/* Shared (between Arm and Thumb mode) opcode. */
388struct sopcode32
389{
390 enum isa isa; /* Execution mode instruction availability. */
391 arm_feature_set arch; /* Architecture defining this insn. */
392 unsigned long value; /* If arch is 0 then value is a sentinel. */
393 unsigned long mask; /* Recognise insn if (op & mask) == value. */
394 const char * assembler; /* How to disassemble this insn. */
395};
396
6b5d3a4d
ZW		 397struct opcode16
398{
823d2571 399 arm_feature_set arch; /* Architecture defining this insn. */
aefd8a40 400 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
6b5d3a4d
ZW		 401 const char *assembler; /* How to disassemble this insn. */
402};
b7693d02 403
8f06b2d8 404/* print_insn_coprocessor recognizes the following format control codes:
4a5329c6 405
2fbad815 406 %% %
4a5329c6 407
c22aaad1 408 %c print condition code (always bits 28-31 in ARM mode)
aab2c27d 409 %b print condition code allowing cp_num == 9
37b37b2d 410 %q print shifter argument
e2efe87d
MGD		 411 %u print condition code (unconditional in ARM mode,
412 UNPREDICTABLE if not AL in Thumb)
4a5329c6 413 %A print address for ldc/stc/ldf/stf instruction
16980d0b 414 %B print vstm/vldm register list
efd6b359 415 %C print vscclrm register list
4a5329c6 416 %I print cirrus signed shift immediate: bits 0..3|4..6
32c36c3c
AV		 417 %J print register for VLDR instruction
418 %K print address for VLDR instruction
4a5329c6
ZW		 419 %F print the COUNT field of a LFM/SFM instruction.
420 %P print floating point precision in arithmetic insn
421 %Q print floating point precision in ldf/stf insn
422 %R print floating point rounding mode
423
33399f07 424 %<bitfield>c print as a condition code (for vsel)
4a5329c6 425 %<bitfield>r print as an ARM register
ff4a8d2b
NC		 426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
427 %<bitfield>ru as %<>r but each u register must be unique.
2fbad815 428 %<bitfield>d print the bitfield in decimal
16980d0b 429 %<bitfield>k print immediate for VFPv3 conversion instruction
2fbad815
RE		 430 %<bitfield>x print the bitfield in hex
431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2fbad815
RE		 432 %<bitfield>f print a floating point constant if >7 else a
433 floating point register
4a5329c6
ZW		 434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
435 %<bitfield>g print as an iWMMXt 64-bit register
436 %<bitfield>G print as an iWMMXt general purpose or control register
16980d0b
JB		 437 %<bitfield>D print as a NEON D register
438 %<bitfield>Q print as a NEON Q register
c28eeff2 439 %<bitfield>V print as a NEON D or Q register
6f1c2142 440 %<bitfield>E print a quarter-float immediate value
4a5329c6 441
16980d0b 442 %y<code> print a single precision VFP reg.
2fbad815 443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
16980d0b 444 %z<code> print a double precision VFP reg
2fbad815 445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
4a5329c6 446
16980d0b
JB		 447 %<bitfield>'c print specified char iff bitfield is all ones
448 %<bitfield>`c print specified char iff bitfield is all zeroes
449 %<bitfield>?ab... select from array of values in big endian order
43e65147 450
2fbad815 451 %L print as an iWMMXt N/M width field.
4a5329c6 452 %Z print the Immediate of a WSHUFH instruction.
8f06b2d8 453 %l like 'A' except use byte offsets for 'B' & 'H'
2d447fca
JM		 454 versions.
455 %i print 5-bit immediate in bits 8,3..0
456 (print "32" when 0)
fe56b6ce 457 %r print register offset address for wldt/wstr instruction. */
2fbad815 458
21d799b5 459enum opcode_sentinel_enum
05413229
NC		 460{
461 SENTINEL_IWMMXT_START = 1,
462 SENTINEL_IWMMXT_END,
463 SENTINEL_GENERIC_START
464} opcode_sentinels;
465
aefd8a40 466#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
0b347048
TC		 467#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
468#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
c1e26897 469#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
05413229 470
8f06b2d8 471/* Common coprocessor opcodes shared between Arm and Thumb-2. */
2fbad815 472
4934a27c
MM		 473/* print_insn_cde recognizes the following format control codes:
474
475 %% %
476
477 %a print 'a' iff bit 28 is 1
478 %p print bits 8-10 as coprocessor
479 %<bitfield>d print as decimal
480 %<bitfield>r print as an ARM register
481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
482 %<bitfield>T print as an ARM register + 1
483 %<bitfield>R as %r but r13 is UNPREDICTABLE
484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
485 %j print immediate taken from bits (16..21,7,0..5)
486 %k print immediate taken from bits (20..21,7,0..5).
487 %l print immediate taken from bits (20..22,7,4..5). */
488
489/* At the moment there is only one valid position for the coprocessor number,
490 and hence that's encoded in the macro below. */
491#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
492 { ARCH, 8, 7, VALUE, MASK, ASM }
493static const struct cdeopcode32 cde_opcodes[] =
494{
495 /* Custom Datapath Extension instructions. */
496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
497 0xee000000, 0xefc00840,
498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
500 0xee000040, 0xefc00840,
501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
502
503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
504 0xee400000, 0xefc00840,
505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
507 0xee400040, 0xefc00840,
508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
509
510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
511 0xee800000, 0xef800840,
512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
514 0xee800040, 0xef800840,
515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
516
5aae9ae9
MM		 517 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
518 0xec200000, 0xeeb00840,
519 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
520 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
521 0xec200040, 0xeeb00840,
522 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
523
524 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
525 0xec300000, 0xeeb00840,
526 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
527 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
528 0xec300040, 0xeeb00840,
529 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
530
531 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
532 0xec800000, 0xee800840,
533 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
534 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
535 0xec800040, 0xee800840,
536 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
537
4934a27c
MM		 538 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
539
540};
541
6b0dd094 542static const struct sopcode32 coprocessor_opcodes[] =
2fbad815 543{
2fbad815 544 /* XScale instructions. */
6b0dd094 545 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 546 0x0e200010, 0x0fff0ff0,
547 "mia%c\tacc0, %0-3r, %12-15r"},
6b0dd094 548 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 549 0x0e280010, 0x0fff0ff0,
550 "miaph%c\tacc0, %0-3r, %12-15r"},
6b0dd094 551 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 552 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
6b0dd094 553 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 554 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
6b0dd094 555 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 556 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
05413229 557
2fbad815 558 /* Intel Wireless MMX technology instructions. */
6b0dd094
AV		 559 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
560 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
823d2571 561 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
6b0dd094 562 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 563 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
6b0dd094 564 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 565 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
6b0dd094 566 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 567 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
6b0dd094 568 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 569 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
6b0dd094 570 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 571 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
6b0dd094 572 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 573 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
6b0dd094 574 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 575 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 576 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 577 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 578 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 579 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
6b0dd094 580 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 581 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
6b0dd094 582 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 583 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
6b0dd094 584 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 585 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
6b0dd094 586 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 587 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
6b0dd094 588 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 589 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
6b0dd094 590 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 591 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 592 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 593 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 594 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 595 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 596 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 597 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 598 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 599 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 600 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 601 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
6b0dd094 602 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 603 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 604 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 605 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 606 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 607 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 608 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 609 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 610 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 611 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 612 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 613 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 614 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 615 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
6b0dd094 616 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 617 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
6b0dd094 618 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 619 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
6b0dd094 620 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 621 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 622 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 623 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 624 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 625 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 626 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 627 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 628 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 629 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
6b0dd094 630 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 631 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 632 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 633 0x0e800120, 0x0f800ff0,
634 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 635 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 636 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 637 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 638 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 639 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 640 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 641 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 642 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 643 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 644 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 645 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 646 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 647 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571
TG		 648 0x0e8000a0, 0x0f800ff0,
649 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 650 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 651 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 652 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 653 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 654 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 655 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 656 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 657 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 658 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 659 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 660 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 661 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 662 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 663 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 664 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 665 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 666 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 667 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
6b0dd094 668 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 669 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 670 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 671 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 672 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 673 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 674 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 675 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 676 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 677 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 678 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 679 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 680 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 681 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
6b0dd094 682 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 683 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 684 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 685 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
6b0dd094 686 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 687 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
6b0dd094 688 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 689 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
6b0dd094 690 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 691 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
6b0dd094 692 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 693 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 694 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 695 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 696 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 697 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 698 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 699 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
6b0dd094 700 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 701 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
6b0dd094 702 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 703 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
6b0dd094 704 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 705 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
6b0dd094 706 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 707 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 708 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 709 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 710 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
823d2571 711 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
6b0dd094 712 {ANY, ARM_FEATURE_CORE_LOW (0),
823d2571 713 SENTINEL_IWMMXT_END, 0, "" },
2fbad815 714
fe56b6ce 715 /* Floating point coprocessor (FPA) instructions. */
6b0dd094 716 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 717 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 718 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 719 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 720 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 721 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 722 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 723 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 724 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 725 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 726 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 727 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 728 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 729 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 730 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 731 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 732 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 733 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 734 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 735 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 736 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 737 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 738 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 739 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 740 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 741 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
6b0dd094 742 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 743 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 744 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 745 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
6b0dd094 746 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 747 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 748 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 749 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 750 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 751 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
6b0dd094 752 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 753 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
6b0dd094 754 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 755 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 756 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 757 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
6b0dd094 758 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 759 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
6b0dd094 760 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 761 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
6b0dd094 762 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 763 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
6b0dd094 764 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 765 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 766 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 767 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
6b0dd094 768 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 769 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
6b0dd094 770 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 771 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
6b0dd094 772 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 773 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
6b0dd094 774 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 775 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
6b0dd094 776 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 777 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
6b0dd094 778 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 779 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
6b0dd094 780 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 781 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
6b0dd094 782 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 783 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
6b0dd094 784 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 785 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
6b0dd094 786 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 787 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
6b0dd094 788 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 789 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
6b0dd094 790 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 791 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
6b0dd094 792 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 793 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
6b0dd094 794 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 795 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
6b0dd094 796 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
823d2571 797 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
6b0dd094 798 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 799 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
6b0dd094 800 {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
823d2571 801 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
2fbad815 802
efd6b359
AV		 803 /* Armv8.1-M Mainline instructions. */
804 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
805 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
806 {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
807 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
808
16a1fa25 809 /* ARMv8-M Mainline Security Extensions instructions. */
6b0dd094 810 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25 811 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
6b0dd094 812 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
16a1fa25
TP		 813 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
814
fe56b6ce 815 /* Register load/store. */
6b0dd094 816 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 817 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
6b0dd094 818 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 819 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
6b0dd094 820 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 821 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
6b0dd094 822 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 823 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
6b0dd094 824 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 825 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
6b0dd094 826 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 827 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
6b0dd094 828 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 829 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
6b0dd094 830 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
823d2571 831 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
6b0dd094 832 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 833 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
6b0dd094 834 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 835 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
6b0dd094 836 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 837 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
6b0dd094 838 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 839 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
6b0dd094 840 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 841 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
6b0dd094 842 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 843 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
6b0dd094 844 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 845 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
6b0dd094 846 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 847 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
32c36c3c
AV		 848 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
849 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
850 {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
851 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
823d2571 852
6b0dd094 853 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 854 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 855 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 856 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
6b0dd094 857 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 858 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
6b0dd094 859 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 860 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
16980d0b 861
fe56b6ce 862 /* Data transfer between ARM and NEON registers. */
6b0dd094 863 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 864 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
6b0dd094 865 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 866 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
6b0dd094 867 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 868 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
6b0dd094 869 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 870 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
6b0dd094 871 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 872 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
6b0dd094 873 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 874 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
6b0dd094 875 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 876 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
6b0dd094 877 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
823d2571 878 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
8e79c3df 879 /* Half-precision conversion instructions. */
6b0dd094 880 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 881 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
6b0dd094 882 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 883 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
6b0dd094 884 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 885 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
6b0dd094 886 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
823d2571 887 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
16980d0b 888
fe56b6ce 889 /* Floating point coprocessor (VFP) instructions. */
6b0dd094 890 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 891 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
2da2eaf4 892 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 893 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
ba6cd17f
SD		 894 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
895 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
6b0dd094 896 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 897 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
6b0dd094 898 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 899 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
6b0dd094 900 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 901 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
6b0dd094 902 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 903 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
6b0dd094 904 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 905 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
6b0dd094 906 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 907 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
2da2eaf4 908 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 909 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
2da2eaf4 910 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 911 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
912 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
913 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
914 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
915 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
6b0dd094 916 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 917 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
6b0dd094 918 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 919 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
2da2eaf4 920 {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
823d2571 921 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
ba6cd17f
SD		 922 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
923 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
6b0dd094 924 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
40c7d507 925 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
6b0dd094 926 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 927 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
6b0dd094 928 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 929 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
6b0dd094 930 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 931 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
6b0dd094 932 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 933 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
6b0dd094 934 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 935 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
2da2eaf4 936 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f 937 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
2da2eaf4 938 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ba6cd17f
SD		 939 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
940 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
941 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
942 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
943 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
6b0dd094 944 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 945 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
6b0dd094 946 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 947 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
6b0dd094 948 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 949 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
6b0dd094 950 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 951 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
6b0dd094 952 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 953 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
6b0dd094 954 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 955 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
6b0dd094 956 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 957 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
6b0dd094 958 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 959 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
6b0dd094 960 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 961 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
6b0dd094 962 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 963 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
6b0dd094 964 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 965 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
6b0dd094 966 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 967 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
6b0dd094 968 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 969 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
6b0dd094 970 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 971 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
6b0dd094 972 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 973 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
6b0dd094 974 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 975 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
6b0dd094 976 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 977 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
6b0dd094 978 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 979 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
6b0dd094 980 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 981 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
6b0dd094 982 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 983 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
6b0dd094 984 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 985 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
6b0dd094 986 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 987 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
6b0dd094 988 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 989 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 990 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 991 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
6b0dd094 992 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 993 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
6b0dd094 994 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 995 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
6b0dd094 996 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
823d2571 997 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
6b0dd094 998 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
823d2571 999 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
6b0dd094 1000 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1001 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
6b0dd094 1002 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
6f1c2142 1003 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
6b0dd094 1004 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
6f1c2142 1005 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
6b0dd094 1006 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1007 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
6b0dd094 1008 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1009 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
6b0dd094 1010 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
823d2571 1011 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
6b0dd094 1012 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1013 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1014 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1015 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1016 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1017 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1018 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1019 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1020 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1021 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
6b0dd094 1022 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1023 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
6b0dd094 1024 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1025 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
6b0dd094 1026 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1027 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
6b0dd094 1028 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1029 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1030 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1031 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
6b0dd094 1032 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1033 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1034 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1035 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
6b0dd094 1036 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1037 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
6b0dd094 1038 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1039 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
6b0dd094 1040 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1041 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
6b0dd094 1042 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1043 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
6b0dd094 1044 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
823d2571 1045 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
6b0dd094 1046 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
823d2571 1047 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
2fbad815
RE		 1048
1049 /* Cirrus coprocessor instructions. */
6b0dd094 1050 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1051 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1052 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1053 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
6b0dd094 1054 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1055 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1056 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1057 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
6b0dd094 1058 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1059 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1060 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1061 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
6b0dd094 1062 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1063 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1064 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1065 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
6b0dd094 1066 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1067 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1068 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1069 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
6b0dd094 1070 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1071 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1072 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1073 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
6b0dd094 1074 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1075 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1076 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1077 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
6b0dd094 1078 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1079 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1080 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1081 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
6b0dd094 1082 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1083 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
6b0dd094 1084 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1085 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
6b0dd094 1086 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1087 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1088 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1089 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
6b0dd094 1090 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1091 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
6b0dd094 1092 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1093 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
6b0dd094 1094 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1095 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1096 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1097 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1098 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1099 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
6b0dd094 1100 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1101 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
6b0dd094 1102 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1103 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1104 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1105 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1106 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1107 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1108 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1109 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1110 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1111 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1112 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1113 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1114 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1115 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
6b0dd094 1116 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1117 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
6b0dd094 1118 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1119 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
6b0dd094 1120 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1121 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
6b0dd094 1122 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1123 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
6b0dd094 1124 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1125 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
6b0dd094 1126 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1127 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1128 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1129 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1130 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1131 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
6b0dd094 1132 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1133 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
6b0dd094 1134 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1135 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
6b0dd094 1136 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1137 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
6b0dd094 1138 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1139 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
6b0dd094 1140 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1141 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
6b0dd094 1142 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1143 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1144 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1145 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1146 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1147 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
6b0dd094 1148 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1149 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
6b0dd094 1150 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1151 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
6b0dd094 1152 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1153 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
6b0dd094 1154 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1155 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
6b0dd094 1156 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1157 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
6b0dd094 1158 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1159 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
6b0dd094 1160 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1161 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
6b0dd094 1162 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1163 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1164 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1165 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1166 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1167 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1168 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1169 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1170 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1171 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
6b0dd094 1172 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1173 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
6b0dd094 1174 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1175 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1176 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1177 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1178 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1179 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1180 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1181 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1182 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1183 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
6b0dd094 1184 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1185 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
6b0dd094 1186 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1187 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1188 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1189 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1190 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1191 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
6b0dd094 1192 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1193 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
6b0dd094 1194 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1195 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1196 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1197 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1198 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1199 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1200 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1201 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1202 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1203 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1204 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1205 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
6b0dd094 1206 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1207 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1208 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571 1209 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1210 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1211 0x0e000600, 0x0ff00f10,
1212 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1213 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1214 0x0e100600, 0x0ff00f10,
1215 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1216 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1217 0x0e200600, 0x0ff00f10,
1218 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
6b0dd094 1219 {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
823d2571
TG		 1220 0x0e300600, 0x0ff00f10,
1221 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
2fbad815 1222
62f3b8c8 1223 /* VFP Fused multiply add instructions. */
6b0dd094 1224 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1225 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1226 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1227 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1228 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1229 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1230 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1231 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
6b0dd094 1232 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1233 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
6b0dd094 1234 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1235 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
6b0dd094 1236 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1237 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
6b0dd094 1238 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
823d2571 1239 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
62f3b8c8 1240
33399f07 1241 /* FP v5. */
6b0dd094 1242 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1243 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
6b0dd094 1244 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1245 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
6b0dd094 1246 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1247 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1248 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1249 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1250 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1251 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
6b0dd094 1252 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1253 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
6b0dd094 1254 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1255 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
6b0dd094 1256 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1257 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
6b0dd094 1258 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1259 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
6b0dd094 1260 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
823d2571 1261 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
6b0dd094 1262 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1263 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
6b0dd094 1264 {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
3e309328 1265 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
33399f07 1266
6b0dd094 1267 {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
c28eeff2 1268 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
6b0dd094 1269 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1270 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1271 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1272 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
6b0dd094 1273 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1274 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1275 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1276 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1277 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1278 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
6b0dd094 1279 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c28eeff2 1280 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
6b0dd094 1281 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1282 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
6b0dd094 1283 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1284 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
6b0dd094 1285 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1286 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
6b0dd094 1287 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
c13a63b0 1288 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
c28eeff2 1289
aab2c27d
MM		 1290 /* BFloat16 instructions. */
1291 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1292 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1293
c604a79a 1294 /* Dot Product instructions in the space of coprocessor 13. */
6b0dd094 1295 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
c604a79a 1296 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
6b0dd094 1297 {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
aab2c27d 1298 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
c604a79a 1299
dec41383 1300 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
6b0dd094 1301 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1302 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1303 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1304 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
6b0dd094 1305 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1306 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1307 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1308 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
6b0dd094 1309 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1310 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1311 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1312 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
6b0dd094 1313 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383 1314 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
6b0dd094 1315 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
dec41383
JW		 1316 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1317
b0c11777
RL		 1318 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1319 cp_num: bit <11:8> == 0b1001.
1320 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
6b0dd094 1321 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1322 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
6b0dd094 1323 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1324 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
6b0dd094 1325 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1326 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
6b0dd094 1327 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1328 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
6b0dd094 1329 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1330 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
6b0dd094 1331 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1332 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
6b0dd094 1333 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1334 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
6b0dd094 1335 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1336 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
6b0dd094 1337 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1338 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
6b0dd094 1339 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1340 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
6b0dd094 1341 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1342 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1343 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1344 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1345 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1346 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
6b0dd094 1347 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1348 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
6b0dd094 1349 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1350 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
6b0dd094 1351 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1352 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
6b0dd094 1353 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1354 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
6b0dd094 1355 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1356 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
6b0dd094 1357 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1358 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1359 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1360 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
6b0dd094 1361 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1362 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1363 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1364 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1365 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1366 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
6b0dd094 1367 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1368 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
6b0dd094 1369 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1370 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
6b0dd094 1371 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1372 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1373 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1374 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
6b0dd094 1375 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1376 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
6b0dd094 1377 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1378 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
6b0dd094 1379 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1380 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
6b0dd094 1381 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1382 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
6b0dd094 1383 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1384 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
6b0dd094 1385 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1386 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
6b0dd094 1387 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777 1388 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
6b0dd094 1389 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
b0c11777
RL		 1390 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1391
49e8a725 1392 /* ARMv8.3 javascript conversion instruction. */
6b0dd094 1393 {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
49e8a725
SN		 1394 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1395
6b0dd094 1396 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2fbad815
RE		 1397};
1398
33593eaf
MM		 1399/* Generic coprocessor instructions. These are only matched if a more specific
1400 SIMD or co-processor instruction does not match first. */
1401
1402static const struct sopcode32 generic_coprocessor_opcodes[] =
1403{
1404 /* Generic coprocessor instructions. */
1405 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1406 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1407 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
1408 0x0c500000, 0x0ff00000,
1409 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1410 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1411 0x0e000000, 0x0f000010,
1412 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1413 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1414 0x0e10f010, 0x0f10f010,
1415 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1416 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1417 0x0e100010, 0x0f100010,
1418 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1419 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1420 0x0e000010, 0x0f100010,
1421 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1422 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1423 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1424 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1425 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1426
1427 /* V6 coprocessor instructions. */
1428 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1429 0xfc500000, 0xfff00000,
1430 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1431 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1432 0xfc400000, 0xfff00000,
1433 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1434
1435 /* V5 coprocessor instructions. */
1436 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1437 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1438 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1439 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1440 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1441 0xfe000000, 0xff000010,
1442 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1443 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1444 0xfe000010, 0xff100010,
1445 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1446 {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
1447 0xfe100010, 0xff100010,
1448 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1449
1450 {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1451};
1452
16980d0b
JB		 1453/* Neon opcode table: This does not encode the top byte -- that is
1454 checked by the print_insn_neon routine, as it depends on whether we are
1455 doing thumb32 or arm32 disassembly. */
1456
1457/* print_insn_neon recognizes the following format control codes:
1458
1459 %% %
1460
c22aaad1 1461 %c print condition code
e2efe87d
MGD		 1462 %u print condition code (unconditional in ARM mode,
1463 UNPREDICTABLE if not AL in Thumb)
16980d0b
JB		 1464 %A print v{st,ld}[1234] operands
1465 %B print v{st,ld}[1234] any one operands
1466 %C print v{st,ld}[1234] single->all operands
1467 %D print scalar
1468 %E print vmov, vmvn, vorr, vbic encoded constant
1469 %F print vtbl,vtbx register list
1470
1471 %<bitfield>r print as an ARM register
1472 %<bitfield>d print the bitfield in decimal
1473 %<bitfield>e print the 2^N - bitfield in decimal
1474 %<bitfield>D print as a NEON D register
1475 %<bitfield>Q print as a NEON Q register
1476 %<bitfield>R print as a NEON D or Q register
1477 %<bitfield>Sn print byte scaled width limited by n
1478 %<bitfield>Tn print short scaled width limited by n
1479 %<bitfield>Un print long scaled width limited by n
43e65147 1480
16980d0b
JB		 1481 %<bitfield>'c print specified char iff bitfield is all ones
1482 %<bitfield>`c print specified char iff bitfield is all zeroes
fe56b6ce 1483 %<bitfield>?ab... select from array of values in big endian order. */
16980d0b
JB		 1484
1485static const struct opcode32 neon_opcodes[] =
1486{
fe56b6ce 1487 /* Extract. */
823d2571
TG		 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1489 0xf2b00840, 0xffb00850,
1490 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492 0xf2b00000, 0xffb00810,
1493 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
16980d0b 1494
9743db03
AV		 1495 /* Data transfer between ARM and NEON registers. */
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1497 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
9743db03 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1499 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
9743db03 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1501 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
9743db03 1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1503 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
9743db03 1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1505 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
9743db03 1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
e409955d 1507 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
9743db03 1508
fe56b6ce 1509 /* Move data element to all lanes. */
823d2571
TG		 1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1511 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1513 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1515 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
16980d0b 1516
fe56b6ce 1517 /* Table lookup. */
823d2571
TG		 1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1519 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1521 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1522
8e79c3df 1523 /* Half-precision conversions. */
823d2571
TG		 1524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1525 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1527 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
62f3b8c8
PB		 1528
1529 /* NEON fused multiply add instructions. */
823d2571 1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1531 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1533 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
cc933301
JW		 1535 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1537 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
8e79c3df 1538
aab2c27d
MM		 1539 /* BFloat16 instructions. */
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1541 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1543 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1545 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1547 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1549 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
1551 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1552
616ce08e
MM		 1553 /* Matrix Multiply instructions. */
1554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1555 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1557 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1559 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1561 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1563 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
1565 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1566
fe56b6ce 1567 /* Two registers, miscellaneous. */
823d2571
TG		 1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1569 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1571 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1573 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1575 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1576 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1577 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1578 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1579 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1580 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1581 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1582 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1583 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1584 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1585 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1586 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1587 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1589 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1591 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1593 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1595 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1597 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1599 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1601 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1603 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1605 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1607 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1609 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1611 0xf3b20300, 0xffb30fd0,
1612 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1616 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1618 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1620 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
823d2571
TG		 1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1624 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1632 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1634 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1638 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1640 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1642 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1644 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1646 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1648 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1650 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1652 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301 1660 0xf3bb0600, 0xffbf0e10,
823d2571 1661 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
cc933301
JW		 1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1663 0xf3b70600, 0xffbf0e10,
1664 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
16980d0b 1665
fe56b6ce 1666 /* Three registers of the same length. */
823d2571
TG		 1667 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1668 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1669 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1670 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1671 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1672 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1673 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1674 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1675 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1676 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1677 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1678 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1679 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1680 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1682 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1684 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
cc933301
JW		 1686 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1688 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1692 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1694 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1696 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1698 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1700 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1702 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1704 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1706 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1708 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1710 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1712 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1714 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1716 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1718 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1720 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1722 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1724 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1726 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1728 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1730 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1732 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1734 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1736 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1738 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1740 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1742 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1744 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1746 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1748 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1750 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1752 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1754 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1756 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1758 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1760 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1762 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1764 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1766 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1768 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1770 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1772 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571 1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
cc933301
JW		 1774 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1776 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
823d2571
TG		 1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1778 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1780 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1782 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1784 0xf2000b00, 0xff800f10,
1785 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1787 0xf2000b10, 0xff800f10,
1788 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1790 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1792 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1794 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1796 0xf3000b00, 0xff800f10,
1797 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1799 0xf2000000, 0xfe800f10,
1800 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1802 0xf2000010, 0xfe800f10,
1803 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1805 0xf2000100, 0xfe800f10,
1806 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1808 0xf2000200, 0xfe800f10,
1809 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1811 0xf2000210, 0xfe800f10,
1812 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1814 0xf2000300, 0xfe800f10,
1815 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1817 0xf2000310, 0xfe800f10,
1818 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1820 0xf2000400, 0xfe800f10,
1821 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1823 0xf2000410, 0xfe800f10,
1824 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1826 0xf2000500, 0xfe800f10,
1827 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1829 0xf2000510, 0xfe800f10,
1830 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1832 0xf2000600, 0xfe800f10,
1833 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1835 0xf2000610, 0xfe800f10,
1836 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1838 0xf2000700, 0xfe800f10,
1839 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1841 0xf2000710, 0xfe800f10,
1842 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1844 0xf2000910, 0xfe800f10,
1845 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1847 0xf2000a00, 0xfe800f10,
1848 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1850 0xf2000a10, 0xfe800f10,
1851 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
d6b4b13e
MW		 1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1853 0xf3000b10, 0xff800f10,
1854 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1856 0xf3000c10, 0xff800f10,
1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
16980d0b 1858
fe56b6ce 1859 /* One register and an immediate value. */
823d2571
TG		 1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1861 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1863 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1865 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1867 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1869 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1871 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1873 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1875 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1877 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1879 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1881 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1883 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1885 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
16980d0b 1886
fe56b6ce 1887 /* Two registers and a shift amount. */
823d2571
TG		 1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1889 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1891 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1893 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1895 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1897 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1899 0xf2880950, 0xfeb80fd0,
1900 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1902 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1904 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1906 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1908 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1910 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1912 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1914 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1916 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1918 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1920 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1922 0xf2900950, 0xfeb00fd0,
1923 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1925 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1927 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1929 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1931 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1933 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1935 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1937 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1939 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1941 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1943 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1945 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1947 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1949 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1951 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1953 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1955 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1957 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1959 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1961 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1963 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1965 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1967 0xf2a00950, 0xfea00fd0,
1968 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1970 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1972 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1974 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1976 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1978 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1980 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1982 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1984 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1986 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1988 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1990 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1992 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1994 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1996 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1998 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2000 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2002 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2004 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2006 0xf2a00e10, 0xfea00e90,
2007 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
cc933301
JW		 2008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
2009 0xf2a00c10, 0xfea00e90,
2010 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
16980d0b 2011
fe56b6ce 2012 /* Three registers of different lengths. */
823d2571
TG		 2013 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
2014 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2016 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2018 0xf2800400, 0xff800f50,
2019 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2021 0xf2800600, 0xff800f50,
2022 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2024 0xf2800900, 0xff800f50,
2025 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2027 0xf2800b00, 0xff800f50,
2028 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2030 0xf2800d00, 0xff800f50,
2031 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2033 0xf3800400, 0xff800f50,
2034 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2036 0xf3800600, 0xff800f50,
2037 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2039 0xf2800000, 0xfe800f50,
2040 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2042 0xf2800100, 0xfe800f50,
2043 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2045 0xf2800200, 0xfe800f50,
2046 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2048 0xf2800300, 0xfe800f50,
2049 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2051 0xf2800500, 0xfe800f50,
2052 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2054 0xf2800700, 0xfe800f50,
2055 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2057 0xf2800800, 0xfe800f50,
2058 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2060 0xf2800a00, 0xfe800f50,
2061 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2063 0xf2800c00, 0xfe800f50,
2064 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
16980d0b 2065
fe56b6ce 2066 /* Two registers and a scalar. */
823d2571
TG		 2067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2068 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2070 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2071 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2072 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2073 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2074 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2076 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2078 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2079 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2080 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2082 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2084 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2086 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2087 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2088 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
823d2571
TG		 2089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2090 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2092 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2094 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2096 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2098 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2099 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2100 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2102 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2104 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2105 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2106 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2108 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
589a7d88
JW		 2110 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2111 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
2112 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
823d2571
TG		 2113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2114 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2116 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2118 0xf2800240, 0xfe800f50,
2119 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2121 0xf2800640, 0xfe800f50,
2122 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2124 0xf2800a40, 0xfe800f50,
2125 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
d6b4b13e
MW		 2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2127 0xf2800e40, 0xff800f50,
2128 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2130 0xf2800f40, 0xff800f50,
2131 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2133 0xf3800e40, 0xff800f50,
2134 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
2136 0xf3800f40, 0xff800f50,
2137 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2138 },
16980d0b 2139
fe56b6ce 2140 /* Element and structure load/store. */
823d2571
TG		 2141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2142 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2144 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2146 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2148 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2150 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2152 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2154 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2156 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2158 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2160 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2162 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2164 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2166 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2168 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2170 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2172 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2174 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2176 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
2178 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2179
2180 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
16980d0b
JB		 2181};
2182
73cd51e5
AV		 2183/* mve opcode table. */
2184
2185/* print_insn_mve recognizes the following format control codes:
2186
2187 %% %
2188
ef1576a1
AV		 2189 %a print '+' or '-' or imm offset in vldr[bhwd] and
2190 vstr[bhwd]
9743db03 2191 %c print condition code
aef6d006
AV		 2192 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2193 %u print 'U' (unsigned) or 'S' for various mve instructions
143275ea 2194 %i print MVE predicate(s) for vpt and vpst
23d00a41 2195 %j print a 5-bit immediate from hw2[14:12,7:6]
08132bdd 2196 %k print 48 if the 7th position bit is set else print 64.
bf0b396d 2197 %m print rounding mode for vcvt and vrint
143275ea 2198 %n print vector comparison code for predicated instruction
bf0b396d 2199 %s print size for various vcvt instructions
143275ea
AV		 2200 %v print vector predicate for instruction in predicated
2201 block
ef1576a1 2202 %o print offset scaled for vldr[hwd] and vstr[hwd]
04d54ace
AV		 2203 %w print writeback mode for MVE v{st,ld}[24]
2204 %B print v{st,ld}[24] any one operands
c507f10b
AV		 2205 %E print vmov, vmvn, vorr, vbic encoded constant
2206 %N print generic index for vmov
14925797 2207 %T print bottom ('b') or top ('t') of source register
d3b63143 2208 %X print exchange field in vmla* instructions
04d54ace 2209
9743db03 2210 %<bitfield>r print as an ARM register
04d54ace 2211 %<bitfield>d print the bitfield in decimal
d3b63143 2212 %<bitfield>A print accumulate or not
e39c1607
SD		 2213 %<bitfield>c print bitfield as a condition code
2214 %<bitfield>C print bitfield as an inverted condition code
143275ea 2215 %<bitfield>Q print as a MVE Q register
c507f10b 2216 %<bitfield>F print as a MVE S register
143275ea
AV		 2217 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2218 UNPREDICTABLE
23d00a41
SD		 2219
2220 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
143275ea 2221 %<bitfield>s print size for vector predicate & non VMOV instructions
66dcaa5d 2222 %<bitfield>I print carry flag or not
ef1576a1 2223 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1c8f2df8 2224 %<bitfield>h print high half of 64-bit destination reg
bf0b396d 2225 %<bitfield>k print immediate for vector conversion instruction
1c8f2df8 2226 %<bitfield>l print low half of 64-bit destination reg
897b9bbc 2227 %<bitfield>o print rotate value for vcmul
1c8f2df8 2228 %<bitfield>u print immediate value for vddup/vdwdup
c507f10b 2229 %<bitfield>x print the bitfield in hex.
1c8f2df8 2230 */
73cd51e5
AV		 2231
2232static const struct mopcode32 mve_opcodes[] =
2233{
143275ea
AV		 2234 /* MVE. */
2235
2da2eaf4 2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2237 MVE_VPST,
2238 0xfe310f4d, 0xffbf1fff,
2239 "vpst%i"
2240 },
2241
2242 /* Floating point VPT T1. */
2da2eaf4 2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2244 MVE_VPT_FP_T1,
2245 0xee310f00, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2247 /* Floating point VPT T2. */
2da2eaf4 2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2249 MVE_VPT_FP_T2,
2250 0xee310f40, 0xefb10f50,
2251 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2252
2253 /* Vector VPT T1. */
2da2eaf4 2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2255 MVE_VPT_VEC_T1,
2256 0xfe010f00, 0xff811f51,
2257 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T2. */
2da2eaf4 2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2260 MVE_VPT_VEC_T2,
2261 0xfe010f01, 0xff811f51,
2262 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T3. */
2da2eaf4 2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2265 MVE_VPT_VEC_T3,
2266 0xfe011f00, 0xff811f50,
2267 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2268 /* Vector VPT T4. */
2da2eaf4 2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2270 MVE_VPT_VEC_T4,
2271 0xfe010f40, 0xff811f70,
2272 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T5. */
2da2eaf4 2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2275 MVE_VPT_VEC_T5,
2276 0xfe010f60, 0xff811f70,
2277 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2278 /* Vector VPT T6. */
2da2eaf4 2279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2280 MVE_VPT_VEC_T6,
2281 0xfe011f40, 0xff811f50,
2282 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2283
c507f10b 2284 /* Vector VBIC immediate. */
2da2eaf4 2285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2286 MVE_VBIC_IMM,
2287 0xef800070, 0xefb81070,
2288 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2289
2290 /* Vector VBIC register. */
2da2eaf4 2291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2292 MVE_VBIC_REG,
2293 0xef100150, 0xffb11f51,
2294 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2295
66dcaa5d 2296 /* Vector VABAV. */
2da2eaf4 2297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2298 MVE_VABAV,
2299 0xee800f01, 0xefc10f51,
2300 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2301
2302 /* Vector VABD floating point. */
2da2eaf4 2303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2304 MVE_VABD_FP,
2305 0xff200d40, 0xffa11f51,
2306 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2307
2308 /* Vector VABD. */
2da2eaf4 2309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2310 MVE_VABD_VEC,
2311 0xef000740, 0xef811f51,
2312 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2313
2314 /* Vector VABS floating point. */
2da2eaf4 2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2316 MVE_VABS_FP,
2317 0xFFB10740, 0xFFB31FD1,
2318 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2319 /* Vector VABS. */
2da2eaf4 2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2321 MVE_VABS_VEC,
2322 0xffb10340, 0xffb31fd1,
2323 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2324
2325 /* Vector VADD floating point T1. */
2da2eaf4 2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2327 MVE_VADD_FP_T1,
2328 0xef000d40, 0xffa11f51,
2329 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2330 /* Vector VADD floating point T2. */
2da2eaf4 2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 2332 MVE_VADD_FP_T2,
2333 0xee300f40, 0xefb11f70,
2334 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2335 /* Vector VADD T1. */
2da2eaf4 2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2337 MVE_VADD_VEC_T1,
2338 0xef000840, 0xff811f51,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340 /* Vector VADD T2. */
2da2eaf4 2341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2342 MVE_VADD_VEC_T2,
2343 0xee010f40, 0xff811f70,
2344 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2345
d3b63143 2346 /* Vector VADDLV. */
2da2eaf4 2347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2348 MVE_VADDLV,
2349 0xee890f00, 0xef8f1fd1,
2350 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2351
2352 /* Vector VADDV. */
2da2eaf4 2353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2354 MVE_VADDV,
2355 0xeef10f00, 0xeff31fd1,
2356 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2357
66dcaa5d 2358 /* Vector VADC. */
2da2eaf4 2359 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 2360 MVE_VADC,
2361 0xee300f00, 0xffb10f51,
2362 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2363
e523f101 2364 /* Vector VAND. */
2da2eaf4 2365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2366 MVE_VAND,
2367 0xef000150, 0xffb11f51,
2368 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2369
2370 /* Vector VBRSR register. */
2da2eaf4 2371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2372 MVE_VBRSR,
2373 0xfe011e60, 0xff811f70,
2374 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2375
897b9bbc 2376 /* Vector VCADD floating point. */
2da2eaf4 2377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2378 MVE_VCADD_FP,
2379 0xfc800840, 0xfea11f51,
2380 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2381
2382 /* Vector VCADD. */
2da2eaf4 2383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2384 MVE_VCADD_VEC,
2385 0xfe000f00, 0xff810f51,
2386 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2387
e523f101 2388 /* Vector VCLS. */
2da2eaf4 2389 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2390 MVE_VCLS,
2391 0xffb00440, 0xffb31fd1,
2392 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2393
2394 /* Vector VCLZ. */
2da2eaf4 2395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2396 MVE_VCLZ,
2397 0xffb004c0, 0xffb31fd1,
2398 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2399
897b9bbc 2400 /* Vector VCMLA. */
2da2eaf4 2401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2402 MVE_VCMLA_FP,
2403 0xfc200840, 0xfe211f51,
2404 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2405
143275ea 2406 /* Vector VCMP floating point T1. */
2da2eaf4 2407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2408 MVE_VCMP_FP_T1,
2409 0xee310f00, 0xeff1ef50,
2410 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2411
2412 /* Vector VCMP floating point T2. */
2da2eaf4 2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
143275ea
AV		 2414 MVE_VCMP_FP_T2,
2415 0xee310f40, 0xeff1ef50,
2416 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2417
2418 /* Vector VCMP T1. */
2da2eaf4 2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2420 MVE_VCMP_VEC_T1,
2421 0xfe010f00, 0xffc1ff51,
2422 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T2. */
2da2eaf4 2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2425 MVE_VCMP_VEC_T2,
2426 0xfe010f01, 0xffc1ff51,
2427 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T3. */
2da2eaf4 2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2430 MVE_VCMP_VEC_T3,
2431 0xfe011f00, 0xffc1ff50,
2432 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2433 /* Vector VCMP T4. */
2da2eaf4 2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2435 MVE_VCMP_VEC_T4,
2436 0xfe010f40, 0xffc1ff70,
2437 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T5. */
2da2eaf4 2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2440 MVE_VCMP_VEC_T5,
2441 0xfe010f60, 0xffc1ff70,
2442 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2443 /* Vector VCMP T6. */
2da2eaf4 2444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
143275ea
AV		 2445 MVE_VCMP_VEC_T6,
2446 0xfe011f40, 0xffc1ff50,
2447 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2448
9743db03 2449 /* Vector VDUP. */
2da2eaf4 2450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2451 MVE_VDUP,
2452 0xeea00b10, 0xffb10f5f,
2453 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2454
2455 /* Vector VEOR. */
2da2eaf4 2456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2457 MVE_VEOR,
2458 0xff000150, 0xffd11f51,
2459 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2460
2461 /* Vector VFMA, vector * scalar. */
2da2eaf4 2462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2463 MVE_VFMA_FP_SCALAR,
2464 0xee310e40, 0xefb11f70,
2465 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2466
2467 /* Vector VFMA floating point. */
2da2eaf4 2468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2469 MVE_VFMA_FP,
2470 0xef000c50, 0xffa11f51,
2471 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2472
2473 /* Vector VFMS floating point. */
2da2eaf4 2474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2475 MVE_VFMS_FP,
2476 0xef200c50, 0xffa11f51,
2477 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2478
2479 /* Vector VFMAS, vector * scalar. */
2da2eaf4 2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
9743db03
AV		 2481 MVE_VFMAS_FP_SCALAR,
2482 0xee311e40, 0xefb11f70,
2483 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2484
2485 /* Vector VHADD T1. */
2da2eaf4 2486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2487 MVE_VHADD_T1,
2488 0xef000040, 0xef811f51,
2489 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2490
2491 /* Vector VHADD T2. */
2da2eaf4 2492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2493 MVE_VHADD_T2,
2494 0xee000f40, 0xef811f70,
2495 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2496
2497 /* Vector VHSUB T1. */
2da2eaf4 2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2499 MVE_VHSUB_T1,
2500 0xef000240, 0xef811f51,
2501 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2502
2503 /* Vector VHSUB T2. */
2da2eaf4 2504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2505 MVE_VHSUB_T2,
2506 0xee001f40, 0xef811f70,
2507 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2508
897b9bbc 2509 /* Vector VCMUL. */
2da2eaf4 2510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
897b9bbc
AV		 2511 MVE_VCMUL_FP,
2512 0xee300e00, 0xefb10f50,
2513 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2514
e523f101 2515 /* Vector VCTP. */
2da2eaf4 2516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
e523f101
AV		 2517 MVE_VCTP,
2518 0xf000e801, 0xffc0ffff,
2519 "vctp%v.%20-21s\t%16-19r"},
2520
9743db03 2521 /* Vector VDUP. */
2da2eaf4 2522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2523 MVE_VDUP,
2524 0xeea00b10, 0xffb10f5f,
2525 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2526
2527 /* Vector VRHADD. */
2da2eaf4 2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
9743db03
AV		 2529 MVE_VRHADD,
2530 0xef000140, 0xef811f51,
2531 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2532
bf0b396d 2533 /* Vector VCVT. */
2da2eaf4 2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2535 MVE_VCVT_FP_FIX_VEC,
2536 0xef800c50, 0xef801cd1,
2537 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2538
2539 /* Vector VCVT. */
2da2eaf4 2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2541 MVE_VCVT_BETWEEN_FP_INT,
2542 0xffb30640, 0xffb31e51,
2543 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2544
2545 /* Vector VCVT between single and half-precision float, bottom half. */
2da2eaf4 2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2547 MVE_VCVT_FP_HALF_FP,
2548 0xee3f0e01, 0xefbf1fd1,
2549 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2550
2551 /* Vector VCVT between single and half-precision float, top half. */
2da2eaf4 2552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2553 MVE_VCVT_FP_HALF_FP,
2554 0xee3f1e01, 0xefbf1fd1,
2555 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2556
2557 /* Vector VCVT. */
2da2eaf4 2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 2559 MVE_VCVT_FROM_FP_TO_INT,
2560 0xffb30040, 0xffb31c51,
2561 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2562
1c8f2df8 2563 /* Vector VDDUP. */
2da2eaf4 2564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2565 MVE_VDDUP,
2566 0xee011f6e, 0xff811f7e,
2567 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2568
2569 /* Vector VDWDUP. */
2da2eaf4 2570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2571 MVE_VDWDUP,
2572 0xee011f60, 0xff811f70,
2573 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2574
897b9bbc 2575 /* Vector VHCADD. */
2da2eaf4 2576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
897b9bbc
AV		 2577 MVE_VHCADD,
2578 0xee000f00, 0xff810f51,
2579 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2580
1c8f2df8 2581 /* Vector VIWDUP. */
2da2eaf4 2582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2583 MVE_VIWDUP,
2584 0xee010f60, 0xff811f70,
2585 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2586
2587 /* Vector VIDUP. */
2da2eaf4 2588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
1c8f2df8
AV		 2589 MVE_VIDUP,
2590 0xee010f6e, 0xff811f7e,
2591 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2592
04d54ace 2593 /* Vector VLD2. */
2da2eaf4 2594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2595 MVE_VLD2,
2596 0xfc901e00, 0xff901e5f,
2597 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2598
2599 /* Vector VLD4. */
2da2eaf4 2600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 2601 MVE_VLD4,
2602 0xfc901e01, 0xff901e1f,
2603 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2604
ef1576a1 2605 /* Vector VLDRB gather load. */
2da2eaf4 2606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2607 MVE_VLDRB_GATHER_T1,
2608 0xec900e00, 0xefb01e50,
2609 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2610
2611 /* Vector VLDRH gather load. */
2da2eaf4 2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2613 MVE_VLDRH_GATHER_T2,
2614 0xec900e10, 0xefb01e50,
2615 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2616
2617 /* Vector VLDRW gather load. */
2da2eaf4 2618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2619 MVE_VLDRW_GATHER_T3,
2620 0xfc900f40, 0xffb01fd0,
2621 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2622
2623 /* Vector VLDRD gather load. */
2da2eaf4 2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2625 MVE_VLDRD_GATHER_T4,
2626 0xec900fd0, 0xefb01fd0,
2627 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2628
2629 /* Vector VLDRW gather load. */
2da2eaf4 2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2631 MVE_VLDRW_GATHER_T5,
2632 0xfd101e00, 0xff111f00,
2633 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2634
2635 /* Vector VLDRD gather load, variant T6. */
2da2eaf4 2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 2637 MVE_VLDRD_GATHER_T6,
2638 0xfd101f00, 0xff111f00,
2639 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2640
aef6d006 2641 /* Vector VLDRB. */
2da2eaf4 2642 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2643 MVE_VLDRB_T1,
2644 0xec100e00, 0xee581e00,
2645 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2646
2647 /* Vector VLDRH. */
2da2eaf4 2648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2649 MVE_VLDRH_T2,
2650 0xec180e00, 0xee581e00,
2651 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2652
2653 /* Vector VLDRB unsigned, variant T5. */
2da2eaf4 2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2655 MVE_VLDRB_T5,
2656 0xec101e00, 0xfe101f80,
2657 "vldrb%v.u8\t%13-15,22Q, %d"},
2658
2659 /* Vector VLDRH unsigned, variant T6. */
2da2eaf4 2660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2661 MVE_VLDRH_T6,
2662 0xec101e80, 0xfe101f80,
2663 "vldrh%v.u16\t%13-15,22Q, %d"},
2664
2665 /* Vector VLDRW unsigned, variant T7. */
2da2eaf4 2666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 2667 MVE_VLDRW_T7,
2668 0xec101f00, 0xfe101f80,
2669 "vldrw%v.u32\t%13-15,22Q, %d"},
2670
56858bea 2671 /* Vector VMAX. */
2da2eaf4 2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2673 MVE_VMAX,
2674 0xef000640, 0xef811f51,
2675 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2676
2677 /* Vector VMAXA. */
2da2eaf4 2678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2679 MVE_VMAXA,
2680 0xee330e81, 0xffb31fd1,
2681 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2682
2683 /* Vector VMAXNM floating point. */
2da2eaf4 2684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2685 MVE_VMAXNM_FP,
2686 0xff000f50, 0xffa11f51,
2687 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2688
2689 /* Vector VMAXNMA floating point. */
2da2eaf4 2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2691 MVE_VMAXNMA_FP,
2692 0xee3f0e81, 0xefbf1fd1,
2693 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2694
2695 /* Vector VMAXNMV floating point. */
2da2eaf4 2696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2697 MVE_VMAXNMV_FP,
2698 0xeeee0f00, 0xefff0fd1,
2699 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2700
2701 /* Vector VMAXNMAV floating point. */
2da2eaf4 2702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2703 MVE_VMAXNMAV_FP,
2704 0xeeec0f00, 0xefff0fd1,
2705 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2706
2707 /* Vector VMAXV. */
2da2eaf4 2708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2709 MVE_VMAXV,
2710 0xeee20f00, 0xeff30fd1,
2711 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2712
2713 /* Vector VMAXAV. */
2da2eaf4 2714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2715 MVE_VMAXAV,
2716 0xeee00f00, 0xfff30fd1,
2717 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2718
2719 /* Vector VMIN. */
2da2eaf4 2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2721 MVE_VMIN,
2722 0xef000650, 0xef811f51,
2723 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2724
2725 /* Vector VMINA. */
2da2eaf4 2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2727 MVE_VMINA,
2728 0xee331e81, 0xffb31fd1,
2729 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2730
2731 /* Vector VMINNM floating point. */
2da2eaf4 2732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2733 MVE_VMINNM_FP,
2734 0xff200f50, 0xffa11f51,
2735 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2736
2737 /* Vector VMINNMA floating point. */
2da2eaf4 2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2739 MVE_VMINNMA_FP,
2740 0xee3f1e81, 0xefbf1fd1,
2741 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2742
2743 /* Vector VMINNMV floating point. */
2da2eaf4 2744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2745 MVE_VMINNMV_FP,
2746 0xeeee0f80, 0xefff0fd1,
2747 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2748
2749 /* Vector VMINNMAV floating point. */
2da2eaf4 2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
56858bea
AV		 2751 MVE_VMINNMAV_FP,
2752 0xeeec0f80, 0xefff0fd1,
2753 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2754
2755 /* Vector VMINV. */
2da2eaf4 2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2757 MVE_VMINV,
2758 0xeee20f80, 0xeff30fd1,
2759 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2760
2761 /* Vector VMINAV. */
2da2eaf4 2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2763 MVE_VMINAV,
2764 0xeee00f80, 0xfff30fd1,
2765 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2766
2767 /* Vector VMLA. */
2da2eaf4 2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
56858bea
AV		 2769 MVE_VMLA,
2770 0xee010e40, 0xef811f70,
2771 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2772
d3b63143
AV		 2773 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2774 opcode aliasing. */
2da2eaf4 2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2776 MVE_VMLALDAV,
2777 0xee801e00, 0xef801f51,
2778 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2779
2da2eaf4 2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2781 MVE_VMLALDAV,
2782 0xee800e00, 0xef801f51,
2783 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2784
2785 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2787 MVE_VMLADAV_T1,
2788 0xeef00e00, 0xeff01f51,
2789 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2790
2791 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2da2eaf4 2792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2793 MVE_VMLADAV_T2,
2794 0xeef00f00, 0xeff11f51,
2795 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2796
2797 /* Vector VMLADAV T1 variant. */
2da2eaf4 2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2799 MVE_VMLADAV_T1,
2800 0xeef01e00, 0xeff01f51,
2801 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2802
2803 /* Vector VMLADAV T2 variant. */
2da2eaf4 2804 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2805 MVE_VMLADAV_T2,
2806 0xeef01f00, 0xeff11f51,
2807 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2808
2809 /* Vector VMLAS. */
2da2eaf4 2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2811 MVE_VMLAS,
2812 0xee011e40, 0xef811f70,
2813 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2814
2815 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2816 opcode aliasing. */
2da2eaf4 2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2818 MVE_VRMLSLDAVH,
2819 0xfe800e01, 0xff810f51,
2820 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2821
2822 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2823 opcdoe aliasing. */
2da2eaf4 2824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2825 MVE_VMLSLDAV,
2826 0xee800e01, 0xff800f51,
2827 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2828
2829 /* Vector VMLSDAV T1 Variant. */
2da2eaf4 2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2831 MVE_VMLSDAV_T1,
2832 0xeef00e01, 0xfff00f51,
2833 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2834
2835 /* Vector VMLSDAV T2 Variant. */
2da2eaf4 2836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 2837 MVE_VMLSDAV_T2,
2838 0xfef00e01, 0xfff10f51,
2839 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2840
c507f10b 2841 /* Vector VMOV between gpr and half precision register, op == 0. */
2da2eaf4 2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2843 MVE_VMOV_HFP_TO_GP,
2844 0xee000910, 0xfff00f7f,
2845 "vmov.f16\t%7,16-19F, %12-15r"},
2846
2847 /* Vector VMOV between gpr and half precision register, op == 1. */
2da2eaf4 2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2849 MVE_VMOV_HFP_TO_GP,
2850 0xee100910, 0xfff00f7f,
2851 "vmov.f16\t%12-15r, %7,16-19F"},
2852
2da2eaf4 2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2854 MVE_VMOV_GP_TO_VEC_LANE,
2855 0xee000b10, 0xff900f1f,
2856 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2857
2858 /* Vector VORR immediate to vector.
2859 NOTE: MVE_VORR_IMM must appear in the table
2860 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2862 MVE_VORR_IMM,
2863 0xef800050, 0xefb810f0,
2864 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2865
ed63aa17
AV		 2866 /* Vector VQSHL T2 Variant.
2867 NOTE: MVE_VQSHL_T2 must appear in the table before
2868 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2869 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2870 MVE_VQSHL_T2,
2871 0xef800750, 0xef801fd1,
2872 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2873
2874 /* Vector VQSHLU T3 Variant
2875 NOTE: MVE_VQSHL_T2 must appear in the table before
2876 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2877
2da2eaf4 2878 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2879 MVE_VQSHLU_T3,
2880 0xff800650, 0xff801fd1,
2881 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2882
2883 /* Vector VRSHR
2884 NOTE: MVE_VRSHR must appear in the table before
2885 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2887 MVE_VRSHR,
2888 0xef800250, 0xef801fd1,
2889 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2890
2891 /* Vector VSHL.
2892 NOTE: MVE_VSHL must appear in the table before
2893 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2895 MVE_VSHL_T1,
2896 0xef800550, 0xff801fd1,
2897 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2898
2899 /* Vector VSHR
2900 NOTE: MVE_VSHR must appear in the table before
2901 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2903 MVE_VSHR,
2904 0xef800050, 0xef801fd1,
2905 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2906
2907 /* Vector VSLI
2908 NOTE: MVE_VSLI must appear in the table before
2909 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2911 MVE_VSLI,
2912 0xff800550, 0xff801fd1,
2913 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2914
2915 /* Vector VSRI
2916 NOTE: MVE_VSRI must appear in the table before
2917 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2da2eaf4 2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2919 MVE_VSRI,
2920 0xff800450, 0xff801fd1,
2921 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2922
c507f10b 2923 /* Vector VMOV immediate to vector,
ce760a76 2924 undefinded for cmode == 1111 */
2da2eaf4 2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2926 MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
2927
2928 /* Vector VMOV immediate to vector,
2929 cmode == 1101 */
2da2eaf4 2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ce760a76
MI		 2931 MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
2932 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
c507f10b
AV		 2933
2934 /* Vector VMOV immediate to vector. */
2da2eaf4 2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2936 MVE_VMOV_IMM_TO_VEC,
2937 0xef800050, 0xefb810d0,
2938 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2939
2940 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2da2eaf4 2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2942 MVE_VMOV2_VEC_LANE_TO_GP,
2943 0xec000f00, 0xffb01ff0,
2944 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2945
2946 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2da2eaf4 2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2948 MVE_VMOV2_VEC_LANE_TO_GP,
2949 0xec000f10, 0xffb01ff0,
2950 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2951
2952 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2da2eaf4 2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2954 MVE_VMOV2_GP_TO_VEC_LANE,
2955 0xec100f00, 0xffb01ff0,
2956 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2957
2958 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2da2eaf4 2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 2960 MVE_VMOV2_GP_TO_VEC_LANE,
2961 0xec100f10, 0xffb01ff0,
2962 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2963
2964 /* Vector VMOV Vector lane to gpr. */
2da2eaf4 2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2966 MVE_VMOV_VEC_LANE_TO_GP,
2967 0xee100b10, 0xff100f1f,
2968 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2969
ed63aa17
AV		 2970 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2971 to instruction opcode aliasing. */
2da2eaf4 2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 2973 MVE_VSHLL_T1,
2974 0xeea00f40, 0xefa00fd1,
2975 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2976
14925797 2977 /* Vector VMOVL long. */
2da2eaf4 2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2979 MVE_VMOVL,
2980 0xeea00f40, 0xefa70fd1,
2981 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2982
2983 /* Vector VMOV and narrow. */
2da2eaf4 2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 2985 MVE_VMOVN,
2986 0xfe310e81, 0xffb30fd1,
2987 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2988
c507f10b 2989 /* Floating point move extract. */
2da2eaf4 2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
c507f10b
AV		 2991 MVE_VMOVX,
2992 0xfeb00a40, 0xffbf0fd0,
2993 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2994
f49bb598 2995 /* Vector VMUL floating-point T1 variant. */
2da2eaf4 2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 2997 MVE_VMUL_FP_T1,
2998 0xff000d50, 0xffa11f51,
2999 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3000
3001 /* Vector VMUL floating-point T2 variant. */
2da2eaf4 3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3003 MVE_VMUL_FP_T2,
3004 0xee310e60, 0xefb11f70,
3005 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006
3007 /* Vector VMUL T1 variant. */
2da2eaf4 3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3009 MVE_VMUL_VEC_T1,
3010 0xef000950, 0xff811f51,
3011 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3012
3013 /* Vector VMUL T2 variant. */
2da2eaf4 3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3015 MVE_VMUL_VEC_T2,
3016 0xee011e60, 0xff811f70,
3017 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3018
3019 /* Vector VMULH. */
2da2eaf4 3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3021 MVE_VMULH,
3022 0xee010e01, 0xef811f51,
3023 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3024
3025 /* Vector VRMULH. */
2da2eaf4 3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3027 MVE_VRMULH,
3028 0xee011e01, 0xef811f51,
3029 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3030
14925797 3031 /* Vector VMULL integer. */
2da2eaf4 3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3033 MVE_VMULL_INT,
3034 0xee010e00, 0xef810f51,
3035 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3036
3037 /* Vector VMULL polynomial. */
2da2eaf4 3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3039 MVE_VMULL_POLY,
3040 0xee310e00, 0xefb10f51,
3041 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3042
c507f10b 3043 /* Vector VMVN immediate to vector. */
2da2eaf4 3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3045 MVE_VMVN_IMM,
3046 0xef800070, 0xefb810f0,
3047 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3048
3049 /* Vector VMVN register. */
2da2eaf4 3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3051 MVE_VMVN_REG,
3052 0xffb005c0, 0xffbf1fd1,
3053 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3054
f49bb598 3055 /* Vector VNEG floating point. */
2da2eaf4 3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
f49bb598
AV		 3057 MVE_VNEG_FP,
3058 0xffb107c0, 0xffb31fd1,
3059 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3060
3061 /* Vector VNEG. */
2da2eaf4 3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
f49bb598
AV		 3063 MVE_VNEG_VEC,
3064 0xffb103c0, 0xffb31fd1,
3065 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3066
c507f10b 3067 /* Vector VORN, vector bitwise or not. */
2da2eaf4 3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3069 MVE_VORN,
3070 0xef300150, 0xffb11f51,
3071 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3072
3073 /* Vector VORR register. */
2da2eaf4 3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c507f10b
AV		 3075 MVE_VORR_REG,
3076 0xef200150, 0xffb11f51,
3077 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3078
c4a23bf8
SP		 3079 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3080 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3081 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3082 array. */
3083
2da2eaf4 3084 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
c4a23bf8
SP		 3085 MVE_VMOV_VEC_TO_VEC,
3086 0xef200150, 0xffb11f51,
3087 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3088
14925797 3089 /* Vector VQDMULL T1 variant. */
2da2eaf4 3090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3091 MVE_VQDMULL_T1,
3092 0xee300f01, 0xefb10f51,
3093 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3094
14b456f2 3095 /* Vector VPNOT. */
2da2eaf4 3096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3097 MVE_VPNOT,
3098 0xfe310f4d, 0xffffffff,
3099 "vpnot%v"},
3100
3101 /* Vector VPSEL. */
2da2eaf4 3102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3103 MVE_VPSEL,
3104 0xfe310f01, 0xffb11f51,
3105 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3106
3107 /* Vector VQABS. */
2da2eaf4 3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3109 MVE_VQABS,
3110 0xffb00740, 0xffb31fd1,
3111 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3112
3113 /* Vector VQADD T1 variant. */
2da2eaf4 3114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3115 MVE_VQADD_T1,
3116 0xef000050, 0xef811f51,
3117 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3118
3119 /* Vector VQADD T2 variant. */
2da2eaf4 3120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3121 MVE_VQADD_T2,
3122 0xee000f60, 0xef811f70,
3123 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3124
14925797 3125 /* Vector VQDMULL T2 variant. */
2da2eaf4 3126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3127 MVE_VQDMULL_T2,
3128 0xee300f60, 0xefb10f70,
3129 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3130
3131 /* Vector VQMOVN. */
2da2eaf4 3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3133 MVE_VQMOVN,
3134 0xee330e01, 0xefb30fd1,
3135 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3136
3137 /* Vector VQMOVUN. */
2da2eaf4 3138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14925797
AV		 3139 MVE_VQMOVUN,
3140 0xee310e81, 0xffb30fd1,
3141 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3142
d3b63143 3143 /* Vector VQDMLADH. */
2da2eaf4 3144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3145 MVE_VQDMLADH,
3146 0xee000e00, 0xff810f51,
3147 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3148
3149 /* Vector VQRDMLADH. */
2da2eaf4 3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3151 MVE_VQRDMLADH,
3152 0xee000e01, 0xff810f51,
3153 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3154
3155 /* Vector VQDMLAH. */
2da2eaf4 3156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3157 MVE_VQDMLAH,
23d188c7 3158 0xee000e60, 0xff811f70,
d3b63143
AV		 3159 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3160
3161 /* Vector VQRDMLAH. */
2da2eaf4 3162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3163 MVE_VQRDMLAH,
23d188c7 3164 0xee000e40, 0xff811f70,
d3b63143
AV		 3165 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3166
3167 /* Vector VQDMLASH. */
2da2eaf4 3168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3169 MVE_VQDMLASH,
23d188c7 3170 0xee001e60, 0xff811f70,
d3b63143
AV		 3171 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3172
3173 /* Vector VQRDMLASH. */
2da2eaf4 3174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143 3175 MVE_VQRDMLASH,
23d188c7 3176 0xee001e40, 0xff811f70,
d3b63143
AV		 3177 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3178
3179 /* Vector VQDMLSDH. */
2da2eaf4 3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3181 MVE_VQDMLSDH,
3182 0xfe000e00, 0xff810f51,
3183 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3184
3185 /* Vector VQRDMLSDH. */
2da2eaf4 3186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3187 MVE_VQRDMLSDH,
3188 0xfe000e01, 0xff810f51,
3189 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3190
3191 /* Vector VQDMULH T1 variant. */
2da2eaf4 3192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3193 MVE_VQDMULH_T1,
3194 0xef000b40, 0xff811f51,
3195 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3196
3197 /* Vector VQRDMULH T2 variant. */
2da2eaf4 3198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3199 MVE_VQRDMULH_T2,
3200 0xff000b40, 0xff811f51,
3201 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3202
3203 /* Vector VQDMULH T3 variant. */
2da2eaf4 3204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3205 MVE_VQDMULH_T3,
3206 0xee010e60, 0xff811f70,
3207 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3208
3209 /* Vector VQRDMULH T4 variant. */
2da2eaf4 3210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3211 MVE_VQRDMULH_T4,
3212 0xfe010e60, 0xff811f70,
3213 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3214
14b456f2 3215 /* Vector VQNEG. */
2da2eaf4 3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3217 MVE_VQNEG,
3218 0xffb007c0, 0xffb31fd1,
3219 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3220
ed63aa17 3221 /* Vector VQRSHL T1 variant. */
2da2eaf4 3222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3223 MVE_VQRSHL_T1,
3224 0xef000550, 0xef811f51,
3225 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3226
3227 /* Vector VQRSHL T2 variant. */
2da2eaf4 3228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3229 MVE_VQRSHL_T2,
3230 0xee331ee0, 0xefb31ff0,
3231 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3232
3233 /* Vector VQRSHRN. */
2da2eaf4 3234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3235 MVE_VQRSHRN,
3236 0xee800f41, 0xefa00fd1,
3237 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3238
3239 /* Vector VQRSHRUN. */
2da2eaf4 3240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3241 MVE_VQRSHRUN,
3242 0xfe800fc0, 0xffa00fd1,
3243 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3244
3245 /* Vector VQSHL T1 Variant. */
2da2eaf4 3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3247 MVE_VQSHL_T1,
3248 0xee311ee0, 0xefb31ff0,
3249 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3250
3251 /* Vector VQSHL T4 Variant. */
2da2eaf4 3252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3253 MVE_VQSHL_T4,
3254 0xef000450, 0xef811f51,
3255 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3256
3257 /* Vector VQSHRN. */
2da2eaf4 3258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3259 MVE_VQSHRN,
3260 0xee800f40, 0xefa00fd1,
3261 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3262
3263 /* Vector VQSHRUN. */
2da2eaf4 3264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3265 MVE_VQSHRUN,
3266 0xee800fc0, 0xffa00fd1,
3267 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3268
14b456f2 3269 /* Vector VQSUB T1 Variant. */
2da2eaf4 3270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3271 MVE_VQSUB_T1,
3272 0xef000250, 0xef811f51,
3273 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3274
3275 /* Vector VQSUB T2 Variant. */
2da2eaf4 3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3277 MVE_VQSUB_T2,
3278 0xee001f60, 0xef811f70,
3279 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3280
3281 /* Vector VREV16. */
2da2eaf4 3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3283 MVE_VREV16,
3284 0xffb00140, 0xffb31fd1,
3285 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3286
3287 /* Vector VREV32. */
2da2eaf4 3288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3289 MVE_VREV32,
3290 0xffb000c0, 0xffb31fd1,
3291 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3292
3293 /* Vector VREV64. */
2da2eaf4 3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
14b456f2
AV		 3295 MVE_VREV64,
3296 0xffb00040, 0xffb31fd1,
3297 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3298
bf0b396d 3299 /* Vector VRINT floating point. */
2da2eaf4 3300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
bf0b396d
AV		 3301 MVE_VRINT_FP,
3302 0xffb20440, 0xffb31c51,
3303 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3304
d3b63143 3305 /* Vector VRMLALDAVH. */
2da2eaf4 3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3307 MVE_VRMLALDAVH,
3308 0xee800f00, 0xef811f51,
3309 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3310
3311 /* Vector VRMLALDAVH. */
2da2eaf4 3312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
d3b63143
AV		 3313 MVE_VRMLALDAVH,
3314 0xee801f00, 0xef811f51,
3315 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3316
ed63aa17 3317 /* Vector VRSHL T1 Variant. */
2da2eaf4 3318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3319 MVE_VRSHL_T1,
3320 0xef000540, 0xef811f51,
3321 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3322
3323 /* Vector VRSHL T2 Variant. */
2da2eaf4 3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3325 MVE_VRSHL_T2,
3326 0xee331e60, 0xefb31ff0,
3327 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3328
3329 /* Vector VRSHRN. */
2da2eaf4 3330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3331 MVE_VRSHRN,
3332 0xfe800fc1, 0xffa00fd1,
3333 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3334
66dcaa5d 3335 /* Vector VSBC. */
2da2eaf4 3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3337 MVE_VSBC,
3338 0xfe300f00, 0xffb10f51,
3339 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3340
ed63aa17 3341 /* Vector VSHL T2 Variant. */
2da2eaf4 3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3343 MVE_VSHL_T2,
3344 0xee311e60, 0xefb31ff0,
3345 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3346
3347 /* Vector VSHL T3 Variant. */
2da2eaf4 3348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3349 MVE_VSHL_T3,
3350 0xef000440, 0xef811f51,
3351 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3352
3353 /* Vector VSHLC. */
2da2eaf4 3354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3355 MVE_VSHLC,
3356 0xeea00fc0, 0xffa01ff0,
3357 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3358
3359 /* Vector VSHLL T2 Variant. */
2da2eaf4 3360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3361 MVE_VSHLL_T2,
3362 0xee310e01, 0xefb30fd1,
3363 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3364
3365 /* Vector VSHRN. */
2da2eaf4 3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ed63aa17
AV		 3367 MVE_VSHRN,
3368 0xee800fc1, 0xffa00fd1,
3369 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3370
04d54ace 3371 /* Vector VST2 no writeback. */
2da2eaf4 3372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3373 MVE_VST2,
3374 0xfc801e00, 0xffb01e5f,
3375 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3376
3377 /* Vector VST2 writeback. */
2da2eaf4 3378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3379 MVE_VST2,
3380 0xfca01e00, 0xffb01e5f,
3381 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3382
3383 /* Vector VST4 no writeback. */
2da2eaf4 3384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3385 MVE_VST4,
3386 0xfc801e01, 0xffb01e1f,
3387 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3388
3389 /* Vector VST4 writeback. */
2da2eaf4 3390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
04d54ace
AV		 3391 MVE_VST4,
3392 0xfca01e01, 0xffb01e1f,
3393 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3394
ef1576a1 3395 /* Vector VSTRB scatter store, T1 variant. */
2da2eaf4 3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3397 MVE_VSTRB_SCATTER_T1,
3398 0xec800e00, 0xffb01e50,
3399 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3400
3401 /* Vector VSTRH scatter store, T2 variant. */
2da2eaf4 3402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3403 MVE_VSTRH_SCATTER_T2,
3404 0xec800e10, 0xffb01e50,
3405 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3406
3407 /* Vector VSTRW scatter store, T3 variant. */
2da2eaf4 3408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3409 MVE_VSTRW_SCATTER_T3,
3410 0xec800e40, 0xffb01e50,
3411 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3412
3413 /* Vector VSTRD scatter store, T4 variant. */
2da2eaf4 3414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3415 MVE_VSTRD_SCATTER_T4,
3416 0xec800fd0, 0xffb01fd0,
3417 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3418
3419 /* Vector VSTRW scatter store, T5 variant. */
2da2eaf4 3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3421 MVE_VSTRW_SCATTER_T5,
3422 0xfd001e00, 0xff111f00,
3423 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3424
3425 /* Vector VSTRD scatter store, T6 variant. */
2da2eaf4 3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
ef1576a1
AV		 3427 MVE_VSTRD_SCATTER_T6,
3428 0xfd001f00, 0xff111f00,
3429 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3430
aef6d006 3431 /* Vector VSTRB. */
2da2eaf4 3432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3433 MVE_VSTRB_T1,
3434 0xec000e00, 0xfe581e00,
3435 "vstrb%v.%7-8s\t%13-15Q, %d"},
3436
3437 /* Vector VSTRH. */
2da2eaf4 3438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3439 MVE_VSTRH_T2,
3440 0xec080e00, 0xfe581e00,
3441 "vstrh%v.%7-8s\t%13-15Q, %d"},
3442
3443 /* Vector VSTRB variant T5. */
2da2eaf4 3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3445 MVE_VSTRB_T5,
3446 0xec001e00, 0xfe101f80,
3447 "vstrb%v.8\t%13-15,22Q, %d"},
3448
3449 /* Vector VSTRH variant T6. */
2da2eaf4 3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3451 MVE_VSTRH_T6,
3452 0xec001e80, 0xfe101f80,
3453 "vstrh%v.16\t%13-15,22Q, %d"},
3454
3455 /* Vector VSTRW variant T7. */
2da2eaf4 3456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
aef6d006
AV		 3457 MVE_VSTRW_T7,
3458 0xec001f00, 0xfe101f80,
3459 "vstrw%v.32\t%13-15,22Q, %d"},
3460
66dcaa5d 3461 /* Vector VSUB floating point T1 variant. */
2da2eaf4 3462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3463 MVE_VSUB_FP_T1,
3464 0xef200d40, 0xffa11f51,
3465 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3466
3467 /* Vector VSUB floating point T2 variant. */
2da2eaf4 3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
66dcaa5d
AV		 3469 MVE_VSUB_FP_T2,
3470 0xee301f40, 0xefb11f70,
3471 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3472
3473 /* Vector VSUB T1 variant. */
2da2eaf4 3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3475 MVE_VSUB_VEC_T1,
3476 0xff000840, 0xff811f51,
3477 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3478
3479 /* Vector VSUB T2 variant. */
2da2eaf4 3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
66dcaa5d
AV		 3481 MVE_VSUB_VEC_T2,
3482 0xee011f40, 0xff811f70,
3483 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3484
2da2eaf4 3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3486 MVE_ASRLI,
3487 0xea50012f, 0xfff1813f,
3488 "asrl%c\t%17-19l, %9-11h, %j"},
3489
2da2eaf4 3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3491 MVE_ASRL,
3492 0xea50012d, 0xfff101ff,
3493 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3494
2da2eaf4 3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3496 MVE_LSLLI,
3497 0xea50010f, 0xfff1813f,
3498 "lsll%c\t%17-19l, %9-11h, %j"},
3499
2da2eaf4 3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3501 MVE_LSLL,
3502 0xea50010d, 0xfff101ff,
3503 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3504
2da2eaf4 3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3506 MVE_LSRL,
3507 0xea50011f, 0xfff1813f,
3508 "lsrl%c\t%17-19l, %9-11h, %j"},
3509
2da2eaf4 3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3511 MVE_SQRSHRL,
08132bdd
SP		 3512 0xea51012d, 0xfff1017f,
3513 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3514
2da2eaf4 3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3516 MVE_SQRSHR,
3517 0xea500f2d, 0xfff00fff,
3518 "sqrshr%c\t%16-19S, %12-15S"},
3519
2da2eaf4 3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3521 MVE_SQSHLL,
3522 0xea51013f, 0xfff1813f,
3523 "sqshll%c\t%17-19l, %9-11h, %j"},
3524
2da2eaf4 3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3526 MVE_SQSHL,
3527 0xea500f3f, 0xfff08f3f,
3528 "sqshl%c\t%16-19S, %j"},
3529
2da2eaf4 3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3531 MVE_SRSHRL,
3532 0xea51012f, 0xfff1813f,
3533 "srshrl%c\t%17-19l, %9-11h, %j"},
3534
2da2eaf4 3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3536 MVE_SRSHR,
3537 0xea500f2f, 0xfff08f3f,
3538 "srshr%c\t%16-19S, %j"},
3539
2da2eaf4 3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41 3541 MVE_UQRSHLL,
08132bdd
SP		 3542 0xea51010d, 0xfff1017f,
3543 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
23d00a41 3544
2da2eaf4 3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3546 MVE_UQRSHL,
3547 0xea500f0d, 0xfff00fff,
3548 "uqrshl%c\t%16-19S, %12-15S"},
3549
2da2eaf4 3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3551 MVE_UQSHLL,
3552 0xea51010f, 0xfff1813f,
3553 "uqshll%c\t%17-19l, %9-11h, %j"},
3554
2da2eaf4 3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3556 MVE_UQSHL,
3557 0xea500f0f, 0xfff08f3f,
3558 "uqshl%c\t%16-19S, %j"},
3559
2da2eaf4 3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3561 MVE_URSHRL,
3562 0xea51011f, 0xfff1813f,
3563 "urshrl%c\t%17-19l, %9-11h, %j"},
3564
2da2eaf4 3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
23d00a41
SD		 3566 MVE_URSHR,
3567 0xea500f1f, 0xfff08f3f,
3568 "urshr%c\t%16-19S, %j"},
3569
e39c1607
SD		 3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3571 MVE_CSINC,
3572 0xea509000, 0xfff0f000,
3573 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3574
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3576 MVE_CSINV,
3577 0xea50a000, 0xfff0f000,
3578 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3579
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3581 MVE_CSET,
3582 0xea5f900f, 0xfffff00f,
3583 "cset\t%8-11S, %4-7C"},
3584
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3586 MVE_CSETM,
3587 0xea5fa00f, 0xfffff00f,
3588 "csetm\t%8-11S, %4-7C"},
3589
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3591 MVE_CSEL,
3592 0xea508000, 0xfff0f000,
3593 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3594
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3596 MVE_CSNEG,
3597 0xea50b000, 0xfff0f000,
3598 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3599
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3601 MVE_CINC,
3602 0xea509000, 0xfff0f000,
3603 "cinc\t%8-11S, %16-19Z, %4-7C"},
3604
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3606 MVE_CINV,
3607 0xea50a000, 0xfff0f000,
3608 "cinv\t%8-11S, %16-19Z, %4-7C"},
3609
3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
3611 MVE_CNEG,
3612 0xea50b000, 0xfff0f000,
3613 "cneg\t%8-11S, %16-19Z, %4-7C"},
3614
143275ea
AV		 3615 {ARM_FEATURE_CORE_LOW (0),
3616 MVE_NONE,
3617 0x00000000, 0x00000000, 0}
73cd51e5
AV		 3618};
3619
8f06b2d8
PB		 3620/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3621 ordered: they must be searched linearly from the top to obtain a correct
3622 match. */
3623
3624/* print_insn_arm recognizes the following format control codes:
3625
3626 %% %
3627
3628 %a print address for ldr/str instruction
3629 %s print address for ldr/str halfword/signextend instruction
c1e26897 3630 %S like %s but allow UNPREDICTABLE addressing
8f06b2d8
PB		 3631 %b print branch destination
3632 %c print condition code (always bits 28-31)
3633 %m print register mask for ldm/stm instruction
3634 %o print operand2 (immediate or register + shift)
3635 %p print 'p' iff bits 12-15 are 15
3636 %t print 't' iff bit 21 set and bit 24 clear
3637 %B print arm BLX(1) destination
3638 %C print the PSR sub type.
62b3e311
PB		 3639 %U print barrier type.
3640 %P print address for pli instruction.
8f06b2d8
PB		 3641
3642 %<bitfield>r print as an ARM register
9eb6c0f1 3643 %<bitfield>T print as an ARM register + 1
ff4a8d2b
NC		 3644 %<bitfield>R as %r but r15 is UNPREDICTABLE
3645 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3646 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
8f06b2d8 3647 %<bitfield>d print the bitfield in decimal
43e65147 3648 %<bitfield>W print the bitfield plus one in decimal
8f06b2d8
PB		 3649 %<bitfield>x print the bitfield in hex
3650 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
43e65147 3651
16980d0b
JB		 3652 %<bitfield>'c print specified char iff bitfield is all ones
3653 %<bitfield>`c print specified char iff bitfield is all zeroes
3654 %<bitfield>?ab... select from array of values in big endian order
4a5329c6 3655
8f06b2d8
PB		 3656 %e print arm SMI operand (bits 0..7,8..19).
3657 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
90ec0d68
MGD		 3658 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3659 %R print the SPSR/CPSR or banked register of an MRS. */
2fbad815 3660
8f06b2d8
PB		 3661static const struct opcode32 arm_opcodes[] =
3662{
3663 /* ARM instructions. */
823d2571
TG		 3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3665 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3667 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3668
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
3670 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3672 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
3674 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
3676 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3678 0x00800090, 0x0fa000f0,
3679 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
3681 0x00a00090, 0x0fa000f0,
3682 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
c19d1205 3683
105bde57 3684 /* V8.2 RAS extension instructions. */
4d1464f2 3685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 3686 0xe320f010, 0xffffffff, "esb"},
3687
53c4b28b 3688 /* V8 instructions. */
823d2571
TG		 3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3690 0x0320f005, 0x0fffffff, "sevl"},
f7dd2fb2
TC		 3691 /* Defined in V8 but is in NOP space so available to all arch. */
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
823d2571 3693 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
4ed7ed8d 3694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
823d2571 3695 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3696 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571
TG		 3697 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3699 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
3701 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
4ed7ed8d 3702 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3703 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3704 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3705 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3706 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3707 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
4ed7ed8d 3708 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3709 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3710 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3711 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3712 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3713 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3714 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3715 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3716 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3717 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4ed7ed8d 3718 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
823d2571 3719 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
4ed7ed8d 3720 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
3395762e 3721 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
dd5181d5 3722 /* CRC32 instructions. */
8b301fbb 3723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3724 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3725 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3726 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3728 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3730 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3732 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
8b301fbb 3733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
823d2571 3734 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
53c4b28b 3735
ddfded2f
MW		 3736 /* Privileged Access Never extension instructions. */
3737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
3738 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3739
90ec0d68 3740 /* Virtualization Extension instructions. */
823d2571
TG		 3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
90ec0d68 3743
eea54501 3744 /* Integer Divide Extension instructions. */
823d2571
TG		 3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3746 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
3748 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
eea54501 3749
60e5ef9f 3750 /* MP Extension instructions. */
823d2571 3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
60e5ef9f 3752
c597cc3d
SD		 3753 /* Speculation Barriers. */
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"},
3757
62b3e311 3758 /* V7 instructions. */
823d2571
TG		 3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
4ab90a7a
AV		 3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
3767 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
62b3e311 3768
c19d1205 3769 /* ARM V6T2 instructions. */
823d2571
TG		 3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3771 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3773 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3775 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3777 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3778
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3780 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3782 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3783
ff8646ee 3784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 3785 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
ff8646ee 3786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 3787 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3789 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3791 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
885fc257 3792
f4c65163 3793 /* ARM Security extension instructions. */
823d2571
TG		 3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
3795 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2fbad815 3796
8f06b2d8 3797 /* ARM V6K instructions. */
823d2571
TG		 3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3799 0xf57ff01f, 0xffffffff, "clrex"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3801 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3803 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3805 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3807 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3809 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3811 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
c19d1205 3812
7fadb25d
SD		 3813 /* ARMv8.5-A instructions. */
3814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
3815
8f06b2d8 3816 /* ARM V6K NOP hints. */
823d2571
TG		 3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3818 0x0320f001, 0x0fffffff, "yield%c"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3820 0x0320f002, 0x0fffffff, "wfe%c"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3822 0x0320f003, 0x0fffffff, "wfi%c"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3824 0x0320f004, 0x0fffffff, "sev%c"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
3826 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
c19d1205 3827
fe56b6ce 3828 /* ARM V6 instructions. */
823d2571
TG		 3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3830 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3832 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3834 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3836 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3838 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3840 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3842 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3844 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3846 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3848 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3850 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3852 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3854 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3856 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3858 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3860 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3862 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3864 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3866 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3868 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3870 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3872 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3874 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3876 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3878 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3880 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3882 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3884 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3886 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3888 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3890 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3892 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3894 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3896 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3898 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3900 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3902 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3904 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3906 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3908 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3910 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3912 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3914 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3916 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3918 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3920 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3922 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3924 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3926 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3928 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3930 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3932 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3934 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3936 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3938 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3940 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3942 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3944 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3946 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3948 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3950 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3952 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3954 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3956 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3958 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3960 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3962 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3964 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3966 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3968 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3970 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3972 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3974 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3976 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3978 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3980 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3982 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3984 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3986 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3988 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3990 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3992 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3994 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3996 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
3998 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4000 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4002 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4004 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4006 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4008 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4010 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4012 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4014 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4016 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4018 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4020 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4022 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4024 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4026 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4028 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4030 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4032 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4034 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4036 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4038 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4040 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4042 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4044 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4046 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4048 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4050 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4052 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4054 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4056 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4058 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4060 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4062 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4064 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4066 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4068 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4070 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
4072 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
c19d1205 4073
8f06b2d8 4074 /* V5J instruction. */
823d2571
TG		 4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
4076 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
c19d1205 4077
8f06b2d8 4078 /* V5 Instructions. */
823d2571
TG		 4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4080 0xe1200070, 0xfff000f0,
4081 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4083 0xfa000000, 0xfe000000, "blx\t%B"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4085 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
4087 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4088
4089 /* V5E "El Segundo" Instructions. */
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4091 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4093 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
4095 0xf450f000, 0xfc70f000, "pld\t%a"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4097 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4099 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4101 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4103 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4104
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4106 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4108 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4109
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4111 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4113 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4115 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4117 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4118
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4120 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4122 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4124 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4126 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4127
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4129 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4131 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4132
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4134 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4136 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4138 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
4140 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
c19d1205 4141
8f06b2d8 4142 /* ARM Instructions. */
823d2571
TG		 4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4144 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4145
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4147 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4149 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4151 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4153 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4155 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4157 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4158
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4160 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4162 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4164 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4166 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4167
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4169 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4171 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4173 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4175 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4176
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4178 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4180 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4182 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4183
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4185 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4187 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4189 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4190
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4192 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4194 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4196 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4197
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4199 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4201 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4203 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4204
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4206 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4208 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4210 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4211
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4213 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4215 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4217 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4218
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4220 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4222 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4224 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4225
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4227 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4229 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4231 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4232
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
4234 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4236 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
4238 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4239
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4241 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4243 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4245 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4246
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4248 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
823d2571 4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4250 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
823d2571 4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4ab90a7a 4252 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
823d2571
TG		 4253
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4255 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4257 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4259 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4260
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4262 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4264 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4266 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4267
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4269 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4271 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4273 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4274
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4276 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4278 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4280 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4282 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4284 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4286 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4288 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4289
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4291 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4293 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4295 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4296
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4298 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4300 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4302 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4303
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4305 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4307 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4308
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4310 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4311
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4313 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4315 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4316
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4318 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4320 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4322 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4324 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4326 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4328 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4330 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4332 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4334 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4336 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4338 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4340 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4342 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4344 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4346 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4348 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4350 0x092d0000, 0x0fff0000, "push%c\t%m"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4352 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4354 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4355
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4357 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4359 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4361 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4363 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4365 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4367 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4369 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4371 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4373 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4375 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4377 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4379 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4381 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4383 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4385 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4387 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4389 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4391 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4393 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4394
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4396 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4398 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
8f06b2d8
PB		 4399
4400 /* The rest. */
4ab90a7a
AV		 4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
4402 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
823d2571
TG		 4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
4404 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
4405 {ARM_FEATURE_CORE_LOW (0),
4406 0x00000000, 0x00000000, 0}
8f06b2d8
PB		 4407};
4408
4409/* print_insn_thumb16 recognizes the following format control codes:
4410
4411 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4412 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4413 %<bitfield>I print bitfield as a signed decimal
4414 (top bit of range being the sign bit)
4415 %N print Thumb register mask (with LR)
4416 %O print Thumb register mask (with PC)
4417 %M print Thumb register mask
4418 %b print CZB's 6-bit unsigned branch destination
4419 %s print Thumb right-shift immediate (6..10; 0 == 32).
c22aaad1
PB		 4420 %c print the condition code
4421 %C print the condition code, or "s" if not conditional
4422 %x print warning if conditional an not at end of IT block"
4423 %X print "\t; unpredictable <IT:code>" if conditional
4424 %I print IT instruction suffix and operands
4547cb56 4425 %W print Thumb Writeback indicator for LDMIA
8f06b2d8
PB		 4426 %<bitfield>r print bitfield as an ARM register
4427 %<bitfield>d print bitfield as a decimal
4428 %<bitfield>H print (bitfield * 2) as a decimal
4429 %<bitfield>W print (bitfield * 4) as a decimal
4430 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4431 %<bitfield>B print Thumb branch destination (signed displacement)
4432 %<bitfield>c print bitfield as a condition code
4433 %<bitnum>'c print specified char iff bit is one
4434 %<bitnum>?ab print a if bit is one else print b. */
4435
4436static const struct opcode16 thumb_opcodes[] =
4437{
4438 /* Thumb instructions. */
4439
16a1fa25
TP		 4440 /* ARMv8-M Security Extensions instructions. */
4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
e207bc53 4442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"},
16a1fa25 4443
53c4b28b 4444 /* ARM V8 instructions. */
823d2571
TG		 4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
ddfded2f 4447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
53c4b28b 4448
8f06b2d8 4449 /* ARM V6K no-argument instructions. */
823d2571
TG		 4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
8f06b2d8
PB		 4456
4457 /* ARM V6T2 instructions. */
ff8646ee
TP		 4458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4459 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
4461 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
823d2571 4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
8f06b2d8
PB		 4463
4464 /* ARM V6. */
823d2571
TG		 4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
8f06b2d8
PB		 4476
4477 /* ARM V5 ISA extends Thumb. */
823d2571
TG		 4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4479 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
8f06b2d8 4480 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
823d2571
TG		 4481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
4482 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
8f06b2d8 4483 /* ARM V4T ISA (Thumb v1). */
823d2571
TG		 4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4485 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
8f06b2d8 4486 /* Format 4. */
823d2571
TG		 4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
8f06b2d8 4503 /* format 13 */
823d2571
TG		 4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
8f06b2d8 4506 /* format 5 */
823d2571
TG		 4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
8f06b2d8 4511 /* format 14 */
823d2571
TG		 4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
8f06b2d8 4514 /* format 2 */
823d2571
TG		 4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4516 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4518 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4520 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4522 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
8f06b2d8 4523 /* format 8 */
823d2571
TG		 4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4525 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4527 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4529 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4530 /* format 7 */
823d2571
TG		 4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4532 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4534 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
8f06b2d8 4535 /* format 1 */
823d2571
TG		 4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4538 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
8f06b2d8 4541 /* format 3 */
823d2571
TG		 4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
8f06b2d8 4546 /* format 6 */
823d2571
TG		 4547 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4549 0x4800, 0xF800,
4550 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
8f06b2d8 4551 /* format 9 */
823d2571
TG		 4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4553 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4555 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4557 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4559 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
8f06b2d8 4560 /* format 10 */
823d2571
TG		 4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4562 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4564 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
8f06b2d8 4565 /* format 11 */
823d2571
TG		 4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4567 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4569 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
8f06b2d8 4570 /* format 12 */
823d2571
TG		 4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4572 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
4574 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
8f06b2d8 4575 /* format 15 */
823d2571
TG		 4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
8f06b2d8 4578 /* format 17 */
823d2571 4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
8f06b2d8 4580 /* format 16 */
823d2571
TG		 4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
8f06b2d8 4584 /* format 18 */
823d2571 4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
8f06b2d8
PB		 4586
4587 /* The E800 .. FFFF range is unconditionally redirected to the
4588 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4589 are processed via that table. Thus, we can never encounter a
4590 bare "second half of BL/BLX(1)" instruction here. */
823d2571
TG		 4591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
4592 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8
PB		 4593};
4594
4595/* Thumb32 opcodes use the same table structure as the ARM opcodes.
4596 We adopt the convention that hw1 is the high 16 bits of .value and
4597 .mask, hw2 the low 16 bits.
4598
4599 print_insn_thumb32 recognizes the following format control codes:
4600
4601 %% %
4602
4603 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4604 %M print a modified 12-bit immediate (same location)
4605 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4606 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
90ec0d68 4607 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
8f06b2d8
PB		 4608 %S print a possibly-shifted Rm
4609
32a94698 4610 %L print address for a ldrd/strd instruction
8f06b2d8
PB		 4611 %a print the address of a plain load/store
4612 %w print the width and signedness of a core load/store
4613 %m print register mask for ldm/stm
4b5a202f 4614 %n print register mask for clrm
8f06b2d8
PB		 4615
4616 %E print the lsb and width fields of a bfc/bfi instruction
4617 %F print the lsb and width fields of a sbfx/ubfx instruction
e12437dc 4618 %G print a fallback offset for Branch Future instructions
e5d6e09e 4619 %W print an offset for BF instruction
1caf72a5 4620 %Y print an offset for BFL instruction
1889da70 4621 %Z print an offset for BFCSEL instruction
60f993ce
AV		 4622 %Q print an offset for Low Overhead Loop instructions
4623 %P print an offset for Low Overhead Loop end instructions
8f06b2d8
PB		 4624 %b print a conditional branch offset
4625 %B print an unconditional branch offset
4626 %s print the shift field of an SSAT instruction
4627 %R print the rotation field of an SXT instruction
62b3e311
PB		 4628 %U print barrier type.
4629 %P print address for pli instruction.
c22aaad1
PB		 4630 %c print the condition code
4631 %x print warning if conditional an not at end of IT block"
4632 %X print "\t; unpredictable <IT:code>" if conditional
8f06b2d8
PB		 4633
4634 %<bitfield>d print bitfield in decimal
f0fba320 4635 %<bitfield>D print bitfield plus one in decimal
8f06b2d8
PB		 4636 %<bitfield>W print bitfield*4 in decimal
4637 %<bitfield>r print bitfield as an ARM register
dd5181d5 4638 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
f1c7f421 4639 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
8f06b2d8
PB		 4640 %<bitfield>c print bitfield as a condition code
4641
16980d0b
JB		 4642 %<bitfield>'c print specified char iff bitfield is all ones
4643 %<bitfield>`c print specified char iff bitfield is all zeroes
4644 %<bitfield>?ab... select from array of values in big endian order
8f06b2d8
PB		 4645
4646 With one exception at the bottom (done because BL and BLX(1) need
4647 to come dead last), this table was machine-sorted first in
4648 decreasing order of number of bits set in the mask, then in
4649 increasing numeric order of mask, then in increasing numeric order
4650 of opcode. This order is not the clearest for a human reader, but
4651 is guaranteed never to catch a special-case bit pattern with a more
4652 general mask, which is important, because this instruction encoding
4653 makes heavy use of special-case bit patterns. */
4654static const struct opcode32 thumb32_opcodes[] =
4655{
4b5a202f
AV		 4656 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4657 instructions. */
60f993ce 4658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
d052b9b7 4659 0xf00fe001, 0xffffffff, "lctp%c"},
60f993ce
AV		 4660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4661 0xf02fc001, 0xfffff001, "le\t%P"},
4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4663 0xf00fc001, 0xfffff001, "le\tlr, %P"},
d052b9b7
AV		 4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4665 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4667 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4669 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4671 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4673 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
60f993ce 4674
4389b29a
AV		 4675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4676 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
f1c7f421
AV		 4677 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4678 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
65d1bc05
AV		 4679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4680 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
f1c7f421
AV		 4681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4682 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
f6b2b12d
AV		 4683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4684 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4389b29a 4685
4b5a202f
AV		 4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
4687 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4389b29a 4688
16a1fa25
TP		 4689 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
4ed7ed8d
TP		 4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4692 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4694 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
16a1fa25
TP		 4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4696 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
4698 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4ed7ed8d 4699
105bde57 4700 /* ARM V8.2 RAS extension instructions. */
4d1464f2 4701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
105bde57
MW		 4702 0xf3af8010, 0xffffffff, "esb"},
4703
53c4b28b 4704 /* V8 instructions. */
823d2571
TG		 4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4706 0xf3af8005, 0xffffffff, "sevl%c.w"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4708 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4710 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4712 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4714 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4716 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4718 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4720 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4722 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4724 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4726 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4728 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4730 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4732 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4734 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
4736 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
53c4b28b 4737
dd5181d5 4738 /* CRC32 instructions. */
8b301fbb 4739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4740 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4742 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
8b301fbb 4743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4744 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4746 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4748 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
8b301fbb 4749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
cc4a945a 4750 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
dd5181d5 4751
c597cc3d
SD		 4752 /* Speculation Barriers. */
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"},
4756
62b3e311 4757 /* V7 instructions. */
823d2571
TG		 4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4766 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
4768 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
62b3e311 4769
90ec0d68 4770 /* Virtualization Extension instructions. */
823d2571 4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
90ec0d68
MGD		 4772 /* We skip ERET as that is SUBS pc, lr, #0. */
4773
60e5ef9f 4774 /* MP Extension instructions. */
823d2571 4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
60e5ef9f 4776
f4c65163 4777 /* Security extension instructions. */
823d2571 4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
f4c65163 4779
7fadb25d
SD		 4780 /* ARMv8.5-A instructions. */
4781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
4782
8f06b2d8 4783 /* Instructions defined in the basic V6T2 set. */
823d2571
TG		 4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4790 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4792
ff8646ee 4793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4794 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4796 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4798 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4800 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4802 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4804 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4806 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4808 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4810 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4812 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4814 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4816 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4818 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4820 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
ff8646ee 4821 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571 4822 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
ff8646ee 4823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4824 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4826 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4828 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4830 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4832 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4834 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4836 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4838 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4840 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
ff8646ee 4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4842 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4844 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4846 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4848 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4850 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4852 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4854 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4856 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4858 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4860 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4862 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4864 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4866 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4868 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4870 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4872 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4874 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4876 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4878 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4880 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4882 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4884 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4886 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4888 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4890 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4892 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4894 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4896 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4898 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4900 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4902 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4904 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4906 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4908 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4910 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4912 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4914 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4916 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4918 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4920 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4922 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4924 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4926 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4928 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4930 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4932 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4934 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4936 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4938 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4940 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4942 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4944 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4946 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4948 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
ff8646ee 4949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 4950 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 4952 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
823d2571
TG		 4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4954 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4956 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4958 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4960 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4962 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4964 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4966 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4968 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4970 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4972 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4974 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4976 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4978 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4980 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4982 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4984 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4986 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4988 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4990 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4992 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4994 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4996 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
4998 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5000 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5002 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5004 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5006 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5008 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5010 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5012 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5014 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5016 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
ff8646ee 5017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5018 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5020 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5022 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5024 0xf810f000, 0xff70f000, "pld%c\t%a"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5026 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5028 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5030 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5032 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5034 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5036 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5038 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5040 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5042 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5044 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5046 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5048 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5050 0xfb100000, 0xfff000c0,
5051 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5053 0xfbc00080, 0xfff000c0,
5054 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5056 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5058 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
f0fba320 5060 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
823d2571
TG		 5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5062 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5064 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5065 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5066 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5068 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
ff8646ee 5069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5070 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5072 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5074 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5076 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5078 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5080 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5082 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5084 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5086 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5088 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5090 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
ff8646ee 5091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
823d2571
TG		 5092 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5094 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5096 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5098 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5100 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5102 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5104 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5106 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5108 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5110 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5112 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5114 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5116 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5118 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5120 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5122 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5124 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5126 0xe9400000, 0xff500000,
5127 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5129 0xe9500000, 0xff500000,
5130 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5132 0xe8600000, 0xff700000,
5133 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5135 0xe8700000, 0xff700000,
5136 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5138 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5140 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
c19d1205
ZW		 5141
5142 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
823d2571
TG		 5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5144 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5146 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5148 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
5150 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
c19d1205 5151
8f06b2d8 5152 /* These have been 32-bit since the invention of Thumb. */
823d2571
TG		 5153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5154 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
5156 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
8f06b2d8
PB		 5157
5158 /* Fallback. */
823d2571
TG		 5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
5160 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
5161 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
8f06b2d8 5162};
ff4a8d2b 5163
8f06b2d8
PB		 5164static const char *const arm_conditional[] =
5165{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
c22aaad1 5166 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
8f06b2d8
PB		 5167
5168static const char *const arm_fp_const[] =
5169{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5170
5171static const char *const arm_shift[] =
5172{"lsl", "lsr", "asr", "ror"};
5173
5174typedef struct
5175{
5176 const char *name;
5177 const char *description;
5178 const char *reg_names[16];
5179}
5180arm_regname;
5181
5182static const arm_regname regnames[] =
5183{
65b48a81 5184 { "reg-names-raw", N_("Select raw register names"),
8f06b2d8 5185 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
65b48a81 5186 { "reg-names-gcc", N_("Select register names used by GCC"),
8f06b2d8 5187 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5188 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
8f06b2d8 5189 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
65b48a81
PB		 5190 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
5191 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
5192 { "reg-names-apcs", N_("Select register names used in the APCS"),
8f06b2d8 5193 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
65b48a81 5194 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
8f06b2d8 5195 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
65b48a81 5196 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4934a27c
MM		 5197 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5198 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } }
8f06b2d8
PB		 5199};
5200
5201static const char *const iwmmxt_wwnames[] =
5202{"b", "h", "w", "d"};
5203
5204static const char *const iwmmxt_wwssnames[] =
2d447fca
JM		 5205{"b", "bus", "bc", "bss",
5206 "h", "hus", "hc", "hss",
5207 "w", "wus", "wc", "wss",
5208 "d", "dus", "dc", "dss"
8f06b2d8
PB		 5209};
5210
5211static const char *const iwmmxt_regnames[] =
5212{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5213 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5214};
5215
5216static const char *const iwmmxt_cregnames[] =
5217{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5218 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5219};
5220
143275ea
AV		 5221static const char *const vec_condnames[] =
5222{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5223};
5224
5225static const char *const mve_predicatenames[] =
5226{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5227 "eee", "ee", "eet", "e", "ett", "et", "ete"
5228};
5229
5230/* Names for 2-bit size field for mve vector isntructions. */
5231static const char *const mve_vec_sizename[] =
5232 { "8", "16", "32", "64"};
5233
5234/* Indicates whether we are processing a then predicate,
5235 else predicate or none at all. */
5236enum vpt_pred_state
5237{
5238 PRED_NONE,
5239 PRED_THEN,
5240 PRED_ELSE
5241};
5242
5243/* Information used to process a vpt block and subsequent instructions. */
5244struct vpt_block
5245{
5246 /* Are we in a vpt block. */
5247 bfd_boolean in_vpt_block;
5248
5249 /* Next predicate state if in vpt block. */
5250 enum vpt_pred_state next_pred_state;
5251
5252 /* Mask from vpt/vpst instruction. */
5253 long predicate_mask;
5254
5255 /* Instruction number in vpt block. */
5256 long current_insn_num;
5257
5258 /* Number of instructions in vpt block.. */
5259 long num_pred_insn;
5260};
5261
5262static struct vpt_block vpt_block_state =
5263{
5264 FALSE,
5265 PRED_NONE,
5266 0,
5267 0,
5268 0
5269};
5270
8f06b2d8
PB		 5271/* Default to GCC register name set. */
5272static unsigned int regname_selected = 1;
5273
65b48a81 5274#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
8f06b2d8
PB		 5275#define arm_regnames regnames[regname_selected].reg_names
5276
5277static bfd_boolean force_thumb = FALSE;
4934a27c 5278static uint16_t cde_coprocs = 0;
8f06b2d8 5279
c22aaad1
PB		 5280/* Current IT instruction state. This contains the same state as the IT
5281 bits in the CPSR. */
5282static unsigned int ifthen_state;
5283/* IT state for the next instruction. */
5284static unsigned int ifthen_next_state;
5285/* The address of the insn for which the IT state is valid. */
5286static bfd_vma ifthen_address;
5287#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
e2efe87d
MGD		 5288/* Indicates that the current Conditional state is unconditional or outside
5289 an IT block. */
5290#define COND_UNCOND 16
c22aaad1 5291
8f06b2d8
PB		 5292\f
5293/* Functions. */
143275ea
AV		 5294/* Extract the predicate mask for a VPT or VPST instruction.
5295 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5296
5297static long
5298mve_extract_pred_mask (long given)
5299{
5300 return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
5301}
5302
5303/* Return the number of instructions in a MVE predicate block. */
5304static long
5305num_instructions_vpt_block (long given)
5306{
5307 long mask = mve_extract_pred_mask (given);
5308 if (mask == 0)
5309 return 0;
5310
5311 if (mask == 8)
5312 return 1;
5313
5314 if ((mask & 7) == 4)
5315 return 2;
5316
5317 if ((mask & 3) == 2)
5318 return 3;
5319
5320 if ((mask & 1) == 1)
5321 return 4;
5322
5323 return 0;
5324}
5325
5326static void
5327mark_outside_vpt_block (void)
5328{
5329 vpt_block_state.in_vpt_block = FALSE;
5330 vpt_block_state.next_pred_state = PRED_NONE;
5331 vpt_block_state.predicate_mask = 0;
5332 vpt_block_state.current_insn_num = 0;
5333 vpt_block_state.num_pred_insn = 0;
5334}
5335
5336static void
5337mark_inside_vpt_block (long given)
5338{
5339 vpt_block_state.in_vpt_block = TRUE;
5340 vpt_block_state.next_pred_state = PRED_THEN;
5341 vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
5342 vpt_block_state.current_insn_num = 0;
5343 vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
5344 assert (vpt_block_state.num_pred_insn >= 1);
5345}
5346
5347static enum vpt_pred_state
5348invert_next_predicate_state (enum vpt_pred_state astate)
5349{
5350 if (astate == PRED_THEN)
5351 return PRED_ELSE;
5352 else if (astate == PRED_ELSE)
5353 return PRED_THEN;
5354 else
5355 return PRED_NONE;
5356}
5357
5358static enum vpt_pred_state
5359update_next_predicate_state (void)
5360{
5361 long pred_mask = vpt_block_state.predicate_mask;
5362 long mask_for_insn = 0;
5363
5364 switch (vpt_block_state.current_insn_num)
5365 {
5366 case 1:
5367 mask_for_insn = 8;
5368 break;
5369
5370 case 2:
5371 mask_for_insn = 4;
5372 break;
5373
5374 case 3:
5375 mask_for_insn = 2;
5376 break;
5377
5378 case 4:
5379 return PRED_NONE;
5380 }
5381
5382 if (pred_mask & mask_for_insn)
5383 return invert_next_predicate_state (vpt_block_state.next_pred_state);
5384 else
5385 return vpt_block_state.next_pred_state;
5386}
5387
5388static void
5389update_vpt_block_state (void)
5390{
5391 vpt_block_state.current_insn_num++;
5392 if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
5393 {
5394 /* No more instructions to process in vpt block. */
5395 mark_outside_vpt_block ();
5396 return;
5397 }
5398
5399 vpt_block_state.next_pred_state = update_next_predicate_state ();
5400}
8f06b2d8 5401
16980d0b
JB		 5402/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5403 Returns pointer to following character of the format string and
5404 fills in *VALUEP and *WIDTHP with the extracted value and number of
fe56b6ce 5405 bits extracted. WIDTHP can be NULL. */
16980d0b
JB		 5406
5407static const char *
fe56b6ce
NC		 5408arm_decode_bitfield (const char *ptr,
5409 unsigned long insn,
5410 unsigned long *valuep,
5411 int *widthp)
16980d0b
JB		 5412{
5413 unsigned long value = 0;
5414 int width = 0;
43e65147
L		 5415
5416 do
16980d0b
JB		 5417 {
5418 int start, end;
5419 int bits;
5420
5421 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
5422 start = start * 10 + *ptr - '0';
5423 if (*ptr == '-')
5424 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
5425 end = end * 10 + *ptr - '0';
5426 else
5427 end = start;
5428 bits = end - start;
5429 if (bits < 0)
5430 abort ();
5431 value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
5432 width += bits + 1;
5433 }
5434 while (*ptr++ == ',');
5435 *valuep = value;
5436 if (widthp)
5437 *widthp = width;
5438 return ptr - 1;
5439}
5440
8f06b2d8 5441static void
37b37b2d 5442arm_decode_shift (long given, fprintf_ftype func, void *stream,
78c66db8 5443 bfd_boolean print_shift)
8f06b2d8
PB		 5444{
5445 func (stream, "%s", arm_regnames[given & 0xf]);
5446
5447 if ((given & 0xff0) != 0)
5448 {
5449 if ((given & 0x10) == 0)
5450 {
5451 int amount = (given & 0xf80) >> 7;
5452 int shift = (given & 0x60) >> 5;
5453
5454 if (amount == 0)
5455 {
5456 if (shift == 3)
5457 {
5458 func (stream, ", rrx");
5459 return;
5460 }
5461
5462 amount = 32;
5463 }
5464
37b37b2d
RE		 5465 if (print_shift)
5466 func (stream, ", %s #%d", arm_shift[shift], amount);
5467 else
5468 func (stream, ", #%d", amount);
8f06b2d8 5469 }
74bdfecf 5470 else if ((given & 0x80) == 0x80)
aefd8a40 5471 func (stream, "\t; <illegal shifter operand>");
37b37b2d 5472 else if (print_shift)
8f06b2d8
PB		 5473 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
5474 arm_regnames[(given & 0xf00) >> 8]);
37b37b2d
RE		 5475 else
5476 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
8f06b2d8
PB		 5477 }
5478}
5479
73cd51e5
AV		 5480/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5481
5482static bfd_boolean
5483is_mve_okay_in_it (enum mve_instructions matched_insn)
5484{
c507f10b
AV		 5485 switch (matched_insn)
5486 {
5487 case MVE_VMOV_GP_TO_VEC_LANE:
5488 case MVE_VMOV2_VEC_LANE_TO_GP:
5489 case MVE_VMOV2_GP_TO_VEC_LANE:
5490 case MVE_VMOV_VEC_LANE_TO_GP:
23d00a41
SD		 5491 case MVE_LSLL:
5492 case MVE_LSLLI:
5493 case MVE_LSRL:
5494 case MVE_ASRL:
5495 case MVE_ASRLI:
5496 case MVE_SQRSHRL:
5497 case MVE_SQRSHR:
5498 case MVE_UQRSHL:
5499 case MVE_UQRSHLL:
5500 case MVE_UQSHL:
5501 case MVE_UQSHLL:
5502 case MVE_URSHRL:
5503 case MVE_URSHR:
5504 case MVE_SRSHRL:
5505 case MVE_SRSHR:
5506 case MVE_SQSHLL:
5507 case MVE_SQSHL:
c507f10b
AV		 5508 return TRUE;
5509 default:
5510 return FALSE;
5511 }
73cd51e5
AV		 5512}
5513
5514static bfd_boolean
5515is_mve_architecture (struct disassemble_info *info)
5516{
5517 struct arm_private_data *private_data = info->private_data;
5518 arm_feature_set allowed_arches = private_data->features;
5519
5520 arm_feature_set arm_ext_v8_1m_main
5521 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
5522
5523 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
5524 && !ARM_CPU_IS_ANY (allowed_arches))
5525 return TRUE;
5526 else
5527 return FALSE;
5528}
5529
143275ea
AV		 5530static bfd_boolean
5531is_vpt_instruction (long given)
5532{
5533
5534 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5535 if ((given & 0x0040e000) == 0)
5536 return FALSE;
5537
5538 /* VPT floating point T1 variant. */
5539 if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
5540 /* VPT floating point T2 variant. */
5541 || ((given & 0xefb10f50) == 0xee310f40)
5542 /* VPT vector T1 variant. */
5543 || ((given & 0xff811f51) == 0xfe010f00)
5544 /* VPT vector T2 variant. */
5545 || ((given & 0xff811f51) == 0xfe010f01
5546 && ((given & 0x300000) != 0x300000))
5547 /* VPT vector T3 variant. */
5548 || ((given & 0xff811f50) == 0xfe011f00)
5549 /* VPT vector T4 variant. */
5550 || ((given & 0xff811f70) == 0xfe010f40)
5551 /* VPT vector T5 variant. */
5552 || ((given & 0xff811f70) == 0xfe010f60)
5553 /* VPT vector T6 variant. */
5554 || ((given & 0xff811f50) == 0xfe011f40)
5555 /* VPST vector T variant. */
5556 || ((given & 0xffbf1fff) == 0xfe310f4d))
5557 return TRUE;
5558 else
5559 return FALSE;
5560}
5561
73cd51e5
AV		 5562/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5563 and ending bitfield = END. END must be greater than START. */
5564
5565static unsigned long
5566arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
5567{
5568 int bits = end - start;
5569
5570 if (bits < 0)
5571 abort ();
5572
5573 return ((given >> start) & ((2ul << bits) - 1));
5574}
5575
5576/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5577 START:END and START2:END2. END/END2 must be greater than
5578 START/START2. */
5579
5580static unsigned long
5581arm_decode_field_multiple (unsigned long given, unsigned int start,
5582 unsigned int end, unsigned int start2,
5583 unsigned int end2)
5584{
5585 int bits = end - start;
5586 int bits2 = end2 - start2;
5587 unsigned long value = 0;
5588 int width = 0;
5589
5590 if (bits2 < 0)
5591 abort ();
5592
5593 value = arm_decode_field (given, start, end);
5594 width += bits + 1;
5595
5596 value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
5597 return value;
5598}
5599
5600/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5601 This helps us decode instructions that change mnemonic depending on specific
5602 operand values/encodings. */
5603
5604static bfd_boolean
5605is_mve_encoding_conflict (unsigned long given,
5606 enum mve_instructions matched_insn)
5607{
143275ea
AV		 5608 switch (matched_insn)
5609 {
5610 case MVE_VPST:
5611 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5612 return TRUE;
5613 else
5614 return FALSE;
5615
5616 case MVE_VPT_FP_T1:
5617 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5618 return TRUE;
5619 if ((arm_decode_field (given, 12, 12) == 0)
5620 && (arm_decode_field (given, 0, 0) == 1))
5621 return TRUE;
5622 return FALSE;
5623
5624 case MVE_VPT_FP_T2:
5625 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5626 return TRUE;
5627 if (arm_decode_field (given, 0, 3) == 0xd)
5628 return TRUE;
5629 return FALSE;
5630
5631 case MVE_VPT_VEC_T1:
5632 case MVE_VPT_VEC_T2:
5633 case MVE_VPT_VEC_T3:
5634 case MVE_VPT_VEC_T4:
5635 case MVE_VPT_VEC_T5:
5636 case MVE_VPT_VEC_T6:
5637 if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
5638 return TRUE;
5639 if (arm_decode_field (given, 20, 21) == 3)
5640 return TRUE;
5641 return FALSE;
5642
5643 case MVE_VCMP_FP_T1:
5644 if ((arm_decode_field (given, 12, 12) == 0)
5645 && (arm_decode_field (given, 0, 0) == 1))
5646 return TRUE;
5647 else
5648 return FALSE;
5649
5650 case MVE_VCMP_FP_T2:
5651 if (arm_decode_field (given, 0, 3) == 0xd)
5652 return TRUE;
5653 else
5654 return FALSE;
5655
14b456f2
AV		 5656 case MVE_VQADD_T2:
5657 case MVE_VQSUB_T2:
f49bb598
AV		 5658 case MVE_VMUL_VEC_T2:
5659 case MVE_VMULH:
5660 case MVE_VRMULH:
56858bea
AV		 5661 case MVE_VMLA:
5662 case MVE_VMAX:
5663 case MVE_VMIN:
e523f101 5664 case MVE_VBRSR:
66dcaa5d
AV		 5665 case MVE_VADD_VEC_T2:
5666 case MVE_VSUB_VEC_T2:
5667 case MVE_VABAV:
ed63aa17
AV		 5668 case MVE_VQRSHL_T1:
5669 case MVE_VQSHL_T4:
5670 case MVE_VRSHL_T1:
5671 case MVE_VSHL_T3:
897b9bbc
AV		 5672 case MVE_VCADD_VEC:
5673 case MVE_VHCADD:
1c8f2df8
AV		 5674 case MVE_VDDUP:
5675 case MVE_VIDUP:
d3b63143
AV		 5676 case MVE_VQRDMLADH:
5677 case MVE_VQDMLAH:
5678 case MVE_VQRDMLAH:
5679 case MVE_VQDMLASH:
5680 case MVE_VQRDMLASH:
5681 case MVE_VQDMLSDH:
5682 case MVE_VQRDMLSDH:
5683 case MVE_VQDMULH_T3:
5684 case MVE_VQRDMULH_T4:
5685 case MVE_VQDMLADH:
5686 case MVE_VMLAS:
14925797 5687 case MVE_VMULL_INT:
9743db03
AV		 5688 case MVE_VHADD_T2:
5689 case MVE_VHSUB_T2:
143275ea
AV		 5690 case MVE_VCMP_VEC_T1:
5691 case MVE_VCMP_VEC_T2:
5692 case MVE_VCMP_VEC_T3:
5693 case MVE_VCMP_VEC_T4:
5694 case MVE_VCMP_VEC_T5:
5695 case MVE_VCMP_VEC_T6:
5696 if (arm_decode_field (given, 20, 21) == 3)
5697 return TRUE;
5698 else
5699 return FALSE;
5700
04d54ace
AV		 5701 case MVE_VLD2:
5702 case MVE_VLD4:
5703 case MVE_VST2:
5704 case MVE_VST4:
5705 if (arm_decode_field (given, 7, 8) == 3)
5706 return TRUE;
5707 else
5708 return FALSE;
5709
aef6d006
AV		 5710 case MVE_VSTRB_T1:
5711 case MVE_VSTRH_T2:
5712 if ((arm_decode_field (given, 24, 24) == 0)
5713 && (arm_decode_field (given, 21, 21) == 0))
5714 {
5715 return TRUE;
5716 }
5717 else if ((arm_decode_field (given, 7, 8) == 3))
5718 return TRUE;
5719 else
5720 return FALSE;
5721
5722 case MVE_VSTRB_T5:
5723 case MVE_VSTRH_T6:
5724 case MVE_VSTRW_T7:
5725 if ((arm_decode_field (given, 24, 24) == 0)
5726 && (arm_decode_field (given, 21, 21) == 0))
5727 {
5728 return TRUE;
5729 }
5730 else
5731 return FALSE;
5732
bf0b396d
AV		 5733 case MVE_VCVT_FP_FIX_VEC:
5734 return (arm_decode_field (given, 16, 21) & 0x38) == 0;
5735
c507f10b
AV		 5736 case MVE_VBIC_IMM:
5737 case MVE_VORR_IMM:
5738 {
5739 unsigned long cmode = arm_decode_field (given, 8, 11);
5740
5741 if ((cmode & 1) == 0)
5742 return TRUE;
5743 else if ((cmode & 0xc) == 0xc)
5744 return TRUE;
5745 else
5746 return FALSE;
5747 }
5748
5749 case MVE_VMVN_IMM:
5750 {
5751 unsigned long cmode = arm_decode_field (given, 8, 11);
5752
ce760a76 5753 if (cmode == 0xe)
c507f10b 5754 return TRUE;
ce760a76 5755 else if ((cmode & 0x9) == 1)
c507f10b 5756 return TRUE;
ce760a76 5757 else if ((cmode & 0xd) == 9)
c507f10b
AV		 5758 return TRUE;
5759 else
5760 return FALSE;
5761 }
5762
5763 case MVE_VMOV_IMM_TO_VEC:
5764 if ((arm_decode_field (given, 5, 5) == 1)
5765 && (arm_decode_field (given, 8, 11) != 0xe))
5766 return TRUE;
5767 else
5768 return FALSE;
5769
14925797
AV		 5770 case MVE_VMOVL:
5771 {
5772 unsigned long size = arm_decode_field (given, 19, 20);
5773 if ((size == 0) || (size == 3))
5774 return TRUE;
5775 else
5776 return FALSE;
5777 }
5778
56858bea
AV		 5779 case MVE_VMAXA:
5780 case MVE_VMINA:
5781 case MVE_VMAXV:
5782 case MVE_VMAXAV:
5783 case MVE_VMINV:
5784 case MVE_VMINAV:
ed63aa17
AV		 5785 case MVE_VQRSHL_T2:
5786 case MVE_VQSHL_T1:
5787 case MVE_VRSHL_T2:
5788 case MVE_VSHL_T2:
5789 case MVE_VSHLL_T2:
d3b63143 5790 case MVE_VADDV:
14925797
AV		 5791 case MVE_VMOVN:
5792 case MVE_VQMOVUN:
5793 case MVE_VQMOVN:
5794 if (arm_decode_field (given, 18, 19) == 3)
5795 return TRUE;
5796 else
5797 return FALSE;
5798
d3b63143
AV		 5799 case MVE_VMLSLDAV:
5800 case MVE_VRMLSLDAVH:
5801 case MVE_VMLALDAV:
5802 case MVE_VADDLV:
5803 if (arm_decode_field (given, 20, 22) == 7)
5804 return TRUE;
5805 else
5806 return FALSE;
5807
5808 case MVE_VRMLALDAVH:
5809 if ((arm_decode_field (given, 20, 22) & 6) == 6)
5810 return TRUE;
5811 else
5812 return FALSE;
5813
1c8f2df8
AV		 5814 case MVE_VDWDUP:
5815 case MVE_VIWDUP:
5816 if ((arm_decode_field (given, 20, 21) == 3)
5817 || (arm_decode_field (given, 1, 3) == 7))
5818 return TRUE;
5819 else
5820 return FALSE;
5821
ed63aa17
AV		 5822
5823 case MVE_VSHLL_T1:
5824 if (arm_decode_field (given, 16, 18) == 0)
5825 {
5826 unsigned long sz = arm_decode_field (given, 19, 20);
5827
5828 if ((sz == 1) || (sz == 2))
5829 return TRUE;
5830 else
5831 return FALSE;
5832 }
5833 else
5834 return FALSE;
5835
5836 case MVE_VQSHL_T2:
5837 case MVE_VQSHLU_T3:
5838 case MVE_VRSHR:
5839 case MVE_VSHL_T1:
5840 case MVE_VSHR:
5841 case MVE_VSLI:
5842 case MVE_VSRI:
5843 if (arm_decode_field (given, 19, 21) == 0)
5844 return TRUE;
5845 else
5846 return FALSE;
5847
e523f101
AV		 5848 case MVE_VCTP:
5849 if (arm_decode_field (given, 16, 19) == 0xf)
5850 return TRUE;
5851 else
5852 return FALSE;
5853
23d00a41
SD		 5854 case MVE_ASRLI:
5855 case MVE_ASRL:
5856 case MVE_LSLLI:
5857 case MVE_LSLL:
5858 case MVE_LSRL:
5859 case MVE_SQRSHRL:
5860 case MVE_SQSHLL:
5861 case MVE_SRSHRL:
5862 case MVE_UQRSHLL:
5863 case MVE_UQSHLL:
5864 case MVE_URSHRL:
5865 if (arm_decode_field (given, 9, 11) == 0x7)
5866 return TRUE;
5867 else
5868 return FALSE;
5869
e39c1607
SD		 5870 case MVE_CSINC:
5871 case MVE_CSINV:
5872 {
5873 unsigned long rm, rn;
5874 rm = arm_decode_field (given, 0, 3);
5875 rn = arm_decode_field (given, 16, 19);
5876 /* CSET/CSETM. */
5877 if (rm == 0xf && rn == 0xf)
5878 return TRUE;
5879 /* CINC/CINV. */
5880 else if (rn == rm && rn != 0xf)
5881 return TRUE;
5882 }
5883 /* Fall through. */
5884 case MVE_CSEL:
5885 case MVE_CSNEG:
5886 if (arm_decode_field (given, 0, 3) == 0xd)
5887 return TRUE;
5888 /* CNEG. */
5889 else if (matched_insn == MVE_CSNEG)
5890 if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
5891 return TRUE;
5892 return FALSE;
5893
143275ea 5894 default:
66dcaa5d
AV		 5895 case MVE_VADD_FP_T1:
5896 case MVE_VADD_FP_T2:
5897 case MVE_VADD_VEC_T1:
143275ea
AV		 5898 return FALSE;
5899
5900 }
73cd51e5
AV		 5901}
5902
aef6d006
AV		 5903static void
5904print_mve_vld_str_addr (struct disassemble_info *info,
5905 unsigned long given,
5906 enum mve_instructions matched_insn)
5907{
5908 void *stream = info->stream;
5909 fprintf_ftype func = info->fprintf_func;
5910
5911 unsigned long p, w, gpr, imm, add, mod_imm;
5912
5913 imm = arm_decode_field (given, 0, 6);
5914 mod_imm = imm;
5915
5916 switch (matched_insn)
5917 {
5918 case MVE_VLDRB_T1:
5919 case MVE_VSTRB_T1:
5920 gpr = arm_decode_field (given, 16, 18);
5921 break;
5922
5923 case MVE_VLDRH_T2:
5924 case MVE_VSTRH_T2:
5925 gpr = arm_decode_field (given, 16, 18);
5926 mod_imm = imm << 1;
5927 break;
5928
5929 case MVE_VLDRH_T6:
5930 case MVE_VSTRH_T6:
5931 gpr = arm_decode_field (given, 16, 19);
5932 mod_imm = imm << 1;
5933 break;
5934
5935 case MVE_VLDRW_T7:
5936 case MVE_VSTRW_T7:
5937 gpr = arm_decode_field (given, 16, 19);
5938 mod_imm = imm << 2;
5939 break;
5940
5941 case MVE_VLDRB_T5:
5942 case MVE_VSTRB_T5:
5943 gpr = arm_decode_field (given, 16, 19);
5944 break;
5945
5946 default:
5947 return;
5948 }
5949
5950 p = arm_decode_field (given, 24, 24);
5951 w = arm_decode_field (given, 21, 21);
5952
5953 add = arm_decode_field (given, 23, 23);
5954
5955 char * add_sub;
5956
5957 /* Don't print anything for '+' as it is implied. */
5958 if (add == 1)
5959 add_sub = "";
5960 else
5961 add_sub = "-";
5962
5963 if (p == 1)
5964 {
5965 /* Offset mode. */
5966 if (w == 0)
5967 func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
5968 /* Pre-indexed mode. */
5969 else
5970 func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
5971 }
5972 else if ((p == 0) && (w == 1))
5973 /* Post-index mode. */
5974 func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
5975}
5976
73cd51e5
AV		 5977/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5978 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5979 this encoding is undefined. */
5980
5981static bfd_boolean
5982is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
5983 enum mve_undefined *undefined_code)
5984{
5985 *undefined_code = UNDEF_NONE;
5986
9743db03
AV		 5987 switch (matched_insn)
5988 {
5989 case MVE_VDUP:
5990 if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
5991 {
5992 *undefined_code = UNDEF_SIZE_3;
5993 return TRUE;
5994 }
5995 else
5996 return FALSE;
5997
14b456f2
AV		 5998 case MVE_VQADD_T1:
5999 case MVE_VQSUB_T1:
f49bb598 6000 case MVE_VMUL_VEC_T1:
66dcaa5d
AV		 6001 case MVE_VABD_VEC:
6002 case MVE_VADD_VEC_T1:
6003 case MVE_VSUB_VEC_T1:
d3b63143
AV		 6004 case MVE_VQDMULH_T1:
6005 case MVE_VQRDMULH_T2:
9743db03
AV		 6006 case MVE_VRHADD:
6007 case MVE_VHADD_T1:
6008 case MVE_VHSUB_T1:
6009 if (arm_decode_field (given, 20, 21) == 3)
6010 {
6011 *undefined_code = UNDEF_SIZE_3;
6012 return TRUE;
6013 }
6014 else
6015 return FALSE;
6016
aef6d006
AV		 6017 case MVE_VLDRB_T1:
6018 if (arm_decode_field (given, 7, 8) == 3)
6019 {
6020 *undefined_code = UNDEF_SIZE_3;
6021 return TRUE;
6022 }
6023 else
6024 return FALSE;
6025
6026 case MVE_VLDRH_T2:
6027 if (arm_decode_field (given, 7, 8) <= 1)
6028 {
6029 *undefined_code = UNDEF_SIZE_LE_1;
6030 return TRUE;
6031 }
6032 else
6033 return FALSE;
6034
6035 case MVE_VSTRB_T1:
6036 if ((arm_decode_field (given, 7, 8) == 0))
6037 {
6038 *undefined_code = UNDEF_SIZE_0;
6039 return TRUE;
6040 }
6041 else
6042 return FALSE;
6043
6044 case MVE_VSTRH_T2:
6045 if ((arm_decode_field (given, 7, 8) <= 1))
6046 {
6047 *undefined_code = UNDEF_SIZE_LE_1;
6048 return TRUE;
6049 }
6050 else
6051 return FALSE;
6052
ef1576a1
AV		 6053 case MVE_VLDRB_GATHER_T1:
6054 if (arm_decode_field (given, 7, 8) == 3)
6055 {
6056 *undefined_code = UNDEF_SIZE_3;
6057 return TRUE;
6058 }
6059 else if ((arm_decode_field (given, 28, 28) == 0)
6060 && (arm_decode_field (given, 7, 8) == 0))
6061 {
6062 *undefined_code = UNDEF_NOT_UNS_SIZE_0;
6063 return TRUE;
6064 }
6065 else
6066 return FALSE;
6067
6068 case MVE_VLDRH_GATHER_T2:
6069 if (arm_decode_field (given, 7, 8) == 3)
6070 {
6071 *undefined_code = UNDEF_SIZE_3;
6072 return TRUE;
6073 }
6074 else if ((arm_decode_field (given, 28, 28) == 0)
6075 && (arm_decode_field (given, 7, 8) == 1))
6076 {
6077 *undefined_code = UNDEF_NOT_UNS_SIZE_1;
6078 return TRUE;
6079 }
6080 else if (arm_decode_field (given, 7, 8) == 0)
6081 {
6082 *undefined_code = UNDEF_SIZE_0;
6083 return TRUE;
6084 }
6085 else
6086 return FALSE;
6087
6088 case MVE_VLDRW_GATHER_T3:
6089 if (arm_decode_field (given, 7, 8) != 2)
6090 {
6091 *undefined_code = UNDEF_SIZE_NOT_2;
6092 return TRUE;
6093 }
6094 else if (arm_decode_field (given, 28, 28) == 0)
6095 {
6096 *undefined_code = UNDEF_NOT_UNSIGNED;
6097 return TRUE;
6098 }
6099 else
6100 return FALSE;
6101
6102 case MVE_VLDRD_GATHER_T4:
6103 if (arm_decode_field (given, 7, 8) != 3)
6104 {
6105 *undefined_code = UNDEF_SIZE_NOT_3;
6106 return TRUE;
6107 }
6108 else if (arm_decode_field (given, 28, 28) == 0)
6109 {
6110 *undefined_code = UNDEF_NOT_UNSIGNED;
6111 return TRUE;
6112 }
6113 else
6114 return FALSE;
6115
6116 case MVE_VSTRB_SCATTER_T1:
6117 if (arm_decode_field (given, 7, 8) == 3)
6118 {
6119 *undefined_code = UNDEF_SIZE_3;
6120 return TRUE;
6121 }
6122 else
6123 return FALSE;
6124
6125 case MVE_VSTRH_SCATTER_T2:
6126 {
6127 unsigned long size = arm_decode_field (given, 7, 8);
6128 if (size == 3)
6129 {
6130 *undefined_code = UNDEF_SIZE_3;
6131 return TRUE;
6132 }
6133 else if (size == 0)
6134 {
6135 *undefined_code = UNDEF_SIZE_0;
6136 return TRUE;
6137 }
6138 else
6139 return FALSE;
6140 }
6141
6142 case MVE_VSTRW_SCATTER_T3:
6143 if (arm_decode_field (given, 7, 8) != 2)
6144 {
6145 *undefined_code = UNDEF_SIZE_NOT_2;
6146 return TRUE;
6147 }
6148 else
6149 return FALSE;
6150
6151 case MVE_VSTRD_SCATTER_T4:
6152 if (arm_decode_field (given, 7, 8) != 3)
6153 {
6154 *undefined_code = UNDEF_SIZE_NOT_3;
6155 return TRUE;
6156 }
6157 else
6158 return FALSE;
6159
bf0b396d
AV		 6160 case MVE_VCVT_FP_FIX_VEC:
6161 {
6162 unsigned long imm6 = arm_decode_field (given, 16, 21);
6163 if ((imm6 & 0x20) == 0)
6164 {
6165 *undefined_code = UNDEF_VCVT_IMM6;
6166 return TRUE;
6167 }
6168
6169 if ((arm_decode_field (given, 9, 9) == 0)
6170 && ((imm6 & 0x30) == 0x20))
6171 {
6172 *undefined_code = UNDEF_VCVT_FSI_IMM6;
6173 return TRUE;
6174 }
6175
6176 return FALSE;
6177 }
6178
f49bb598 6179 case MVE_VNEG_FP:
66dcaa5d 6180 case MVE_VABS_FP:
bf0b396d
AV		 6181 case MVE_VCVT_BETWEEN_FP_INT:
6182 case MVE_VCVT_FROM_FP_TO_INT:
6183 {
6184 unsigned long size = arm_decode_field (given, 18, 19);
6185 if (size == 0)
6186 {
6187 *undefined_code = UNDEF_SIZE_0;
6188 return TRUE;
6189 }
6190 else if (size == 3)
6191 {
6192 *undefined_code = UNDEF_SIZE_3;
6193 return TRUE;
6194 }
6195 else
6196 return FALSE;
6197 }
6198
c507f10b
AV		 6199 case MVE_VMOV_VEC_LANE_TO_GP:
6200 {
6201 unsigned long op1 = arm_decode_field (given, 21, 22);
6202 unsigned long op2 = arm_decode_field (given, 5, 6);
6203 unsigned long u = arm_decode_field (given, 23, 23);
6204
6205 if ((op2 == 0) && (u == 1))
6206 {
6207 if ((op1 == 0) || (op1 == 1))
6208 {
6209 *undefined_code = UNDEF_BAD_U_OP1_OP2;
6210 return TRUE;
6211 }
6212 else
6213 return FALSE;
6214 }
6215 else if (op2 == 2)
6216 {
6217 if ((op1 == 0) || (op1 == 1))
6218 {
6219 *undefined_code = UNDEF_BAD_OP1_OP2;
6220 return TRUE;
6221 }
6222 else
6223 return FALSE;
6224 }
6225
6226 return FALSE;
6227 }
6228
6229 case MVE_VMOV_GP_TO_VEC_LANE:
6230 if (arm_decode_field (given, 5, 6) == 2)
6231 {
6232 unsigned long op1 = arm_decode_field (given, 21, 22);
6233 if ((op1 == 0) || (op1 == 1))
6234 {
6235 *undefined_code = UNDEF_BAD_OP1_OP2;
6236 return TRUE;
6237 }
6238 else
6239 return FALSE;
6240 }
6241 else
6242 return FALSE;
6243
c4a23bf8
SP		 6244 case MVE_VMOV_VEC_TO_VEC:
6245 if ((arm_decode_field (given, 5, 5) == 1)
6246 || (arm_decode_field (given, 22, 22) == 1))
6247 return TRUE;
6248 return FALSE;
6249
c507f10b
AV		 6250 case MVE_VMOV_IMM_TO_VEC:
6251 if (arm_decode_field (given, 5, 5) == 0)
6252 {
6253 unsigned long cmode = arm_decode_field (given, 8, 11);
6254
6255 if (((cmode & 9) == 1) || ((cmode & 5) == 1))
6256 {
6257 *undefined_code = UNDEF_OP_0_BAD_CMODE;
6258 return TRUE;
6259 }
6260 else
6261 return FALSE;
6262 }
6263 else
6264 return FALSE;
6265
ed63aa17 6266 case MVE_VSHLL_T2:
14925797
AV		 6267 case MVE_VMOVN:
6268 if (arm_decode_field (given, 18, 19) == 2)
6269 {
6270 *undefined_code = UNDEF_SIZE_2;
6271 return TRUE;
6272 }
6273 else
6274 return FALSE;
6275
d3b63143
AV		 6276 case MVE_VRMLALDAVH:
6277 case MVE_VMLADAV_T1:
6278 case MVE_VMLADAV_T2:
6279 case MVE_VMLALDAV:
6280 if ((arm_decode_field (given, 28, 28) == 1)
6281 && (arm_decode_field (given, 12, 12) == 1))
6282 {
6283 *undefined_code = UNDEF_XCHG_UNS;
6284 return TRUE;
6285 }
6286 else
6287 return FALSE;
6288
ed63aa17
AV		 6289 case MVE_VQSHRN:
6290 case MVE_VQSHRUN:
6291 case MVE_VSHLL_T1:
6292 case MVE_VSHRN:
6293 {
6294 unsigned long sz = arm_decode_field (given, 19, 20);
6295 if (sz == 1)
6296 return FALSE;
6297 else if ((sz & 2) == 2)
6298 return FALSE;
6299 else
6300 {
6301 *undefined_code = UNDEF_SIZE;
6302 return TRUE;
6303 }
6304 }
6305 break;
6306
6307 case MVE_VQSHL_T2:
6308 case MVE_VQSHLU_T3:
6309 case MVE_VRSHR:
6310 case MVE_VSHL_T1:
6311 case MVE_VSHR:
6312 case MVE_VSLI:
6313 case MVE_VSRI:
6314 {
6315 unsigned long sz = arm_decode_field (given, 19, 21);
6316 if ((sz & 7) == 1)
6317 return FALSE;
6318 else if ((sz & 6) == 2)
6319 return FALSE;
6320 else if ((sz & 4) == 4)
6321 return FALSE;
6322 else
6323 {
6324 *undefined_code = UNDEF_SIZE;
6325 return TRUE;
6326 }
6327 }
6328
6329 case MVE_VQRSHRN:
6330 case MVE_VQRSHRUN:
6331 if (arm_decode_field (given, 19, 20) == 0)
6332 {
6333 *undefined_code = UNDEF_SIZE_0;
6334 return TRUE;
6335 }
6336 else
6337 return FALSE;
6338
66dcaa5d
AV		 6339 case MVE_VABS_VEC:
6340 if (arm_decode_field (given, 18, 19) == 3)
6341 {
6342 *undefined_code = UNDEF_SIZE_3;
6343 return TRUE;
6344 }
6345 else
6346 return FALSE;
6347
14b456f2
AV		 6348 case MVE_VQNEG:
6349 case MVE_VQABS:
f49bb598 6350 case MVE_VNEG_VEC:
e523f101
AV		 6351 case MVE_VCLS:
6352 case MVE_VCLZ:
6353 if (arm_decode_field (given, 18, 19) == 3)
6354 {
6355 *undefined_code = UNDEF_SIZE_3;
6356 return TRUE;
6357 }
6358 else
6359 return FALSE;
6360
14b456f2
AV		 6361 case MVE_VREV16:
6362 if (arm_decode_field (given, 18, 19) == 0)
6363 return FALSE;
6364 else
6365 {
6366 *undefined_code = UNDEF_SIZE_NOT_0;
6367 return TRUE;
6368 }
6369
6370 case MVE_VREV32:
6371 {
6372 unsigned long size = arm_decode_field (given, 18, 19);
6373 if ((size & 2) == 2)
6374 {
6375 *undefined_code = UNDEF_SIZE_2;
6376 return TRUE;
6377 }
6378 else
6379 return FALSE;
6380 }
6381
6382 case MVE_VREV64:
6383 if (arm_decode_field (given, 18, 19) != 3)
6384 return FALSE;
6385 else
6386 {
6387 *undefined_code = UNDEF_SIZE_3;
6388 return TRUE;
6389 }
6390
9743db03
AV		 6391 default:
6392 return FALSE;
6393 }
73cd51e5
AV		 6394}
6395
6396/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6397 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6398 why this encoding is unpredictable. */
6399
6400static bfd_boolean
6401is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
6402 enum mve_unpredictable *unpredictable_code)
6403{
6404 *unpredictable_code = UNPRED_NONE;
6405
143275ea
AV		 6406 switch (matched_insn)
6407 {
6408 case MVE_VCMP_FP_T2:
6409 case MVE_VPT_FP_T2:
6410 if ((arm_decode_field (given, 12, 12) == 0)
6411 && (arm_decode_field (given, 5, 5) == 1))
6412 {
6413 *unpredictable_code = UNPRED_FCA_0_FCB_1;
6414 return TRUE;
6415 }
6416 else
6417 return FALSE;
73cd51e5 6418
143275ea
AV		 6419 case MVE_VPT_VEC_T4:
6420 case MVE_VPT_VEC_T5:
6421 case MVE_VPT_VEC_T6:
6422 case MVE_VCMP_VEC_T4:
6423 case MVE_VCMP_VEC_T5:
6424 case MVE_VCMP_VEC_T6:
6425 if (arm_decode_field (given, 0, 3) == 0xd)
6426 {
6427 *unpredictable_code = UNPRED_R13;
6428 return TRUE;
6429 }
6430 else
6431 return FALSE;
c1e26897 6432
9743db03
AV		 6433 case MVE_VDUP:
6434 {
6435 unsigned long gpr = arm_decode_field (given, 12, 15);
6436 if (gpr == 0xd)
6437 {
6438 *unpredictable_code = UNPRED_R13;
6439 return TRUE;
6440 }
6441 else if (gpr == 0xf)
6442 {
6443 *unpredictable_code = UNPRED_R15;
6444 return TRUE;
6445 }
6446
6447 return FALSE;
6448 }
6449
14b456f2
AV		 6450 case MVE_VQADD_T2:
6451 case MVE_VQSUB_T2:
f49bb598
AV		 6452 case MVE_VMUL_FP_T2:
6453 case MVE_VMUL_VEC_T2:
56858bea 6454 case MVE_VMLA:
e523f101 6455 case MVE_VBRSR:
66dcaa5d
AV		 6456 case MVE_VADD_FP_T2:
6457 case MVE_VSUB_FP_T2:
6458 case MVE_VADD_VEC_T2:
6459 case MVE_VSUB_VEC_T2:
ed63aa17
AV		 6460 case MVE_VQRSHL_T2:
6461 case MVE_VQSHL_T1:
6462 case MVE_VRSHL_T2:
6463 case MVE_VSHL_T2:
6464 case MVE_VSHLC:
d3b63143
AV		 6465 case MVE_VQDMLAH:
6466 case MVE_VQRDMLAH:
6467 case MVE_VQDMLASH:
6468 case MVE_VQRDMLASH:
6469 case MVE_VQDMULH_T3:
6470 case MVE_VQRDMULH_T4:
6471 case MVE_VMLAS:
9743db03
AV		 6472 case MVE_VFMA_FP_SCALAR:
6473 case MVE_VFMAS_FP_SCALAR:
6474 case MVE_VHADD_T2:
6475 case MVE_VHSUB_T2:
6476 {
6477 unsigned long gpr = arm_decode_field (given, 0, 3);
6478 if (gpr == 0xd)
6479 {
6480 *unpredictable_code = UNPRED_R13;
6481 return TRUE;
6482 }
6483 else if (gpr == 0xf)
6484 {
6485 *unpredictable_code = UNPRED_R15;
6486 return TRUE;
6487 }
6488
6489 return FALSE;
6490 }
6491
04d54ace
AV		 6492 case MVE_VLD2:
6493 case MVE_VST2:
6494 {
6495 unsigned long rn = arm_decode_field (given, 16, 19);
6496
6497 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6498 {
6499 *unpredictable_code = UNPRED_R13_AND_WB;
6500 return TRUE;
6501 }
6502
6503 if (rn == 0xf)
6504 {
6505 *unpredictable_code = UNPRED_R15;
6506 return TRUE;
6507 }
6508
6509 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
6510 {
6511 *unpredictable_code = UNPRED_Q_GT_6;
6512 return TRUE;
6513 }
6514 else
6515 return FALSE;
6516 }
6517
6518 case MVE_VLD4:
6519 case MVE_VST4:
6520 {
6521 unsigned long rn = arm_decode_field (given, 16, 19);
6522
6523 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6524 {
6525 *unpredictable_code = UNPRED_R13_AND_WB;
6526 return TRUE;
6527 }
6528
6529 if (rn == 0xf)
6530 {
6531 *unpredictable_code = UNPRED_R15;
6532 return TRUE;
6533 }
6534
6535 if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
6536 {
6537 *unpredictable_code = UNPRED_Q_GT_4;
6538 return TRUE;
6539 }
6540 else
6541 return FALSE;
6542 }
6543
aef6d006
AV		 6544 case MVE_VLDRB_T5:
6545 case MVE_VLDRH_T6:
6546 case MVE_VLDRW_T7:
6547 case MVE_VSTRB_T5:
6548 case MVE_VSTRH_T6:
6549 case MVE_VSTRW_T7:
6550 {
6551 unsigned long rn = arm_decode_field (given, 16, 19);
6552
6553 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6554 {
6555 *unpredictable_code = UNPRED_R13_AND_WB;
6556 return TRUE;
6557 }
6558 else if (rn == 0xf)
6559 {
6560 *unpredictable_code = UNPRED_R15;
6561 return TRUE;
6562 }
6563 else
6564 return FALSE;
6565 }
6566
ef1576a1
AV		 6567 case MVE_VLDRB_GATHER_T1:
6568 if (arm_decode_field (given, 0, 0) == 1)
6569 {
6570 *unpredictable_code = UNPRED_OS;
6571 return TRUE;
6572 }
6573
6574 /* fall through. */
6575 /* To handle common code with T2-T4 variants. */
6576 case MVE_VLDRH_GATHER_T2:
6577 case MVE_VLDRW_GATHER_T3:
6578 case MVE_VLDRD_GATHER_T4:
6579 {
6580 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6581 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6582
6583 if (qd == qm)
6584 {
6585 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6586 return TRUE;
6587 }
6588
6589 if (arm_decode_field (given, 16, 19) == 0xf)
6590 {
6591 *unpredictable_code = UNPRED_R15;
6592 return TRUE;
6593 }
6594
6595 return FALSE;
6596 }
6597
6598 case MVE_VLDRW_GATHER_T5:
6599 case MVE_VLDRD_GATHER_T6:
6600 {
6601 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6602 unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7);
6603
6604 if (qd == qm)
6605 {
6606 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6607 return TRUE;
6608 }
6609 else
6610 return FALSE;
6611 }
6612
6613 case MVE_VSTRB_SCATTER_T1:
6614 if (arm_decode_field (given, 16, 19) == 0xf)
6615 {
6616 *unpredictable_code = UNPRED_R15;
6617 return TRUE;
6618 }
6619 else if (arm_decode_field (given, 0, 0) == 1)
6620 {
6621 *unpredictable_code = UNPRED_OS;
6622 return TRUE;
6623 }
6624 else
6625 return FALSE;
6626
6627 case MVE_VSTRH_SCATTER_T2:
6628 case MVE_VSTRW_SCATTER_T3:
6629 case MVE_VSTRD_SCATTER_T4:
6630 if (arm_decode_field (given, 16, 19) == 0xf)
6631 {
6632 *unpredictable_code = UNPRED_R15;
6633 return TRUE;
6634 }
6635 else
6636 return FALSE;
6637
c507f10b
AV		 6638 case MVE_VMOV2_VEC_LANE_TO_GP:
6639 case MVE_VMOV2_GP_TO_VEC_LANE:
bf0b396d
AV		 6640 case MVE_VCVT_BETWEEN_FP_INT:
6641 case MVE_VCVT_FROM_FP_TO_INT:
6642 {
6643 unsigned long rt = arm_decode_field (given, 0, 3);
6644 unsigned long rt2 = arm_decode_field (given, 16, 19);
6645
6646 if ((rt == 0xd) || (rt2 == 0xd))
6647 {
6648 *unpredictable_code = UNPRED_R13;
6649 return TRUE;
6650 }
6651 else if ((rt == 0xf) || (rt2 == 0xf))
6652 {
6653 *unpredictable_code = UNPRED_R15;
6654 return TRUE;
6655 }
6656 else if (rt == rt2)
6657 {
6658 *unpredictable_code = UNPRED_GP_REGS_EQUAL;
6659 return TRUE;
6660 }
6661
6662 return FALSE;
6663 }
6664
56858bea
AV		 6665 case MVE_VMAXV:
6666 case MVE_VMAXAV:
6667 case MVE_VMAXNMV_FP:
6668 case MVE_VMAXNMAV_FP:
6669 case MVE_VMINNMV_FP:
6670 case MVE_VMINNMAV_FP:
6671 case MVE_VMINV:
6672 case MVE_VMINAV:
66dcaa5d 6673 case MVE_VABAV:
c507f10b
AV		 6674 case MVE_VMOV_HFP_TO_GP:
6675 case MVE_VMOV_GP_TO_VEC_LANE:
6676 case MVE_VMOV_VEC_LANE_TO_GP:
6677 {
6678 unsigned long rda = arm_decode_field (given, 12, 15);
6679 if (rda == 0xd)
6680 {
6681 *unpredictable_code = UNPRED_R13;
6682 return TRUE;
6683 }
6684 else if (rda == 0xf)
6685 {
6686 *unpredictable_code = UNPRED_R15;
6687 return TRUE;
6688 }
6689
6690 return FALSE;
6691 }
6692
14925797
AV		 6693 case MVE_VMULL_INT:
6694 {
6695 unsigned long Qd;
6696 unsigned long Qm;
6697 unsigned long Qn;
6698
6699 if (arm_decode_field (given, 20, 21) == 2)
6700 {
6701 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6702 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6703 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6704
6705 if ((Qd == Qn) || (Qd == Qm))
6706 {
6707 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6708 return TRUE;
6709 }
6710 else
6711 return FALSE;
6712 }
6713 else
6714 return FALSE;
6715 }
6716
897b9bbc 6717 case MVE_VCMUL_FP:
14925797
AV		 6718 case MVE_VQDMULL_T1:
6719 {
6720 unsigned long Qd;
6721 unsigned long Qm;
6722 unsigned long Qn;
6723
6724 if (arm_decode_field (given, 28, 28) == 1)
6725 {
6726 Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6727 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6728 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6729
6730 if ((Qd == Qn) || (Qd == Qm))
6731 {
6732 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6733 return TRUE;
6734 }
6735 else
6736 return FALSE;
6737 }
6738 else
6739 return FALSE;
6740 }
6741
6742 case MVE_VQDMULL_T2:
6743 {
6744 unsigned long gpr = arm_decode_field (given, 0, 3);
6745 if (gpr == 0xd)
6746 {
6747 *unpredictable_code = UNPRED_R13;
6748 return TRUE;
6749 }
6750 else if (gpr == 0xf)
6751 {
6752 *unpredictable_code = UNPRED_R15;
6753 return TRUE;
6754 }
6755
6756 if (arm_decode_field (given, 28, 28) == 1)
6757 {
6758 unsigned long Qd
6759 = arm_decode_field_multiple (given, 13, 15, 22, 22);
6760 unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6761
a9d96ab9 6762 if (Qd == Qn)
14925797
AV		 6763 {
6764 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6765 return TRUE;
6766 }
6767 else
6768 return FALSE;
6769 }
6770
6771 return FALSE;
6772 }
6773
d3b63143
AV		 6774 case MVE_VMLSLDAV:
6775 case MVE_VRMLSLDAVH:
6776 case MVE_VMLALDAV:
6777 case MVE_VADDLV:
6778 if (arm_decode_field (given, 20, 22) == 6)
6779 {
6780 *unpredictable_code = UNPRED_R13;
6781 return TRUE;
6782 }
6783 else
6784 return FALSE;
6785
1c8f2df8
AV		 6786 case MVE_VDWDUP:
6787 case MVE_VIWDUP:
6788 if (arm_decode_field (given, 1, 3) == 6)
6789 {
6790 *unpredictable_code = UNPRED_R13;
6791 return TRUE;
6792 }
6793 else
6794 return FALSE;
6795
897b9bbc
AV		 6796 case MVE_VCADD_VEC:
6797 case MVE_VHCADD:
6798 {
6799 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6800 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6801 if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2)
6802 {
6803 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2;
6804 return TRUE;
6805 }
6806 else
6807 return FALSE;
6808 }
6809
6810 case MVE_VCADD_FP:
6811 {
6812 unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6813 unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6814 if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1)
6815 {
6816 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6817 return TRUE;
6818 }
6819 else
6820 return FALSE;
6821 }
6822
6823 case MVE_VCMLA_FP:
6824 {
6825 unsigned long Qda;
6826 unsigned long Qm;
6827 unsigned long Qn;
6828
6829 if (arm_decode_field (given, 20, 20) == 1)
6830 {
6831 Qda = arm_decode_field_multiple (given, 13, 15, 22, 22);
6832 Qm = arm_decode_field_multiple (given, 1, 3, 5, 5);
6833 Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
6834
6835 if ((Qda == Qn) || (Qda == Qm))
6836 {
6837 *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
6838 return TRUE;
6839 }
6840 else
6841 return FALSE;
6842 }
6843 else
6844 return FALSE;
6845
6846 }
6847
e523f101
AV		 6848 case MVE_VCTP:
6849 if (arm_decode_field (given, 16, 19) == 0xd)
6850 {
6851 *unpredictable_code = UNPRED_R13;
6852 return TRUE;
6853 }
6854 else
6855 return FALSE;
6856
14b456f2
AV		 6857 case MVE_VREV64:
6858 {
6859 unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22);
6860 unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6);
6861
6862 if (qd == qm)
6863 {
6864 *unpredictable_code = UNPRED_Q_REGS_EQUAL;
6865 return TRUE;
6866 }
6867 else
6868 return FALSE;
6869 }
6870
23d00a41
SD		 6871 case MVE_LSLL:
6872 case MVE_LSLLI:
6873 case MVE_LSRL:
6874 case MVE_ASRL:
6875 case MVE_ASRLI:
6876 case MVE_UQSHLL:
6877 case MVE_UQRSHLL:
6878 case MVE_URSHRL:
6879 case MVE_SRSHRL:
6880 case MVE_SQSHLL:
6881 case MVE_SQRSHRL:
6882 {
6883 unsigned long gpr = arm_decode_field (given, 9, 11);
6884 gpr = ((gpr << 1) | 1);
6885 if (gpr == 0xd)
6886 {
6887 *unpredictable_code = UNPRED_R13;
6888 return TRUE;
6889 }
6890 else if (gpr == 0xf)
6891 {
6892 *unpredictable_code = UNPRED_R15;
6893 return TRUE;
6894 }
6895
6896 return FALSE;
6897 }
6898
143275ea
AV		 6899 default:
6900 return FALSE;
6901 }
6902}
c1e26897 6903
c507f10b
AV		 6904static void
6905print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
6906{
6907 unsigned long op1 = arm_decode_field (given, 21, 22);
6908 unsigned long op2 = arm_decode_field (given, 5, 6);
6909 unsigned long h = arm_decode_field (given, 16, 16);
43dd7626 6910 unsigned long index_operand, esize, targetBeat, idx;
c507f10b
AV		 6911 void *stream = info->stream;
6912 fprintf_ftype func = info->fprintf_func;
6913
6914 if ((op1 & 0x2) == 0x2)
6915 {
43dd7626 6916 index_operand = op2;
c507f10b
AV		 6917 esize = 8;
6918 }
6919 else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
6920 {
43dd7626 6921 index_operand = op2 >> 1;
c507f10b
AV		 6922 esize = 16;
6923 }
6924 else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
6925 {
43dd7626 6926 index_operand = 0;
c507f10b
AV		 6927 esize = 32;
6928 }
6929 else
6930 {
6931 func (stream, "<undefined index>");
6932 return;
6933 }
6934
6935 targetBeat = (op1 & 0x1) | (h << 1);
43dd7626 6936 idx = index_operand + targetBeat * (32/esize);
c507f10b
AV		 6937
6938 func (stream, "%lu", idx);
6939}
6940
6941/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6942 in length and integer of floating-point type. */
6943static void
6944print_simd_imm8 (struct disassemble_info *info, unsigned long given,
6945 unsigned int ibit_loc, const struct mopcode32 *insn)
6946{
6947 int bits = 0;
6948 int cmode = (given >> 8) & 0xf;
6949 int op = (given >> 5) & 0x1;
6950 unsigned long value = 0, hival = 0;
6951 unsigned shift;
6952 int size = 0;
6953 int isfloat = 0;
6954 void *stream = info->stream;
6955 fprintf_ftype func = info->fprintf_func;
6956
6957 /* On Neon the 'i' bit is at bit 24, on mve it is
6958 at bit 28. */
6959 bits |= ((given >> ibit_loc) & 1) << 7;
6960 bits |= ((given >> 16) & 7) << 4;
6961 bits |= ((given >> 0) & 15) << 0;
6962
6963 if (cmode < 8)
6964 {
6965 shift = (cmode >> 1) & 3;
6966 value = (unsigned long) bits << (8 * shift);
6967 size = 32;
6968 }
6969 else if (cmode < 12)
6970 {
6971 shift = (cmode >> 1) & 1;
6972 value = (unsigned long) bits << (8 * shift);
6973 size = 16;
6974 }
6975 else if (cmode < 14)
6976 {
6977 shift = (cmode & 1) + 1;
6978 value = (unsigned long) bits << (8 * shift);
6979 value |= (1ul << (8 * shift)) - 1;
6980 size = 32;
6981 }
6982 else if (cmode == 14)
6983 {
6984 if (op)
6985 {
6986 /* Bit replication into bytes. */
6987 int ix;
6988 unsigned long mask;
6989
6990 value = 0;
6991 hival = 0;
6992 for (ix = 7; ix >= 0; ix--)
6993 {
6994 mask = ((bits >> ix) & 1) ? 0xff : 0;
6995 if (ix <= 3)
6996 value = (value << 8) | mask;
6997 else
6998 hival = (hival << 8) | mask;
6999 }
7000 size = 64;
7001 }
7002 else
7003 {
7004 /* Byte replication. */
7005 value = (unsigned long) bits;
7006 size = 8;
7007 }
7008 }
7009 else if (!op)
7010 {
7011 /* Floating point encoding. */
7012 int tmp;
7013
7014 value = (unsigned long) (bits & 0x7f) << 19;
7015 value |= (unsigned long) (bits & 0x80) << 24;
7016 tmp = bits & 0x40 ? 0x3c : 0x40;
7017 value |= (unsigned long) tmp << 24;
7018 size = 32;
7019 isfloat = 1;
7020 }
7021 else
7022 {
7023 func (stream, "<illegal constant %.8x:%x:%x>",
7024 bits, cmode, op);
7025 size = 32;
7026 return;
7027 }
7028
7029 // printU determines whether the immediate value should be printed as
7030 // unsigned.
7031 unsigned printU = 0;
7032 switch (insn->mve_op)
7033 {
7034 default:
7035 break;
7036 // We want this for instructions that don't have a 'signed' type
7037 case MVE_VBIC_IMM:
7038 case MVE_VORR_IMM:
7039 case MVE_VMVN_IMM:
7040 case MVE_VMOV_IMM_TO_VEC:
7041 printU = 1;
7042 break;
7043 }
7044 switch (size)
7045 {
7046 case 8:
7047 func (stream, "#%ld\t; 0x%.2lx", value, value);
7048 break;
7049
7050 case 16:
7051 func (stream,
7052 printU
7053 ? "#%lu\t; 0x%.4lx"
7054 : "#%ld\t; 0x%.4lx", value, value);
7055 break;
7056
7057 case 32:
7058 if (isfloat)
7059 {
7060 unsigned char valbytes[4];
7061 double fvalue;
7062
7063 /* Do this a byte at a time so we don't have to
7064 worry about the host's endianness. */
7065 valbytes[0] = value & 0xff;
7066 valbytes[1] = (value >> 8) & 0xff;
7067 valbytes[2] = (value >> 16) & 0xff;
7068 valbytes[3] = (value >> 24) & 0xff;
7069
7070 floatformat_to_double
7071 (& floatformat_ieee_single_little, valbytes,
7072 & fvalue);
7073
7074 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
7075 value);
7076 }
7077 else
7078 func (stream,
7079 printU
7080 ? "#%lu\t; 0x%.8lx"
7081 : "#%ld\t; 0x%.8lx",
7082 (long) (((value & 0x80000000L) != 0)
7083 && !printU
7084 ? value | ~0xffffffffL : value),
7085 value);
7086 break;
7087
7088 case 64:
7089 func (stream, "#0x%.8lx%.8lx", hival, value);
7090 break;
7091
7092 default:
7093 abort ();
7094 }
7095
7096}
7097
73cd51e5
AV		 7098static void
7099print_mve_undefined (struct disassemble_info *info,
7100 enum mve_undefined undefined_code)
7101{
7102 void *stream = info->stream;
7103 fprintf_ftype func = info->fprintf_func;
7104
7105 func (stream, "\t\tundefined instruction: ");
7106
7107 switch (undefined_code)
7108 {
ed63aa17
AV		 7109 case UNDEF_SIZE:
7110 func (stream, "illegal size");
7111 break;
7112
aef6d006
AV		 7113 case UNDEF_SIZE_0:
7114 func (stream, "size equals zero");
7115 break;
7116
c507f10b
AV		 7117 case UNDEF_SIZE_2:
7118 func (stream, "size equals two");
7119 break;
7120
9743db03
AV		 7121 case UNDEF_SIZE_3:
7122 func (stream, "size equals three");
7123 break;
7124
aef6d006
AV		 7125 case UNDEF_SIZE_LE_1:
7126 func (stream, "size <= 1");
7127 break;
7128
14b456f2
AV		 7129 case UNDEF_SIZE_NOT_0:
7130 func (stream, "size not equal to 0");
7131 break;
7132
ef1576a1
AV		 7133 case UNDEF_SIZE_NOT_2:
7134 func (stream, "size not equal to 2");
7135 break;
7136
7137 case UNDEF_SIZE_NOT_3:
7138 func (stream, "size not equal to 3");
7139 break;
7140
7141 case UNDEF_NOT_UNS_SIZE_0:
7142 func (stream, "not unsigned and size = zero");
7143 break;
7144
7145 case UNDEF_NOT_UNS_SIZE_1:
7146 func (stream, "not unsigned and size = one");
7147 break;
7148
7149 case UNDEF_NOT_UNSIGNED:
7150 func (stream, "not unsigned");
7151 break;
7152
bf0b396d
AV		 7153 case UNDEF_VCVT_IMM6:
7154 func (stream, "invalid imm6");
7155 break;
7156
7157 case UNDEF_VCVT_FSI_IMM6:
7158 func (stream, "fsi = 0 and invalid imm6");
7159 break;
7160
c507f10b
AV		 7161 case UNDEF_BAD_OP1_OP2:
7162 func (stream, "bad size with op2 = 2 and op1 = 0 or 1");
7163 break;
7164
7165 case UNDEF_BAD_U_OP1_OP2:
7166 func (stream, "unsigned with op2 = 0 and op1 = 0 or 1");
7167 break;
7168
7169 case UNDEF_OP_0_BAD_CMODE:
7170 func (stream, "op field equal 0 and bad cmode");
7171 break;
7172
d3b63143
AV		 7173 case UNDEF_XCHG_UNS:
7174 func (stream, "exchange and unsigned together");
7175 break;
7176
73cd51e5
AV		 7177 case UNDEF_NONE:
7178 break;
7179 }
7180
7181}
7182
7183static void
7184print_mve_unpredictable (struct disassemble_info *info,
7185 enum mve_unpredictable unpredict_code)
7186{
7187 void *stream = info->stream;
7188 fprintf_ftype func = info->fprintf_func;
7189
7190 func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
7191
7192 switch (unpredict_code)
7193 {
7194 case UNPRED_IT_BLOCK:
7195 func (stream, "mve instruction in it block");
7196 break;
7197
143275ea
AV		 7198 case UNPRED_FCA_0_FCB_1:
7199 func (stream, "condition bits, fca = 0 and fcb = 1");
7200 break;
7201
7202 case UNPRED_R13:
7203 func (stream, "use of r13 (sp)");
7204 break;
7205
9743db03
AV		 7206 case UNPRED_R15:
7207 func (stream, "use of r15 (pc)");
7208 break;
7209
04d54ace
AV		 7210 case UNPRED_Q_GT_4:
7211 func (stream, "start register block > r4");
7212 break;
7213
7214 case UNPRED_Q_GT_6:
7215 func (stream, "start register block > r6");
7216 break;
7217
7218 case UNPRED_R13_AND_WB:
7219 func (stream, "use of r13 and write back");
7220 break;
7221
ef1576a1
AV		 7222 case UNPRED_Q_REGS_EQUAL:
7223 func (stream,
7224 "same vector register used for destination and other operand");
7225 break;
7226
7227 case UNPRED_OS:
7228 func (stream, "use of offset scaled");
7229 break;
7230
bf0b396d
AV		 7231 case UNPRED_GP_REGS_EQUAL:
7232 func (stream, "same general-purpose register used for both operands");
7233 break;
7234
c507f10b
AV		 7235 case UNPRED_Q_REGS_EQ_AND_SIZE_1:
7236 func (stream, "use of identical q registers and size = 1");
7237 break;
7238
7239 case UNPRED_Q_REGS_EQ_AND_SIZE_2:
7240 func (stream, "use of identical q registers and size = 1");
7241 break;
7242
73cd51e5
AV		 7243 case UNPRED_NONE:
7244 break;
7245 }
7246}
7247
04d54ace
AV		 7248/* Print register block operand for mve vld2/vld4/vst2/vld4. */
7249
7250static void
7251print_mve_register_blocks (struct disassemble_info *info,
7252 unsigned long given,
7253 enum mve_instructions matched_insn)
7254{
7255 void *stream = info->stream;
7256 fprintf_ftype func = info->fprintf_func;
7257
7258 unsigned long q_reg_start = arm_decode_field_multiple (given,
7259 13, 15,
7260 22, 22);
7261 switch (matched_insn)
7262 {
7263 case MVE_VLD2:
7264 case MVE_VST2:
7265 if (q_reg_start <= 6)
7266 func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
7267 else
7268 func (stream, "<illegal reg q%ld>", q_reg_start);
7269 break;
7270
7271 case MVE_VLD4:
7272 case MVE_VST4:
7273 if (q_reg_start <= 4)
7274 func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
7275 q_reg_start + 1, q_reg_start + 2,
7276 q_reg_start + 3);
7277 else
7278 func (stream, "<illegal reg q%ld>", q_reg_start);
7279 break;
7280
7281 default:
7282 break;
7283 }
7284}
7285
bf0b396d
AV		 7286static void
7287print_mve_rounding_mode (struct disassemble_info *info,
7288 unsigned long given,
7289 enum mve_instructions matched_insn)
7290{
7291 void *stream = info->stream;
7292 fprintf_ftype func = info->fprintf_func;
7293
7294 switch (matched_insn)
7295 {
7296 case MVE_VCVT_FROM_FP_TO_INT:
7297 {
7298 switch (arm_decode_field (given, 8, 9))
7299 {
7300 case 0:
7301 func (stream, "a");
7302 break;
7303
7304 case 1:
7305 func (stream, "n");
7306 break;
7307
7308 case 2:
7309 func (stream, "p");
7310 break;
7311
7312 case 3:
7313 func (stream, "m");
7314 break;
7315
7316 default:
7317 break;
7318 }
7319 }
7320 break;
7321
7322 case MVE_VRINT_FP:
7323 {
7324 switch (arm_decode_field (given, 7, 9))
7325 {
7326 case 0:
7327 func (stream, "n");
7328 break;
7329
7330 case 1:
7331 func (stream, "x");
7332 break;
7333
7334 case 2:
7335 func (stream, "a");
7336 break;
7337
7338 case 3:
7339 func (stream, "z");
7340 break;
7341
7342 case 5:
7343 func (stream, "m");
7344 break;
7345
7346 case 7:
7347 func (stream, "p");
7348
7349 case 4:
7350 case 6:
7351 default:
7352 break;
7353 }
7354 }
7355 break;
7356
7357 default:
7358 break;
7359 }
7360}
7361
7362static void
7363print_mve_vcvt_size (struct disassemble_info *info,
7364 unsigned long given,
7365 enum mve_instructions matched_insn)
7366{
7367 unsigned long mode = 0;
7368 void *stream = info->stream;
7369 fprintf_ftype func = info->fprintf_func;
7370
7371 switch (matched_insn)
7372 {
7373 case MVE_VCVT_FP_FIX_VEC:
7374 {
7375 mode = (((given & 0x200) >> 7)
7376 | ((given & 0x10000000) >> 27)
7377 | ((given & 0x100) >> 8));
7378
7379 switch (mode)
7380 {
7381 case 0:
7382 func (stream, "f16.s16");
7383 break;
7384
7385 case 1:
7386 func (stream, "s16.f16");
7387 break;
7388
7389 case 2:
7390 func (stream, "f16.u16");
7391 break;
7392
7393 case 3:
7394 func (stream, "u16.f16");
7395 break;
7396
7397 case 4:
7398 func (stream, "f32.s32");
7399 break;
7400
7401 case 5:
7402 func (stream, "s32.f32");
7403 break;
7404
7405 case 6:
7406 func (stream, "f32.u32");
7407 break;
7408
7409 case 7:
7410 func (stream, "u32.f32");
7411 break;
7412
7413 default:
7414 break;
7415 }
7416 break;
7417 }
7418 case MVE_VCVT_BETWEEN_FP_INT:
7419 {
7420 unsigned long size = arm_decode_field (given, 18, 19);
7421 unsigned long op = arm_decode_field (given, 7, 8);
7422
7423 if (size == 1)
7424 {
7425 switch (op)
7426 {
7427 case 0:
7428 func (stream, "f16.s16");
7429 break;
7430
7431 case 1:
7432 func (stream, "f16.u16");
7433 break;
7434
7435 case 2:
7436 func (stream, "s16.f16");
7437 break;
7438
7439 case 3:
7440 func (stream, "u16.f16");
7441 break;
7442
7443 default:
7444 break;
7445 }
7446 }
7447 else if (size == 2)
7448 {
7449 switch (op)
7450 {
7451 case 0:
7452 func (stream, "f32.s32");
7453 break;
7454
7455 case 1:
7456 func (stream, "f32.u32");
7457 break;
7458
7459 case 2:
7460 func (stream, "s32.f32");
7461 break;
7462
7463 case 3:
7464 func (stream, "u32.f32");
7465 break;
7466 }
7467 }
7468 }
7469 break;
7470
7471 case MVE_VCVT_FP_HALF_FP:
7472 {
7473 unsigned long op = arm_decode_field (given, 28, 28);
7474 if (op == 0)
7475 func (stream, "f16.f32");
7476 else if (op == 1)
7477 func (stream, "f32.f16");
7478 }
7479 break;
7480
7481 case MVE_VCVT_FROM_FP_TO_INT:
7482 {
7483 unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19);
7484
7485 switch (size)
7486 {
7487 case 2:
7488 func (stream, "s16.f16");
7489 break;
7490
7491 case 3:
7492 func (stream, "u16.f16");
7493 break;
7494
7495 case 4:
7496 func (stream, "s32.f32");
7497 break;
7498
7499 case 5:
7500 func (stream, "u32.f32");
7501 break;
7502
7503 default:
7504 break;
7505 }
7506 }
7507 break;
7508
7509 default:
7510 break;
7511 }
7512}
7513
897b9bbc
AV		 7514static void
7515print_mve_rotate (struct disassemble_info *info, unsigned long rot,
7516 unsigned long rot_width)
7517{
7518 void *stream = info->stream;
7519 fprintf_ftype func = info->fprintf_func;
7520
7521 if (rot_width == 1)
7522 {
7523 switch (rot)
7524 {
7525 case 0:
7526 func (stream, "90");
7527 break;
7528 case 1:
7529 func (stream, "270");
7530 break;
7531 default:
7532 break;
7533 }
7534 }
7535 else if (rot_width == 2)
7536 {
7537 switch (rot)
7538 {
7539 case 0:
7540 func (stream, "0");
7541 break;
7542 case 1:
7543 func (stream, "90");
7544 break;
7545 case 2:
7546 func (stream, "180");
7547 break;
7548 case 3:
7549 func (stream, "270");
7550 break;
7551 default:
7552 break;
7553 }
7554 }
7555}
7556
143275ea
AV		 7557static void
7558print_instruction_predicate (struct disassemble_info *info)
7559{
7560 void *stream = info->stream;
7561 fprintf_ftype func = info->fprintf_func;
7562
7563 if (vpt_block_state.next_pred_state == PRED_THEN)
7564 func (stream, "t");
7565 else if (vpt_block_state.next_pred_state == PRED_ELSE)
7566 func (stream, "e");
7567}
7568
7569static void
7570print_mve_size (struct disassemble_info *info,
7571 unsigned long size,
7572 enum mve_instructions matched_insn)
7573{
7574 void *stream = info->stream;
7575 fprintf_ftype func = info->fprintf_func;
7576
7577 switch (matched_insn)
7578 {
66dcaa5d
AV		 7579 case MVE_VABAV:
7580 case MVE_VABD_VEC:
7581 case MVE_VABS_FP:
7582 case MVE_VABS_VEC:
7583 case MVE_VADD_VEC_T1:
7584 case MVE_VADD_VEC_T2:
d3b63143 7585 case MVE_VADDV:
e523f101 7586 case MVE_VBRSR:
897b9bbc 7587 case MVE_VCADD_VEC:
e523f101
AV		 7588 case MVE_VCLS:
7589 case MVE_VCLZ:
143275ea
AV		 7590 case MVE_VCMP_VEC_T1:
7591 case MVE_VCMP_VEC_T2:
7592 case MVE_VCMP_VEC_T3:
7593 case MVE_VCMP_VEC_T4:
7594 case MVE_VCMP_VEC_T5:
7595 case MVE_VCMP_VEC_T6:
e523f101 7596 case MVE_VCTP:
1c8f2df8
AV		 7597 case MVE_VDDUP:
7598 case MVE_VDWDUP:
9743db03
AV		 7599 case MVE_VHADD_T1:
7600 case MVE_VHADD_T2:
897b9bbc 7601 case MVE_VHCADD:
9743db03
AV		 7602 case MVE_VHSUB_T1:
7603 case MVE_VHSUB_T2:
1c8f2df8
AV		 7604 case MVE_VIDUP:
7605 case MVE_VIWDUP:
04d54ace
AV		 7606 case MVE_VLD2:
7607 case MVE_VLD4:
ef1576a1
AV		 7608 case MVE_VLDRB_GATHER_T1:
7609 case MVE_VLDRH_GATHER_T2:
7610 case MVE_VLDRW_GATHER_T3:
7611 case MVE_VLDRD_GATHER_T4:
aef6d006
AV		 7612 case MVE_VLDRB_T1:
7613 case MVE_VLDRH_T2:
56858bea
AV		 7614 case MVE_VMAX:
7615 case MVE_VMAXA:
7616 case MVE_VMAXV:
7617 case MVE_VMAXAV:
7618 case MVE_VMIN:
7619 case MVE_VMINA:
7620 case MVE_VMINV:
7621 case MVE_VMINAV:
7622 case MVE_VMLA:
d3b63143 7623 case MVE_VMLAS:
f49bb598
AV		 7624 case MVE_VMUL_VEC_T1:
7625 case MVE_VMUL_VEC_T2:
7626 case MVE_VMULH:
7627 case MVE_VRMULH:
7628 case MVE_VMULL_INT:
7629 case MVE_VNEG_FP:
7630 case MVE_VNEG_VEC:
143275ea
AV		 7631 case MVE_VPT_VEC_T1:
7632 case MVE_VPT_VEC_T2:
7633 case MVE_VPT_VEC_T3:
7634 case MVE_VPT_VEC_T4:
7635 case MVE_VPT_VEC_T5:
7636 case MVE_VPT_VEC_T6:
14b456f2
AV		 7637 case MVE_VQABS:
7638 case MVE_VQADD_T1:
7639 case MVE_VQADD_T2:
d3b63143
AV		 7640 case MVE_VQDMLADH:
7641 case MVE_VQRDMLADH:
7642 case MVE_VQDMLAH:
7643 case MVE_VQRDMLAH:
7644 case MVE_VQDMLASH:
7645 case MVE_VQRDMLASH:
7646 case MVE_VQDMLSDH:
7647 case MVE_VQRDMLSDH:
7648 case MVE_VQDMULH_T1:
7649 case MVE_VQRDMULH_T2:
7650 case MVE_VQDMULH_T3:
7651 case MVE_VQRDMULH_T4:
14b456f2 7652 case MVE_VQNEG:
ed63aa17
AV		 7653 case MVE_VQRSHL_T1:
7654 case MVE_VQRSHL_T2:
7655 case MVE_VQSHL_T1:
7656 case MVE_VQSHL_T4:
14b456f2
AV		 7657 case MVE_VQSUB_T1:
7658 case MVE_VQSUB_T2:
7659 case MVE_VREV32:
7660 case MVE_VREV64:
9743db03 7661 case MVE_VRHADD:
bf0b396d 7662 case MVE_VRINT_FP:
ed63aa17
AV		 7663 case MVE_VRSHL_T1:
7664 case MVE_VRSHL_T2:
7665 case MVE_VSHL_T2:
7666 case MVE_VSHL_T3:
7667 case MVE_VSHLL_T2:
04d54ace
AV		 7668 case MVE_VST2:
7669 case MVE_VST4:
ef1576a1
AV		 7670 case MVE_VSTRB_SCATTER_T1:
7671 case MVE_VSTRH_SCATTER_T2:
7672 case MVE_VSTRW_SCATTER_T3:
aef6d006
AV		 7673 case MVE_VSTRB_T1:
7674 case MVE_VSTRH_T2:
66dcaa5d
AV		 7675 case MVE_VSUB_VEC_T1:
7676 case MVE_VSUB_VEC_T2:
143275ea
AV		 7677 if (size <= 3)
7678 func (stream, "%s", mve_vec_sizename[size]);
7679 else
7680 func (stream, "<undef size>");
7681 break;
7682
66dcaa5d
AV		 7683 case MVE_VABD_FP:
7684 case MVE_VADD_FP_T1:
7685 case MVE_VADD_FP_T2:
7686 case MVE_VSUB_FP_T1:
7687 case MVE_VSUB_FP_T2:
143275ea
AV		 7688 case MVE_VCMP_FP_T1:
7689 case MVE_VCMP_FP_T2:
9743db03
AV		 7690 case MVE_VFMA_FP_SCALAR:
7691 case MVE_VFMA_FP:
7692 case MVE_VFMS_FP:
7693 case MVE_VFMAS_FP_SCALAR:
56858bea
AV		 7694 case MVE_VMAXNM_FP:
7695 case MVE_VMAXNMA_FP:
7696 case MVE_VMAXNMV_FP:
7697 case MVE_VMAXNMAV_FP:
7698 case MVE_VMINNM_FP:
7699 case MVE_VMINNMA_FP:
7700 case MVE_VMINNMV_FP:
7701 case MVE_VMINNMAV_FP:
f49bb598
AV		 7702 case MVE_VMUL_FP_T1:
7703 case MVE_VMUL_FP_T2:
143275ea
AV		 7704 case MVE_VPT_FP_T1:
7705 case MVE_VPT_FP_T2:
7706 if (size == 0)
7707 func (stream, "32");
7708 else if (size == 1)
7709 func (stream, "16");
7710 break;
7711
897b9bbc
AV		 7712 case MVE_VCADD_FP:
7713 case MVE_VCMLA_FP:
7714 case MVE_VCMUL_FP:
d3b63143
AV		 7715 case MVE_VMLADAV_T1:
7716 case MVE_VMLALDAV:
7717 case MVE_VMLSDAV_T1:
7718 case MVE_VMLSLDAV:
14925797
AV		 7719 case MVE_VMOVN:
7720 case MVE_VQDMULL_T1:
7721 case MVE_VQDMULL_T2:
7722 case MVE_VQMOVN:
7723 case MVE_VQMOVUN:
7724 if (size == 0)
7725 func (stream, "16");
7726 else if (size == 1)
7727 func (stream, "32");
7728 break;
7729
7730 case MVE_VMOVL:
7731 if (size == 1)
7732 func (stream, "8");
7733 else if (size == 2)
7734 func (stream, "16");
7735 break;
7736
9743db03
AV		 7737 case MVE_VDUP:
7738 switch (size)
7739 {
7740 case 0:
7741 func (stream, "32");
7742 break;
7743 case 1:
7744 func (stream, "16");
7745 break;
7746 case 2:
7747 func (stream, "8");
7748 break;
7749 default:
7750 break;
7751 }
7752 break;
7753
c507f10b
AV		 7754 case MVE_VMOV_GP_TO_VEC_LANE:
7755 case MVE_VMOV_VEC_LANE_TO_GP:
7756 switch (size)
7757 {
7758 case 0: case 4:
7759 func (stream, "32");
7760 break;
7761
7762 case 1: case 3:
7763 case 5: case 7:
7764 func (stream, "16");
7765 break;
7766
7767 case 8: case 9: case 10: case 11:
7768 case 12: case 13: case 14: case 15:
7769 func (stream, "8");
7770 break;
7771
7772 default:
7773 break;
7774 }
7775 break;
7776
7777 case MVE_VMOV_IMM_TO_VEC:
7778 switch (size)
7779 {
7780 case 0: case 4: case 8:
7781 case 12: case 24: case 26:
7782 func (stream, "i32");
7783 break;
7784 case 16: case 20:
7785 func (stream, "i16");
7786 break;
7787 case 28:
7788 func (stream, "i8");
7789 break;
7790 case 29:
7791 func (stream, "i64");
7792 break;
7793 case 30:
7794 func (stream, "f32");
7795 break;
7796 default:
7797 break;
7798 }
7799 break;
7800
14925797
AV		 7801 case MVE_VMULL_POLY:
7802 if (size == 0)
7803 func (stream, "p8");
7804 else if (size == 1)
7805 func (stream, "p16");
7806 break;
7807
c507f10b
AV		 7808 case MVE_VMVN_IMM:
7809 switch (size)
7810 {
7811 case 0: case 2: case 4:
7812 case 6: case 12: case 13:
7813 func (stream, "32");
7814 break;
7815
7816 case 8: case 10:
7817 func (stream, "16");
7818 break;
7819
7820 default:
7821 break;
7822 }
7823 break;
7824
7825 case MVE_VBIC_IMM:
7826 case MVE_VORR_IMM:
7827 switch (size)
7828 {
7829 case 1: case 3:
7830 case 5: case 7:
7831 func (stream, "32");
7832 break;
7833
7834 case 9: case 11:
7835 func (stream, "16");
7836 break;
7837
7838 default:
7839 break;
7840 }
7841 break;
7842
ed63aa17
AV		 7843 case MVE_VQSHRN:
7844 case MVE_VQSHRUN:
7845 case MVE_VQRSHRN:
7846 case MVE_VQRSHRUN:
7847 case MVE_VRSHRN:
7848 case MVE_VSHRN:
7849 {
7850 switch (size)
7851 {
7852 case 1:
7853 func (stream, "16");
7854 break;
7855
7856 case 2: case 3:
7857 func (stream, "32");
7858 break;
7859
7860 default:
7861 break;
7862 }
7863 }
7864 break;
7865
7866 case MVE_VQSHL_T2:
7867 case MVE_VQSHLU_T3:
7868 case MVE_VRSHR:
7869 case MVE_VSHL_T1:
7870 case MVE_VSHLL_T1:
7871 case MVE_VSHR:
7872 case MVE_VSLI:
7873 case MVE_VSRI:
7874 {
7875 switch (size)
7876 {
7877 case 1:
7878 func (stream, "8");
7879 break;
7880
7881 case 2: case 3:
7882 func (stream, "16");
7883 break;
7884
7885 case 4: case 5: case 6: case 7:
7886 func (stream, "32");
7887 break;
7888
7889 default:
7890 break;
7891 }
7892 }
7893 break;
7894
143275ea
AV		 7895 default:
7896 break;
7897 }
7898}
7899
ed63aa17
AV		 7900static void
7901print_mve_shift_n (struct disassemble_info *info, long given,
7902 enum mve_instructions matched_insn)
7903{
7904 void *stream = info->stream;
7905 fprintf_ftype func = info->fprintf_func;
7906
7907 int startAt0
7908 = matched_insn == MVE_VQSHL_T2
7909 || matched_insn == MVE_VQSHLU_T3
7910 || matched_insn == MVE_VSHL_T1
7911 || matched_insn == MVE_VSHLL_T1
7912 || matched_insn == MVE_VSLI;
7913
7914 unsigned imm6 = (given & 0x3f0000) >> 16;
7915
7916 if (matched_insn == MVE_VSHLL_T1)
7917 imm6 &= 0x1f;
7918
7919 unsigned shiftAmount = 0;
7920 if ((imm6 & 0x20) != 0)
7921 shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6;
7922 else if ((imm6 & 0x10) != 0)
7923 shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6;
7924 else if ((imm6 & 0x08) != 0)
7925 shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6;
7926 else
7927 print_mve_undefined (info, UNDEF_SIZE_0);
7928
7929 func (stream, "%u", shiftAmount);
7930}
7931
143275ea
AV		 7932static void
7933print_vec_condition (struct disassemble_info *info, long given,
7934 enum mve_instructions matched_insn)
7935{
7936 void *stream = info->stream;
7937 fprintf_ftype func = info->fprintf_func;
7938 long vec_cond = 0;
7939
7940 switch (matched_insn)
7941 {
7942 case MVE_VPT_FP_T1:
7943 case MVE_VCMP_FP_T1:
7944 vec_cond = (((given & 0x1000) >> 10)
7945 | ((given & 1) << 1)
7946 | ((given & 0x0080) >> 7));
7947 func (stream, "%s",vec_condnames[vec_cond]);
7948 break;
7949
7950 case MVE_VPT_FP_T2:
7951 case MVE_VCMP_FP_T2:
7952 vec_cond = (((given & 0x1000) >> 10)
7953 | ((given & 0x0020) >> 4)
7954 | ((given & 0x0080) >> 7));
7955 func (stream, "%s",vec_condnames[vec_cond]);
7956 break;
7957
7958 case MVE_VPT_VEC_T1:
7959 case MVE_VCMP_VEC_T1:
7960 vec_cond = (given & 0x0080) >> 7;
7961 func (stream, "%s",vec_condnames[vec_cond]);
7962 break;
7963
7964 case MVE_VPT_VEC_T2:
7965 case MVE_VCMP_VEC_T2:
7966 vec_cond = 2 | ((given & 0x0080) >> 7);
7967 func (stream, "%s",vec_condnames[vec_cond]);
7968 break;
7969
7970 case MVE_VPT_VEC_T3:
7971 case MVE_VCMP_VEC_T3:
7972 vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
7973 func (stream, "%s",vec_condnames[vec_cond]);
7974 break;
7975
7976 case MVE_VPT_VEC_T4:
7977 case MVE_VCMP_VEC_T4:
7978 vec_cond = (given & 0x0080) >> 7;
7979 func (stream, "%s",vec_condnames[vec_cond]);
7980 break;
7981
7982 case MVE_VPT_VEC_T5:
7983 case MVE_VCMP_VEC_T5:
7984 vec_cond = 2 | ((given & 0x0080) >> 7);
7985 func (stream, "%s",vec_condnames[vec_cond]);
7986 break;
7987
7988 case MVE_VPT_VEC_T6:
7989 case MVE_VCMP_VEC_T6:
7990 vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
7991 func (stream, "%s",vec_condnames[vec_cond]);
7992 break;
7993
7994 case MVE_NONE:
7995 case MVE_VPST:
7996 default:
7997 break;
7998 }
7999}
8000
8001#define W_BIT 21
8002#define I_BIT 22
8003#define U_BIT 23
8004#define P_BIT 24
8005
8006#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8007#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8008#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8009#define PRE_BIT_SET (given & (1 << P_BIT))
8010
8011
8f06b2d8
PB		 8012/* Print one coprocessor instruction on INFO->STREAM.
8013 Return TRUE if the instuction matched, FALSE if this is not a
8014 recognised coprocessor instruction. */
8015
8016static bfd_boolean
33593eaf
MM		 8017print_insn_coprocessor_1 (const struct sopcode32 *opcodes,
8018 bfd_vma pc,
8019 struct disassemble_info *info,
8020 long given,
8021 bfd_boolean thumb)
8f06b2d8 8022{
6b0dd094 8023 const struct sopcode32 *insn;
8f06b2d8
PB		 8024 void *stream = info->stream;
8025 fprintf_ftype func = info->fprintf_func;
8026 unsigned long mask;
2edcd244 8027 unsigned long value = 0;
c22aaad1 8028 int cond;
8afc7bea 8029 int cp_num;
823d2571
TG		 8030 struct arm_private_data *private_data = info->private_data;
8031 arm_feature_set allowed_arches = ARM_ARCH_NONE;
32c36c3c
AV		 8032 arm_feature_set arm_ext_v8_1m_main =
8033 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
823d2571 8034
5b616bef 8035 allowed_arches = private_data->features;
8f06b2d8 8036
33593eaf 8037 for (insn = opcodes; insn->assembler; insn++)
8f06b2d8 8038 {
ff4a8d2b
NC		 8039 unsigned long u_reg = 16;
8040 bfd_boolean is_unpredictable = FALSE;
05413229 8041 signed long value_in_comment = 0;
0313a2b8
NC		 8042 const char *c;
8043
823d2571 8044 if (ARM_FEATURE_ZERO (insn->arch))
05413229
NC		 8045 switch (insn->value)
8046 {
8047 case SENTINEL_IWMMXT_START:
8048 if (info->mach != bfd_mach_arm_XScale
8049 && info->mach != bfd_mach_arm_iWMMXt
8050 && info->mach != bfd_mach_arm_iWMMXt2)
8051 do
8052 insn++;
823d2571
TG		 8053 while ((! ARM_FEATURE_ZERO (insn->arch))
8054 && insn->value != SENTINEL_IWMMXT_END);
05413229
NC		 8055 continue;
8056
8057 case SENTINEL_IWMMXT_END:
8058 continue;
8059
8060 case SENTINEL_GENERIC_START:
5b616bef 8061 allowed_arches = private_data->features;
05413229
NC		 8062 continue;
8063
8064 default:
8065 abort ();
8066 }
8f06b2d8
PB		 8067
8068 mask = insn->mask;
8069 value = insn->value;
8afc7bea
RL		 8070 cp_num = (given >> 8) & 0xf;
8071
8f06b2d8
PB		 8072 if (thumb)
8073 {
8074 /* The high 4 bits are 0xe for Arm conditional instructions, and
8075 0xe for arm unconditional instructions. The rest of the
8076 encoding is the same. */
8077 mask |= 0xf0000000;
8078 value |= 0xe0000000;
c22aaad1
PB		 8079 if (ifthen_state)
8080 cond = IFTHEN_COND;
8081 else
e2efe87d 8082 cond = COND_UNCOND;
8f06b2d8
PB		 8083 }
8084 else
8085 {
8086 /* Only match unconditional instuctions against unconditional
8087 patterns. */
8088 if ((given & 0xf0000000) == 0xf0000000)
c22aaad1
PB		 8089 {
8090 mask |= 0xf0000000;
e2efe87d 8091 cond = COND_UNCOND;
c22aaad1
PB		 8092 }
8093 else
8094 {
8095 cond = (given >> 28) & 0xf;
8096 if (cond == 0xe)
e2efe87d 8097 cond = COND_UNCOND;
c22aaad1 8098 }
8f06b2d8 8099 }
823d2571 8100
6b0dd094
AV		 8101 if ((insn->isa == T32 && !thumb)
8102 || (insn->isa == ARM && thumb))
8103 continue;
8104
0313a2b8
NC		 8105 if ((given & mask) != value)
8106 continue;
8f06b2d8 8107
823d2571 8108 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
0313a2b8
NC		 8109 continue;
8110
8afc7bea
RL		 8111 if (insn->value == 0xfe000010 /* mcr2 */
8112 || insn->value == 0xfe100010 /* mrc2 */
8113 || insn->value == 0xfc100000 /* ldc2 */
8114 || insn->value == 0xfc000000) /* stc2 */
8115 {
b0c11777 8116 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8117 is_unpredictable = TRUE;
f08d8ce3
AV		 8118
8119 /* Armv8.1-M Mainline FP & MVE instructions. */
8120 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8121 && !ARM_CPU_IS_ANY (allowed_arches)
8122 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8123 continue;
8124
8afc7bea
RL		 8125 }
8126 else if (insn->value == 0x0e000000 /* cdp */
8127 || insn->value == 0xfe000000 /* cdp2 */
8128 || insn->value == 0x0e000010 /* mcr */
8129 || insn->value == 0x0e100010 /* mrc */
8130 || insn->value == 0x0c100000 /* ldc */
8131 || insn->value == 0x0c000000) /* stc */
8132 {
8133 /* Floating-point instructions. */
b0c11777 8134 if (cp_num == 9 || cp_num == 10 || cp_num == 11)
8afc7bea 8135 continue;
32c36c3c
AV		 8136
8137 /* Armv8.1-M Mainline FP & MVE instructions. */
8138 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
8139 && !ARM_CPU_IS_ANY (allowed_arches)
8140 && (cp_num == 8 || cp_num == 14 || cp_num == 15))
8141 continue;
8afc7bea 8142 }
aef6d006
AV		 8143 else if ((insn->value == 0xec100f80 /* vldr (system register) */
8144 || insn->value == 0xec000f80) /* vstr (system register) */
8145 && arm_decode_field (given, 24, 24) == 0
8146 && arm_decode_field (given, 21, 21) == 0)
8147 /* If the P and W bits are both 0 then these encodings match the MVE
8148 VLDR and VSTR instructions, these are in a different table, so we
8149 don't let it match here. */
8150 continue;
8151
0313a2b8
NC		 8152 for (c = insn->assembler; *c; c++)
8153 {
8154 if (*c == '%')
8f06b2d8 8155 {
32c36c3c
AV		 8156 const char mod = *++c;
8157 switch (mod)
8f06b2d8 8158 {
0313a2b8
NC		 8159 case '%':
8160 func (stream, "%%");
8161 break;
8162
8163 case 'A':
32c36c3c 8164 case 'K':
05413229 8165 {
79862e45 8166 int rn = (given >> 16) & 0xf;
b0c11777 8167 bfd_vma offset = given & 0xff;
0313a2b8 8168
32c36c3c
AV		 8169 if (mod == 'K')
8170 offset = given & 0x7f;
8171
05413229 8172 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
8f06b2d8 8173
79862e45
DJ		 8174 if (PRE_BIT_SET || WRITEBACK_BIT_SET)
8175 {
8176 /* Not unindexed. The offset is scaled. */
b0c11777
RL		 8177 if (cp_num == 9)
8178 /* vldr.16/vstr.16 will shift the address
8179 left by 1 bit only. */
8180 offset = offset * 2;
8181 else
8182 offset = offset * 4;
8183
79862e45
DJ		 8184 if (NEGATIVE_BIT_SET)
8185 offset = - offset;
8186 if (rn != 15)
8187 value_in_comment = offset;
8188 }
8189
c1e26897 8190 if (PRE_BIT_SET)
05413229
NC		 8191 {
8192 if (offset)
fe56b6ce 8193 func (stream, ", #%d]%s",
d908c8af 8194 (int) offset,
c1e26897 8195 WRITEBACK_BIT_SET ? "!" : "");
26d97720
NS		 8196 else if (NEGATIVE_BIT_SET)
8197 func (stream, ", #-0]");
05413229
NC		 8198 else
8199 func (stream, "]");
8200 }
8201 else
8202 {
0313a2b8 8203 func (stream, "]");
8f06b2d8 8204
c1e26897 8205 if (WRITEBACK_BIT_SET)
05413229
NC		 8206 {
8207 if (offset)
d908c8af 8208 func (stream, ", #%d", (int) offset);
26d97720
NS		 8209 else if (NEGATIVE_BIT_SET)
8210 func (stream, ", #-0");
05413229
NC		 8211 }
8212 else
fe56b6ce 8213 {
26d97720
NS		 8214 func (stream, ", {%s%d}",
8215 (NEGATIVE_BIT_SET && !offset) ? "-" : "",
d908c8af 8216 (int) offset);
fe56b6ce
NC		 8217 value_in_comment = offset;
8218 }
05413229 8219 }
79862e45
DJ		 8220 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
8221 {
8222 func (stream, "\t; ");
6844b2c2
MGD		 8223 /* For unaligned PCs, apply off-by-alignment
8224 correction. */
43e65147 8225 info->print_address_func (offset + pc
6844b2c2
MGD		 8226 + info->bytes_per_chunk * 2
8227 - (pc & 3),
dffaa15c 8228 info);
79862e45 8229 }
05413229 8230 }
0313a2b8 8231 break;
8f06b2d8 8232
0313a2b8
NC		 8233 case 'B':
8234 {
8235 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
8236 int offset = (given >> 1) & 0x3f;
8237
8238 if (offset == 1)
8239 func (stream, "{d%d}", regno);
8240 else if (regno + offset > 32)
8241 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
8242 else
8243 func (stream, "{d%d-d%d}", regno, regno + offset - 1);
8244 }
8245 break;
8f06b2d8 8246
efd6b359
AV		 8247 case 'C':
8248 {
8249 bfd_boolean single = ((given >> 8) & 1) == 0;
8250 char reg_prefix = single ? 's' : 'd';
8251 int Dreg = (given >> 22) & 0x1;
8252 int Vdreg = (given >> 12) & 0xf;
8253 int reg = single ? ((Vdreg << 1) | Dreg)
8254 : ((Dreg << 4) | Vdreg);
8255 int num = (given >> (single ? 0 : 1)) & 0x7f;
8256 int maxreg = single ? 31 : 15;
8257 int topreg = reg + num - 1;
8258
8259 if (!num)
8260 func (stream, "{VPR}");
8261 else if (num == 1)
8262 func (stream, "{%c%d, VPR}", reg_prefix, reg);
8263 else if (topreg > maxreg)
8264 func (stream, "{%c%d-<overflow reg d%d, VPR}",
8265 reg_prefix, reg, single ? topreg >> 1 : topreg);
8266 else
8267 func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
8268 reg_prefix, topreg);
8269 }
8270 break;
8271
e2efe87d
MGD		 8272 case 'u':
8273 if (cond != COND_UNCOND)
8274 is_unpredictable = TRUE;
8275
8276 /* Fall through. */
0313a2b8 8277 case 'c':
b0c11777
RL		 8278 if (cond != COND_UNCOND && cp_num == 9)
8279 is_unpredictable = TRUE;
8280
aab2c27d
MM		 8281 /* Fall through. */
8282 case 'b':
0313a2b8
NC		 8283 func (stream, "%s", arm_conditional[cond]);
8284 break;
8f06b2d8 8285
0313a2b8
NC		 8286 case 'I':
8287 /* Print a Cirrus/DSP shift immediate. */
8288 /* Immediates are 7bit signed ints with bits 0..3 in
8289 bits 0..3 of opcode and bits 4..6 in bits 5..7
8290 of opcode. */
8291 {
8292 int imm;
8f06b2d8 8293
0313a2b8 8294 imm = (given & 0xf) | ((given & 0xe0) >> 1);
8f06b2d8 8295
0313a2b8
NC		 8296 /* Is ``imm'' a negative number? */
8297 if (imm & 0x40)
24b4cf66 8298 imm -= 0x80;
8f06b2d8 8299
0313a2b8
NC		 8300 func (stream, "%d", imm);
8301 }
8302
8303 break;
8f06b2d8 8304
32c36c3c
AV		 8305 case 'J':
8306 {
73cd51e5
AV		 8307 unsigned long regno
8308 = arm_decode_field_multiple (given, 13, 15, 22, 22);
32c36c3c
AV		 8309
8310 switch (regno)
8311 {
8312 case 0x1:
8313 func (stream, "FPSCR");
8314 break;
8315 case 0x2:
8316 func (stream, "FPSCR_nzcvqc");
8317 break;
8318 case 0xc:
8319 func (stream, "VPR");
8320 break;
8321 case 0xd:
8322 func (stream, "P0");
8323 break;
8324 case 0xe:
8325 func (stream, "FPCXTNS");
8326 break;
8327 case 0xf:
8328 func (stream, "FPCXTS");
8329 break;
8330 default:
73cd51e5 8331 func (stream, "<invalid reg %lu>", regno);
32c36c3c
AV		 8332 break;
8333 }
8334 }
8335 break;
8336
0313a2b8
NC		 8337 case 'F':
8338 switch (given & 0x00408000)
8339 {
8340 case 0:
8341 func (stream, "4");
8342 break;
8343 case 0x8000:
8344 func (stream, "1");
8345 break;
8346 case 0x00400000:
8347 func (stream, "2");
8f06b2d8 8348 break;
0313a2b8
NC		 8349 default:
8350 func (stream, "3");
8351 }
8352 break;
8f06b2d8 8353
0313a2b8
NC		 8354 case 'P':
8355 switch (given & 0x00080080)
8356 {
8357 case 0:
8358 func (stream, "s");
8359 break;
8360 case 0x80:
8361 func (stream, "d");
8362 break;
8363 case 0x00080000:
8364 func (stream, "e");
8365 break;
8366 default:
8367 func (stream, _("<illegal precision>"));
8f06b2d8 8368 break;
0313a2b8
NC		 8369 }
8370 break;
8f06b2d8 8371
0313a2b8
NC		 8372 case 'Q':
8373 switch (given & 0x00408000)
8374 {
8375 case 0:
8376 func (stream, "s");
8f06b2d8 8377 break;
0313a2b8
NC		 8378 case 0x8000:
8379 func (stream, "d");
8f06b2d8 8380 break;
0313a2b8
NC		 8381 case 0x00400000:
8382 func (stream, "e");
8383 break;
8384 default:
8385 func (stream, "p");
8f06b2d8 8386 break;
0313a2b8
NC		 8387 }
8388 break;
8f06b2d8 8389
0313a2b8
NC		 8390 case 'R':
8391 switch (given & 0x60)
8392 {
8393 case 0:
8394 break;
8395 case 0x20:
8396 func (stream, "p");
8397 break;
8398 case 0x40:
8399 func (stream, "m");
8400 break;
8401 default:
8402 func (stream, "z");
8403 break;
8404 }
8405 break;
16980d0b 8406
0313a2b8
NC		 8407 case '0': case '1': case '2': case '3': case '4':
8408 case '5': case '6': case '7': case '8': case '9':
8409 {
8410 int width;
8f06b2d8 8411
0313a2b8 8412 c = arm_decode_bitfield (c, given, &value, &width);
8f06b2d8 8413
0313a2b8
NC		 8414 switch (*c)
8415 {
ff4a8d2b
NC		 8416 case 'R':
8417 if (value == 15)
8418 is_unpredictable = TRUE;
8419 /* Fall through. */
0313a2b8 8420 case 'r':
ff4a8d2b
NC		 8421 if (c[1] == 'u')
8422 {
8423 /* Eat the 'u' character. */
8424 ++ c;
8425
8426 if (u_reg == value)
8427 is_unpredictable = TRUE;
8428 u_reg = value;
8429 }
0313a2b8
NC		 8430 func (stream, "%s", arm_regnames[value]);
8431 break;
c28eeff2
SN		 8432 case 'V':
8433 if (given & (1 << 6))
8434 goto Q;
8435 /* FALLTHROUGH */
0313a2b8
NC		 8436 case 'D':
8437 func (stream, "d%ld", value);
8438 break;
8439 case 'Q':
c28eeff2 8440 Q:
0313a2b8
NC		 8441 if (value & 1)
8442 func (stream, "<illegal reg q%ld.5>", value >> 1);
8443 else
8444 func (stream, "q%ld", value >> 1);
8445 break;
8446 case 'd':
8447 func (stream, "%ld", value);
05413229 8448 value_in_comment = value;
0313a2b8 8449 break;
6f1c2142
AM		 8450 case 'E':
8451 {
8452 /* Converts immediate 8 bit back to float value. */
8453 unsigned floatVal = (value & 0x80) << 24
8454 | (value & 0x3F) << 19
8455 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
8456
8457 /* Quarter float have a maximum value of 31.0.
8458 Get floating point value multiplied by 1e7.
8459 The maximum value stays in limit of a 32-bit int. */
8460 unsigned decVal =
8461 (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
8462 (16 + (value & 0xF));
8463
8464 if (!(decVal % 1000000))
8465 func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
8466 floatVal, value & 0x80 ? '-' : ' ',
8467 decVal / 10000000,
8468 decVal % 10000000 / 1000000);
8469 else if (!(decVal % 10000))
8470 func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
8471 floatVal, value & 0x80 ? '-' : ' ',
8472 decVal / 10000000,
8473 decVal % 10000000 / 10000);
8474 else
8475 func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
8476 floatVal, value & 0x80 ? '-' : ' ',
8477 decVal / 10000000, decVal % 10000000);
8478 break;
8479 }
0313a2b8
NC		 8480 case 'k':
8481 {
8482 int from = (given & (1 << 7)) ? 32 : 16;
8483 func (stream, "%ld", from - value);
8484 }
8485 break;
8f06b2d8 8486
0313a2b8
NC		 8487 case 'f':
8488 if (value > 7)
8489 func (stream, "#%s", arm_fp_const[value & 7]);
8490 else
8491 func (stream, "f%ld", value);
8492 break;
4146fd53 8493
0313a2b8
NC		 8494 case 'w':
8495 if (width == 2)
8496 func (stream, "%s", iwmmxt_wwnames[value]);
8497 else
8498 func (stream, "%s", iwmmxt_wwssnames[value]);
8499 break;
4146fd53 8500
0313a2b8
NC		 8501 case 'g':
8502 func (stream, "%s", iwmmxt_regnames[value]);
8503 break;
8504 case 'G':
8505 func (stream, "%s", iwmmxt_cregnames[value]);
16980d0b 8506 break;
8f06b2d8 8507
0313a2b8 8508 case 'x':
d1aaab3c 8509 func (stream, "0x%lx", (value & 0xffffffffUL));
0313a2b8 8510 break;
8f06b2d8 8511
33399f07
MGD		 8512 case 'c':
8513 switch (value)
8514 {
8515 case 0:
8516 func (stream, "eq");
8517 break;
8518
8519 case 1:
8520 func (stream, "vs");
8521 break;
8522
8523 case 2:
8524 func (stream, "ge");
8525 break;
8526
8527 case 3:
8528 func (stream, "gt");
8529 break;
8530
8531 default:
8532 func (stream, "??");
8533 break;
8534 }
8535 break;
8536
0313a2b8
NC		 8537 case '`':
8538 c++;
8539 if (value == 0)
8540 func (stream, "%c", *c);
8541 break;
8542 case '\'':
8543 c++;
8544 if (value == ((1ul << width) - 1))
8545 func (stream, "%c", *c);
8546 break;
8547 case '?':
fe56b6ce 8548 func (stream, "%c", c[(1 << width) - (int) value]);
0313a2b8
NC		 8549 c += 1 << width;
8550 break;
8551 default:
8552 abort ();
8553 }
dffaa15c
AM		 8554 }
8555 break;
0313a2b8 8556
dffaa15c
AM		 8557 case 'y':
8558 case 'z':
8559 {
8560 int single = *c++ == 'y';
8561 int regno;
8f06b2d8 8562
dffaa15c
AM		 8563 switch (*c)
8564 {
8565 case '4': /* Sm pair */
8566 case '0': /* Sm, Dm */
8567 regno = given & 0x0000000f;
8568 if (single)
8569 {
8570 regno <<= 1;
8571 regno += (given >> 5) & 1;
8572 }
8573 else
8574 regno += ((given >> 5) & 1) << 4;
8575 break;
8f06b2d8 8576
dffaa15c
AM		 8577 case '1': /* Sd, Dd */
8578 regno = (given >> 12) & 0x0000000f;
8579 if (single)
8580 {
8581 regno <<= 1;
8582 regno += (given >> 22) & 1;
8583 }
8584 else
8585 regno += ((given >> 22) & 1) << 4;
8586 break;
7df76b80 8587
dffaa15c
AM		 8588 case '2': /* Sn, Dn */
8589 regno = (given >> 16) & 0x0000000f;
8590 if (single)
8591 {
8592 regno <<= 1;
8593 regno += (given >> 7) & 1;
8594 }
8595 else
8596 regno += ((given >> 7) & 1) << 4;
8597 break;
a7f8487e 8598
dffaa15c
AM		 8599 case '3': /* List */
8600 func (stream, "{");
8601 regno = (given >> 12) & 0x0000000f;
8602 if (single)
8603 {
8604 regno <<= 1;
8605 regno += (given >> 22) & 1;
8606 }
8607 else
8608 regno += ((given >> 22) & 1) << 4;
8609 break;
a7f8487e 8610
dffaa15c
AM		 8611 default:
8612 abort ();
8613 }
0313a2b8 8614
dffaa15c 8615 func (stream, "%c%d", single ? 's' : 'd', regno);
a7f8487e 8616
dffaa15c
AM		 8617 if (*c == '3')
8618 {
8619 int count = given & 0xff;
b34976b6 8620
dffaa15c
AM		 8621 if (single == 0)
8622 count >>= 1;
0313a2b8 8623
dffaa15c
AM		 8624 if (--count)
8625 {
8626 func (stream, "-%c%d",
8627 single ? 's' : 'd',
8628 regno + count);
8629 }
0313a2b8 8630
dffaa15c 8631 func (stream, "}");
0313a2b8 8632 }
dffaa15c
AM		 8633 else if (*c == '4')
8634 func (stream, ", %c%d", single ? 's' : 'd',
8635 regno + 1);
8636 }
8637 break;
b34976b6 8638
dffaa15c
AM		 8639 case 'L':
8640 switch (given & 0x00400100)
0313a2b8 8641 {
dffaa15c
AM		 8642 case 0x00000000: func (stream, "b"); break;
8643 case 0x00400000: func (stream, "h"); break;
8644 case 0x00000100: func (stream, "w"); break;
8645 case 0x00400100: func (stream, "d"); break;
8646 default:
8647 break;
0313a2b8 8648 }
dffaa15c 8649 break;
2d447fca 8650
dffaa15c
AM		 8651 case 'Z':
8652 {
8653 /* given (20, 23) | given (0, 3) */
8654 value = ((given >> 16) & 0xf0) | (given & 0xf);
8655 func (stream, "%d", (int) value);
8656 }
8657 break;
0313a2b8 8658
dffaa15c
AM		 8659 case 'l':
8660 /* This is like the 'A' operator, except that if
8661 the width field "M" is zero, then the offset is
8662 *not* multiplied by four. */
8663 {
8664 int offset = given & 0xff;
8665 int multiplier = (given & 0x00000100) ? 4 : 1;
0313a2b8 8666
dffaa15c 8667 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
05413229 8668
dffaa15c
AM		 8669 if (multiplier > 1)
8670 {
8671 value_in_comment = offset * multiplier;
8672 if (NEGATIVE_BIT_SET)
8673 value_in_comment = - value_in_comment;
8674 }
0313a2b8 8675
dffaa15c
AM		 8676 if (offset)
8677 {
8678 if (PRE_BIT_SET)
8679 func (stream, ", #%s%d]%s",
8680 NEGATIVE_BIT_SET ? "-" : "",
8681 offset * multiplier,
8682 WRITEBACK_BIT_SET ? "!" : "");
8683 else
8684 func (stream, "], #%s%d",
8685 NEGATIVE_BIT_SET ? "-" : "",
8686 offset * multiplier);
8687 }
8688 else
8689 func (stream, "]");
8690 }
8691 break;
2d447fca 8692
dffaa15c
AM		 8693 case 'r':
8694 {
8695 int imm4 = (given >> 4) & 0xf;
8696 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
8697 int ubit = ! NEGATIVE_BIT_SET;
8698 const char *rm = arm_regnames [given & 0xf];
8699 const char *rn = arm_regnames [(given >> 16) & 0xf];
0313a2b8 8700
dffaa15c
AM		 8701 switch (puw_bits)
8702 {
8703 case 1:
8704 case 3:
8705 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
8706 if (imm4)
8707 func (stream, ", lsl #%d", imm4);
8708 break;
0313a2b8 8709
dffaa15c
AM		 8710 case 4:
8711 case 5:
8712 case 6:
8713 case 7:
8714 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
8715 if (imm4 > 0)
8716 func (stream, ", lsl #%d", imm4);
8717 func (stream, "]");
8718 if (puw_bits == 5 || puw_bits == 7)
8719 func (stream, "!");
8720 break;
2d447fca 8721
dffaa15c
AM		 8722 default:
8723 func (stream, "INVALID");
8724 }
8725 }
8726 break;
0313a2b8 8727
dffaa15c
AM		 8728 case 'i':
8729 {
8730 long imm5;
8731 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8732 func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
0313a2b8 8733 }
dffaa15c
AM		 8734 break;
8735
8736 default:
8737 abort ();
252b5132 8738 }
252b5132 8739 }
0313a2b8
NC		 8740 else
8741 func (stream, "%c", *c);
252b5132 8742 }
05413229
NC		 8743
8744 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 8745 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
05413229 8746
ff4a8d2b
NC		 8747 if (is_unpredictable)
8748 func (stream, UNPREDICTABLE_INSTRUCTION);
8749
0313a2b8 8750 return TRUE;
252b5132 8751 }
8f06b2d8 8752 return FALSE;
252b5132
RH		 8753}
8754
33593eaf
MM		 8755static bfd_boolean
8756print_insn_coprocessor (bfd_vma pc,
8757 struct disassemble_info *info,
8758 long given,
8759 bfd_boolean thumb)
8760{
8761 return print_insn_coprocessor_1 (coprocessor_opcodes,
8762 pc, info, given, thumb);
8763}
8764
8765static bfd_boolean
8766print_insn_generic_coprocessor (bfd_vma pc,
8767 struct disassemble_info *info,
8768 long given,
8769 bfd_boolean thumb)
8770{
8771 return print_insn_coprocessor_1 (generic_coprocessor_opcodes,
8772 pc, info, given, thumb);
8773}
8774
05413229
NC		 8775/* Decodes and prints ARM addressing modes. Returns the offset
8776 used in the address, if any, if it is worthwhile printing the
8777 offset as a hexadecimal value in a comment at the end of the
8778 line of disassembly. */
8779
8780static signed long
62b3e311
PB		 8781print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
8782{
8783 void *stream = info->stream;
8784 fprintf_ftype func = info->fprintf_func;
f8b960bc 8785 bfd_vma offset = 0;
62b3e311
PB		 8786
8787 if (((given & 0x000f0000) == 0x000f0000)
8788 && ((given & 0x02000000) == 0))
8789 {
05413229 8790 offset = given & 0xfff;
62b3e311
PB		 8791
8792 func (stream, "[pc");
8793
c1e26897 8794 if (PRE_BIT_SET)
62b3e311 8795 {
26d97720
NS		 8796 /* Pre-indexed. Elide offset of positive zero when
8797 non-writeback. */
8798 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8799 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
26d97720
NS		 8800
8801 if (NEGATIVE_BIT_SET)
8802 offset = -offset;
62b3e311
PB		 8803
8804 offset += pc + 8;
8805
8806 /* Cope with the possibility of write-back
8807 being used. Probably a very dangerous thing
8808 for the programmer to do, but who are we to
8809 argue ? */
26d97720 8810 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
62b3e311 8811 }
c1e26897 8812 else /* Post indexed. */
62b3e311 8813 {
d908c8af 8814 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311 8815
c1e26897 8816 /* Ie ignore the offset. */
62b3e311
PB		 8817 offset = pc + 8;
8818 }
8819
8820 func (stream, "\t; ");
8821 info->print_address_func (offset, info);
05413229 8822 offset = 0;
62b3e311
PB		 8823 }
8824 else
8825 {
8826 func (stream, "[%s",
8827 arm_regnames[(given >> 16) & 0xf]);
c1e26897
NC		 8828
8829 if (PRE_BIT_SET)
62b3e311
PB		 8830 {
8831 if ((given & 0x02000000) == 0)
8832 {
26d97720 8833 /* Elide offset of positive zero when non-writeback. */
05413229 8834 offset = given & 0xfff;
26d97720 8835 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
d908c8af 8836 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8837 }
8838 else
8839 {
26d97720 8840 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8841 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8842 }
8843
8844 func (stream, "]%s",
c1e26897 8845 WRITEBACK_BIT_SET ? "!" : "");
62b3e311
PB		 8846 }
8847 else
8848 {
8849 if ((given & 0x02000000) == 0)
8850 {
26d97720 8851 /* Always show offset. */
05413229 8852 offset = given & 0xfff;
26d97720 8853 func (stream, "], #%s%d",
d908c8af 8854 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
62b3e311
PB		 8855 }
8856 else
8857 {
8858 func (stream, "], %s",
c1e26897 8859 NEGATIVE_BIT_SET ? "-" : "");
78c66db8 8860 arm_decode_shift (given, func, stream, TRUE);
62b3e311
PB		 8861 }
8862 }
84919466
MR		 8863 if (NEGATIVE_BIT_SET)
8864 offset = -offset;
62b3e311 8865 }
05413229
NC		 8866
8867 return (signed long) offset;
62b3e311
PB		 8868}
8869
4934a27c
MM		 8870
8871/* Print one cde instruction on INFO->STREAM.
8872 Return TRUE if the instuction matched, FALSE if this is not a
8873 recognised cde instruction. */
8874static bfd_boolean
8875print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb)
8876{
8877 const struct cdeopcode32 *insn;
8878 void *stream = info->stream;
8879 fprintf_ftype func = info->fprintf_func;
8880
8881 if (thumb)
8882 {
8883 /* Manually extract the coprocessor code from a known point.
8884 This position is the same across all CDE instructions. */
8885 for (insn = cde_opcodes; insn->assembler; insn++)
8886 {
8887 uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask;
8888 uint16_t coproc_mask = 1 << coproc;
8889 if (! (coproc_mask & cde_coprocs))
8890 continue;
8891
8892 if ((given & insn->mask) == insn->value)
8893 {
8894 bfd_boolean is_unpredictable = FALSE;
8895 const char *c;
8896
8897 for (c = insn->assembler; *c; c++)
8898 {
8899 if (*c == '%')
8900 {
8901 switch (*++c)
8902 {
8903 case '%':
8904 func (stream, "%%");
8905 break;
8906
8907 case '0': case '1': case '2': case '3': case '4':
8908 case '5': case '6': case '7': case '8': case '9':
8909 {
8910 int width;
8911 unsigned long value;
8912
8913 c = arm_decode_bitfield (c, given, &value, &width);
8914
8915 switch (*c)
8916 {
8917 case 'S':
8918 if (value > 10)
8919 is_unpredictable = TRUE;
8920 /* Fall through. */
8921 case 'R':
8922 if (value == 13)
8923 is_unpredictable = TRUE;
8924 /* Fall through. */
8925 case 'r':
8926 func (stream, "%s", arm_regnames[value]);
8927 break;
8928
8929 case 'n':
8930 if (value == 15)
8931 func (stream, "%s", "APSR_nzcv");
8932 else
8933 func (stream, "%s", arm_regnames[value]);
8934 break;
8935
8936 case 'T':
8937 func (stream, "%s", arm_regnames[value + 1]);
8938 break;
8939
8940 case 'd':
8941 func (stream, "%ld", value);
8942 break;
8943
5aae9ae9
MM		 8944 case 'V':
8945 if (given & (1 << 6))
8946 func (stream, "q%ld", value >> 1);
8947 else if (given & (1 << 24))
8948 func (stream, "d%ld", value);
8949 else
8950 {
8951 /* Encoding for S register is different than for D and
8952 Q registers. S registers are encoded using the top
8953 single bit in position 22 as the lowest bit of the
8954 register number, while for Q and D it represents the
8955 highest bit of the register number. */
8956 uint8_t top_bit = (value >> 4) & 1;
8957 uint8_t tmp = (value << 1) & 0x1e;
8958 uint8_t res = tmp | top_bit;
8959 func (stream, "s%u", res);
8960 }
8961 break;
8962
4934a27c
MM		 8963 default:
8964 abort ();
8965 }
8966 }
8967 break;
8968
8969 case 'p':
8970 {
8971 uint8_t proc_number = (given >> 8) & 0x7;
8972 func (stream, "p%u", proc_number);
8973 break;
8974 }
8975
8976 case 'a':
8977 {
8978 uint8_t a_offset = 28;
8979 if (given & (1 << a_offset))
8980 func (stream, "a");
8981 break;
8982 }
8983 default:
8984 abort ();
8985 }
8986 }
8987 else
8988 func (stream, "%c", *c);
8989 }
8990
8991 if (is_unpredictable)
8992 func (stream, UNPREDICTABLE_INSTRUCTION);
8993
8994 return TRUE;
8995 }
8996 }
8997 return FALSE;
8998 }
8999 else
9000 return FALSE;
9001}
9002
9003
16980d0b
JB		 9004/* Print one neon instruction on INFO->STREAM.
9005 Return TRUE if the instuction matched, FALSE if this is not a
9006 recognised neon instruction. */
9007
9008static bfd_boolean
9009print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
9010{
9011 const struct opcode32 *insn;
9012 void *stream = info->stream;
9013 fprintf_ftype func = info->fprintf_func;
9014
9015 if (thumb)
9016 {
9017 if ((given & 0xef000000) == 0xef000000)
9018 {
0313a2b8 9019 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
16980d0b
JB		 9020 unsigned long bit28 = given & (1 << 28);
9021
9022 given &= 0x00ffffff;
9023 if (bit28)
9024 given |= 0xf3000000;
9025 else
9026 given |= 0xf2000000;
9027 }
9028 else if ((given & 0xff000000) == 0xf9000000)
9029 given ^= 0xf9000000 ^ 0xf4000000;
aab2c27d
MM		 9030 /* BFloat16 neon instructions without special top byte handling. */
9031 else if ((given & 0xff000000) == 0xfe000000
9032 || (given & 0xff000000) == 0xfc000000)
9033 ;
9743db03 9034 /* vdup is also a valid neon instruction. */
e409955d 9035 else if ((given & 0xff900f5f) != 0xee800b10)
16980d0b
JB		 9036 return FALSE;
9037 }
43e65147 9038
16980d0b
JB		 9039 for (insn = neon_opcodes; insn->assembler; insn++)
9040 {
e409955d
FS		 9041 unsigned long cond_mask = insn->mask;
9042 unsigned long cond_value = insn->value;
9043 int cond;
9044
9045 if (thumb)
9046 {
9047 if ((cond_mask & 0xf0000000) == 0) {
9048 /* For the entries in neon_opcodes, an opcode mask/value with
9049 the high 4 bits equal to 0 indicates a conditional
9050 instruction. For thumb however, we need to include those
9051 bits in the instruction matching. */
9052 cond_mask |= 0xf0000000;
9053 /* Furthermore, the thumb encoding of a conditional instruction
9054 will have the high 4 bits equal to 0xe. */
9055 cond_value |= 0xe0000000;
9056 }
9057 if (ifthen_state)
9058 cond = IFTHEN_COND;
9059 else
9060 cond = COND_UNCOND;
9061 }
9062 else
9063 {
9064 if ((given & 0xf0000000) == 0xf0000000)
9065 {
9066 /* If the instruction is unconditional, update the mask to only
9067 match against unconditional opcode values. */
9068 cond_mask |= 0xf0000000;
9069 cond = COND_UNCOND;
9070 }
9071 else
9072 {
9073 cond = (given >> 28) & 0xf;
9074 if (cond == 0xe)
9075 cond = COND_UNCOND;
9076 }
9077 }
9078
9079 if ((given & cond_mask) == cond_value)
16980d0b 9080 {
05413229 9081 signed long value_in_comment = 0;
e2efe87d 9082 bfd_boolean is_unpredictable = FALSE;
16980d0b
JB		 9083 const char *c;
9084
9085 for (c = insn->assembler; *c; c++)
9086 {
9087 if (*c == '%')
9088 {
9089 switch (*++c)
9090 {
9091 case '%':
9092 func (stream, "%%");
9093 break;
9094
e2efe87d
MGD		 9095 case 'u':
9096 if (thumb && ifthen_state)
9097 is_unpredictable = TRUE;
9098
9099 /* Fall through. */
c22aaad1 9100 case 'c':
e409955d 9101 func (stream, "%s", arm_conditional[cond]);
c22aaad1
PB		 9102 break;
9103
16980d0b
JB		 9104 case 'A':
9105 {
43e65147 9106 static const unsigned char enc[16] =
16980d0b
JB		 9107 {
9108 0x4, 0x14, /* st4 0,1 */
9109 0x4, /* st1 2 */
9110 0x4, /* st2 3 */
9111 0x3, /* st3 4 */
9112 0x13, /* st3 5 */
9113 0x3, /* st1 6 */
9114 0x1, /* st1 7 */
9115 0x2, /* st2 8 */
9116 0x12, /* st2 9 */
9117 0x2, /* st1 10 */
9118 0, 0, 0, 0, 0
9119 };
9120 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9121 int rn = ((given >> 16) & 0xf);
9122 int rm = ((given >> 0) & 0xf);
9123 int align = ((given >> 4) & 0x3);
9124 int type = ((given >> 8) & 0xf);
9125 int n = enc[type] & 0xf;
9126 int stride = (enc[type] >> 4) + 1;
9127 int ix;
43e65147 9128
16980d0b
JB		 9129 func (stream, "{");
9130 if (stride > 1)
9131 for (ix = 0; ix != n; ix++)
9132 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
9133 else if (n == 1)
9134 func (stream, "d%d", rd);
9135 else
9136 func (stream, "d%d-d%d", rd, rd + n - 1);
9137 func (stream, "}, [%s", arm_regnames[rn]);
9138 if (align)
8e560766 9139 func (stream, " :%d", 32 << align);
16980d0b
JB		 9140 func (stream, "]");
9141 if (rm == 0xd)
9142 func (stream, "!");
9143 else if (rm != 0xf)
9144 func (stream, ", %s", arm_regnames[rm]);
9145 }
9146 break;
43e65147 9147
16980d0b
JB		 9148 case 'B':
9149 {
9150 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9151 int rn = ((given >> 16) & 0xf);
9152 int rm = ((given >> 0) & 0xf);
9153 int idx_align = ((given >> 4) & 0xf);
9154 int align = 0;
9155 int size = ((given >> 10) & 0x3);
9156 int idx = idx_align >> (size + 1);
9157 int length = ((given >> 8) & 3) + 1;
9158 int stride = 1;
9159 int i;
9160
9161 if (length > 1 && size > 0)
9162 stride = (idx_align & (1 << size)) ? 2 : 1;
43e65147 9163
16980d0b
JB		 9164 switch (length)
9165 {
9166 case 1:
9167 {
9168 int amask = (1 << size) - 1;
9169 if ((idx_align & (1 << size)) != 0)
9170 return FALSE;
9171 if (size > 0)
9172 {
9173 if ((idx_align & amask) == amask)
9174 align = 8 << size;
9175 else if ((idx_align & amask) != 0)
9176 return FALSE;
9177 }
9178 }
9179 break;
43e65147 9180
16980d0b
JB		 9181 case 2:
9182 if (size == 2 && (idx_align & 2) != 0)
9183 return FALSE;
9184 align = (idx_align & 1) ? 16 << size : 0;
9185 break;
43e65147 9186
16980d0b
JB		 9187 case 3:
9188 if ((size == 2 && (idx_align & 3) != 0)
9189 || (idx_align & 1) != 0)
9190 return FALSE;
9191 break;
43e65147 9192
16980d0b
JB		 9193 case 4:
9194 if (size == 2)
9195 {
9196 if ((idx_align & 3) == 3)
9197 return FALSE;
9198 align = (idx_align & 3) * 64;
9199 }
9200 else
9201 align = (idx_align & 1) ? 32 << size : 0;
9202 break;
43e65147 9203
16980d0b
JB		 9204 default:
9205 abort ();
9206 }
43e65147 9207
16980d0b
JB		 9208 func (stream, "{");
9209 for (i = 0; i < length; i++)
9210 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
9211 rd + i * stride, idx);
9212 func (stream, "}, [%s", arm_regnames[rn]);
9213 if (align)
8e560766 9214 func (stream, " :%d", align);
16980d0b
JB		 9215 func (stream, "]");
9216 if (rm == 0xd)
9217 func (stream, "!");
9218 else if (rm != 0xf)
9219 func (stream, ", %s", arm_regnames[rm]);
9220 }
9221 break;
43e65147 9222
16980d0b
JB		 9223 case 'C':
9224 {
9225 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
9226 int rn = ((given >> 16) & 0xf);
9227 int rm = ((given >> 0) & 0xf);
9228 int align = ((given >> 4) & 0x1);
9229 int size = ((given >> 6) & 0x3);
9230 int type = ((given >> 8) & 0x3);
9231 int n = type + 1;
9232 int stride = ((given >> 5) & 0x1);
9233 int ix;
43e65147 9234
16980d0b
JB		 9235 if (stride && (n == 1))
9236 n++;
9237 else
9238 stride++;
43e65147 9239
16980d0b
JB		 9240 func (stream, "{");
9241 if (stride > 1)
9242 for (ix = 0; ix != n; ix++)
9243 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
9244 else if (n == 1)
9245 func (stream, "d%d[]", rd);
9246 else
9247 func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
9248 func (stream, "}, [%s", arm_regnames[rn]);
9249 if (align)
9250 {
91d6fa6a 9251 align = (8 * (type + 1)) << size;
16980d0b
JB		 9252 if (type == 3)
9253 align = (size > 1) ? align >> 1 : align;
9254 if (type == 2 || (type == 0 && !size))
8e560766 9255 func (stream, " :<bad align %d>", align);
16980d0b 9256 else
8e560766 9257 func (stream, " :%d", align);
16980d0b
JB		 9258 }
9259 func (stream, "]");
9260 if (rm == 0xd)
9261 func (stream, "!");
9262 else if (rm != 0xf)
9263 func (stream, ", %s", arm_regnames[rm]);
9264 }
9265 break;
43e65147 9266
16980d0b
JB		 9267 case 'D':
9268 {
9269 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
9270 int size = (given >> 20) & 3;
9271 int reg = raw_reg & ((4 << size) - 1);
9272 int ix = raw_reg >> size >> 2;
43e65147 9273
16980d0b
JB		 9274 func (stream, "d%d[%d]", reg, ix);
9275 }
9276 break;
43e65147 9277
16980d0b 9278 case 'E':
fe56b6ce 9279 /* Neon encoded constant for mov, mvn, vorr, vbic. */
16980d0b
JB		 9280 {
9281 int bits = 0;
9282 int cmode = (given >> 8) & 0xf;
9283 int op = (given >> 5) & 0x1;
9284 unsigned long value = 0, hival = 0;
9285 unsigned shift;
9286 int size = 0;
0dbde4cf 9287 int isfloat = 0;
43e65147 9288
16980d0b
JB		 9289 bits |= ((given >> 24) & 1) << 7;
9290 bits |= ((given >> 16) & 7) << 4;
9291 bits |= ((given >> 0) & 15) << 0;
43e65147 9292
16980d0b
JB		 9293 if (cmode < 8)
9294 {
9295 shift = (cmode >> 1) & 3;
fe56b6ce 9296 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9297 size = 32;
9298 }
9299 else if (cmode < 12)
9300 {
9301 shift = (cmode >> 1) & 1;
fe56b6ce 9302 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9303 size = 16;
9304 }
9305 else if (cmode < 14)
9306 {
9307 shift = (cmode & 1) + 1;
fe56b6ce 9308 value = (unsigned long) bits << (8 * shift);
16980d0b
JB		 9309 value |= (1ul << (8 * shift)) - 1;
9310 size = 32;
9311 }
9312 else if (cmode == 14)
9313 {
9314 if (op)
9315 {
fe56b6ce 9316 /* Bit replication into bytes. */
16980d0b
JB		 9317 int ix;
9318 unsigned long mask;
43e65147 9319
16980d0b
JB		 9320 value = 0;
9321 hival = 0;
9322 for (ix = 7; ix >= 0; ix--)
9323 {
9324 mask = ((bits >> ix) & 1) ? 0xff : 0;
9325 if (ix <= 3)
9326 value = (value << 8) | mask;
9327 else
9328 hival = (hival << 8) | mask;
9329 }
9330 size = 64;
9331 }
9332 else
9333 {
fe56b6ce
NC		 9334 /* Byte replication. */
9335 value = (unsigned long) bits;
16980d0b
JB		 9336 size = 8;
9337 }
9338 }
9339 else if (!op)
9340 {
fe56b6ce 9341 /* Floating point encoding. */
16980d0b 9342 int tmp;
43e65147 9343
fe56b6ce
NC		 9344 value = (unsigned long) (bits & 0x7f) << 19;
9345 value |= (unsigned long) (bits & 0x80) << 24;
16980d0b 9346 tmp = bits & 0x40 ? 0x3c : 0x40;
fe56b6ce 9347 value |= (unsigned long) tmp << 24;
16980d0b 9348 size = 32;
0dbde4cf 9349 isfloat = 1;
16980d0b
JB		 9350 }
9351 else
9352 {
9353 func (stream, "<illegal constant %.8x:%x:%x>",
9354 bits, cmode, op);
9355 size = 32;
9356 break;
9357 }
9358 switch (size)
9359 {
9360 case 8:
9361 func (stream, "#%ld\t; 0x%.2lx", value, value);
9362 break;
43e65147 9363
16980d0b
JB		 9364 case 16:
9365 func (stream, "#%ld\t; 0x%.4lx", value, value);
9366 break;
9367
9368 case 32:
0dbde4cf
JB		 9369 if (isfloat)
9370 {
9371 unsigned char valbytes[4];
9372 double fvalue;
43e65147 9373
0dbde4cf
JB		 9374 /* Do this a byte at a time so we don't have to
9375 worry about the host's endianness. */
9376 valbytes[0] = value & 0xff;
9377 valbytes[1] = (value >> 8) & 0xff;
9378 valbytes[2] = (value >> 16) & 0xff;
9379 valbytes[3] = (value >> 24) & 0xff;
43e65147
L		 9380
9381 floatformat_to_double
c1e26897
NC		 9382 (& floatformat_ieee_single_little, valbytes,
9383 & fvalue);
43e65147 9384
0dbde4cf
JB		 9385 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
9386 value);
9387 }
9388 else
4e9d3b81 9389 func (stream, "#%ld\t; 0x%.8lx",
43e65147 9390 (long) (((value & 0x80000000L) != 0)
9d82ec38 9391 ? value | ~0xffffffffL : value),
c1e26897 9392 value);
16980d0b
JB		 9393 break;
9394
9395 case 64:
9396 func (stream, "#0x%.8lx%.8lx", hival, value);
9397 break;
43e65147 9398
16980d0b
JB		 9399 default:
9400 abort ();
9401 }
9402 }
9403 break;
43e65147 9404
16980d0b
JB		 9405 case 'F':
9406 {
9407 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
9408 int num = (given >> 8) & 0x3;
43e65147 9409
16980d0b
JB		 9410 if (!num)
9411 func (stream, "{d%d}", regno);
9412 else if (num + regno >= 32)
9413 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
9414 else
9415 func (stream, "{d%d-d%d}", regno, regno + num);
9416 }
9417 break;
7e8e6784 9418
16980d0b
JB		 9419
9420 case '0': case '1': case '2': case '3': case '4':
9421 case '5': case '6': case '7': case '8': case '9':
9422 {
9423 int width;
9424 unsigned long value;
9425
9426 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 9427
16980d0b
JB		 9428 switch (*c)
9429 {
9430 case 'r':
9431 func (stream, "%s", arm_regnames[value]);
9432 break;
9433 case 'd':
9434 func (stream, "%ld", value);
05413229 9435 value_in_comment = value;
16980d0b
JB		 9436 break;
9437 case 'e':
9438 func (stream, "%ld", (1ul << width) - value);
9439 break;
43e65147 9440
16980d0b
JB		 9441 case 'S':
9442 case 'T':
9443 case 'U':
05413229 9444 /* Various width encodings. */
16980d0b
JB		 9445 {
9446 int base = 8 << (*c - 'S'); /* 8,16 or 32 */
9447 int limit;
9448 unsigned low, high;
9449
9450 c++;
9451 if (*c >= '0' && *c <= '9')
9452 limit = *c - '0';
9453 else if (*c >= 'a' && *c <= 'f')
9454 limit = *c - 'a' + 10;
9455 else
9456 abort ();
9457 low = limit >> 2;
9458 high = limit & 3;
9459
9460 if (value < low || value > high)
9461 func (stream, "<illegal width %d>", base << value);
9462 else
9463 func (stream, "%d", base << value);
9464 }
9465 break;
9466 case 'R':
9467 if (given & (1 << 6))
9468 goto Q;
9469 /* FALLTHROUGH */
9470 case 'D':
9471 func (stream, "d%ld", value);
9472 break;
9473 case 'Q':
9474 Q:
9475 if (value & 1)
9476 func (stream, "<illegal reg q%ld.5>", value >> 1);
9477 else
9478 func (stream, "q%ld", value >> 1);
9479 break;
43e65147 9480
16980d0b
JB		 9481 case '`':
9482 c++;
9483 if (value == 0)
9484 func (stream, "%c", *c);
9485 break;
9486 case '\'':
9487 c++;
9488 if (value == ((1ul << width) - 1))
9489 func (stream, "%c", *c);
9490 break;
9491 case '?':
fe56b6ce 9492 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b
JB		 9493 c += 1 << width;
9494 break;
9495 default:
9496 abort ();
9497 }
16980d0b 9498 }
dffaa15c
AM		 9499 break;
9500
9501 default:
9502 abort ();
16980d0b
JB		 9503 }
9504 }
9505 else
9506 func (stream, "%c", *c);
9507 }
05413229
NC		 9508
9509 if (value_in_comment > 32 || value_in_comment < -16)
9510 func (stream, "\t; 0x%lx", value_in_comment);
9511
e2efe87d
MGD		 9512 if (is_unpredictable)
9513 func (stream, UNPREDICTABLE_INSTRUCTION);
9514
16980d0b
JB		 9515 return TRUE;
9516 }
9517 }
9518 return FALSE;
9519}
9520
73cd51e5
AV		 9521/* Print one mve instruction on INFO->STREAM.
9522 Return TRUE if the instuction matched, FALSE if this is not a
9523 recognised mve instruction. */
9524
9525static bfd_boolean
9526print_insn_mve (struct disassemble_info *info, long given)
9527{
9528 const struct mopcode32 *insn;
9529 void *stream = info->stream;
9530 fprintf_ftype func = info->fprintf_func;
9531
9532 for (insn = mve_opcodes; insn->assembler; insn++)
9533 {
9534 if (((given & insn->mask) == insn->value)
9535 && !is_mve_encoding_conflict (given, insn->mve_op))
9536 {
9537 signed long value_in_comment = 0;
9538 bfd_boolean is_unpredictable = FALSE;
9539 bfd_boolean is_undefined = FALSE;
9540 const char *c;
9541 enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
9542 enum mve_undefined undefined_cond = UNDEF_NONE;
9543
9544 /* Most vector mve instruction are illegal in a it block.
9545 There are a few exceptions; check for them. */
9546 if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
9547 {
9548 is_unpredictable = TRUE;
9549 unpredictable_cond = UNPRED_IT_BLOCK;
9550 }
9551 else if (is_mve_unpredictable (given, insn->mve_op,
9552 &unpredictable_cond))
9553 is_unpredictable = TRUE;
9554
9555 if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
9556 is_undefined = TRUE;
9557
c4a23bf8
SP		 9558 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9559 i.e "VMOV Qd, Qm". */
9560 if ((insn->mve_op == MVE_VORR_REG)
9561 && (arm_decode_field (given, 1, 3)
9562 == arm_decode_field (given, 17, 19)))
9563 continue;
9564
73cd51e5
AV		 9565 for (c = insn->assembler; *c; c++)
9566 {
9567 if (*c == '%')
9568 {
9569 switch (*++c)
9570 {
9571 case '%':
9572 func (stream, "%%");
9573 break;
9574
ef1576a1
AV		 9575 case 'a':
9576 /* Don't print anything for '+' as it is implied. */
9577 if (arm_decode_field (given, 23, 23) == 0)
9578 func (stream, "-");
9579 break;
9580
143275ea
AV		 9581 case 'c':
9582 if (ifthen_state)
9583 func (stream, "%s", arm_conditional[IFTHEN_COND]);
9584 break;
9585
aef6d006
AV		 9586 case 'd':
9587 print_mve_vld_str_addr (info, given, insn->mve_op);
9588 break;
9589
143275ea
AV		 9590 case 'i':
9591 {
9592 long mve_mask = mve_extract_pred_mask (given);
9593 func (stream, "%s", mve_predicatenames[mve_mask]);
9594 }
9595 break;
9596
23d00a41
SD		 9597 case 'j':
9598 {
9599 unsigned int imm5 = 0;
9600 imm5 |= arm_decode_field (given, 6, 7);
9601 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9602 func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
9603 }
9604 break;
9605
08132bdd
SP		 9606 case 'k':
9607 func (stream, "#%u",
9608 (arm_decode_field (given, 7, 7) == 0) ? 64 : 48);
9609 break;
9610
143275ea
AV		 9611 case 'n':
9612 print_vec_condition (info, given, insn->mve_op);
9613 break;
9614
ef1576a1
AV		 9615 case 'o':
9616 if (arm_decode_field (given, 0, 0) == 1)
9617 {
9618 unsigned long size
9619 = arm_decode_field (given, 4, 4)
9620 | (arm_decode_field (given, 6, 6) << 1);
9621
9622 func (stream, ", uxtw #%lu", size);
9623 }
9624 break;
9625
bf0b396d
AV		 9626 case 'm':
9627 print_mve_rounding_mode (info, given, insn->mve_op);
9628 break;
9629
9630 case 's':
9631 print_mve_vcvt_size (info, given, insn->mve_op);
9632 break;
9633
aef6d006
AV		 9634 case 'u':
9635 {
c507f10b
AV		 9636 unsigned long op1 = arm_decode_field (given, 21, 22);
9637
9638 if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP))
9639 {
9640 /* Check for signed. */
9641 if (arm_decode_field (given, 23, 23) == 0)
9642 {
9643 /* We don't print 's' for S32. */
9644 if ((arm_decode_field (given, 5, 6) == 0)
9645 && ((op1 == 0) || (op1 == 1)))
9646 ;
9647 else
9648 func (stream, "s");
9649 }
9650 else
9651 func (stream, "u");
9652 }
aef6d006 9653 else
c507f10b
AV		 9654 {
9655 if (arm_decode_field (given, 28, 28) == 0)
9656 func (stream, "s");
9657 else
9658 func (stream, "u");
9659 }
aef6d006 9660 }
ef1576a1 9661 break;
aef6d006 9662
143275ea
AV		 9663 case 'v':
9664 print_instruction_predicate (info);
9665 break;
9666
04d54ace
AV		 9667 case 'w':
9668 if (arm_decode_field (given, 21, 21) == 1)
9669 func (stream, "!");
9670 break;
9671
9672 case 'B':
9673 print_mve_register_blocks (info, given, insn->mve_op);
9674 break;
9675
c507f10b
AV		 9676 case 'E':
9677 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9678
9679 print_simd_imm8 (info, given, 28, insn);
9680 break;
9681
9682 case 'N':
9683 print_mve_vmov_index (info, given);
9684 break;
9685
14925797
AV		 9686 case 'T':
9687 if (arm_decode_field (given, 12, 12) == 0)
9688 func (stream, "b");
9689 else
9690 func (stream, "t");
9691 break;
9692
d3b63143
AV		 9693 case 'X':
9694 if (arm_decode_field (given, 12, 12) == 1)
9695 func (stream, "x");
9696 break;
9697
143275ea
AV		 9698 case '0': case '1': case '2': case '3': case '4':
9699 case '5': case '6': case '7': case '8': case '9':
9700 {
9701 int width;
9702 unsigned long value;
9703
9704 c = arm_decode_bitfield (c, given, &value, &width);
9705
9706 switch (*c)
9707 {
9708 case 'Z':
9709 if (value == 13)
9710 is_unpredictable = TRUE;
9711 else if (value == 15)
9712 func (stream, "zr");
9713 else
9714 func (stream, "%s", arm_regnames[value]);
9715 break;
23d00a41 9716
e39c1607
SD		 9717 case 'c':
9718 func (stream, "%s", arm_conditional[value]);
9719 break;
9720
9721 case 'C':
9722 value ^= 1;
9723 func (stream, "%s", arm_conditional[value]);
9724 break;
9725
23d00a41
SD		 9726 case 'S':
9727 if (value == 13 || value == 15)
9728 is_unpredictable = TRUE;
9729 else
9730 func (stream, "%s", arm_regnames[value]);
9731 break;
9732
143275ea
AV		 9733 case 's':
9734 print_mve_size (info,
9735 value,
9736 insn->mve_op);
9737 break;
66dcaa5d
AV		 9738 case 'I':
9739 if (value == 1)
9740 func (stream, "i");
9741 break;
d3b63143
AV		 9742 case 'A':
9743 if (value == 1)
9744 func (stream, "a");
9745 break;
1c8f2df8
AV		 9746 case 'h':
9747 {
9748 unsigned int odd_reg = (value << 1) | 1;
9749 func (stream, "%s", arm_regnames[odd_reg]);
9750 }
9751 break;
ef1576a1
AV		 9752 case 'i':
9753 {
9754 unsigned long imm
9755 = arm_decode_field (given, 0, 6);
9756 unsigned long mod_imm = imm;
9757
9758 switch (insn->mve_op)
9759 {
9760 case MVE_VLDRW_GATHER_T5:
9761 case MVE_VSTRW_SCATTER_T5:
9762 mod_imm = mod_imm << 2;
9763 break;
9764 case MVE_VSTRD_SCATTER_T6:
9765 case MVE_VLDRD_GATHER_T6:
9766 mod_imm = mod_imm << 3;
9767 break;
9768
9769 default:
9770 break;
9771 }
9772
9773 func (stream, "%lu", mod_imm);
9774 }
9775 break;
bf0b396d
AV		 9776 case 'k':
9777 func (stream, "%lu", 64 - value);
9778 break;
1c8f2df8
AV		 9779 case 'l':
9780 {
9781 unsigned int even_reg = value << 1;
9782 func (stream, "%s", arm_regnames[even_reg]);
9783 }
9784 break;
9785 case 'u':
9786 switch (value)
9787 {
9788 case 0:
9789 func (stream, "1");
9790 break;
9791 case 1:
9792 func (stream, "2");
9793 break;
9794 case 2:
9795 func (stream, "4");
9796 break;
9797 case 3:
9798 func (stream, "8");
9799 break;
9800 default:
9801 break;
9802 }
9803 break;
897b9bbc
AV		 9804 case 'o':
9805 print_mve_rotate (info, value, width);
9806 break;
9743db03
AV		 9807 case 'r':
9808 func (stream, "%s", arm_regnames[value]);
9809 break;
04d54ace 9810 case 'd':
ed63aa17
AV		 9811 if (insn->mve_op == MVE_VQSHL_T2
9812 || insn->mve_op == MVE_VQSHLU_T3
9813 || insn->mve_op == MVE_VRSHR
9814 || insn->mve_op == MVE_VRSHRN
9815 || insn->mve_op == MVE_VSHL_T1
9816 || insn->mve_op == MVE_VSHLL_T1
9817 || insn->mve_op == MVE_VSHR
9818 || insn->mve_op == MVE_VSHRN
9819 || insn->mve_op == MVE_VSLI
9820 || insn->mve_op == MVE_VSRI)
9821 print_mve_shift_n (info, given, insn->mve_op);
9822 else if (insn->mve_op == MVE_VSHLL_T2)
9823 {
9824 switch (value)
9825 {
9826 case 0x00:
9827 func (stream, "8");
9828 break;
9829 case 0x01:
9830 func (stream, "16");
9831 break;
9832 case 0x10:
9833 print_mve_undefined (info, UNDEF_SIZE_0);
9834 break;
9835 default:
9836 assert (0);
9837 break;
9838 }
9839 }
9840 else
9841 {
9842 if (insn->mve_op == MVE_VSHLC && value == 0)
9843 value = 32;
9844 func (stream, "%ld", value);
9845 value_in_comment = value;
9846 }
04d54ace 9847 break;
c507f10b
AV		 9848 case 'F':
9849 func (stream, "s%ld", value);
9850 break;
143275ea
AV		 9851 case 'Q':
9852 if (value & 0x8)
9853 func (stream, "<illegal reg q%ld.5>", value);
9854 else
9855 func (stream, "q%ld", value);
9856 break;
c507f10b
AV		 9857 case 'x':
9858 func (stream, "0x%08lx", value);
9859 break;
143275ea
AV		 9860 default:
9861 abort ();
9862 }
9863 break;
9864 default:
9865 abort ();
9866 }
73cd51e5
AV		 9867 }
9868 }
9869 else
9870 func (stream, "%c", *c);
9871 }
9872
9873 if (value_in_comment > 32 || value_in_comment < -16)
9874 func (stream, "\t; 0x%lx", value_in_comment);
9875
9876 if (is_unpredictable)
9877 print_mve_unpredictable (info, unpredictable_cond);
9878
9879 if (is_undefined)
9880 print_mve_undefined (info, undefined_cond);
9881
143275ea
AV		 9882 if ((vpt_block_state.in_vpt_block == FALSE)
9883 && !ifthen_state
9884 && (is_vpt_instruction (given) == TRUE))
9885 mark_inside_vpt_block (given);
9886 else if (vpt_block_state.in_vpt_block == TRUE)
9887 update_vpt_block_state ();
9888
73cd51e5
AV		 9889 return TRUE;
9890 }
9891 }
9892 return FALSE;
9893}
9894
9895
90ec0d68
MGD		 9896/* Return the name of a v7A special register. */
9897
43e65147 9898static const char *
90ec0d68
MGD		 9899banked_regname (unsigned reg)
9900{
9901 switch (reg)
9902 {
9903 case 15: return "CPSR";
43e65147 9904 case 32: return "R8_usr";
90ec0d68
MGD		 9905 case 33: return "R9_usr";
9906 case 34: return "R10_usr";
9907 case 35: return "R11_usr";
9908 case 36: return "R12_usr";
9909 case 37: return "SP_usr";
9910 case 38: return "LR_usr";
43e65147 9911 case 40: return "R8_fiq";
90ec0d68
MGD		 9912 case 41: return "R9_fiq";
9913 case 42: return "R10_fiq";
9914 case 43: return "R11_fiq";
9915 case 44: return "R12_fiq";
9916 case 45: return "SP_fiq";
9917 case 46: return "LR_fiq";
9918 case 48: return "LR_irq";
9919 case 49: return "SP_irq";
9920 case 50: return "LR_svc";
9921 case 51: return "SP_svc";
9922 case 52: return "LR_abt";
9923 case 53: return "SP_abt";
9924 case 54: return "LR_und";
9925 case 55: return "SP_und";
9926 case 60: return "LR_mon";
9927 case 61: return "SP_mon";
9928 case 62: return "ELR_hyp";
9929 case 63: return "SP_hyp";
9930 case 79: return "SPSR";
9931 case 110: return "SPSR_fiq";
9932 case 112: return "SPSR_irq";
9933 case 114: return "SPSR_svc";
9934 case 116: return "SPSR_abt";
9935 case 118: return "SPSR_und";
9936 case 124: return "SPSR_mon";
9937 case 126: return "SPSR_hyp";
9938 default: return NULL;
9939 }
9940}
9941
e797f7e0
MGD		 9942/* Return the name of the DMB/DSB option. */
9943static const char *
9944data_barrier_option (unsigned option)
9945{
9946 switch (option & 0xf)
9947 {
9948 case 0xf: return "sy";
9949 case 0xe: return "st";
9950 case 0xd: return "ld";
9951 case 0xb: return "ish";
9952 case 0xa: return "ishst";
9953 case 0x9: return "ishld";
9954 case 0x7: return "un";
9955 case 0x6: return "unst";
9956 case 0x5: return "nshld";
9957 case 0x3: return "osh";
9958 case 0x2: return "oshst";
9959 case 0x1: return "oshld";
9960 default: return NULL;
9961 }
9962}
9963
4a5329c6
ZW		 9964/* Print one ARM instruction from PC on INFO->STREAM. */
9965
9966static void
9967print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 9968{
6b5d3a4d 9969 const struct opcode32 *insn;
6a51a8a8 9970 void *stream = info->stream;
6b5d3a4d 9971 fprintf_ftype func = info->fprintf_func;
b0e28b39 9972 struct arm_private_data *private_data = info->private_data;
252b5132 9973
16980d0b
JB		 9974 if (print_insn_coprocessor (pc, info, given, FALSE))
9975 return;
9976
9977 if (print_insn_neon (info, given, FALSE))
8f06b2d8
PB		 9978 return;
9979
33593eaf
MM		 9980 if (print_insn_generic_coprocessor (pc, info, given, FALSE))
9981 return;
9982
252b5132
RH		 9983 for (insn = arm_opcodes; insn->assembler; insn++)
9984 {
0313a2b8
NC		 9985 if ((given & insn->mask) != insn->value)
9986 continue;
823d2571
TG		 9987
9988 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
0313a2b8
NC		 9989 continue;
9990
9991 /* Special case: an instruction with all bits set in the condition field
9992 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9993 or by the catchall at the end of the table. */
9994 if ((given & 0xF0000000) != 0xF0000000
9995 || (insn->mask & 0xF0000000) == 0xF0000000
9996 || (insn->mask == 0 && insn->value == 0))
252b5132 9997 {
ff4a8d2b
NC		 9998 unsigned long u_reg = 16;
9999 unsigned long U_reg = 16;
ab8e2090 10000 bfd_boolean is_unpredictable = FALSE;
05413229 10001 signed long value_in_comment = 0;
6b5d3a4d 10002 const char *c;
b34976b6 10003
252b5132
RH		 10004 for (c = insn->assembler; *c; c++)
10005 {
10006 if (*c == '%')
10007 {
c1e26897
NC		 10008 bfd_boolean allow_unpredictable = FALSE;
10009
252b5132
RH		 10010 switch (*++c)
10011 {
10012 case '%':
10013 func (stream, "%%");
10014 break;
10015
10016 case 'a':
05413229 10017 value_in_comment = print_arm_address (pc, info, given);
62b3e311 10018 break;
252b5132 10019
62b3e311
PB		 10020 case 'P':
10021 /* Set P address bit and use normal address
10022 printing routine. */
c1e26897 10023 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
252b5132
RH		 10024 break;
10025
c1e26897
NC		 10026 case 'S':
10027 allow_unpredictable = TRUE;
1a0670f3 10028 /* Fall through. */
252b5132
RH		 10029 case 's':
10030 if ((given & 0x004f0000) == 0x004f0000)
10031 {
58efb6c0 10032 /* PC relative with immediate offset. */
f8b960bc 10033 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
b34976b6 10034
aefd8a40
NC		 10035 if (PRE_BIT_SET)
10036 {
26d97720
NS		 10037 /* Elide positive zero offset. */
10038 if (offset || NEGATIVE_BIT_SET)
10039 func (stream, "[pc, #%s%d]\t; ",
d908c8af 10040 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
945ee430 10041 else
26d97720
NS		 10042 func (stream, "[pc]\t; ");
10043 if (NEGATIVE_BIT_SET)
10044 offset = -offset;
aefd8a40
NC		 10045 info->print_address_func (offset + pc + 8, info);
10046 }
10047 else
10048 {
26d97720
NS		 10049 /* Always show the offset. */
10050 func (stream, "[pc], #%s%d",
d908c8af 10051 NEGATIVE_BIT_SET ? "-" : "", (int) offset);
ff4a8d2b
NC		 10052 if (! allow_unpredictable)
10053 is_unpredictable = TRUE;
aefd8a40 10054 }
252b5132
RH		 10055 }
10056 else
10057 {
fe56b6ce
NC		 10058 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
10059
b34976b6 10060 func (stream, "[%s",
252b5132 10061 arm_regnames[(given >> 16) & 0xf]);
fe56b6ce 10062
c1e26897 10063 if (PRE_BIT_SET)
252b5132 10064 {
c1e26897 10065 if (IMMEDIATE_BIT_SET)
252b5132 10066 {
26d97720
NS		 10067 /* Elide offset for non-writeback
10068 positive zero. */
10069 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
10070 || offset)
10071 func (stream, ", #%s%d",
10072 NEGATIVE_BIT_SET ? "-" : "", offset);
10073
10074 if (NEGATIVE_BIT_SET)
10075 offset = -offset;
945ee430 10076
fe56b6ce 10077 value_in_comment = offset;
252b5132 10078 }
945ee430 10079 else
ff4a8d2b
NC		 10080 {
10081 /* Register Offset or Register Pre-Indexed. */
10082 func (stream, ", %s%s",
10083 NEGATIVE_BIT_SET ? "-" : "",
10084 arm_regnames[given & 0xf]);
10085
10086 /* Writing back to the register that is the source/
10087 destination of the load/store is unpredictable. */
10088 if (! allow_unpredictable
10089 && WRITEBACK_BIT_SET
10090 && ((given & 0xf) == ((given >> 12) & 0xf)))
10091 is_unpredictable = TRUE;
10092 }
252b5132 10093
b34976b6 10094 func (stream, "]%s",
c1e26897 10095 WRITEBACK_BIT_SET ? "!" : "");
252b5132 10096 }
945ee430 10097 else
252b5132 10098 {
c1e26897 10099 if (IMMEDIATE_BIT_SET)
252b5132 10100 {
945ee430 10101 /* Immediate Post-indexed. */
aefd8a40 10102 /* PR 10924: Offset must be printed, even if it is zero. */
26d97720
NS		 10103 func (stream, "], #%s%d",
10104 NEGATIVE_BIT_SET ? "-" : "", offset);
10105 if (NEGATIVE_BIT_SET)
10106 offset = -offset;
fe56b6ce 10107 value_in_comment = offset;
252b5132 10108 }
945ee430 10109 else
ff4a8d2b
NC		 10110 {
10111 /* Register Post-indexed. */
10112 func (stream, "], %s%s",
10113 NEGATIVE_BIT_SET ? "-" : "",
10114 arm_regnames[given & 0xf]);
10115
10116 /* Writing back to the register that is the source/
10117 destination of the load/store is unpredictable. */
10118 if (! allow_unpredictable
10119 && (given & 0xf) == ((given >> 12) & 0xf))
10120 is_unpredictable = TRUE;
10121 }
c1e26897 10122
07a28fab
NC		 10123 if (! allow_unpredictable)
10124 {
10125 /* Writeback is automatically implied by post- addressing.
10126 Setting the W bit is unnecessary and ARM specify it as
10127 being unpredictable. */
10128 if (WRITEBACK_BIT_SET
10129 /* Specifying the PC register as the post-indexed
10130 registers is also unpredictable. */
ab8e2090
NC		 10131 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
10132 is_unpredictable = TRUE;
07a28fab 10133 }
252b5132
RH		 10134 }
10135 }
10136 break;
b34976b6 10137
252b5132 10138 case 'b':
6b5d3a4d 10139 {
f8b960bc 10140 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
1d67fe3b
TT		 10141 bfd_vma target = disp * 4 + pc + 8;
10142 info->print_address_func (target, info);
10143
10144 /* Fill in instruction information. */
10145 info->insn_info_valid = 1;
10146 info->insn_type = dis_branch;
10147 info->target = target;
6b5d3a4d 10148 }
252b5132
RH		 10149 break;
10150
10151 case 'c':
c22aaad1
PB		 10152 if (((given >> 28) & 0xf) != 0xe)
10153 func (stream, "%s",
10154 arm_conditional [(given >> 28) & 0xf]);
252b5132
RH		 10155 break;
10156
10157 case 'm':
10158 {
10159 int started = 0;
10160 int reg;
10161
10162 func (stream, "{");
10163 for (reg = 0; reg < 16; reg++)
10164 if ((given & (1 << reg)) != 0)
10165 {
10166 if (started)
10167 func (stream, ", ");
10168 started = 1;
10169 func (stream, "%s", arm_regnames[reg]);
10170 }
10171 func (stream, "}");
ab8e2090
NC		 10172 if (! started)
10173 is_unpredictable = TRUE;
252b5132
RH		 10174 }
10175 break;
10176
37b37b2d 10177 case 'q':
78c66db8 10178 arm_decode_shift (given, func, stream, FALSE);
37b37b2d
RE		 10179 break;
10180
252b5132
RH		 10181 case 'o':
10182 if ((given & 0x02000000) != 0)
10183 {
a415b1cd
JB		 10184 unsigned int rotate = (given & 0xf00) >> 7;
10185 unsigned int immed = (given & 0xff);
10186 unsigned int a, i;
10187
ebd1c6d1
AM		 10188 a = (immed << ((32 - rotate) & 31)
10189 | immed >> rotate) & 0xffffffff;
a415b1cd
JB		 10190 /* If there is another encoding with smaller rotate,
10191 the rotate should be specified directly. */
10192 for (i = 0; i < 32; i += 2)
ebd1c6d1 10193 if ((a << i | a >> ((32 - i) & 31)) <= 0xff)
a415b1cd
JB		 10194 break;
10195
10196 if (i != rotate)
10197 func (stream, "#%d, %d", immed, rotate);
10198 else
10199 func (stream, "#%d", a);
10200 value_in_comment = a;
252b5132
RH		 10201 }
10202 else
78c66db8 10203 arm_decode_shift (given, func, stream, TRUE);
252b5132
RH		 10204 break;
10205
10206 case 'p':
10207 if ((given & 0x0000f000) == 0x0000f000)
aefd8a40 10208 {
823d2571
TG		 10209 arm_feature_set arm_ext_v6 =
10210 ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
10211
aefd8a40
NC		 10212 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10213 mechanism for setting PSR flag bits. They are
10214 obsolete in V6 onwards. */
823d2571
TG		 10215 if (! ARM_CPU_HAS_FEATURE (private_data->features, \
10216 arm_ext_v6))
aefd8a40 10217 func (stream, "p");
4ab90a7a
AV		 10218 else
10219 is_unpredictable = TRUE;
aefd8a40 10220 }
252b5132
RH		 10221 break;
10222
10223 case 't':
10224 if ((given & 0x01200000) == 0x00200000)
10225 func (stream, "t");
10226 break;
10227
252b5132 10228 case 'A':
05413229
NC		 10229 {
10230 int offset = given & 0xff;
f02232aa 10231
05413229 10232 value_in_comment = offset * 4;
c1e26897 10233 if (NEGATIVE_BIT_SET)
05413229 10234 value_in_comment = - value_in_comment;
f02232aa 10235
05413229 10236 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
f02232aa 10237
c1e26897 10238 if (PRE_BIT_SET)
05413229
NC		 10239 {
10240 if (offset)
fe56b6ce 10241 func (stream, ", #%d]%s",
d908c8af 10242 (int) value_in_comment,
c1e26897 10243 WRITEBACK_BIT_SET ? "!" : "");
05413229
NC		 10244 else
10245 func (stream, "]");
10246 }
10247 else
10248 {
10249 func (stream, "]");
f02232aa 10250
c1e26897 10251 if (WRITEBACK_BIT_SET)
05413229
NC		 10252 {
10253 if (offset)
d908c8af 10254 func (stream, ", #%d", (int) value_in_comment);
05413229
NC		 10255 }
10256 else
fe56b6ce 10257 {
d908c8af 10258 func (stream, ", {%d}", (int) offset);
fe56b6ce
NC		 10259 value_in_comment = offset;
10260 }
05413229
NC		 10261 }
10262 }
252b5132
RH		 10263 break;
10264
077b8428
NC		 10265 case 'B':
10266 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10267 {
10268 bfd_vma address;
10269 bfd_vma offset = 0;
b34976b6 10270
c1e26897 10271 if (! NEGATIVE_BIT_SET)
077b8428
NC		 10272 /* Is signed, hi bits should be ones. */
10273 offset = (-1) ^ 0x00ffffff;
10274
10275 /* Offset is (SignExtend(offset field)<<2). */
10276 offset += given & 0x00ffffff;
10277 offset <<= 2;
10278 address = offset + pc + 8;
b34976b6 10279
8f06b2d8
PB		 10280 if (given & 0x01000000)
10281 /* H bit allows addressing to 2-byte boundaries. */
10282 address += 2;
b1ee46c5 10283
8f06b2d8 10284 info->print_address_func (address, info);
1d67fe3b
TT		 10285
10286 /* Fill in instruction information. */
10287 info->insn_info_valid = 1;
10288 info->insn_type = dis_branch;
10289 info->target = address;
b1ee46c5 10290 }
b1ee46c5
AH		 10291 break;
10292
252b5132 10293 case 'C':
90ec0d68
MGD		 10294 if ((given & 0x02000200) == 0x200)
10295 {
10296 const char * name;
10297 unsigned sysm = (given & 0x004f0000) >> 16;
10298
10299 sysm |= (given & 0x300) >> 4;
10300 name = banked_regname (sysm);
10301
10302 if (name != NULL)
10303 func (stream, "%s", name);
10304 else
d908c8af 10305 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68
MGD		 10306 }
10307 else
10308 {
43e65147 10309 func (stream, "%cPSR_",
90ec0d68
MGD		 10310 (given & 0x00400000) ? 'S' : 'C');
10311 if (given & 0x80000)
10312 func (stream, "f");
10313 if (given & 0x40000)
10314 func (stream, "s");
10315 if (given & 0x20000)
10316 func (stream, "x");
10317 if (given & 0x10000)
10318 func (stream, "c");
10319 }
252b5132
RH		 10320 break;
10321
62b3e311 10322 case 'U':
43e65147 10323 if ((given & 0xf0) == 0x60)
62b3e311 10324 {
52e7f43d
RE		 10325 switch (given & 0xf)
10326 {
10327 case 0xf: func (stream, "sy"); break;
10328 default:
10329 func (stream, "#%d", (int) given & 0xf);
10330 break;
10331 }
43e65147
L		 10332 }
10333 else
52e7f43d 10334 {
e797f7e0
MGD		 10335 const char * opt = data_barrier_option (given & 0xf);
10336 if (opt != NULL)
10337 func (stream, "%s", opt);
10338 else
52e7f43d 10339 func (stream, "#%d", (int) given & 0xf);
62b3e311
PB		 10340 }
10341 break;
10342
b34976b6 10343 case '0': case '1': case '2': case '3': case '4':
252b5132
RH		 10344 case '5': case '6': case '7': case '8': case '9':
10345 {
16980d0b
JB		 10346 int width;
10347 unsigned long value;
252b5132 10348
16980d0b 10349 c = arm_decode_bitfield (c, given, &value, &width);
43e65147 10350
252b5132
RH		 10351 switch (*c)
10352 {
ab8e2090
NC		 10353 case 'R':
10354 if (value == 15)
10355 is_unpredictable = TRUE;
10356 /* Fall through. */
16980d0b 10357 case 'r':
9eb6c0f1
MGD		 10358 case 'T':
10359 /* We want register + 1 when decoding T. */
10360 if (*c == 'T')
2bddb71a 10361 value = (value + 1) & 0xf;
9eb6c0f1 10362
ff4a8d2b
NC		 10363 if (c[1] == 'u')
10364 {
10365 /* Eat the 'u' character. */
10366 ++ c;
10367
10368 if (u_reg == value)
10369 is_unpredictable = TRUE;
10370 u_reg = value;
10371 }
10372 if (c[1] == 'U')
10373 {
10374 /* Eat the 'U' character. */
10375 ++ c;
10376
10377 if (U_reg == value)
10378 is_unpredictable = TRUE;
10379 U_reg = value;
10380 }
16980d0b
JB		 10381 func (stream, "%s", arm_regnames[value]);
10382 break;
10383 case 'd':
10384 func (stream, "%ld", value);
05413229 10385 value_in_comment = value;
16980d0b
JB		 10386 break;
10387 case 'b':
10388 func (stream, "%ld", value * 8);
05413229 10389 value_in_comment = value * 8;
16980d0b
JB		 10390 break;
10391 case 'W':
10392 func (stream, "%ld", value + 1);
05413229 10393 value_in_comment = value + 1;
16980d0b
JB		 10394 break;
10395 case 'x':
10396 func (stream, "0x%08lx", value);
10397
10398 /* Some SWI instructions have special
10399 meanings. */
10400 if ((given & 0x0fffffff) == 0x0FF00000)
10401 func (stream, "\t; IMB");
10402 else if ((given & 0x0fffffff) == 0x0FF00001)
10403 func (stream, "\t; IMBRange");
10404 break;
10405 case 'X':
10406 func (stream, "%01lx", value & 0xf);
05413229 10407 value_in_comment = value;
252b5132
RH		 10408 break;
10409 case '`':
10410 c++;
16980d0b 10411 if (value == 0)
252b5132
RH		 10412 func (stream, "%c", *c);
10413 break;
10414 case '\'':
10415 c++;
16980d0b 10416 if (value == ((1ul << width) - 1))
252b5132
RH		 10417 func (stream, "%c", *c);
10418 break;
10419 case '?':
fe56b6ce 10420 func (stream, "%c", c[(1 << width) - (int) value]);
16980d0b 10421 c += 1 << width;
252b5132
RH		 10422 break;
10423 default:
10424 abort ();
10425 }
dffaa15c
AM		 10426 }
10427 break;
0dd132b6 10428
dffaa15c
AM		 10429 case 'e':
10430 {
10431 int imm;
0dd132b6 10432
dffaa15c
AM		 10433 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
10434 func (stream, "%d", imm);
10435 value_in_comment = imm;
10436 }
10437 break;
fe56b6ce 10438
dffaa15c
AM		 10439 case 'E':
10440 /* LSB and WIDTH fields of BFI or BFC. The machine-
10441 language instruction encodes LSB and MSB. */
10442 {
10443 long msb = (given & 0x001f0000) >> 16;
10444 long lsb = (given & 0x00000f80) >> 7;
10445 long w = msb - lsb + 1;
0a003adc 10446
dffaa15c
AM		 10447 if (w > 0)
10448 func (stream, "#%lu, #%lu", lsb, w);
10449 else
10450 func (stream, "(invalid: %lu:%lu)", lsb, msb);
10451 }
10452 break;
90ec0d68 10453
dffaa15c
AM		 10454 case 'R':
10455 /* Get the PSR/banked register name. */
10456 {
10457 const char * name;
10458 unsigned sysm = (given & 0x004f0000) >> 16;
90ec0d68 10459
dffaa15c
AM		 10460 sysm |= (given & 0x300) >> 4;
10461 name = banked_regname (sysm);
90ec0d68 10462
dffaa15c
AM		 10463 if (name != NULL)
10464 func (stream, "%s", name);
10465 else
10466 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
10467 }
10468 break;
fe56b6ce 10469
dffaa15c
AM		 10470 case 'V':
10471 /* 16-bit unsigned immediate from a MOVT or MOVW
10472 instruction, encoded in bits 0:11 and 15:19. */
10473 {
10474 long hi = (given & 0x000f0000) >> 4;
10475 long lo = (given & 0x00000fff);
10476 long imm16 = hi | lo;
0a003adc 10477
dffaa15c
AM		 10478 func (stream, "#%lu", imm16);
10479 value_in_comment = imm16;
252b5132 10480 }
dffaa15c
AM		 10481 break;
10482
10483 default:
10484 abort ();
252b5132
RH		 10485 }
10486 }
10487 else
10488 func (stream, "%c", *c);
10489 }
05413229
NC		 10490
10491 if (value_in_comment > 32 || value_in_comment < -16)
d1aaab3c 10492 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
ab8e2090
NC		 10493
10494 if (is_unpredictable)
10495 func (stream, UNPREDICTABLE_INSTRUCTION);
ff4a8d2b 10496
4a5329c6 10497 return;
252b5132
RH		 10498 }
10499 }
0b347048
TC		 10500 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
10501 return;
252b5132
RH		 10502}
10503
4a5329c6 10504/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
baf0cc5e 10505
4a5329c6
ZW		 10506static void
10507print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
252b5132 10508{
6b5d3a4d 10509 const struct opcode16 *insn;
6a51a8a8
AM		 10510 void *stream = info->stream;
10511 fprintf_ftype func = info->fprintf_func;
252b5132
RH		 10512
10513 for (insn = thumb_opcodes; insn->assembler; insn++)
c19d1205
ZW		 10514 if ((given & insn->mask) == insn->value)
10515 {
05413229 10516 signed long value_in_comment = 0;
6b5d3a4d 10517 const char *c = insn->assembler;
05413229 10518
c19d1205
ZW		 10519 for (; *c; c++)
10520 {
10521 int domaskpc = 0;
10522 int domasklr = 0;
10523
10524 if (*c != '%')
10525 {
10526 func (stream, "%c", *c);
10527 continue;
10528 }
252b5132 10529
c19d1205
ZW		 10530 switch (*++c)
10531 {
10532 case '%':
10533 func (stream, "%%");
10534 break;
b34976b6 10535
c22aaad1
PB		 10536 case 'c':
10537 if (ifthen_state)
10538 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10539 break;
10540
10541 case 'C':
10542 if (ifthen_state)
10543 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10544 else
10545 func (stream, "s");
10546 break;
10547
10548 case 'I':
10549 {
10550 unsigned int tmp;
10551
10552 ifthen_next_state = given & 0xff;
10553 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
10554 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
10555 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
10556 }
10557 break;
10558
10559 case 'x':
10560 if (ifthen_next_state)
10561 func (stream, "\t; unpredictable branch in IT block\n");
10562 break;
10563
10564 case 'X':
10565 if (ifthen_state)
10566 func (stream, "\t; unpredictable <IT:%s>",
10567 arm_conditional[IFTHEN_COND]);
10568 break;
10569
c19d1205
ZW		 10570 case 'S':
10571 {
10572 long reg;
10573
10574 reg = (given >> 3) & 0x7;
10575 if (given & (1 << 6))
10576 reg += 8;
4f3c3dbb 10577
c19d1205
ZW		 10578 func (stream, "%s", arm_regnames[reg]);
10579 }
10580 break;
baf0cc5e 10581
c19d1205 10582 case 'D':
4f3c3dbb 10583 {
c19d1205
ZW		 10584 long reg;
10585
10586 reg = given & 0x7;
10587 if (given & (1 << 7))
10588 reg += 8;
10589
10590 func (stream, "%s", arm_regnames[reg]);
4f3c3dbb 10591 }
c19d1205
ZW		 10592 break;
10593
10594 case 'N':
10595 if (given & (1 << 8))
10596 domasklr = 1;
10597 /* Fall through. */
10598 case 'O':
10599 if (*c == 'O' && (given & (1 << 8)))
10600 domaskpc = 1;
10601 /* Fall through. */
10602 case 'M':
10603 {
10604 int started = 0;
10605 int reg;
10606
10607 func (stream, "{");
10608
10609 /* It would be nice if we could spot
10610 ranges, and generate the rS-rE format: */
10611 for (reg = 0; (reg < 8); reg++)
10612 if ((given & (1 << reg)) != 0)
10613 {
10614 if (started)
10615 func (stream, ", ");
10616 started = 1;
10617 func (stream, "%s", arm_regnames[reg]);
10618 }
10619
10620 if (domasklr)
10621 {
10622 if (started)
10623 func (stream, ", ");
10624 started = 1;
d908c8af 10625 func (stream, "%s", arm_regnames[14] /* "lr" */);
c19d1205
ZW		 10626 }
10627
10628 if (domaskpc)
10629 {
10630 if (started)
10631 func (stream, ", ");
d908c8af 10632 func (stream, "%s", arm_regnames[15] /* "pc" */);
c19d1205
ZW		 10633 }
10634
10635 func (stream, "}");
10636 }
10637 break;
10638
4547cb56
NC		 10639 case 'W':
10640 /* Print writeback indicator for a LDMIA. We are doing a
10641 writeback if the base register is not in the register
10642 mask. */
10643 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
10644 func (stream, "!");
dffaa15c 10645 break;
4547cb56 10646
c19d1205
ZW		 10647 case 'b':
10648 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10649 {
10650 bfd_vma address = (pc + 4
10651 + ((given & 0x00f8) >> 2)
10652 + ((given & 0x0200) >> 3));
10653 info->print_address_func (address, info);
1d67fe3b
TT		 10654
10655 /* Fill in instruction information. */
10656 info->insn_info_valid = 1;
10657 info->insn_type = dis_branch;
10658 info->target = address;
c19d1205
ZW		 10659 }
10660 break;
10661
10662 case 's':
10663 /* Right shift immediate -- bits 6..10; 1-31 print
10664 as themselves, 0 prints as 32. */
10665 {
10666 long imm = (given & 0x07c0) >> 6;
10667 if (imm == 0)
10668 imm = 32;
0fd3a477 10669 func (stream, "#%ld", imm);
c19d1205
ZW		 10670 }
10671 break;
10672
10673 case '0': case '1': case '2': case '3': case '4':
10674 case '5': case '6': case '7': case '8': case '9':
10675 {
10676 int bitstart = *c++ - '0';
10677 int bitend = 0;
10678
10679 while (*c >= '0' && *c <= '9')
10680 bitstart = (bitstart * 10) + *c++ - '0';
10681
10682 switch (*c)
10683 {
10684 case '-':
10685 {
f8b960bc 10686 bfd_vma reg;
c19d1205
ZW		 10687
10688 c++;
10689 while (*c >= '0' && *c <= '9')
10690 bitend = (bitend * 10) + *c++ - '0';
10691 if (!bitend)
10692 abort ();
10693 reg = given >> bitstart;
10694 reg &= (2 << (bitend - bitstart)) - 1;
ff4a8d2b 10695
c19d1205
ZW		 10696 switch (*c)
10697 {
10698 case 'r':
10699 func (stream, "%s", arm_regnames[reg]);
10700 break;
10701
10702 case 'd':
d908c8af 10703 func (stream, "%ld", (long) reg);
05413229 10704 value_in_comment = reg;
c19d1205
ZW		 10705 break;
10706
10707 case 'H':
d908c8af 10708 func (stream, "%ld", (long) (reg << 1));
05413229 10709 value_in_comment = reg << 1;
c19d1205
ZW		 10710 break;
10711
10712 case 'W':
d908c8af 10713 func (stream, "%ld", (long) (reg << 2));
05413229 10714 value_in_comment = reg << 2;
c19d1205
ZW		 10715 break;
10716
10717 case 'a':
10718 /* PC-relative address -- the bottom two
10719 bits of the address are dropped
10720 before the calculation. */
10721 info->print_address_func
10722 (((pc + 4) & ~3) + (reg << 2), info);
05413229 10723 value_in_comment = 0;
c19d1205
ZW		 10724 break;
10725
10726 case 'x':
d908c8af 10727 func (stream, "0x%04lx", (long) reg);
c19d1205
ZW		 10728 break;
10729
c19d1205
ZW		 10730 case 'B':
10731 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
1d67fe3b
TT		 10732 bfd_vma target = reg * 2 + pc + 4;
10733 info->print_address_func (target, info);
05413229 10734 value_in_comment = 0;
1d67fe3b
TT		 10735
10736 /* Fill in instruction information. */
10737 info->insn_info_valid = 1;
10738 info->insn_type = dis_branch;
10739 info->target = target;
c19d1205
ZW		 10740 break;
10741
10742 case 'c':
c22aaad1 10743 func (stream, "%s", arm_conditional [reg]);
c19d1205
ZW		 10744 break;
10745
10746 default:
10747 abort ();
10748 }
10749 }
10750 break;
10751
10752 case '\'':
10753 c++;
10754 if ((given & (1 << bitstart)) != 0)
10755 func (stream, "%c", *c);
10756 break;
10757
10758 case '?':
10759 ++c;
10760 if ((given & (1 << bitstart)) != 0)
10761 func (stream, "%c", *c++);
10762 else
10763 func (stream, "%c", *++c);
10764 break;
10765
10766 default:
10767 abort ();
10768 }
10769 }
10770 break;
10771
10772 default:
10773 abort ();
10774 }
10775 }
05413229
NC		 10776
10777 if (value_in_comment > 32 || value_in_comment < -16)
10778 func (stream, "\t; 0x%lx", value_in_comment);
4a5329c6 10779 return;
c19d1205
ZW		 10780 }
10781
10782 /* No match. */
0b347048
TC		 10783 func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given);
10784 return;
c19d1205
ZW		 10785}
10786
62b3e311 10787/* Return the name of an V7M special register. */
fe56b6ce 10788
62b3e311
PB		 10789static const char *
10790psr_name (int regno)
10791{
10792 switch (regno)
10793 {
1a336194
TP		 10794 case 0x0: return "APSR";
10795 case 0x1: return "IAPSR";
10796 case 0x2: return "EAPSR";
10797 case 0x3: return "PSR";
10798 case 0x5: return "IPSR";
10799 case 0x6: return "EPSR";
10800 case 0x7: return "IEPSR";
10801 case 0x8: return "MSP";
10802 case 0x9: return "PSP";
10803 case 0xa: return "MSPLIM";
10804 case 0xb: return "PSPLIM";
10805 case 0x10: return "PRIMASK";
10806 case 0x11: return "BASEPRI";
10807 case 0x12: return "BASEPRI_MAX";
10808 case 0x13: return "FAULTMASK";
10809 case 0x14: return "CONTROL";
16a1fa25
TP		 10810 case 0x88: return "MSP_NS";
10811 case 0x89: return "PSP_NS";
1a336194
TP		 10812 case 0x8a: return "MSPLIM_NS";
10813 case 0x8b: return "PSPLIM_NS";
10814 case 0x90: return "PRIMASK_NS";
10815 case 0x91: return "BASEPRI_NS";
10816 case 0x93: return "FAULTMASK_NS";
10817 case 0x94: return "CONTROL_NS";
10818 case 0x98: return "SP_NS";
62b3e311
PB		 10819 default: return "<unknown>";
10820 }
10821}
10822
4a5329c6
ZW		 10823/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10824
10825static void
10826print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
c19d1205 10827{
6b5d3a4d 10828 const struct opcode32 *insn;
c19d1205
ZW		 10829 void *stream = info->stream;
10830 fprintf_ftype func = info->fprintf_func;
73cd51e5 10831 bfd_boolean is_mve = is_mve_architecture (info);
c19d1205 10832
16980d0b
JB		 10833 if (print_insn_coprocessor (pc, info, given, TRUE))
10834 return;
10835
73cd51e5
AV		 10836 if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
10837 return;
10838
10839 if (is_mve && print_insn_mve (info, given))
8f06b2d8
PB		 10840 return;
10841
4934a27c
MM		 10842 if (print_insn_cde (info, given, TRUE))
10843 return;
10844
33593eaf
MM		 10845 if (print_insn_generic_coprocessor (pc, info, given, TRUE))
10846 return;
10847
c19d1205
ZW		 10848 for (insn = thumb32_opcodes; insn->assembler; insn++)
10849 if ((given & insn->mask) == insn->value)
10850 {
4b5a202f 10851 bfd_boolean is_clrm = FALSE;
ff4a8d2b 10852 bfd_boolean is_unpredictable = FALSE;
05413229 10853 signed long value_in_comment = 0;
6b5d3a4d 10854 const char *c = insn->assembler;
05413229 10855
c19d1205
ZW		 10856 for (; *c; c++)
10857 {
10858 if (*c != '%')
10859 {
10860 func (stream, "%c", *c);
10861 continue;
10862 }
10863
10864 switch (*++c)
10865 {
10866 case '%':
10867 func (stream, "%%");
10868 break;
10869
c22aaad1
PB		 10870 case 'c':
10871 if (ifthen_state)
10872 func (stream, "%s", arm_conditional[IFTHEN_COND]);
10873 break;
10874
10875 case 'x':
10876 if (ifthen_next_state)
10877 func (stream, "\t; unpredictable branch in IT block\n");
10878 break;
10879
10880 case 'X':
10881 if (ifthen_state)
10882 func (stream, "\t; unpredictable <IT:%s>",
10883 arm_conditional[IFTHEN_COND]);
10884 break;
10885
c19d1205
ZW		 10886 case 'I':
10887 {
10888 unsigned int imm12 = 0;
fe56b6ce 10889
c19d1205
ZW		 10890 imm12 |= (given & 0x000000ffu);
10891 imm12 |= (given & 0x00007000u) >> 4;
92e90b6e 10892 imm12 |= (given & 0x04000000u) >> 15;
fe56b6ce
NC		 10893 func (stream, "#%u", imm12);
10894 value_in_comment = imm12;
c19d1205
ZW		 10895 }
10896 break;
10897
10898 case 'M':
10899 {
10900 unsigned int bits = 0, imm, imm8, mod;
fe56b6ce 10901
c19d1205
ZW		 10902 bits |= (given & 0x000000ffu);
10903 bits |= (given & 0x00007000u) >> 4;
10904 bits |= (given & 0x04000000u) >> 15;
10905 imm8 = (bits & 0x0ff);
10906 mod = (bits & 0xf00) >> 8;
10907 switch (mod)
10908 {
10909 case 0: imm = imm8; break;
c1e26897
NC		 10910 case 1: imm = ((imm8 << 16) | imm8); break;
10911 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
10912 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
c19d1205
ZW		 10913 default:
10914 mod = (bits & 0xf80) >> 7;
10915 imm8 = (bits & 0x07f) | 0x80;
10916 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
10917 }
fe56b6ce
NC		 10918 func (stream, "#%u", imm);
10919 value_in_comment = imm;
c19d1205
ZW		 10920 }
10921 break;
43e65147 10922
c19d1205
ZW		 10923 case 'J':
10924 {
10925 unsigned int imm = 0;
fe56b6ce 10926
c19d1205
ZW		 10927 imm |= (given & 0x000000ffu);
10928 imm |= (given & 0x00007000u) >> 4;
10929 imm |= (given & 0x04000000u) >> 15;
10930 imm |= (given & 0x000f0000u) >> 4;
fe56b6ce
NC		 10931 func (stream, "#%u", imm);
10932 value_in_comment = imm;
c19d1205
ZW		 10933 }
10934 break;
10935
10936 case 'K':
10937 {
10938 unsigned int imm = 0;
fe56b6ce 10939
c19d1205
ZW		 10940 imm |= (given & 0x000f0000u) >> 16;
10941 imm |= (given & 0x00000ff0u) >> 0;
10942 imm |= (given & 0x0000000fu) << 12;
fe56b6ce
NC		 10943 func (stream, "#%u", imm);
10944 value_in_comment = imm;
c19d1205
ZW		 10945 }
10946 break;
10947
74db7efb
NC		 10948 case 'H':
10949 {
10950 unsigned int imm = 0;
10951
10952 imm |= (given & 0x000f0000u) >> 4;
10953 imm |= (given & 0x00000fffu) >> 0;
10954 func (stream, "#%u", imm);
10955 value_in_comment = imm;
10956 }
10957 break;
10958
90ec0d68
MGD		 10959 case 'V':
10960 {
10961 unsigned int imm = 0;
10962
10963 imm |= (given & 0x00000fffu);
10964 imm |= (given & 0x000f0000u) >> 4;
10965 func (stream, "#%u", imm);
10966 value_in_comment = imm;
10967 }
10968 break;
10969
c19d1205
ZW		 10970 case 'S':
10971 {
10972 unsigned int reg = (given & 0x0000000fu);
10973 unsigned int stp = (given & 0x00000030u) >> 4;
10974 unsigned int imm = 0;
10975 imm |= (given & 0x000000c0u) >> 6;
10976 imm |= (given & 0x00007000u) >> 10;
10977
10978 func (stream, "%s", arm_regnames[reg]);
10979 switch (stp)
10980 {
10981 case 0:
10982 if (imm > 0)
10983 func (stream, ", lsl #%u", imm);
10984 break;
10985
10986 case 1:
10987 if (imm == 0)
10988 imm = 32;
10989 func (stream, ", lsr #%u", imm);
10990 break;
10991
10992 case 2:
10993 if (imm == 0)
10994 imm = 32;
10995 func (stream, ", asr #%u", imm);
10996 break;
10997
10998 case 3:
10999 if (imm == 0)
11000 func (stream, ", rrx");
11001 else
11002 func (stream, ", ror #%u", imm);
11003 }
11004 }
11005 break;
11006
11007 case 'a':
11008 {
11009 unsigned int Rn = (given & 0x000f0000) >> 16;
c1e26897 11010 unsigned int U = ! NEGATIVE_BIT_SET;
c19d1205
ZW		 11011 unsigned int op = (given & 0x00000f00) >> 8;
11012 unsigned int i12 = (given & 0x00000fff);
11013 unsigned int i8 = (given & 0x000000ff);
11014 bfd_boolean writeback = FALSE, postind = FALSE;
f8b960bc 11015 bfd_vma offset = 0;
c19d1205
ZW		 11016
11017 func (stream, "[%s", arm_regnames[Rn]);
05413229
NC		 11018 if (U) /* 12-bit positive immediate offset. */
11019 {
11020 offset = i12;
11021 if (Rn != 15)
11022 value_in_comment = offset;
11023 }
11024 else if (Rn == 15) /* 12-bit negative immediate offset. */
11025 offset = - (int) i12;
11026 else if (op == 0x0) /* Shifted register offset. */
c19d1205
ZW		 11027 {
11028 unsigned int Rm = (i8 & 0x0f);
11029 unsigned int sh = (i8 & 0x30) >> 4;
05413229 11030
c19d1205
ZW		 11031 func (stream, ", %s", arm_regnames[Rm]);
11032 if (sh)
11033 func (stream, ", lsl #%u", sh);
11034 func (stream, "]");
11035 break;
11036 }
11037 else switch (op)
11038 {
05413229 11039 case 0xE: /* 8-bit positive immediate offset. */
c19d1205
ZW		 11040 offset = i8;
11041 break;
11042
05413229 11043 case 0xC: /* 8-bit negative immediate offset. */
c19d1205
ZW		 11044 offset = -i8;
11045 break;
11046
05413229 11047 case 0xF: /* 8-bit + preindex with wb. */
c19d1205
ZW		 11048 offset = i8;
11049 writeback = TRUE;
11050 break;
11051
05413229 11052 case 0xD: /* 8-bit - preindex with wb. */
c19d1205
ZW		 11053 offset = -i8;
11054 writeback = TRUE;
11055 break;
11056
05413229 11057 case 0xB: /* 8-bit + postindex. */
c19d1205
ZW		 11058 offset = i8;
11059 postind = TRUE;
11060 break;
11061
05413229 11062 case 0x9: /* 8-bit - postindex. */
c19d1205
ZW		 11063 offset = -i8;
11064 postind = TRUE;
11065 break;
11066
11067 default:
11068 func (stream, ", <undefined>]");
11069 goto skip;
11070 }
11071
11072 if (postind)
d908c8af 11073 func (stream, "], #%d", (int) offset);
c19d1205
ZW		 11074 else
11075 {
11076 if (offset)
d908c8af 11077 func (stream, ", #%d", (int) offset);
c19d1205
ZW		 11078 func (stream, writeback ? "]!" : "]");
11079 }
11080
11081 if (Rn == 15)
11082 {
11083 func (stream, "\t; ");
11084 info->print_address_func (((pc + 4) & ~3) + offset, info);
11085 }
11086 }
11087 skip:
11088 break;
11089
11090 case 'A':
11091 {
c1e26897
NC		 11092 unsigned int U = ! NEGATIVE_BIT_SET;
11093 unsigned int W = WRITEBACK_BIT_SET;
c19d1205
ZW		 11094 unsigned int Rn = (given & 0x000f0000) >> 16;
11095 unsigned int off = (given & 0x000000ff);
11096
11097 func (stream, "[%s", arm_regnames[Rn]);
c1e26897
NC		 11098
11099 if (PRE_BIT_SET)
c19d1205
ZW		 11100 {
11101 if (off || !U)
05413229
NC		 11102 {
11103 func (stream, ", #%c%u", U ? '+' : '-', off * 4);
fe50e98c 11104 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11105 }
c19d1205
ZW		 11106 func (stream, "]");
11107 if (W)
11108 func (stream, "!");
11109 }
11110 else
11111 {
11112 func (stream, "], ");
11113 if (W)
05413229
NC		 11114 {
11115 func (stream, "#%c%u", U ? '+' : '-', off * 4);
fe50e98c 11116 value_in_comment = off * 4 * (U ? 1 : -1);
05413229 11117 }
c19d1205 11118 else
fe56b6ce
NC		 11119 {
11120 func (stream, "{%u}", off);
11121 value_in_comment = off;
11122 }
c19d1205
ZW		 11123 }
11124 }
11125 break;
11126
11127 case 'w':
11128 {
11129 unsigned int Sbit = (given & 0x01000000) >> 24;
11130 unsigned int type = (given & 0x00600000) >> 21;
05413229 11131
c19d1205
ZW		 11132 switch (type)
11133 {
11134 case 0: func (stream, Sbit ? "sb" : "b"); break;
11135 case 1: func (stream, Sbit ? "sh" : "h"); break;
11136 case 2:
11137 if (Sbit)
11138 func (stream, "??");
11139 break;
11140 case 3:
11141 func (stream, "??");
11142 break;
11143 }
11144 }
11145 break;
11146
4b5a202f
AV		 11147 case 'n':
11148 is_clrm = TRUE;
11149 /* Fall through. */
c19d1205
ZW		 11150 case 'm':
11151 {
11152 int started = 0;
11153 int reg;
11154
11155 func (stream, "{");
11156 for (reg = 0; reg < 16; reg++)
11157 if ((given & (1 << reg)) != 0)
11158 {
11159 if (started)
11160 func (stream, ", ");
11161 started = 1;
4b5a202f
AV		 11162 if (is_clrm && reg == 13)
11163 func (stream, "(invalid: %s)", arm_regnames[reg]);
11164 else if (is_clrm && reg == 15)
11165 func (stream, "%s", "APSR");
11166 else
11167 func (stream, "%s", arm_regnames[reg]);
c19d1205
ZW		 11168 }
11169 func (stream, "}");
11170 }
11171 break;
11172
11173 case 'E':
11174 {
11175 unsigned int msb = (given & 0x0000001f);
11176 unsigned int lsb = 0;
fe56b6ce 11177
c19d1205
ZW		 11178 lsb |= (given & 0x000000c0u) >> 6;
11179 lsb |= (given & 0x00007000u) >> 10;
11180 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
11181 }
11182 break;
11183
11184 case 'F':
11185 {
11186 unsigned int width = (given & 0x0000001f) + 1;
11187 unsigned int lsb = 0;
fe56b6ce 11188
c19d1205
ZW		 11189 lsb |= (given & 0x000000c0u) >> 6;
11190 lsb |= (given & 0x00007000u) >> 10;
11191 func (stream, "#%u, #%u", lsb, width);
11192 }
11193 break;
11194
e12437dc
AV		 11195 case 'G':
11196 {
11197 unsigned int boff = (((given & 0x07800000) >> 23) << 1);
11198 func (stream, "%x", boff);
11199 }
11200 break;
11201
e5d6e09e
AV		 11202 case 'W':
11203 {
11204 unsigned int immA = (given & 0x001f0000u) >> 16;
11205 unsigned int immB = (given & 0x000007feu) >> 1;
11206 unsigned int immC = (given & 0x00000800u) >> 11;
11207 bfd_vma offset = 0;
11208
11209 offset |= immA << 12;
11210 offset |= immB << 2;
11211 offset |= immC << 1;
11212 /* Sign extend. */
11213 offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
11214
11215 info->print_address_func (pc + 4 + offset, info);
11216 }
11217 break;
11218
1caf72a5
AV		 11219 case 'Y':
11220 {
11221 unsigned int immA = (given & 0x007f0000u) >> 16;
11222 unsigned int immB = (given & 0x000007feu) >> 1;
11223 unsigned int immC = (given & 0x00000800u) >> 11;
11224 bfd_vma offset = 0;
11225
11226 offset |= immA << 12;
11227 offset |= immB << 2;
11228 offset |= immC << 1;
11229 /* Sign extend. */
11230 offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
11231
11232 info->print_address_func (pc + 4 + offset, info);
11233 }
11234 break;
11235
1889da70
AV		 11236 case 'Z':
11237 {
11238 unsigned int immA = (given & 0x00010000u) >> 16;
11239 unsigned int immB = (given & 0x000007feu) >> 1;
11240 unsigned int immC = (given & 0x00000800u) >> 11;
11241 bfd_vma offset = 0;
11242
11243 offset |= immA << 12;
11244 offset |= immB << 2;
11245 offset |= immC << 1;
11246 /* Sign extend. */
11247 offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
11248
11249 info->print_address_func (pc + 4 + offset, info);
f6b2b12d
AV		 11250
11251 unsigned int T = (given & 0x00020000u) >> 17;
11252 unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
11253 unsigned int boffset = (T == 1) ? 4 : 2;
11254 func (stream, ", ");
11255 func (stream, "%x", endoffset + boffset);
1889da70
AV		 11256 }
11257 break;
11258
60f993ce
AV		 11259 case 'Q':
11260 {
11261 unsigned int immh = (given & 0x000007feu) >> 1;
11262 unsigned int imml = (given & 0x00000800u) >> 11;
11263 bfd_vma imm32 = 0;
11264
11265 imm32 |= immh << 2;
11266 imm32 |= imml << 1;
11267
11268 info->print_address_func (pc + 4 + imm32, info);
11269 }
11270 break;
11271
11272 case 'P':
11273 {
11274 unsigned int immh = (given & 0x000007feu) >> 1;
11275 unsigned int imml = (given & 0x00000800u) >> 11;
11276 bfd_vma imm32 = 0;
11277
11278 imm32 |= immh << 2;
11279 imm32 |= imml << 1;
11280
11281 info->print_address_func (pc + 4 - imm32, info);
11282 }
11283 break;
11284
c19d1205
ZW		 11285 case 'b':
11286 {
11287 unsigned int S = (given & 0x04000000u) >> 26;
11288 unsigned int J1 = (given & 0x00002000u) >> 13;
11289 unsigned int J2 = (given & 0x00000800u) >> 11;
f8b960bc 11290 bfd_vma offset = 0;
c19d1205
ZW		 11291
11292 offset |= !S << 20;
11293 offset |= J2 << 19;
11294 offset |= J1 << 18;
11295 offset |= (given & 0x003f0000) >> 4;
11296 offset |= (given & 0x000007ff) << 1;
11297 offset -= (1 << 20);
11298
1d67fe3b
TT		 11299 bfd_vma target = pc + 4 + offset;
11300 info->print_address_func (target, info);
11301
11302 /* Fill in instruction information. */
11303 info->insn_info_valid = 1;
11304 info->insn_type = dis_branch;
11305 info->target = target;
c19d1205
ZW		 11306 }
11307 break;
11308
11309 case 'B':
11310 {
11311 unsigned int S = (given & 0x04000000u) >> 26;
11312 unsigned int I1 = (given & 0x00002000u) >> 13;
11313 unsigned int I2 = (given & 0x00000800u) >> 11;
f8b960bc 11314 bfd_vma offset = 0;
c19d1205
ZW		 11315
11316 offset |= !S << 24;
11317 offset |= !(I1 ^ S) << 23;
11318 offset |= !(I2 ^ S) << 22;
11319 offset |= (given & 0x03ff0000u) >> 4;
11320 offset |= (given & 0x000007ffu) << 1;
11321 offset -= (1 << 24);
36b0c57d 11322 offset += pc + 4;
c19d1205 11323
36b0c57d
PB		 11324 /* BLX target addresses are always word aligned. */
11325 if ((given & 0x00001000u) == 0)
11326 offset &= ~2u;
11327
11328 info->print_address_func (offset, info);
1d67fe3b
TT		 11329
11330 /* Fill in instruction information. */
11331 info->insn_info_valid = 1;
11332 info->insn_type = dis_branch;
11333 info->target = offset;
c19d1205
ZW		 11334 }
11335 break;
11336
11337 case 's':
11338 {
11339 unsigned int shift = 0;
fe56b6ce 11340
c19d1205
ZW		 11341 shift |= (given & 0x000000c0u) >> 6;
11342 shift |= (given & 0x00007000u) >> 10;
c1e26897 11343 if (WRITEBACK_BIT_SET)
c19d1205
ZW		 11344 func (stream, ", asr #%u", shift);
11345 else if (shift)
11346 func (stream, ", lsl #%u", shift);
11347 /* else print nothing - lsl #0 */
11348 }
11349 break;
11350
11351 case 'R':
11352 {
11353 unsigned int rot = (given & 0x00000030) >> 4;
fe56b6ce 11354
c19d1205
ZW		 11355 if (rot)
11356 func (stream, ", ror #%u", rot * 8);
11357 }
11358 break;
11359
62b3e311 11360 case 'U':
43e65147 11361 if ((given & 0xf0) == 0x60)
62b3e311 11362 {
52e7f43d
RE		 11363 switch (given & 0xf)
11364 {
11365 case 0xf: func (stream, "sy"); break;
11366 default:
11367 func (stream, "#%d", (int) given & 0xf);
11368 break;
11369 }
62b3e311 11370 }
43e65147 11371 else
52e7f43d 11372 {
e797f7e0
MGD		 11373 const char * opt = data_barrier_option (given & 0xf);
11374 if (opt != NULL)
11375 func (stream, "%s", opt);
11376 else
11377 func (stream, "#%d", (int) given & 0xf);
52e7f43d 11378 }
62b3e311
PB		 11379 break;
11380
11381 case 'C':
11382 if ((given & 0xff) == 0)
11383 {
11384 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
11385 if (given & 0x800)
11386 func (stream, "f");
11387 if (given & 0x400)
11388 func (stream, "s");
11389 if (given & 0x200)
11390 func (stream, "x");
11391 if (given & 0x100)
11392 func (stream, "c");
11393 }
90ec0d68
MGD		 11394 else if ((given & 0x20) == 0x20)
11395 {
11396 char const* name;
11397 unsigned sysm = (given & 0xf00) >> 8;
11398
11399 sysm |= (given & 0x30);
11400 sysm |= (given & 0x00100000) >> 14;
11401 name = banked_regname (sysm);
43e65147 11402
90ec0d68
MGD		 11403 if (name != NULL)
11404 func (stream, "%s", name);
11405 else
d908c8af 11406 func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
90ec0d68 11407 }
62b3e311
PB		 11408 else
11409 {
d908c8af 11410 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11411 }
11412 break;
11413
11414 case 'D':
90ec0d68
MGD		 11415 if (((given & 0xff) == 0)
11416 || ((given & 0x20) == 0x20))
11417 {
11418 char const* name;
11419 unsigned sm = (given & 0xf0000) >> 16;
11420
11421 sm |= (given & 0x30);
11422 sm |= (given & 0x00100000) >> 14;
11423 name = banked_regname (sm);
11424
11425 if (name != NULL)
11426 func (stream, "%s", name);
11427 else
d908c8af 11428 func (stream, "(UNDEF: %lu)", (unsigned long) sm);
90ec0d68 11429 }
62b3e311 11430 else
d908c8af 11431 func (stream, "%s", psr_name (given & 0xff));
62b3e311
PB		 11432 break;
11433
c19d1205
ZW		 11434 case '0': case '1': case '2': case '3': case '4':
11435 case '5': case '6': case '7': case '8': case '9':
11436 {
16980d0b
JB		 11437 int width;
11438 unsigned long val;
c19d1205 11439
16980d0b 11440 c = arm_decode_bitfield (c, given, &val, &width);
43e65147 11441
c19d1205
ZW		 11442 switch (*c)
11443 {
d052b9b7
AV		 11444 case 's':
11445 if (val <= 3)
11446 func (stream, "%s", mve_vec_sizename[val]);
11447 else
11448 func (stream, "<undef size>");
11449 break;
11450
05413229
NC		 11451 case 'd':
11452 func (stream, "%lu", val);
11453 value_in_comment = val;
11454 break;
ff4a8d2b 11455
f0fba320
RL		 11456 case 'D':
11457 func (stream, "%lu", val + 1);
11458 value_in_comment = val + 1;
11459 break;
11460
05413229
NC		 11461 case 'W':
11462 func (stream, "%lu", val * 4);
11463 value_in_comment = val * 4;
11464 break;
ff4a8d2b 11465
f1c7f421
AV		 11466 case 'S':
11467 if (val == 13)
11468 is_unpredictable = TRUE;
11469 /* Fall through. */
ff4a8d2b
NC		 11470 case 'R':
11471 if (val == 15)
11472 is_unpredictable = TRUE;
11473 /* Fall through. */
11474 case 'r':
11475 func (stream, "%s", arm_regnames[val]);
11476 break;
c19d1205
ZW		 11477
11478 case 'c':
c22aaad1 11479 func (stream, "%s", arm_conditional[val]);
c19d1205
ZW		 11480 break;
11481
11482 case '\'':
c19d1205 11483 c++;
16980d0b
JB		 11484 if (val == ((1ul << width) - 1))
11485 func (stream, "%c", *c);
c19d1205 11486 break;
43e65147 11487
c19d1205 11488 case '`':
c19d1205 11489 c++;
16980d0b
JB		 11490 if (val == 0)
11491 func (stream, "%c", *c);
c19d1205
ZW		 11492 break;
11493
11494 case '?':
fe56b6ce 11495 func (stream, "%c", c[(1 << width) - (int) val]);
16980d0b 11496 c += 1 << width;
c19d1205 11497 break;
43e65147 11498
0bb027fd
RR		 11499 case 'x':
11500 func (stream, "0x%lx", val & 0xffffffffUL);
11501 break;
c19d1205
ZW		 11502
11503 default:
11504 abort ();
11505 }
11506 }
11507 break;
11508
32a94698
NC		 11509 case 'L':
11510 /* PR binutils/12534
11511 If we have a PC relative offset in an LDRD or STRD
11512 instructions then display the decoded address. */
11513 if (((given >> 16) & 0xf) == 0xf)
11514 {
11515 bfd_vma offset = (given & 0xff) * 4;
11516
11517 if ((given & (1 << 23)) == 0)
11518 offset = - offset;
11519 func (stream, "\t; ");
11520 info->print_address_func ((pc & ~3) + 4 + offset, info);
11521 }
11522 break;
11523
c19d1205
ZW		 11524 default:
11525 abort ();
11526 }
11527 }
05413229
NC		 11528
11529 if (value_in_comment > 32 || value_in_comment < -16)
11530 func (stream, "\t; 0x%lx", value_in_comment);
ff4a8d2b
NC		 11531
11532 if (is_unpredictable)
11533 func (stream, UNPREDICTABLE_INSTRUCTION);
11534
4a5329c6 11535 return;
c19d1205 11536 }
252b5132 11537
58efb6c0 11538 /* No match. */
0b347048
TC		 11539 func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given);
11540 return;
252b5132
RH		 11541}
11542
e821645d
DJ		 11543/* Print data bytes on INFO->STREAM. */
11544
11545static void
fe56b6ce
NC		 11546print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
11547 struct disassemble_info *info,
e821645d
DJ		 11548 long given)
11549{
11550 switch (info->bytes_per_chunk)
11551 {
11552 case 1:
11553 info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
11554 break;
11555 case 2:
11556 info->fprintf_func (info->stream, ".short\t0x%04lx", given);
11557 break;
11558 case 4:
11559 info->fprintf_func (info->stream, ".word\t0x%08lx", given);
11560 break;
11561 default:
11562 abort ();
11563 }
11564}
11565
22a398e1 11566/* Disallow mapping symbols ($a, $b, $d, $t etc) from
d8282f0e
JW		 11567 being displayed in symbol relative addresses.
11568
11569 Also disallow private symbol, with __tagsym$$ prefix,
11570 from ARM RVCT toolchain being displayed. */
22a398e1
NC		 11571
11572bfd_boolean
11573arm_symbol_is_valid (asymbol * sym,
11574 struct disassemble_info * info ATTRIBUTE_UNUSED)
11575{
11576 const char * name;
43e65147 11577
22a398e1
NC		 11578 if (sym == NULL)
11579 return FALSE;
11580
11581 name = bfd_asymbol_name (sym);
11582
d8282f0e 11583 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
22a398e1
NC		 11584}
11585
65b48a81 11586/* Parse the string of disassembler options. */
baf0cc5e 11587
65b48a81 11588static void
f995bbe8 11589parse_arm_disassembler_options (const char *options)
dd92f639 11590{
f995bbe8 11591 const char *opt;
b34976b6 11592
65b48a81 11593 FOR_EACH_DISASSEMBLER_OPTION (opt, options)
dd92f639 11594 {
65b48a81
PB		 11595 if (CONST_STRNEQ (opt, "reg-names-"))
11596 {
11597 unsigned int i;
11598 for (i = 0; i < NUM_ARM_OPTIONS; i++)
11599 if (disassembler_options_cmp (opt, regnames[i].name) == 0)
11600 {
11601 regname_selected = i;
11602 break;
11603 }
b34976b6 11604
65b48a81 11605 if (i >= NUM_ARM_OPTIONS)
a6743a54
AM		 11606 /* xgettext: c-format */
11607 opcodes_error_handler (_("unrecognised register name set: %s"),
11608 opt);
65b48a81
PB		 11609 }
11610 else if (CONST_STRNEQ (opt, "force-thumb"))
11611 force_thumb = 1;
11612 else if (CONST_STRNEQ (opt, "no-force-thumb"))
11613 force_thumb = 0;
4934a27c
MM		 11614 else if (CONST_STRNEQ (opt, "coproc"))
11615 {
11616 const char *procptr = opt + sizeof ("coproc") - 1;
11617 char *endptr;
11618 uint8_t coproc_number = strtol (procptr, &endptr, 10);
11619 if (endptr != procptr + 1 || coproc_number > 7)
11620 {
11621 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11622 opt);
11623 continue;
11624 }
11625 if (*endptr != '=')
11626 {
11627 opcodes_error_handler (_("coproc must have an argument: %s"),
11628 opt);
11629 continue;
11630 }
11631 endptr += 1;
11632 if (CONST_STRNEQ (endptr, "generic"))
11633 cde_coprocs &= ~(1 << coproc_number);
11634 else if (CONST_STRNEQ (endptr, "cde")
11635 || CONST_STRNEQ (endptr, "CDE"))
11636 cde_coprocs |= (1 << coproc_number);
11637 else
11638 {
11639 opcodes_error_handler (
11640 _("coprocN argument takes options \"generic\","
11641 " \"cde\", or \"CDE\": %s"), opt);
11642 }
11643 }
65b48a81 11644 else
a6743a54
AM		 11645 /* xgettext: c-format */
11646 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt);
dd92f639 11647 }
b34976b6 11648
dd92f639
NC		 11649 return;
11650}
11651
5bc5ae88
RL		 11652static bfd_boolean
11653mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11654 enum map_type *map_symbol);
11655
c22aaad1
PB		 11656/* Search back through the insn stream to determine if this instruction is
11657 conditionally executed. */
fe56b6ce 11658
c22aaad1 11659static void
fe56b6ce
NC		 11660find_ifthen_state (bfd_vma pc,
11661 struct disassemble_info *info,
c22aaad1
PB		 11662 bfd_boolean little)
11663{
11664 unsigned char b[2];
11665 unsigned int insn;
11666 int status;
11667 /* COUNT is twice the number of instructions seen. It will be odd if we
11668 just crossed an instruction boundary. */
11669 int count;
11670 int it_count;
11671 unsigned int seen_it;
11672 bfd_vma addr;
11673
11674 ifthen_address = pc;
11675 ifthen_state = 0;
11676
11677 addr = pc;
11678 count = 1;
11679 it_count = 0;
11680 seen_it = 0;
11681 /* Scan backwards looking for IT instructions, keeping track of where
11682 instruction boundaries are. We don't know if something is actually an
11683 IT instruction until we find a definite instruction boundary. */
11684 for (;;)
11685 {
fe56b6ce 11686 if (addr == 0 || info->symbol_at_address_func (addr, info))
c22aaad1
PB		 11687 {
11688 /* A symbol must be on an instruction boundary, and will not
11689 be within an IT block. */
11690 if (seen_it && (count & 1))
11691 break;
11692
11693 return;
11694 }
11695 addr -= 2;
fe56b6ce 11696 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
c22aaad1
PB		 11697 if (status)
11698 return;
11699
11700 if (little)
11701 insn = (b[0]) | (b[1] << 8);
11702 else
11703 insn = (b[1]) | (b[0] << 8);
11704 if (seen_it)
11705 {
11706 if ((insn & 0xf800) < 0xe800)
11707 {
11708 /* Addr + 2 is an instruction boundary. See if this matches
11709 the expected boundary based on the position of the last
11710 IT candidate. */
11711 if (count & 1)
11712 break;
11713 seen_it = 0;
11714 }
11715 }
11716 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
11717 {
5bc5ae88
RL		 11718 enum map_type type = MAP_ARM;
11719 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
11720
11721 if (!found || (found && type == MAP_THUMB))
11722 {
11723 /* This could be an IT instruction. */
11724 seen_it = insn;
11725 it_count = count >> 1;
11726 }
c22aaad1
PB		 11727 }
11728 if ((insn & 0xf800) >= 0xe800)
11729 count++;
11730 else
11731 count = (count + 2) | 1;
11732 /* IT blocks contain at most 4 instructions. */
11733 if (count >= 8 && !seen_it)
11734 return;
11735 }
11736 /* We found an IT instruction. */
11737 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
11738 if ((ifthen_state & 0xf) == 0)
11739 ifthen_state = 0;
11740}
11741
b0e28b39
DJ		 11742/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11743 mapping symbol. */
11744
11745static int
11746is_mapping_symbol (struct disassemble_info *info, int n,
11747 enum map_type *map_type)
11748{
11749 const char *name;
11750
11751 name = bfd_asymbol_name (info->symtab[n]);
11752 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
11753 && (name[2] == 0 || name[2] == '.'))
11754 {
11755 *map_type = ((name[1] == 'a') ? MAP_ARM
11756 : (name[1] == 't') ? MAP_THUMB
11757 : MAP_DATA);
11758 return TRUE;
11759 }
11760
11761 return FALSE;
11762}
11763
11764/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11765 Returns nonzero if *MAP_TYPE was set. */
11766
11767static int
11768get_map_sym_type (struct disassemble_info *info,
11769 int n,
11770 enum map_type *map_type)
11771{
11772 /* If the symbol is in a different section, ignore it. */
11773 if (info->section != NULL && info->section != info->symtab[n]->section)
11774 return FALSE;
11775
11776 return is_mapping_symbol (info, n, map_type);
11777}
11778
11779/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
e821645d 11780 Returns nonzero if *MAP_TYPE was set. */
2087ad84
PB		 11781
11782static int
fe56b6ce
NC		 11783get_sym_code_type (struct disassemble_info *info,
11784 int n,
e821645d 11785 enum map_type *map_type)
2087ad84
PB		 11786{
11787 elf_symbol_type *es;
11788 unsigned int type;
b0e28b39
DJ		 11789
11790 /* If the symbol is in a different section, ignore it. */
11791 if (info->section != NULL && info->section != info->symtab[n]->section)
11792 return FALSE;
2087ad84 11793
e821645d 11794 es = *(elf_symbol_type **)(info->symtab + n);
2087ad84
PB		 11795 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
11796
11797 /* If the symbol has function type then use that. */
34e77a92 11798 if (type == STT_FUNC || type == STT_GNU_IFUNC)
2087ad84 11799 {
39d911fc
TP		 11800 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
11801 == ST_BRANCH_TO_THUMB)
35fc36a8
RS		 11802 *map_type = MAP_THUMB;
11803 else
11804 *map_type = MAP_ARM;
2087ad84
PB		 11805 return TRUE;
11806 }
11807
2087ad84
PB		 11808 return FALSE;
11809}
11810
5bc5ae88
RL		 11811/* Search the mapping symbol state for instruction at pc. This is only
11812 applicable for elf target.
11813
11814 There is an assumption Here, info->private_data contains the correct AND
11815 up-to-date information about current scan process. The information will be
11816 used to speed this search process.
11817
11818 Return TRUE if the mapping state can be determined, and map_symbol
11819 will be updated accordingly. Otherwise, return FALSE. */
11820
11821static bfd_boolean
11822mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
11823 enum map_type *map_symbol)
11824{
796d6298
TC		 11825 bfd_vma addr, section_vma = 0;
11826 int n, last_sym = -1;
5bc5ae88 11827 bfd_boolean found = FALSE;
796d6298
TC		 11828 bfd_boolean can_use_search_opt_p = FALSE;
11829
11830 /* Default to DATA. A text section is required by the ABI to contain an
11831 INSN mapping symbol at the start. A data section has no such
11832 requirement, hence if no mapping symbol is found the section must
11833 contain only data. This however isn't very useful if the user has
11834 fully stripped the binaries. If this is the case use the section
11835 attributes to determine the default. If we have no section default to
11836 INSN as well, as we may be disassembling some raw bytes on a baremetal
11837 HEX file or similar. */
11838 enum map_type type = MAP_DATA;
11839 if ((info->section && info->section->flags & SEC_CODE) || !info->section)
11840 type = MAP_ARM;
5bc5ae88
RL		 11841 struct arm_private_data *private_data;
11842
796d6298 11843 if (info->private_data == NULL
5bc5ae88
RL		 11844 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
11845 return FALSE;
11846
11847 private_data = info->private_data;
5bc5ae88 11848
796d6298
TC		 11849 /* First, look for mapping symbols. */
11850 if (info->symtab_size != 0)
11851 {
11852 if (pc <= private_data->last_mapping_addr)
11853 private_data->last_mapping_sym = -1;
11854
11855 /* Start scanning at the start of the function, or wherever
11856 we finished last time. */
11857 n = info->symtab_pos + 1;
11858
11859 /* If the last stop offset is different from the current one it means we
11860 are disassembling a different glob of bytes. As such the optimization
11861 would not be safe and we should start over. */
11862 can_use_search_opt_p
11863 = private_data->last_mapping_sym >= 0
11864 && info->stop_offset == private_data->last_stop_offset;
11865
11866 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11867 n = private_data->last_mapping_sym;
11868
11869 /* Look down while we haven't passed the location being disassembled.
11870 The reason for this is that there's no defined order between a symbol
11871 and an mapping symbol that may be at the same address. We may have to
11872 look at least one position ahead. */
11873 for (; n < info->symtab_size; n++)
11874 {
11875 addr = bfd_asymbol_value (info->symtab[n]);
11876 if (addr > pc)
11877 break;
11878 if (get_map_sym_type (info, n, &type))
11879 {
11880 last_sym = n;
11881 found = TRUE;
11882 }
11883 }
5bc5ae88 11884
796d6298
TC		 11885 if (!found)
11886 {
11887 n = info->symtab_pos;
11888 if (n >= private_data->last_mapping_sym && can_use_search_opt_p)
11889 n = private_data->last_mapping_sym;
11890
11891 /* No mapping symbol found at this address. Look backwards
11892 for a preceeding one, but don't go pass the section start
11893 otherwise a data section with no mapping symbol can pick up
11894 a text mapping symbol of a preceeding section. The documentation
11895 says section can be NULL, in which case we will seek up all the
11896 way to the top. */
11897 if (info->section)
11898 section_vma = info->section->vma;
11899
11900 for (; n >= 0; n--)
11901 {
11902 addr = bfd_asymbol_value (info->symtab[n]);
11903 if (addr < section_vma)
11904 break;
11905
11906 if (get_map_sym_type (info, n, &type))
11907 {
11908 last_sym = n;
11909 found = TRUE;
11910 break;
11911 }
11912 }
11913 }
11914 }
11915
11916 /* If no mapping symbol was found, try looking up without a mapping
11917 symbol. This is done by walking up from the current PC to the nearest
11918 symbol. We don't actually have to loop here since symtab_pos will
11919 contain the nearest symbol already. */
11920 if (!found)
5bc5ae88 11921 {
796d6298
TC		 11922 n = info->symtab_pos;
11923 if (n >= 0 && get_sym_code_type (info, n, &type))
5bc5ae88 11924 {
796d6298
TC		 11925 last_sym = n;
11926 found = TRUE;
5bc5ae88
RL		 11927 }
11928 }
11929
796d6298
TC		 11930 private_data->last_mapping_sym = last_sym;
11931 private_data->last_type = type;
11932 private_data->last_stop_offset = info->stop_offset;
5bc5ae88
RL		 11933
11934 *map_symbol = type;
11935 return found;
11936}
11937
0313a2b8
NC		 11938/* Given a bfd_mach_arm_XXX value, this function fills in the fields
11939 of the supplied arm_feature_set structure with bitmasks indicating
c0c468d5 11940 the supported base architectures and coprocessor extensions.
0313a2b8
NC		 11941
11942 FIXME: This could more efficiently implemented as a constant array,
11943 although it would also be less robust. */
11944
11945static void
11946select_arm_features (unsigned long mach,
11947 arm_feature_set * features)
11948{
c0c468d5
TP		 11949 arm_feature_set arch_fset;
11950 const arm_feature_set fpu_any = FPU_ANY;
11951
1af1dd51
MW		 11952#undef ARM_SET_FEATURES
11953#define ARM_SET_FEATURES(FSET) \
11954 { \
11955 const arm_feature_set fset = FSET; \
c0c468d5 11956 arch_fset = fset; \
1af1dd51 11957 }
823d2571 11958
c0c468d5
TP		 11959 /* When several architecture versions share the same bfd_mach_arm_XXX value
11960 the most featureful is chosen. */
0313a2b8
NC		 11961 switch (mach)
11962 {
c0c468d5
TP		 11963 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
11964 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
11965 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
11966 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
11967 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
11968 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
11969 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
11970 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
11971 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
11972 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
1af1dd51 11973 case bfd_mach_arm_ep9312:
c0c468d5
TP		 11974 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
11975 ARM_CEXT_MAVERICK | FPU_MAVERICK));
1af1dd51 11976 break;
c0c468d5
TP		 11977 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
11978 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
11979 case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
11980 case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
11981 case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
11982 case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
11983 case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
11984 case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
11985 case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
11986 case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
11987 case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
11988 case bfd_mach_arm_8:
11989 {
aab2c27d
MM		 11990 /* Add bits for extensions that Armv8.6-A recognizes. */
11991 arm_feature_set armv8_6_ext_fset
0632eeea 11992 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
aab2c27d
MM		 11993 ARM_SET_FEATURES (ARM_ARCH_V8_6A);
11994 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset);
c0c468d5
TP		 11995 break;
11996 }
11997 case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
11998 case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
11999 case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
73cd51e5
AV		 12000 case bfd_mach_arm_8_1M_MAIN:
12001 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
2da2eaf4
AV		 12002 arm_feature_set mve_all
12003 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP);
12004 ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all);
73cd51e5
AV		 12005 force_thumb = 1;
12006 break;
c0c468d5 12007 /* If the machine type is unknown allow all architecture types and all
2da2eaf4
AV		 12008 extensions, with the exception of MVE as that clashes with NEON. */
12009 case bfd_mach_arm_unknown:
12010 ARM_SET_FEATURES (ARM_FEATURE (-1,
12011 -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP),
12012 -1));
12013 break;
0313a2b8
NC		 12014 default:
12015 abort ();
12016 }
1af1dd51 12017#undef ARM_SET_FEATURES
c0c468d5
TP		 12018
12019 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12020 and thus on bfd_mach_arm_XXX value. Therefore for a given
12021 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12022 ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
0313a2b8
NC		 12023}
12024
12025
58efb6c0
NC		 12026/* NOTE: There are no checks in these routines that
12027 the relevant number of data bytes exist. */
baf0cc5e 12028
58efb6c0 12029static int
4a5329c6 12030print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
252b5132 12031{
c19d1205 12032 unsigned char b[4];
2480b6fa 12033 unsigned long given;
c19d1205 12034 int status;
e821645d 12035 int is_thumb = FALSE;
b0e28b39 12036 int is_data = FALSE;
bd2e2557 12037 int little_code;
e821645d 12038 unsigned int size = 4;
4a5329c6 12039 void (*printer) (bfd_vma, struct disassemble_info *, long);
e821645d 12040 bfd_boolean found = FALSE;
b0e28b39 12041 struct arm_private_data *private_data;
58efb6c0 12042
1d67fe3b
TT		 12043 /* Clear instruction information field. */
12044 info->insn_info_valid = 0;
12045 info->branch_delay_insns = 0;
12046 info->data_size = 0;
12047 info->insn_type = dis_noninsn;
12048 info->target = 0;
12049 info->target2 = 0;
12050
dd92f639
NC		 12051 if (info->disassembler_options)
12052 {
65b48a81 12053 parse_arm_disassembler_options (info->disassembler_options);
b34976b6 12054
58efb6c0 12055 /* To avoid repeated parsing of these options, we remove them here. */
dd92f639
NC		 12056 info->disassembler_options = NULL;
12057 }
b34976b6 12058
0313a2b8
NC		 12059 /* PR 10288: Control which instructions will be disassembled. */
12060 if (info->private_data == NULL)
12061 {
b0e28b39 12062 static struct arm_private_data private;
0313a2b8
NC		 12063
12064 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
12065 /* If the user did not use the -m command line switch then default to
12066 disassembling all types of ARM instruction.
43e65147 12067
0313a2b8
NC		 12068 The info->mach value has to be ignored as this will be based on
12069 the default archictecture for the target and/or hints in the notes
12070 section, but it will never be greater than the current largest arm
12071 machine value (iWMMXt2), which is only equivalent to the V5TE
12072 architecture. ARM architectures have advanced beyond the machine
12073 value encoding, and these newer architectures would be ignored if
12074 the machine value was used.
12075
12076 Ie the -m switch is used to restrict which instructions will be
12077 disassembled. If it is necessary to use the -m switch to tell
12078 objdump that an ARM binary is being disassembled, eg because the
12079 input is a raw binary file, but it is also desired to disassemble
12080 all ARM instructions then use "-marm". This will select the
12081 "unknown" arm architecture which is compatible with any ARM
12082 instruction. */
12083 info->mach = bfd_mach_arm_unknown;
12084
12085 /* Compute the architecture bitmask from the machine number.
12086 Note: This assumes that the machine number will not change
12087 during disassembly.... */
b0e28b39 12088 select_arm_features (info->mach, & private.features);
0313a2b8 12089
1fbaefec
PB		 12090 private.last_mapping_sym = -1;
12091 private.last_mapping_addr = 0;
796d6298 12092 private.last_stop_offset = 0;
b0e28b39
DJ		 12093
12094 info->private_data = & private;
0313a2b8 12095 }
b0e28b39
DJ		 12096
12097 private_data = info->private_data;
12098
bd2e2557
SS		 12099 /* Decide if our code is going to be little-endian, despite what the
12100 function argument might say. */
12101 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
12102
b0e28b39
DJ		 12103 /* For ELF, consult the symbol table to determine what kind of code
12104 or data we have. */
8977d4b2 12105 if (info->symtab_size != 0
e821645d
DJ		 12106 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
12107 {
12108 bfd_vma addr;
796d6298 12109 int n;
e821645d 12110 int last_sym = -1;
b0e28b39 12111 enum map_type type = MAP_ARM;
e821645d 12112
796d6298
TC		 12113 found = mapping_symbol_for_insn (pc, info, &type);
12114 last_sym = private_data->last_mapping_sym;
e821645d 12115
1fbaefec
PB		 12116 is_thumb = (private_data->last_type == MAP_THUMB);
12117 is_data = (private_data->last_type == MAP_DATA);
b34976b6 12118
e821645d
DJ		 12119 /* Look a little bit ahead to see if we should print out
12120 two or four bytes of data. If there's a symbol,
12121 mapping or otherwise, after two bytes then don't
12122 print more. */
12123 if (is_data)
12124 {
12125 size = 4 - (pc & 3);
12126 for (n = last_sym + 1; n < info->symtab_size; n++)
12127 {
12128 addr = bfd_asymbol_value (info->symtab[n]);
e3e535bc
NC		 12129 if (addr > pc
12130 && (info->section == NULL
12131 || info->section == info->symtab[n]->section))
e821645d
DJ		 12132 {
12133 if (addr - pc < size)
12134 size = addr - pc;
12135 break;
12136 }
12137 }
12138 /* If the next symbol is after three bytes, we need to
12139 print only part of the data, so that we can use either
12140 .byte or .short. */
12141 if (size == 3)
12142 size = (pc & 1) ? 1 : 2;
12143 }
12144 }
12145
12146 if (info->symbols != NULL)
252b5132 12147 {
5876e06d
NC		 12148 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
12149 {
2f0ca46a 12150 coff_symbol_type * cs;
b34976b6 12151
5876e06d
NC		 12152 cs = coffsymbol (*info->symbols);
12153 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
12154 || cs->native->u.syment.n_sclass == C_THUMBSTAT
12155 || cs->native->u.syment.n_sclass == C_THUMBLABEL
12156 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
12157 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
12158 }
e821645d
DJ		 12159 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
12160 && !found)
5876e06d 12161 {
2087ad84
PB		 12162 /* If no mapping symbol has been found then fall back to the type
12163 of the function symbol. */
e821645d
DJ		 12164 elf_symbol_type * es;
12165 unsigned int type;
2087ad84 12166
e821645d
DJ		 12167 es = *(elf_symbol_type **)(info->symbols);
12168 type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
2087ad84 12169
39d911fc
TP		 12170 is_thumb =
12171 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
12172 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
5876e06d 12173 }
e49d43ff
TG		 12174 else if (bfd_asymbol_flavour (*info->symbols)
12175 == bfd_target_mach_o_flavour)
12176 {
12177 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
12178
12179 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
12180 }
5876e06d 12181 }
b34976b6 12182
e821645d
DJ		 12183 if (force_thumb)
12184 is_thumb = TRUE;
12185
b8f9ee44
CL		 12186 if (is_data)
12187 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12188 else
12189 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
12190
c19d1205 12191 info->bytes_per_line = 4;
252b5132 12192
1316c8b3
NC		 12193 /* PR 10263: Disassemble data if requested to do so by the user. */
12194 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
e821645d
DJ		 12195 {
12196 int i;
12197
1316c8b3 12198 /* Size was already set above. */
e821645d
DJ		 12199 info->bytes_per_chunk = size;
12200 printer = print_insn_data;
12201
fe56b6ce 12202 status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
e821645d
DJ		 12203 given = 0;
12204 if (little)
12205 for (i = size - 1; i >= 0; i--)
12206 given = b[i] | (given << 8);
12207 else
12208 for (i = 0; i < (int) size; i++)
12209 given = b[i] | (given << 8);
12210 }
12211 else if (!is_thumb)
252b5132 12212 {
c19d1205
ZW		 12213 /* In ARM mode endianness is a straightforward issue: the instruction
12214 is four bytes long and is either ordered 0123 or 3210. */
12215 printer = print_insn_arm;
12216 info->bytes_per_chunk = 4;
4a5329c6 12217 size = 4;
c19d1205 12218
0313a2b8 12219 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
bd2e2557 12220 if (little_code)
2480b6fa 12221 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
c19d1205 12222 else
2480b6fa 12223 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
252b5132 12224 }
58efb6c0 12225 else
252b5132 12226 {
c19d1205
ZW		 12227 /* In Thumb mode we have the additional wrinkle of two
12228 instruction lengths. Fortunately, the bits that determine
12229 the length of the current instruction are always to be found
12230 in the first two bytes. */
4a5329c6 12231 printer = print_insn_thumb16;
c19d1205 12232 info->bytes_per_chunk = 2;
4a5329c6
ZW		 12233 size = 2;
12234
fe56b6ce 12235 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
bd2e2557 12236 if (little_code)
9a2ff3f5
AM		 12237 given = (b[0]) | (b[1] << 8);
12238 else
12239 given = (b[1]) | (b[0] << 8);
12240
c19d1205 12241 if (!status)
252b5132 12242 {
c19d1205
ZW		 12243 /* These bit patterns signal a four-byte Thumb
12244 instruction. */
12245 if ((given & 0xF800) == 0xF800
12246 || (given & 0xF800) == 0xF000
12247 || (given & 0xF800) == 0xE800)
252b5132 12248 {
0313a2b8 12249 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
bd2e2557 12250 if (little_code)
c19d1205 12251 given = (b[0]) | (b[1] << 8) | (given << 16);
b7693d02 12252 else
c19d1205
ZW		 12253 given = (b[1]) | (b[0] << 8) | (given << 16);
12254
12255 printer = print_insn_thumb32;
4a5329c6 12256 size = 4;
252b5132 12257 }
252b5132 12258 }
c22aaad1
PB		 12259
12260 if (ifthen_address != pc)
0313a2b8 12261 find_ifthen_state (pc, info, little_code);
c22aaad1
PB		 12262
12263 if (ifthen_state)
12264 {
12265 if ((ifthen_state & 0xf) == 0x8)
12266 ifthen_next_state = 0;
12267 else
12268 ifthen_next_state = (ifthen_state & 0xe0)
12269 | ((ifthen_state & 0xf) << 1);
12270 }
252b5132 12271 }
b34976b6 12272
c19d1205
ZW		 12273 if (status)
12274 {
12275 info->memory_error_func (status, pc, info);
12276 return -1;
12277 }
6a56ec7e
NC		 12278 if (info->flags & INSN_HAS_RELOC)
12279 /* If the instruction has a reloc associated with it, then
12280 the offset field in the instruction will actually be the
12281 addend for the reloc. (We are using REL type relocs).
12282 In such cases, we can ignore the pc when computing
12283 addresses, since the addend is not currently pc-relative. */
12284 pc = 0;
b34976b6 12285
4a5329c6 12286 printer (pc, info, given);
c22aaad1
PB		 12287
12288 if (is_thumb)
12289 {
12290 ifthen_state = ifthen_next_state;
12291 ifthen_address += size;
12292 }
4a5329c6 12293 return size;
252b5132
RH		 12294}
12295
12296int
4a5329c6 12297print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
252b5132 12298{
bd2e2557
SS		 12299 /* Detect BE8-ness and record it in the disassembler info. */
12300 if (info->flavour == bfd_target_elf_flavour
12301 && info->section != NULL
12302 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
12303 info->endian_code = BFD_ENDIAN_LITTLE;
12304
b34976b6 12305 return print_insn (pc, info, FALSE);
58efb6c0 12306}
01c7f630 12307
58efb6c0 12308int
4a5329c6 12309print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
58efb6c0 12310{
b34976b6 12311 return print_insn (pc, info, TRUE);
58efb6c0 12312}
252b5132 12313
471b9d15 12314const disasm_options_and_args_t *
65b48a81
PB		 12315disassembler_options_arm (void)
12316{
471b9d15 12317 static disasm_options_and_args_t *opts_and_args;
65b48a81 12318
471b9d15 12319 if (opts_and_args == NULL)
65b48a81 12320 {
471b9d15 12321 disasm_options_t *opts;
65b48a81 12322 unsigned int i;
471b9d15
MR		 12323
12324 opts_and_args = XNEW (disasm_options_and_args_t);
12325 opts_and_args->args = NULL;
12326
12327 opts = &opts_and_args->options;
65b48a81
PB		 12328 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
12329 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
471b9d15 12330 opts->arg = NULL;
65b48a81
PB		 12331 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12332 {
12333 opts->name[i] = regnames[i].name;
12334 if (regnames[i].description != NULL)
12335 opts->description[i] = _(regnames[i].description);
12336 else
12337 opts->description[i] = NULL;
12338 }
12339 /* The array we return must be NULL terminated. */
12340 opts->name[i] = NULL;
12341 opts->description[i] = NULL;
12342 }
12343
471b9d15 12344 return opts_and_args;
65b48a81
PB		 12345}
12346
58efb6c0 12347void
4a5329c6 12348print_arm_disassembler_options (FILE *stream)
58efb6c0 12349{
65b48a81 12350 unsigned int i, max_len = 0;
58efb6c0
NC		 12351 fprintf (stream, _("\n\
12352The following ARM specific disassembler options are supported for use with\n\
12353the -M switch:\n"));
b34976b6 12354
65b48a81
PB		 12355 for (i = 0; i < NUM_ARM_OPTIONS; i++)
12356 {
12357 unsigned int len = strlen (regnames[i].name);
12358 if (max_len < len)
12359 max_len = len;
12360 }
58efb6c0 12361
65b48a81
PB		 12362 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
12363 fprintf (stream, " %s%*c %s\n",
12364 regnames[i].name,
12365 (int)(max_len - strlen (regnames[i].name)), ' ',
12366 _(regnames[i].description));
252b5132 12367}
GDB Binutils - Deliverables
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