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[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
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252b5132 1/* Print i386 instructions for GDB, the GNU debugger.
060d22b0 2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0f10071e 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
252b5132
RH		 4
5This file is part of GDB.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2 of the License, or
10(at your option) any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21/*
22 * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 * July 1988
24 * modified by John Hassey (hassey@dg-rtp.dg.com)
52b15da3 25 * x86-64 support added by Jan Hubicka (jh@suse.cz)
0f10071e 26 * VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
252b5132
RH		 27 */
28
29/*
30 * The main tables describing the instructions is essentially a copy
31 * of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 * Programmers Manual. Usually, there is a capital letter, followed
33 * by a small letter. The capital letter tell the addressing mode,
34 * and the small letter tells about the operand size. Refer to
35 * the Intel manual for details.
36 */
37
38#include "dis-asm.h"
39#include "sysdep.h"
40#include "opintl.h"
41
42#define MAXLEN 20
43
44#include <setjmp.h>
45
46#ifndef UNIXWARE_COMPAT
47/* Set non-zero for broken, compatible instructions. Set to zero for
48 non-broken opcodes. */
49#define UNIXWARE_COMPAT 1
50#endif
51
26ca5450
AJ		 52static int fetch_data (struct disassemble_info *, bfd_byte *);
53static void ckprefix (void);
54static const char *prefix_name (int, int);
55static int print_insn (bfd_vma, disassemble_info *);
56static void dofloat (int);
57static void OP_ST (int, int);
58static void OP_STi (int, int);
59static int putop (const char *, int);
60static void oappend (const char *);
61static void append_seg (void);
62static void OP_indirE (int, int);
63static void print_operand_value (char *, int, bfd_vma);
64static void OP_E (int, int);
65static void OP_G (int, int);
66static bfd_vma get64 (void);
67static bfd_signed_vma get32 (void);
68static bfd_signed_vma get32s (void);
69static int get16 (void);
70static void set_op (bfd_vma, int);
71static void OP_REG (int, int);
72static void OP_IMREG (int, int);
73static void OP_I (int, int);
74static void OP_I64 (int, int);
75static void OP_sI (int, int);
76static void OP_J (int, int);
77static void OP_SEG (int, int);
78static void OP_DIR (int, int);
79static void OP_OFF (int, int);
80static void OP_OFF64 (int, int);
81static void ptr_reg (int, int);
82static void OP_ESreg (int, int);
83static void OP_DSreg (int, int);
84static void OP_C (int, int);
85static void OP_D (int, int);
86static void OP_T (int, int);
87static void OP_Rd (int, int);
88static void OP_MMX (int, int);
89static void OP_XMM (int, int);
90static void OP_EM (int, int);
91static void OP_EX (int, int);
92static void OP_MS (int, int);
93static void OP_XS (int, int);
94static void OP_3DNowSuffix (int, int);
95static void OP_SIMD_Suffix (int, int);
96static void SIMD_Fixup (int, int);
97static void PNI_Fixup (int, int);
4fd61dcb 98static void INVLPG_Fixup (int, int);
26ca5450 99static void BadOp (void);
252b5132 100
6608db57 101struct dis_private {
252b5132
RH		 102 /* Points to first byte not fetched. */
103 bfd_byte *max_fetched;
104 bfd_byte the_buffer[MAXLEN];
105 bfd_vma insn_start;
e396998b 106 int orig_sizeflag;
252b5132
RH		 107 jmp_buf bailout;
108};
109
5076851f
ILT		 110/* The opcode for the fwait instruction, which we treat as a prefix
111 when we can. */
112#define FWAIT_OPCODE (0x9b)
113
52b15da3
JH		 114/* Set to 1 for 64bit mode disassembly. */
115static int mode_64bit;
116
5076851f
ILT		 117/* Flags for the prefixes for the current instruction. See below. */
118static int prefixes;
119
52b15da3
JH		 120/* REX prefix the current instruction. See below. */
121static int rex;
122/* Bits of REX we've already used. */
123static int rex_used;
124#define REX_MODE64 8
125#define REX_EXTX 4
126#define REX_EXTY 2
127#define REX_EXTZ 1
128/* Mark parts used in the REX prefix. When we are testing for
129 empty prefix (for 8bit register REX extension), just mask it
130 out. Otherwise test for REX bit is excuse for existence of REX
131 only in case value is nonzero. */
132#define USED_REX(value) \
133 { \
134 if (value) \
135 rex_used |= (rex & value) ? (value) | 0x40 : 0; \
136 else \
137 rex_used |= 0x40; \
138 }
139
7d421014
ILT		 140/* Flags for prefixes which we somehow handled when printing the
141 current instruction. */
142static int used_prefixes;
143
5076851f
ILT		 144/* Flags stored in PREFIXES. */
145#define PREFIX_REPZ 1
146#define PREFIX_REPNZ 2
147#define PREFIX_LOCK 4
148#define PREFIX_CS 8
149#define PREFIX_SS 0x10
150#define PREFIX_DS 0x20
151#define PREFIX_ES 0x40
152#define PREFIX_FS 0x80
153#define PREFIX_GS 0x100
154#define PREFIX_DATA 0x200
155#define PREFIX_ADDR 0x400
156#define PREFIX_FWAIT 0x800
157
252b5132
RH		 158/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
159 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
160 on error. */
161#define FETCH_DATA(info, addr) \
6608db57 162 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
252b5132
RH		 163 ? 1 : fetch_data ((info), (addr)))
164
165static int
26ca5450 166fetch_data (struct disassemble_info *info, bfd_byte *addr)
252b5132
RH		 167{
168 int status;
6608db57 169 struct dis_private *priv = (struct dis_private *) info->private_data;
252b5132
RH		 170 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
171
172 status = (*info->read_memory_func) (start,
173 priv->max_fetched,
174 addr - priv->max_fetched,
175 info);
176 if (status != 0)
177 {
7d421014 178 /* If we did manage to read at least one byte, then
db6eb5be
AM		 179 print_insn_i386 will do something sensible. Otherwise, print
180 an error. We do that here because this is where we know
181 STATUS. */
7d421014 182 if (priv->max_fetched == priv->the_buffer)
5076851f 183 (*info->memory_error_func) (status, start, info);
252b5132
RH		 184 longjmp (priv->bailout, 1);
185 }
186 else
187 priv->max_fetched = addr;
188 return 1;
189}
190
57d91c3c
ILT		 191#define XX NULL, 0
192
252b5132 193#define Eb OP_E, b_mode
52b15da3
JH		 194#define Ev OP_E, v_mode
195#define Ed OP_E, d_mode
db6eb5be 196#define Edq OP_E, dq_mode
252b5132 197#define indirEb OP_indirE, b_mode
252b5132
RH		 198#define indirEv OP_indirE, v_mode
199#define Ew OP_E, w_mode
200#define Ma OP_E, v_mode
bcb5558b 201#define M OP_E, 0 /* lea, lgdt, etc. */
2da11e11 202#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */
992aaec9 203#define Gb OP_G, b_mode
252b5132 204#define Gv OP_G, v_mode
992aaec9 205#define Gd OP_G, d_mode
252b5132 206#define Gw OP_G, w_mode
2da11e11 207#define Rd OP_Rd, d_mode
52b15da3 208#define Rm OP_Rd, m_mode
252b5132
RH		 209#define Ib OP_I, b_mode
210#define sIb OP_sI, b_mode /* sign extened byte */
211#define Iv OP_I, v_mode
52b15da3
JH		 212#define Iq OP_I, q_mode
213#define Iv64 OP_I64, v_mode
252b5132
RH		 214#define Iw OP_I, w_mode
215#define Jb OP_J, b_mode
216#define Jv OP_J, v_mode
52b15da3
JH		 217#define Cm OP_C, m_mode
218#define Dm OP_D, m_mode
252b5132
RH		 219#define Td OP_T, d_mode
220
52b15da3
JH		 221#define RMeAX OP_REG, eAX_reg
222#define RMeBX OP_REG, eBX_reg
223#define RMeCX OP_REG, eCX_reg
224#define RMeDX OP_REG, eDX_reg
225#define RMeSP OP_REG, eSP_reg
226#define RMeBP OP_REG, eBP_reg
227#define RMeSI OP_REG, eSI_reg
228#define RMeDI OP_REG, eDI_reg
229#define RMrAX OP_REG, rAX_reg
230#define RMrBX OP_REG, rBX_reg
231#define RMrCX OP_REG, rCX_reg
232#define RMrDX OP_REG, rDX_reg
233#define RMrSP OP_REG, rSP_reg
234#define RMrBP OP_REG, rBP_reg
235#define RMrSI OP_REG, rSI_reg
236#define RMrDI OP_REG, rDI_reg
237#define RMAL OP_REG, al_reg
238#define RMAL OP_REG, al_reg
239#define RMCL OP_REG, cl_reg
240#define RMDL OP_REG, dl_reg
241#define RMBL OP_REG, bl_reg
242#define RMAH OP_REG, ah_reg
243#define RMCH OP_REG, ch_reg
244#define RMDH OP_REG, dh_reg
245#define RMBH OP_REG, bh_reg
246#define RMAX OP_REG, ax_reg
247#define RMDX OP_REG, dx_reg
248
249#define eAX OP_IMREG, eAX_reg
250#define eBX OP_IMREG, eBX_reg
251#define eCX OP_IMREG, eCX_reg
252#define eDX OP_IMREG, eDX_reg
253#define eSP OP_IMREG, eSP_reg
254#define eBP OP_IMREG, eBP_reg
255#define eSI OP_IMREG, eSI_reg
256#define eDI OP_IMREG, eDI_reg
257#define AL OP_IMREG, al_reg
258#define AL OP_IMREG, al_reg
259#define CL OP_IMREG, cl_reg
260#define DL OP_IMREG, dl_reg
261#define BL OP_IMREG, bl_reg
262#define AH OP_IMREG, ah_reg
263#define CH OP_IMREG, ch_reg
264#define DH OP_IMREG, dh_reg
265#define BH OP_IMREG, bh_reg
266#define AX OP_IMREG, ax_reg
267#define DX OP_IMREG, dx_reg
268#define indirDX OP_IMREG, indir_dx_reg
252b5132
RH		 269
270#define Sw OP_SEG, w_mode
c608c12e 271#define Ap OP_DIR, 0
252b5132 272#define Ob OP_OFF, b_mode
52b15da3 273#define Ob64 OP_OFF64, b_mode
252b5132 274#define Ov OP_OFF, v_mode
52b15da3 275#define Ov64 OP_OFF64, v_mode
252b5132
RH		 276#define Xb OP_DSreg, eSI_reg
277#define Xv OP_DSreg, eSI_reg
278#define Yb OP_ESreg, eDI_reg
279#define Yv OP_ESreg, eDI_reg
280#define DSBX OP_DSreg, eBX_reg
281
282#define es OP_REG, es_reg
283#define ss OP_REG, ss_reg
284#define cs OP_REG, cs_reg
285#define ds OP_REG, ds_reg
286#define fs OP_REG, fs_reg
287#define gs OP_REG, gs_reg
288
289#define MX OP_MMX, 0
c608c12e 290#define XM OP_XMM, 0
252b5132 291#define EM OP_EM, v_mode
c608c12e 292#define EX OP_EX, v_mode
2da11e11 293#define MS OP_MS, v_mode
992aaec9 294#define XS OP_XS, v_mode
c608c12e 295#define None OP_E, 0
252b5132 296#define OPSUF OP_3DNowSuffix, 0
c608c12e 297#define OPSIMD OP_SIMD_Suffix, 0
252b5132 298
3ffd33cf
AM		 299#define cond_jump_flag NULL, cond_jump_mode
300#define loop_jcxz_flag NULL, loop_jcxz_mode
301
252b5132 302/* bits in sizeflag */
252b5132 303#define SUFFIX_ALWAYS 4
252b5132
RH		 304#define AFLAG 2
305#define DFLAG 1
306
52b15da3
JH		 307#define b_mode 1 /* byte operand */
308#define v_mode 2 /* operand size depends on prefixes */
309#define w_mode 3 /* word operand */
310#define d_mode 4 /* double word operand */
311#define q_mode 5 /* quad word operand */
312#define x_mode 6
313#define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */
3ffd33cf
AM		 314#define cond_jump_mode 8
315#define loop_jcxz_mode 9
db6eb5be 316#define dq_mode 10 /* operand size depends on REX prefixes. */
252b5132
RH		 317
318#define es_reg 100
319#define cs_reg 101
320#define ss_reg 102
321#define ds_reg 103
322#define fs_reg 104
323#define gs_reg 105
252b5132 324
c608c12e
AM		 325#define eAX_reg 108
326#define eCX_reg 109
327#define eDX_reg 110
328#define eBX_reg 111
329#define eSP_reg 112
330#define eBP_reg 113
331#define eSI_reg 114
332#define eDI_reg 115
252b5132
RH		 333
334#define al_reg 116
335#define cl_reg 117
336#define dl_reg 118
337#define bl_reg 119
338#define ah_reg 120
339#define ch_reg 121
340#define dh_reg 122
341#define bh_reg 123
342
343#define ax_reg 124
344#define cx_reg 125
345#define dx_reg 126
346#define bx_reg 127
347#define sp_reg 128
348#define bp_reg 129
349#define si_reg 130
350#define di_reg 131
351
52b15da3
JH		 352#define rAX_reg 132
353#define rCX_reg 133
354#define rDX_reg 134
355#define rBX_reg 135
356#define rSP_reg 136
357#define rBP_reg 137
358#define rSI_reg 138
359#define rDI_reg 139
360
252b5132
RH		 361#define indir_dx_reg 150
362
6439fc28
AM		 363#define FLOATCODE 1
364#define USE_GROUPS 2
365#define USE_PREFIX_USER_TABLE 3
366#define X86_64_SPECIAL 4
0f10071e 367#define PADLOCK_SPECIAL 5
6439fc28
AM		 368
369#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
370
371#define GRP1b NULL, NULL, USE_GROUPS, NULL, 0, NULL, 0
372#define GRP1S NULL, NULL, USE_GROUPS, NULL, 1, NULL, 0
373#define GRP1Ss NULL, NULL, USE_GROUPS, NULL, 2, NULL, 0
374#define GRP2b NULL, NULL, USE_GROUPS, NULL, 3, NULL, 0
375#define GRP2S NULL, NULL, USE_GROUPS, NULL, 4, NULL, 0
376#define GRP2b_one NULL, NULL, USE_GROUPS, NULL, 5, NULL, 0
377#define GRP2S_one NULL, NULL, USE_GROUPS, NULL, 6, NULL, 0
378#define GRP2b_cl NULL, NULL, USE_GROUPS, NULL, 7, NULL, 0
379#define GRP2S_cl NULL, NULL, USE_GROUPS, NULL, 8, NULL, 0
380#define GRP3b NULL, NULL, USE_GROUPS, NULL, 9, NULL, 0
381#define GRP3S NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0
382#define GRP4 NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0
383#define GRP5 NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0
384#define GRP6 NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0
385#define GRP7 NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0
386#define GRP8 NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0
387#define GRP9 NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0
388#define GRP10 NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0
389#define GRP11 NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0
390#define GRP12 NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0
391#define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0
392#define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0
393#define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0
0f10071e 394#define GRPPLOCK NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0
6439fc28
AM		 395
396#define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0
397#define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0
398#define PREGRP2 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 2, NULL, 0
399#define PREGRP3 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 3, NULL, 0
400#define PREGRP4 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 4, NULL, 0
401#define PREGRP5 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 5, NULL, 0
402#define PREGRP6 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 6, NULL, 0
403#define PREGRP7 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 7, NULL, 0
404#define PREGRP8 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 8, NULL, 0
405#define PREGRP9 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 9, NULL, 0
406#define PREGRP10 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0
407#define PREGRP11 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0
408#define PREGRP12 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0
409#define PREGRP13 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0
410#define PREGRP14 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0
411#define PREGRP15 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0
412#define PREGRP16 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0
413#define PREGRP17 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0
414#define PREGRP18 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0
415#define PREGRP19 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0
416#define PREGRP20 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0
417#define PREGRP21 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0
418#define PREGRP22 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0
419#define PREGRP23 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0
420#define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0
421#define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0
422#define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0
ca164297
L		 423#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0
424#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0
425#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0
426#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0
427#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0
428#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0
6439fc28
AM		 429
430#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0
431
0f10071e
ML		 432#define PADLOCK_0 NULL, NULL, PADLOCK_SPECIAL, NULL, 0, NULL, 0
433
26ca5450 434typedef void (*op_rtn) (int bytemode, int sizeflag);
252b5132
RH		 435
436struct dis386 {
2da11e11 437 const char *name;
252b5132
RH		 438 op_rtn op1;
439 int bytemode1;
440 op_rtn op2;
441 int bytemode2;
442 op_rtn op3;
443 int bytemode3;
444};
445
446/* Upper case letters in the instruction names here are macros.
447 'A' => print 'b' if no register operands or suffix_always is true
448 'B' => print 'b' if suffix_always is true
449 'E' => print 'e' if 32-bit form of jcxz
3ffd33cf 450 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
5dd0794d 451 'H' => print ",pt" or ",pn" branch hint
252b5132
RH		 452 'L' => print 'l' if suffix_always is true
453 'N' => print 'n' if instruction has no wait "prefix"
52b15da3
JH		 454 'O' => print 'd', or 'o'
455 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
e396998b
AM		 456 . or suffix_always is true. print 'q' if rex prefix is present.
457 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
458 . is true
52b15da3
JH		 459 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)
460 'S' => print 'w', 'l' or 'q' if suffix_always is true
6439fc28
AM		 461 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
462 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
041bd2e0 463 'X' => print 's', 'd' depending on data16 prefix (for XMM)
10084519 464 'W' => print 'b' or 'w' ("w" or "de" in intel mode)
76f227a5 465 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
52b15da3 466
6439fc28
AM		 467 Many of the above letters print nothing in Intel mode. See "putop"
468 for the details.
52b15da3 469
6439fc28
AM		 470 Braces '{' and '}', and vertical bars '|', indicate alternative
471 mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
472 modes. In cases where there are only two alternatives, the X86_64
473 instruction is reserved, and "(bad)" is printed.
474*/
252b5132 475
6439fc28 476static const struct dis386 dis386[] = {
252b5132 477 /* 00 */
6439fc28
AM		 478 { "addB", Eb, Gb, XX },
479 { "addS", Ev, Gv, XX },
480 { "addB", Gb, Eb, XX },
481 { "addS", Gv, Ev, XX },
482 { "addB", AL, Ib, XX },
483 { "addS", eAX, Iv, XX },
484 { "push{T|}", es, XX, XX },
485 { "pop{T|}", es, XX, XX },
252b5132 486 /* 08 */
6439fc28
AM		 487 { "orB", Eb, Gb, XX },
488 { "orS", Ev, Gv, XX },
489 { "orB", Gb, Eb, XX },
490 { "orS", Gv, Ev, XX },
491 { "orB", AL, Ib, XX },
492 { "orS", eAX, Iv, XX },
493 { "push{T|}", cs, XX, XX },
494 { "(bad)", XX, XX, XX }, /* 0x0f extended opcode escape */
252b5132 495 /* 10 */
6439fc28
AM		 496 { "adcB", Eb, Gb, XX },
497 { "adcS", Ev, Gv, XX },
498 { "adcB", Gb, Eb, XX },
499 { "adcS", Gv, Ev, XX },
500 { "adcB", AL, Ib, XX },
501 { "adcS", eAX, Iv, XX },
502 { "push{T|}", ss, XX, XX },
503 { "popT|}", ss, XX, XX },
252b5132 504 /* 18 */
6439fc28
AM		 505 { "sbbB", Eb, Gb, XX },
506 { "sbbS", Ev, Gv, XX },
507 { "sbbB", Gb, Eb, XX },
508 { "sbbS", Gv, Ev, XX },
509 { "sbbB", AL, Ib, XX },
510 { "sbbS", eAX, Iv, XX },
511 { "push{T|}", ds, XX, XX },
512 { "pop{T|}", ds, XX, XX },
252b5132 513 /* 20 */
6439fc28
AM		 514 { "andB", Eb, Gb, XX },
515 { "andS", Ev, Gv, XX },
516 { "andB", Gb, Eb, XX },
517 { "andS", Gv, Ev, XX },
518 { "andB", AL, Ib, XX },
519 { "andS", eAX, Iv, XX },
520 { "(bad)", XX, XX, XX }, /* SEG ES prefix */
521 { "daa{|}", XX, XX, XX },
252b5132 522 /* 28 */
6439fc28
AM		 523 { "subB", Eb, Gb, XX },
524 { "subS", Ev, Gv, XX },
525 { "subB", Gb, Eb, XX },
526 { "subS", Gv, Ev, XX },
527 { "subB", AL, Ib, XX },
528 { "subS", eAX, Iv, XX },
529 { "(bad)", XX, XX, XX }, /* SEG CS prefix */
530 { "das{|}", XX, XX, XX },
252b5132 531 /* 30 */
6439fc28
AM		 532 { "xorB", Eb, Gb, XX },
533 { "xorS", Ev, Gv, XX },
534 { "xorB", Gb, Eb, XX },
535 { "xorS", Gv, Ev, XX },
536 { "xorB", AL, Ib, XX },
537 { "xorS", eAX, Iv, XX },
538 { "(bad)", XX, XX, XX }, /* SEG SS prefix */
539 { "aaa{|}", XX, XX, XX },
252b5132 540 /* 38 */
6439fc28
AM		 541 { "cmpB", Eb, Gb, XX },
542 { "cmpS", Ev, Gv, XX },
543 { "cmpB", Gb, Eb, XX },
544 { "cmpS", Gv, Ev, XX },
545 { "cmpB", AL, Ib, XX },
546 { "cmpS", eAX, Iv, XX },
547 { "(bad)", XX, XX, XX }, /* SEG DS prefix */
548 { "aas{|}", XX, XX, XX },
252b5132 549 /* 40 */
6439fc28
AM		 550 { "inc{S|}", RMeAX, XX, XX },
551 { "inc{S|}", RMeCX, XX, XX },
552 { "inc{S|}", RMeDX, XX, XX },
553 { "inc{S|}", RMeBX, XX, XX },
554 { "inc{S|}", RMeSP, XX, XX },
555 { "inc{S|}", RMeBP, XX, XX },
556 { "inc{S|}", RMeSI, XX, XX },
557 { "inc{S|}", RMeDI, XX, XX },
252b5132 558 /* 48 */
6439fc28
AM		 559 { "dec{S|}", RMeAX, XX, XX },
560 { "dec{S|}", RMeCX, XX, XX },
561 { "dec{S|}", RMeDX, XX, XX },
562 { "dec{S|}", RMeBX, XX, XX },
563 { "dec{S|}", RMeSP, XX, XX },
564 { "dec{S|}", RMeBP, XX, XX },
565 { "dec{S|}", RMeSI, XX, XX },
566 { "dec{S|}", RMeDI, XX, XX },
252b5132 567 /* 50 */
6439fc28
AM		 568 { "pushS", RMrAX, XX, XX },
569 { "pushS", RMrCX, XX, XX },
570 { "pushS", RMrDX, XX, XX },
571 { "pushS", RMrBX, XX, XX },
572 { "pushS", RMrSP, XX, XX },
573 { "pushS", RMrBP, XX, XX },
574 { "pushS", RMrSI, XX, XX },
575 { "pushS", RMrDI, XX, XX },
252b5132 576 /* 58 */
6439fc28
AM		 577 { "popS", RMrAX, XX, XX },
578 { "popS", RMrCX, XX, XX },
579 { "popS", RMrDX, XX, XX },
580 { "popS", RMrBX, XX, XX },
581 { "popS", RMrSP, XX, XX },
582 { "popS", RMrBP, XX, XX },
583 { "popS", RMrSI, XX, XX },
584 { "popS", RMrDI, XX, XX },
252b5132 585 /* 60 */
6439fc28
AM		 586 { "pusha{P|}", XX, XX, XX },
587 { "popa{P|}", XX, XX, XX },
588 { "bound{S|}", Gv, Ma, XX },
589 { X86_64_0 },
590 { "(bad)", XX, XX, XX }, /* seg fs */
591 { "(bad)", XX, XX, XX }, /* seg gs */
592 { "(bad)", XX, XX, XX }, /* op size prefix */
593 { "(bad)", XX, XX, XX }, /* adr size prefix */
252b5132 594 /* 68 */
6439fc28
AM		 595 { "pushT", Iq, XX, XX },
596 { "imulS", Gv, Ev, Iv },
597 { "pushT", sIb, XX, XX },
598 { "imulS", Gv, Ev, sIb },
599 { "ins{b||b|}", Yb, indirDX, XX },
600 { "ins{R||R|}", Yv, indirDX, XX },
601 { "outs{b||b|}", indirDX, Xb, XX },
602 { "outs{R||R|}", indirDX, Xv, XX },
252b5132 603 /* 70 */
6439fc28
AM		 604 { "joH", Jb, XX, cond_jump_flag },
605 { "jnoH", Jb, XX, cond_jump_flag },
606 { "jbH", Jb, XX, cond_jump_flag },
607 { "jaeH", Jb, XX, cond_jump_flag },
608 { "jeH", Jb, XX, cond_jump_flag },
609 { "jneH", Jb, XX, cond_jump_flag },
610 { "jbeH", Jb, XX, cond_jump_flag },
611 { "jaH", Jb, XX, cond_jump_flag },
252b5132 612 /* 78 */
6439fc28
AM		 613 { "jsH", Jb, XX, cond_jump_flag },
614 { "jnsH", Jb, XX, cond_jump_flag },
615 { "jpH", Jb, XX, cond_jump_flag },
616 { "jnpH", Jb, XX, cond_jump_flag },
617 { "jlH", Jb, XX, cond_jump_flag },
618 { "jgeH", Jb, XX, cond_jump_flag },
619 { "jleH", Jb, XX, cond_jump_flag },
620 { "jgH", Jb, XX, cond_jump_flag },
252b5132
RH		 621 /* 80 */
622 { GRP1b },
623 { GRP1S },
6439fc28 624 { "(bad)", XX, XX, XX },
252b5132 625 { GRP1Ss },
6439fc28
AM		 626 { "testB", Eb, Gb, XX },
627 { "testS", Ev, Gv, XX },
628 { "xchgB", Eb, Gb, XX },
629 { "xchgS", Ev, Gv, XX },
252b5132 630 /* 88 */
6439fc28
AM		 631 { "movB", Eb, Gb, XX },
632 { "movS", Ev, Gv, XX },
633 { "movB", Gb, Eb, XX },
634 { "movS", Gv, Ev, XX },
635 { "movQ", Ev, Sw, XX },
636 { "leaS", Gv, M, XX },
637 { "movQ", Sw, Ev, XX },
638 { "popU", Ev, XX, XX },
252b5132 639 /* 90 */
6439fc28 640 { "nop", XX, XX, XX },
041bd2e0 641 /* FIXME: NOP with REPz prefix is called PAUSE. */
6439fc28
AM		 642 { "xchgS", RMeCX, eAX, XX },
643 { "xchgS", RMeDX, eAX, XX },
644 { "xchgS", RMeBX, eAX, XX },
645 { "xchgS", RMeSP, eAX, XX },
646 { "xchgS", RMeBP, eAX, XX },
647 { "xchgS", RMeSI, eAX, XX },
648 { "xchgS", RMeDI, eAX, XX },
252b5132 649 /* 98 */
6439fc28
AM		 650 { "cW{tR||tR|}", XX, XX, XX },
651 { "cR{tO||tO|}", XX, XX, XX },
652 { "lcall{T|}", Ap, XX, XX },
653 { "(bad)", XX, XX, XX }, /* fwait */
654 { "pushfT", XX, XX, XX },
655 { "popfT", XX, XX, XX },
656 { "sahf{|}", XX, XX, XX },
657 { "lahf{|}", XX, XX, XX },
252b5132 658 /* a0 */
6439fc28
AM		 659 { "movB", AL, Ob64, XX },
660 { "movS", eAX, Ov64, XX },
661 { "movB", Ob64, AL, XX },
662 { "movS", Ov64, eAX, XX },
663 { "movs{b||b|}", Yb, Xb, XX },
664 { "movs{R||R|}", Yv, Xv, XX },
665 { "cmps{b||b|}", Xb, Yb, XX },
666 { "cmps{R||R|}", Xv, Yv, XX },
252b5132 667 /* a8 */
6439fc28
AM		 668 { "testB", AL, Ib, XX },
669 { "testS", eAX, Iv, XX },
670 { "stosB", Yb, AL, XX },
671 { "stosS", Yv, eAX, XX },
672 { "lodsB", AL, Xb, XX },
673 { "lodsS", eAX, Xv, XX },
674 { "scasB", AL, Yb, XX },
675 { "scasS", eAX, Yv, XX },
252b5132 676 /* b0 */
6439fc28
AM		 677 { "movB", RMAL, Ib, XX },
678 { "movB", RMCL, Ib, XX },
679 { "movB", RMDL, Ib, XX },
680 { "movB", RMBL, Ib, XX },
681 { "movB", RMAH, Ib, XX },
682 { "movB", RMCH, Ib, XX },
683 { "movB", RMDH, Ib, XX },
684 { "movB", RMBH, Ib, XX },
252b5132 685 /* b8 */
6439fc28
AM		 686 { "movS", RMeAX, Iv64, XX },
687 { "movS", RMeCX, Iv64, XX },
688 { "movS", RMeDX, Iv64, XX },
689 { "movS", RMeBX, Iv64, XX },
690 { "movS", RMeSP, Iv64, XX },
691 { "movS", RMeBP, Iv64, XX },
692 { "movS", RMeSI, Iv64, XX },
693 { "movS", RMeDI, Iv64, XX },
252b5132
RH		 694 /* c0 */
695 { GRP2b },
696 { GRP2S },
6439fc28
AM		 697 { "retT", Iw, XX, XX },
698 { "retT", XX, XX, XX },
699 { "les{S|}", Gv, Mp, XX },
700 { "ldsS", Gv, Mp, XX },
701 { "movA", Eb, Ib, XX },
702 { "movQ", Ev, Iv, XX },
252b5132 703 /* c8 */
6439fc28
AM		 704 { "enterT", Iw, Ib, XX },
705 { "leaveT", XX, XX, XX },
706 { "lretP", Iw, XX, XX },
707 { "lretP", XX, XX, XX },
708 { "int3", XX, XX, XX },
709 { "int", Ib, XX, XX },
710 { "into{|}", XX, XX, XX },
711 { "iretP", XX, XX, XX },
252b5132
RH		 712 /* d0 */
713 { GRP2b_one },
714 { GRP2S_one },
715 { GRP2b_cl },
716 { GRP2S_cl },
6439fc28
AM		 717 { "aam{|}", sIb, XX, XX },
718 { "aad{|}", sIb, XX, XX },
719 { "(bad)", XX, XX, XX },
720 { "xlat", DSBX, XX, XX },
252b5132
RH		 721 /* d8 */
722 { FLOAT },
723 { FLOAT },
724 { FLOAT },
725 { FLOAT },
726 { FLOAT },
727 { FLOAT },
728 { FLOAT },
729 { FLOAT },
730 /* e0 */
6439fc28
AM		 731 { "loopneFH", Jb, XX, loop_jcxz_flag },
732 { "loopeFH", Jb, XX, loop_jcxz_flag },
733 { "loopFH", Jb, XX, loop_jcxz_flag },
734 { "jEcxzH", Jb, XX, loop_jcxz_flag },
735 { "inB", AL, Ib, XX },
736 { "inS", eAX, Ib, XX },
737 { "outB", Ib, AL, XX },
738 { "outS", Ib, eAX, XX },
252b5132 739 /* e8 */
6439fc28
AM		 740 { "callT", Jv, XX, XX },
741 { "jmpT", Jv, XX, XX },
742 { "ljmp{T|}", Ap, XX, XX },
743 { "jmp", Jb, XX, XX },
744 { "inB", AL, indirDX, XX },
745 { "inS", eAX, indirDX, XX },
746 { "outB", indirDX, AL, XX },
747 { "outS", indirDX, eAX, XX },
252b5132 748 /* f0 */
6439fc28 749 { "(bad)", XX, XX, XX }, /* lock prefix */
067186e4 750 { "icebp", XX, XX, XX },
6439fc28
AM		 751 { "(bad)", XX, XX, XX }, /* repne */
752 { "(bad)", XX, XX, XX }, /* repz */
753 { "hlt", XX, XX, XX },
754 { "cmc", XX, XX, XX },
252b5132
RH		 755 { GRP3b },
756 { GRP3S },
757 /* f8 */
6439fc28
AM		 758 { "clc", XX, XX, XX },
759 { "stc", XX, XX, XX },
760 { "cli", XX, XX, XX },
761 { "sti", XX, XX, XX },
762 { "cld", XX, XX, XX },
763 { "std", XX, XX, XX },
252b5132
RH		 764 { GRP4 },
765 { GRP5 },
766};
767
6439fc28 768static const struct dis386 dis386_twobyte[] = {
252b5132
RH		 769 /* 00 */
770 { GRP6 },
771 { GRP7 },
6439fc28
AM		 772 { "larS", Gv, Ew, XX },
773 { "lslS", Gv, Ew, XX },
774 { "(bad)", XX, XX, XX },
775 { "syscall", XX, XX, XX },
776 { "clts", XX, XX, XX },
777 { "sysretP", XX, XX, XX },
252b5132 778 /* 08 */
6439fc28
AM		 779 { "invd", XX, XX, XX },
780 { "wbinvd", XX, XX, XX },
781 { "(bad)", XX, XX, XX },
782 { "ud2a", XX, XX, XX },
783 { "(bad)", XX, XX, XX },
c608c12e 784 { GRPAMD },
6439fc28 785 { "femms", XX, XX, XX },
6608db57 786 { "", MX, EM, OPSUF }, /* See OP_3DNowSuffix. */
252b5132 787 /* 10 */
c608c12e
AM		 788 { PREGRP8 },
789 { PREGRP9 },
ca164297 790 { PREGRP30 },
6439fc28
AM		 791 { "movlpX", EX, XM, SIMD_Fixup, 'h' },
792 { "unpcklpX", XM, EX, XX },
793 { "unpckhpX", XM, EX, XX },
ca164297 794 { PREGRP31 },
6439fc28 795 { "movhpX", EX, XM, SIMD_Fixup, 'l' },
252b5132 796 /* 18 */
c608c12e 797 { GRP14 },
6439fc28
AM		 798 { "(bad)", XX, XX, XX },
799 { "(bad)", XX, XX, XX },
800 { "(bad)", XX, XX, XX },
801 { "(bad)", XX, XX, XX },
802 { "(bad)", XX, XX, XX },
803 { "(bad)", XX, XX, XX },
804 { "(bad)", XX, XX, XX },
252b5132 805 /* 20 */
6439fc28
AM		 806 { "movL", Rm, Cm, XX },
807 { "movL", Rm, Dm, XX },
808 { "movL", Cm, Rm, XX },
809 { "movL", Dm, Rm, XX },
810 { "movL", Rd, Td, XX },
811 { "(bad)", XX, XX, XX },
812 { "movL", Td, Rd, XX },
813 { "(bad)", XX, XX, XX },
252b5132 814 /* 28 */
6439fc28
AM		 815 { "movapX", XM, EX, XX },
816 { "movapX", EX, XM, XX },
c608c12e 817 { PREGRP2 },
6439fc28 818 { "movntpX", Ev, XM, XX },
2da11e11 819 { PREGRP4 },
c608c12e 820 { PREGRP3 },
6439fc28
AM		 821 { "ucomisX", XM,EX, XX },
822 { "comisX", XM,EX, XX },
252b5132 823 /* 30 */
6439fc28
AM		 824 { "wrmsr", XX, XX, XX },
825 { "rdtsc", XX, XX, XX },
826 { "rdmsr", XX, XX, XX },
827 { "rdpmc", XX, XX, XX },
828 { "sysenter", XX, XX, XX },
829 { "sysexit", XX, XX, XX },
830 { "(bad)", XX, XX, XX },
831 { "(bad)", XX, XX, XX },
252b5132 832 /* 38 */
6439fc28
AM		 833 { "(bad)", XX, XX, XX },
834 { "(bad)", XX, XX, XX },
835 { "(bad)", XX, XX, XX },
836 { "(bad)", XX, XX, XX },
837 { "(bad)", XX, XX, XX },
838 { "(bad)", XX, XX, XX },
839 { "(bad)", XX, XX, XX },
840 { "(bad)", XX, XX, XX },
252b5132 841 /* 40 */
6439fc28
AM		 842 { "cmovo", Gv, Ev, XX },
843 { "cmovno", Gv, Ev, XX },
844 { "cmovb", Gv, Ev, XX },
845 { "cmovae", Gv, Ev, XX },
846 { "cmove", Gv, Ev, XX },
847 { "cmovne", Gv, Ev, XX },
848 { "cmovbe", Gv, Ev, XX },
849 { "cmova", Gv, Ev, XX },
252b5132 850 /* 48 */
6439fc28
AM		 851 { "cmovs", Gv, Ev, XX },
852 { "cmovns", Gv, Ev, XX },
853 { "cmovp", Gv, Ev, XX },
854 { "cmovnp", Gv, Ev, XX },
855 { "cmovl", Gv, Ev, XX },
856 { "cmovge", Gv, Ev, XX },
857 { "cmovle", Gv, Ev, XX },
858 { "cmovg", Gv, Ev, XX },
252b5132 859 /* 50 */
6439fc28 860 { "movmskpX", Gd, XS, XX },
c608c12e
AM		 861 { PREGRP13 },
862 { PREGRP12 },
863 { PREGRP11 },
6439fc28
AM		 864 { "andpX", XM, EX, XX },
865 { "andnpX", XM, EX, XX },
866 { "orpX", XM, EX, XX },
867 { "xorpX", XM, EX, XX },
252b5132 868 /* 58 */
c608c12e
AM		 869 { PREGRP0 },
870 { PREGRP10 },
041bd2e0
JH		 871 { PREGRP17 },
872 { PREGRP16 },
c608c12e
AM		 873 { PREGRP14 },
874 { PREGRP7 },
875 { PREGRP5 },
2da11e11 876 { PREGRP6 },
252b5132 877 /* 60 */
6439fc28
AM		 878 { "punpcklbw", MX, EM, XX },
879 { "punpcklwd", MX, EM, XX },
880 { "punpckldq", MX, EM, XX },
881 { "packsswb", MX, EM, XX },
882 { "pcmpgtb", MX, EM, XX },
883 { "pcmpgtw", MX, EM, XX },
884 { "pcmpgtd", MX, EM, XX },
885 { "packuswb", MX, EM, XX },
252b5132 886 /* 68 */
6439fc28
AM		 887 { "punpckhbw", MX, EM, XX },
888 { "punpckhwd", MX, EM, XX },
889 { "punpckhdq", MX, EM, XX },
890 { "packssdw", MX, EM, XX },
0f17484f 891 { PREGRP26 },
041bd2e0 892 { PREGRP24 },
db6eb5be 893 { "movd", MX, Edq, XX },
041bd2e0 894 { PREGRP19 },
252b5132 895 /* 70 */
041bd2e0 896 { PREGRP22 },
252b5132
RH		 897 { GRP10 },
898 { GRP11 },
899 { GRP12 },
6439fc28
AM		 900 { "pcmpeqb", MX, EM, XX },
901 { "pcmpeqw", MX, EM, XX },
902 { "pcmpeqd", MX, EM, XX },
903 { "emms", XX, XX, XX },
252b5132 904 /* 78 */
6439fc28
AM		 905 { "(bad)", XX, XX, XX },
906 { "(bad)", XX, XX, XX },
907 { "(bad)", XX, XX, XX },
908 { "(bad)", XX, XX, XX },
ca164297
L		 909 { PREGRP28 },
910 { PREGRP29 },
041bd2e0
JH		 911 { PREGRP23 },
912 { PREGRP20 },
252b5132 913 /* 80 */
6439fc28
AM		 914 { "joH", Jv, XX, cond_jump_flag },
915 { "jnoH", Jv, XX, cond_jump_flag },
916 { "jbH", Jv, XX, cond_jump_flag },
917 { "jaeH", Jv, XX, cond_jump_flag },
918 { "jeH", Jv, XX, cond_jump_flag },
919 { "jneH", Jv, XX, cond_jump_flag },
920 { "jbeH", Jv, XX, cond_jump_flag },
921 { "jaH", Jv, XX, cond_jump_flag },
252b5132 922 /* 88 */
6439fc28
AM		 923 { "jsH", Jv, XX, cond_jump_flag },
924 { "jnsH", Jv, XX, cond_jump_flag },
925 { "jpH", Jv, XX, cond_jump_flag },
926 { "jnpH", Jv, XX, cond_jump_flag },
927 { "jlH", Jv, XX, cond_jump_flag },
928 { "jgeH", Jv, XX, cond_jump_flag },
929 { "jleH", Jv, XX, cond_jump_flag },
930 { "jgH", Jv, XX, cond_jump_flag },
252b5132 931 /* 90 */
6439fc28
AM		 932 { "seto", Eb, XX, XX },
933 { "setno", Eb, XX, XX },
934 { "setb", Eb, XX, XX },
935 { "setae", Eb, XX, XX },
936 { "sete", Eb, XX, XX },
937 { "setne", Eb, XX, XX },
938 { "setbe", Eb, XX, XX },
939 { "seta", Eb, XX, XX },
252b5132 940 /* 98 */
6439fc28
AM		 941 { "sets", Eb, XX, XX },
942 { "setns", Eb, XX, XX },
943 { "setp", Eb, XX, XX },
944 { "setnp", Eb, XX, XX },
945 { "setl", Eb, XX, XX },
946 { "setge", Eb, XX, XX },
947 { "setle", Eb, XX, XX },
948 { "setg", Eb, XX, XX },
252b5132 949 /* a0 */
6439fc28
AM		 950 { "pushT", fs, XX, XX },
951 { "popT", fs, XX, XX },
952 { "cpuid", XX, XX, XX },
953 { "btS", Ev, Gv, XX },
954 { "shldS", Ev, Gv, Ib },
955 { "shldS", Ev, Gv, CL },
956 { "(bad)", XX, XX, XX },
0f10071e 957 { PADLOCK_0 },
252b5132 958 /* a8 */
6439fc28
AM		 959 { "pushT", gs, XX, XX },
960 { "popT", gs, XX, XX },
961 { "rsm", XX, XX, XX },
962 { "btsS", Ev, Gv, XX },
963 { "shrdS", Ev, Gv, Ib },
964 { "shrdS", Ev, Gv, CL },
252b5132 965 { GRP13 },
6439fc28 966 { "imulS", Gv, Ev, XX },
252b5132 967 /* b0 */
6439fc28
AM		 968 { "cmpxchgB", Eb, Gb, XX },
969 { "cmpxchgS", Ev, Gv, XX },
970 { "lssS", Gv, Mp, XX },
971 { "btrS", Ev, Gv, XX },
972 { "lfsS", Gv, Mp, XX },
973 { "lgsS", Gv, Mp, XX },
974 { "movz{bR|x|bR|x}", Gv, Eb, XX },
975 { "movz{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movzww ! */
252b5132 976 /* b8 */
6439fc28
AM		 977 { "(bad)", XX, XX, XX },
978 { "ud2b", XX, XX, XX },
252b5132 979 { GRP8 },
6439fc28
AM		 980 { "btcS", Ev, Gv, XX },
981 { "bsfS", Gv, Ev, XX },
982 { "bsrS", Gv, Ev, XX },
983 { "movs{bR|x|bR|x}", Gv, Eb, XX },
984 { "movs{wR|x|wR|x}", Gv, Ew, XX }, /* yes, there really is movsww ! */
252b5132 985 /* c0 */
6439fc28
AM		 986 { "xaddB", Eb, Gb, XX },
987 { "xaddS", Ev, Gv, XX },
c608c12e 988 { PREGRP1 },
6439fc28
AM		 989 { "movntiS", Ev, Gv, XX },
990 { "pinsrw", MX, Ed, Ib },
991 { "pextrw", Gd, MS, Ib },
992 { "shufpX", XM, EX, Ib },
252b5132
RH		 993 { GRP9 },
994 /* c8 */
6439fc28
AM		 995 { "bswap", RMeAX, XX, XX },
996 { "bswap", RMeCX, XX, XX },
997 { "bswap", RMeDX, XX, XX },
998 { "bswap", RMeBX, XX, XX },
999 { "bswap", RMeSP, XX, XX },
1000 { "bswap", RMeBP, XX, XX },
1001 { "bswap", RMeSI, XX, XX },
1002 { "bswap", RMeDI, XX, XX },
252b5132 1003 /* d0 */
ca164297 1004 { PREGRP27 },
6439fc28
AM		 1005 { "psrlw", MX, EM, XX },
1006 { "psrld", MX, EM, XX },
1007 { "psrlq", MX, EM, XX },
1008 { "paddq", MX, EM, XX },
1009 { "pmullw", MX, EM, XX },
041bd2e0 1010 { PREGRP21 },
6439fc28 1011 { "pmovmskb", Gd, MS, XX },
252b5132 1012 /* d8 */
6439fc28
AM		 1013 { "psubusb", MX, EM, XX },
1014 { "psubusw", MX, EM, XX },
1015 { "pminub", MX, EM, XX },
1016 { "pand", MX, EM, XX },
1017 { "paddusb", MX, EM, XX },
1018 { "paddusw", MX, EM, XX },
1019 { "pmaxub", MX, EM, XX },
1020 { "pandn", MX, EM, XX },
252b5132 1021 /* e0 */
6439fc28
AM		 1022 { "pavgb", MX, EM, XX },
1023 { "psraw", MX, EM, XX },
1024 { "psrad", MX, EM, XX },
1025 { "pavgw", MX, EM, XX },
1026 { "pmulhuw", MX, EM, XX },
1027 { "pmulhw", MX, EM, XX },
041bd2e0 1028 { PREGRP15 },
0f17484f 1029 { PREGRP25 },
252b5132 1030 /* e8 */
6439fc28
AM		 1031 { "psubsb", MX, EM, XX },
1032 { "psubsw", MX, EM, XX },
1033 { "pminsw", MX, EM, XX },
1034 { "por", MX, EM, XX },
1035 { "paddsb", MX, EM, XX },
1036 { "paddsw", MX, EM, XX },
1037 { "pmaxsw", MX, EM, XX },
1038 { "pxor", MX, EM, XX },
252b5132 1039 /* f0 */
ca164297 1040 { PREGRP32 },
6439fc28
AM		 1041 { "psllw", MX, EM, XX },
1042 { "pslld", MX, EM, XX },
1043 { "psllq", MX, EM, XX },
1044 { "pmuludq", MX, EM, XX },
1045 { "pmaddwd", MX, EM, XX },
1046 { "psadbw", MX, EM, XX },
041bd2e0 1047 { PREGRP18 },
252b5132 1048 /* f8 */
6439fc28
AM		 1049 { "psubb", MX, EM, XX },
1050 { "psubw", MX, EM, XX },
1051 { "psubd", MX, EM, XX },
1052 { "psubq", MX, EM, XX },
1053 { "paddb", MX, EM, XX },
1054 { "paddw", MX, EM, XX },
1055 { "paddd", MX, EM, XX },
1056 { "(bad)", XX, XX, XX }
252b5132
RH		 1057};
1058
1059static const unsigned char onebyte_has_modrm[256] = {
c608c12e
AM		 1060 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1061 /* ------------------------------- */
1062 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1063 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1064 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1065 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1066 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1067 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1068 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1069 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1070 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1071 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1072 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1073 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1074 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1075 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1076 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1077 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1078 /* ------------------------------- */
1079 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1080};
1081
1082static const unsigned char twobyte_has_modrm[256] = {
c608c12e
AM		 1083 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1084 /* ------------------------------- */
252b5132 1085 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
c608c12e 1086 /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */
4bba6815 1087 /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
252b5132
RH		 1088 /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
1089 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
4bba6815
AM		 1090 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1091 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
ca164297 1092 /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */
252b5132
RH		 1093 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1094 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
4bba6815 1095 /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */
252b5132
RH		 1096 /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */
1097 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
ca164297 1098 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
4bba6815 1099 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
ca164297 1100 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
c608c12e
AM		 1101 /* ------------------------------- */
1102 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1103};
1104
041bd2e0 1105static const unsigned char twobyte_uses_SSE_prefix[256] = {
c608c12e
AM		 1106 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1107 /* ------------------------------- */
1108 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
ca164297 1109 /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
c608c12e
AM		 1110 /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */
1111 /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
1112 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
041bd2e0
JH		 1113 /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
1114 /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
ca164297 1115 /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */
c608c12e
AM		 1116 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1117 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
1118 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
1119 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
1120 /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
ca164297 1121 /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
041bd2e0 1122 /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
ca164297 1123 /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */
c608c12e
AM		 1124 /* ------------------------------- */
1125 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
252b5132
RH		 1126};
1127
1128static char obuf[100];
1129static char *obufp;
1130static char scratchbuf[100];
1131static unsigned char *start_codep;
1132static unsigned char *insn_codep;
1133static unsigned char *codep;
1134static disassemble_info *the_info;
1135static int mod;
1136static int rm;
1137static int reg;
4bba6815 1138static unsigned char need_modrm;
252b5132 1139
4bba6815
AM		 1140/* If we are accessing mod/rm/reg without need_modrm set, then the
1141 values are stale. Hitting this abort likely indicates that you
1142 need to update onebyte_has_modrm or twobyte_has_modrm. */
1143#define MODRM_CHECK if (!need_modrm) abort ()
1144
d708bcba
AM		 1145static const char **names64;
1146static const char **names32;
1147static const char **names16;
1148static const char **names8;
1149static const char **names8rex;
1150static const char **names_seg;
1151static const char **index16;
1152
1153static const char *intel_names64[] = {
1154 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1155 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1156};
1157static const char *intel_names32[] = {
1158 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1159 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1160};
1161static const char *intel_names16[] = {
1162 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1163 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1164};
1165static const char *intel_names8[] = {
1166 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1167};
1168static const char *intel_names8rex[] = {
1169 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1170 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1171};
1172static const char *intel_names_seg[] = {
1173 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1174};
1175static const char *intel_index16[] = {
1176 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1177};
1178
1179static const char *att_names64[] = {
1180 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
52b15da3
JH		 1181 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1182};
d708bcba
AM		 1183static const char *att_names32[] = {
1184 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
52b15da3 1185 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
252b5132 1186};
d708bcba
AM		 1187static const char *att_names16[] = {
1188 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
52b15da3 1189 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
252b5132 1190};
d708bcba
AM		 1191static const char *att_names8[] = {
1192 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
252b5132 1193};
d708bcba
AM		 1194static const char *att_names8rex[] = {
1195 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
52b15da3
JH		 1196 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
1197};
d708bcba
AM		 1198static const char *att_names_seg[] = {
1199 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
252b5132 1200};
d708bcba
AM		 1201static const char *att_index16[] = {
1202 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
252b5132
RH		 1203};
1204
2da11e11 1205static const struct dis386 grps[][8] = {
252b5132
RH		 1206 /* GRP1b */
1207 {
57d91c3c
ILT		 1208 { "addA", Eb, Ib, XX },
1209 { "orA", Eb, Ib, XX },
1210 { "adcA", Eb, Ib, XX },
1211 { "sbbA", Eb, Ib, XX },
1212 { "andA", Eb, Ib, XX },
1213 { "subA", Eb, Ib, XX },
1214 { "xorA", Eb, Ib, XX },
1215 { "cmpA", Eb, Ib, XX }
252b5132
RH		 1216 },
1217 /* GRP1S */
1218 {
57d91c3c
ILT		 1219 { "addQ", Ev, Iv, XX },
1220 { "orQ", Ev, Iv, XX },
1221 { "adcQ", Ev, Iv, XX },
1222 { "sbbQ", Ev, Iv, XX },
1223 { "andQ", Ev, Iv, XX },
1224 { "subQ", Ev, Iv, XX },
1225 { "xorQ", Ev, Iv, XX },
1226 { "cmpQ", Ev, Iv, XX }
252b5132
RH		 1227 },
1228 /* GRP1Ss */
1229 {
57d91c3c
ILT		 1230 { "addQ", Ev, sIb, XX },
1231 { "orQ", Ev, sIb, XX },
1232 { "adcQ", Ev, sIb, XX },
1233 { "sbbQ", Ev, sIb, XX },
1234 { "andQ", Ev, sIb, XX },
1235 { "subQ", Ev, sIb, XX },
1236 { "xorQ", Ev, sIb, XX },
1237 { "cmpQ", Ev, sIb, XX }
252b5132
RH		 1238 },
1239 /* GRP2b */
1240 {
57d91c3c
ILT		 1241 { "rolA", Eb, Ib, XX },
1242 { "rorA", Eb, Ib, XX },
1243 { "rclA", Eb, Ib, XX },
1244 { "rcrA", Eb, Ib, XX },
1245 { "shlA", Eb, Ib, XX },
1246 { "shrA", Eb, Ib, XX },
1247 { "(bad)", XX, XX, XX },
1248 { "sarA", Eb, Ib, XX },
252b5132
RH		 1249 },
1250 /* GRP2S */
1251 {
57d91c3c
ILT		 1252 { "rolQ", Ev, Ib, XX },
1253 { "rorQ", Ev, Ib, XX },
1254 { "rclQ", Ev, Ib, XX },
1255 { "rcrQ", Ev, Ib, XX },
1256 { "shlQ", Ev, Ib, XX },
1257 { "shrQ", Ev, Ib, XX },
1258 { "(bad)", XX, XX, XX },
1259 { "sarQ", Ev, Ib, XX },
252b5132
RH		 1260 },
1261 /* GRP2b_one */
1262 {
57d91c3c
ILT		 1263 { "rolA", Eb, XX, XX },
1264 { "rorA", Eb, XX, XX },
1265 { "rclA", Eb, XX, XX },
1266 { "rcrA", Eb, XX, XX },
1267 { "shlA", Eb, XX, XX },
1268 { "shrA", Eb, XX, XX },
1269 { "(bad)", XX, XX, XX },
1270 { "sarA", Eb, XX, XX },
252b5132
RH		 1271 },
1272 /* GRP2S_one */
1273 {
57d91c3c
ILT		 1274 { "rolQ", Ev, XX, XX },
1275 { "rorQ", Ev, XX, XX },
1276 { "rclQ", Ev, XX, XX },
1277 { "rcrQ", Ev, XX, XX },
1278 { "shlQ", Ev, XX, XX },
1279 { "shrQ", Ev, XX, XX },
1280 { "(bad)", XX, XX, XX},
1281 { "sarQ", Ev, XX, XX },
252b5132
RH		 1282 },
1283 /* GRP2b_cl */
1284 {
57d91c3c
ILT		 1285 { "rolA", Eb, CL, XX },
1286 { "rorA", Eb, CL, XX },
1287 { "rclA", Eb, CL, XX },
1288 { "rcrA", Eb, CL, XX },
1289 { "shlA", Eb, CL, XX },
1290 { "shrA", Eb, CL, XX },
1291 { "(bad)", XX, XX, XX },
1292 { "sarA", Eb, CL, XX },
252b5132
RH		 1293 },
1294 /* GRP2S_cl */
1295 {
57d91c3c
ILT		 1296 { "rolQ", Ev, CL, XX },
1297 { "rorQ", Ev, CL, XX },
1298 { "rclQ", Ev, CL, XX },
1299 { "rcrQ", Ev, CL, XX },
1300 { "shlQ", Ev, CL, XX },
1301 { "shrQ", Ev, CL, XX },
1302 { "(bad)", XX, XX, XX },
1303 { "sarQ", Ev, CL, XX }
252b5132
RH		 1304 },
1305 /* GRP3b */
1306 {
57d91c3c
ILT		 1307 { "testA", Eb, Ib, XX },
1308 { "(bad)", Eb, XX, XX },
1309 { "notA", Eb, XX, XX },
1310 { "negA", Eb, XX, XX },
8227b51f
AM		 1311 { "mulA", Eb, XX, XX }, /* Don't print the implicit %al register, */
1312 { "imulA", Eb, XX, XX }, /* to distinguish these opcodes from other */
1313 { "divA", Eb, XX, XX }, /* mul/imul opcodes. Do the same for div */
1314 { "idivA", Eb, XX, XX } /* and idiv for consistency. */
252b5132
RH		 1315 },
1316 /* GRP3S */
1317 {
57d91c3c
ILT		 1318 { "testQ", Ev, Iv, XX },
1319 { "(bad)", XX, XX, XX },
1320 { "notQ", Ev, XX, XX },
1321 { "negQ", Ev, XX, XX },
8227b51f
AM		 1322 { "mulQ", Ev, XX, XX }, /* Don't print the implicit register. */
1323 { "imulQ", Ev, XX, XX },
1324 { "divQ", Ev, XX, XX },
1325 { "idivQ", Ev, XX, XX },
252b5132
RH		 1326 },
1327 /* GRP4 */
1328 {
57d91c3c
ILT		 1329 { "incA", Eb, XX, XX },
1330 { "decA", Eb, XX, XX },
1331 { "(bad)", XX, XX, XX },
1332 { "(bad)", XX, XX, XX },
1333 { "(bad)", XX, XX, XX },
1334 { "(bad)", XX, XX, XX },
1335 { "(bad)", XX, XX, XX },
1336 { "(bad)", XX, XX, XX },
252b5132
RH		 1337 },
1338 /* GRP5 */
1339 {
57d91c3c
ILT		 1340 { "incQ", Ev, XX, XX },
1341 { "decQ", Ev, XX, XX },
6439fc28
AM		 1342 { "callT", indirEv, XX, XX },
1343 { "lcallT", indirEv, XX, XX },
1344 { "jmpT", indirEv, XX, XX },
1345 { "ljmpT", indirEv, XX, XX },
1346 { "pushU", Ev, XX, XX },
57d91c3c 1347 { "(bad)", XX, XX, XX },
252b5132
RH		 1348 },
1349 /* GRP6 */
1350 {
e5470cdc
AM		 1351 { "sldtQ", Ev, XX, XX },
1352 { "strQ", Ev, XX, XX },
57d91c3c
ILT		 1353 { "lldt", Ew, XX, XX },
1354 { "ltr", Ew, XX, XX },
1355 { "verr", Ew, XX, XX },
1356 { "verw", Ew, XX, XX },
1357 { "(bad)", XX, XX, XX },
1358 { "(bad)", XX, XX, XX }
252b5132
RH		 1359 },
1360 /* GRP7 */
1361 {
bcb5558b 1362 { "sgdtQ", M, XX, XX },
ca164297 1363 { "sidtQ", PNI_Fixup, 0, XX, XX },
bcb5558b
AM		 1364 { "lgdtQ", M, XX, XX },
1365 { "lidtQ", M, XX, XX },
e5470cdc 1366 { "smswQ", Ev, XX, XX },
bcb5558b
AM		 1367 { "(bad)", XX, XX, XX },
1368 { "lmsw", Ew, XX, XX },
4fd61dcb 1369 { "invlpg", INVLPG_Fixup, w_mode, XX, XX },
252b5132
RH		 1370 },
1371 /* GRP8 */
1372 {
57d91c3c
ILT		 1373 { "(bad)", XX, XX, XX },
1374 { "(bad)", XX, XX, XX },
1375 { "(bad)", XX, XX, XX },
1376 { "(bad)", XX, XX, XX },
1377 { "btQ", Ev, Ib, XX },
1378 { "btsQ", Ev, Ib, XX },
1379 { "btrQ", Ev, Ib, XX },
1380 { "btcQ", Ev, Ib, XX },
252b5132
RH		 1381 },
1382 /* GRP9 */
1383 {
57d91c3c
ILT		 1384 { "(bad)", XX, XX, XX },
1385 { "cmpxchg8b", Ev, XX, XX },
1386 { "(bad)", XX, XX, XX },
1387 { "(bad)", XX, XX, XX },
1388 { "(bad)", XX, XX, XX },
1389 { "(bad)", XX, XX, XX },
1390 { "(bad)", XX, XX, XX },
1391 { "(bad)", XX, XX, XX },
252b5132
RH		 1392 },
1393 /* GRP10 */
1394 {
57d91c3c
ILT		 1395 { "(bad)", XX, XX, XX },
1396 { "(bad)", XX, XX, XX },
1397 { "psrlw", MS, Ib, XX },
1398 { "(bad)", XX, XX, XX },
1399 { "psraw", MS, Ib, XX },
1400 { "(bad)", XX, XX, XX },
1401 { "psllw", MS, Ib, XX },
1402 { "(bad)", XX, XX, XX },
252b5132
RH		 1403 },
1404 /* GRP11 */
1405 {
57d91c3c
ILT		 1406 { "(bad)", XX, XX, XX },
1407 { "(bad)", XX, XX, XX },
1408 { "psrld", MS, Ib, XX },
1409 { "(bad)", XX, XX, XX },
1410 { "psrad", MS, Ib, XX },
1411 { "(bad)", XX, XX, XX },
1412 { "pslld", MS, Ib, XX },
1413 { "(bad)", XX, XX, XX },
252b5132
RH		 1414 },
1415 /* GRP12 */
1416 {
57d91c3c
ILT		 1417 { "(bad)", XX, XX, XX },
1418 { "(bad)", XX, XX, XX },
1419 { "psrlq", MS, Ib, XX },
041bd2e0 1420 { "psrldq", MS, Ib, XX },
57d91c3c
ILT		 1421 { "(bad)", XX, XX, XX },
1422 { "(bad)", XX, XX, XX },
1423 { "psllq", MS, Ib, XX },
041bd2e0 1424 { "pslldq", MS, Ib, XX },
252b5132
RH		 1425 },
1426 /* GRP13 */
1427 {
57d91c3c
ILT		 1428 { "fxsave", Ev, XX, XX },
1429 { "fxrstor", Ev, XX, XX },
1430 { "ldmxcsr", Ev, XX, XX },
1431 { "stmxcsr", Ev, XX, XX },
1432 { "(bad)", XX, XX, XX },
041bd2e0
JH		 1433 { "lfence", None, XX, XX },
1434 { "mfence", None, XX, XX },
c02908d2 1435 { "clflush", None, XX, XX },
c608c12e
AM		 1436 },
1437 /* GRP14 */
1438 {
57d91c3c
ILT		 1439 { "prefetchnta", Ev, XX, XX },
1440 { "prefetcht0", Ev, XX, XX },
1441 { "prefetcht1", Ev, XX, XX },
1442 { "prefetcht2", Ev, XX, XX },
1443 { "(bad)", XX, XX, XX },
1444 { "(bad)", XX, XX, XX },
1445 { "(bad)", XX, XX, XX },
1446 { "(bad)", XX, XX, XX },
252b5132 1447 },
c608c12e 1448 /* GRPAMD */
252b5132 1449 {
57d91c3c
ILT		 1450 { "prefetch", Eb, XX, XX },
1451 { "prefetchw", Eb, XX, XX },
1452 { "(bad)", XX, XX, XX },
1453 { "(bad)", XX, XX, XX },
1454 { "(bad)", XX, XX, XX },
1455 { "(bad)", XX, XX, XX },
1456 { "(bad)", XX, XX, XX },
1457 { "(bad)", XX, XX, XX },
0f10071e
ML		 1458 },
1459 /* GRPPLOCK */
1460 {
1461 { "xstore", XX, XX, XX },
1462 { "xcryptecb", XX, XX, XX },
1463 { "xcryptcbc", XX, XX, XX },
1464 { "(bad)", XX, XX, XX },
1465 { "xcryptcfb", XX, XX, XX },
1466 { "xcryptofb", XX, XX, XX },
1467 { "(bad)", XX, XX, XX },
1468 { "(bad)", XX, XX, XX },
252b5132 1469 }
252b5132
RH		 1470};
1471
041bd2e0 1472static const struct dis386 prefix_user_table[][4] = {
c608c12e
AM		 1473 /* PREGRP0 */
1474 {
57d91c3c
ILT		 1475 { "addps", XM, EX, XX },
1476 { "addss", XM, EX, XX },
041bd2e0
JH		 1477 { "addpd", XM, EX, XX },
1478 { "addsd", XM, EX, XX },
c608c12e
AM		 1479 },
1480 /* PREGRP1 */
1481 {
6608db57 1482 { "", XM, EX, OPSIMD }, /* See OP_SIMD_SUFFIX. */
c608c12e 1483 { "", XM, EX, OPSIMD },
041bd2e0
JH		 1484 { "", XM, EX, OPSIMD },
1485 { "", XM, EX, OPSIMD },
c608c12e
AM		 1486 },
1487 /* PREGRP2 */
1488 {
57d91c3c 1489 { "cvtpi2ps", XM, EM, XX },
76f227a5 1490 { "cvtsi2ssY", XM, Ev, XX },
041bd2e0 1491 { "cvtpi2pd", XM, EM, XX },
76f227a5 1492 { "cvtsi2sdY", XM, Ev, XX },
c608c12e
AM		 1493 },
1494 /* PREGRP3 */
1495 {
57d91c3c 1496 { "cvtps2pi", MX, EX, XX },
76f227a5 1497 { "cvtss2siY", Gv, EX, XX },
041bd2e0 1498 { "cvtpd2pi", MX, EX, XX },
76f227a5 1499 { "cvtsd2siY", Gv, EX, XX },
c608c12e
AM		 1500 },
1501 /* PREGRP4 */
1502 {
57d91c3c 1503 { "cvttps2pi", MX, EX, XX },
76f227a5 1504 { "cvttss2siY", Gv, EX, XX },
041bd2e0 1505 { "cvttpd2pi", MX, EX, XX },
76f227a5 1506 { "cvttsd2siY", Gv, EX, XX },
c608c12e
AM		 1507 },
1508 /* PREGRP5 */
1509 {
57d91c3c
ILT		 1510 { "divps", XM, EX, XX },
1511 { "divss", XM, EX, XX },
041bd2e0
JH		 1512 { "divpd", XM, EX, XX },
1513 { "divsd", XM, EX, XX },
c608c12e
AM		 1514 },
1515 /* PREGRP6 */
1516 {
57d91c3c
ILT		 1517 { "maxps", XM, EX, XX },
1518 { "maxss", XM, EX, XX },
041bd2e0
JH		 1519 { "maxpd", XM, EX, XX },
1520 { "maxsd", XM, EX, XX },
c608c12e
AM		 1521 },
1522 /* PREGRP7 */
1523 {
57d91c3c
ILT		 1524 { "minps", XM, EX, XX },
1525 { "minss", XM, EX, XX },
041bd2e0
JH		 1526 { "minpd", XM, EX, XX },
1527 { "minsd", XM, EX, XX },
c608c12e
AM		 1528 },
1529 /* PREGRP8 */
1530 {
57d91c3c
ILT		 1531 { "movups", XM, EX, XX },
1532 { "movss", XM, EX, XX },
041bd2e0
JH		 1533 { "movupd", XM, EX, XX },
1534 { "movsd", XM, EX, XX },
c608c12e
AM		 1535 },
1536 /* PREGRP9 */
1537 {
57d91c3c
ILT		 1538 { "movups", EX, XM, XX },
1539 { "movss", EX, XM, XX },
041bd2e0
JH		 1540 { "movupd", EX, XM, XX },
1541 { "movsd", EX, XM, XX },
c608c12e
AM		 1542 },
1543 /* PREGRP10 */
1544 {
57d91c3c
ILT		 1545 { "mulps", XM, EX, XX },
1546 { "mulss", XM, EX, XX },
041bd2e0
JH		 1547 { "mulpd", XM, EX, XX },
1548 { "mulsd", XM, EX, XX },
c608c12e
AM		 1549 },
1550 /* PREGRP11 */
1551 {
57d91c3c
ILT		 1552 { "rcpps", XM, EX, XX },
1553 { "rcpss", XM, EX, XX },
041bd2e0
JH		 1554 { "(bad)", XM, EX, XX },
1555 { "(bad)", XM, EX, XX },
c608c12e
AM		 1556 },
1557 /* PREGRP12 */
1558 {
57d91c3c
ILT		 1559 { "rsqrtps", XM, EX, XX },
1560 { "rsqrtss", XM, EX, XX },
041bd2e0
JH		 1561 { "(bad)", XM, EX, XX },
1562 { "(bad)", XM, EX, XX },
c608c12e
AM		 1563 },
1564 /* PREGRP13 */
1565 {
57d91c3c
ILT		 1566 { "sqrtps", XM, EX, XX },
1567 { "sqrtss", XM, EX, XX },
041bd2e0
JH		 1568 { "sqrtpd", XM, EX, XX },
1569 { "sqrtsd", XM, EX, XX },
c608c12e
AM		 1570 },
1571 /* PREGRP14 */
1572 {
57d91c3c
ILT		 1573 { "subps", XM, EX, XX },
1574 { "subss", XM, EX, XX },
041bd2e0
JH		 1575 { "subpd", XM, EX, XX },
1576 { "subsd", XM, EX, XX },
1577 },
1578 /* PREGRP15 */
1579 {
1580 { "(bad)", XM, EX, XX },
1581 { "cvtdq2pd", XM, EX, XX },
1582 { "cvttpd2dq", XM, EX, XX },
1583 { "cvtpd2dq", XM, EX, XX },
1584 },
1585 /* PREGRP16 */
1586 {
1587 { "cvtdq2ps", XM, EX, XX },
1588 { "cvttps2dq",XM, EX, XX },
1589 { "cvtps2dq",XM, EX, XX },
1590 { "(bad)", XM, EX, XX },
1591 },
1592 /* PREGRP17 */
1593 {
1594 { "cvtps2pd", XM, EX, XX },
1595 { "cvtss2sd", XM, EX, XX },
1596 { "cvtpd2ps", XM, EX, XX },
1597 { "cvtsd2ss", XM, EX, XX },
1598 },
1599 /* PREGRP18 */
1600 {
992aaec9 1601 { "maskmovq", MX, MS, XX },
041bd2e0 1602 { "(bad)", XM, EX, XX },
0f17484f 1603 { "maskmovdqu", XM, EX, XX },
041bd2e0
JH		 1604 { "(bad)", XM, EX, XX },
1605 },
1606 /* PREGRP19 */
1607 {
1608 { "movq", MX, EM, XX },
1609 { "movdqu", XM, EX, XX },
1610 { "movdqa", XM, EX, XX },
1611 { "(bad)", XM, EX, XX },
1612 },
1613 /* PREGRP20 */
1614 {
1615 { "movq", EM, MX, XX },
1616 { "movdqu", EX, XM, XX },
1617 { "movdqa", EX, XM, XX },
1618 { "(bad)", EX, XM, XX },
1619 },
1620 /* PREGRP21 */
1621 {
1622 { "(bad)", EX, XM, XX },
67d6227d 1623 { "movq2dq", XM, MS, XX },
041bd2e0 1624 { "movq", EX, XM, XX },
67d6227d 1625 { "movdq2q", MX, XS, XX },
041bd2e0
JH		 1626 },
1627 /* PREGRP22 */
1628 {
1629 { "pshufw", MX, EM, Ib },
1630 { "pshufhw", XM, EX, Ib },
1631 { "pshufd", XM, EX, Ib },
1632 { "pshuflw", XM, EX, Ib },
1633 },
1634 /* PREGRP23 */
1635 {
db6eb5be 1636 { "movd", Edq, MX, XX },
67d6227d 1637 { "movq", XM, EX, XX },
db6eb5be 1638 { "movd", Edq, XM, XX },
0f17484f 1639 { "(bad)", Ed, XM, XX },
041bd2e0
JH		 1640 },
1641 /* PREGRP24 */
1642 {
0f17484f
AM		 1643 { "(bad)", MX, EX, XX },
1644 { "(bad)", XM, EX, XX },
041bd2e0 1645 { "punpckhqdq", XM, EX, XX },
0f17484f
AM		 1646 { "(bad)", XM, EX, XX },
1647 },
1648 /* PREGRP25 */
1649 {
1650 { "movntq", Ev, MX, XX },
1651 { "(bad)", Ev, XM, XX },
1652 { "movntdq", Ev, XM, XX },
1653 { "(bad)", Ev, XM, XX },
1654 },
1655 /* PREGRP26 */
1656 {
1657 { "(bad)", MX, EX, XX },
1658 { "(bad)", XM, EX, XX },
1659 { "punpcklqdq", XM, EX, XX },
1660 { "(bad)", XM, EX, XX },
041bd2e0 1661 },
ca164297
L		 1662 /* PREGRP27 */
1663 {
1664 { "(bad)", MX, EX, XX },
1665 { "(bad)", XM, EX, XX },
1666 { "addsubpd", XM, EX, XX },
1667 { "addsubps", XM, EX, XX },
1668 },
1669 /* PREGRP28 */
1670 {
1671 { "(bad)", MX, EX, XX },
1672 { "(bad)", XM, EX, XX },
1673 { "haddpd", XM, EX, XX },
1674 { "haddps", XM, EX, XX },
1675 },
1676 /* PREGRP29 */
1677 {
1678 { "(bad)", MX, EX, XX },
1679 { "(bad)", XM, EX, XX },
1680 { "hsubpd", XM, EX, XX },
1681 { "hsubps", XM, EX, XX },
1682 },
1683 /* PREGRP30 */
1684 {
1685 { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */
1686 { "movsldup", XM, EX, XX },
1687 { "movlpd", XM, EX, XX },
1688 { "movddup", XM, EX, XX },
1689 },
1690 /* PREGRP31 */
1691 {
1692 { "movhpX", XM, EX, SIMD_Fixup, 'l' },
1693 { "movshdup", XM, EX, XX },
1694 { "movhpd", XM, EX, XX },
1695 { "(bad)", XM, EX, XX },
1696 },
1697 /* PREGRP32 */
1698 {
1699 { "(bad)", XM, EX, XX },
1700 { "(bad)", XM, EX, XX },
1701 { "(bad)", XM, EX, XX },
1702 { "lddqu", XM, M, XX },
1703 },
c608c12e
AM		 1704};
1705
6439fc28
AM		 1706static const struct dis386 x86_64_table[][2] = {
1707 {
1708 { "arpl", Ew, Gw, XX },
1709 { "movs{||lq|xd}", Gv, Ed, XX },
1710 },
1711};
1712
0f10071e
ML		 1713static const struct dis386 padlock_table[][8] = {
1714 {
1715 { "xstorerng", XX, XX, XX },
1716 { "xcryptecb", XX, XX, XX },
1717 { "xcryptcbc", XX, XX, XX },
1718 { "(bad)", XX, XX, XX },
1719 { "xcryptcfb", XX, XX, XX },
1720 { "xcryptofb", XX, XX, XX },
1721 { "(bad)", XX, XX, XX },
1722 { "(bad)", XX, XX, XX },
1723 },
1724};
1725
c608c12e
AM		 1726#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
1727
252b5132 1728static void
26ca5450 1729ckprefix (void)
252b5132 1730{
52b15da3
JH		 1731 int newrex;
1732 rex = 0;
252b5132 1733 prefixes = 0;
7d421014 1734 used_prefixes = 0;
52b15da3 1735 rex_used = 0;
252b5132
RH		 1736 while (1)
1737 {
1738 FETCH_DATA (the_info, codep + 1);
52b15da3 1739 newrex = 0;
252b5132
RH		 1740 switch (*codep)
1741 {
52b15da3
JH		 1742 /* REX prefixes family. */
1743 case 0x40:
1744 case 0x41:
1745 case 0x42:
1746 case 0x43:
1747 case 0x44:
1748 case 0x45:
1749 case 0x46:
1750 case 0x47:
1751 case 0x48:
1752 case 0x49:
1753 case 0x4a:
1754 case 0x4b:
1755 case 0x4c:
1756 case 0x4d:
1757 case 0x4e:
1758 case 0x4f:
1759 if (mode_64bit)
1760 newrex = *codep;
1761 else
1762 return;
1763 break;
252b5132
RH		 1764 case 0xf3:
1765 prefixes |= PREFIX_REPZ;
1766 break;
1767 case 0xf2:
1768 prefixes |= PREFIX_REPNZ;
1769 break;
1770 case 0xf0:
1771 prefixes |= PREFIX_LOCK;
1772 break;
1773 case 0x2e:
1774 prefixes |= PREFIX_CS;
1775 break;
1776 case 0x36:
1777 prefixes |= PREFIX_SS;
1778 break;
1779 case 0x3e:
1780 prefixes |= PREFIX_DS;
1781 break;
1782 case 0x26:
1783 prefixes |= PREFIX_ES;
1784 break;
1785 case 0x64:
1786 prefixes |= PREFIX_FS;
1787 break;
1788 case 0x65:
1789 prefixes |= PREFIX_GS;
1790 break;
1791 case 0x66:
1792 prefixes |= PREFIX_DATA;
1793 break;
1794 case 0x67:
1795 prefixes |= PREFIX_ADDR;
1796 break;
5076851f 1797 case FWAIT_OPCODE:
252b5132
RH		 1798 /* fwait is really an instruction. If there are prefixes
1799 before the fwait, they belong to the fwait, *not* to the
1800 following instruction. */
1801 if (prefixes)
1802 {
1803 prefixes |= PREFIX_FWAIT;
1804 codep++;
1805 return;
1806 }
1807 prefixes = PREFIX_FWAIT;
1808 break;
1809 default:
1810 return;
1811 }
52b15da3
JH		 1812 /* Rex is ignored when followed by another prefix. */
1813 if (rex)
1814 {
1815 oappend (prefix_name (rex, 0));
1816 oappend (" ");
1817 }
1818 rex = newrex;
252b5132
RH		 1819 codep++;
1820 }
1821}
1822
7d421014
ILT		 1823/* Return the name of the prefix byte PREF, or NULL if PREF is not a
1824 prefix byte. */
1825
1826static const char *
26ca5450 1827prefix_name (int pref, int sizeflag)
7d421014
ILT		 1828{
1829 switch (pref)
1830 {
52b15da3
JH		 1831 /* REX prefixes family. */
1832 case 0x40:
1833 return "rex";
1834 case 0x41:
1835 return "rexZ";
1836 case 0x42:
1837 return "rexY";
1838 case 0x43:
1839 return "rexYZ";
1840 case 0x44:
1841 return "rexX";
1842 case 0x45:
1843 return "rexXZ";
1844 case 0x46:
1845 return "rexXY";
1846 case 0x47:
1847 return "rexXYZ";
1848 case 0x48:
1849 return "rex64";
1850 case 0x49:
1851 return "rex64Z";
1852 case 0x4a:
1853 return "rex64Y";
1854 case 0x4b:
1855 return "rex64YZ";
1856 case 0x4c:
1857 return "rex64X";
1858 case 0x4d:
1859 return "rex64XZ";
1860 case 0x4e:
1861 return "rex64XY";
1862 case 0x4f:
1863 return "rex64XYZ";
7d421014
ILT		 1864 case 0xf3:
1865 return "repz";
1866 case 0xf2:
1867 return "repnz";
1868 case 0xf0:
1869 return "lock";
1870 case 0x2e:
1871 return "cs";
1872 case 0x36:
1873 return "ss";
1874 case 0x3e:
1875 return "ds";
1876 case 0x26:
1877 return "es";
1878 case 0x64:
1879 return "fs";
1880 case 0x65:
1881 return "gs";
1882 case 0x66:
1883 return (sizeflag & DFLAG) ? "data16" : "data32";
1884 case 0x67:
c1a64871 1885 if (mode_64bit)
db6eb5be 1886 return (sizeflag & AFLAG) ? "addr32" : "addr64";
c1a64871 1887 else
db6eb5be 1888 return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32";
7d421014
ILT		 1889 case FWAIT_OPCODE:
1890 return "fwait";
1891 default:
1892 return NULL;
1893 }
1894}
1895
252b5132
RH		 1896static char op1out[100], op2out[100], op3out[100];
1897static int op_ad, op_index[3];
7081ff04
AJ		 1898static bfd_vma op_address[3];
1899static bfd_vma op_riprel[3];
52b15da3 1900static bfd_vma start_pc;
252b5132
RH		 1901\f
1902/*
1903 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
1904 * (see topic "Redundant prefixes" in the "Differences from 8086"
1905 * section of the "Virtual 8086 Mode" chapter.)
1906 * 'pc' should be the address of this instruction, it will
1907 * be used to print the target address if this is a relative jump or call
1908 * The function returns the length of this instruction in bytes.
1909 */
1910
252b5132
RH		 1911static char intel_syntax;
1912static char open_char;
1913static char close_char;
1914static char separator_char;
1915static char scale_char;
1916
e396998b
AM		 1917/* Here for backwards compatibility. When gdb stops using
1918 print_insn_i386_att and print_insn_i386_intel these functions can
1919 disappear, and print_insn_i386 be merged into print_insn. */
252b5132 1920int
26ca5450 1921print_insn_i386_att (bfd_vma pc, disassemble_info *info)
252b5132
RH		 1922{
1923 intel_syntax = 0;
e396998b
AM		 1924
1925 return print_insn (pc, info);
252b5132
RH		 1926}
1927
1928int
26ca5450 1929print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
252b5132
RH		 1930{
1931 intel_syntax = 1;
e396998b
AM		 1932
1933 return print_insn (pc, info);
252b5132
RH		 1934}
1935
e396998b 1936int
26ca5450 1937print_insn_i386 (bfd_vma pc, disassemble_info *info)
e396998b
AM		 1938{
1939 intel_syntax = -1;
1940
1941 return print_insn (pc, info);
1942}
1943
1944static int
26ca5450 1945print_insn (bfd_vma pc, disassemble_info *info)
252b5132 1946{
2da11e11 1947 const struct dis386 *dp;
252b5132
RH		 1948 int i;
1949 int two_source_ops;
1950 char *first, *second, *third;
1951 int needcomma;
041bd2e0 1952 unsigned char uses_SSE_prefix;
e396998b
AM		 1953 int sizeflag;
1954 const char *p;
252b5132 1955 struct dis_private priv;
252b5132 1956
52b15da3
JH		 1957 mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax
1958 || info->mach == bfd_mach_x86_64);
1959
8373f971 1960 if (intel_syntax == (char) -1)
e396998b
AM		 1961 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
1962 || info->mach == bfd_mach_x86_64_intel_syntax);
1963
2da11e11 1964 if (info->mach == bfd_mach_i386_i386
52b15da3
JH		 1965 || info->mach == bfd_mach_x86_64
1966 || info->mach == bfd_mach_i386_i386_intel_syntax
1967 || info->mach == bfd_mach_x86_64_intel_syntax)
e396998b 1968 priv.orig_sizeflag = AFLAG | DFLAG;
2da11e11 1969 else if (info->mach == bfd_mach_i386_i8086)
e396998b 1970 priv.orig_sizeflag = 0;
2da11e11
AM		 1971 else
1972 abort ();
e396998b
AM		 1973
1974 for (p = info->disassembler_options; p != NULL; )
1975 {
fa405d97 1976 if (strncmp (p, "x86-64", 6) == 0)
e396998b
AM		 1977 {
1978 mode_64bit = 1;
1979 priv.orig_sizeflag = AFLAG | DFLAG;
1980 }
1981 else if (strncmp (p, "i386", 4) == 0)
1982 {
1983 mode_64bit = 0;
1984 priv.orig_sizeflag = AFLAG | DFLAG;
1985 }
1986 else if (strncmp (p, "i8086", 5) == 0)
1987 {
1988 mode_64bit = 0;
1989 priv.orig_sizeflag = 0;
1990 }
1991 else if (strncmp (p, "intel", 5) == 0)
1992 {
1993 intel_syntax = 1;
1994 }
1995 else if (strncmp (p, "att", 3) == 0)
1996 {
1997 intel_syntax = 0;
1998 }
1999 else if (strncmp (p, "addr", 4) == 0)
2000 {
2001 if (p[4] == '1' && p[5] == '6')
2002 priv.orig_sizeflag &= ~AFLAG;
2003 else if (p[4] == '3' && p[5] == '2')
2004 priv.orig_sizeflag |= AFLAG;
2005 }
2006 else if (strncmp (p, "data", 4) == 0)
2007 {
2008 if (p[4] == '1' && p[5] == '6')
2009 priv.orig_sizeflag &= ~DFLAG;
2010 else if (p[4] == '3' && p[5] == '2')
2011 priv.orig_sizeflag |= DFLAG;
2012 }
2013 else if (strncmp (p, "suffix", 6) == 0)
2014 priv.orig_sizeflag |= SUFFIX_ALWAYS;
2015
2016 p = strchr (p, ',');
2017 if (p != NULL)
2018 p++;
2019 }
2020
2021 if (intel_syntax)
2022 {
2023 names64 = intel_names64;
2024 names32 = intel_names32;
2025 names16 = intel_names16;
2026 names8 = intel_names8;
2027 names8rex = intel_names8rex;
2028 names_seg = intel_names_seg;
2029 index16 = intel_index16;
2030 open_char = '[';
2031 close_char = ']';
2032 separator_char = '+';
2033 scale_char = '*';
2034 }
2035 else
2036 {
2037 names64 = att_names64;
2038 names32 = att_names32;
2039 names16 = att_names16;
2040 names8 = att_names8;
2041 names8rex = att_names8rex;
2042 names_seg = att_names_seg;
2043 index16 = att_index16;
2044 open_char = '(';
2045 close_char = ')';
2046 separator_char = ',';
2047 scale_char = ',';
2048 }
2da11e11 2049
4fe53c98 2050 /* The output looks better if we put 7 bytes on a line, since that
c608c12e 2051 puts most long word instructions on a single line. */
4fe53c98 2052 info->bytes_per_line = 7;
252b5132 2053
26ca5450 2054 info->private_data = &priv;
252b5132
RH		 2055 priv.max_fetched = priv.the_buffer;
2056 priv.insn_start = pc;
252b5132
RH		 2057
2058 obuf[0] = 0;
2059 op1out[0] = 0;
2060 op2out[0] = 0;
2061 op3out[0] = 0;
2062
2063 op_index[0] = op_index[1] = op_index[2] = -1;
2064
2065 the_info = info;
2066 start_pc = pc;
e396998b
AM		 2067 start_codep = priv.the_buffer;
2068 codep = priv.the_buffer;
252b5132 2069
5076851f
ILT		 2070 if (setjmp (priv.bailout) != 0)
2071 {
7d421014
ILT		 2072 const char *name;
2073
5076851f 2074 /* Getting here means we tried for data but didn't get it. That
e396998b
AM		 2075 means we have an incomplete instruction of some sort. Just
2076 print the first byte as a prefix or a .byte pseudo-op. */
2077 if (codep > priv.the_buffer)
5076851f 2078 {
e396998b 2079 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2080 if (name != NULL)
2081 (*info->fprintf_func) (info->stream, "%s", name);
2082 else
5076851f 2083 {
7d421014
ILT		 2084 /* Just print the first byte as a .byte instruction. */
2085 (*info->fprintf_func) (info->stream, ".byte 0x%x",
e396998b 2086 (unsigned int) priv.the_buffer[0]);
5076851f 2087 }
5076851f 2088
7d421014 2089 return 1;
5076851f
ILT		 2090 }
2091
2092 return -1;
2093 }
2094
52b15da3 2095 obufp = obuf;
252b5132
RH		 2096 ckprefix ();
2097
2098 insn_codep = codep;
e396998b 2099 sizeflag = priv.orig_sizeflag;
252b5132
RH		 2100
2101 FETCH_DATA (info, codep + 1);
2102 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
2103
252b5132
RH		 2104 if ((prefixes & PREFIX_FWAIT)
2105 && ((*codep < 0xd8) || (*codep > 0xdf)))
2106 {
7d421014
ILT		 2107 const char *name;
2108
2109 /* fwait not followed by floating point instruction. Print the
db6eb5be 2110 first prefix, which is probably fwait itself. */
e396998b 2111 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2112 if (name == NULL)
2113 name = INTERNAL_DISASSEMBLER_ERROR;
2114 (*info->fprintf_func) (info->stream, "%s", name);
2115 return 1;
252b5132
RH		 2116 }
2117
252b5132
RH		 2118 if (*codep == 0x0f)
2119 {
2120 FETCH_DATA (info, codep + 2);
6439fc28 2121 dp = &dis386_twobyte[*++codep];
252b5132 2122 need_modrm = twobyte_has_modrm[*codep];
041bd2e0 2123 uses_SSE_prefix = twobyte_uses_SSE_prefix[*codep];
252b5132
RH		 2124 }
2125 else
2126 {
6439fc28 2127 dp = &dis386[*codep];
252b5132 2128 need_modrm = onebyte_has_modrm[*codep];
041bd2e0 2129 uses_SSE_prefix = 0;
252b5132
RH		 2130 }
2131 codep++;
2132
041bd2e0 2133 if (!uses_SSE_prefix && (prefixes & PREFIX_REPZ))
7d421014
ILT		 2134 {
2135 oappend ("repz ");
2136 used_prefixes |= PREFIX_REPZ;
2137 }
041bd2e0 2138 if (!uses_SSE_prefix && (prefixes & PREFIX_REPNZ))
7d421014
ILT		 2139 {
2140 oappend ("repnz ");
2141 used_prefixes |= PREFIX_REPNZ;
2142 }
c608c12e 2143 if (prefixes & PREFIX_LOCK)
7d421014
ILT		 2144 {
2145 oappend ("lock ");
2146 used_prefixes |= PREFIX_LOCK;
2147 }
c608c12e 2148
c608c12e
AM		 2149 if (prefixes & PREFIX_ADDR)
2150 {
2151 sizeflag ^= AFLAG;
6439fc28 2152 if (dp->bytemode3 != loop_jcxz_mode || intel_syntax)
3ffd33cf 2153 {
c1a64871 2154 if ((sizeflag & AFLAG) || mode_64bit)
3ffd33cf
AM		 2155 oappend ("addr32 ");
2156 else
2157 oappend ("addr16 ");
2158 used_prefixes |= PREFIX_ADDR;
2159 }
2160 }
2161
2162 if (!uses_SSE_prefix && (prefixes & PREFIX_DATA))
2163 {
2164 sizeflag ^= DFLAG;
6439fc28
AM		 2165 if (dp->bytemode3 == cond_jump_mode
2166 && dp->bytemode1 == v_mode
2167 && !intel_syntax)
3ffd33cf
AM		 2168 {
2169 if (sizeflag & DFLAG)
2170 oappend ("data32 ");
2171 else
2172 oappend ("data16 ");
2173 used_prefixes |= PREFIX_DATA;
2174 }
2175 }
2176
252b5132
RH		 2177 if (need_modrm)
2178 {
2179 FETCH_DATA (info, codep + 1);
2180 mod = (*codep >> 6) & 3;
2181 reg = (*codep >> 3) & 7;
2182 rm = *codep & 7;
2183 }
2184
2185 if (dp->name == NULL && dp->bytemode1 == FLOATCODE)
2186 {
2187 dofloat (sizeflag);
2188 }
2189 else
2190 {
041bd2e0 2191 int index;
252b5132 2192 if (dp->name == NULL)
c608c12e 2193 {
6439fc28 2194 switch (dp->bytemode1)
c608c12e 2195 {
6439fc28
AM		 2196 case USE_GROUPS:
2197 dp = &grps[dp->bytemode2][reg];
2198 break;
2199
2200 case USE_PREFIX_USER_TABLE:
2201 index = 0;
2202 used_prefixes |= (prefixes & PREFIX_REPZ);
2203 if (prefixes & PREFIX_REPZ)
2204 index = 1;
2205 else
2206 {
2207 used_prefixes |= (prefixes & PREFIX_DATA);
2208 if (prefixes & PREFIX_DATA)
2209 index = 2;
2210 else
2211 {
2212 used_prefixes |= (prefixes & PREFIX_REPNZ);
2213 if (prefixes & PREFIX_REPNZ)
2214 index = 3;
2215 }
2216 }
2217 dp = &prefix_user_table[dp->bytemode2][index];
2218 break;
252b5132 2219
6439fc28
AM		 2220 case X86_64_SPECIAL:
2221 dp = &x86_64_table[dp->bytemode2][mode_64bit];
2222 break;
252b5132 2223
0f10071e
ML		 2224 case PADLOCK_SPECIAL:
2225 FETCH_DATA (info, codep + 1);
2226 index = (*codep++ >> 3) & 0x07;
2227 dp = &padlock_table[dp->bytemode2][index];
2228 break;
2229
6439fc28
AM		 2230 default:
2231 oappend (INTERNAL_DISASSEMBLER_ERROR);
2232 break;
2233 }
2234 }
252b5132 2235
6439fc28
AM		 2236 if (putop (dp->name, sizeflag) == 0)
2237 {
2238 obufp = op1out;
2239 op_ad = 2;
2240 if (dp->op1)
6608db57 2241 (*dp->op1) (dp->bytemode1, sizeflag);
6439fc28
AM		 2242
2243 obufp = op2out;
2244 op_ad = 1;
2245 if (dp->op2)
6608db57 2246 (*dp->op2) (dp->bytemode2, sizeflag);
6439fc28
AM		 2247
2248 obufp = op3out;
2249 op_ad = 0;
2250 if (dp->op3)
6608db57 2251 (*dp->op3) (dp->bytemode3, sizeflag);
6439fc28 2252 }
252b5132
RH		 2253 }
2254
7d421014
ILT		 2255 /* See if any prefixes were not used. If so, print the first one
2256 separately. If we don't do this, we'll wind up printing an
2257 instruction stream which does not precisely correspond to the
2258 bytes we are disassembling. */
2259 if ((prefixes & ~used_prefixes) != 0)
2260 {
2261 const char *name;
2262
e396998b 2263 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
7d421014
ILT		 2264 if (name == NULL)
2265 name = INTERNAL_DISASSEMBLER_ERROR;
2266 (*info->fprintf_func) (info->stream, "%s", name);
2267 return 1;
2268 }
52b15da3
JH		 2269 if (rex & ~rex_used)
2270 {
2271 const char *name;
e396998b 2272 name = prefix_name (rex | 0x40, priv.orig_sizeflag);
52b15da3
JH		 2273 if (name == NULL)
2274 name = INTERNAL_DISASSEMBLER_ERROR;
2275 (*info->fprintf_func) (info->stream, "%s ", name);
2276 }
7d421014 2277
252b5132
RH		 2278 obufp = obuf + strlen (obuf);
2279 for (i = strlen (obuf); i < 6; i++)
2280 oappend (" ");
2281 oappend (" ");
2282 (*info->fprintf_func) (info->stream, "%s", obuf);
2283
2284 /* The enter and bound instructions are printed with operands in the same
2285 order as the intel book; everything else is printed in reverse order. */
2da11e11 2286 if (intel_syntax || two_source_ops)
252b5132
RH		 2287 {
2288 first = op1out;
2289 second = op2out;
2290 third = op3out;
2291 op_ad = op_index[0];
2292 op_index[0] = op_index[2];
2293 op_index[2] = op_ad;
2294 }
2295 else
2296 {
2297 first = op3out;
2298 second = op2out;
2299 third = op1out;
2300 }
2301 needcomma = 0;
2302 if (*first)
2303 {
52b15da3 2304 if (op_index[0] != -1 && !op_riprel[0])
252b5132
RH		 2305 (*info->print_address_func) ((bfd_vma) op_address[op_index[0]], info);
2306 else
2307 (*info->fprintf_func) (info->stream, "%s", first);
2308 needcomma = 1;
2309 }
2310 if (*second)
2311 {
2312 if (needcomma)
2313 (*info->fprintf_func) (info->stream, ",");
52b15da3 2314 if (op_index[1] != -1 && !op_riprel[1])
252b5132
RH		 2315 (*info->print_address_func) ((bfd_vma) op_address[op_index[1]], info);
2316 else
2317 (*info->fprintf_func) (info->stream, "%s", second);
2318 needcomma = 1;
2319 }
2320 if (*third)
2321 {
2322 if (needcomma)
2323 (*info->fprintf_func) (info->stream, ",");
52b15da3 2324 if (op_index[2] != -1 && !op_riprel[2])
252b5132
RH		 2325 (*info->print_address_func) ((bfd_vma) op_address[op_index[2]], info);
2326 else
2327 (*info->fprintf_func) (info->stream, "%s", third);
2328 }
52b15da3
JH		 2329 for (i = 0; i < 3; i++)
2330 if (op_index[i] != -1 && op_riprel[i])
2331 {
2332 (*info->fprintf_func) (info->stream, " # ");
2333 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
2334 + op_address[op_index[i]]), info);
2335 }
e396998b 2336 return codep - priv.the_buffer;
252b5132
RH		 2337}
2338
6439fc28 2339static const char *float_mem[] = {
252b5132 2340 /* d8 */
6439fc28
AM		 2341 "fadd{s||s|}",
2342 "fmul{s||s|}",
2343 "fcom{s||s|}",
2344 "fcomp{s||s|}",
2345 "fsub{s||s|}",
2346 "fsubr{s||s|}",
2347 "fdiv{s||s|}",
2348 "fdivr{s||s|}",
db6eb5be 2349 /* d9 */
6439fc28 2350 "fld{s||s|}",
252b5132 2351 "(bad)",
6439fc28
AM		 2352 "fst{s||s|}",
2353 "fstp{s||s|}",
252b5132
RH		 2354 "fldenv",
2355 "fldcw",
2356 "fNstenv",
2357 "fNstcw",
2358 /* da */
6439fc28
AM		 2359 "fiadd{l||l|}",
2360 "fimul{l||l|}",
2361 "ficom{l||l|}",
2362 "ficomp{l||l|}",
2363 "fisub{l||l|}",
2364 "fisubr{l||l|}",
2365 "fidiv{l||l|}",
2366 "fidivr{l||l|}",
252b5132 2367 /* db */
6439fc28 2368 "fild{l||l|}",
ca164297 2369 "fisttp{l||l|}",
6439fc28
AM		 2370 "fist{l||l|}",
2371 "fistp{l||l|}",
252b5132 2372 "(bad)",
6439fc28 2373 "fld{t||t|}",
252b5132 2374 "(bad)",
6439fc28 2375 "fstp{t||t|}",
252b5132 2376 /* dc */
6439fc28
AM		 2377 "fadd{l||l|}",
2378 "fmul{l||l|}",
2379 "fcom{l||l|}",
2380 "fcomp{l||l|}",
2381 "fsub{l||l|}",
2382 "fsubr{l||l|}",
2383 "fdiv{l||l|}",
2384 "fdivr{l||l|}",
252b5132 2385 /* dd */
6439fc28 2386 "fld{l||l|}",
ca164297 2387 "fisttpll",
6439fc28
AM		 2388 "fst{l||l|}",
2389 "fstp{l||l|}",
252b5132
RH		 2390 "frstor",
2391 "(bad)",
2392 "fNsave",
2393 "fNstsw",
2394 /* de */
2395 "fiadd",
2396 "fimul",
2397 "ficom",
2398 "ficomp",
2399 "fisub",
2400 "fisubr",
2401 "fidiv",
2402 "fidivr",
2403 /* df */
2404 "fild",
ca164297 2405 "fisttp",
252b5132
RH		 2406 "fist",
2407 "fistp",
2408 "fbld",
6439fc28 2409 "fild{ll||ll|}",
252b5132
RH		 2410 "fbstp",
2411 "fistpll",
2412};
2413
2414#define ST OP_ST, 0
2415#define STi OP_STi, 0
2416
57d91c3c
ILT		 2417#define FGRPd9_2 NULL, NULL, 0, NULL, 0, NULL, 0
2418#define FGRPd9_4 NULL, NULL, 1, NULL, 0, NULL, 0
2419#define FGRPd9_5 NULL, NULL, 2, NULL, 0, NULL, 0
2420#define FGRPd9_6 NULL, NULL, 3, NULL, 0, NULL, 0
2421#define FGRPd9_7 NULL, NULL, 4, NULL, 0, NULL, 0
2422#define FGRPda_5 NULL, NULL, 5, NULL, 0, NULL, 0
2423#define FGRPdb_4 NULL, NULL, 6, NULL, 0, NULL, 0
2424#define FGRPde_3 NULL, NULL, 7, NULL, 0, NULL, 0
2425#define FGRPdf_4 NULL, NULL, 8, NULL, 0, NULL, 0
252b5132 2426
2da11e11 2427static const struct dis386 float_reg[][8] = {
252b5132
RH		 2428 /* d8 */
2429 {
57d91c3c
ILT		 2430 { "fadd", ST, STi, XX },
2431 { "fmul", ST, STi, XX },
2432 { "fcom", STi, XX, XX },
2433 { "fcomp", STi, XX, XX },
2434 { "fsub", ST, STi, XX },
2435 { "fsubr", ST, STi, XX },
2436 { "fdiv", ST, STi, XX },
2437 { "fdivr", ST, STi, XX },
252b5132
RH		 2438 },
2439 /* d9 */
2440 {
57d91c3c
ILT		 2441 { "fld", STi, XX, XX },
2442 { "fxch", STi, XX, XX },
252b5132 2443 { FGRPd9_2 },
57d91c3c 2444 { "(bad)", XX, XX, XX },
252b5132
RH		 2445 { FGRPd9_4 },
2446 { FGRPd9_5 },
2447 { FGRPd9_6 },
2448 { FGRPd9_7 },
2449 },
2450 /* da */
2451 {
57d91c3c
ILT		 2452 { "fcmovb", ST, STi, XX },
2453 { "fcmove", ST, STi, XX },
2454 { "fcmovbe",ST, STi, XX },
2455 { "fcmovu", ST, STi, XX },
2456 { "(bad)", XX, XX, XX },
252b5132 2457 { FGRPda_5 },
57d91c3c
ILT		 2458 { "(bad)", XX, XX, XX },
2459 { "(bad)", XX, XX, XX },
252b5132
RH		 2460 },
2461 /* db */
2462 {
57d91c3c
ILT		 2463 { "fcmovnb",ST, STi, XX },
2464 { "fcmovne",ST, STi, XX },
2465 { "fcmovnbe",ST, STi, XX },
2466 { "fcmovnu",ST, STi, XX },
252b5132 2467 { FGRPdb_4 },
57d91c3c
ILT		 2468 { "fucomi", ST, STi, XX },
2469 { "fcomi", ST, STi, XX },
2470 { "(bad)", XX, XX, XX },
252b5132
RH		 2471 },
2472 /* dc */
2473 {
57d91c3c
ILT		 2474 { "fadd", STi, ST, XX },
2475 { "fmul", STi, ST, XX },
2476 { "(bad)", XX, XX, XX },
2477 { "(bad)", XX, XX, XX },
252b5132 2478#if UNIXWARE_COMPAT
57d91c3c
ILT		 2479 { "fsub", STi, ST, XX },
2480 { "fsubr", STi, ST, XX },
2481 { "fdiv", STi, ST, XX },
2482 { "fdivr", STi, ST, XX },
252b5132 2483#else
57d91c3c
ILT		 2484 { "fsubr", STi, ST, XX },
2485 { "fsub", STi, ST, XX },
2486 { "fdivr", STi, ST, XX },
2487 { "fdiv", STi, ST, XX },
252b5132
RH		 2488#endif
2489 },
2490 /* dd */
2491 {
57d91c3c
ILT		 2492 { "ffree", STi, XX, XX },
2493 { "(bad)", XX, XX, XX },
2494 { "fst", STi, XX, XX },
2495 { "fstp", STi, XX, XX },
2496 { "fucom", STi, XX, XX },
2497 { "fucomp", STi, XX, XX },
2498 { "(bad)", XX, XX, XX },
2499 { "(bad)", XX, XX, XX },
252b5132
RH		 2500 },
2501 /* de */
2502 {
57d91c3c
ILT		 2503 { "faddp", STi, ST, XX },
2504 { "fmulp", STi, ST, XX },
2505 { "(bad)", XX, XX, XX },
252b5132
RH		 2506 { FGRPde_3 },
2507#if UNIXWARE_COMPAT
57d91c3c
ILT		 2508 { "fsubp", STi, ST, XX },
2509 { "fsubrp", STi, ST, XX },
2510 { "fdivp", STi, ST, XX },
2511 { "fdivrp", STi, ST, XX },
252b5132 2512#else
57d91c3c
ILT		 2513 { "fsubrp", STi, ST, XX },
2514 { "fsubp", STi, ST, XX },
2515 { "fdivrp", STi, ST, XX },
2516 { "fdivp", STi, ST, XX },
252b5132
RH		 2517#endif
2518 },
2519 /* df */
2520 {
c2419411 2521 { "ffreep", STi, XX, XX },
57d91c3c
ILT		 2522 { "(bad)", XX, XX, XX },
2523 { "(bad)", XX, XX, XX },
2524 { "(bad)", XX, XX, XX },
252b5132 2525 { FGRPdf_4 },
57d91c3c
ILT		 2526 { "fucomip",ST, STi, XX },
2527 { "fcomip", ST, STi, XX },
2528 { "(bad)", XX, XX, XX },
252b5132
RH		 2529 },
2530};
2531
252b5132
RH		 2532static char *fgrps[][8] = {
2533 /* d9_2 0 */
2534 {
2535 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2536 },
2537
2538 /* d9_4 1 */
2539 {
2540 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
2541 },
2542
2543 /* d9_5 2 */
2544 {
2545 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
2546 },
2547
2548 /* d9_6 3 */
2549 {
2550 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
2551 },
2552
2553 /* d9_7 4 */
2554 {
2555 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
2556 },
2557
2558 /* da_5 5 */
2559 {
2560 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2561 },
2562
2563 /* db_4 6 */
2564 {
2565 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
2566 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
2567 },
2568
2569 /* de_3 7 */
2570 {
2571 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2572 },
2573
2574 /* df_4 8 */
2575 {
2576 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
2577 },
2578};
2579
2580static void
26ca5450 2581dofloat (int sizeflag)
252b5132 2582{
2da11e11 2583 const struct dis386 *dp;
252b5132
RH		 2584 unsigned char floatop;
2585
2586 floatop = codep[-1];
2587
2588 if (mod != 3)
2589 {
6608db57 2590 putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag);
252b5132
RH		 2591 obufp = op1out;
2592 if (floatop == 0xdb)
db6eb5be 2593 OP_E (x_mode, sizeflag);
252b5132 2594 else if (floatop == 0xdd)
db6eb5be 2595 OP_E (d_mode, sizeflag);
2da11e11 2596 else
db6eb5be 2597 OP_E (v_mode, sizeflag);
252b5132
RH		 2598 return;
2599 }
6608db57 2600 /* Skip mod/rm byte. */
4bba6815 2601 MODRM_CHECK;
252b5132
RH		 2602 codep++;
2603
2604 dp = &float_reg[floatop - 0xd8][reg];
2605 if (dp->name == NULL)
2606 {
2607 putop (fgrps[dp->bytemode1][rm], sizeflag);
2608
6608db57 2609 /* Instruction fnstsw is only one with strange arg. */
252b5132
RH		 2610 if (floatop == 0xdf && codep[-1] == 0xe0)
2611 strcpy (op1out, names16[0]);
2612 }
2613 else
2614 {
2615 putop (dp->name, sizeflag);
2616
2617 obufp = op1out;
2618 if (dp->op1)
6608db57 2619 (*dp->op1) (dp->bytemode1, sizeflag);
252b5132
RH		 2620 obufp = op2out;
2621 if (dp->op2)
6608db57 2622 (*dp->op2) (dp->bytemode2, sizeflag);
252b5132
RH		 2623 }
2624}
2625
252b5132 2626static void
26ca5450 2627OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 2628{
2629 oappend ("%st");
2630}
2631
252b5132 2632static void
26ca5450 2633OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 2634{
2635 sprintf (scratchbuf, "%%st(%d)", rm);
d708bcba 2636 oappend (scratchbuf + intel_syntax);
252b5132
RH		 2637}
2638
6608db57 2639/* Capital letters in template are macros. */
6439fc28 2640static int
26ca5450 2641putop (const char *template, int sizeflag)
252b5132 2642{
2da11e11 2643 const char *p;
6439fc28 2644 int alt;
252b5132
RH		 2645
2646 for (p = template; *p; p++)
2647 {
2648 switch (*p)
2649 {
2650 default:
2651 *obufp++ = *p;
2652 break;
6439fc28
AM		 2653 case '{':
2654 alt = 0;
2655 if (intel_syntax)
2656 alt += 1;
2657 if (mode_64bit)
2658 alt += 2;
2659 while (alt != 0)
2660 {
2661 while (*++p != '|')
2662 {
2663 if (*p == '}')
2664 {
2665 /* Alternative not valid. */
2666 strcpy (obuf, "(bad)");
2667 obufp = obuf + 5;
2668 return 1;
2669 }
2670 else if (*p == '\0')
2671 abort ();
2672 }
2673 alt--;
2674 }
2675 break;
2676 case '|':
2677 while (*++p != '}')
2678 {
2679 if (*p == '\0')
2680 abort ();
2681 }
2682 break;
2683 case '}':
2684 break;
252b5132 2685 case 'A':
db6eb5be
AM		 2686 if (intel_syntax)
2687 break;
e396998b 2688 if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132
RH		 2689 *obufp++ = 'b';
2690 break;
2691 case 'B':
db6eb5be
AM		 2692 if (intel_syntax)
2693 break;
252b5132
RH		 2694 if (sizeflag & SUFFIX_ALWAYS)
2695 *obufp++ = 'b';
252b5132
RH		 2696 break;
2697 case 'E': /* For jcxz/jecxz */
c1a64871
JH		 2698 if (mode_64bit)
2699 {
2700 if (sizeflag & AFLAG)
2701 *obufp++ = 'r';
2702 else
2703 *obufp++ = 'e';
2704 }
2705 else
2706 if (sizeflag & AFLAG)
2707 *obufp++ = 'e';
3ffd33cf
AM		 2708 used_prefixes |= (prefixes & PREFIX_ADDR);
2709 break;
2710 case 'F':
db6eb5be
AM		 2711 if (intel_syntax)
2712 break;
e396998b 2713 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
3ffd33cf
AM		 2714 {
2715 if (sizeflag & AFLAG)
c1a64871 2716 *obufp++ = mode_64bit ? 'q' : 'l';
3ffd33cf 2717 else
c1a64871 2718 *obufp++ = mode_64bit ? 'l' : 'w';
3ffd33cf
AM		 2719 used_prefixes |= (prefixes & PREFIX_ADDR);
2720 }
252b5132 2721 break;
5dd0794d 2722 case 'H':
db6eb5be
AM		 2723 if (intel_syntax)
2724 break;
5dd0794d
AM		 2725 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
2726 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
2727 {
2728 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
2729 *obufp++ = ',';
2730 *obufp++ = 'p';
2731 if (prefixes & PREFIX_DS)
2732 *obufp++ = 't';
2733 else
2734 *obufp++ = 'n';
2735 }
2736 break;
252b5132 2737 case 'L':
db6eb5be
AM		 2738 if (intel_syntax)
2739 break;
252b5132
RH		 2740 if (sizeflag & SUFFIX_ALWAYS)
2741 *obufp++ = 'l';
252b5132
RH		 2742 break;
2743 case 'N':
2744 if ((prefixes & PREFIX_FWAIT) == 0)
2745 *obufp++ = 'n';
7d421014
ILT		 2746 else
2747 used_prefixes |= PREFIX_FWAIT;
252b5132 2748 break;
52b15da3
JH		 2749 case 'O':
2750 USED_REX (REX_MODE64);
2751 if (rex & REX_MODE64)
6439fc28 2752 *obufp++ = 'o';
52b15da3
JH		 2753 else
2754 *obufp++ = 'd';
2755 break;
6439fc28 2756 case 'T':
db6eb5be
AM		 2757 if (intel_syntax)
2758 break;
6439fc28
AM		 2759 if (mode_64bit)
2760 {
2761 *obufp++ = 'q';
2762 break;
2763 }
6608db57 2764 /* Fall through. */
252b5132 2765 case 'P':
db6eb5be
AM		 2766 if (intel_syntax)
2767 break;
252b5132 2768 if ((prefixes & PREFIX_DATA)
52b15da3 2769 || (rex & REX_MODE64)
e396998b 2770 || (sizeflag & SUFFIX_ALWAYS))
252b5132 2771 {
52b15da3
JH		 2772 USED_REX (REX_MODE64);
2773 if (rex & REX_MODE64)
2774 *obufp++ = 'q';
c2419411 2775 else
52b15da3
JH		 2776 {
2777 if (sizeflag & DFLAG)
2778 *obufp++ = 'l';
2779 else
2780 *obufp++ = 'w';
2781 used_prefixes |= (prefixes & PREFIX_DATA);
2782 }
252b5132
RH		 2783 }
2784 break;
6439fc28 2785 case 'U':
db6eb5be
AM		 2786 if (intel_syntax)
2787 break;
6439fc28
AM		 2788 if (mode_64bit)
2789 {
2790 *obufp++ = 'q';
2791 break;
2792 }
6608db57 2793 /* Fall through. */
252b5132 2794 case 'Q':
db6eb5be
AM		 2795 if (intel_syntax)
2796 break;
90530880 2797 USED_REX (REX_MODE64);
e396998b 2798 if (mod != 3 || (sizeflag & SUFFIX_ALWAYS))
252b5132 2799 {
52b15da3
JH		 2800 if (rex & REX_MODE64)
2801 *obufp++ = 'q';
252b5132 2802 else
52b15da3
JH		 2803 {
2804 if (sizeflag & DFLAG)
2805 *obufp++ = 'l';
2806 else
2807 *obufp++ = 'w';
2808 used_prefixes |= (prefixes & PREFIX_DATA);
2809 }
252b5132
RH		 2810 }
2811 break;
2812 case 'R':
52b15da3 2813 USED_REX (REX_MODE64);
db6eb5be 2814 if (intel_syntax)
c608c12e 2815 {
52b15da3
JH		 2816 if (rex & REX_MODE64)
2817 {
2818 *obufp++ = 'q';
2819 *obufp++ = 't';
2820 }
2821 else if (sizeflag & DFLAG)
c608c12e
AM		 2822 {
2823 *obufp++ = 'd';
2824 *obufp++ = 'q';
2825 }
2826 else
2827 {
2828 *obufp++ = 'w';
2829 *obufp++ = 'd';
2830 }
2831 }
252b5132 2832 else
c608c12e 2833 {
52b15da3
JH		 2834 if (rex & REX_MODE64)
2835 *obufp++ = 'q';
2836 else if (sizeflag & DFLAG)
c608c12e
AM		 2837 *obufp++ = 'l';
2838 else
2839 *obufp++ = 'w';
2840 }
52b15da3
JH		 2841 if (!(rex & REX_MODE64))
2842 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 2843 break;
2844 case 'S':
db6eb5be
AM		 2845 if (intel_syntax)
2846 break;
252b5132
RH		 2847 if (sizeflag & SUFFIX_ALWAYS)
2848 {
52b15da3
JH		 2849 if (rex & REX_MODE64)
2850 *obufp++ = 'q';
252b5132 2851 else
52b15da3
JH		 2852 {
2853 if (sizeflag & DFLAG)
2854 *obufp++ = 'l';
2855 else
2856 *obufp++ = 'w';
2857 used_prefixes |= (prefixes & PREFIX_DATA);
2858 }
252b5132 2859 }
252b5132 2860 break;
041bd2e0
JH		 2861 case 'X':
2862 if (prefixes & PREFIX_DATA)
2863 *obufp++ = 'd';
2864 else
2865 *obufp++ = 's';
db6eb5be 2866 used_prefixes |= (prefixes & PREFIX_DATA);
041bd2e0 2867 break;
76f227a5 2868 case 'Y':
db6eb5be
AM		 2869 if (intel_syntax)
2870 break;
76f227a5
JH		 2871 if (rex & REX_MODE64)
2872 {
2873 USED_REX (REX_MODE64);
2874 *obufp++ = 'q';
2875 }
2876 break;
52b15da3 2877 /* implicit operand size 'l' for i386 or 'q' for x86-64 */
252b5132 2878 case 'W':
252b5132 2879 /* operand size flag for cwtl, cbtw */
52b15da3
JH		 2880 USED_REX (0);
2881 if (rex)
2882 *obufp++ = 'l';
2883 else if (sizeflag & DFLAG)
252b5132
RH		 2884 *obufp++ = 'w';
2885 else
2886 *obufp++ = 'b';
db6eb5be 2887 if (intel_syntax)
c608c12e 2888 {
52b15da3
JH		 2889 if (rex)
2890 {
2891 *obufp++ = 'q';
2892 *obufp++ = 'e';
2893 }
c608c12e
AM		 2894 if (sizeflag & DFLAG)
2895 {
2896 *obufp++ = 'd';
2897 *obufp++ = 'e';
2898 }
2899 else
2900 {
2901 *obufp++ = 'w';
2902 }
2903 }
52b15da3
JH		 2904 if (!rex)
2905 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 2906 break;
2907 }
2908 }
2909 *obufp = 0;
6439fc28 2910 return 0;
252b5132
RH		 2911}
2912
2913static void
26ca5450 2914oappend (const char *s)
252b5132
RH		 2915{
2916 strcpy (obufp, s);
2917 obufp += strlen (s);
2918}
2919
2920static void
26ca5450 2921append_seg (void)
252b5132
RH		 2922{
2923 if (prefixes & PREFIX_CS)
7d421014 2924 {
7d421014 2925 used_prefixes |= PREFIX_CS;
d708bcba 2926 oappend ("%cs:" + intel_syntax);
7d421014 2927 }
252b5132 2928 if (prefixes & PREFIX_DS)
7d421014 2929 {
7d421014 2930 used_prefixes |= PREFIX_DS;
d708bcba 2931 oappend ("%ds:" + intel_syntax);
7d421014 2932 }
252b5132 2933 if (prefixes & PREFIX_SS)
7d421014 2934 {
7d421014 2935 used_prefixes |= PREFIX_SS;
d708bcba 2936 oappend ("%ss:" + intel_syntax);
7d421014 2937 }
252b5132 2938 if (prefixes & PREFIX_ES)
7d421014 2939 {
7d421014 2940 used_prefixes |= PREFIX_ES;
d708bcba 2941 oappend ("%es:" + intel_syntax);
7d421014 2942 }
252b5132 2943 if (prefixes & PREFIX_FS)
7d421014 2944 {
7d421014 2945 used_prefixes |= PREFIX_FS;
d708bcba 2946 oappend ("%fs:" + intel_syntax);
7d421014 2947 }
252b5132 2948 if (prefixes & PREFIX_GS)
7d421014 2949 {
7d421014 2950 used_prefixes |= PREFIX_GS;
d708bcba 2951 oappend ("%gs:" + intel_syntax);
7d421014 2952 }
252b5132
RH		 2953}
2954
2955static void
26ca5450 2956OP_indirE (int bytemode, int sizeflag)
252b5132
RH		 2957{
2958 if (!intel_syntax)
2959 oappend ("*");
2960 OP_E (bytemode, sizeflag);
2961}
2962
52b15da3 2963static void
26ca5450 2964print_operand_value (char *buf, int hex, bfd_vma disp)
52b15da3
JH		 2965{
2966 if (mode_64bit)
2967 {
2968 if (hex)
2969 {
2970 char tmp[30];
2971 int i;
2972 buf[0] = '0';
2973 buf[1] = 'x';
2974 sprintf_vma (tmp, disp);
6608db57 2975 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
52b15da3
JH		 2976 strcpy (buf + 2, tmp + i);
2977 }
2978 else
2979 {
2980 bfd_signed_vma v = disp;
2981 char tmp[30];
2982 int i;
2983 if (v < 0)
2984 {
2985 *(buf++) = '-';
2986 v = -disp;
6608db57 2987 /* Check for possible overflow on 0x8000000000000000. */
52b15da3
JH		 2988 if (v < 0)
2989 {
2990 strcpy (buf, "9223372036854775808");
2991 return;
2992 }
2993 }
2994 if (!v)
2995 {
2996 strcpy (buf, "0");
2997 return;
2998 }
2999
3000 i = 0;
3001 tmp[29] = 0;
3002 while (v)
3003 {
6608db57 3004 tmp[28 - i] = (v % 10) + '0';
52b15da3
JH		 3005 v /= 10;
3006 i++;
3007 }
3008 strcpy (buf, tmp + 29 - i);
3009 }
3010 }
3011 else
3012 {
3013 if (hex)
3014 sprintf (buf, "0x%x", (unsigned int) disp);
3015 else
3016 sprintf (buf, "%d", (int) disp);
3017 }
3018}
3019
252b5132 3020static void
26ca5450 3021OP_E (int bytemode, int sizeflag)
252b5132 3022{
52b15da3
JH		 3023 bfd_vma disp;
3024 int add = 0;
3025 int riprel = 0;
3026 USED_REX (REX_EXTZ);
3027 if (rex & REX_EXTZ)
3028 add += 8;
252b5132 3029
6608db57 3030 /* Skip mod/rm byte. */
4bba6815 3031 MODRM_CHECK;
252b5132
RH		 3032 codep++;
3033
3034 if (mod == 3)
3035 {
3036 switch (bytemode)
3037 {
3038 case b_mode:
52b15da3
JH		 3039 USED_REX (0);
3040 if (rex)
3041 oappend (names8rex[rm + add]);
3042 else
3043 oappend (names8[rm + add]);
252b5132
RH		 3044 break;
3045 case w_mode:
52b15da3 3046 oappend (names16[rm + add]);
252b5132 3047 break;
2da11e11 3048 case d_mode:
52b15da3
JH		 3049 oappend (names32[rm + add]);
3050 break;
3051 case q_mode:
3052 oappend (names64[rm + add]);
3053 break;
3054 case m_mode:
3055 if (mode_64bit)
3056 oappend (names64[rm + add]);
3057 else
3058 oappend (names32[rm + add]);
2da11e11 3059 break;
252b5132 3060 case v_mode:
db6eb5be 3061 case dq_mode:
52b15da3
JH		 3062 USED_REX (REX_MODE64);
3063 if (rex & REX_MODE64)
3064 oappend (names64[rm + add]);
db6eb5be 3065 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
52b15da3 3066 oappend (names32[rm + add]);
252b5132 3067 else
52b15da3 3068 oappend (names16[rm + add]);
7d421014 3069 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132 3070 break;
2da11e11 3071 case 0:
c02908d2
AM		 3072 if (codep[-2] == 0xAE && codep[-1] == 0xF8)
3073 /* sfence */
3074 strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
3075 else if (codep[-2] == 0xAE && codep[-1] == 0xF0)
3076 /* mfence */
3077 ;
3078 else if (codep[-2] == 0xAE && codep[-1] == 0xe8)
3079 /* lfence */
3080 ;
3081 else
6608db57 3082 BadOp (); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */
c608c12e 3083 break;
252b5132 3084 default:
c608c12e 3085 oappend (INTERNAL_DISASSEMBLER_ERROR);
252b5132
RH		 3086 break;
3087 }
3088 return;
3089 }
3090
3091 disp = 0;
3092 append_seg ();
3093
c1a64871 3094 if ((sizeflag & AFLAG) || mode_64bit) /* 32 bit address mode */
252b5132
RH		 3095 {
3096 int havesib;
3097 int havebase;
3098 int base;
3099 int index = 0;
3100 int scale = 0;
3101
3102 havesib = 0;
3103 havebase = 1;
3104 base = rm;
3105
3106 if (base == 4)
3107 {
3108 havesib = 1;
3109 FETCH_DATA (the_info, codep + 1);
3110 scale = (*codep >> 6) & 3;
3111 index = (*codep >> 3) & 7;
3112 base = *codep & 7;
52b15da3
JH		 3113 USED_REX (REX_EXTY);
3114 USED_REX (REX_EXTZ);
3115 if (rex & REX_EXTY)
3116 index += 8;
3117 if (rex & REX_EXTZ)
3118 base += 8;
252b5132
RH		 3119 codep++;
3120 }
3121
3122 switch (mod)
3123 {
3124 case 0:
52b15da3 3125 if ((base & 7) == 5)
252b5132
RH		 3126 {
3127 havebase = 0;
c1a64871 3128 if (mode_64bit && !havesib && (sizeflag & AFLAG))
52b15da3
JH		 3129 riprel = 1;
3130 disp = get32s ();
252b5132
RH		 3131 }
3132 break;
3133 case 1:
3134 FETCH_DATA (the_info, codep + 1);
3135 disp = *codep++;
3136 if ((disp & 0x80) != 0)
3137 disp -= 0x100;
3138 break;
3139 case 2:
52b15da3 3140 disp = get32s ();
252b5132
RH		 3141 break;
3142 }
3143
3144 if (!intel_syntax)
db6eb5be
AM		 3145 if (mod != 0 || (base & 7) == 5)
3146 {
52b15da3 3147 print_operand_value (scratchbuf, !riprel, disp);
db6eb5be 3148 oappend (scratchbuf);
52b15da3
JH		 3149 if (riprel)
3150 {
3151 set_op (disp, 1);
3152 oappend ("(%rip)");
3153 }
db6eb5be 3154 }
2da11e11 3155
252b5132
RH		 3156 if (havebase || (havesib && (index != 4 || scale != 0)))
3157 {
db6eb5be
AM		 3158 if (intel_syntax)
3159 {
3160 switch (bytemode)
3161 {
3162 case b_mode:
3163 oappend ("BYTE PTR ");
3164 break;
3165 case w_mode:
3166 oappend ("WORD PTR ");
3167 break;
3168 case v_mode:
3169 oappend ("DWORD PTR ");
3170 break;
3171 case d_mode:
3172 oappend ("QWORD PTR ");
3173 break;
3174 case m_mode:
52b15da3
JH		 3175 if (mode_64bit)
3176 oappend ("DWORD PTR ");
3177 else
3178 oappend ("QWORD PTR ");
3179 break;
db6eb5be
AM		 3180 case x_mode:
3181 oappend ("XWORD PTR ");
3182 break;
3183 default:
3184 break;
3185 }
3186 }
252b5132 3187 *obufp++ = open_char;
52b15da3
JH		 3188 if (intel_syntax && riprel)
3189 oappend ("rip + ");
db6eb5be 3190 *obufp = '\0';
52b15da3
JH		 3191 USED_REX (REX_EXTZ);
3192 if (!havesib && (rex & REX_EXTZ))
3193 base += 8;
252b5132 3194 if (havebase)
c1a64871
JH		 3195 oappend (mode_64bit && (sizeflag & AFLAG)
3196 ? names64[base] : names32[base]);
252b5132
RH		 3197 if (havesib)
3198 {
3199 if (index != 4)
3200 {
db6eb5be
AM		 3201 if (intel_syntax)
3202 {
3203 if (havebase)
3204 {
3205 *obufp++ = separator_char;
3206 *obufp = '\0';
3207 }
3208 sprintf (scratchbuf, "%s",
c1a64871
JH		 3209 mode_64bit && (sizeflag & AFLAG)
3210 ? names64[index] : names32[index]);
db6eb5be
AM		 3211 }
3212 else
d708bcba 3213 sprintf (scratchbuf, ",%s",
c1a64871
JH		 3214 mode_64bit && (sizeflag & AFLAG)
3215 ? names64[index] : names32[index]);
252b5132
RH		 3216 oappend (scratchbuf);
3217 }
a02a862a 3218 if (scale != 0 || (!intel_syntax && index != 4))
db6eb5be
AM		 3219 {
3220 *obufp++ = scale_char;
3221 *obufp = '\0';
3222 sprintf (scratchbuf, "%d", 1 << scale);
3223 oappend (scratchbuf);
3224 }
252b5132 3225 }
db6eb5be
AM		 3226 if (intel_syntax)
3227 if (mod != 0 || (base & 7) == 5)
3228 {
6608db57 3229 /* Don't print zero displacements. */
db6eb5be
AM		 3230 if (disp != 0)
3231 {
d708bcba
AM		 3232 if ((bfd_signed_vma) disp > 0)
3233 {
3234 *obufp++ = '+';
3235 *obufp = '\0';
3236 }
3237
52b15da3 3238 print_operand_value (scratchbuf, 0, disp);
db6eb5be
AM		 3239 oappend (scratchbuf);
3240 }
3241 }
252b5132
RH		 3242
3243 *obufp++ = close_char;
db6eb5be 3244 *obufp = '\0';
252b5132
RH		 3245 }
3246 else if (intel_syntax)
db6eb5be
AM		 3247 {
3248 if (mod != 0 || (base & 7) == 5)
3249 {
252b5132
RH		 3250 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
3251 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
3252 ;
3253 else
3254 {
d708bcba 3255 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 3256 oappend (":");
3257 }
52b15da3 3258 print_operand_value (scratchbuf, 1, disp);
db6eb5be
AM		 3259 oappend (scratchbuf);
3260 }
3261 }
252b5132
RH		 3262 }
3263 else
3264 { /* 16 bit address mode */
3265 switch (mod)
3266 {
3267 case 0:
52b15da3 3268 if ((rm & 7) == 6)
252b5132
RH		 3269 {
3270 disp = get16 ();
3271 if ((disp & 0x8000) != 0)
3272 disp -= 0x10000;
3273 }
3274 break;
3275 case 1:
3276 FETCH_DATA (the_info, codep + 1);
3277 disp = *codep++;
3278 if ((disp & 0x80) != 0)
3279 disp -= 0x100;
3280 break;
3281 case 2:
3282 disp = get16 ();
3283 if ((disp & 0x8000) != 0)
3284 disp -= 0x10000;
3285 break;
3286 }
3287
3288 if (!intel_syntax)
db6eb5be
AM		 3289 if (mod != 0 || (rm & 7) == 6)
3290 {
52b15da3 3291 print_operand_value (scratchbuf, 0, disp);
db6eb5be
AM		 3292 oappend (scratchbuf);
3293 }
252b5132 3294
52b15da3 3295 if (mod != 0 || (rm & 7) != 6)
252b5132
RH		 3296 {
3297 *obufp++ = open_char;
db6eb5be 3298 *obufp = '\0';
52b15da3 3299 oappend (index16[rm + add]);
db6eb5be
AM		 3300 *obufp++ = close_char;
3301 *obufp = '\0';
252b5132
RH		 3302 }
3303 }
3304}
3305
252b5132 3306static void
26ca5450 3307OP_G (int bytemode, int sizeflag)
252b5132 3308{
52b15da3
JH		 3309 int add = 0;
3310 USED_REX (REX_EXTX);
3311 if (rex & REX_EXTX)
3312 add += 8;
252b5132
RH		 3313 switch (bytemode)
3314 {
3315 case b_mode:
52b15da3
JH		 3316 USED_REX (0);
3317 if (rex)
3318 oappend (names8rex[reg + add]);
3319 else
3320 oappend (names8[reg + add]);
252b5132
RH		 3321 break;
3322 case w_mode:
52b15da3 3323 oappend (names16[reg + add]);
252b5132
RH		 3324 break;
3325 case d_mode:
52b15da3
JH		 3326 oappend (names32[reg + add]);
3327 break;
3328 case q_mode:
3329 oappend (names64[reg + add]);
252b5132
RH		 3330 break;
3331 case v_mode:
52b15da3
JH		 3332 USED_REX (REX_MODE64);
3333 if (rex & REX_MODE64)
3334 oappend (names64[reg + add]);
3335 else if (sizeflag & DFLAG)
3336 oappend (names32[reg + add]);
252b5132 3337 else
52b15da3 3338 oappend (names16[reg + add]);
7d421014 3339 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3340 break;
3341 default:
3342 oappend (INTERNAL_DISASSEMBLER_ERROR);
3343 break;
3344 }
3345}
3346
52b15da3 3347static bfd_vma
26ca5450 3348get64 (void)
52b15da3 3349{
5dd0794d 3350 bfd_vma x;
52b15da3 3351#ifdef BFD64
5dd0794d
AM		 3352 unsigned int a;
3353 unsigned int b;
3354
52b15da3
JH		 3355 FETCH_DATA (the_info, codep + 8);
3356 a = *codep++ & 0xff;
3357 a |= (*codep++ & 0xff) << 8;
3358 a |= (*codep++ & 0xff) << 16;
3359 a |= (*codep++ & 0xff) << 24;
5dd0794d 3360 b = *codep++ & 0xff;
52b15da3
JH		 3361 b |= (*codep++ & 0xff) << 8;
3362 b |= (*codep++ & 0xff) << 16;
3363 b |= (*codep++ & 0xff) << 24;
3364 x = a + ((bfd_vma) b << 32);
3365#else
6608db57 3366 abort ();
5dd0794d 3367 x = 0;
52b15da3
JH		 3368#endif
3369 return x;
3370}
3371
3372static bfd_signed_vma
26ca5450 3373get32 (void)
252b5132 3374{
52b15da3 3375 bfd_signed_vma x = 0;
252b5132
RH		 3376
3377 FETCH_DATA (the_info, codep + 4);
52b15da3
JH		 3378 x = *codep++ & (bfd_signed_vma) 0xff;
3379 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
3380 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
3381 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
3382 return x;
3383}
3384
3385static bfd_signed_vma
26ca5450 3386get32s (void)
52b15da3
JH		 3387{
3388 bfd_signed_vma x = 0;
3389
3390 FETCH_DATA (the_info, codep + 4);
3391 x = *codep++ & (bfd_signed_vma) 0xff;
3392 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
3393 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
3394 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
3395
3396 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
3397
252b5132
RH		 3398 return x;
3399}
3400
3401static int
26ca5450 3402get16 (void)
252b5132
RH		 3403{
3404 int x = 0;
3405
3406 FETCH_DATA (the_info, codep + 2);
3407 x = *codep++ & 0xff;
3408 x |= (*codep++ & 0xff) << 8;
3409 return x;
3410}
3411
3412static void
26ca5450 3413set_op (bfd_vma op, int riprel)
252b5132
RH		 3414{
3415 op_index[op_ad] = op_ad;
7081ff04
AJ		 3416 if (mode_64bit)
3417 {
3418 op_address[op_ad] = op;
3419 op_riprel[op_ad] = riprel;
3420 }
3421 else
3422 {
3423 /* Mask to get a 32-bit address. */
3424 op_address[op_ad] = op & 0xffffffff;
3425 op_riprel[op_ad] = riprel & 0xffffffff;
3426 }
252b5132
RH		 3427}
3428
3429static void
26ca5450 3430OP_REG (int code, int sizeflag)
252b5132 3431{
2da11e11 3432 const char *s;
52b15da3
JH		 3433 int add = 0;
3434 USED_REX (REX_EXTZ);
3435 if (rex & REX_EXTZ)
3436 add = 8;
3437
3438 switch (code)
3439 {
3440 case indir_dx_reg:
d708bcba 3441 if (intel_syntax)
db6eb5be 3442 s = "[dx]";
d708bcba 3443 else
db6eb5be 3444 s = "(%dx)";
52b15da3
JH		 3445 break;
3446 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
3447 case sp_reg: case bp_reg: case si_reg: case di_reg:
3448 s = names16[code - ax_reg + add];
3449 break;
3450 case es_reg: case ss_reg: case cs_reg:
3451 case ds_reg: case fs_reg: case gs_reg:
3452 s = names_seg[code - es_reg + add];
3453 break;
3454 case al_reg: case ah_reg: case cl_reg: case ch_reg:
3455 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
3456 USED_REX (0);
3457 if (rex)
3458 s = names8rex[code - al_reg + add];
3459 else
3460 s = names8[code - al_reg];
3461 break;
6439fc28
AM		 3462 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
3463 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
3464 if (mode_64bit)
3465 {
3466 s = names64[code - rAX_reg + add];
3467 break;
3468 }
3469 code += eAX_reg - rAX_reg;
6608db57 3470 /* Fall through. */
52b15da3
JH		 3471 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
3472 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
3473 USED_REX (REX_MODE64);
3474 if (rex & REX_MODE64)
3475 s = names64[code - eAX_reg + add];
3476 else if (sizeflag & DFLAG)
3477 s = names32[code - eAX_reg + add];
3478 else
3479 s = names16[code - eAX_reg + add];
3480 used_prefixes |= (prefixes & PREFIX_DATA);
3481 break;
52b15da3
JH		 3482 default:
3483 s = INTERNAL_DISASSEMBLER_ERROR;
3484 break;
3485 }
3486 oappend (s);
3487}
3488
3489static void
26ca5450 3490OP_IMREG (int code, int sizeflag)
52b15da3
JH		 3491{
3492 const char *s;
252b5132
RH		 3493
3494 switch (code)
3495 {
3496 case indir_dx_reg:
d708bcba 3497 if (intel_syntax)
db6eb5be 3498 s = "[dx]";
d708bcba 3499 else
db6eb5be 3500 s = "(%dx)";
252b5132
RH		 3501 break;
3502 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
3503 case sp_reg: case bp_reg: case si_reg: case di_reg:
3504 s = names16[code - ax_reg];
3505 break;
3506 case es_reg: case ss_reg: case cs_reg:
3507 case ds_reg: case fs_reg: case gs_reg:
3508 s = names_seg[code - es_reg];
3509 break;
3510 case al_reg: case ah_reg: case cl_reg: case ch_reg:
3511 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
52b15da3
JH		 3512 USED_REX (0);
3513 if (rex)
3514 s = names8rex[code - al_reg];
3515 else
3516 s = names8[code - al_reg];
252b5132
RH		 3517 break;
3518 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
3519 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
52b15da3
JH		 3520 USED_REX (REX_MODE64);
3521 if (rex & REX_MODE64)
3522 s = names64[code - eAX_reg];
3523 else if (sizeflag & DFLAG)
252b5132
RH		 3524 s = names32[code - eAX_reg];
3525 else
3526 s = names16[code - eAX_reg];
7d421014 3527 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3528 break;
3529 default:
3530 s = INTERNAL_DISASSEMBLER_ERROR;
3531 break;
3532 }
3533 oappend (s);
3534}
3535
3536static void
26ca5450 3537OP_I (int bytemode, int sizeflag)
252b5132 3538{
52b15da3
JH		 3539 bfd_signed_vma op;
3540 bfd_signed_vma mask = -1;
252b5132
RH		 3541
3542 switch (bytemode)
3543 {
3544 case b_mode:
3545 FETCH_DATA (the_info, codep + 1);
52b15da3
JH		 3546 op = *codep++;
3547 mask = 0xff;
3548 break;
3549 case q_mode:
6439fc28
AM		 3550 if (mode_64bit)
3551 {
3552 op = get32s ();
3553 break;
3554 }
6608db57 3555 /* Fall through. */
252b5132 3556 case v_mode:
52b15da3
JH		 3557 USED_REX (REX_MODE64);
3558 if (rex & REX_MODE64)
3559 op = get32s ();
3560 else if (sizeflag & DFLAG)
3561 {
3562 op = get32 ();
3563 mask = 0xffffffff;
3564 }
252b5132 3565 else
52b15da3
JH		 3566 {
3567 op = get16 ();
3568 mask = 0xfffff;
3569 }
7d421014 3570 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3571 break;
3572 case w_mode:
52b15da3 3573 mask = 0xfffff;
252b5132
RH		 3574 op = get16 ();
3575 break;
3576 default:
3577 oappend (INTERNAL_DISASSEMBLER_ERROR);
3578 return;
3579 }
3580
52b15da3
JH		 3581 op &= mask;
3582 scratchbuf[0] = '$';
d708bcba
AM		 3583 print_operand_value (scratchbuf + 1, 1, op);
3584 oappend (scratchbuf + intel_syntax);
52b15da3
JH		 3585 scratchbuf[0] = '\0';
3586}
3587
3588static void
26ca5450 3589OP_I64 (int bytemode, int sizeflag)
52b15da3
JH		 3590{
3591 bfd_signed_vma op;
3592 bfd_signed_vma mask = -1;
3593
6439fc28
AM		 3594 if (!mode_64bit)
3595 {
3596 OP_I (bytemode, sizeflag);
3597 return;
3598 }
3599
52b15da3
JH		 3600 switch (bytemode)
3601 {
3602 case b_mode:
3603 FETCH_DATA (the_info, codep + 1);
3604 op = *codep++;
3605 mask = 0xff;
3606 break;
3607 case v_mode:
3608 USED_REX (REX_MODE64);
3609 if (rex & REX_MODE64)
3610 op = get64 ();
3611 else if (sizeflag & DFLAG)
3612 {
3613 op = get32 ();
3614 mask = 0xffffffff;
3615 }
3616 else
3617 {
3618 op = get16 ();
3619 mask = 0xfffff;
3620 }
3621 used_prefixes |= (prefixes & PREFIX_DATA);
3622 break;
3623 case w_mode:
3624 mask = 0xfffff;
3625 op = get16 ();
3626 break;
3627 default:
3628 oappend (INTERNAL_DISASSEMBLER_ERROR);
3629 return;
3630 }
3631
3632 op &= mask;
3633 scratchbuf[0] = '$';
d708bcba
AM		 3634 print_operand_value (scratchbuf + 1, 1, op);
3635 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3636 scratchbuf[0] = '\0';
3637}
3638
3639static void
26ca5450 3640OP_sI (int bytemode, int sizeflag)
252b5132 3641{
52b15da3
JH		 3642 bfd_signed_vma op;
3643 bfd_signed_vma mask = -1;
252b5132
RH		 3644
3645 switch (bytemode)
3646 {
3647 case b_mode:
3648 FETCH_DATA (the_info, codep + 1);
3649 op = *codep++;
3650 if ((op & 0x80) != 0)
3651 op -= 0x100;
52b15da3 3652 mask = 0xffffffff;
252b5132
RH		 3653 break;
3654 case v_mode:
52b15da3
JH		 3655 USED_REX (REX_MODE64);
3656 if (rex & REX_MODE64)
3657 op = get32s ();
3658 else if (sizeflag & DFLAG)
3659 {
3660 op = get32s ();
3661 mask = 0xffffffff;
3662 }
252b5132
RH		 3663 else
3664 {
52b15da3 3665 mask = 0xffffffff;
6608db57 3666 op = get16 ();
252b5132
RH		 3667 if ((op & 0x8000) != 0)
3668 op -= 0x10000;
3669 }
7d421014 3670 used_prefixes |= (prefixes & PREFIX_DATA);
252b5132
RH		 3671 break;
3672 case w_mode:
3673 op = get16 ();
52b15da3 3674 mask = 0xffffffff;
252b5132
RH		 3675 if ((op & 0x8000) != 0)
3676 op -= 0x10000;
3677 break;
3678 default:
3679 oappend (INTERNAL_DISASSEMBLER_ERROR);
3680 return;
3681 }
52b15da3
JH		 3682
3683 scratchbuf[0] = '$';
3684 print_operand_value (scratchbuf + 1, 1, op);
d708bcba 3685 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3686}
3687
3688static void
26ca5450 3689OP_J (int bytemode, int sizeflag)
252b5132 3690{
52b15da3 3691 bfd_vma disp;
7081ff04 3692 bfd_vma mask = -1;
252b5132
RH		 3693
3694 switch (bytemode)
3695 {
3696 case b_mode:
3697 FETCH_DATA (the_info, codep + 1);
3698 disp = *codep++;
3699 if ((disp & 0x80) != 0)
3700 disp -= 0x100;
3701 break;
3702 case v_mode:
3703 if (sizeflag & DFLAG)
52b15da3 3704 disp = get32s ();
252b5132
RH		 3705 else
3706 {
3707 disp = get16 ();
6608db57 3708 /* For some reason, a data16 prefix on a jump instruction
252b5132
RH		 3709 means that the pc is masked to 16 bits after the
3710 displacement is added! */
3711 mask = 0xffff;
3712 }
3713 break;
3714 default:
3715 oappend (INTERNAL_DISASSEMBLER_ERROR);
3716 return;
3717 }
3718 disp = (start_pc + codep - start_codep + disp) & mask;
52b15da3
JH		 3719 set_op (disp, 0);
3720 print_operand_value (scratchbuf, 1, disp);
252b5132
RH		 3721 oappend (scratchbuf);
3722}
3723
252b5132 3724static void
26ca5450 3725OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 3726{
d708bcba 3727 oappend (names_seg[reg]);
252b5132
RH		 3728}
3729
3730static void
26ca5450 3731OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
252b5132
RH		 3732{
3733 int seg, offset;
3734
c608c12e 3735 if (sizeflag & DFLAG)
252b5132 3736 {
c608c12e
AM		 3737 offset = get32 ();
3738 seg = get16 ();
252b5132 3739 }
c608c12e
AM		 3740 else
3741 {
3742 offset = get16 ();
3743 seg = get16 ();
3744 }
7d421014 3745 used_prefixes |= (prefixes & PREFIX_DATA);
d708bcba
AM		 3746 if (intel_syntax)
3747 sprintf (scratchbuf, "0x%x,0x%x", seg, offset);
3748 else
3749 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
c608c12e 3750 oappend (scratchbuf);
252b5132
RH		 3751}
3752
252b5132 3753static void
26ca5450 3754OP_OFF (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
252b5132 3755{
52b15da3 3756 bfd_vma off;
252b5132
RH		 3757
3758 append_seg ();
3759
c1a64871 3760 if ((sizeflag & AFLAG) || mode_64bit)
252b5132
RH		 3761 off = get32 ();
3762 else
3763 off = get16 ();
3764
3765 if (intel_syntax)
3766 {
3767 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 3768 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
252b5132 3769 {
d708bcba 3770 oappend (names_seg[ds_reg - es_reg]);
252b5132
RH		 3771 oappend (":");
3772 }
3773 }
52b15da3
JH		 3774 print_operand_value (scratchbuf, 1, off);
3775 oappend (scratchbuf);
3776}
6439fc28 3777
52b15da3 3778static void
26ca5450 3779OP_OFF64 (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
52b15da3
JH		 3780{
3781 bfd_vma off;
3782
6439fc28
AM		 3783 if (!mode_64bit)
3784 {
3785 OP_OFF (bytemode, sizeflag);
3786 return;
3787 }
3788
52b15da3
JH		 3789 append_seg ();
3790
6608db57 3791 off = get64 ();
52b15da3
JH		 3792
3793 if (intel_syntax)
3794 {
3795 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
db6eb5be 3796 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
52b15da3 3797 {
d708bcba 3798 oappend (names_seg[ds_reg - es_reg]);
52b15da3
JH		 3799 oappend (":");
3800 }
3801 }
3802 print_operand_value (scratchbuf, 1, off);
252b5132
RH		 3803 oappend (scratchbuf);
3804}
3805
3806static void
26ca5450 3807ptr_reg (int code, int sizeflag)
252b5132 3808{
2da11e11 3809 const char *s;
6608db57 3810 if (intel_syntax)
d708bcba
AM		 3811 oappend ("[");
3812 else
3813 oappend ("(");
3814
52b15da3
JH		 3815 USED_REX (REX_MODE64);
3816 if (rex & REX_MODE64)
c1a64871
JH		 3817 {
3818 if (!(sizeflag & AFLAG))
db6eb5be 3819 s = names32[code - eAX_reg];
c1a64871 3820 else
db6eb5be 3821 s = names64[code - eAX_reg];
c1a64871 3822 }
52b15da3 3823 else if (sizeflag & AFLAG)
252b5132
RH		 3824 s = names32[code - eAX_reg];
3825 else
3826 s = names16[code - eAX_reg];
3827 oappend (s);
6608db57 3828 if (intel_syntax)
d708bcba
AM		 3829 oappend ("]");
3830 else
3831 oappend (")");
252b5132
RH		 3832}
3833
3834static void
26ca5450 3835OP_ESreg (int code, int sizeflag)
252b5132 3836{
d708bcba 3837 oappend ("%es:" + intel_syntax);
252b5132
RH		 3838 ptr_reg (code, sizeflag);
3839}
3840
3841static void
26ca5450 3842OP_DSreg (int code, int sizeflag)
252b5132
RH		 3843{
3844 if ((prefixes
3845 & (PREFIX_CS
3846 | PREFIX_DS
3847 | PREFIX_SS
3848 | PREFIX_ES
3849 | PREFIX_FS
3850 | PREFIX_GS)) == 0)
3851 prefixes |= PREFIX_DS;
6608db57 3852 append_seg ();
252b5132
RH		 3853 ptr_reg (code, sizeflag);
3854}
3855
252b5132 3856static void
26ca5450 3857OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 3858{
52b15da3
JH		 3859 int add = 0;
3860 USED_REX (REX_EXTX);
3861 if (rex & REX_EXTX)
3862 add = 8;
d708bcba
AM		 3863 sprintf (scratchbuf, "%%cr%d", reg + add);
3864 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3865}
3866
252b5132 3867static void
26ca5450 3868OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 3869{
52b15da3
JH		 3870 int add = 0;
3871 USED_REX (REX_EXTX);
3872 if (rex & REX_EXTX)
3873 add = 8;
d708bcba 3874 if (intel_syntax)
6608db57 3875 sprintf (scratchbuf, "db%d", reg + add);
d708bcba 3876 else
6608db57 3877 sprintf (scratchbuf, "%%db%d", reg + add);
252b5132
RH		 3878 oappend (scratchbuf);
3879}
3880
252b5132 3881static void
26ca5450 3882OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 3883{
252b5132 3884 sprintf (scratchbuf, "%%tr%d", reg);
d708bcba 3885 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3886}
3887
3888static void
26ca5450 3889OP_Rd (int bytemode, int sizeflag)
252b5132 3890{
2da11e11
AM		 3891 if (mod == 3)
3892 OP_E (bytemode, sizeflag);
3893 else
6608db57 3894 BadOp ();
252b5132
RH		 3895}
3896
3897static void
26ca5450 3898OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132 3899{
041bd2e0
JH		 3900 int add = 0;
3901 USED_REX (REX_EXTX);
3902 if (rex & REX_EXTX)
3903 add = 8;
3904 used_prefixes |= (prefixes & PREFIX_DATA);
3905 if (prefixes & PREFIX_DATA)
3906 sprintf (scratchbuf, "%%xmm%d", reg + add);
3907 else
3908 sprintf (scratchbuf, "%%mm%d", reg + add);
d708bcba 3909 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3910}
3911
c608c12e 3912static void
26ca5450 3913OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e 3914{
041bd2e0
JH		 3915 int add = 0;
3916 USED_REX (REX_EXTX);
3917 if (rex & REX_EXTX)
3918 add = 8;
3919 sprintf (scratchbuf, "%%xmm%d", reg + add);
d708bcba 3920 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 3921}
3922
252b5132 3923static void
26ca5450 3924OP_EM (int bytemode, int sizeflag)
252b5132 3925{
041bd2e0 3926 int add = 0;
252b5132
RH		 3927 if (mod != 3)
3928 {
3929 OP_E (bytemode, sizeflag);
3930 return;
3931 }
041bd2e0
JH		 3932 USED_REX (REX_EXTZ);
3933 if (rex & REX_EXTZ)
3934 add = 8;
252b5132 3935
6608db57 3936 /* Skip mod/rm byte. */
4bba6815 3937 MODRM_CHECK;
252b5132 3938 codep++;
041bd2e0
JH		 3939 used_prefixes |= (prefixes & PREFIX_DATA);
3940 if (prefixes & PREFIX_DATA)
3941 sprintf (scratchbuf, "%%xmm%d", rm + add);
3942 else
3943 sprintf (scratchbuf, "%%mm%d", rm + add);
d708bcba 3944 oappend (scratchbuf + intel_syntax);
252b5132
RH		 3945}
3946
c608c12e 3947static void
26ca5450 3948OP_EX (int bytemode, int sizeflag)
c608c12e 3949{
041bd2e0 3950 int add = 0;
c608c12e
AM		 3951 if (mod != 3)
3952 {
3953 OP_E (bytemode, sizeflag);
3954 return;
3955 }
041bd2e0
JH		 3956 USED_REX (REX_EXTZ);
3957 if (rex & REX_EXTZ)
3958 add = 8;
c608c12e 3959
6608db57 3960 /* Skip mod/rm byte. */
4bba6815 3961 MODRM_CHECK;
c608c12e 3962 codep++;
041bd2e0 3963 sprintf (scratchbuf, "%%xmm%d", rm + add);
d708bcba 3964 oappend (scratchbuf + intel_syntax);
c608c12e
AM		 3965}
3966
252b5132 3967static void
26ca5450 3968OP_MS (int bytemode, int sizeflag)
252b5132 3969{
2da11e11
AM		 3970 if (mod == 3)
3971 OP_EM (bytemode, sizeflag);
3972 else
6608db57 3973 BadOp ();
252b5132
RH		 3974}
3975
992aaec9 3976static void
26ca5450 3977OP_XS (int bytemode, int sizeflag)
992aaec9
AM		 3978{
3979 if (mod == 3)
3980 OP_EX (bytemode, sizeflag);
3981 else
6608db57 3982 BadOp ();
992aaec9
AM		 3983}
3984
84037f8c 3985static const char *const Suffix3DNow[] = {
252b5132
RH		 3986/* 00 */ NULL, NULL, NULL, NULL,
3987/* 04 */ NULL, NULL, NULL, NULL,
3988/* 08 */ NULL, NULL, NULL, NULL,
9e525108 3989/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
252b5132
RH		 3990/* 10 */ NULL, NULL, NULL, NULL,
3991/* 14 */ NULL, NULL, NULL, NULL,
3992/* 18 */ NULL, NULL, NULL, NULL,
9e525108 3993/* 1C */ "pf2iw", "pf2id", NULL, NULL,
252b5132
RH		 3994/* 20 */ NULL, NULL, NULL, NULL,
3995/* 24 */ NULL, NULL, NULL, NULL,
3996/* 28 */ NULL, NULL, NULL, NULL,
3997/* 2C */ NULL, NULL, NULL, NULL,
3998/* 30 */ NULL, NULL, NULL, NULL,
3999/* 34 */ NULL, NULL, NULL, NULL,
4000/* 38 */ NULL, NULL, NULL, NULL,
4001/* 3C */ NULL, NULL, NULL, NULL,
4002/* 40 */ NULL, NULL, NULL, NULL,
4003/* 44 */ NULL, NULL, NULL, NULL,
4004/* 48 */ NULL, NULL, NULL, NULL,
4005/* 4C */ NULL, NULL, NULL, NULL,
4006/* 50 */ NULL, NULL, NULL, NULL,
4007/* 54 */ NULL, NULL, NULL, NULL,
4008/* 58 */ NULL, NULL, NULL, NULL,
4009/* 5C */ NULL, NULL, NULL, NULL,
4010/* 60 */ NULL, NULL, NULL, NULL,
4011/* 64 */ NULL, NULL, NULL, NULL,
4012/* 68 */ NULL, NULL, NULL, NULL,
4013/* 6C */ NULL, NULL, NULL, NULL,
4014/* 70 */ NULL, NULL, NULL, NULL,
4015/* 74 */ NULL, NULL, NULL, NULL,
4016/* 78 */ NULL, NULL, NULL, NULL,
4017/* 7C */ NULL, NULL, NULL, NULL,
4018/* 80 */ NULL, NULL, NULL, NULL,
4019/* 84 */ NULL, NULL, NULL, NULL,
9e525108
AM		 4020/* 88 */ NULL, NULL, "pfnacc", NULL,
4021/* 8C */ NULL, NULL, "pfpnacc", NULL,
252b5132
RH		 4022/* 90 */ "pfcmpge", NULL, NULL, NULL,
4023/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
4024/* 98 */ NULL, NULL, "pfsub", NULL,
4025/* 9C */ NULL, NULL, "pfadd", NULL,
4026/* A0 */ "pfcmpgt", NULL, NULL, NULL,
4027/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
4028/* A8 */ NULL, NULL, "pfsubr", NULL,
4029/* AC */ NULL, NULL, "pfacc", NULL,
4030/* B0 */ "pfcmpeq", NULL, NULL, NULL,
4031/* B4 */ "pfmul", NULL, "pfrcpit2", "pfmulhrw",
9e525108 4032/* B8 */ NULL, NULL, NULL, "pswapd",
252b5132
RH		 4033/* BC */ NULL, NULL, NULL, "pavgusb",
4034/* C0 */ NULL, NULL, NULL, NULL,
4035/* C4 */ NULL, NULL, NULL, NULL,
4036/* C8 */ NULL, NULL, NULL, NULL,
4037/* CC */ NULL, NULL, NULL, NULL,
4038/* D0 */ NULL, NULL, NULL, NULL,
4039/* D4 */ NULL, NULL, NULL, NULL,
4040/* D8 */ NULL, NULL, NULL, NULL,
4041/* DC */ NULL, NULL, NULL, NULL,
4042/* E0 */ NULL, NULL, NULL, NULL,
4043/* E4 */ NULL, NULL, NULL, NULL,
4044/* E8 */ NULL, NULL, NULL, NULL,
4045/* EC */ NULL, NULL, NULL, NULL,
4046/* F0 */ NULL, NULL, NULL, NULL,
4047/* F4 */ NULL, NULL, NULL, NULL,
4048/* F8 */ NULL, NULL, NULL, NULL,
4049/* FC */ NULL, NULL, NULL, NULL,
4050};
4051
4052static void
26ca5450 4053OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
252b5132
RH		 4054{
4055 const char *mnemonic;
4056
4057 FETCH_DATA (the_info, codep + 1);
4058 /* AMD 3DNow! instructions are specified by an opcode suffix in the
4059 place where an 8-bit immediate would normally go. ie. the last
4060 byte of the instruction. */
6608db57 4061 obufp = obuf + strlen (obuf);
c608c12e 4062 mnemonic = Suffix3DNow[*codep++ & 0xff];
252b5132 4063 if (mnemonic)
2da11e11 4064 oappend (mnemonic);
252b5132
RH		 4065 else
4066 {
4067 /* Since a variable sized modrm/sib chunk is between the start
4068 of the opcode (0x0f0f) and the opcode suffix, we need to do
4069 all the modrm processing first, and don't know until now that
4070 we have a bad opcode. This necessitates some cleaning up. */
2da11e11
AM		 4071 op1out[0] = '\0';
4072 op2out[0] = '\0';
6608db57 4073 BadOp ();
252b5132
RH		 4074 }
4075}
c608c12e 4076
6608db57 4077static const char *simd_cmp_op[] = {
c608c12e
AM		 4078 "eq",
4079 "lt",
4080 "le",
4081 "unord",
4082 "neq",
4083 "nlt",
4084 "nle",
4085 "ord"
4086};
4087
4088static void
26ca5450 4089OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 4090{
4091 unsigned int cmp_type;
4092
4093 FETCH_DATA (the_info, codep + 1);
6608db57 4094 obufp = obuf + strlen (obuf);
c608c12e
AM		 4095 cmp_type = *codep++ & 0xff;
4096 if (cmp_type < 8)
4097 {
041bd2e0
JH		 4098 char suffix1 = 'p', suffix2 = 's';
4099 used_prefixes |= (prefixes & PREFIX_REPZ);
4100 if (prefixes & PREFIX_REPZ)
4101 suffix1 = 's';
4102 else
4103 {
4104 used_prefixes |= (prefixes & PREFIX_DATA);
4105 if (prefixes & PREFIX_DATA)
4106 suffix2 = 'd';
4107 else
4108 {
4109 used_prefixes |= (prefixes & PREFIX_REPNZ);
4110 if (prefixes & PREFIX_REPNZ)
4111 suffix1 = 's', suffix2 = 'd';
4112 }
4113 }
4114 sprintf (scratchbuf, "cmp%s%c%c",
4115 simd_cmp_op[cmp_type], suffix1, suffix2);
7d421014 4116 used_prefixes |= (prefixes & PREFIX_REPZ);
2da11e11 4117 oappend (scratchbuf);
c608c12e
AM		 4118 }
4119 else
4120 {
4121 /* We have a bad extension byte. Clean up. */
2da11e11
AM		 4122 op1out[0] = '\0';
4123 op2out[0] = '\0';
6608db57 4124 BadOp ();
c608c12e
AM		 4125 }
4126}
4127
4128static void
26ca5450 4129SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
c608c12e
AM		 4130{
4131 /* Change movlps/movhps to movhlps/movlhps for 2 register operand
4132 forms of these instructions. */
4133 if (mod == 3)
4134 {
6608db57
KH		 4135 char *p = obuf + strlen (obuf);
4136 *(p + 1) = '\0';
4137 *p = *(p - 1);
4138 *(p - 1) = *(p - 2);
4139 *(p - 2) = *(p - 3);
4140 *(p - 3) = extrachar;
c608c12e
AM		 4141 }
4142}
2da11e11 4143
ca164297 4144static void
4fd61dcb 4145PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
ca164297
L		 4146{
4147 if (mod == 3 && reg == 1)
4148 {
4149 char *p = obuf + strlen (obuf);
4150
4151 /* Override "sidt". */
4152 if (rm)
4153 {
4154 /* mwait %eax,%ecx */
4155 strcpy (p - 4, "mwait %eax,%ecx");
4156 }
4157 else
4158 {
4159 /* monitor %eax,%ecx,%edx" */
4160 strcpy (p - 4, "monitor %eax,%ecx,%edx");
4161 }
4162
4163 codep++;
4164 }
4165 else
4166 OP_E (0, sizeflag);
4167}
4168
4fd61dcb
JJ		 4169static void
4170INVLPG_Fixup (int bytemode, int sizeflag)
4171{
4172 if (*codep == 0xf8)
4173 {
4174 char *p = obuf + strlen (obuf);
4175
4176 /* Override "invlpg". */
4177 strcpy (p - 6, "swapgs");
4178 codep++;
4179 }
4180 else
4181 OP_E (bytemode, sizeflag);
4182}
4183
6608db57
KH		 4184static void
4185BadOp (void)
2da11e11 4186{
6608db57
KH		 4187 /* Throw away prefixes and 1st. opcode byte. */
4188 codep = insn_codep + 1;
2da11e11
AM		 4189 oappend ("(bad)");
4190}
GDB Binutils - Deliverables
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