cpu/mep-rhcop.cpu

   1 ; Copyright 2011 Free Software Foundation, Inc.
   2 ;
   3 ; Contributed by Red Hat Inc;
   4 ;
   5 ; This file is part of the GNU Binutils.
   6 ;
   7 ; This program is free software; you can redistribute it and/or modify
   8 ; it under the terms of the GNU General Public License as published by
   9 ; the Free Software Foundation; either version 3 of the License, or
  10 ; (at your option) any later version.
  11 ;
  12 ; This program is distributed in the hope that it will be useful,
  13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ; GNU General Public License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with this program; if not, write to the Free Software
  19 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  20 ; MA 02110-1301, USA.
  21
  22 ;; This coprocessor definition is being used to verify vliw mode behaviour.
  23 ;; This is a mock-up done by Red Hat and is in no way supposed to represent
  24 ;; a real coprocessor.  The hardware is defined in mep-core.cpu.
  25
  26 ; Coprocessor registers
  27 (define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
  28
  29 (define-hardware
  30   (name h-cr64-rh-1)
  31   (comment "64-bit coprocessor registers for rh coprocessor for core 1")
  32   (attrs VIRTUAL rh-isa-1)
  33   (type register DI (32))
  34   (set (index newval) (c-call VOID "h_cr64_set" index newval))
  35   (get (index) (c-call DI "h_cr64_get" index))
  36   (indices keyword "$c" (.map -reg-pair (.iota 32)))
  37 )
  38
  39 (define-hardware
  40   (name h-cr-rh-1)
  41   (comment "32-bit coprocessor registers for rh coprocessor for core 1")
  42   (attrs VIRTUAL rh-isa-1)
  43   (type register SI (32))
  44   (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
  45   (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
  46   (indices keyword "$c" (.map -reg-pair (.iota 32)))
  47 )
  48
  49 (define-hardware
  50   (name h-ccr-rh-1)
  51   (comment "Coprocessor control registers for rh coprocessor for core 1")
  52   (attrs VIRTUAL rh-isa-1)
  53   (type register SI (64))
  54   (set (index newval) (c-call VOID "h_ccr_set" index newval))
  55   (get (index) (c-call DI "h_ccr_get" index))
  56   (indices keyword "" (.map -ccr-reg-pair (.iota 64)))
  57 )
  58
  59 ; ifields For 16-bit insns
  60 (dnf f-cphigh4 "High 4 bits"            ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))   0  4)
  61 (dnf f-cpcrn   "Copro Reg"              ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))   4  5)
  62 (dnf f-cpcrm   "Copro Reg"              ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))  11  5)
  63 (dnf f-uu2   "UU for 16-bit insns"      ((ISA ext_cop1_16))   9  2)
  64 (dnf f-uu3   "UU for 16-bit insns"      ((ISA ext_cop1_16))   9  3)
  65 (dnf f-cprm   "Core GPR"                ((ISA ext_cop1_16))  12  4)
  66
  67 ; ifields For 32-bit insns (some of the above are used too)
  68 ; Notes:
  69 ;
  70 ;  f-alone: A value of 0111 means that the insn can run alone in
  71 ;           one of the vliw modes.
  72 ;
  73 ;  f-seg32:   Together f-seg32 and f-seg32-a allow 64 different 32-bit
  74 ;  f-seg32-a: insns to be defined.
  75 (dnf f-seg32 "Enumerate 32 bit-insns"     ((ISA ext_cop1_32))   9  3)
  76 (dnf f-alone "Run-alone indicator"        ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64))  12  4)
  77 (dnf f-seg32-a "Enumerate 32 bit-insns"   ((ISA ext_cop1_32))  21  3)
  78 (dnf f-code8 "8 bit unsigned immediate"   ((ISA ext_cop1_32))  24 8)
  79 (dnf f-cpcrm-32 "Corpocessor Reg"         ((ISA ext_cop1_32))  16  5)
  80
  81 ; ifields for 48-bit insns
  82 ; Note: Part of f-uu12 can be broken off later to enumerate
  83 ;       any 48-bit insns that may be added.
  84 (dnf f-uu12 "Unusued 12 bits"            ((ISA ext_cop1_48))   4 12)
  85 (dnf f-code16a "Unsigned immediate"      ((ISA ext_cop1_48))  16 16)
  86 (dnf f-code16b "Unsigned immediate"      ((ISA ext_cop1_48,ext_cop1_64))  32 16)
  87
  88 ; ifields for 64-bit insns
  89 (dnf f-uu8 "Unsused 8 bits"               ((ISA ext_cop1_64))   4  8)
  90 (dnf f-uu8a "Unused 13 bits"              ((ISA ext_cop1_64))  16  8)
  91 (dnf f-seg64 "Enumerate 64-bit insns"     ((ISA ext_cop1_64))  24  8)
  92 (dnf f-code16c "Unsigned immediate"       ((ISA ext_cop1_64))  48 16)
  93 (dnf f-cpcrn-64 "Coprocessor Register"    ((ISA ext_cop1_64))  32  5)
  94 (dnf f-cpcrm-64 "Coprocessor Register"    ((ISA ext_cop1_64))  37  4)
  95 (dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64))  41 23)
  96 (dnf f-cpccrn-64 "Coprocessor Register"   ((ISA ext_cop1_64))  32  4)
  97 (dnf f-cpccrm-64 "Core GPR"               ((ISA ext_cop1_64))  36  4)
  98 (dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64))  40 24)
  99
 100 \f
 101 ; Operands for 16-bit insns
 102 (dnop cpcrn   "cpcrn"  ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn)
 103 (dnop cpcrm   "cpcrm"  ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm)
 104 (dnop cprm    "cprm"   ((ISA ext_cop1_16)) h-gpr f-cprm)
 105
 106 ; Additional operands for 32-bit insns
 107 (dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8)
 108
 109 ; Operands for 48-bit insns
 110 (dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a)
 111 (dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b)
 112
 113 ; Additional operands for 64-bit insns
 114 (dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c)
 115 (dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64)
 116 (dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64)
 117 (dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64)
 118 (dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64)
 119 (dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23)
 120 (dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24)
 121
 122
 123 \f
 124 ; 16- and 32-bit nops can be defined as normal instructions without
 125 ; any problems.  nops take no operands, so nops longer than 32
 126 ; bits cannot be defined as normal insns since that would result in
 127 ; decodable bits beyond cgen's 32-bit boundary.  As a result, we
 128 ; have to use macros and other real insns to create 48- and 64-bit nops.
 129 ;
 130 ; In addition, since the names of the nops that will be created as part
 131 ; of future insn sets are not known at this time, the assembler needs a
 132 ; fixed set of nop names that it can use for automatic nop insertion.
 133 ; The idea is that no matter what those insns are called, we don't want
 134 ; to have to change the C code in the assemblers vliw grouping validation
 135 ; and nop insertion routines.  We therefore have to create macros for
 136 ; all nops to map the macro names which are known to the assembler to the
 137 ; names of the real nop insns.
 138 ;
 139 ; These emitted insns in these macros will need to be modified when
 140 ; new nops are defined in new coprocessor insn sets.
 141
 142 ; A real 16-bit nop insn exists
 143 (dnmi cpnop16 "cpnop16"
 144       ((ISA ext_cop1_16))
 145       "cpnop16"
 146       (emit cp16nop)
 147 )
 148
 149 ; A real 32-bit nop insn exists
 150 (dnmi cpnop32 "cpnop32"
 151       ((ISA ext_cop1_32))
 152       "cpnop32"
 153       (emit cp32nop)
 154 )
 155
 156 ; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop.
 157 (dnmi cpnop48 "cpnop48"
 158       ((ISA ext_cop1_48))
 159       "cpnop48"
 160       (emit cpf1nop (code16a 0) (code16b 0))
 161 )
 162
 163 ; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop.
 164 (dnmi cpnop64 "cpnop64"
 165       ((ISA ext_cop1_64))
 166       "cpnop64"
 167       (emit cpf3nop (code16b 0) (code16c 0))
 168 )
 169
 170 \f
 171 (define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16))
 172 (define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32))
 173 (define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48))
 174 (define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64))
 175
 176 ; 16-Bit Insns
 177 (dncp116i movcp16 "16-bit coprocessor move insn"
 178         (VLIW64_NO_MATCHING_NOP)
 179         "movcp16 $cpcrn,$cpcrm"
 180         (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm)
 181         (set cpcrn cpcrm)
 182         ()
 183 )
 184
 185 (dncp116i movcp16a "16-bit coprocessor move insn"
 186         (VLIW64_NO_MATCHING_NOP)
 187         "movcp16a $cpcrn,$cprm"
 188         (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm)
 189         (set cpcrn (zext DI cprm))
 190         ()
 191 )
 192
 193 (dncp116i movcp16b "16-bit coprocessor move insn"
 194         (VLIW64_NO_MATCHING_NOP)
 195         "movcp16b $cprm,$cpcrn"
 196         (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm)
 197         (set cprm (subword SI cpcrn 1))
 198         ()
 199 )
 200
 201 (dncp116i cp16nop "16-bit coprocessor nop"
 202         (VLIW64_NO_MATCHING_NOP)
 203         "cp16nop"
 204         (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0))
 205         (unimp "cp16nop")
 206         ()
 207 )
 208
 209 ; 32-Bit Insns
 210 (dncp132i cp32nop "32-bit coprocessor nop"
 211         (VLIW64_NO_MATCHING_NOP)
 212         "cp32nop"
 213         (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
 214            (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0))
 215         (unimp "cpnop32")
 216         ()
 217 )
 218
 219 (dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests "
 220         (VLIW64_NO_MATCHING_NOP)
 221         "cpf2 $code8"
 222         (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
 223            (f-cpcrm-32 0) (f-seg32-a 1) code8)
 224         (unimp "cpf2")
 225         ()
 226 )
 227
 228 ; 48-Bit Insns
 229 (dncp148i cpf1 "48-bit coprocessor helper insn"
 230         ()
 231         "cpf1 $code16a,$code16b"
 232         (+ (f-cphigh4 4) (f-uu12 0) code16a code16b)
 233         (sequence ((HI result))
 234            (if (eq code16a 0)
 235                (set pc (c-call USI "cop_exception" pc))
 236                ; Set branch condition flags to value of code16a[0:3]
 237                ; Branch condition flags do not exist yet.
 238                (nop)
 239            )
 240         )
 241         ()
 242 )
 243
 244 (dncp148i cpf1nop "48-bit coprocessor nop insn"
 245         ()
 246         "cpf1nop $code16a,$code16b"
 247         (+ (f-cphigh4 5) (f-uu12 0) code16a code16b)
 248         (sequence ((HI result))
 249            (set result (add code16a code16b))
 250         )
 251         ()
 252 )
 253
 254 ; 64-Bit Insns
 255 (dncp164i cpf3 "64-bit coprocessor helper insn"
 256         ()
 257         "cpf3 $code16b,$code16c"
 258         (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 259            (f-seg64 0) code16b code16c)
 260         (sequence ((HI result))
 261            (set result (add code16b code16c))
 262         )
 263         ()
 264 )
 265
 266 (dncp164i cpf3nop "64-bit coprocessor helper insn"
 267         ()
 268         "cpf3nop $code16b,$code16c"
 269         (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 270            (f-seg64 7) code16b code16c)
 271         (sequence ((HI result))
 272            (set result (add code16b code16c))
 273         )
 274         ()
 275 )
 276
 277 (dncp164i cmov64a "64-bit cmov"
 278         ()
 279         "cmov64a $cpcrn64,$cpcrm64,$cpcode23"
 280         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 281            (f-seg64 1) cpcrn64 cpcrm64 cpcode23)
 282         (sequence ((SI dummy))
 283            (set dummy cpcode23)
 284            (set cpcrn64 (zext DI cpcrm64)))
 285         ()
 286 )
 287
 288 (dncp164i cmov64b "64-bit cmov"
 289         ()
 290         "cmov64b $cpcrm64,$cpcrn64,$cpcode23"
 291         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 292            (f-seg64 2) cpcrn64 cpcrm64 cpcode23)
 293         (sequence ((SI dummy))
 294           (set dummy cpcode23)
 295           (set cpcrm64 (subword SI cpcrn64 1)))
 296         ()
 297 )
 298
 299 (dncp164i cmovh64a "64-bit cmovh"
 300         ()
 301         "cmovh64a $cpcrn64,$cpcrm64,$cpcode23"
 302         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 303            (f-seg64 3) cpcrn64 cpcrm64 cpcode23)
 304         (sequence ((SI dummy))
 305            (set dummy cpcode23)
 306            (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1)))))
 307         ()
 308 )
 309
 310 (dncp164i cmovh64b "64-bit cmovh"
 311         ()
 312         "cmovh64b $cpcrm64,$cpcrn64,$cpcode23"
 313         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 314            (f-seg64 4) cpcrn64 cpcrm64 cpcode23)
 315         (sequence ((SI dummy))
 316            (set dummy cpcode23)
 317            (set cpcrm64 (subword SI cpcrn64 0)))
 318         ()
 319 )
 320
 321 (dncp164i cmovc64a "64-bit cmovc"
 322         ()
 323         "cmovc64a $cpccrn64,$cpccrm64,$cpcode24"
 324         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 325            (f-seg64 5) cpccrn64 cpccrm64 cpcode24)
 326         (sequence ((SI dummy))
 327            (set dummy cpcode24)
 328            (set cpccrn64 cpccrm64))
 329         ()
 330 )
 331
 332 (dncp164i cmovc64b "64-bit cmovc"
 333         ()
 334         "cmovc64b $cpccrm64,$cpccrn64,$cpcode24"
 335         (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
 336            (f-seg64 6) cpccrn64 cpccrm64 cpcode24)
 337         (sequence ((SI dummy))
 338            (set dummy cpcode24)
 339            (set cpccrm64 cpccrn64))
 340         ()
 341 )
 342