1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template
*match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry
*build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS
*, offsetT
);
199 static void output_disp (fragS
*, offsetT
);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used
;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used
;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
214 static const char *default_arch
= DEFAULT_ARCH
;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op
;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry
*mask
;
238 unsigned int zeroing
;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op
;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op
;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes
[4];
267 /* Destination or source register specifier. */
268 const reg_entry
*register_specifier
;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry
*regs
;
283 operand_size_mismatch
,
284 operand_type_mismatch
,
285 register_type_mismatch
,
286 number_of_operands_mismatch
,
287 invalid_instruction_suffix
,
289 unsupported_with_intel_mnemonic
,
292 invalid_vsib_address
,
293 invalid_vector_register_set
,
294 unsupported_vector_index_register
,
295 unsupported_broadcast
,
298 mask_not_on_destination
,
301 rc_sae_operand_not_last_imm
,
302 invalid_register_operand
,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands
;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types
[MAX_OPERANDS
];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op
[MAX_OPERANDS
];
330 /* Flags for operands. */
331 unsigned int flags
[MAX_OPERANDS
];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry
*base_reg
;
341 const reg_entry
*index_reg
;
342 unsigned int log2_scale_factor
;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry
*seg
[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes
;
354 unsigned char prefix
[MAX_PREFIXES
];
356 /* The operand to a branch insn indicates an absolute branch. */
357 bfd_boolean jumpabsolute
;
359 /* Has MMX register operands. */
360 bfd_boolean has_regmmx
;
362 /* Has XMM register operands. */
363 bfd_boolean has_regxmm
;
365 /* Has YMM register operands. */
366 bfd_boolean has_regymm
;
368 /* Has ZMM register operands. */
369 bfd_boolean has_regzmm
;
371 /* Has GOTPC or TLS relocation. */
372 bfd_boolean has_gotpc_tls_reloc
;
374 /* RM and SIB are the modrm byte and the sib byte where the
375 addressing modes of this insn are encoded. */
382 /* Masking attributes. */
383 struct Mask_Operation
*mask
;
385 /* Rounding control and SAE attributes. */
386 struct RC_Operation
*rounding
;
388 /* Broadcasting attributes. */
389 struct Broadcast_Operation
*broadcast
;
391 /* Compressed disp8*N attribute. */
392 unsigned int memshift
;
394 /* Prefer load or store in encoding. */
397 dir_encoding_default
= 0,
403 /* Prefer 8bit or 32bit displacement in encoding. */
406 disp_encoding_default
= 0,
411 /* Prefer the REX byte in encoding. */
412 bfd_boolean rex_encoding
;
414 /* Disable instruction size optimization. */
415 bfd_boolean no_optimize
;
417 /* How to encode vector instructions. */
420 vex_encoding_default
= 0,
427 const char *rep_prefix
;
430 const char *hle_prefix
;
432 /* Have BND prefix. */
433 const char *bnd_prefix
;
435 /* Have NOTRACK prefix. */
436 const char *notrack_prefix
;
439 enum i386_error error
;
442 typedef struct _i386_insn i386_insn
;
444 /* Link RC type with corresponding string, that'll be looked for in
453 static const struct RC_name RC_NamesTable
[] =
455 { rne
, STRING_COMMA_LEN ("rn-sae") },
456 { rd
, STRING_COMMA_LEN ("rd-sae") },
457 { ru
, STRING_COMMA_LEN ("ru-sae") },
458 { rz
, STRING_COMMA_LEN ("rz-sae") },
459 { saeonly
, STRING_COMMA_LEN ("sae") },
462 /* List of chars besides those in app.c:symbol_chars that can start an
463 operand. Used to prevent the scrubber eating vital white-space. */
464 const char extra_symbol_chars
[] = "*%-([{}"
473 #if (defined (TE_I386AIX) \
474 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
475 && !defined (TE_GNU) \
476 && !defined (TE_LINUX) \
477 && !defined (TE_NACL) \
478 && !defined (TE_FreeBSD) \
479 && !defined (TE_DragonFly) \
480 && !defined (TE_NetBSD)))
481 /* This array holds the chars that always start a comment. If the
482 pre-processor is disabled, these aren't very useful. The option
483 --divide will remove '/' from this list. */
484 const char *i386_comment_chars
= "#/";
485 #define SVR4_COMMENT_CHARS 1
486 #define PREFIX_SEPARATOR '\\'
489 const char *i386_comment_chars
= "#";
490 #define PREFIX_SEPARATOR '/'
493 /* This array holds the chars that only start a comment at the beginning of
494 a line. If the line seems to have the form '# 123 filename'
495 .line and .file directives will appear in the pre-processed output.
496 Note that input_file.c hand checks for '#' at the beginning of the
497 first line of the input file. This is because the compiler outputs
498 #NO_APP at the beginning of its output.
499 Also note that comments started like this one will always work if
500 '/' isn't otherwise defined. */
501 const char line_comment_chars
[] = "#/";
503 const char line_separator_chars
[] = ";";
505 /* Chars that can be used to separate mant from exp in floating point
507 const char EXP_CHARS
[] = "eE";
509 /* Chars that mean this number is a floating point constant
512 const char FLT_CHARS
[] = "fFdDxX";
514 /* Tables for lexical analysis. */
515 static char mnemonic_chars
[256];
516 static char register_chars
[256];
517 static char operand_chars
[256];
518 static char identifier_chars
[256];
519 static char digit_chars
[256];
521 /* Lexical macros. */
522 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
523 #define is_operand_char(x) (operand_chars[(unsigned char) x])
524 #define is_register_char(x) (register_chars[(unsigned char) x])
525 #define is_space_char(x) ((x) == ' ')
526 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
527 #define is_digit_char(x) (digit_chars[(unsigned char) x])
529 /* All non-digit non-letter characters that may occur in an operand. */
530 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
532 /* md_assemble() always leaves the strings it's passed unaltered. To
533 effect this we maintain a stack of saved characters that we've smashed
534 with '\0's (indicating end of strings for various sub-fields of the
535 assembler instruction). */
536 static char save_stack
[32];
537 static char *save_stack_p
;
538 #define END_STRING_AND_SAVE(s) \
539 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
540 #define RESTORE_END_STRING(s) \
541 do { *(s) = *--save_stack_p; } while (0)
543 /* The instruction we're assembling. */
546 /* Possible templates for current insn. */
547 static const templates
*current_templates
;
549 /* Per instruction expressionS buffers: max displacements & immediates. */
550 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
551 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
553 /* Current operand we are working on. */
554 static int this_operand
= -1;
556 /* We support four different modes. FLAG_CODE variable is used to distinguish
564 static enum flag_code flag_code
;
565 static unsigned int object_64bit
;
566 static unsigned int disallow_64bit_reloc
;
567 static int use_rela_relocations
= 0;
568 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
569 static const char *tls_get_addr
;
571 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
572 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
573 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
575 /* The ELF ABI to use. */
583 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
586 #if defined (TE_PE) || defined (TE_PEP)
587 /* Use big object file format. */
588 static int use_big_obj
= 0;
591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
592 /* 1 if generating code for a shared library. */
593 static int shared
= 0;
596 /* 1 for intel syntax,
598 static int intel_syntax
= 0;
600 /* 1 for Intel64 ISA,
604 /* 1 for intel mnemonic,
605 0 if att mnemonic. */
606 static int intel_mnemonic
= !SYSV386_COMPAT
;
608 /* 1 if pseudo registers are permitted. */
609 static int allow_pseudo_reg
= 0;
611 /* 1 if register prefix % not required. */
612 static int allow_naked_reg
= 0;
614 /* 1 if the assembler should add BND prefix for all control-transferring
615 instructions supporting it, even if this prefix wasn't specified
617 static int add_bnd_prefix
= 0;
619 /* 1 if pseudo index register, eiz/riz, is allowed . */
620 static int allow_index_reg
= 0;
622 /* 1 if the assembler should ignore LOCK prefix, even if it was
623 specified explicitly. */
624 static int omit_lock_prefix
= 0;
626 /* 1 if the assembler should encode lfence, mfence, and sfence as
627 "lock addl $0, (%{re}sp)". */
628 static int avoid_fence
= 0;
630 /* Type of the previous instruction. */
645 /* 1 if the assembler should generate relax relocations. */
647 static int generate_relax_relocations
648 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
650 static enum check_kind
656 sse_check
, operand_check
= check_warning
;
658 /* Non-zero if branches should be aligned within power of 2 boundary. */
659 static int align_branch_power
= 0;
661 /* Types of branches to align. */
662 enum align_branch_kind
664 align_branch_none
= 0,
665 align_branch_jcc
= 1,
666 align_branch_fused
= 2,
667 align_branch_jmp
= 3,
668 align_branch_call
= 4,
669 align_branch_indirect
= 5,
673 /* Type bits of branches to align. */
674 enum align_branch_bit
676 align_branch_jcc_bit
= 1 << align_branch_jcc
,
677 align_branch_fused_bit
= 1 << align_branch_fused
,
678 align_branch_jmp_bit
= 1 << align_branch_jmp
,
679 align_branch_call_bit
= 1 << align_branch_call
,
680 align_branch_indirect_bit
= 1 << align_branch_indirect
,
681 align_branch_ret_bit
= 1 << align_branch_ret
684 static unsigned int align_branch
= (align_branch_jcc_bit
685 | align_branch_fused_bit
686 | align_branch_jmp_bit
);
688 /* The maximum padding size for fused jcc. CMP like instruction can
689 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
691 #define MAX_FUSED_JCC_PADDING_SIZE 20
693 /* The maximum number of prefixes added for an instruction. */
694 static unsigned int align_branch_prefix_size
= 5;
697 1. Clear the REX_W bit with register operand if possible.
698 2. Above plus use 128bit vector instruction to clear the full vector
701 static int optimize
= 0;
704 1. Clear the REX_W bit with register operand if possible.
705 2. Above plus use 128bit vector instruction to clear the full vector
707 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
710 static int optimize_for_space
= 0;
712 /* Register prefix used for error message. */
713 static const char *register_prefix
= "%";
715 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
716 leave, push, and pop instructions so that gcc has the same stack
717 frame as in 32 bit mode. */
718 static char stackop_size
= '\0';
720 /* Non-zero to optimize code alignment. */
721 int optimize_align_code
= 1;
723 /* Non-zero to quieten some warnings. */
724 static int quiet_warnings
= 0;
727 static const char *cpu_arch_name
= NULL
;
728 static char *cpu_sub_arch_name
= NULL
;
730 /* CPU feature flags. */
731 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
733 /* If we have selected a cpu we are generating instructions for. */
734 static int cpu_arch_tune_set
= 0;
736 /* Cpu we are generating instructions for. */
737 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
739 /* CPU feature flags of cpu we are generating instructions for. */
740 static i386_cpu_flags cpu_arch_tune_flags
;
742 /* CPU instruction set architecture used. */
743 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
745 /* CPU feature flags of instruction set architecture used. */
746 i386_cpu_flags cpu_arch_isa_flags
;
748 /* If set, conditional jumps are not automatically promoted to handle
749 larger than a byte offset. */
750 static unsigned int no_cond_jump_promotion
= 0;
752 /* Encode SSE instructions with VEX prefix. */
753 static unsigned int sse2avx
;
755 /* Encode scalar AVX instructions with specific vector length. */
762 /* Encode VEX WIG instructions with specific vex.w. */
769 /* Encode scalar EVEX LIG instructions with specific vector length. */
777 /* Encode EVEX WIG instructions with specific evex.w. */
784 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
785 static enum rc_type evexrcig
= rne
;
787 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
788 static symbolS
*GOT_symbol
;
790 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
791 unsigned int x86_dwarf2_return_column
;
793 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
794 int x86_cie_data_alignment
;
796 /* Interface to relax_segment.
797 There are 3 major relax states for 386 jump insns because the
798 different types of jumps add different sizes to frags when we're
799 figuring out what sort of jump to choose to reach a given label.
801 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
802 branches which are handled by md_estimate_size_before_relax() and
803 i386_generic_table_relax_frag(). */
806 #define UNCOND_JUMP 0
808 #define COND_JUMP86 2
809 #define BRANCH_PADDING 3
810 #define BRANCH_PREFIX 4
811 #define FUSED_JCC_PADDING 5
816 #define SMALL16 (SMALL | CODE16)
818 #define BIG16 (BIG | CODE16)
822 #define INLINE __inline__
828 #define ENCODE_RELAX_STATE(type, size) \
829 ((relax_substateT) (((type) << 2) | (size)))
830 #define TYPE_FROM_RELAX_STATE(s) \
832 #define DISP_SIZE_FROM_RELAX_STATE(s) \
833 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
835 /* This table is used by relax_frag to promote short jumps to long
836 ones where necessary. SMALL (short) jumps may be promoted to BIG
837 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
838 don't allow a short jump in a 32 bit code segment to be promoted to
839 a 16 bit offset jump because it's slower (requires data size
840 prefix), and doesn't work, unless the destination is in the bottom
841 64k of the code segment (The top 16 bits of eip are zeroed). */
843 const relax_typeS md_relax_table
[] =
846 1) most positive reach of this state,
847 2) most negative reach of this state,
848 3) how many bytes this mode will have in the variable part of the frag
849 4) which index into the table to try if we can't fit into this one. */
851 /* UNCOND_JUMP states. */
852 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
853 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
854 /* dword jmp adds 4 bytes to frag:
855 0 extra opcode bytes, 4 displacement bytes. */
857 /* word jmp adds 2 byte2 to frag:
858 0 extra opcode bytes, 2 displacement bytes. */
861 /* COND_JUMP states. */
862 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
863 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
864 /* dword conditionals adds 5 bytes to frag:
865 1 extra opcode byte, 4 displacement bytes. */
867 /* word conditionals add 3 bytes to frag:
868 1 extra opcode byte, 2 displacement bytes. */
871 /* COND_JUMP86 states. */
872 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
873 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
874 /* dword conditionals adds 5 bytes to frag:
875 1 extra opcode byte, 4 displacement bytes. */
877 /* word conditionals add 4 bytes to frag:
878 1 displacement byte and a 3 byte long branch insn. */
882 static const arch_entry cpu_arch
[] =
884 /* Do not replace the first two entries - i386_target_format()
885 relies on them being there in this order. */
886 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
887 CPU_GENERIC32_FLAGS
, 0 },
888 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
889 CPU_GENERIC64_FLAGS
, 0 },
890 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
898 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
900 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
902 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
904 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
906 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
907 CPU_PENTIUMPRO_FLAGS
, 0 },
908 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
910 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
912 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
914 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
916 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
917 CPU_NOCONA_FLAGS
, 0 },
918 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
920 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
922 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
923 CPU_CORE2_FLAGS
, 1 },
924 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
925 CPU_CORE2_FLAGS
, 0 },
926 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
927 CPU_COREI7_FLAGS
, 0 },
928 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
930 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
932 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
933 CPU_IAMCU_FLAGS
, 0 },
934 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
936 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
938 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
939 CPU_ATHLON_FLAGS
, 0 },
940 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
942 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
944 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
946 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
947 CPU_AMDFAM10_FLAGS
, 0 },
948 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
949 CPU_BDVER1_FLAGS
, 0 },
950 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
951 CPU_BDVER2_FLAGS
, 0 },
952 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
953 CPU_BDVER3_FLAGS
, 0 },
954 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
955 CPU_BDVER4_FLAGS
, 0 },
956 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
957 CPU_ZNVER1_FLAGS
, 0 },
958 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
959 CPU_ZNVER2_FLAGS
, 0 },
960 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
961 CPU_BTVER1_FLAGS
, 0 },
962 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
963 CPU_BTVER2_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
966 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
968 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
970 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
972 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
974 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
976 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
978 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
980 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
982 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
984 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
985 CPU_SSSE3_FLAGS
, 0 },
986 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
987 CPU_SSE4_1_FLAGS
, 0 },
988 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
989 CPU_SSE4_2_FLAGS
, 0 },
990 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
991 CPU_SSE4_2_FLAGS
, 0 },
992 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
994 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
996 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
997 CPU_AVX512F_FLAGS
, 0 },
998 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
999 CPU_AVX512CD_FLAGS
, 0 },
1000 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1001 CPU_AVX512ER_FLAGS
, 0 },
1002 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1003 CPU_AVX512PF_FLAGS
, 0 },
1004 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1005 CPU_AVX512DQ_FLAGS
, 0 },
1006 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1007 CPU_AVX512BW_FLAGS
, 0 },
1008 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1009 CPU_AVX512VL_FLAGS
, 0 },
1010 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1012 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1013 CPU_VMFUNC_FLAGS
, 0 },
1014 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1016 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1017 CPU_XSAVE_FLAGS
, 0 },
1018 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1019 CPU_XSAVEOPT_FLAGS
, 0 },
1020 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1021 CPU_XSAVEC_FLAGS
, 0 },
1022 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1023 CPU_XSAVES_FLAGS
, 0 },
1024 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1026 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1027 CPU_PCLMUL_FLAGS
, 0 },
1028 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1029 CPU_PCLMUL_FLAGS
, 1 },
1030 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1031 CPU_FSGSBASE_FLAGS
, 0 },
1032 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1033 CPU_RDRND_FLAGS
, 0 },
1034 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1035 CPU_F16C_FLAGS
, 0 },
1036 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1037 CPU_BMI2_FLAGS
, 0 },
1038 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1040 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1041 CPU_FMA4_FLAGS
, 0 },
1042 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1044 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1046 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1047 CPU_MOVBE_FLAGS
, 0 },
1048 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1049 CPU_CX16_FLAGS
, 0 },
1050 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1052 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1053 CPU_LZCNT_FLAGS
, 0 },
1054 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1056 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1058 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1059 CPU_INVPCID_FLAGS
, 0 },
1060 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1061 CPU_CLFLUSH_FLAGS
, 0 },
1062 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1064 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1065 CPU_SYSCALL_FLAGS
, 0 },
1066 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1067 CPU_RDTSCP_FLAGS
, 0 },
1068 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1069 CPU_3DNOW_FLAGS
, 0 },
1070 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1071 CPU_3DNOWA_FLAGS
, 0 },
1072 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1073 CPU_PADLOCK_FLAGS
, 0 },
1074 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1075 CPU_SVME_FLAGS
, 1 },
1076 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1077 CPU_SVME_FLAGS
, 0 },
1078 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1079 CPU_SSE4A_FLAGS
, 0 },
1080 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1082 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1084 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1086 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1088 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1089 CPU_RDSEED_FLAGS
, 0 },
1090 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1091 CPU_PRFCHW_FLAGS
, 0 },
1092 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1093 CPU_SMAP_FLAGS
, 0 },
1094 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1096 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1098 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1099 CPU_CLFLUSHOPT_FLAGS
, 0 },
1100 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1101 CPU_PREFETCHWT1_FLAGS
, 0 },
1102 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1104 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1105 CPU_CLWB_FLAGS
, 0 },
1106 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1107 CPU_AVX512IFMA_FLAGS
, 0 },
1108 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1109 CPU_AVX512VBMI_FLAGS
, 0 },
1110 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1111 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1112 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1113 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1114 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1115 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1116 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1117 CPU_AVX512_VBMI2_FLAGS
, 0 },
1118 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1119 CPU_AVX512_VNNI_FLAGS
, 0 },
1120 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1121 CPU_AVX512_BITALG_FLAGS
, 0 },
1122 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1123 CPU_CLZERO_FLAGS
, 0 },
1124 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1125 CPU_MWAITX_FLAGS
, 0 },
1126 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1127 CPU_OSPKE_FLAGS
, 0 },
1128 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1129 CPU_RDPID_FLAGS
, 0 },
1130 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1131 CPU_PTWRITE_FLAGS
, 0 },
1132 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1134 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1135 CPU_SHSTK_FLAGS
, 0 },
1136 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1137 CPU_GFNI_FLAGS
, 0 },
1138 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1139 CPU_VAES_FLAGS
, 0 },
1140 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1141 CPU_VPCLMULQDQ_FLAGS
, 0 },
1142 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1143 CPU_WBNOINVD_FLAGS
, 0 },
1144 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1145 CPU_PCONFIG_FLAGS
, 0 },
1146 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1147 CPU_WAITPKG_FLAGS
, 0 },
1148 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1149 CPU_CLDEMOTE_FLAGS
, 0 },
1150 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1151 CPU_MOVDIRI_FLAGS
, 0 },
1152 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1153 CPU_MOVDIR64B_FLAGS
, 0 },
1154 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1155 CPU_AVX512_BF16_FLAGS
, 0 },
1156 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1157 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1158 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1159 CPU_ENQCMD_FLAGS
, 0 },
1160 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1161 CPU_RDPRU_FLAGS
, 0 },
1162 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1163 CPU_MCOMMIT_FLAGS
, 0 },
1166 static const noarch_entry cpu_noarch
[] =
1168 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1169 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1170 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1171 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1172 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1173 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1174 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1175 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1176 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1178 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1179 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1180 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1182 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1183 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1199 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1200 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1201 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1202 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1203 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1205 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1209 /* Like s_lcomm_internal in gas/read.c but the alignment string
1210 is allowed to be optional. */
1213 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1220 && *input_line_pointer
== ',')
1222 align
= parse_align (needs_align
- 1);
1224 if (align
== (addressT
) -1)
1239 bss_alloc (symbolP
, size
, align
);
1244 pe_lcomm (int needs_align
)
1246 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1250 const pseudo_typeS md_pseudo_table
[] =
1252 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1253 {"align", s_align_bytes
, 0},
1255 {"align", s_align_ptwo
, 0},
1257 {"arch", set_cpu_arch
, 0},
1261 {"lcomm", pe_lcomm
, 1},
1263 {"ffloat", float_cons
, 'f'},
1264 {"dfloat", float_cons
, 'd'},
1265 {"tfloat", float_cons
, 'x'},
1267 {"slong", signed_cons
, 4},
1268 {"noopt", s_ignore
, 0},
1269 {"optim", s_ignore
, 0},
1270 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1271 {"code16", set_code_flag
, CODE_16BIT
},
1272 {"code32", set_code_flag
, CODE_32BIT
},
1274 {"code64", set_code_flag
, CODE_64BIT
},
1276 {"intel_syntax", set_intel_syntax
, 1},
1277 {"att_syntax", set_intel_syntax
, 0},
1278 {"intel_mnemonic", set_intel_mnemonic
, 1},
1279 {"att_mnemonic", set_intel_mnemonic
, 0},
1280 {"allow_index_reg", set_allow_index_reg
, 1},
1281 {"disallow_index_reg", set_allow_index_reg
, 0},
1282 {"sse_check", set_check
, 0},
1283 {"operand_check", set_check
, 1},
1284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1285 {"largecomm", handle_large_common
, 0},
1287 {"file", dwarf2_directive_file
, 0},
1288 {"loc", dwarf2_directive_loc
, 0},
1289 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1292 {"secrel32", pe_directive_secrel
, 0},
1297 /* For interface with expression (). */
1298 extern char *input_line_pointer
;
1300 /* Hash table for instruction mnemonic lookup. */
1301 static struct hash_control
*op_hash
;
1303 /* Hash table for register lookup. */
1304 static struct hash_control
*reg_hash
;
1306 /* Various efficient no-op patterns for aligning code labels.
1307 Note: Don't try to assemble the instructions in the comments.
1308 0L and 0w are not legal. */
1309 static const unsigned char f32_1
[] =
1311 static const unsigned char f32_2
[] =
1312 {0x66,0x90}; /* xchg %ax,%ax */
1313 static const unsigned char f32_3
[] =
1314 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1315 static const unsigned char f32_4
[] =
1316 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1317 static const unsigned char f32_6
[] =
1318 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1319 static const unsigned char f32_7
[] =
1320 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1321 static const unsigned char f16_3
[] =
1322 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1323 static const unsigned char f16_4
[] =
1324 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1325 static const unsigned char jump_disp8
[] =
1326 {0xeb}; /* jmp disp8 */
1327 static const unsigned char jump32_disp32
[] =
1328 {0xe9}; /* jmp disp32 */
1329 static const unsigned char jump16_disp32
[] =
1330 {0x66,0xe9}; /* jmp disp32 */
1331 /* 32-bit NOPs patterns. */
1332 static const unsigned char *const f32_patt
[] = {
1333 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1335 /* 16-bit NOPs patterns. */
1336 static const unsigned char *const f16_patt
[] = {
1337 f32_1
, f32_2
, f16_3
, f16_4
1339 /* nopl (%[re]ax) */
1340 static const unsigned char alt_3
[] =
1342 /* nopl 0(%[re]ax) */
1343 static const unsigned char alt_4
[] =
1344 {0x0f,0x1f,0x40,0x00};
1345 /* nopl 0(%[re]ax,%[re]ax,1) */
1346 static const unsigned char alt_5
[] =
1347 {0x0f,0x1f,0x44,0x00,0x00};
1348 /* nopw 0(%[re]ax,%[re]ax,1) */
1349 static const unsigned char alt_6
[] =
1350 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1351 /* nopl 0L(%[re]ax) */
1352 static const unsigned char alt_7
[] =
1353 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1354 /* nopl 0L(%[re]ax,%[re]ax,1) */
1355 static const unsigned char alt_8
[] =
1356 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1357 /* nopw 0L(%[re]ax,%[re]ax,1) */
1358 static const unsigned char alt_9
[] =
1359 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1360 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1361 static const unsigned char alt_10
[] =
1362 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1363 /* data16 nopw %cs:0L(%eax,%eax,1) */
1364 static const unsigned char alt_11
[] =
1365 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1366 /* 32-bit and 64-bit NOPs patterns. */
1367 static const unsigned char *const alt_patt
[] = {
1368 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1369 alt_9
, alt_10
, alt_11
1372 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1373 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1376 i386_output_nops (char *where
, const unsigned char *const *patt
,
1377 int count
, int max_single_nop_size
)
1380 /* Place the longer NOP first. */
1383 const unsigned char *nops
;
1385 if (max_single_nop_size
< 1)
1387 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1388 max_single_nop_size
);
1392 nops
= patt
[max_single_nop_size
- 1];
1394 /* Use the smaller one if the requsted one isn't available. */
1397 max_single_nop_size
--;
1398 nops
= patt
[max_single_nop_size
- 1];
1401 last
= count
% max_single_nop_size
;
1404 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1405 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1409 nops
= patt
[last
- 1];
1412 /* Use the smaller one plus one-byte NOP if the needed one
1415 nops
= patt
[last
- 1];
1416 memcpy (where
+ offset
, nops
, last
);
1417 where
[offset
+ last
] = *patt
[0];
1420 memcpy (where
+ offset
, nops
, last
);
1425 fits_in_imm7 (offsetT num
)
1427 return (num
& 0x7f) == num
;
1431 fits_in_imm31 (offsetT num
)
1433 return (num
& 0x7fffffff) == num
;
1436 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1437 single NOP instruction LIMIT. */
1440 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1442 const unsigned char *const *patt
= NULL
;
1443 int max_single_nop_size
;
1444 /* Maximum number of NOPs before switching to jump over NOPs. */
1445 int max_number_of_nops
;
1447 switch (fragP
->fr_type
)
1452 case rs_machine_dependent
:
1453 /* Allow NOP padding for jumps and calls. */
1454 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1455 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1462 /* We need to decide which NOP sequence to use for 32bit and
1463 64bit. When -mtune= is used:
1465 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1466 PROCESSOR_GENERIC32, f32_patt will be used.
1467 2. For the rest, alt_patt will be used.
1469 When -mtune= isn't used, alt_patt will be used if
1470 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1473 When -march= or .arch is used, we can't use anything beyond
1474 cpu_arch_isa_flags. */
1476 if (flag_code
== CODE_16BIT
)
1479 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1480 /* Limit number of NOPs to 2 in 16-bit mode. */
1481 max_number_of_nops
= 2;
1485 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1487 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1488 switch (cpu_arch_tune
)
1490 case PROCESSOR_UNKNOWN
:
1491 /* We use cpu_arch_isa_flags to check if we SHOULD
1492 optimize with nops. */
1493 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1498 case PROCESSOR_PENTIUM4
:
1499 case PROCESSOR_NOCONA
:
1500 case PROCESSOR_CORE
:
1501 case PROCESSOR_CORE2
:
1502 case PROCESSOR_COREI7
:
1503 case PROCESSOR_L1OM
:
1504 case PROCESSOR_K1OM
:
1505 case PROCESSOR_GENERIC64
:
1507 case PROCESSOR_ATHLON
:
1509 case PROCESSOR_AMDFAM10
:
1511 case PROCESSOR_ZNVER
:
1515 case PROCESSOR_I386
:
1516 case PROCESSOR_I486
:
1517 case PROCESSOR_PENTIUM
:
1518 case PROCESSOR_PENTIUMPRO
:
1519 case PROCESSOR_IAMCU
:
1520 case PROCESSOR_GENERIC32
:
1527 switch (fragP
->tc_frag_data
.tune
)
1529 case PROCESSOR_UNKNOWN
:
1530 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1531 PROCESSOR_UNKNOWN. */
1535 case PROCESSOR_I386
:
1536 case PROCESSOR_I486
:
1537 case PROCESSOR_PENTIUM
:
1538 case PROCESSOR_IAMCU
:
1540 case PROCESSOR_ATHLON
:
1542 case PROCESSOR_AMDFAM10
:
1544 case PROCESSOR_ZNVER
:
1546 case PROCESSOR_GENERIC32
:
1547 /* We use cpu_arch_isa_flags to check if we CAN optimize
1549 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1554 case PROCESSOR_PENTIUMPRO
:
1555 case PROCESSOR_PENTIUM4
:
1556 case PROCESSOR_NOCONA
:
1557 case PROCESSOR_CORE
:
1558 case PROCESSOR_CORE2
:
1559 case PROCESSOR_COREI7
:
1560 case PROCESSOR_L1OM
:
1561 case PROCESSOR_K1OM
:
1562 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1567 case PROCESSOR_GENERIC64
:
1573 if (patt
== f32_patt
)
1575 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1576 /* Limit number of NOPs to 2 for older processors. */
1577 max_number_of_nops
= 2;
1581 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1582 /* Limit number of NOPs to 7 for newer processors. */
1583 max_number_of_nops
= 7;
1588 limit
= max_single_nop_size
;
1590 if (fragP
->fr_type
== rs_fill_nop
)
1592 /* Output NOPs for .nop directive. */
1593 if (limit
> max_single_nop_size
)
1595 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1596 _("invalid single nop size: %d "
1597 "(expect within [0, %d])"),
1598 limit
, max_single_nop_size
);
1602 else if (fragP
->fr_type
!= rs_machine_dependent
)
1603 fragP
->fr_var
= count
;
1605 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1607 /* Generate jump over NOPs. */
1608 offsetT disp
= count
- 2;
1609 if (fits_in_imm7 (disp
))
1611 /* Use "jmp disp8" if possible. */
1613 where
[0] = jump_disp8
[0];
1619 unsigned int size_of_jump
;
1621 if (flag_code
== CODE_16BIT
)
1623 where
[0] = jump16_disp32
[0];
1624 where
[1] = jump16_disp32
[1];
1629 where
[0] = jump32_disp32
[0];
1633 count
-= size_of_jump
+ 4;
1634 if (!fits_in_imm31 (count
))
1636 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1637 _("jump over nop padding out of range"));
1641 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1642 where
+= size_of_jump
+ 4;
1646 /* Generate multiple NOPs. */
1647 i386_output_nops (where
, patt
, count
, limit
);
1651 operand_type_all_zero (const union i386_operand_type
*x
)
1653 switch (ARRAY_SIZE(x
->array
))
1664 return !x
->array
[0];
1671 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1673 switch (ARRAY_SIZE(x
->array
))
1689 x
->bitfield
.class = ClassNone
;
1690 x
->bitfield
.instance
= InstanceNone
;
1694 operand_type_equal (const union i386_operand_type
*x
,
1695 const union i386_operand_type
*y
)
1697 switch (ARRAY_SIZE(x
->array
))
1700 if (x
->array
[2] != y
->array
[2])
1704 if (x
->array
[1] != y
->array
[1])
1708 return x
->array
[0] == y
->array
[0];
1716 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1718 switch (ARRAY_SIZE(x
->array
))
1733 return !x
->array
[0];
1740 cpu_flags_equal (const union i386_cpu_flags
*x
,
1741 const union i386_cpu_flags
*y
)
1743 switch (ARRAY_SIZE(x
->array
))
1746 if (x
->array
[3] != y
->array
[3])
1750 if (x
->array
[2] != y
->array
[2])
1754 if (x
->array
[1] != y
->array
[1])
1758 return x
->array
[0] == y
->array
[0];
1766 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1768 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1769 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1772 static INLINE i386_cpu_flags
1773 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1775 switch (ARRAY_SIZE (x
.array
))
1778 x
.array
[3] &= y
.array
[3];
1781 x
.array
[2] &= y
.array
[2];
1784 x
.array
[1] &= y
.array
[1];
1787 x
.array
[0] &= y
.array
[0];
1795 static INLINE i386_cpu_flags
1796 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1798 switch (ARRAY_SIZE (x
.array
))
1801 x
.array
[3] |= y
.array
[3];
1804 x
.array
[2] |= y
.array
[2];
1807 x
.array
[1] |= y
.array
[1];
1810 x
.array
[0] |= y
.array
[0];
1818 static INLINE i386_cpu_flags
1819 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1821 switch (ARRAY_SIZE (x
.array
))
1824 x
.array
[3] &= ~y
.array
[3];
1827 x
.array
[2] &= ~y
.array
[2];
1830 x
.array
[1] &= ~y
.array
[1];
1833 x
.array
[0] &= ~y
.array
[0];
1841 #define CPU_FLAGS_ARCH_MATCH 0x1
1842 #define CPU_FLAGS_64BIT_MATCH 0x2
1844 #define CPU_FLAGS_PERFECT_MATCH \
1845 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1847 /* Return CPU flags match bits. */
1850 cpu_flags_match (const insn_template
*t
)
1852 i386_cpu_flags x
= t
->cpu_flags
;
1853 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1855 x
.bitfield
.cpu64
= 0;
1856 x
.bitfield
.cpuno64
= 0;
1858 if (cpu_flags_all_zero (&x
))
1860 /* This instruction is available on all archs. */
1861 match
|= CPU_FLAGS_ARCH_MATCH
;
1865 /* This instruction is available only on some archs. */
1866 i386_cpu_flags cpu
= cpu_arch_flags
;
1868 /* AVX512VL is no standalone feature - match it and then strip it. */
1869 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1871 x
.bitfield
.cpuavx512vl
= 0;
1873 cpu
= cpu_flags_and (x
, cpu
);
1874 if (!cpu_flags_all_zero (&cpu
))
1876 if (x
.bitfield
.cpuavx
)
1878 /* We need to check a few extra flags with AVX. */
1879 if (cpu
.bitfield
.cpuavx
1880 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1881 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1882 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1883 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1884 match
|= CPU_FLAGS_ARCH_MATCH
;
1886 else if (x
.bitfield
.cpuavx512f
)
1888 /* We need to check a few extra flags with AVX512F. */
1889 if (cpu
.bitfield
.cpuavx512f
1890 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1891 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1892 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1893 match
|= CPU_FLAGS_ARCH_MATCH
;
1896 match
|= CPU_FLAGS_ARCH_MATCH
;
1902 static INLINE i386_operand_type
1903 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1905 if (x
.bitfield
.class != y
.bitfield
.class)
1906 x
.bitfield
.class = ClassNone
;
1907 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1908 x
.bitfield
.instance
= InstanceNone
;
1910 switch (ARRAY_SIZE (x
.array
))
1913 x
.array
[2] &= y
.array
[2];
1916 x
.array
[1] &= y
.array
[1];
1919 x
.array
[0] &= y
.array
[0];
1927 static INLINE i386_operand_type
1928 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1930 gas_assert (y
.bitfield
.class == ClassNone
);
1931 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1933 switch (ARRAY_SIZE (x
.array
))
1936 x
.array
[2] &= ~y
.array
[2];
1939 x
.array
[1] &= ~y
.array
[1];
1942 x
.array
[0] &= ~y
.array
[0];
1950 static INLINE i386_operand_type
1951 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1953 gas_assert (x
.bitfield
.class == ClassNone
||
1954 y
.bitfield
.class == ClassNone
||
1955 x
.bitfield
.class == y
.bitfield
.class);
1956 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1957 y
.bitfield
.instance
== InstanceNone
||
1958 x
.bitfield
.instance
== y
.bitfield
.instance
);
1960 switch (ARRAY_SIZE (x
.array
))
1963 x
.array
[2] |= y
.array
[2];
1966 x
.array
[1] |= y
.array
[1];
1969 x
.array
[0] |= y
.array
[0];
1977 static INLINE i386_operand_type
1978 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1980 gas_assert (y
.bitfield
.class == ClassNone
);
1981 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1983 switch (ARRAY_SIZE (x
.array
))
1986 x
.array
[2] ^= y
.array
[2];
1989 x
.array
[1] ^= y
.array
[1];
1992 x
.array
[0] ^= y
.array
[0];
2000 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2001 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2002 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2003 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2004 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2005 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2006 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2007 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2008 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2009 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2010 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2011 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2012 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2013 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2014 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2015 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2016 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2027 operand_type_check (i386_operand_type t
, enum operand_type c
)
2032 return t
.bitfield
.class == Reg
;
2035 return (t
.bitfield
.imm8
2039 || t
.bitfield
.imm32s
2040 || t
.bitfield
.imm64
);
2043 return (t
.bitfield
.disp8
2044 || t
.bitfield
.disp16
2045 || t
.bitfield
.disp32
2046 || t
.bitfield
.disp32s
2047 || t
.bitfield
.disp64
);
2050 return (t
.bitfield
.disp8
2051 || t
.bitfield
.disp16
2052 || t
.bitfield
.disp32
2053 || t
.bitfield
.disp32s
2054 || t
.bitfield
.disp64
2055 || t
.bitfield
.baseindex
);
2064 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2065 between operand GIVEN and opeand WANTED for instruction template T. */
2068 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2071 return !((i
.types
[given
].bitfield
.byte
2072 && !t
->operand_types
[wanted
].bitfield
.byte
)
2073 || (i
.types
[given
].bitfield
.word
2074 && !t
->operand_types
[wanted
].bitfield
.word
)
2075 || (i
.types
[given
].bitfield
.dword
2076 && !t
->operand_types
[wanted
].bitfield
.dword
)
2077 || (i
.types
[given
].bitfield
.qword
2078 && !t
->operand_types
[wanted
].bitfield
.qword
)
2079 || (i
.types
[given
].bitfield
.tbyte
2080 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2083 /* Return 1 if there is no conflict in SIMD register between operand
2084 GIVEN and opeand WANTED for instruction template T. */
2087 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2090 return !((i
.types
[given
].bitfield
.xmmword
2091 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2092 || (i
.types
[given
].bitfield
.ymmword
2093 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2094 || (i
.types
[given
].bitfield
.zmmword
2095 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2098 /* Return 1 if there is no conflict in any size between operand GIVEN
2099 and opeand WANTED for instruction template T. */
2102 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2105 return (match_operand_size (t
, wanted
, given
)
2106 && !((i
.types
[given
].bitfield
.unspecified
2108 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2109 || (i
.types
[given
].bitfield
.fword
2110 && !t
->operand_types
[wanted
].bitfield
.fword
)
2111 /* For scalar opcode templates to allow register and memory
2112 operands at the same time, some special casing is needed
2113 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2114 down-conversion vpmov*. */
2115 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2116 && !t
->opcode_modifier
.broadcast
2117 && (t
->operand_types
[wanted
].bitfield
.byte
2118 || t
->operand_types
[wanted
].bitfield
.word
2119 || t
->operand_types
[wanted
].bitfield
.dword
2120 || t
->operand_types
[wanted
].bitfield
.qword
))
2121 ? (i
.types
[given
].bitfield
.xmmword
2122 || i
.types
[given
].bitfield
.ymmword
2123 || i
.types
[given
].bitfield
.zmmword
)
2124 : !match_simd_size(t
, wanted
, given
))));
2127 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2128 operands for instruction template T, and it has MATCH_REVERSE set if there
2129 is no size conflict on any operands for the template with operands reversed
2130 (and the template allows for reversing in the first place). */
2132 #define MATCH_STRAIGHT 1
2133 #define MATCH_REVERSE 2
2135 static INLINE
unsigned int
2136 operand_size_match (const insn_template
*t
)
2138 unsigned int j
, match
= MATCH_STRAIGHT
;
2140 /* Don't check non-absolute jump instructions. */
2141 if (t
->opcode_modifier
.jump
2142 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2145 /* Check memory and accumulator operand size. */
2146 for (j
= 0; j
< i
.operands
; j
++)
2148 if (i
.types
[j
].bitfield
.class != Reg
2149 && i
.types
[j
].bitfield
.class != RegSIMD
2150 && t
->opcode_modifier
.anysize
)
2153 if (t
->operand_types
[j
].bitfield
.class == Reg
2154 && !match_operand_size (t
, j
, j
))
2160 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2161 && !match_simd_size (t
, j
, j
))
2167 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2168 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2174 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2181 if (!t
->opcode_modifier
.d
)
2185 i
.error
= operand_size_mismatch
;
2189 /* Check reverse. */
2190 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2192 for (j
= 0; j
< i
.operands
; j
++)
2194 unsigned int given
= i
.operands
- j
- 1;
2196 if (t
->operand_types
[j
].bitfield
.class == Reg
2197 && !match_operand_size (t
, j
, given
))
2200 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2201 && !match_simd_size (t
, j
, given
))
2204 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2205 && (!match_operand_size (t
, j
, given
)
2206 || !match_simd_size (t
, j
, given
)))
2209 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2213 return match
| MATCH_REVERSE
;
2217 operand_type_match (i386_operand_type overlap
,
2218 i386_operand_type given
)
2220 i386_operand_type temp
= overlap
;
2222 temp
.bitfield
.unspecified
= 0;
2223 temp
.bitfield
.byte
= 0;
2224 temp
.bitfield
.word
= 0;
2225 temp
.bitfield
.dword
= 0;
2226 temp
.bitfield
.fword
= 0;
2227 temp
.bitfield
.qword
= 0;
2228 temp
.bitfield
.tbyte
= 0;
2229 temp
.bitfield
.xmmword
= 0;
2230 temp
.bitfield
.ymmword
= 0;
2231 temp
.bitfield
.zmmword
= 0;
2232 if (operand_type_all_zero (&temp
))
2235 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2239 i
.error
= operand_type_mismatch
;
2243 /* If given types g0 and g1 are registers they must be of the same type
2244 unless the expected operand type register overlap is null.
2245 Memory operand size of certain SIMD instructions is also being checked
2249 operand_type_register_match (i386_operand_type g0
,
2250 i386_operand_type t0
,
2251 i386_operand_type g1
,
2252 i386_operand_type t1
)
2254 if (g0
.bitfield
.class != Reg
2255 && g0
.bitfield
.class != RegSIMD
2256 && (!operand_type_check (g0
, anymem
)
2257 || g0
.bitfield
.unspecified
2258 || t0
.bitfield
.class != RegSIMD
))
2261 if (g1
.bitfield
.class != Reg
2262 && g1
.bitfield
.class != RegSIMD
2263 && (!operand_type_check (g1
, anymem
)
2264 || g1
.bitfield
.unspecified
2265 || t1
.bitfield
.class != RegSIMD
))
2268 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2269 && g0
.bitfield
.word
== g1
.bitfield
.word
2270 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2271 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2272 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2273 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2274 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2277 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2278 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2279 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2280 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2281 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2282 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2283 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2286 i
.error
= register_type_mismatch
;
2291 static INLINE
unsigned int
2292 register_number (const reg_entry
*r
)
2294 unsigned int nr
= r
->reg_num
;
2296 if (r
->reg_flags
& RegRex
)
2299 if (r
->reg_flags
& RegVRex
)
2305 static INLINE
unsigned int
2306 mode_from_disp_size (i386_operand_type t
)
2308 if (t
.bitfield
.disp8
)
2310 else if (t
.bitfield
.disp16
2311 || t
.bitfield
.disp32
2312 || t
.bitfield
.disp32s
)
2319 fits_in_signed_byte (addressT num
)
2321 return num
+ 0x80 <= 0xff;
2325 fits_in_unsigned_byte (addressT num
)
2331 fits_in_unsigned_word (addressT num
)
2333 return num
<= 0xffff;
2337 fits_in_signed_word (addressT num
)
2339 return num
+ 0x8000 <= 0xffff;
2343 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2348 return num
+ 0x80000000 <= 0xffffffff;
2350 } /* fits_in_signed_long() */
2353 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2358 return num
<= 0xffffffff;
2360 } /* fits_in_unsigned_long() */
2363 fits_in_disp8 (offsetT num
)
2365 int shift
= i
.memshift
;
2371 mask
= (1 << shift
) - 1;
2373 /* Return 0 if NUM isn't properly aligned. */
2377 /* Check if NUM will fit in 8bit after shift. */
2378 return fits_in_signed_byte (num
>> shift
);
2382 fits_in_imm4 (offsetT num
)
2384 return (num
& 0xf) == num
;
2387 static i386_operand_type
2388 smallest_imm_type (offsetT num
)
2390 i386_operand_type t
;
2392 operand_type_set (&t
, 0);
2393 t
.bitfield
.imm64
= 1;
2395 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2397 /* This code is disabled on the 486 because all the Imm1 forms
2398 in the opcode table are slower on the i486. They're the
2399 versions with the implicitly specified single-position
2400 displacement, which has another syntax if you really want to
2402 t
.bitfield
.imm1
= 1;
2403 t
.bitfield
.imm8
= 1;
2404 t
.bitfield
.imm8s
= 1;
2405 t
.bitfield
.imm16
= 1;
2406 t
.bitfield
.imm32
= 1;
2407 t
.bitfield
.imm32s
= 1;
2409 else if (fits_in_signed_byte (num
))
2411 t
.bitfield
.imm8
= 1;
2412 t
.bitfield
.imm8s
= 1;
2413 t
.bitfield
.imm16
= 1;
2414 t
.bitfield
.imm32
= 1;
2415 t
.bitfield
.imm32s
= 1;
2417 else if (fits_in_unsigned_byte (num
))
2419 t
.bitfield
.imm8
= 1;
2420 t
.bitfield
.imm16
= 1;
2421 t
.bitfield
.imm32
= 1;
2422 t
.bitfield
.imm32s
= 1;
2424 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2426 t
.bitfield
.imm16
= 1;
2427 t
.bitfield
.imm32
= 1;
2428 t
.bitfield
.imm32s
= 1;
2430 else if (fits_in_signed_long (num
))
2432 t
.bitfield
.imm32
= 1;
2433 t
.bitfield
.imm32s
= 1;
2435 else if (fits_in_unsigned_long (num
))
2436 t
.bitfield
.imm32
= 1;
2442 offset_in_range (offsetT val
, int size
)
2448 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2449 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2450 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2452 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2458 /* If BFD64, sign extend val for 32bit address mode. */
2459 if (flag_code
!= CODE_64BIT
2460 || i
.prefix
[ADDR_PREFIX
])
2461 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2462 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2465 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2467 char buf1
[40], buf2
[40];
2469 sprint_value (buf1
, val
);
2470 sprint_value (buf2
, val
& mask
);
2471 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2486 a. PREFIX_EXIST if attempting to add a prefix where one from the
2487 same class already exists.
2488 b. PREFIX_LOCK if lock prefix is added.
2489 c. PREFIX_REP if rep/repne prefix is added.
2490 d. PREFIX_DS if ds prefix is added.
2491 e. PREFIX_OTHER if other prefix is added.
2494 static enum PREFIX_GROUP
2495 add_prefix (unsigned int prefix
)
2497 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2500 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2501 && flag_code
== CODE_64BIT
)
2503 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2504 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2505 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2506 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2517 case DS_PREFIX_OPCODE
:
2520 case CS_PREFIX_OPCODE
:
2521 case ES_PREFIX_OPCODE
:
2522 case FS_PREFIX_OPCODE
:
2523 case GS_PREFIX_OPCODE
:
2524 case SS_PREFIX_OPCODE
:
2528 case REPNE_PREFIX_OPCODE
:
2529 case REPE_PREFIX_OPCODE
:
2534 case LOCK_PREFIX_OPCODE
:
2543 case ADDR_PREFIX_OPCODE
:
2547 case DATA_PREFIX_OPCODE
:
2551 if (i
.prefix
[q
] != 0)
2559 i
.prefix
[q
] |= prefix
;
2562 as_bad (_("same type of prefix used twice"));
2568 update_code_flag (int value
, int check
)
2570 PRINTF_LIKE ((*as_error
));
2572 flag_code
= (enum flag_code
) value
;
2573 if (flag_code
== CODE_64BIT
)
2575 cpu_arch_flags
.bitfield
.cpu64
= 1;
2576 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2580 cpu_arch_flags
.bitfield
.cpu64
= 0;
2581 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2583 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2586 as_error
= as_fatal
;
2589 (*as_error
) (_("64bit mode not supported on `%s'."),
2590 cpu_arch_name
? cpu_arch_name
: default_arch
);
2592 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2595 as_error
= as_fatal
;
2598 (*as_error
) (_("32bit mode not supported on `%s'."),
2599 cpu_arch_name
? cpu_arch_name
: default_arch
);
2601 stackop_size
= '\0';
2605 set_code_flag (int value
)
2607 update_code_flag (value
, 0);
2611 set_16bit_gcc_code_flag (int new_code_flag
)
2613 flag_code
= (enum flag_code
) new_code_flag
;
2614 if (flag_code
!= CODE_16BIT
)
2616 cpu_arch_flags
.bitfield
.cpu64
= 0;
2617 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2618 stackop_size
= LONG_MNEM_SUFFIX
;
2622 set_intel_syntax (int syntax_flag
)
2624 /* Find out if register prefixing is specified. */
2625 int ask_naked_reg
= 0;
2628 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2631 int e
= get_symbol_name (&string
);
2633 if (strcmp (string
, "prefix") == 0)
2635 else if (strcmp (string
, "noprefix") == 0)
2638 as_bad (_("bad argument to syntax directive."));
2639 (void) restore_line_pointer (e
);
2641 demand_empty_rest_of_line ();
2643 intel_syntax
= syntax_flag
;
2645 if (ask_naked_reg
== 0)
2646 allow_naked_reg
= (intel_syntax
2647 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2649 allow_naked_reg
= (ask_naked_reg
< 0);
2651 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2653 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2654 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2655 register_prefix
= allow_naked_reg
? "" : "%";
2659 set_intel_mnemonic (int mnemonic_flag
)
2661 intel_mnemonic
= mnemonic_flag
;
2665 set_allow_index_reg (int flag
)
2667 allow_index_reg
= flag
;
2671 set_check (int what
)
2673 enum check_kind
*kind
;
2678 kind
= &operand_check
;
2689 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2692 int e
= get_symbol_name (&string
);
2694 if (strcmp (string
, "none") == 0)
2696 else if (strcmp (string
, "warning") == 0)
2697 *kind
= check_warning
;
2698 else if (strcmp (string
, "error") == 0)
2699 *kind
= check_error
;
2701 as_bad (_("bad argument to %s_check directive."), str
);
2702 (void) restore_line_pointer (e
);
2705 as_bad (_("missing argument for %s_check directive"), str
);
2707 demand_empty_rest_of_line ();
2711 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2712 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2714 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2715 static const char *arch
;
2717 /* Intel LIOM is only supported on ELF. */
2723 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2724 use default_arch. */
2725 arch
= cpu_arch_name
;
2727 arch
= default_arch
;
2730 /* If we are targeting Intel MCU, we must enable it. */
2731 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2732 || new_flag
.bitfield
.cpuiamcu
)
2735 /* If we are targeting Intel L1OM, we must enable it. */
2736 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2737 || new_flag
.bitfield
.cpul1om
)
2740 /* If we are targeting Intel K1OM, we must enable it. */
2741 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2742 || new_flag
.bitfield
.cpuk1om
)
2745 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2750 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2754 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2757 int e
= get_symbol_name (&string
);
2759 i386_cpu_flags flags
;
2761 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2763 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2765 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2769 cpu_arch_name
= cpu_arch
[j
].name
;
2770 cpu_sub_arch_name
= NULL
;
2771 cpu_arch_flags
= cpu_arch
[j
].flags
;
2772 if (flag_code
== CODE_64BIT
)
2774 cpu_arch_flags
.bitfield
.cpu64
= 1;
2775 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2779 cpu_arch_flags
.bitfield
.cpu64
= 0;
2780 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2782 cpu_arch_isa
= cpu_arch
[j
].type
;
2783 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2784 if (!cpu_arch_tune_set
)
2786 cpu_arch_tune
= cpu_arch_isa
;
2787 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2792 flags
= cpu_flags_or (cpu_arch_flags
,
2795 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2797 if (cpu_sub_arch_name
)
2799 char *name
= cpu_sub_arch_name
;
2800 cpu_sub_arch_name
= concat (name
,
2802 (const char *) NULL
);
2806 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2807 cpu_arch_flags
= flags
;
2808 cpu_arch_isa_flags
= flags
;
2812 = cpu_flags_or (cpu_arch_isa_flags
,
2814 (void) restore_line_pointer (e
);
2815 demand_empty_rest_of_line ();
2820 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2822 /* Disable an ISA extension. */
2823 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2824 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2826 flags
= cpu_flags_and_not (cpu_arch_flags
,
2827 cpu_noarch
[j
].flags
);
2828 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2830 if (cpu_sub_arch_name
)
2832 char *name
= cpu_sub_arch_name
;
2833 cpu_sub_arch_name
= concat (name
, string
,
2834 (const char *) NULL
);
2838 cpu_sub_arch_name
= xstrdup (string
);
2839 cpu_arch_flags
= flags
;
2840 cpu_arch_isa_flags
= flags
;
2842 (void) restore_line_pointer (e
);
2843 demand_empty_rest_of_line ();
2847 j
= ARRAY_SIZE (cpu_arch
);
2850 if (j
>= ARRAY_SIZE (cpu_arch
))
2851 as_bad (_("no such architecture: `%s'"), string
);
2853 *input_line_pointer
= e
;
2856 as_bad (_("missing cpu architecture"));
2858 no_cond_jump_promotion
= 0;
2859 if (*input_line_pointer
== ','
2860 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2865 ++input_line_pointer
;
2866 e
= get_symbol_name (&string
);
2868 if (strcmp (string
, "nojumps") == 0)
2869 no_cond_jump_promotion
= 1;
2870 else if (strcmp (string
, "jumps") == 0)
2873 as_bad (_("no such architecture modifier: `%s'"), string
);
2875 (void) restore_line_pointer (e
);
2878 demand_empty_rest_of_line ();
2881 enum bfd_architecture
2884 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2886 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2887 || flag_code
!= CODE_64BIT
)
2888 as_fatal (_("Intel L1OM is 64bit ELF only"));
2889 return bfd_arch_l1om
;
2891 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2893 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2894 || flag_code
!= CODE_64BIT
)
2895 as_fatal (_("Intel K1OM is 64bit ELF only"));
2896 return bfd_arch_k1om
;
2898 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2900 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2901 || flag_code
== CODE_64BIT
)
2902 as_fatal (_("Intel MCU is 32bit ELF only"));
2903 return bfd_arch_iamcu
;
2906 return bfd_arch_i386
;
2912 if (!strncmp (default_arch
, "x86_64", 6))
2914 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2916 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2917 || default_arch
[6] != '\0')
2918 as_fatal (_("Intel L1OM is 64bit ELF only"));
2919 return bfd_mach_l1om
;
2921 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2923 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2924 || default_arch
[6] != '\0')
2925 as_fatal (_("Intel K1OM is 64bit ELF only"));
2926 return bfd_mach_k1om
;
2928 else if (default_arch
[6] == '\0')
2929 return bfd_mach_x86_64
;
2931 return bfd_mach_x64_32
;
2933 else if (!strcmp (default_arch
, "i386")
2934 || !strcmp (default_arch
, "iamcu"))
2936 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2938 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2939 as_fatal (_("Intel MCU is 32bit ELF only"));
2940 return bfd_mach_i386_iamcu
;
2943 return bfd_mach_i386_i386
;
2946 as_fatal (_("unknown architecture"));
2952 const char *hash_err
;
2954 /* Support pseudo prefixes like {disp32}. */
2955 lex_type
['{'] = LEX_BEGIN_NAME
;
2957 /* Initialize op_hash hash table. */
2958 op_hash
= hash_new ();
2961 const insn_template
*optab
;
2962 templates
*core_optab
;
2964 /* Setup for loop. */
2966 core_optab
= XNEW (templates
);
2967 core_optab
->start
= optab
;
2972 if (optab
->name
== NULL
2973 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2975 /* different name --> ship out current template list;
2976 add to hash table; & begin anew. */
2977 core_optab
->end
= optab
;
2978 hash_err
= hash_insert (op_hash
,
2980 (void *) core_optab
);
2983 as_fatal (_("can't hash %s: %s"),
2987 if (optab
->name
== NULL
)
2989 core_optab
= XNEW (templates
);
2990 core_optab
->start
= optab
;
2995 /* Initialize reg_hash hash table. */
2996 reg_hash
= hash_new ();
2998 const reg_entry
*regtab
;
2999 unsigned int regtab_size
= i386_regtab_size
;
3001 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3003 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3005 as_fatal (_("can't hash %s: %s"),
3011 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3016 for (c
= 0; c
< 256; c
++)
3021 mnemonic_chars
[c
] = c
;
3022 register_chars
[c
] = c
;
3023 operand_chars
[c
] = c
;
3025 else if (ISLOWER (c
))
3027 mnemonic_chars
[c
] = c
;
3028 register_chars
[c
] = c
;
3029 operand_chars
[c
] = c
;
3031 else if (ISUPPER (c
))
3033 mnemonic_chars
[c
] = TOLOWER (c
);
3034 register_chars
[c
] = mnemonic_chars
[c
];
3035 operand_chars
[c
] = c
;
3037 else if (c
== '{' || c
== '}')
3039 mnemonic_chars
[c
] = c
;
3040 operand_chars
[c
] = c
;
3043 if (ISALPHA (c
) || ISDIGIT (c
))
3044 identifier_chars
[c
] = c
;
3047 identifier_chars
[c
] = c
;
3048 operand_chars
[c
] = c
;
3053 identifier_chars
['@'] = '@';
3056 identifier_chars
['?'] = '?';
3057 operand_chars
['?'] = '?';
3059 digit_chars
['-'] = '-';
3060 mnemonic_chars
['_'] = '_';
3061 mnemonic_chars
['-'] = '-';
3062 mnemonic_chars
['.'] = '.';
3063 identifier_chars
['_'] = '_';
3064 identifier_chars
['.'] = '.';
3066 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3067 operand_chars
[(unsigned char) *p
] = *p
;
3070 if (flag_code
== CODE_64BIT
)
3072 #if defined (OBJ_COFF) && defined (TE_PE)
3073 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3076 x86_dwarf2_return_column
= 16;
3078 x86_cie_data_alignment
= -8;
3082 x86_dwarf2_return_column
= 8;
3083 x86_cie_data_alignment
= -4;
3086 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3087 can be turned into BRANCH_PREFIX frag. */
3088 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3093 i386_print_statistics (FILE *file
)
3095 hash_print_statistics (file
, "i386 opcode", op_hash
);
3096 hash_print_statistics (file
, "i386 register", reg_hash
);
3101 /* Debugging routines for md_assemble. */
3102 static void pte (insn_template
*);
3103 static void pt (i386_operand_type
);
3104 static void pe (expressionS
*);
3105 static void ps (symbolS
*);
3108 pi (const char *line
, i386_insn
*x
)
3112 fprintf (stdout
, "%s: template ", line
);
3114 fprintf (stdout
, " address: base %s index %s scale %x\n",
3115 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3116 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3117 x
->log2_scale_factor
);
3118 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3119 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3120 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3121 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3122 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3123 (x
->rex
& REX_W
) != 0,
3124 (x
->rex
& REX_R
) != 0,
3125 (x
->rex
& REX_X
) != 0,
3126 (x
->rex
& REX_B
) != 0);
3127 for (j
= 0; j
< x
->operands
; j
++)
3129 fprintf (stdout
, " #%d: ", j
+ 1);
3131 fprintf (stdout
, "\n");
3132 if (x
->types
[j
].bitfield
.class == Reg
3133 || x
->types
[j
].bitfield
.class == RegMMX
3134 || x
->types
[j
].bitfield
.class == RegSIMD
3135 || x
->types
[j
].bitfield
.class == SReg
3136 || x
->types
[j
].bitfield
.class == RegCR
3137 || x
->types
[j
].bitfield
.class == RegDR
3138 || x
->types
[j
].bitfield
.class == RegTR
)
3139 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3140 if (operand_type_check (x
->types
[j
], imm
))
3142 if (operand_type_check (x
->types
[j
], disp
))
3143 pe (x
->op
[j
].disps
);
3148 pte (insn_template
*t
)
3151 fprintf (stdout
, " %d operands ", t
->operands
);
3152 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3153 if (t
->extension_opcode
!= None
)
3154 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3155 if (t
->opcode_modifier
.d
)
3156 fprintf (stdout
, "D");
3157 if (t
->opcode_modifier
.w
)
3158 fprintf (stdout
, "W");
3159 fprintf (stdout
, "\n");
3160 for (j
= 0; j
< t
->operands
; j
++)
3162 fprintf (stdout
, " #%d type ", j
+ 1);
3163 pt (t
->operand_types
[j
]);
3164 fprintf (stdout
, "\n");
3171 fprintf (stdout
, " operation %d\n", e
->X_op
);
3172 fprintf (stdout
, " add_number %ld (%lx)\n",
3173 (long) e
->X_add_number
, (long) e
->X_add_number
);
3174 if (e
->X_add_symbol
)
3176 fprintf (stdout
, " add_symbol ");
3177 ps (e
->X_add_symbol
);
3178 fprintf (stdout
, "\n");
3182 fprintf (stdout
, " op_symbol ");
3183 ps (e
->X_op_symbol
);
3184 fprintf (stdout
, "\n");
3191 fprintf (stdout
, "%s type %s%s",
3193 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3194 segment_name (S_GET_SEGMENT (s
)));
3197 static struct type_name
3199 i386_operand_type mask
;
3202 const type_names
[] =
3204 { OPERAND_TYPE_REG8
, "r8" },
3205 { OPERAND_TYPE_REG16
, "r16" },
3206 { OPERAND_TYPE_REG32
, "r32" },
3207 { OPERAND_TYPE_REG64
, "r64" },
3208 { OPERAND_TYPE_ACC8
, "acc8" },
3209 { OPERAND_TYPE_ACC16
, "acc16" },
3210 { OPERAND_TYPE_ACC32
, "acc32" },
3211 { OPERAND_TYPE_ACC64
, "acc64" },
3212 { OPERAND_TYPE_IMM8
, "i8" },
3213 { OPERAND_TYPE_IMM8
, "i8s" },
3214 { OPERAND_TYPE_IMM16
, "i16" },
3215 { OPERAND_TYPE_IMM32
, "i32" },
3216 { OPERAND_TYPE_IMM32S
, "i32s" },
3217 { OPERAND_TYPE_IMM64
, "i64" },
3218 { OPERAND_TYPE_IMM1
, "i1" },
3219 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3220 { OPERAND_TYPE_DISP8
, "d8" },
3221 { OPERAND_TYPE_DISP16
, "d16" },
3222 { OPERAND_TYPE_DISP32
, "d32" },
3223 { OPERAND_TYPE_DISP32S
, "d32s" },
3224 { OPERAND_TYPE_DISP64
, "d64" },
3225 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3226 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3227 { OPERAND_TYPE_CONTROL
, "control reg" },
3228 { OPERAND_TYPE_TEST
, "test reg" },
3229 { OPERAND_TYPE_DEBUG
, "debug reg" },
3230 { OPERAND_TYPE_FLOATREG
, "FReg" },
3231 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3232 { OPERAND_TYPE_SREG
, "SReg" },
3233 { OPERAND_TYPE_REGMMX
, "rMMX" },
3234 { OPERAND_TYPE_REGXMM
, "rXMM" },
3235 { OPERAND_TYPE_REGYMM
, "rYMM" },
3236 { OPERAND_TYPE_REGZMM
, "rZMM" },
3237 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3241 pt (i386_operand_type t
)
3244 i386_operand_type a
;
3246 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3248 a
= operand_type_and (t
, type_names
[j
].mask
);
3249 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3250 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3255 #endif /* DEBUG386 */
3257 static bfd_reloc_code_real_type
3258 reloc (unsigned int size
,
3261 bfd_reloc_code_real_type other
)
3263 if (other
!= NO_RELOC
)
3265 reloc_howto_type
*rel
;
3270 case BFD_RELOC_X86_64_GOT32
:
3271 return BFD_RELOC_X86_64_GOT64
;
3273 case BFD_RELOC_X86_64_GOTPLT64
:
3274 return BFD_RELOC_X86_64_GOTPLT64
;
3276 case BFD_RELOC_X86_64_PLTOFF64
:
3277 return BFD_RELOC_X86_64_PLTOFF64
;
3279 case BFD_RELOC_X86_64_GOTPC32
:
3280 other
= BFD_RELOC_X86_64_GOTPC64
;
3282 case BFD_RELOC_X86_64_GOTPCREL
:
3283 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3285 case BFD_RELOC_X86_64_TPOFF32
:
3286 other
= BFD_RELOC_X86_64_TPOFF64
;
3288 case BFD_RELOC_X86_64_DTPOFF32
:
3289 other
= BFD_RELOC_X86_64_DTPOFF64
;
3295 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3296 if (other
== BFD_RELOC_SIZE32
)
3299 other
= BFD_RELOC_SIZE64
;
3302 as_bad (_("there are no pc-relative size relocations"));
3308 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3309 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3312 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3314 as_bad (_("unknown relocation (%u)"), other
);
3315 else if (size
!= bfd_get_reloc_size (rel
))
3316 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3317 bfd_get_reloc_size (rel
),
3319 else if (pcrel
&& !rel
->pc_relative
)
3320 as_bad (_("non-pc-relative relocation for pc-relative field"));
3321 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3323 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3325 as_bad (_("relocated field and relocation type differ in signedness"));
3334 as_bad (_("there are no unsigned pc-relative relocations"));
3337 case 1: return BFD_RELOC_8_PCREL
;
3338 case 2: return BFD_RELOC_16_PCREL
;
3339 case 4: return BFD_RELOC_32_PCREL
;
3340 case 8: return BFD_RELOC_64_PCREL
;
3342 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3349 case 4: return BFD_RELOC_X86_64_32S
;
3354 case 1: return BFD_RELOC_8
;
3355 case 2: return BFD_RELOC_16
;
3356 case 4: return BFD_RELOC_32
;
3357 case 8: return BFD_RELOC_64
;
3359 as_bad (_("cannot do %s %u byte relocation"),
3360 sign
> 0 ? "signed" : "unsigned", size
);
3366 /* Here we decide which fixups can be adjusted to make them relative to
3367 the beginning of the section instead of the symbol. Basically we need
3368 to make sure that the dynamic relocations are done correctly, so in
3369 some cases we force the original symbol to be used. */
3372 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3374 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3378 /* Don't adjust pc-relative references to merge sections in 64-bit
3380 if (use_rela_relocations
3381 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3385 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3386 and changed later by validate_fix. */
3387 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3388 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3391 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3392 for size relocations. */
3393 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3394 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3395 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3396 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3397 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3398 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3399 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3400 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3401 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3402 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3409 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3410 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3411 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3412 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3424 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3425 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3432 intel_float_operand (const char *mnemonic
)
3434 /* Note that the value returned is meaningful only for opcodes with (memory)
3435 operands, hence the code here is free to improperly handle opcodes that
3436 have no operands (for better performance and smaller code). */
3438 if (mnemonic
[0] != 'f')
3439 return 0; /* non-math */
3441 switch (mnemonic
[1])
3443 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3444 the fs segment override prefix not currently handled because no
3445 call path can make opcodes without operands get here */
3447 return 2 /* integer op */;
3449 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3450 return 3; /* fldcw/fldenv */
3453 if (mnemonic
[2] != 'o' /* fnop */)
3454 return 3; /* non-waiting control op */
3457 if (mnemonic
[2] == 's')
3458 return 3; /* frstor/frstpm */
3461 if (mnemonic
[2] == 'a')
3462 return 3; /* fsave */
3463 if (mnemonic
[2] == 't')
3465 switch (mnemonic
[3])
3467 case 'c': /* fstcw */
3468 case 'd': /* fstdw */
3469 case 'e': /* fstenv */
3470 case 's': /* fsts[gw] */
3476 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3477 return 0; /* fxsave/fxrstor are not really math ops */
3484 /* Build the VEX prefix. */
3487 build_vex_prefix (const insn_template
*t
)
3489 unsigned int register_specifier
;
3490 unsigned int implied_prefix
;
3491 unsigned int vector_length
;
3494 /* Check register specifier. */
3495 if (i
.vex
.register_specifier
)
3497 register_specifier
=
3498 ~register_number (i
.vex
.register_specifier
) & 0xf;
3499 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3502 register_specifier
= 0xf;
3504 /* Use 2-byte VEX prefix by swapping destination and source operand
3505 if there are more than 1 register operand. */
3506 if (i
.reg_operands
> 1
3507 && i
.vec_encoding
!= vex_encoding_vex3
3508 && i
.dir_encoding
== dir_encoding_default
3509 && i
.operands
== i
.reg_operands
3510 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3511 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3512 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3515 unsigned int xchg
= i
.operands
- 1;
3516 union i386_op temp_op
;
3517 i386_operand_type temp_type
;
3519 temp_type
= i
.types
[xchg
];
3520 i
.types
[xchg
] = i
.types
[0];
3521 i
.types
[0] = temp_type
;
3522 temp_op
= i
.op
[xchg
];
3523 i
.op
[xchg
] = i
.op
[0];
3526 gas_assert (i
.rm
.mode
== 3);
3530 i
.rm
.regmem
= i
.rm
.reg
;
3533 if (i
.tm
.opcode_modifier
.d
)
3534 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3535 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3536 else /* Use the next insn. */
3540 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3541 are no memory operands and at least 3 register ones. */
3542 if (i
.reg_operands
>= 3
3543 && i
.vec_encoding
!= vex_encoding_vex3
3544 && i
.reg_operands
== i
.operands
- i
.imm_operands
3545 && i
.tm
.opcode_modifier
.vex
3546 && i
.tm
.opcode_modifier
.commutative
3547 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3549 && i
.vex
.register_specifier
3550 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3552 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3553 union i386_op temp_op
;
3554 i386_operand_type temp_type
;
3556 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3557 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3558 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3559 &i
.types
[i
.operands
- 3]));
3560 gas_assert (i
.rm
.mode
== 3);
3562 temp_type
= i
.types
[xchg
];
3563 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3564 i
.types
[xchg
+ 1] = temp_type
;
3565 temp_op
= i
.op
[xchg
];
3566 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3567 i
.op
[xchg
+ 1] = temp_op
;
3570 xchg
= i
.rm
.regmem
| 8;
3571 i
.rm
.regmem
= ~register_specifier
& 0xf;
3572 gas_assert (!(i
.rm
.regmem
& 8));
3573 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3574 register_specifier
= ~xchg
& 0xf;
3577 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3578 vector_length
= avxscalar
;
3579 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3585 /* Determine vector length from the last multi-length vector
3588 for (op
= t
->operands
; op
--;)
3589 if (t
->operand_types
[op
].bitfield
.xmmword
3590 && t
->operand_types
[op
].bitfield
.ymmword
3591 && i
.types
[op
].bitfield
.ymmword
)
3598 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3603 case DATA_PREFIX_OPCODE
:
3606 case REPE_PREFIX_OPCODE
:
3609 case REPNE_PREFIX_OPCODE
:
3616 /* Check the REX.W bit and VEXW. */
3617 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3618 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3619 else if (i
.tm
.opcode_modifier
.vexw
)
3620 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3622 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3624 /* Use 2-byte VEX prefix if possible. */
3626 && i
.vec_encoding
!= vex_encoding_vex3
3627 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3628 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3630 /* 2-byte VEX prefix. */
3634 i
.vex
.bytes
[0] = 0xc5;
3636 /* Check the REX.R bit. */
3637 r
= (i
.rex
& REX_R
) ? 0 : 1;
3638 i
.vex
.bytes
[1] = (r
<< 7
3639 | register_specifier
<< 3
3640 | vector_length
<< 2
3645 /* 3-byte VEX prefix. */
3650 switch (i
.tm
.opcode_modifier
.vexopcode
)
3654 i
.vex
.bytes
[0] = 0xc4;
3658 i
.vex
.bytes
[0] = 0xc4;
3662 i
.vex
.bytes
[0] = 0xc4;
3666 i
.vex
.bytes
[0] = 0x8f;
3670 i
.vex
.bytes
[0] = 0x8f;
3674 i
.vex
.bytes
[0] = 0x8f;
3680 /* The high 3 bits of the second VEX byte are 1's compliment
3681 of RXB bits from REX. */
3682 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3684 i
.vex
.bytes
[2] = (w
<< 7
3685 | register_specifier
<< 3
3686 | vector_length
<< 2
3691 static INLINE bfd_boolean
3692 is_evex_encoding (const insn_template
*t
)
3694 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3695 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3696 || t
->opcode_modifier
.sae
;
3699 static INLINE bfd_boolean
3700 is_any_vex_encoding (const insn_template
*t
)
3702 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3703 || is_evex_encoding (t
);
3706 /* Build the EVEX prefix. */
3709 build_evex_prefix (void)
3711 unsigned int register_specifier
;
3712 unsigned int implied_prefix
;
3714 rex_byte vrex_used
= 0;
3716 /* Check register specifier. */
3717 if (i
.vex
.register_specifier
)
3719 gas_assert ((i
.vrex
& REX_X
) == 0);
3721 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3722 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3723 register_specifier
+= 8;
3724 /* The upper 16 registers are encoded in the fourth byte of the
3726 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3727 i
.vex
.bytes
[3] = 0x8;
3728 register_specifier
= ~register_specifier
& 0xf;
3732 register_specifier
= 0xf;
3734 /* Encode upper 16 vector index register in the fourth byte of
3736 if (!(i
.vrex
& REX_X
))
3737 i
.vex
.bytes
[3] = 0x8;
3742 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3747 case DATA_PREFIX_OPCODE
:
3750 case REPE_PREFIX_OPCODE
:
3753 case REPNE_PREFIX_OPCODE
:
3760 /* 4 byte EVEX prefix. */
3762 i
.vex
.bytes
[0] = 0x62;
3765 switch (i
.tm
.opcode_modifier
.vexopcode
)
3781 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3783 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3785 /* The fifth bit of the second EVEX byte is 1's compliment of the
3786 REX_R bit in VREX. */
3787 if (!(i
.vrex
& REX_R
))
3788 i
.vex
.bytes
[1] |= 0x10;
3792 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3794 /* When all operands are registers, the REX_X bit in REX is not
3795 used. We reuse it to encode the upper 16 registers, which is
3796 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3797 as 1's compliment. */
3798 if ((i
.vrex
& REX_B
))
3801 i
.vex
.bytes
[1] &= ~0x40;
3805 /* EVEX instructions shouldn't need the REX prefix. */
3806 i
.vrex
&= ~vrex_used
;
3807 gas_assert (i
.vrex
== 0);
3809 /* Check the REX.W bit and VEXW. */
3810 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3811 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3812 else if (i
.tm
.opcode_modifier
.vexw
)
3813 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3815 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3817 /* Encode the U bit. */
3818 implied_prefix
|= 0x4;
3820 /* The third byte of the EVEX prefix. */
3821 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3823 /* The fourth byte of the EVEX prefix. */
3824 /* The zeroing-masking bit. */
3825 if (i
.mask
&& i
.mask
->zeroing
)
3826 i
.vex
.bytes
[3] |= 0x80;
3828 /* Don't always set the broadcast bit if there is no RC. */
3831 /* Encode the vector length. */
3832 unsigned int vec_length
;
3834 if (!i
.tm
.opcode_modifier
.evex
3835 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3839 /* Determine vector length from the last multi-length vector
3842 for (op
= i
.operands
; op
--;)
3843 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3844 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3845 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3847 if (i
.types
[op
].bitfield
.zmmword
)
3849 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3852 else if (i
.types
[op
].bitfield
.ymmword
)
3854 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3857 else if (i
.types
[op
].bitfield
.xmmword
)
3859 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3862 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3864 switch (i
.broadcast
->bytes
)
3867 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3870 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3873 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3882 if (op
>= MAX_OPERANDS
)
3886 switch (i
.tm
.opcode_modifier
.evex
)
3888 case EVEXLIG
: /* LL' is ignored */
3889 vec_length
= evexlig
<< 5;
3892 vec_length
= 0 << 5;
3895 vec_length
= 1 << 5;
3898 vec_length
= 2 << 5;
3904 i
.vex
.bytes
[3] |= vec_length
;
3905 /* Encode the broadcast bit. */
3907 i
.vex
.bytes
[3] |= 0x10;
3911 if (i
.rounding
->type
!= saeonly
)
3912 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3914 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3917 if (i
.mask
&& i
.mask
->mask
)
3918 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3922 process_immext (void)
3926 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3927 which is coded in the same place as an 8-bit immediate field
3928 would be. Here we fake an 8-bit immediate operand from the
3929 opcode suffix stored in tm.extension_opcode.
3931 AVX instructions also use this encoding, for some of
3932 3 argument instructions. */
3934 gas_assert (i
.imm_operands
<= 1
3936 || (is_any_vex_encoding (&i
.tm
)
3937 && i
.operands
<= 4)));
3939 exp
= &im_expressions
[i
.imm_operands
++];
3940 i
.op
[i
.operands
].imms
= exp
;
3941 i
.types
[i
.operands
] = imm8
;
3943 exp
->X_op
= O_constant
;
3944 exp
->X_add_number
= i
.tm
.extension_opcode
;
3945 i
.tm
.extension_opcode
= None
;
3952 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3957 as_bad (_("invalid instruction `%s' after `%s'"),
3958 i
.tm
.name
, i
.hle_prefix
);
3961 if (i
.prefix
[LOCK_PREFIX
])
3963 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3967 case HLEPrefixRelease
:
3968 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3970 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3974 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3976 as_bad (_("memory destination needed for instruction `%s'"
3977 " after `xrelease'"), i
.tm
.name
);
3984 /* Try the shortest encoding by shortening operand size. */
3987 optimize_encoding (void)
3991 if (optimize_for_space
3992 && i
.reg_operands
== 1
3993 && i
.imm_operands
== 1
3994 && !i
.types
[1].bitfield
.byte
3995 && i
.op
[0].imms
->X_op
== O_constant
3996 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3997 && ((i
.tm
.base_opcode
== 0xa8
3998 && i
.tm
.extension_opcode
== None
)
3999 || (i
.tm
.base_opcode
== 0xf6
4000 && i
.tm
.extension_opcode
== 0x0)))
4003 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4005 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4006 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4008 i
.types
[1].bitfield
.byte
= 1;
4009 /* Ignore the suffix. */
4011 if (base_regnum
>= 4
4012 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4014 /* Handle SP, BP, SI and DI registers. */
4015 if (i
.types
[1].bitfield
.word
)
4017 else if (i
.types
[1].bitfield
.dword
)
4025 else if (flag_code
== CODE_64BIT
4026 && ((i
.types
[1].bitfield
.qword
4027 && i
.reg_operands
== 1
4028 && i
.imm_operands
== 1
4029 && i
.op
[0].imms
->X_op
== O_constant
4030 && ((i
.tm
.base_opcode
== 0xb8
4031 && i
.tm
.extension_opcode
== None
4032 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4033 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4034 && (((i
.tm
.base_opcode
== 0x24
4035 || i
.tm
.base_opcode
== 0xa8)
4036 && i
.tm
.extension_opcode
== None
)
4037 || (i
.tm
.base_opcode
== 0x80
4038 && i
.tm
.extension_opcode
== 0x4)
4039 || ((i
.tm
.base_opcode
== 0xf6
4040 || (i
.tm
.base_opcode
| 1) == 0xc7)
4041 && i
.tm
.extension_opcode
== 0x0)))
4042 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4043 && i
.tm
.base_opcode
== 0x83
4044 && i
.tm
.extension_opcode
== 0x4)))
4045 || (i
.types
[0].bitfield
.qword
4046 && ((i
.reg_operands
== 2
4047 && i
.op
[0].regs
== i
.op
[1].regs
4048 && ((i
.tm
.base_opcode
== 0x30
4049 || i
.tm
.base_opcode
== 0x28)
4050 && i
.tm
.extension_opcode
== None
))
4051 || (i
.reg_operands
== 1
4053 && i
.tm
.base_opcode
== 0x30
4054 && i
.tm
.extension_opcode
== None
)))))
4057 andq $imm31, %r64 -> andl $imm31, %r32
4058 andq $imm7, %r64 -> andl $imm7, %r32
4059 testq $imm31, %r64 -> testl $imm31, %r32
4060 xorq %r64, %r64 -> xorl %r32, %r32
4061 subq %r64, %r64 -> subl %r32, %r32
4062 movq $imm31, %r64 -> movl $imm31, %r32
4063 movq $imm32, %r64 -> movl $imm32, %r32
4065 i
.tm
.opcode_modifier
.norex64
= 1;
4066 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4069 movq $imm31, %r64 -> movl $imm31, %r32
4070 movq $imm32, %r64 -> movl $imm32, %r32
4072 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4073 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4074 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4075 i
.types
[0].bitfield
.imm32
= 1;
4076 i
.types
[0].bitfield
.imm32s
= 0;
4077 i
.types
[0].bitfield
.imm64
= 0;
4078 i
.types
[1].bitfield
.dword
= 1;
4079 i
.types
[1].bitfield
.qword
= 0;
4080 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4083 movq $imm31, %r64 -> movl $imm31, %r32
4085 i
.tm
.base_opcode
= 0xb8;
4086 i
.tm
.extension_opcode
= None
;
4087 i
.tm
.opcode_modifier
.w
= 0;
4088 i
.tm
.opcode_modifier
.shortform
= 1;
4089 i
.tm
.opcode_modifier
.modrm
= 0;
4093 else if (optimize
> 1
4094 && !optimize_for_space
4095 && i
.reg_operands
== 2
4096 && i
.op
[0].regs
== i
.op
[1].regs
4097 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4098 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4099 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4102 andb %rN, %rN -> testb %rN, %rN
4103 andw %rN, %rN -> testw %rN, %rN
4104 andq %rN, %rN -> testq %rN, %rN
4105 orb %rN, %rN -> testb %rN, %rN
4106 orw %rN, %rN -> testw %rN, %rN
4107 orq %rN, %rN -> testq %rN, %rN
4109 and outside of 64-bit mode
4111 andl %rN, %rN -> testl %rN, %rN
4112 orl %rN, %rN -> testl %rN, %rN
4114 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4116 else if (i
.reg_operands
== 3
4117 && i
.op
[0].regs
== i
.op
[1].regs
4118 && !i
.types
[2].bitfield
.xmmword
4119 && (i
.tm
.opcode_modifier
.vex
4120 || ((!i
.mask
|| i
.mask
->zeroing
)
4122 && is_evex_encoding (&i
.tm
)
4123 && (i
.vec_encoding
!= vex_encoding_evex
4124 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4125 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4126 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4127 && i
.types
[2].bitfield
.ymmword
))))
4128 && ((i
.tm
.base_opcode
== 0x55
4129 || i
.tm
.base_opcode
== 0x6655
4130 || i
.tm
.base_opcode
== 0x66df
4131 || i
.tm
.base_opcode
== 0x57
4132 || i
.tm
.base_opcode
== 0x6657
4133 || i
.tm
.base_opcode
== 0x66ef
4134 || i
.tm
.base_opcode
== 0x66f8
4135 || i
.tm
.base_opcode
== 0x66f9
4136 || i
.tm
.base_opcode
== 0x66fa
4137 || i
.tm
.base_opcode
== 0x66fb
4138 || i
.tm
.base_opcode
== 0x42
4139 || i
.tm
.base_opcode
== 0x6642
4140 || i
.tm
.base_opcode
== 0x47
4141 || i
.tm
.base_opcode
== 0x6647)
4142 && i
.tm
.extension_opcode
== None
))
4145 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4147 EVEX VOP %zmmM, %zmmM, %zmmN
4148 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4149 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4150 EVEX VOP %ymmM, %ymmM, %ymmN
4151 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4152 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4153 VEX VOP %ymmM, %ymmM, %ymmN
4154 -> VEX VOP %xmmM, %xmmM, %xmmN
4155 VOP, one of vpandn and vpxor:
4156 VEX VOP %ymmM, %ymmM, %ymmN
4157 -> VEX VOP %xmmM, %xmmM, %xmmN
4158 VOP, one of vpandnd and vpandnq:
4159 EVEX VOP %zmmM, %zmmM, %zmmN
4160 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4161 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4162 EVEX VOP %ymmM, %ymmM, %ymmN
4163 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4164 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4165 VOP, one of vpxord and vpxorq:
4166 EVEX VOP %zmmM, %zmmM, %zmmN
4167 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4168 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4169 EVEX VOP %ymmM, %ymmM, %ymmN
4170 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4171 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4172 VOP, one of kxord and kxorq:
4173 VEX VOP %kM, %kM, %kN
4174 -> VEX kxorw %kM, %kM, %kN
4175 VOP, one of kandnd and kandnq:
4176 VEX VOP %kM, %kM, %kN
4177 -> VEX kandnw %kM, %kM, %kN
4179 if (is_evex_encoding (&i
.tm
))
4181 if (i
.vec_encoding
!= vex_encoding_evex
)
4183 i
.tm
.opcode_modifier
.vex
= VEX128
;
4184 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4185 i
.tm
.opcode_modifier
.evex
= 0;
4187 else if (optimize
> 1)
4188 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4192 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4194 i
.tm
.base_opcode
&= 0xff;
4195 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4198 i
.tm
.opcode_modifier
.vex
= VEX128
;
4200 if (i
.tm
.opcode_modifier
.vex
)
4201 for (j
= 0; j
< 3; j
++)
4203 i
.types
[j
].bitfield
.xmmword
= 1;
4204 i
.types
[j
].bitfield
.ymmword
= 0;
4207 else if (i
.vec_encoding
!= vex_encoding_evex
4208 && !i
.types
[0].bitfield
.zmmword
4209 && !i
.types
[1].bitfield
.zmmword
4212 && is_evex_encoding (&i
.tm
)
4213 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4214 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4215 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4216 || (i
.tm
.base_opcode
& ~4) == 0x66db
4217 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4218 && i
.tm
.extension_opcode
== None
)
4221 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4222 vmovdqu32 and vmovdqu64:
4223 EVEX VOP %xmmM, %xmmN
4224 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4225 EVEX VOP %ymmM, %ymmN
4226 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4228 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4230 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4232 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4234 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4235 VOP, one of vpand, vpandn, vpor, vpxor:
4236 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4237 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4238 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4239 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4240 EVEX VOP{d,q} mem, %xmmM, %xmmN
4241 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4242 EVEX VOP{d,q} mem, %ymmM, %ymmN
4243 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4245 for (j
= 0; j
< i
.operands
; j
++)
4246 if (operand_type_check (i
.types
[j
], disp
)
4247 && i
.op
[j
].disps
->X_op
== O_constant
)
4249 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4250 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4251 bytes, we choose EVEX Disp8 over VEX Disp32. */
4252 int evex_disp8
, vex_disp8
;
4253 unsigned int memshift
= i
.memshift
;
4254 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4256 evex_disp8
= fits_in_disp8 (n
);
4258 vex_disp8
= fits_in_disp8 (n
);
4259 if (evex_disp8
!= vex_disp8
)
4261 i
.memshift
= memshift
;
4265 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4268 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4269 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4270 i
.tm
.opcode_modifier
.vex
4271 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4272 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4273 /* VPAND, VPOR, and VPXOR are commutative. */
4274 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4275 i
.tm
.opcode_modifier
.commutative
= 1;
4276 i
.tm
.opcode_modifier
.evex
= 0;
4277 i
.tm
.opcode_modifier
.masking
= 0;
4278 i
.tm
.opcode_modifier
.broadcast
= 0;
4279 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4282 i
.types
[j
].bitfield
.disp8
4283 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4287 /* This is the guts of the machine-dependent assembler. LINE points to a
4288 machine dependent instruction. This function is supposed to emit
4289 the frags/bytes it assembles to. */
4292 md_assemble (char *line
)
4295 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4296 const insn_template
*t
;
4298 /* Initialize globals. */
4299 memset (&i
, '\0', sizeof (i
));
4300 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4301 i
.reloc
[j
] = NO_RELOC
;
4302 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4303 memset (im_expressions
, '\0', sizeof (im_expressions
));
4304 save_stack_p
= save_stack
;
4306 /* First parse an instruction mnemonic & call i386_operand for the operands.
4307 We assume that the scrubber has arranged it so that line[0] is the valid
4308 start of a (possibly prefixed) mnemonic. */
4310 line
= parse_insn (line
, mnemonic
);
4313 mnem_suffix
= i
.suffix
;
4315 line
= parse_operands (line
, mnemonic
);
4317 xfree (i
.memop1_string
);
4318 i
.memop1_string
= NULL
;
4322 /* Now we've parsed the mnemonic into a set of templates, and have the
4323 operands at hand. */
4325 /* All intel opcodes have reversed operands except for "bound" and
4326 "enter". We also don't reverse intersegment "jmp" and "call"
4327 instructions with 2 immediate operands so that the immediate segment
4328 precedes the offset, as it does when in AT&T mode. */
4331 && (strcmp (mnemonic
, "bound") != 0)
4332 && (strcmp (mnemonic
, "invlpga") != 0)
4333 && !(operand_type_check (i
.types
[0], imm
)
4334 && operand_type_check (i
.types
[1], imm
)))
4337 /* The order of the immediates should be reversed
4338 for 2 immediates extrq and insertq instructions */
4339 if (i
.imm_operands
== 2
4340 && (strcmp (mnemonic
, "extrq") == 0
4341 || strcmp (mnemonic
, "insertq") == 0))
4342 swap_2_operands (0, 1);
4347 /* Don't optimize displacement for movabs since it only takes 64bit
4350 && i
.disp_encoding
!= disp_encoding_32bit
4351 && (flag_code
!= CODE_64BIT
4352 || strcmp (mnemonic
, "movabs") != 0))
4355 /* Next, we find a template that matches the given insn,
4356 making sure the overlap of the given operands types is consistent
4357 with the template operand types. */
4359 if (!(t
= match_template (mnem_suffix
)))
4362 if (sse_check
!= check_none
4363 && !i
.tm
.opcode_modifier
.noavx
4364 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4365 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4366 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4367 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4368 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4369 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4372 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4373 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4374 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4375 || i
.tm
.cpu_flags
.bitfield
.cpusha
4376 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4378 (sse_check
== check_warning
4380 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4383 /* Zap movzx and movsx suffix. The suffix has been set from
4384 "word ptr" or "byte ptr" on the source operand in Intel syntax
4385 or extracted from mnemonic in AT&T syntax. But we'll use
4386 the destination register to choose the suffix for encoding. */
4387 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4389 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4390 there is no suffix, the default will be byte extension. */
4391 if (i
.reg_operands
!= 2
4394 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4399 if (i
.tm
.opcode_modifier
.fwait
)
4400 if (!add_prefix (FWAIT_OPCODE
))
4403 /* Check if REP prefix is OK. */
4404 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4406 as_bad (_("invalid instruction `%s' after `%s'"),
4407 i
.tm
.name
, i
.rep_prefix
);
4411 /* Check for lock without a lockable instruction. Destination operand
4412 must be memory unless it is xchg (0x86). */
4413 if (i
.prefix
[LOCK_PREFIX
]
4414 && (!i
.tm
.opcode_modifier
.islockable
4415 || i
.mem_operands
== 0
4416 || (i
.tm
.base_opcode
!= 0x86
4417 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4419 as_bad (_("expecting lockable instruction after `lock'"));
4423 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4424 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4426 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4430 /* Check if HLE prefix is OK. */
4431 if (i
.hle_prefix
&& !check_hle ())
4434 /* Check BND prefix. */
4435 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4436 as_bad (_("expecting valid branch instruction after `bnd'"));
4438 /* Check NOTRACK prefix. */
4439 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4440 as_bad (_("expecting indirect branch instruction after `notrack'"));
4442 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4444 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4445 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4446 else if (flag_code
!= CODE_16BIT
4447 ? i
.prefix
[ADDR_PREFIX
]
4448 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4449 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4452 /* Insert BND prefix. */
4453 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4455 if (!i
.prefix
[BND_PREFIX
])
4456 add_prefix (BND_PREFIX_OPCODE
);
4457 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4459 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4460 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4464 /* Check string instruction segment overrides. */
4465 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4467 gas_assert (i
.mem_operands
);
4468 if (!check_string ())
4470 i
.disp_operands
= 0;
4473 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4474 optimize_encoding ();
4476 if (!process_suffix ())
4479 /* Update operand types. */
4480 for (j
= 0; j
< i
.operands
; j
++)
4481 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4483 /* Make still unresolved immediate matches conform to size of immediate
4484 given in i.suffix. */
4485 if (!finalize_imm ())
4488 if (i
.types
[0].bitfield
.imm1
)
4489 i
.imm_operands
= 0; /* kludge for shift insns. */
4491 /* We only need to check those implicit registers for instructions
4492 with 3 operands or less. */
4493 if (i
.operands
<= 3)
4494 for (j
= 0; j
< i
.operands
; j
++)
4495 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4496 && !i
.types
[j
].bitfield
.xmmword
)
4499 /* ImmExt should be processed after SSE2AVX. */
4500 if (!i
.tm
.opcode_modifier
.sse2avx
4501 && i
.tm
.opcode_modifier
.immext
)
4504 /* For insns with operands there are more diddles to do to the opcode. */
4507 if (!process_operands ())
4510 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4512 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4513 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4516 if (is_any_vex_encoding (&i
.tm
))
4518 if (!cpu_arch_flags
.bitfield
.cpui286
)
4520 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4525 if (i
.tm
.opcode_modifier
.vex
)
4526 build_vex_prefix (t
);
4528 build_evex_prefix ();
4531 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4532 instructions may define INT_OPCODE as well, so avoid this corner
4533 case for those instructions that use MODRM. */
4534 if (i
.tm
.base_opcode
== INT_OPCODE
4535 && !i
.tm
.opcode_modifier
.modrm
4536 && i
.op
[0].imms
->X_add_number
== 3)
4538 i
.tm
.base_opcode
= INT3_OPCODE
;
4542 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4543 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4544 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4545 && i
.op
[0].disps
->X_op
== O_constant
)
4547 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4548 the absolute address given by the constant. Since ix86 jumps and
4549 calls are pc relative, we need to generate a reloc. */
4550 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4551 i
.op
[0].disps
->X_op
= O_symbol
;
4554 if (i
.tm
.opcode_modifier
.rex64
)
4557 /* For 8 bit registers we need an empty rex prefix. Also if the
4558 instruction already has a prefix, we need to convert old
4559 registers to new ones. */
4561 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4562 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4563 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4564 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4565 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4566 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4571 i
.rex
|= REX_OPCODE
;
4572 for (x
= 0; x
< 2; x
++)
4574 /* Look for 8 bit operand that uses old registers. */
4575 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4576 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4578 /* In case it is "hi" register, give up. */
4579 if (i
.op
[x
].regs
->reg_num
> 3)
4580 as_bad (_("can't encode register '%s%s' in an "
4581 "instruction requiring REX prefix."),
4582 register_prefix
, i
.op
[x
].regs
->reg_name
);
4584 /* Otherwise it is equivalent to the extended register.
4585 Since the encoding doesn't change this is merely
4586 cosmetic cleanup for debug output. */
4588 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4593 if (i
.rex
== 0 && i
.rex_encoding
)
4595 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4596 that uses legacy register. If it is "hi" register, don't add
4597 the REX_OPCODE byte. */
4599 for (x
= 0; x
< 2; x
++)
4600 if (i
.types
[x
].bitfield
.class == Reg
4601 && i
.types
[x
].bitfield
.byte
4602 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4603 && i
.op
[x
].regs
->reg_num
> 3)
4605 i
.rex_encoding
= FALSE
;
4614 add_prefix (REX_OPCODE
| i
.rex
);
4616 /* We are ready to output the insn. */
4619 last_insn
.seg
= now_seg
;
4621 if (i
.tm
.opcode_modifier
.isprefix
)
4623 last_insn
.kind
= last_insn_prefix
;
4624 last_insn
.name
= i
.tm
.name
;
4625 last_insn
.file
= as_where (&last_insn
.line
);
4628 last_insn
.kind
= last_insn_other
;
4632 parse_insn (char *line
, char *mnemonic
)
4635 char *token_start
= l
;
4638 const insn_template
*t
;
4644 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4649 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4651 as_bad (_("no such instruction: `%s'"), token_start
);
4656 if (!is_space_char (*l
)
4657 && *l
!= END_OF_INSN
4659 || (*l
!= PREFIX_SEPARATOR
4662 as_bad (_("invalid character %s in mnemonic"),
4663 output_invalid (*l
));
4666 if (token_start
== l
)
4668 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4669 as_bad (_("expecting prefix; got nothing"));
4671 as_bad (_("expecting mnemonic; got nothing"));
4675 /* Look up instruction (or prefix) via hash table. */
4676 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4678 if (*l
!= END_OF_INSN
4679 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4680 && current_templates
4681 && current_templates
->start
->opcode_modifier
.isprefix
)
4683 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4685 as_bad ((flag_code
!= CODE_64BIT
4686 ? _("`%s' is only supported in 64-bit mode")
4687 : _("`%s' is not supported in 64-bit mode")),
4688 current_templates
->start
->name
);
4691 /* If we are in 16-bit mode, do not allow addr16 or data16.
4692 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4693 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4694 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4695 && flag_code
!= CODE_64BIT
4696 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4697 ^ (flag_code
== CODE_16BIT
)))
4699 as_bad (_("redundant %s prefix"),
4700 current_templates
->start
->name
);
4703 if (current_templates
->start
->opcode_length
== 0)
4705 /* Handle pseudo prefixes. */
4706 switch (current_templates
->start
->base_opcode
)
4710 i
.disp_encoding
= disp_encoding_8bit
;
4714 i
.disp_encoding
= disp_encoding_32bit
;
4718 i
.dir_encoding
= dir_encoding_load
;
4722 i
.dir_encoding
= dir_encoding_store
;
4726 i
.vec_encoding
= vex_encoding_vex2
;
4730 i
.vec_encoding
= vex_encoding_vex3
;
4734 i
.vec_encoding
= vex_encoding_evex
;
4738 i
.rex_encoding
= TRUE
;
4742 i
.no_optimize
= TRUE
;
4750 /* Add prefix, checking for repeated prefixes. */
4751 switch (add_prefix (current_templates
->start
->base_opcode
))
4756 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4757 i
.notrack_prefix
= current_templates
->start
->name
;
4760 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4761 i
.hle_prefix
= current_templates
->start
->name
;
4762 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4763 i
.bnd_prefix
= current_templates
->start
->name
;
4765 i
.rep_prefix
= current_templates
->start
->name
;
4771 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4778 if (!current_templates
)
4780 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4781 Check if we should swap operand or force 32bit displacement in
4783 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4784 i
.dir_encoding
= dir_encoding_swap
;
4785 else if (mnem_p
- 3 == dot_p
4788 i
.disp_encoding
= disp_encoding_8bit
;
4789 else if (mnem_p
- 4 == dot_p
4793 i
.disp_encoding
= disp_encoding_32bit
;
4798 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4801 if (!current_templates
)
4804 if (mnem_p
> mnemonic
)
4806 /* See if we can get a match by trimming off a suffix. */
4809 case WORD_MNEM_SUFFIX
:
4810 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4811 i
.suffix
= SHORT_MNEM_SUFFIX
;
4814 case BYTE_MNEM_SUFFIX
:
4815 case QWORD_MNEM_SUFFIX
:
4816 i
.suffix
= mnem_p
[-1];
4818 current_templates
= (const templates
*) hash_find (op_hash
,
4821 case SHORT_MNEM_SUFFIX
:
4822 case LONG_MNEM_SUFFIX
:
4825 i
.suffix
= mnem_p
[-1];
4827 current_templates
= (const templates
*) hash_find (op_hash
,
4836 if (intel_float_operand (mnemonic
) == 1)
4837 i
.suffix
= SHORT_MNEM_SUFFIX
;
4839 i
.suffix
= LONG_MNEM_SUFFIX
;
4841 current_templates
= (const templates
*) hash_find (op_hash
,
4848 if (!current_templates
)
4850 as_bad (_("no such instruction: `%s'"), token_start
);
4855 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4856 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4858 /* Check for a branch hint. We allow ",pt" and ",pn" for
4859 predict taken and predict not taken respectively.
4860 I'm not sure that branch hints actually do anything on loop
4861 and jcxz insns (JumpByte) for current Pentium4 chips. They
4862 may work in the future and it doesn't hurt to accept them
4864 if (l
[0] == ',' && l
[1] == 'p')
4868 if (!add_prefix (DS_PREFIX_OPCODE
))
4872 else if (l
[2] == 'n')
4874 if (!add_prefix (CS_PREFIX_OPCODE
))
4880 /* Any other comma loses. */
4883 as_bad (_("invalid character %s in mnemonic"),
4884 output_invalid (*l
));
4888 /* Check if instruction is supported on specified architecture. */
4890 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4892 supported
|= cpu_flags_match (t
);
4893 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4895 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4896 as_warn (_("use .code16 to ensure correct addressing mode"));
4902 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4903 as_bad (flag_code
== CODE_64BIT
4904 ? _("`%s' is not supported in 64-bit mode")
4905 : _("`%s' is only supported in 64-bit mode"),
4906 current_templates
->start
->name
);
4908 as_bad (_("`%s' is not supported on `%s%s'"),
4909 current_templates
->start
->name
,
4910 cpu_arch_name
? cpu_arch_name
: default_arch
,
4911 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4917 parse_operands (char *l
, const char *mnemonic
)
4921 /* 1 if operand is pending after ','. */
4922 unsigned int expecting_operand
= 0;
4924 /* Non-zero if operand parens not balanced. */
4925 unsigned int paren_not_balanced
;
4927 while (*l
!= END_OF_INSN
)
4929 /* Skip optional white space before operand. */
4930 if (is_space_char (*l
))
4932 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4934 as_bad (_("invalid character %s before operand %d"),
4935 output_invalid (*l
),
4939 token_start
= l
; /* After white space. */
4940 paren_not_balanced
= 0;
4941 while (paren_not_balanced
|| *l
!= ',')
4943 if (*l
== END_OF_INSN
)
4945 if (paren_not_balanced
)
4948 as_bad (_("unbalanced parenthesis in operand %d."),
4951 as_bad (_("unbalanced brackets in operand %d."),
4956 break; /* we are done */
4958 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4960 as_bad (_("invalid character %s in operand %d"),
4961 output_invalid (*l
),
4968 ++paren_not_balanced
;
4970 --paren_not_balanced
;
4975 ++paren_not_balanced
;
4977 --paren_not_balanced
;
4981 if (l
!= token_start
)
4982 { /* Yes, we've read in another operand. */
4983 unsigned int operand_ok
;
4984 this_operand
= i
.operands
++;
4985 if (i
.operands
> MAX_OPERANDS
)
4987 as_bad (_("spurious operands; (%d operands/instruction max)"),
4991 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4992 /* Now parse operand adding info to 'i' as we go along. */
4993 END_STRING_AND_SAVE (l
);
4995 if (i
.mem_operands
> 1)
4997 as_bad (_("too many memory references for `%s'"),
5004 i386_intel_operand (token_start
,
5005 intel_float_operand (mnemonic
));
5007 operand_ok
= i386_att_operand (token_start
);
5009 RESTORE_END_STRING (l
);
5015 if (expecting_operand
)
5017 expecting_operand_after_comma
:
5018 as_bad (_("expecting operand after ','; got nothing"));
5023 as_bad (_("expecting operand before ','; got nothing"));
5028 /* Now *l must be either ',' or END_OF_INSN. */
5031 if (*++l
== END_OF_INSN
)
5033 /* Just skip it, if it's \n complain. */
5034 goto expecting_operand_after_comma
;
5036 expecting_operand
= 1;
5043 swap_2_operands (int xchg1
, int xchg2
)
5045 union i386_op temp_op
;
5046 i386_operand_type temp_type
;
5047 unsigned int temp_flags
;
5048 enum bfd_reloc_code_real temp_reloc
;
5050 temp_type
= i
.types
[xchg2
];
5051 i
.types
[xchg2
] = i
.types
[xchg1
];
5052 i
.types
[xchg1
] = temp_type
;
5054 temp_flags
= i
.flags
[xchg2
];
5055 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5056 i
.flags
[xchg1
] = temp_flags
;
5058 temp_op
= i
.op
[xchg2
];
5059 i
.op
[xchg2
] = i
.op
[xchg1
];
5060 i
.op
[xchg1
] = temp_op
;
5062 temp_reloc
= i
.reloc
[xchg2
];
5063 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5064 i
.reloc
[xchg1
] = temp_reloc
;
5068 if (i
.mask
->operand
== xchg1
)
5069 i
.mask
->operand
= xchg2
;
5070 else if (i
.mask
->operand
== xchg2
)
5071 i
.mask
->operand
= xchg1
;
5075 if (i
.broadcast
->operand
== xchg1
)
5076 i
.broadcast
->operand
= xchg2
;
5077 else if (i
.broadcast
->operand
== xchg2
)
5078 i
.broadcast
->operand
= xchg1
;
5082 if (i
.rounding
->operand
== xchg1
)
5083 i
.rounding
->operand
= xchg2
;
5084 else if (i
.rounding
->operand
== xchg2
)
5085 i
.rounding
->operand
= xchg1
;
5090 swap_operands (void)
5096 swap_2_operands (1, i
.operands
- 2);
5100 swap_2_operands (0, i
.operands
- 1);
5106 if (i
.mem_operands
== 2)
5108 const seg_entry
*temp_seg
;
5109 temp_seg
= i
.seg
[0];
5110 i
.seg
[0] = i
.seg
[1];
5111 i
.seg
[1] = temp_seg
;
5115 /* Try to ensure constant immediates are represented in the smallest
5120 char guess_suffix
= 0;
5124 guess_suffix
= i
.suffix
;
5125 else if (i
.reg_operands
)
5127 /* Figure out a suffix from the last register operand specified.
5128 We can't do this properly yet, i.e. excluding special register
5129 instances, but the following works for instructions with
5130 immediates. In any case, we can't set i.suffix yet. */
5131 for (op
= i
.operands
; --op
>= 0;)
5132 if (i
.types
[op
].bitfield
.class != Reg
)
5134 else if (i
.types
[op
].bitfield
.byte
)
5136 guess_suffix
= BYTE_MNEM_SUFFIX
;
5139 else if (i
.types
[op
].bitfield
.word
)
5141 guess_suffix
= WORD_MNEM_SUFFIX
;
5144 else if (i
.types
[op
].bitfield
.dword
)
5146 guess_suffix
= LONG_MNEM_SUFFIX
;
5149 else if (i
.types
[op
].bitfield
.qword
)
5151 guess_suffix
= QWORD_MNEM_SUFFIX
;
5155 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5156 guess_suffix
= WORD_MNEM_SUFFIX
;
5158 for (op
= i
.operands
; --op
>= 0;)
5159 if (operand_type_check (i
.types
[op
], imm
))
5161 switch (i
.op
[op
].imms
->X_op
)
5164 /* If a suffix is given, this operand may be shortened. */
5165 switch (guess_suffix
)
5167 case LONG_MNEM_SUFFIX
:
5168 i
.types
[op
].bitfield
.imm32
= 1;
5169 i
.types
[op
].bitfield
.imm64
= 1;
5171 case WORD_MNEM_SUFFIX
:
5172 i
.types
[op
].bitfield
.imm16
= 1;
5173 i
.types
[op
].bitfield
.imm32
= 1;
5174 i
.types
[op
].bitfield
.imm32s
= 1;
5175 i
.types
[op
].bitfield
.imm64
= 1;
5177 case BYTE_MNEM_SUFFIX
:
5178 i
.types
[op
].bitfield
.imm8
= 1;
5179 i
.types
[op
].bitfield
.imm8s
= 1;
5180 i
.types
[op
].bitfield
.imm16
= 1;
5181 i
.types
[op
].bitfield
.imm32
= 1;
5182 i
.types
[op
].bitfield
.imm32s
= 1;
5183 i
.types
[op
].bitfield
.imm64
= 1;
5187 /* If this operand is at most 16 bits, convert it
5188 to a signed 16 bit number before trying to see
5189 whether it will fit in an even smaller size.
5190 This allows a 16-bit operand such as $0xffe0 to
5191 be recognised as within Imm8S range. */
5192 if ((i
.types
[op
].bitfield
.imm16
)
5193 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5195 i
.op
[op
].imms
->X_add_number
=
5196 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5199 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5200 if ((i
.types
[op
].bitfield
.imm32
)
5201 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5204 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5205 ^ ((offsetT
) 1 << 31))
5206 - ((offsetT
) 1 << 31));
5210 = operand_type_or (i
.types
[op
],
5211 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5213 /* We must avoid matching of Imm32 templates when 64bit
5214 only immediate is available. */
5215 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5216 i
.types
[op
].bitfield
.imm32
= 0;
5223 /* Symbols and expressions. */
5225 /* Convert symbolic operand to proper sizes for matching, but don't
5226 prevent matching a set of insns that only supports sizes other
5227 than those matching the insn suffix. */
5229 i386_operand_type mask
, allowed
;
5230 const insn_template
*t
;
5232 operand_type_set (&mask
, 0);
5233 operand_type_set (&allowed
, 0);
5235 for (t
= current_templates
->start
;
5236 t
< current_templates
->end
;
5239 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5240 allowed
= operand_type_and (allowed
, anyimm
);
5242 switch (guess_suffix
)
5244 case QWORD_MNEM_SUFFIX
:
5245 mask
.bitfield
.imm64
= 1;
5246 mask
.bitfield
.imm32s
= 1;
5248 case LONG_MNEM_SUFFIX
:
5249 mask
.bitfield
.imm32
= 1;
5251 case WORD_MNEM_SUFFIX
:
5252 mask
.bitfield
.imm16
= 1;
5254 case BYTE_MNEM_SUFFIX
:
5255 mask
.bitfield
.imm8
= 1;
5260 allowed
= operand_type_and (mask
, allowed
);
5261 if (!operand_type_all_zero (&allowed
))
5262 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5269 /* Try to use the smallest displacement type too. */
5271 optimize_disp (void)
5275 for (op
= i
.operands
; --op
>= 0;)
5276 if (operand_type_check (i
.types
[op
], disp
))
5278 if (i
.op
[op
].disps
->X_op
== O_constant
)
5280 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5282 if (i
.types
[op
].bitfield
.disp16
5283 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5285 /* If this operand is at most 16 bits, convert
5286 to a signed 16 bit number and don't use 64bit
5288 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5289 i
.types
[op
].bitfield
.disp64
= 0;
5292 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5293 if (i
.types
[op
].bitfield
.disp32
5294 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5296 /* If this operand is at most 32 bits, convert
5297 to a signed 32 bit number and don't use 64bit
5299 op_disp
&= (((offsetT
) 2 << 31) - 1);
5300 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5301 i
.types
[op
].bitfield
.disp64
= 0;
5304 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5306 i
.types
[op
].bitfield
.disp8
= 0;
5307 i
.types
[op
].bitfield
.disp16
= 0;
5308 i
.types
[op
].bitfield
.disp32
= 0;
5309 i
.types
[op
].bitfield
.disp32s
= 0;
5310 i
.types
[op
].bitfield
.disp64
= 0;
5314 else if (flag_code
== CODE_64BIT
)
5316 if (fits_in_signed_long (op_disp
))
5318 i
.types
[op
].bitfield
.disp64
= 0;
5319 i
.types
[op
].bitfield
.disp32s
= 1;
5321 if (i
.prefix
[ADDR_PREFIX
]
5322 && fits_in_unsigned_long (op_disp
))
5323 i
.types
[op
].bitfield
.disp32
= 1;
5325 if ((i
.types
[op
].bitfield
.disp32
5326 || i
.types
[op
].bitfield
.disp32s
5327 || i
.types
[op
].bitfield
.disp16
)
5328 && fits_in_disp8 (op_disp
))
5329 i
.types
[op
].bitfield
.disp8
= 1;
5331 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5332 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5334 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5335 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5336 i
.types
[op
].bitfield
.disp8
= 0;
5337 i
.types
[op
].bitfield
.disp16
= 0;
5338 i
.types
[op
].bitfield
.disp32
= 0;
5339 i
.types
[op
].bitfield
.disp32s
= 0;
5340 i
.types
[op
].bitfield
.disp64
= 0;
5343 /* We only support 64bit displacement on constants. */
5344 i
.types
[op
].bitfield
.disp64
= 0;
5348 /* Return 1 if there is a match in broadcast bytes between operand
5349 GIVEN and instruction template T. */
5352 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5354 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5355 && i
.types
[given
].bitfield
.byte
)
5356 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5357 && i
.types
[given
].bitfield
.word
)
5358 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5359 && i
.types
[given
].bitfield
.dword
)
5360 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5361 && i
.types
[given
].bitfield
.qword
));
5364 /* Check if operands are valid for the instruction. */
5367 check_VecOperands (const insn_template
*t
)
5371 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5373 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5374 any one operand are implicity requiring AVX512VL support if the actual
5375 operand size is YMMword or XMMword. Since this function runs after
5376 template matching, there's no need to check for YMMword/XMMword in
5378 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5379 if (!cpu_flags_all_zero (&cpu
)
5380 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5381 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5383 for (op
= 0; op
< t
->operands
; ++op
)
5385 if (t
->operand_types
[op
].bitfield
.zmmword
5386 && (i
.types
[op
].bitfield
.ymmword
5387 || i
.types
[op
].bitfield
.xmmword
))
5389 i
.error
= unsupported
;
5395 /* Without VSIB byte, we can't have a vector register for index. */
5396 if (!t
->opcode_modifier
.vecsib
5398 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5399 || i
.index_reg
->reg_type
.bitfield
.ymmword
5400 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5402 i
.error
= unsupported_vector_index_register
;
5406 /* Check if default mask is allowed. */
5407 if (t
->opcode_modifier
.nodefmask
5408 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5410 i
.error
= no_default_mask
;
5414 /* For VSIB byte, we need a vector register for index, and all vector
5415 registers must be distinct. */
5416 if (t
->opcode_modifier
.vecsib
)
5419 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5420 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5421 || (t
->opcode_modifier
.vecsib
== VecSIB256
5422 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5423 || (t
->opcode_modifier
.vecsib
== VecSIB512
5424 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5426 i
.error
= invalid_vsib_address
;
5430 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5431 if (i
.reg_operands
== 2 && !i
.mask
)
5433 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5434 gas_assert (i
.types
[0].bitfield
.xmmword
5435 || i
.types
[0].bitfield
.ymmword
);
5436 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5437 gas_assert (i
.types
[2].bitfield
.xmmword
5438 || i
.types
[2].bitfield
.ymmword
);
5439 if (operand_check
== check_none
)
5441 if (register_number (i
.op
[0].regs
)
5442 != register_number (i
.index_reg
)
5443 && register_number (i
.op
[2].regs
)
5444 != register_number (i
.index_reg
)
5445 && register_number (i
.op
[0].regs
)
5446 != register_number (i
.op
[2].regs
))
5448 if (operand_check
== check_error
)
5450 i
.error
= invalid_vector_register_set
;
5453 as_warn (_("mask, index, and destination registers should be distinct"));
5455 else if (i
.reg_operands
== 1 && i
.mask
)
5457 if (i
.types
[1].bitfield
.class == RegSIMD
5458 && (i
.types
[1].bitfield
.xmmword
5459 || i
.types
[1].bitfield
.ymmword
5460 || i
.types
[1].bitfield
.zmmword
)
5461 && (register_number (i
.op
[1].regs
)
5462 == register_number (i
.index_reg
)))
5464 if (operand_check
== check_error
)
5466 i
.error
= invalid_vector_register_set
;
5469 if (operand_check
!= check_none
)
5470 as_warn (_("index and destination registers should be distinct"));
5475 /* Check if broadcast is supported by the instruction and is applied
5476 to the memory operand. */
5479 i386_operand_type type
, overlap
;
5481 /* Check if specified broadcast is supported in this instruction,
5482 and its broadcast bytes match the memory operand. */
5483 op
= i
.broadcast
->operand
;
5484 if (!t
->opcode_modifier
.broadcast
5485 || !(i
.flags
[op
] & Operand_Mem
)
5486 || (!i
.types
[op
].bitfield
.unspecified
5487 && !match_broadcast_size (t
, op
)))
5490 i
.error
= unsupported_broadcast
;
5494 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5495 * i
.broadcast
->type
);
5496 operand_type_set (&type
, 0);
5497 switch (i
.broadcast
->bytes
)
5500 type
.bitfield
.word
= 1;
5503 type
.bitfield
.dword
= 1;
5506 type
.bitfield
.qword
= 1;
5509 type
.bitfield
.xmmword
= 1;
5512 type
.bitfield
.ymmword
= 1;
5515 type
.bitfield
.zmmword
= 1;
5521 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5522 if (operand_type_all_zero (&overlap
))
5525 if (t
->opcode_modifier
.checkregsize
)
5529 type
.bitfield
.baseindex
= 1;
5530 for (j
= 0; j
< i
.operands
; ++j
)
5533 && !operand_type_register_match(i
.types
[j
],
5534 t
->operand_types
[j
],
5536 t
->operand_types
[op
]))
5541 /* If broadcast is supported in this instruction, we need to check if
5542 operand of one-element size isn't specified without broadcast. */
5543 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5545 /* Find memory operand. */
5546 for (op
= 0; op
< i
.operands
; op
++)
5547 if (i
.flags
[op
] & Operand_Mem
)
5549 gas_assert (op
< i
.operands
);
5550 /* Check size of the memory operand. */
5551 if (match_broadcast_size (t
, op
))
5553 i
.error
= broadcast_needed
;
5558 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5560 /* Check if requested masking is supported. */
5563 switch (t
->opcode_modifier
.masking
)
5567 case MERGING_MASKING
:
5568 if (i
.mask
->zeroing
)
5571 i
.error
= unsupported_masking
;
5575 case DYNAMIC_MASKING
:
5576 /* Memory destinations allow only merging masking. */
5577 if (i
.mask
->zeroing
&& i
.mem_operands
)
5579 /* Find memory operand. */
5580 for (op
= 0; op
< i
.operands
; op
++)
5581 if (i
.flags
[op
] & Operand_Mem
)
5583 gas_assert (op
< i
.operands
);
5584 if (op
== i
.operands
- 1)
5586 i
.error
= unsupported_masking
;
5596 /* Check if masking is applied to dest operand. */
5597 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5599 i
.error
= mask_not_on_destination
;
5606 if (!t
->opcode_modifier
.sae
5607 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5609 i
.error
= unsupported_rc_sae
;
5612 /* If the instruction has several immediate operands and one of
5613 them is rounding, the rounding operand should be the last
5614 immediate operand. */
5615 if (i
.imm_operands
> 1
5616 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5618 i
.error
= rc_sae_operand_not_last_imm
;
5623 /* Check vector Disp8 operand. */
5624 if (t
->opcode_modifier
.disp8memshift
5625 && i
.disp_encoding
!= disp_encoding_32bit
)
5628 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5629 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5630 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5633 const i386_operand_type
*type
= NULL
;
5636 for (op
= 0; op
< i
.operands
; op
++)
5637 if (i
.flags
[op
] & Operand_Mem
)
5639 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5640 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5641 else if (t
->operand_types
[op
].bitfield
.xmmword
5642 + t
->operand_types
[op
].bitfield
.ymmword
5643 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5644 type
= &t
->operand_types
[op
];
5645 else if (!i
.types
[op
].bitfield
.unspecified
)
5646 type
= &i
.types
[op
];
5648 else if (i
.types
[op
].bitfield
.class == RegSIMD
5649 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5651 if (i
.types
[op
].bitfield
.zmmword
)
5653 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5655 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5661 if (type
->bitfield
.zmmword
)
5663 else if (type
->bitfield
.ymmword
)
5665 else if (type
->bitfield
.xmmword
)
5669 /* For the check in fits_in_disp8(). */
5670 if (i
.memshift
== 0)
5674 for (op
= 0; op
< i
.operands
; op
++)
5675 if (operand_type_check (i
.types
[op
], disp
)
5676 && i
.op
[op
].disps
->X_op
== O_constant
)
5678 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5680 i
.types
[op
].bitfield
.disp8
= 1;
5683 i
.types
[op
].bitfield
.disp8
= 0;
5692 /* Check if operands are valid for the instruction. Update VEX
5696 VEX_check_operands (const insn_template
*t
)
5698 if (i
.vec_encoding
== vex_encoding_evex
)
5700 /* This instruction must be encoded with EVEX prefix. */
5701 if (!is_evex_encoding (t
))
5703 i
.error
= unsupported
;
5709 if (!t
->opcode_modifier
.vex
)
5711 /* This instruction template doesn't have VEX prefix. */
5712 if (i
.vec_encoding
!= vex_encoding_default
)
5714 i
.error
= unsupported
;
5720 /* Check the special Imm4 cases; must be the first operand. */
5721 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5723 if (i
.op
[0].imms
->X_op
!= O_constant
5724 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5730 /* Turn off Imm<N> so that update_imm won't complain. */
5731 operand_type_set (&i
.types
[0], 0);
5737 static const insn_template
*
5738 match_template (char mnem_suffix
)
5740 /* Points to template once we've found it. */
5741 const insn_template
*t
;
5742 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5743 i386_operand_type overlap4
;
5744 unsigned int found_reverse_match
;
5745 i386_opcode_modifier suffix_check
;
5746 i386_operand_type operand_types
[MAX_OPERANDS
];
5747 int addr_prefix_disp
;
5749 unsigned int found_cpu_match
, size_match
;
5750 unsigned int check_register
;
5751 enum i386_error specific_error
= 0;
5753 #if MAX_OPERANDS != 5
5754 # error "MAX_OPERANDS must be 5."
5757 found_reverse_match
= 0;
5758 addr_prefix_disp
= -1;
5760 /* Prepare for mnemonic suffix check. */
5761 memset (&suffix_check
, 0, sizeof (suffix_check
));
5762 switch (mnem_suffix
)
5764 case BYTE_MNEM_SUFFIX
:
5765 suffix_check
.no_bsuf
= 1;
5767 case WORD_MNEM_SUFFIX
:
5768 suffix_check
.no_wsuf
= 1;
5770 case SHORT_MNEM_SUFFIX
:
5771 suffix_check
.no_ssuf
= 1;
5773 case LONG_MNEM_SUFFIX
:
5774 suffix_check
.no_lsuf
= 1;
5776 case QWORD_MNEM_SUFFIX
:
5777 suffix_check
.no_qsuf
= 1;
5780 /* NB: In Intel syntax, normally we can check for memory operand
5781 size when there is no mnemonic suffix. But jmp and call have
5782 2 different encodings with Dword memory operand size, one with
5783 No_ldSuf and the other without. i.suffix is set to
5784 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5785 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5786 suffix_check
.no_ldsuf
= 1;
5789 /* Must have right number of operands. */
5790 i
.error
= number_of_operands_mismatch
;
5792 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5794 addr_prefix_disp
= -1;
5795 found_reverse_match
= 0;
5797 if (i
.operands
!= t
->operands
)
5800 /* Check processor support. */
5801 i
.error
= unsupported
;
5802 found_cpu_match
= (cpu_flags_match (t
)
5803 == CPU_FLAGS_PERFECT_MATCH
);
5804 if (!found_cpu_match
)
5807 /* Check AT&T mnemonic. */
5808 i
.error
= unsupported_with_intel_mnemonic
;
5809 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5812 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5813 i
.error
= unsupported_syntax
;
5814 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5815 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5816 || (intel64
&& t
->opcode_modifier
.amd64
)
5817 || (!intel64
&& t
->opcode_modifier
.intel64
))
5820 /* Check the suffix. */
5821 i
.error
= invalid_instruction_suffix
;
5822 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5823 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5824 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5825 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5826 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5827 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5830 size_match
= operand_size_match (t
);
5834 /* This is intentionally not
5836 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5838 as the case of a missing * on the operand is accepted (perhaps with
5839 a warning, issued further down). */
5840 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5842 i
.error
= operand_type_mismatch
;
5846 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5847 operand_types
[j
] = t
->operand_types
[j
];
5849 /* In general, don't allow 64-bit operands in 32-bit mode. */
5850 if (i
.suffix
== QWORD_MNEM_SUFFIX
5851 && flag_code
!= CODE_64BIT
5853 ? (!t
->opcode_modifier
.ignoresize
5854 && !t
->opcode_modifier
.broadcast
5855 && !intel_float_operand (t
->name
))
5856 : intel_float_operand (t
->name
) != 2)
5857 && ((operand_types
[0].bitfield
.class != RegMMX
5858 && operand_types
[0].bitfield
.class != RegSIMD
)
5859 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5860 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5861 && (t
->base_opcode
!= 0x0fc7
5862 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5865 /* In general, don't allow 32-bit operands on pre-386. */
5866 else if (i
.suffix
== LONG_MNEM_SUFFIX
5867 && !cpu_arch_flags
.bitfield
.cpui386
5869 ? (!t
->opcode_modifier
.ignoresize
5870 && !intel_float_operand (t
->name
))
5871 : intel_float_operand (t
->name
) != 2)
5872 && ((operand_types
[0].bitfield
.class != RegMMX
5873 && operand_types
[0].bitfield
.class != RegSIMD
)
5874 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5875 && operand_types
[t
->operands
> 1].bitfield
.class
5879 /* Do not verify operands when there are none. */
5883 /* We've found a match; break out of loop. */
5887 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5888 into Disp32/Disp16/Disp32 operand. */
5889 if (i
.prefix
[ADDR_PREFIX
] != 0)
5891 /* There should be only one Disp operand. */
5895 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5897 if (operand_types
[j
].bitfield
.disp16
)
5899 addr_prefix_disp
= j
;
5900 operand_types
[j
].bitfield
.disp32
= 1;
5901 operand_types
[j
].bitfield
.disp16
= 0;
5907 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5909 if (operand_types
[j
].bitfield
.disp32
)
5911 addr_prefix_disp
= j
;
5912 operand_types
[j
].bitfield
.disp32
= 0;
5913 operand_types
[j
].bitfield
.disp16
= 1;
5919 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5921 if (operand_types
[j
].bitfield
.disp64
)
5923 addr_prefix_disp
= j
;
5924 operand_types
[j
].bitfield
.disp64
= 0;
5925 operand_types
[j
].bitfield
.disp32
= 1;
5933 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5934 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5937 /* We check register size if needed. */
5938 if (t
->opcode_modifier
.checkregsize
)
5940 check_register
= (1 << t
->operands
) - 1;
5942 check_register
&= ~(1 << i
.broadcast
->operand
);
5947 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5948 switch (t
->operands
)
5951 if (!operand_type_match (overlap0
, i
.types
[0]))
5955 /* xchg %eax, %eax is a special case. It is an alias for nop
5956 only in 32bit mode and we can use opcode 0x90. In 64bit
5957 mode, we can't use 0x90 for xchg %eax, %eax since it should
5958 zero-extend %eax to %rax. */
5959 if (flag_code
== CODE_64BIT
5960 && t
->base_opcode
== 0x90
5961 && i
.types
[0].bitfield
.instance
== Accum
5962 && i
.types
[0].bitfield
.dword
5963 && i
.types
[1].bitfield
.instance
== Accum
5964 && i
.types
[1].bitfield
.dword
)
5966 /* xrelease mov %eax, <disp> is another special case. It must not
5967 match the accumulator-only encoding of mov. */
5968 if (flag_code
!= CODE_64BIT
5970 && t
->base_opcode
== 0xa0
5971 && i
.types
[0].bitfield
.instance
== Accum
5972 && (i
.flags
[1] & Operand_Mem
))
5977 if (!(size_match
& MATCH_STRAIGHT
))
5979 /* Reverse direction of operands if swapping is possible in the first
5980 place (operands need to be symmetric) and
5981 - the load form is requested, and the template is a store form,
5982 - the store form is requested, and the template is a load form,
5983 - the non-default (swapped) form is requested. */
5984 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5985 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5986 && !operand_type_all_zero (&overlap1
))
5987 switch (i
.dir_encoding
)
5989 case dir_encoding_load
:
5990 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5991 || t
->opcode_modifier
.regmem
)
5995 case dir_encoding_store
:
5996 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5997 && !t
->opcode_modifier
.regmem
)
6001 case dir_encoding_swap
:
6004 case dir_encoding_default
:
6007 /* If we want store form, we skip the current load. */
6008 if ((i
.dir_encoding
== dir_encoding_store
6009 || i
.dir_encoding
== dir_encoding_swap
)
6010 && i
.mem_operands
== 0
6011 && t
->opcode_modifier
.load
)
6016 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6017 if (!operand_type_match (overlap0
, i
.types
[0])
6018 || !operand_type_match (overlap1
, i
.types
[1])
6019 || ((check_register
& 3) == 3
6020 && !operand_type_register_match (i
.types
[0],
6025 /* Check if other direction is valid ... */
6026 if (!t
->opcode_modifier
.d
)
6030 if (!(size_match
& MATCH_REVERSE
))
6032 /* Try reversing direction of operands. */
6033 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6034 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6035 if (!operand_type_match (overlap0
, i
.types
[0])
6036 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6038 && !operand_type_register_match (i
.types
[0],
6039 operand_types
[i
.operands
- 1],
6040 i
.types
[i
.operands
- 1],
6043 /* Does not match either direction. */
6046 /* found_reverse_match holds which of D or FloatR
6048 if (!t
->opcode_modifier
.d
)
6049 found_reverse_match
= 0;
6050 else if (operand_types
[0].bitfield
.tbyte
)
6051 found_reverse_match
= Opcode_FloatD
;
6052 else if (operand_types
[0].bitfield
.xmmword
6053 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6054 || operand_types
[0].bitfield
.class == RegMMX
6055 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6056 || is_any_vex_encoding(t
))
6057 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6058 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6060 found_reverse_match
= Opcode_D
;
6061 if (t
->opcode_modifier
.floatr
)
6062 found_reverse_match
|= Opcode_FloatR
;
6066 /* Found a forward 2 operand match here. */
6067 switch (t
->operands
)
6070 overlap4
= operand_type_and (i
.types
[4],
6074 overlap3
= operand_type_and (i
.types
[3],
6078 overlap2
= operand_type_and (i
.types
[2],
6083 switch (t
->operands
)
6086 if (!operand_type_match (overlap4
, i
.types
[4])
6087 || !operand_type_register_match (i
.types
[3],
6094 if (!operand_type_match (overlap3
, i
.types
[3])
6095 || ((check_register
& 0xa) == 0xa
6096 && !operand_type_register_match (i
.types
[1],
6100 || ((check_register
& 0xc) == 0xc
6101 && !operand_type_register_match (i
.types
[2],
6108 /* Here we make use of the fact that there are no
6109 reverse match 3 operand instructions. */
6110 if (!operand_type_match (overlap2
, i
.types
[2])
6111 || ((check_register
& 5) == 5
6112 && !operand_type_register_match (i
.types
[0],
6116 || ((check_register
& 6) == 6
6117 && !operand_type_register_match (i
.types
[1],
6125 /* Found either forward/reverse 2, 3 or 4 operand match here:
6126 slip through to break. */
6128 if (!found_cpu_match
)
6131 /* Check if vector and VEX operands are valid. */
6132 if (check_VecOperands (t
) || VEX_check_operands (t
))
6134 specific_error
= i
.error
;
6138 /* We've found a match; break out of loop. */
6142 if (t
== current_templates
->end
)
6144 /* We found no match. */
6145 const char *err_msg
;
6146 switch (specific_error
? specific_error
: i
.error
)
6150 case operand_size_mismatch
:
6151 err_msg
= _("operand size mismatch");
6153 case operand_type_mismatch
:
6154 err_msg
= _("operand type mismatch");
6156 case register_type_mismatch
:
6157 err_msg
= _("register type mismatch");
6159 case number_of_operands_mismatch
:
6160 err_msg
= _("number of operands mismatch");
6162 case invalid_instruction_suffix
:
6163 err_msg
= _("invalid instruction suffix");
6166 err_msg
= _("constant doesn't fit in 4 bits");
6168 case unsupported_with_intel_mnemonic
:
6169 err_msg
= _("unsupported with Intel mnemonic");
6171 case unsupported_syntax
:
6172 err_msg
= _("unsupported syntax");
6175 as_bad (_("unsupported instruction `%s'"),
6176 current_templates
->start
->name
);
6178 case invalid_vsib_address
:
6179 err_msg
= _("invalid VSIB address");
6181 case invalid_vector_register_set
:
6182 err_msg
= _("mask, index, and destination registers must be distinct");
6184 case unsupported_vector_index_register
:
6185 err_msg
= _("unsupported vector index register");
6187 case unsupported_broadcast
:
6188 err_msg
= _("unsupported broadcast");
6190 case broadcast_needed
:
6191 err_msg
= _("broadcast is needed for operand of such type");
6193 case unsupported_masking
:
6194 err_msg
= _("unsupported masking");
6196 case mask_not_on_destination
:
6197 err_msg
= _("mask not on destination operand");
6199 case no_default_mask
:
6200 err_msg
= _("default mask isn't allowed");
6202 case unsupported_rc_sae
:
6203 err_msg
= _("unsupported static rounding/sae");
6205 case rc_sae_operand_not_last_imm
:
6207 err_msg
= _("RC/SAE operand must precede immediate operands");
6209 err_msg
= _("RC/SAE operand must follow immediate operands");
6211 case invalid_register_operand
:
6212 err_msg
= _("invalid register operand");
6215 as_bad (_("%s for `%s'"), err_msg
,
6216 current_templates
->start
->name
);
6220 if (!quiet_warnings
)
6223 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6224 as_warn (_("indirect %s without `*'"), t
->name
);
6226 if (t
->opcode_modifier
.isprefix
6227 && t
->opcode_modifier
.ignoresize
)
6229 /* Warn them that a data or address size prefix doesn't
6230 affect assembly of the next line of code. */
6231 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6235 /* Copy the template we found. */
6238 if (addr_prefix_disp
!= -1)
6239 i
.tm
.operand_types
[addr_prefix_disp
]
6240 = operand_types
[addr_prefix_disp
];
6242 if (found_reverse_match
)
6244 /* If we found a reverse match we must alter the opcode direction
6245 bit and clear/flip the regmem modifier one. found_reverse_match
6246 holds bits to change (different for int & float insns). */
6248 i
.tm
.base_opcode
^= found_reverse_match
;
6250 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6251 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6253 /* Certain SIMD insns have their load forms specified in the opcode
6254 table, and hence we need to _set_ RegMem instead of clearing it.
6255 We need to avoid setting the bit though on insns like KMOVW. */
6256 i
.tm
.opcode_modifier
.regmem
6257 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6258 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6259 && !i
.tm
.opcode_modifier
.regmem
;
6268 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6269 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6271 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6273 as_bad (_("`%s' operand %u must use `%ses' segment"),
6275 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6280 /* There's only ever one segment override allowed per instruction.
6281 This instruction possibly has a legal segment override on the
6282 second operand, so copy the segment to where non-string
6283 instructions store it, allowing common code. */
6284 i
.seg
[op
] = i
.seg
[1];
6290 process_suffix (void)
6292 /* If matched instruction specifies an explicit instruction mnemonic
6294 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6295 i
.suffix
= WORD_MNEM_SUFFIX
;
6296 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6297 i
.suffix
= LONG_MNEM_SUFFIX
;
6298 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6299 i
.suffix
= QWORD_MNEM_SUFFIX
;
6300 else if (i
.reg_operands
6301 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6303 /* If there's no instruction mnemonic suffix we try to invent one
6304 based on GPR operands. */
6307 /* We take i.suffix from the last register operand specified,
6308 Destination register type is more significant than source
6309 register type. crc32 in SSE4.2 prefers source register
6311 if (i
.tm
.base_opcode
== 0xf20f38f0
6312 && i
.types
[0].bitfield
.class == Reg
)
6314 if (i
.types
[0].bitfield
.byte
)
6315 i
.suffix
= BYTE_MNEM_SUFFIX
;
6316 else if (i
.types
[0].bitfield
.word
)
6317 i
.suffix
= WORD_MNEM_SUFFIX
;
6318 else if (i
.types
[0].bitfield
.dword
)
6319 i
.suffix
= LONG_MNEM_SUFFIX
;
6320 else if (i
.types
[0].bitfield
.qword
)
6321 i
.suffix
= QWORD_MNEM_SUFFIX
;
6328 if (i
.tm
.base_opcode
== 0xf20f38f0)
6330 /* We have to know the operand size for crc32. */
6331 as_bad (_("ambiguous memory operand size for `%s`"),
6336 for (op
= i
.operands
; --op
>= 0;)
6337 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6338 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6340 if (i
.types
[op
].bitfield
.class != Reg
)
6342 if (i
.types
[op
].bitfield
.byte
)
6343 i
.suffix
= BYTE_MNEM_SUFFIX
;
6344 else if (i
.types
[op
].bitfield
.word
)
6345 i
.suffix
= WORD_MNEM_SUFFIX
;
6346 else if (i
.types
[op
].bitfield
.dword
)
6347 i
.suffix
= LONG_MNEM_SUFFIX
;
6348 else if (i
.types
[op
].bitfield
.qword
)
6349 i
.suffix
= QWORD_MNEM_SUFFIX
;
6356 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6359 && i
.tm
.opcode_modifier
.ignoresize
6360 && i
.tm
.opcode_modifier
.no_bsuf
)
6362 else if (!check_byte_reg ())
6365 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6368 && i
.tm
.opcode_modifier
.ignoresize
6369 && i
.tm
.opcode_modifier
.no_lsuf
6370 && !i
.tm
.opcode_modifier
.todword
6371 && !i
.tm
.opcode_modifier
.toqword
)
6373 else if (!check_long_reg ())
6376 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6379 && i
.tm
.opcode_modifier
.ignoresize
6380 && i
.tm
.opcode_modifier
.no_qsuf
6381 && !i
.tm
.opcode_modifier
.todword
6382 && !i
.tm
.opcode_modifier
.toqword
)
6384 else if (!check_qword_reg ())
6387 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6390 && i
.tm
.opcode_modifier
.ignoresize
6391 && i
.tm
.opcode_modifier
.no_wsuf
)
6393 else if (!check_word_reg ())
6396 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6397 /* Do nothing if the instruction is going to ignore the prefix. */
6402 else if (i
.tm
.opcode_modifier
.defaultsize
6404 /* exclude fldenv/frstor/fsave/fstenv */
6405 && i
.tm
.opcode_modifier
.no_ssuf
6406 /* exclude sysret */
6407 && i
.tm
.base_opcode
!= 0x0f07)
6409 i
.suffix
= stackop_size
;
6410 if (stackop_size
== LONG_MNEM_SUFFIX
)
6412 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6413 .code16gcc directive to support 16-bit mode with
6414 32-bit address. For IRET without a suffix, generate
6415 16-bit IRET (opcode 0xcf) to return from an interrupt
6417 if (i
.tm
.base_opcode
== 0xcf)
6419 i
.suffix
= WORD_MNEM_SUFFIX
;
6420 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6422 /* Warn about changed behavior for segment register push/pop. */
6423 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6424 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6428 else if (intel_syntax
6430 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6431 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6432 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6433 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6434 && i
.tm
.extension_opcode
<= 3)))
6439 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6441 i
.suffix
= QWORD_MNEM_SUFFIX
;
6446 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6447 i
.suffix
= LONG_MNEM_SUFFIX
;
6450 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6451 i
.suffix
= WORD_MNEM_SUFFIX
;
6460 if (i
.tm
.opcode_modifier
.w
)
6462 as_bad (_("no instruction mnemonic suffix given and "
6463 "no register operands; can't size instruction"));
6469 unsigned int suffixes
;
6471 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6472 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6474 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6476 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6478 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6480 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6483 /* There are more than suffix matches. */
6484 if (i
.tm
.opcode_modifier
.w
6485 || ((suffixes
& (suffixes
- 1))
6486 && !i
.tm
.opcode_modifier
.defaultsize
6487 && !i
.tm
.opcode_modifier
.ignoresize
))
6489 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6495 /* Change the opcode based on the operand size given by i.suffix. */
6498 /* Size floating point instruction. */
6499 case LONG_MNEM_SUFFIX
:
6500 if (i
.tm
.opcode_modifier
.floatmf
)
6502 i
.tm
.base_opcode
^= 4;
6506 case WORD_MNEM_SUFFIX
:
6507 case QWORD_MNEM_SUFFIX
:
6508 /* It's not a byte, select word/dword operation. */
6509 if (i
.tm
.opcode_modifier
.w
)
6511 if (i
.tm
.opcode_modifier
.shortform
)
6512 i
.tm
.base_opcode
|= 8;
6514 i
.tm
.base_opcode
|= 1;
6517 case SHORT_MNEM_SUFFIX
:
6518 /* Now select between word & dword operations via the operand
6519 size prefix, except for instructions that will ignore this
6521 if (i
.reg_operands
> 0
6522 && i
.types
[0].bitfield
.class == Reg
6523 && i
.tm
.opcode_modifier
.addrprefixopreg
6524 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6525 || i
.operands
== 1))
6527 /* The address size override prefix changes the size of the
6529 if ((flag_code
== CODE_32BIT
6530 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6531 || (flag_code
!= CODE_32BIT
6532 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6533 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6536 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6537 && !i
.tm
.opcode_modifier
.ignoresize
6538 && !i
.tm
.opcode_modifier
.floatmf
6539 && !is_any_vex_encoding (&i
.tm
)
6540 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6541 || (flag_code
== CODE_64BIT
6542 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6544 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6546 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6547 prefix
= ADDR_PREFIX_OPCODE
;
6549 if (!add_prefix (prefix
))
6553 /* Set mode64 for an operand. */
6554 if (i
.suffix
== QWORD_MNEM_SUFFIX
6555 && flag_code
== CODE_64BIT
6556 && !i
.tm
.opcode_modifier
.norex64
6557 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6559 && ! (i
.operands
== 2
6560 && i
.tm
.base_opcode
== 0x90
6561 && i
.tm
.extension_opcode
== None
6562 && i
.types
[0].bitfield
.instance
== Accum
6563 && i
.types
[0].bitfield
.qword
6564 && i
.types
[1].bitfield
.instance
== Accum
6565 && i
.types
[1].bitfield
.qword
))
6571 if (i
.reg_operands
!= 0
6573 && i
.tm
.opcode_modifier
.addrprefixopreg
6574 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6576 /* Check invalid register operand when the address size override
6577 prefix changes the size of register operands. */
6579 enum { need_word
, need_dword
, need_qword
} need
;
6581 if (flag_code
== CODE_32BIT
)
6582 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6585 if (i
.prefix
[ADDR_PREFIX
])
6588 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6591 for (op
= 0; op
< i
.operands
; op
++)
6592 if (i
.types
[op
].bitfield
.class == Reg
6593 && ((need
== need_word
6594 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6595 || (need
== need_dword
6596 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6597 || (need
== need_qword
6598 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6600 as_bad (_("invalid register operand size for `%s'"),
6610 check_byte_reg (void)
6614 for (op
= i
.operands
; --op
>= 0;)
6616 /* Skip non-register operands. */
6617 if (i
.types
[op
].bitfield
.class != Reg
)
6620 /* If this is an eight bit register, it's OK. If it's the 16 or
6621 32 bit version of an eight bit register, we will just use the
6622 low portion, and that's OK too. */
6623 if (i
.types
[op
].bitfield
.byte
)
6626 /* I/O port address operands are OK too. */
6627 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6628 && i
.tm
.operand_types
[op
].bitfield
.word
)
6631 /* crc32 doesn't generate this warning. */
6632 if (i
.tm
.base_opcode
== 0xf20f38f0)
6635 if ((i
.types
[op
].bitfield
.word
6636 || i
.types
[op
].bitfield
.dword
6637 || i
.types
[op
].bitfield
.qword
)
6638 && i
.op
[op
].regs
->reg_num
< 4
6639 /* Prohibit these changes in 64bit mode, since the lowering
6640 would be more complicated. */
6641 && flag_code
!= CODE_64BIT
)
6643 #if REGISTER_WARNINGS
6644 if (!quiet_warnings
)
6645 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6647 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6648 ? REGNAM_AL
- REGNAM_AX
6649 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6651 i
.op
[op
].regs
->reg_name
,
6656 /* Any other register is bad. */
6657 if (i
.types
[op
].bitfield
.class == Reg
6658 || i
.types
[op
].bitfield
.class == RegMMX
6659 || i
.types
[op
].bitfield
.class == RegSIMD
6660 || i
.types
[op
].bitfield
.class == SReg
6661 || i
.types
[op
].bitfield
.class == RegCR
6662 || i
.types
[op
].bitfield
.class == RegDR
6663 || i
.types
[op
].bitfield
.class == RegTR
)
6665 as_bad (_("`%s%s' not allowed with `%s%c'"),
6667 i
.op
[op
].regs
->reg_name
,
6677 check_long_reg (void)
6681 for (op
= i
.operands
; --op
>= 0;)
6682 /* Skip non-register operands. */
6683 if (i
.types
[op
].bitfield
.class != Reg
)
6685 /* Reject eight bit registers, except where the template requires
6686 them. (eg. movzb) */
6687 else if (i
.types
[op
].bitfield
.byte
6688 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6689 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6690 && (i
.tm
.operand_types
[op
].bitfield
.word
6691 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6693 as_bad (_("`%s%s' not allowed with `%s%c'"),
6695 i
.op
[op
].regs
->reg_name
,
6700 /* Warn if the e prefix on a general reg is missing. */
6701 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6702 && i
.types
[op
].bitfield
.word
6703 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6704 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6705 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6707 /* Prohibit these changes in the 64bit mode, since the
6708 lowering is more complicated. */
6709 if (flag_code
== CODE_64BIT
)
6711 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6712 register_prefix
, i
.op
[op
].regs
->reg_name
,
6716 #if REGISTER_WARNINGS
6717 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6719 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6720 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6723 /* Warn if the r prefix on a general reg is present. */
6724 else if (i
.types
[op
].bitfield
.qword
6725 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6726 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6727 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6730 && i
.tm
.opcode_modifier
.toqword
6731 && i
.types
[0].bitfield
.class != RegSIMD
)
6733 /* Convert to QWORD. We want REX byte. */
6734 i
.suffix
= QWORD_MNEM_SUFFIX
;
6738 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6739 register_prefix
, i
.op
[op
].regs
->reg_name
,
6748 check_qword_reg (void)
6752 for (op
= i
.operands
; --op
>= 0; )
6753 /* Skip non-register operands. */
6754 if (i
.types
[op
].bitfield
.class != Reg
)
6756 /* Reject eight bit registers, except where the template requires
6757 them. (eg. movzb) */
6758 else if (i
.types
[op
].bitfield
.byte
6759 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6760 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6761 && (i
.tm
.operand_types
[op
].bitfield
.word
6762 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6764 as_bad (_("`%s%s' not allowed with `%s%c'"),
6766 i
.op
[op
].regs
->reg_name
,
6771 /* Warn if the r prefix on a general reg is missing. */
6772 else if ((i
.types
[op
].bitfield
.word
6773 || i
.types
[op
].bitfield
.dword
)
6774 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6775 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6776 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6778 /* Prohibit these changes in the 64bit mode, since the
6779 lowering is more complicated. */
6781 && i
.tm
.opcode_modifier
.todword
6782 && i
.types
[0].bitfield
.class != RegSIMD
)
6784 /* Convert to DWORD. We don't want REX byte. */
6785 i
.suffix
= LONG_MNEM_SUFFIX
;
6789 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6790 register_prefix
, i
.op
[op
].regs
->reg_name
,
6799 check_word_reg (void)
6802 for (op
= i
.operands
; --op
>= 0;)
6803 /* Skip non-register operands. */
6804 if (i
.types
[op
].bitfield
.class != Reg
)
6806 /* Reject eight bit registers, except where the template requires
6807 them. (eg. movzb) */
6808 else if (i
.types
[op
].bitfield
.byte
6809 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6810 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6811 && (i
.tm
.operand_types
[op
].bitfield
.word
6812 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6814 as_bad (_("`%s%s' not allowed with `%s%c'"),
6816 i
.op
[op
].regs
->reg_name
,
6821 /* Warn if the e or r prefix on a general reg is present. */
6822 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6823 && (i
.types
[op
].bitfield
.dword
6824 || i
.types
[op
].bitfield
.qword
)
6825 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6826 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6827 && i
.tm
.operand_types
[op
].bitfield
.word
)
6829 /* Prohibit these changes in the 64bit mode, since the
6830 lowering is more complicated. */
6831 if (flag_code
== CODE_64BIT
)
6833 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6834 register_prefix
, i
.op
[op
].regs
->reg_name
,
6838 #if REGISTER_WARNINGS
6839 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6841 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6842 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6849 update_imm (unsigned int j
)
6851 i386_operand_type overlap
= i
.types
[j
];
6852 if ((overlap
.bitfield
.imm8
6853 || overlap
.bitfield
.imm8s
6854 || overlap
.bitfield
.imm16
6855 || overlap
.bitfield
.imm32
6856 || overlap
.bitfield
.imm32s
6857 || overlap
.bitfield
.imm64
)
6858 && !operand_type_equal (&overlap
, &imm8
)
6859 && !operand_type_equal (&overlap
, &imm8s
)
6860 && !operand_type_equal (&overlap
, &imm16
)
6861 && !operand_type_equal (&overlap
, &imm32
)
6862 && !operand_type_equal (&overlap
, &imm32s
)
6863 && !operand_type_equal (&overlap
, &imm64
))
6867 i386_operand_type temp
;
6869 operand_type_set (&temp
, 0);
6870 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6872 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6873 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6875 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6876 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6877 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6879 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6880 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6883 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6886 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6887 || operand_type_equal (&overlap
, &imm16_32
)
6888 || operand_type_equal (&overlap
, &imm16_32s
))
6890 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6895 if (!operand_type_equal (&overlap
, &imm8
)
6896 && !operand_type_equal (&overlap
, &imm8s
)
6897 && !operand_type_equal (&overlap
, &imm16
)
6898 && !operand_type_equal (&overlap
, &imm32
)
6899 && !operand_type_equal (&overlap
, &imm32s
)
6900 && !operand_type_equal (&overlap
, &imm64
))
6902 as_bad (_("no instruction mnemonic suffix given; "
6903 "can't determine immediate size"));
6907 i
.types
[j
] = overlap
;
6917 /* Update the first 2 immediate operands. */
6918 n
= i
.operands
> 2 ? 2 : i
.operands
;
6921 for (j
= 0; j
< n
; j
++)
6922 if (update_imm (j
) == 0)
6925 /* The 3rd operand can't be immediate operand. */
6926 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6933 process_operands (void)
6935 /* Default segment register this instruction will use for memory
6936 accesses. 0 means unknown. This is only for optimizing out
6937 unnecessary segment overrides. */
6938 const seg_entry
*default_seg
= 0;
6940 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6942 unsigned int dupl
= i
.operands
;
6943 unsigned int dest
= dupl
- 1;
6946 /* The destination must be an xmm register. */
6947 gas_assert (i
.reg_operands
6948 && MAX_OPERANDS
> dupl
6949 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6951 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6952 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6954 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6956 /* Keep xmm0 for instructions with VEX prefix and 3
6958 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6959 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6964 /* We remove the first xmm0 and keep the number of
6965 operands unchanged, which in fact duplicates the
6967 for (j
= 1; j
< i
.operands
; j
++)
6969 i
.op
[j
- 1] = i
.op
[j
];
6970 i
.types
[j
- 1] = i
.types
[j
];
6971 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6972 i
.flags
[j
- 1] = i
.flags
[j
];
6976 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6978 gas_assert ((MAX_OPERANDS
- 1) > dupl
6979 && (i
.tm
.opcode_modifier
.vexsources
6982 /* Add the implicit xmm0 for instructions with VEX prefix
6984 for (j
= i
.operands
; j
> 0; j
--)
6986 i
.op
[j
] = i
.op
[j
- 1];
6987 i
.types
[j
] = i
.types
[j
- 1];
6988 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6989 i
.flags
[j
] = i
.flags
[j
- 1];
6992 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6993 i
.types
[0] = regxmm
;
6994 i
.tm
.operand_types
[0] = regxmm
;
6997 i
.reg_operands
+= 2;
7002 i
.op
[dupl
] = i
.op
[dest
];
7003 i
.types
[dupl
] = i
.types
[dest
];
7004 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7005 i
.flags
[dupl
] = i
.flags
[dest
];
7014 i
.op
[dupl
] = i
.op
[dest
];
7015 i
.types
[dupl
] = i
.types
[dest
];
7016 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7017 i
.flags
[dupl
] = i
.flags
[dest
];
7020 if (i
.tm
.opcode_modifier
.immext
)
7023 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7024 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7028 for (j
= 1; j
< i
.operands
; j
++)
7030 i
.op
[j
- 1] = i
.op
[j
];
7031 i
.types
[j
- 1] = i
.types
[j
];
7033 /* We need to adjust fields in i.tm since they are used by
7034 build_modrm_byte. */
7035 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7037 i
.flags
[j
- 1] = i
.flags
[j
];
7044 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7046 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7048 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7049 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7050 regnum
= register_number (i
.op
[1].regs
);
7051 first_reg_in_group
= regnum
& ~3;
7052 last_reg_in_group
= first_reg_in_group
+ 3;
7053 if (regnum
!= first_reg_in_group
)
7054 as_warn (_("source register `%s%s' implicitly denotes"
7055 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7056 register_prefix
, i
.op
[1].regs
->reg_name
,
7057 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7058 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7061 else if (i
.tm
.opcode_modifier
.regkludge
)
7063 /* The imul $imm, %reg instruction is converted into
7064 imul $imm, %reg, %reg, and the clr %reg instruction
7065 is converted into xor %reg, %reg. */
7067 unsigned int first_reg_op
;
7069 if (operand_type_check (i
.types
[0], reg
))
7073 /* Pretend we saw the extra register operand. */
7074 gas_assert (i
.reg_operands
== 1
7075 && i
.op
[first_reg_op
+ 1].regs
== 0);
7076 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7077 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7082 if (i
.tm
.opcode_modifier
.modrm
)
7084 /* The opcode is completed (modulo i.tm.extension_opcode which
7085 must be put into the modrm byte). Now, we make the modrm and
7086 index base bytes based on all the info we've collected. */
7088 default_seg
= build_modrm_byte ();
7090 else if (i
.types
[0].bitfield
.class == SReg
)
7092 if (flag_code
!= CODE_64BIT
7093 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7094 && i
.op
[0].regs
->reg_num
== 1
7095 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7096 && i
.op
[0].regs
->reg_num
< 4)
7098 as_bad (_("you can't `%s %s%s'"),
7099 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7102 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7104 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7105 i
.tm
.opcode_length
= 2;
7107 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7109 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7113 else if (i
.tm
.opcode_modifier
.isstring
)
7115 /* For the string instructions that allow a segment override
7116 on one of their operands, the default segment is ds. */
7119 else if (i
.tm
.opcode_modifier
.shortform
)
7121 /* The register or float register operand is in operand
7123 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7125 /* Register goes in low 3 bits of opcode. */
7126 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7127 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7129 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7131 /* Warn about some common errors, but press on regardless.
7132 The first case can be generated by gcc (<= 2.8.1). */
7133 if (i
.operands
== 2)
7135 /* Reversed arguments on faddp, fsubp, etc. */
7136 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7137 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7138 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7142 /* Extraneous `l' suffix on fp insn. */
7143 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7144 register_prefix
, i
.op
[0].regs
->reg_name
);
7149 if (i
.tm
.base_opcode
== 0x8d /* lea */
7152 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7154 /* If a segment was explicitly specified, and the specified segment
7155 is not the default, use an opcode prefix to select it. If we
7156 never figured out what the default segment is, then default_seg
7157 will be zero at this point, and the specified segment prefix will
7159 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7161 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7167 static const seg_entry
*
7168 build_modrm_byte (void)
7170 const seg_entry
*default_seg
= 0;
7171 unsigned int source
, dest
;
7174 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7177 unsigned int nds
, reg_slot
;
7180 dest
= i
.operands
- 1;
7183 /* There are 2 kinds of instructions:
7184 1. 5 operands: 4 register operands or 3 register operands
7185 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7186 VexW0 or VexW1. The destination must be either XMM, YMM or
7188 2. 4 operands: 4 register operands or 3 register operands
7189 plus 1 memory operand, with VexXDS. */
7190 gas_assert ((i
.reg_operands
== 4
7191 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7192 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7193 && i
.tm
.opcode_modifier
.vexw
7194 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7196 /* If VexW1 is set, the first non-immediate operand is the source and
7197 the second non-immediate one is encoded in the immediate operand. */
7198 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7200 source
= i
.imm_operands
;
7201 reg_slot
= i
.imm_operands
+ 1;
7205 source
= i
.imm_operands
+ 1;
7206 reg_slot
= i
.imm_operands
;
7209 if (i
.imm_operands
== 0)
7211 /* When there is no immediate operand, generate an 8bit
7212 immediate operand to encode the first operand. */
7213 exp
= &im_expressions
[i
.imm_operands
++];
7214 i
.op
[i
.operands
].imms
= exp
;
7215 i
.types
[i
.operands
] = imm8
;
7218 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7219 exp
->X_op
= O_constant
;
7220 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7221 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7225 gas_assert (i
.imm_operands
== 1);
7226 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7227 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7229 /* Turn on Imm8 again so that output_imm will generate it. */
7230 i
.types
[0].bitfield
.imm8
= 1;
7232 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7233 i
.op
[0].imms
->X_add_number
7234 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7235 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7238 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7239 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7244 /* i.reg_operands MUST be the number of real register operands;
7245 implicit registers do not count. If there are 3 register
7246 operands, it must be a instruction with VexNDS. For a
7247 instruction with VexNDD, the destination register is encoded
7248 in VEX prefix. If there are 4 register operands, it must be
7249 a instruction with VEX prefix and 3 sources. */
7250 if (i
.mem_operands
== 0
7251 && ((i
.reg_operands
== 2
7252 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7253 || (i
.reg_operands
== 3
7254 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7255 || (i
.reg_operands
== 4 && vex_3_sources
)))
7263 /* When there are 3 operands, one of them may be immediate,
7264 which may be the first or the last operand. Otherwise,
7265 the first operand must be shift count register (cl) or it
7266 is an instruction with VexNDS. */
7267 gas_assert (i
.imm_operands
== 1
7268 || (i
.imm_operands
== 0
7269 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7270 || (i
.types
[0].bitfield
.instance
== RegC
7271 && i
.types
[0].bitfield
.byte
))));
7272 if (operand_type_check (i
.types
[0], imm
)
7273 || (i
.types
[0].bitfield
.instance
== RegC
7274 && i
.types
[0].bitfield
.byte
))
7280 /* When there are 4 operands, the first two must be 8bit
7281 immediate operands. The source operand will be the 3rd
7284 For instructions with VexNDS, if the first operand
7285 an imm8, the source operand is the 2nd one. If the last
7286 operand is imm8, the source operand is the first one. */
7287 gas_assert ((i
.imm_operands
== 2
7288 && i
.types
[0].bitfield
.imm8
7289 && i
.types
[1].bitfield
.imm8
)
7290 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7291 && i
.imm_operands
== 1
7292 && (i
.types
[0].bitfield
.imm8
7293 || i
.types
[i
.operands
- 1].bitfield
.imm8
7295 if (i
.imm_operands
== 2)
7299 if (i
.types
[0].bitfield
.imm8
)
7306 if (is_evex_encoding (&i
.tm
))
7308 /* For EVEX instructions, when there are 5 operands, the
7309 first one must be immediate operand. If the second one
7310 is immediate operand, the source operand is the 3th
7311 one. If the last one is immediate operand, the source
7312 operand is the 2nd one. */
7313 gas_assert (i
.imm_operands
== 2
7314 && i
.tm
.opcode_modifier
.sae
7315 && operand_type_check (i
.types
[0], imm
));
7316 if (operand_type_check (i
.types
[1], imm
))
7318 else if (operand_type_check (i
.types
[4], imm
))
7332 /* RC/SAE operand could be between DEST and SRC. That happens
7333 when one operand is GPR and the other one is XMM/YMM/ZMM
7335 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7338 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7340 /* For instructions with VexNDS, the register-only source
7341 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7342 register. It is encoded in VEX prefix. */
7344 i386_operand_type op
;
7347 /* Check register-only source operand when two source
7348 operands are swapped. */
7349 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7350 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7358 op
= i
.tm
.operand_types
[vvvv
];
7359 if ((dest
+ 1) >= i
.operands
7360 || ((op
.bitfield
.class != Reg
7361 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7362 && op
.bitfield
.class != RegSIMD
7363 && !operand_type_equal (&op
, ®mask
)))
7365 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7371 /* One of the register operands will be encoded in the i.rm.reg
7372 field, the other in the combined i.rm.mode and i.rm.regmem
7373 fields. If no form of this instruction supports a memory
7374 destination operand, then we assume the source operand may
7375 sometimes be a memory operand and so we need to store the
7376 destination in the i.rm.reg field. */
7377 if (!i
.tm
.opcode_modifier
.regmem
7378 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7380 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7381 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7382 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7383 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7384 i
.has_regmmx
= TRUE
;
7385 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7386 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7388 if (i
.types
[dest
].bitfield
.zmmword
7389 || i
.types
[source
].bitfield
.zmmword
)
7390 i
.has_regzmm
= TRUE
;
7391 else if (i
.types
[dest
].bitfield
.ymmword
7392 || i
.types
[source
].bitfield
.ymmword
)
7393 i
.has_regymm
= TRUE
;
7395 i
.has_regxmm
= TRUE
;
7397 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7399 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7401 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7403 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7408 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7409 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7410 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7412 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7414 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7416 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7419 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7421 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7424 add_prefix (LOCK_PREFIX_OPCODE
);
7428 { /* If it's not 2 reg operands... */
7433 unsigned int fake_zero_displacement
= 0;
7436 for (op
= 0; op
< i
.operands
; op
++)
7437 if (i
.flags
[op
] & Operand_Mem
)
7439 gas_assert (op
< i
.operands
);
7441 if (i
.tm
.opcode_modifier
.vecsib
)
7443 if (i
.index_reg
->reg_num
== RegIZ
)
7446 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7449 i
.sib
.base
= NO_BASE_REGISTER
;
7450 i
.sib
.scale
= i
.log2_scale_factor
;
7451 i
.types
[op
].bitfield
.disp8
= 0;
7452 i
.types
[op
].bitfield
.disp16
= 0;
7453 i
.types
[op
].bitfield
.disp64
= 0;
7454 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7456 /* Must be 32 bit */
7457 i
.types
[op
].bitfield
.disp32
= 1;
7458 i
.types
[op
].bitfield
.disp32s
= 0;
7462 i
.types
[op
].bitfield
.disp32
= 0;
7463 i
.types
[op
].bitfield
.disp32s
= 1;
7466 i
.sib
.index
= i
.index_reg
->reg_num
;
7467 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7469 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7475 if (i
.base_reg
== 0)
7478 if (!i
.disp_operands
)
7479 fake_zero_displacement
= 1;
7480 if (i
.index_reg
== 0)
7482 i386_operand_type newdisp
;
7484 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7485 /* Operand is just <disp> */
7486 if (flag_code
== CODE_64BIT
)
7488 /* 64bit mode overwrites the 32bit absolute
7489 addressing by RIP relative addressing and
7490 absolute addressing is encoded by one of the
7491 redundant SIB forms. */
7492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7493 i
.sib
.base
= NO_BASE_REGISTER
;
7494 i
.sib
.index
= NO_INDEX_REGISTER
;
7495 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7497 else if ((flag_code
== CODE_16BIT
)
7498 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7500 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7505 i
.rm
.regmem
= NO_BASE_REGISTER
;
7508 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7509 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7511 else if (!i
.tm
.opcode_modifier
.vecsib
)
7513 /* !i.base_reg && i.index_reg */
7514 if (i
.index_reg
->reg_num
== RegIZ
)
7515 i
.sib
.index
= NO_INDEX_REGISTER
;
7517 i
.sib
.index
= i
.index_reg
->reg_num
;
7518 i
.sib
.base
= NO_BASE_REGISTER
;
7519 i
.sib
.scale
= i
.log2_scale_factor
;
7520 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7521 i
.types
[op
].bitfield
.disp8
= 0;
7522 i
.types
[op
].bitfield
.disp16
= 0;
7523 i
.types
[op
].bitfield
.disp64
= 0;
7524 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7526 /* Must be 32 bit */
7527 i
.types
[op
].bitfield
.disp32
= 1;
7528 i
.types
[op
].bitfield
.disp32s
= 0;
7532 i
.types
[op
].bitfield
.disp32
= 0;
7533 i
.types
[op
].bitfield
.disp32s
= 1;
7535 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7539 /* RIP addressing for 64bit mode. */
7540 else if (i
.base_reg
->reg_num
== RegIP
)
7542 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7543 i
.rm
.regmem
= NO_BASE_REGISTER
;
7544 i
.types
[op
].bitfield
.disp8
= 0;
7545 i
.types
[op
].bitfield
.disp16
= 0;
7546 i
.types
[op
].bitfield
.disp32
= 0;
7547 i
.types
[op
].bitfield
.disp32s
= 1;
7548 i
.types
[op
].bitfield
.disp64
= 0;
7549 i
.flags
[op
] |= Operand_PCrel
;
7550 if (! i
.disp_operands
)
7551 fake_zero_displacement
= 1;
7553 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7555 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7556 switch (i
.base_reg
->reg_num
)
7559 if (i
.index_reg
== 0)
7561 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7562 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7566 if (i
.index_reg
== 0)
7569 if (operand_type_check (i
.types
[op
], disp
) == 0)
7571 /* fake (%bp) into 0(%bp) */
7572 i
.types
[op
].bitfield
.disp8
= 1;
7573 fake_zero_displacement
= 1;
7576 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7577 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7579 default: /* (%si) -> 4 or (%di) -> 5 */
7580 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7582 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7584 else /* i.base_reg and 32/64 bit mode */
7586 if (flag_code
== CODE_64BIT
7587 && operand_type_check (i
.types
[op
], disp
))
7589 i
.types
[op
].bitfield
.disp16
= 0;
7590 i
.types
[op
].bitfield
.disp64
= 0;
7591 if (i
.prefix
[ADDR_PREFIX
] == 0)
7593 i
.types
[op
].bitfield
.disp32
= 0;
7594 i
.types
[op
].bitfield
.disp32s
= 1;
7598 i
.types
[op
].bitfield
.disp32
= 1;
7599 i
.types
[op
].bitfield
.disp32s
= 0;
7603 if (!i
.tm
.opcode_modifier
.vecsib
)
7604 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7605 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7607 i
.sib
.base
= i
.base_reg
->reg_num
;
7608 /* x86-64 ignores REX prefix bit here to avoid decoder
7610 if (!(i
.base_reg
->reg_flags
& RegRex
)
7611 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7612 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7614 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7616 fake_zero_displacement
= 1;
7617 i
.types
[op
].bitfield
.disp8
= 1;
7619 i
.sib
.scale
= i
.log2_scale_factor
;
7620 if (i
.index_reg
== 0)
7622 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7623 /* <disp>(%esp) becomes two byte modrm with no index
7624 register. We've already stored the code for esp
7625 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7626 Any base register besides %esp will not use the
7627 extra modrm byte. */
7628 i
.sib
.index
= NO_INDEX_REGISTER
;
7630 else if (!i
.tm
.opcode_modifier
.vecsib
)
7632 if (i
.index_reg
->reg_num
== RegIZ
)
7633 i
.sib
.index
= NO_INDEX_REGISTER
;
7635 i
.sib
.index
= i
.index_reg
->reg_num
;
7636 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7637 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7642 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7643 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7647 if (!fake_zero_displacement
7651 fake_zero_displacement
= 1;
7652 if (i
.disp_encoding
== disp_encoding_8bit
)
7653 i
.types
[op
].bitfield
.disp8
= 1;
7655 i
.types
[op
].bitfield
.disp32
= 1;
7657 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7661 if (fake_zero_displacement
)
7663 /* Fakes a zero displacement assuming that i.types[op]
7664 holds the correct displacement size. */
7667 gas_assert (i
.op
[op
].disps
== 0);
7668 exp
= &disp_expressions
[i
.disp_operands
++];
7669 i
.op
[op
].disps
= exp
;
7670 exp
->X_op
= O_constant
;
7671 exp
->X_add_number
= 0;
7672 exp
->X_add_symbol
= (symbolS
*) 0;
7673 exp
->X_op_symbol
= (symbolS
*) 0;
7681 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7683 if (operand_type_check (i
.types
[0], imm
))
7684 i
.vex
.register_specifier
= NULL
;
7687 /* VEX.vvvv encodes one of the sources when the first
7688 operand is not an immediate. */
7689 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7690 i
.vex
.register_specifier
= i
.op
[0].regs
;
7692 i
.vex
.register_specifier
= i
.op
[1].regs
;
7695 /* Destination is a XMM register encoded in the ModRM.reg
7697 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7698 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7701 /* ModRM.rm and VEX.B encodes the other source. */
7702 if (!i
.mem_operands
)
7706 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7707 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7709 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7711 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7715 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7717 i
.vex
.register_specifier
= i
.op
[2].regs
;
7718 if (!i
.mem_operands
)
7721 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7722 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7726 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7727 (if any) based on i.tm.extension_opcode. Again, we must be
7728 careful to make sure that segment/control/debug/test/MMX
7729 registers are coded into the i.rm.reg field. */
7730 else if (i
.reg_operands
)
7733 unsigned int vex_reg
= ~0;
7735 for (op
= 0; op
< i
.operands
; op
++)
7737 if (i
.types
[op
].bitfield
.class == Reg
7738 || i
.types
[op
].bitfield
.class == RegBND
7739 || i
.types
[op
].bitfield
.class == RegMask
7740 || i
.types
[op
].bitfield
.class == SReg
7741 || i
.types
[op
].bitfield
.class == RegCR
7742 || i
.types
[op
].bitfield
.class == RegDR
7743 || i
.types
[op
].bitfield
.class == RegTR
)
7745 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7747 if (i
.types
[op
].bitfield
.zmmword
)
7748 i
.has_regzmm
= TRUE
;
7749 else if (i
.types
[op
].bitfield
.ymmword
)
7750 i
.has_regymm
= TRUE
;
7752 i
.has_regxmm
= TRUE
;
7755 if (i
.types
[op
].bitfield
.class == RegMMX
)
7757 i
.has_regmmx
= TRUE
;
7764 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7766 /* For instructions with VexNDS, the register-only
7767 source operand is encoded in VEX prefix. */
7768 gas_assert (mem
!= (unsigned int) ~0);
7773 gas_assert (op
< i
.operands
);
7777 /* Check register-only source operand when two source
7778 operands are swapped. */
7779 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7780 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7784 gas_assert (mem
== (vex_reg
+ 1)
7785 && op
< i
.operands
);
7790 gas_assert (vex_reg
< i
.operands
);
7794 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7796 /* For instructions with VexNDD, the register destination
7797 is encoded in VEX prefix. */
7798 if (i
.mem_operands
== 0)
7800 /* There is no memory operand. */
7801 gas_assert ((op
+ 2) == i
.operands
);
7806 /* There are only 2 non-immediate operands. */
7807 gas_assert (op
< i
.imm_operands
+ 2
7808 && i
.operands
== i
.imm_operands
+ 2);
7809 vex_reg
= i
.imm_operands
+ 1;
7813 gas_assert (op
< i
.operands
);
7815 if (vex_reg
!= (unsigned int) ~0)
7817 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7819 if ((type
->bitfield
.class != Reg
7820 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7821 && type
->bitfield
.class != RegSIMD
7822 && !operand_type_equal (type
, ®mask
))
7825 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7828 /* Don't set OP operand twice. */
7831 /* If there is an extension opcode to put here, the
7832 register number must be put into the regmem field. */
7833 if (i
.tm
.extension_opcode
!= None
)
7835 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7836 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7838 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7843 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7844 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7846 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7851 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7852 must set it to 3 to indicate this is a register operand
7853 in the regmem field. */
7854 if (!i
.mem_operands
)
7858 /* Fill in i.rm.reg field with extension opcode (if any). */
7859 if (i
.tm
.extension_opcode
!= None
)
7860 i
.rm
.reg
= i
.tm
.extension_opcode
;
7866 output_branch (void)
7872 relax_substateT subtype
;
7876 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7877 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7880 if (i
.prefix
[DATA_PREFIX
] != 0)
7886 /* Pentium4 branch hints. */
7887 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7888 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7893 if (i
.prefix
[REX_PREFIX
] != 0)
7899 /* BND prefixed jump. */
7900 if (i
.prefix
[BND_PREFIX
] != 0)
7902 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
7906 if (i
.prefixes
!= 0 && !intel_syntax
)
7907 as_warn (_("skipping prefixes on this instruction"));
7909 /* It's always a symbol; End frag & setup for relax.
7910 Make sure there is enough room in this frag for the largest
7911 instruction we may generate in md_convert_frag. This is 2
7912 bytes for the opcode and room for the prefix and largest
7914 frag_grow (prefix
+ 2 + 4);
7915 /* Prefix and 1 opcode byte go in fr_fix. */
7916 p
= frag_more (prefix
+ 1);
7917 if (i
.prefix
[DATA_PREFIX
] != 0)
7918 *p
++ = DATA_PREFIX_OPCODE
;
7919 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7920 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7921 *p
++ = i
.prefix
[SEG_PREFIX
];
7922 if (i
.prefix
[REX_PREFIX
] != 0)
7923 *p
++ = i
.prefix
[REX_PREFIX
];
7924 *p
= i
.tm
.base_opcode
;
7926 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7927 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7928 else if (cpu_arch_flags
.bitfield
.cpui386
)
7929 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7931 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7934 sym
= i
.op
[0].disps
->X_add_symbol
;
7935 off
= i
.op
[0].disps
->X_add_number
;
7937 if (i
.op
[0].disps
->X_op
!= O_constant
7938 && i
.op
[0].disps
->X_op
!= O_symbol
)
7940 /* Handle complex expressions. */
7941 sym
= make_expr_symbol (i
.op
[0].disps
);
7945 /* 1 possible extra opcode + 4 byte displacement go in var part.
7946 Pass reloc in fr_var. */
7947 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7950 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7951 /* Return TRUE iff PLT32 relocation should be used for branching to
7955 need_plt32_p (symbolS
*s
)
7957 /* PLT32 relocation is ELF only. */
7962 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7963 krtld support it. */
7967 /* Since there is no need to prepare for PLT branch on x86-64, we
7968 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7969 be used as a marker for 32-bit PC-relative branches. */
7973 /* Weak or undefined symbol need PLT32 relocation. */
7974 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7977 /* Non-global symbol doesn't need PLT32 relocation. */
7978 if (! S_IS_EXTERNAL (s
))
7981 /* Other global symbols need PLT32 relocation. NB: Symbol with
7982 non-default visibilities are treated as normal global symbol
7983 so that PLT32 relocation can be used as a marker for 32-bit
7984 PC-relative branches. It is useful for linker relaxation. */
7995 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
7997 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
7999 /* This is a loop or jecxz type instruction. */
8001 if (i
.prefix
[ADDR_PREFIX
] != 0)
8003 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8006 /* Pentium4 branch hints. */
8007 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8008 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8010 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8019 if (flag_code
== CODE_16BIT
)
8022 if (i
.prefix
[DATA_PREFIX
] != 0)
8024 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8034 if (i
.prefix
[REX_PREFIX
] != 0)
8036 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8040 /* BND prefixed jump. */
8041 if (i
.prefix
[BND_PREFIX
] != 0)
8043 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8047 if (i
.prefixes
!= 0 && !intel_syntax
)
8048 as_warn (_("skipping prefixes on this instruction"));
8050 p
= frag_more (i
.tm
.opcode_length
+ size
);
8051 switch (i
.tm
.opcode_length
)
8054 *p
++ = i
.tm
.base_opcode
>> 8;
8057 *p
++ = i
.tm
.base_opcode
;
8063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8065 && jump_reloc
== NO_RELOC
8066 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8067 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8070 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8072 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8073 i
.op
[0].disps
, 1, jump_reloc
);
8075 /* All jumps handled here are signed, but don't use a signed limit
8076 check for 32 and 16 bit jumps as we want to allow wrap around at
8077 4G and 64k respectively. */
8079 fixP
->fx_signed
= 1;
8083 output_interseg_jump (void)
8091 if (flag_code
== CODE_16BIT
)
8095 if (i
.prefix
[DATA_PREFIX
] != 0)
8101 if (i
.prefix
[REX_PREFIX
] != 0)
8111 if (i
.prefixes
!= 0 && !intel_syntax
)
8112 as_warn (_("skipping prefixes on this instruction"));
8114 /* 1 opcode; 2 segment; offset */
8115 p
= frag_more (prefix
+ 1 + 2 + size
);
8117 if (i
.prefix
[DATA_PREFIX
] != 0)
8118 *p
++ = DATA_PREFIX_OPCODE
;
8120 if (i
.prefix
[REX_PREFIX
] != 0)
8121 *p
++ = i
.prefix
[REX_PREFIX
];
8123 *p
++ = i
.tm
.base_opcode
;
8124 if (i
.op
[1].imms
->X_op
== O_constant
)
8126 offsetT n
= i
.op
[1].imms
->X_add_number
;
8129 && !fits_in_unsigned_word (n
)
8130 && !fits_in_signed_word (n
))
8132 as_bad (_("16-bit jump out of range"));
8135 md_number_to_chars (p
, n
, size
);
8138 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8139 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8140 if (i
.op
[0].imms
->X_op
!= O_constant
)
8141 as_bad (_("can't handle non absolute segment in `%s'"),
8143 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8151 asection
*seg
= now_seg
;
8152 subsegT subseg
= now_subseg
;
8154 unsigned int alignment
, align_size_1
;
8155 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8156 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8157 unsigned int padding
;
8159 if (!IS_ELF
|| !x86_used_note
)
8162 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8164 /* The .note.gnu.property section layout:
8166 Field Length Contents
8169 n_descsz 4 The note descriptor size
8170 n_type 4 NT_GNU_PROPERTY_TYPE_0
8172 n_desc n_descsz The program property array
8176 /* Create the .note.gnu.property section. */
8177 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8178 bfd_set_section_flags (sec
,
8185 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8196 bfd_set_section_alignment (sec
, alignment
);
8197 elf_section_type (sec
) = SHT_NOTE
;
8199 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8201 isa_1_descsz_raw
= 4 + 4 + 4;
8202 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8203 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8205 feature_2_descsz_raw
= isa_1_descsz
;
8206 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8208 feature_2_descsz_raw
+= 4 + 4 + 4;
8209 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8210 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8213 descsz
= feature_2_descsz
;
8214 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8215 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8217 /* Write n_namsz. */
8218 md_number_to_chars (p
, (valueT
) 4, 4);
8220 /* Write n_descsz. */
8221 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8224 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8227 memcpy (p
+ 4 * 3, "GNU", 4);
8229 /* Write 4-byte type. */
8230 md_number_to_chars (p
+ 4 * 4,
8231 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8233 /* Write 4-byte data size. */
8234 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8236 /* Write 4-byte data. */
8237 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8239 /* Zero out paddings. */
8240 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8242 memset (p
+ 4 * 7, 0, padding
);
8244 /* Write 4-byte type. */
8245 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8246 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8248 /* Write 4-byte data size. */
8249 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8251 /* Write 4-byte data. */
8252 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8253 (valueT
) x86_feature_2_used
, 4);
8255 /* Zero out paddings. */
8256 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8258 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8260 /* We probably can't restore the current segment, for there likely
8263 subseg_set (seg
, subseg
);
8268 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8269 const char *frag_now_ptr
)
8271 unsigned int len
= 0;
8273 if (start_frag
!= frag_now
)
8275 const fragS
*fr
= start_frag
;
8280 } while (fr
&& fr
!= frag_now
);
8283 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8286 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8287 be macro-fused with conditional jumps. */
8290 maybe_fused_with_jcc_p (void)
8292 /* No RIP address. */
8293 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8296 /* No VEX/EVEX encoding. */
8297 if (is_any_vex_encoding (&i
.tm
))
8300 /* and, add, sub with destination register. */
8301 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8302 || i
.tm
.base_opcode
<= 5
8303 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8304 || ((i
.tm
.base_opcode
| 3) == 0x83
8305 && ((i
.tm
.extension_opcode
| 1) == 0x5
8306 || i
.tm
.extension_opcode
== 0x0)))
8307 return (i
.types
[1].bitfield
.class == Reg
8308 || i
.types
[1].bitfield
.instance
== Accum
);
8310 /* test, cmp with any register. */
8311 if ((i
.tm
.base_opcode
| 1) == 0x85
8312 || (i
.tm
.base_opcode
| 1) == 0xa9
8313 || ((i
.tm
.base_opcode
| 1) == 0xf7
8314 && i
.tm
.extension_opcode
== 0)
8315 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8316 || ((i
.tm
.base_opcode
| 3) == 0x83
8317 && (i
.tm
.extension_opcode
== 0x7)))
8318 return (i
.types
[0].bitfield
.class == Reg
8319 || i
.types
[0].bitfield
.instance
== Accum
8320 || i
.types
[1].bitfield
.class == Reg
8321 || i
.types
[1].bitfield
.instance
== Accum
);
8323 /* inc, dec with any register. */
8324 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8325 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8326 || ((i
.tm
.base_opcode
| 1) == 0xff
8327 && i
.tm
.extension_opcode
<= 0x1))
8328 return (i
.types
[0].bitfield
.class == Reg
8329 || i
.types
[0].bitfield
.instance
== Accum
);
8334 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8337 add_fused_jcc_padding_frag_p (void)
8339 /* NB: Don't work with COND_JUMP86 without i386. */
8340 if (!align_branch_power
8341 || now_seg
== absolute_section
8342 || !cpu_arch_flags
.bitfield
.cpui386
8343 || !(align_branch
& align_branch_fused_bit
))
8346 if (maybe_fused_with_jcc_p ())
8348 if (last_insn
.kind
== last_insn_other
8349 || last_insn
.seg
!= now_seg
)
8352 as_warn_where (last_insn
.file
, last_insn
.line
,
8353 _("`%s` skips -malign-branch-boundary on `%s`"),
8354 last_insn
.name
, i
.tm
.name
);
8360 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8363 add_branch_prefix_frag_p (void)
8365 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8366 to PadLock instructions since they include prefixes in opcode. */
8367 if (!align_branch_power
8368 || !align_branch_prefix_size
8369 || now_seg
== absolute_section
8370 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8371 || !cpu_arch_flags
.bitfield
.cpui386
)
8374 /* Don't add prefix if it is a prefix or there is no operand in case
8375 that segment prefix is special. */
8376 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8379 if (last_insn
.kind
== last_insn_other
8380 || last_insn
.seg
!= now_seg
)
8384 as_warn_where (last_insn
.file
, last_insn
.line
,
8385 _("`%s` skips -malign-branch-boundary on `%s`"),
8386 last_insn
.name
, i
.tm
.name
);
8391 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8394 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8398 /* NB: Don't work with COND_JUMP86 without i386. */
8399 if (!align_branch_power
8400 || now_seg
== absolute_section
8401 || !cpu_arch_flags
.bitfield
.cpui386
)
8406 /* Check for jcc and direct jmp. */
8407 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8409 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8411 *branch_p
= align_branch_jmp
;
8412 add_padding
= align_branch
& align_branch_jmp_bit
;
8416 *branch_p
= align_branch_jcc
;
8417 if ((align_branch
& align_branch_jcc_bit
))
8421 else if (is_any_vex_encoding (&i
.tm
))
8423 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8426 *branch_p
= align_branch_ret
;
8427 if ((align_branch
& align_branch_ret_bit
))
8432 /* Check for indirect jmp, direct and indirect calls. */
8433 if (i
.tm
.base_opcode
== 0xe8)
8436 *branch_p
= align_branch_call
;
8437 if ((align_branch
& align_branch_call_bit
))
8440 else if (i
.tm
.base_opcode
== 0xff
8441 && (i
.tm
.extension_opcode
== 2
8442 || i
.tm
.extension_opcode
== 4))
8444 /* Indirect call and jmp. */
8445 *branch_p
= align_branch_indirect
;
8446 if ((align_branch
& align_branch_indirect_bit
))
8453 && (i
.op
[0].disps
->X_op
== O_symbol
8454 || (i
.op
[0].disps
->X_op
== O_subtract
8455 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8457 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8458 /* No padding to call to global or undefined tls_get_addr. */
8459 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8460 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8466 && last_insn
.kind
!= last_insn_other
8467 && last_insn
.seg
== now_seg
)
8470 as_warn_where (last_insn
.file
, last_insn
.line
,
8471 _("`%s` skips -malign-branch-boundary on `%s`"),
8472 last_insn
.name
, i
.tm
.name
);
8482 fragS
*insn_start_frag
;
8483 offsetT insn_start_off
;
8484 fragS
*fragP
= NULL
;
8485 enum align_branch_kind branch
= align_branch_none
;
8487 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8488 if (IS_ELF
&& x86_used_note
)
8490 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8491 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8492 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8493 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8494 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8495 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8496 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8497 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8498 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8499 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8500 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8501 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8502 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8503 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8504 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8505 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8506 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8507 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8508 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8509 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8510 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8511 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8512 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8513 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8514 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8515 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8516 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8517 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8518 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8519 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8520 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8521 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8522 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8523 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8524 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8525 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8526 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8527 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8528 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8529 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8530 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8531 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8532 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8533 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8534 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8535 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8536 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8537 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8538 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8539 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8541 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8542 || i
.tm
.cpu_flags
.bitfield
.cpu287
8543 || i
.tm
.cpu_flags
.bitfield
.cpu387
8544 || i
.tm
.cpu_flags
.bitfield
.cpu687
8545 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8546 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8548 || i
.tm
.base_opcode
== 0xf77 /* emms */
8549 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8550 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8552 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8554 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8556 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8557 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8558 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8559 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8560 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8561 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8562 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8563 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8564 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8568 /* Tie dwarf2 debug info to the address at the start of the insn.
8569 We can't do this after the insn has been output as the current
8570 frag may have been closed off. eg. by frag_var. */
8571 dwarf2_emit_insn (0);
8573 insn_start_frag
= frag_now
;
8574 insn_start_off
= frag_now_fix ();
8576 if (add_branch_padding_frag_p (&branch
))
8579 /* Branch can be 8 bytes. Leave some room for prefixes. */
8580 unsigned int max_branch_padding_size
= 14;
8582 /* Align section to boundary. */
8583 record_alignment (now_seg
, align_branch_power
);
8585 /* Make room for padding. */
8586 frag_grow (max_branch_padding_size
);
8588 /* Start of the padding. */
8593 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8594 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8597 fragP
->tc_frag_data
.branch_type
= branch
;
8598 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8602 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8604 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8605 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8607 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8608 output_interseg_jump ();
8611 /* Output normal instructions here. */
8615 unsigned int prefix
;
8618 && (i
.tm
.base_opcode
== 0xfaee8
8619 || i
.tm
.base_opcode
== 0xfaef0
8620 || i
.tm
.base_opcode
== 0xfaef8))
8622 /* Encode lfence, mfence, and sfence as
8623 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8624 offsetT val
= 0x240483f0ULL
;
8626 md_number_to_chars (p
, val
, 5);
8630 /* Some processors fail on LOCK prefix. This options makes
8631 assembler ignore LOCK prefix and serves as a workaround. */
8632 if (omit_lock_prefix
)
8634 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8636 i
.prefix
[LOCK_PREFIX
] = 0;
8640 /* Skip if this is a branch. */
8642 else if (add_fused_jcc_padding_frag_p ())
8644 /* Make room for padding. */
8645 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8650 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8651 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8654 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8655 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8657 else if (add_branch_prefix_frag_p ())
8659 unsigned int max_prefix_size
= align_branch_prefix_size
;
8661 /* Make room for padding. */
8662 frag_grow (max_prefix_size
);
8667 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8668 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8671 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8674 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8675 don't need the explicit prefix. */
8676 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8678 switch (i
.tm
.opcode_length
)
8681 if (i
.tm
.base_opcode
& 0xff000000)
8683 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8684 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8685 || prefix
!= REPE_PREFIX_OPCODE
8686 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8687 add_prefix (prefix
);
8691 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8693 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8694 add_prefix (prefix
);
8700 /* Check for pseudo prefixes. */
8701 as_bad_where (insn_start_frag
->fr_file
,
8702 insn_start_frag
->fr_line
,
8703 _("pseudo prefix without instruction"));
8709 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8710 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8711 R_X86_64_GOTTPOFF relocation so that linker can safely
8712 perform IE->LE optimization. */
8713 if (x86_elf_abi
== X86_64_X32_ABI
8715 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8716 && i
.prefix
[REX_PREFIX
] == 0)
8717 add_prefix (REX_OPCODE
);
8720 /* The prefix bytes. */
8721 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8723 FRAG_APPEND_1_CHAR (*q
);
8727 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8732 /* REX byte is encoded in VEX prefix. */
8736 FRAG_APPEND_1_CHAR (*q
);
8739 /* There should be no other prefixes for instructions
8744 /* For EVEX instructions i.vrex should become 0 after
8745 build_evex_prefix. For VEX instructions upper 16 registers
8746 aren't available, so VREX should be 0. */
8749 /* Now the VEX prefix. */
8750 p
= frag_more (i
.vex
.length
);
8751 for (j
= 0; j
< i
.vex
.length
; j
++)
8752 p
[j
] = i
.vex
.bytes
[j
];
8755 /* Now the opcode; be careful about word order here! */
8756 if (i
.tm
.opcode_length
== 1)
8758 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8762 switch (i
.tm
.opcode_length
)
8766 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8767 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8771 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8781 /* Put out high byte first: can't use md_number_to_chars! */
8782 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8783 *p
= i
.tm
.base_opcode
& 0xff;
8786 /* Now the modrm byte and sib byte (if present). */
8787 if (i
.tm
.opcode_modifier
.modrm
)
8789 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8792 /* If i.rm.regmem == ESP (4)
8793 && i.rm.mode != (Register mode)
8795 ==> need second modrm byte. */
8796 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8798 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8799 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8801 | i
.sib
.scale
<< 6));
8804 if (i
.disp_operands
)
8805 output_disp (insn_start_frag
, insn_start_off
);
8808 output_imm (insn_start_frag
, insn_start_off
);
8811 * frag_now_fix () returning plain abs_section_offset when we're in the
8812 * absolute section, and abs_section_offset not getting updated as data
8813 * gets added to the frag breaks the logic below.
8815 if (now_seg
!= absolute_section
)
8817 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8819 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8823 /* NB: Don't add prefix with GOTPC relocation since
8824 output_disp() above depends on the fixed encoding
8825 length. Can't add prefix with TLS relocation since
8826 it breaks TLS linker optimization. */
8827 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8828 /* Prefix count on the current instruction. */
8829 unsigned int count
= i
.vex
.length
;
8831 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8832 /* REX byte is encoded in VEX/EVEX prefix. */
8833 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8836 /* Count prefixes for extended opcode maps. */
8838 switch (i
.tm
.opcode_length
)
8841 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8844 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8856 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8865 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8868 /* Set the maximum prefix size in BRANCH_PREFIX
8870 if (fragP
->tc_frag_data
.max_bytes
> max
)
8871 fragP
->tc_frag_data
.max_bytes
= max
;
8872 if (fragP
->tc_frag_data
.max_bytes
> count
)
8873 fragP
->tc_frag_data
.max_bytes
-= count
;
8875 fragP
->tc_frag_data
.max_bytes
= 0;
8879 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8881 unsigned int max_prefix_size
;
8882 if (align_branch_prefix_size
> max
)
8883 max_prefix_size
= max
;
8885 max_prefix_size
= align_branch_prefix_size
;
8886 if (max_prefix_size
> count
)
8887 fragP
->tc_frag_data
.max_prefix_length
8888 = max_prefix_size
- count
;
8891 /* Use existing segment prefix if possible. Use CS
8892 segment prefix in 64-bit mode. In 32-bit mode, use SS
8893 segment prefix with ESP/EBP base register and use DS
8894 segment prefix without ESP/EBP base register. */
8895 if (i
.prefix
[SEG_PREFIX
])
8896 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8897 else if (flag_code
== CODE_64BIT
)
8898 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8900 && (i
.base_reg
->reg_num
== 4
8901 || i
.base_reg
->reg_num
== 5))
8902 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8904 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8909 /* NB: Don't work with COND_JUMP86 without i386. */
8910 if (align_branch_power
8911 && now_seg
!= absolute_section
8912 && cpu_arch_flags
.bitfield
.cpui386
)
8914 /* Terminate each frag so that we can add prefix and check for
8916 frag_wane (frag_now
);
8923 pi ("" /*line*/, &i
);
8925 #endif /* DEBUG386 */
8928 /* Return the size of the displacement operand N. */
8931 disp_size (unsigned int n
)
8935 if (i
.types
[n
].bitfield
.disp64
)
8937 else if (i
.types
[n
].bitfield
.disp8
)
8939 else if (i
.types
[n
].bitfield
.disp16
)
8944 /* Return the size of the immediate operand N. */
8947 imm_size (unsigned int n
)
8950 if (i
.types
[n
].bitfield
.imm64
)
8952 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8954 else if (i
.types
[n
].bitfield
.imm16
)
8960 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8965 for (n
= 0; n
< i
.operands
; n
++)
8967 if (operand_type_check (i
.types
[n
], disp
))
8969 if (i
.op
[n
].disps
->X_op
== O_constant
)
8971 int size
= disp_size (n
);
8972 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8974 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8976 p
= frag_more (size
);
8977 md_number_to_chars (p
, val
, size
);
8981 enum bfd_reloc_code_real reloc_type
;
8982 int size
= disp_size (n
);
8983 int sign
= i
.types
[n
].bitfield
.disp32s
;
8984 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8987 /* We can't have 8 bit displacement here. */
8988 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8990 /* The PC relative address is computed relative
8991 to the instruction boundary, so in case immediate
8992 fields follows, we need to adjust the value. */
8993 if (pcrel
&& i
.imm_operands
)
8998 for (n1
= 0; n1
< i
.operands
; n1
++)
8999 if (operand_type_check (i
.types
[n1
], imm
))
9001 /* Only one immediate is allowed for PC
9002 relative address. */
9003 gas_assert (sz
== 0);
9005 i
.op
[n
].disps
->X_add_number
-= sz
;
9007 /* We should find the immediate. */
9008 gas_assert (sz
!= 0);
9011 p
= frag_more (size
);
9012 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9014 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9015 && (((reloc_type
== BFD_RELOC_32
9016 || reloc_type
== BFD_RELOC_X86_64_32S
9017 || (reloc_type
== BFD_RELOC_64
9019 && (i
.op
[n
].disps
->X_op
== O_symbol
9020 || (i
.op
[n
].disps
->X_op
== O_add
9021 && ((symbol_get_value_expression
9022 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9024 || reloc_type
== BFD_RELOC_32_PCREL
))
9028 reloc_type
= BFD_RELOC_386_GOTPC
;
9029 i
.has_gotpc_tls_reloc
= TRUE
;
9030 i
.op
[n
].imms
->X_add_number
+=
9031 encoding_length (insn_start_frag
, insn_start_off
, p
);
9033 else if (reloc_type
== BFD_RELOC_64
)
9034 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9036 /* Don't do the adjustment for x86-64, as there
9037 the pcrel addressing is relative to the _next_
9038 insn, and that is taken care of in other code. */
9039 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9041 else if (align_branch_power
)
9045 case BFD_RELOC_386_TLS_GD
:
9046 case BFD_RELOC_386_TLS_LDM
:
9047 case BFD_RELOC_386_TLS_IE
:
9048 case BFD_RELOC_386_TLS_IE_32
:
9049 case BFD_RELOC_386_TLS_GOTIE
:
9050 case BFD_RELOC_386_TLS_GOTDESC
:
9051 case BFD_RELOC_386_TLS_DESC_CALL
:
9052 case BFD_RELOC_X86_64_TLSGD
:
9053 case BFD_RELOC_X86_64_TLSLD
:
9054 case BFD_RELOC_X86_64_GOTTPOFF
:
9055 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9056 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9057 i
.has_gotpc_tls_reloc
= TRUE
;
9062 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9063 size
, i
.op
[n
].disps
, pcrel
,
9065 /* Check for "call/jmp *mem", "mov mem, %reg",
9066 "test %reg, mem" and "binop mem, %reg" where binop
9067 is one of adc, add, and, cmp, or, sbb, sub, xor
9068 instructions without data prefix. Always generate
9069 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9070 if (i
.prefix
[DATA_PREFIX
] == 0
9071 && (generate_relax_relocations
9074 && i
.rm
.regmem
== 5))
9076 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9077 && ((i
.operands
== 1
9078 && i
.tm
.base_opcode
== 0xff
9079 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9081 && (i
.tm
.base_opcode
== 0x8b
9082 || i
.tm
.base_opcode
== 0x85
9083 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
9087 fixP
->fx_tcbit
= i
.rex
!= 0;
9089 && (i
.base_reg
->reg_num
== RegIP
))
9090 fixP
->fx_tcbit2
= 1;
9093 fixP
->fx_tcbit2
= 1;
9101 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9106 for (n
= 0; n
< i
.operands
; n
++)
9108 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9109 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9112 if (operand_type_check (i
.types
[n
], imm
))
9114 if (i
.op
[n
].imms
->X_op
== O_constant
)
9116 int size
= imm_size (n
);
9119 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9121 p
= frag_more (size
);
9122 md_number_to_chars (p
, val
, size
);
9126 /* Not absolute_section.
9127 Need a 32-bit fixup (don't support 8bit
9128 non-absolute imms). Try to support other
9130 enum bfd_reloc_code_real reloc_type
;
9131 int size
= imm_size (n
);
9134 if (i
.types
[n
].bitfield
.imm32s
9135 && (i
.suffix
== QWORD_MNEM_SUFFIX
9136 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9141 p
= frag_more (size
);
9142 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9144 /* This is tough to explain. We end up with this one if we
9145 * have operands that look like
9146 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9147 * obtain the absolute address of the GOT, and it is strongly
9148 * preferable from a performance point of view to avoid using
9149 * a runtime relocation for this. The actual sequence of
9150 * instructions often look something like:
9155 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9157 * The call and pop essentially return the absolute address
9158 * of the label .L66 and store it in %ebx. The linker itself
9159 * will ultimately change the first operand of the addl so
9160 * that %ebx points to the GOT, but to keep things simple, the
9161 * .o file must have this operand set so that it generates not
9162 * the absolute address of .L66, but the absolute address of
9163 * itself. This allows the linker itself simply treat a GOTPC
9164 * relocation as asking for a pcrel offset to the GOT to be
9165 * added in, and the addend of the relocation is stored in the
9166 * operand field for the instruction itself.
9168 * Our job here is to fix the operand so that it would add
9169 * the correct offset so that %ebx would point to itself. The
9170 * thing that is tricky is that .-.L66 will point to the
9171 * beginning of the instruction, so we need to further modify
9172 * the operand so that it will point to itself. There are
9173 * other cases where you have something like:
9175 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9177 * and here no correction would be required. Internally in
9178 * the assembler we treat operands of this form as not being
9179 * pcrel since the '.' is explicitly mentioned, and I wonder
9180 * whether it would simplify matters to do it this way. Who
9181 * knows. In earlier versions of the PIC patches, the
9182 * pcrel_adjust field was used to store the correction, but
9183 * since the expression is not pcrel, I felt it would be
9184 * confusing to do it this way. */
9186 if ((reloc_type
== BFD_RELOC_32
9187 || reloc_type
== BFD_RELOC_X86_64_32S
9188 || reloc_type
== BFD_RELOC_64
)
9190 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9191 && (i
.op
[n
].imms
->X_op
== O_symbol
9192 || (i
.op
[n
].imms
->X_op
== O_add
9193 && ((symbol_get_value_expression
9194 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9198 reloc_type
= BFD_RELOC_386_GOTPC
;
9200 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9202 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9203 i
.has_gotpc_tls_reloc
= TRUE
;
9204 i
.op
[n
].imms
->X_add_number
+=
9205 encoding_length (insn_start_frag
, insn_start_off
, p
);
9207 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9208 i
.op
[n
].imms
, 0, reloc_type
);
9214 /* x86_cons_fix_new is called via the expression parsing code when a
9215 reloc is needed. We use this hook to get the correct .got reloc. */
9216 static int cons_sign
= -1;
9219 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9220 expressionS
*exp
, bfd_reloc_code_real_type r
)
9222 r
= reloc (len
, 0, cons_sign
, r
);
9225 if (exp
->X_op
== O_secrel
)
9227 exp
->X_op
= O_symbol
;
9228 r
= BFD_RELOC_32_SECREL
;
9232 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9235 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9236 purpose of the `.dc.a' internal pseudo-op. */
9239 x86_address_bytes (void)
9241 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9243 return stdoutput
->arch_info
->bits_per_address
/ 8;
9246 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9248 # define lex_got(reloc, adjust, types) NULL
9250 /* Parse operands of the form
9251 <symbol>@GOTOFF+<nnn>
9252 and similar .plt or .got references.
9254 If we find one, set up the correct relocation in RELOC and copy the
9255 input string, minus the `@GOTOFF' into a malloc'd buffer for
9256 parsing by the calling routine. Return this buffer, and if ADJUST
9257 is non-null set it to the length of the string we removed from the
9258 input line. Otherwise return NULL. */
9260 lex_got (enum bfd_reloc_code_real
*rel
,
9262 i386_operand_type
*types
)
9264 /* Some of the relocations depend on the size of what field is to
9265 be relocated. But in our callers i386_immediate and i386_displacement
9266 we don't yet know the operand size (this will be set by insn
9267 matching). Hence we record the word32 relocation here,
9268 and adjust the reloc according to the real size in reloc(). */
9269 static const struct {
9272 const enum bfd_reloc_code_real rel
[2];
9273 const i386_operand_type types64
;
9275 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9276 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9278 OPERAND_TYPE_IMM32_64
},
9280 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9281 BFD_RELOC_X86_64_PLTOFF64
},
9282 OPERAND_TYPE_IMM64
},
9283 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9284 BFD_RELOC_X86_64_PLT32
},
9285 OPERAND_TYPE_IMM32_32S_DISP32
},
9286 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9287 BFD_RELOC_X86_64_GOTPLT64
},
9288 OPERAND_TYPE_IMM64_DISP64
},
9289 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9290 BFD_RELOC_X86_64_GOTOFF64
},
9291 OPERAND_TYPE_IMM64_DISP64
},
9292 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9293 BFD_RELOC_X86_64_GOTPCREL
},
9294 OPERAND_TYPE_IMM32_32S_DISP32
},
9295 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9296 BFD_RELOC_X86_64_TLSGD
},
9297 OPERAND_TYPE_IMM32_32S_DISP32
},
9298 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9299 _dummy_first_bfd_reloc_code_real
},
9300 OPERAND_TYPE_NONE
},
9301 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9302 BFD_RELOC_X86_64_TLSLD
},
9303 OPERAND_TYPE_IMM32_32S_DISP32
},
9304 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9305 BFD_RELOC_X86_64_GOTTPOFF
},
9306 OPERAND_TYPE_IMM32_32S_DISP32
},
9307 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9308 BFD_RELOC_X86_64_TPOFF32
},
9309 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9310 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9311 _dummy_first_bfd_reloc_code_real
},
9312 OPERAND_TYPE_NONE
},
9313 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9314 BFD_RELOC_X86_64_DTPOFF32
},
9315 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9316 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9317 _dummy_first_bfd_reloc_code_real
},
9318 OPERAND_TYPE_NONE
},
9319 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9320 _dummy_first_bfd_reloc_code_real
},
9321 OPERAND_TYPE_NONE
},
9322 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9323 BFD_RELOC_X86_64_GOT32
},
9324 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9325 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9326 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9327 OPERAND_TYPE_IMM32_32S_DISP32
},
9328 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9329 BFD_RELOC_X86_64_TLSDESC_CALL
},
9330 OPERAND_TYPE_IMM32_32S_DISP32
},
9335 #if defined (OBJ_MAYBE_ELF)
9340 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9341 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9344 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9346 int len
= gotrel
[j
].len
;
9347 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9349 if (gotrel
[j
].rel
[object_64bit
] != 0)
9352 char *tmpbuf
, *past_reloc
;
9354 *rel
= gotrel
[j
].rel
[object_64bit
];
9358 if (flag_code
!= CODE_64BIT
)
9360 types
->bitfield
.imm32
= 1;
9361 types
->bitfield
.disp32
= 1;
9364 *types
= gotrel
[j
].types64
;
9367 if (j
!= 0 && GOT_symbol
== NULL
)
9368 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9370 /* The length of the first part of our input line. */
9371 first
= cp
- input_line_pointer
;
9373 /* The second part goes from after the reloc token until
9374 (and including) an end_of_line char or comma. */
9375 past_reloc
= cp
+ 1 + len
;
9377 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9379 second
= cp
+ 1 - past_reloc
;
9381 /* Allocate and copy string. The trailing NUL shouldn't
9382 be necessary, but be safe. */
9383 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9384 memcpy (tmpbuf
, input_line_pointer
, first
);
9385 if (second
!= 0 && *past_reloc
!= ' ')
9386 /* Replace the relocation token with ' ', so that
9387 errors like foo@GOTOFF1 will be detected. */
9388 tmpbuf
[first
++] = ' ';
9390 /* Increment length by 1 if the relocation token is
9395 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9396 tmpbuf
[first
+ second
] = '\0';
9400 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9401 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9406 /* Might be a symbol version string. Don't as_bad here. */
9415 /* Parse operands of the form
9416 <symbol>@SECREL32+<nnn>
9418 If we find one, set up the correct relocation in RELOC and copy the
9419 input string, minus the `@SECREL32' into a malloc'd buffer for
9420 parsing by the calling routine. Return this buffer, and if ADJUST
9421 is non-null set it to the length of the string we removed from the
9422 input line. Otherwise return NULL.
9424 This function is copied from the ELF version above adjusted for PE targets. */
9427 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9428 int *adjust ATTRIBUTE_UNUSED
,
9429 i386_operand_type
*types
)
9435 const enum bfd_reloc_code_real rel
[2];
9436 const i386_operand_type types64
;
9440 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9441 BFD_RELOC_32_SECREL
},
9442 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9448 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9449 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9452 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9454 int len
= gotrel
[j
].len
;
9456 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9458 if (gotrel
[j
].rel
[object_64bit
] != 0)
9461 char *tmpbuf
, *past_reloc
;
9463 *rel
= gotrel
[j
].rel
[object_64bit
];
9469 if (flag_code
!= CODE_64BIT
)
9471 types
->bitfield
.imm32
= 1;
9472 types
->bitfield
.disp32
= 1;
9475 *types
= gotrel
[j
].types64
;
9478 /* The length of the first part of our input line. */
9479 first
= cp
- input_line_pointer
;
9481 /* The second part goes from after the reloc token until
9482 (and including) an end_of_line char or comma. */
9483 past_reloc
= cp
+ 1 + len
;
9485 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9487 second
= cp
+ 1 - past_reloc
;
9489 /* Allocate and copy string. The trailing NUL shouldn't
9490 be necessary, but be safe. */
9491 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9492 memcpy (tmpbuf
, input_line_pointer
, first
);
9493 if (second
!= 0 && *past_reloc
!= ' ')
9494 /* Replace the relocation token with ' ', so that
9495 errors like foo@SECLREL321 will be detected. */
9496 tmpbuf
[first
++] = ' ';
9497 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9498 tmpbuf
[first
+ second
] = '\0';
9502 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9503 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9508 /* Might be a symbol version string. Don't as_bad here. */
9514 bfd_reloc_code_real_type
9515 x86_cons (expressionS
*exp
, int size
)
9517 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9519 intel_syntax
= -intel_syntax
;
9522 if (size
== 4 || (object_64bit
&& size
== 8))
9524 /* Handle @GOTOFF and the like in an expression. */
9526 char *gotfree_input_line
;
9529 save
= input_line_pointer
;
9530 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9531 if (gotfree_input_line
)
9532 input_line_pointer
= gotfree_input_line
;
9536 if (gotfree_input_line
)
9538 /* expression () has merrily parsed up to the end of line,
9539 or a comma - in the wrong buffer. Transfer how far
9540 input_line_pointer has moved to the right buffer. */
9541 input_line_pointer
= (save
9542 + (input_line_pointer
- gotfree_input_line
)
9544 free (gotfree_input_line
);
9545 if (exp
->X_op
== O_constant
9546 || exp
->X_op
== O_absent
9547 || exp
->X_op
== O_illegal
9548 || exp
->X_op
== O_register
9549 || exp
->X_op
== O_big
)
9551 char c
= *input_line_pointer
;
9552 *input_line_pointer
= 0;
9553 as_bad (_("missing or invalid expression `%s'"), save
);
9554 *input_line_pointer
= c
;
9556 else if ((got_reloc
== BFD_RELOC_386_PLT32
9557 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9558 && exp
->X_op
!= O_symbol
)
9560 char c
= *input_line_pointer
;
9561 *input_line_pointer
= 0;
9562 as_bad (_("invalid PLT expression `%s'"), save
);
9563 *input_line_pointer
= c
;
9570 intel_syntax
= -intel_syntax
;
9573 i386_intel_simplify (exp
);
9579 signed_cons (int size
)
9581 if (flag_code
== CODE_64BIT
)
9589 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9596 if (exp
.X_op
== O_symbol
)
9597 exp
.X_op
= O_secrel
;
9599 emit_expr (&exp
, 4);
9601 while (*input_line_pointer
++ == ',');
9603 input_line_pointer
--;
9604 demand_empty_rest_of_line ();
9608 /* Handle Vector operations. */
9611 check_VecOperations (char *op_string
, char *op_end
)
9613 const reg_entry
*mask
;
9618 && (op_end
== NULL
|| op_string
< op_end
))
9621 if (*op_string
== '{')
9625 /* Check broadcasts. */
9626 if (strncmp (op_string
, "1to", 3) == 0)
9631 goto duplicated_vec_op
;
9634 if (*op_string
== '8')
9636 else if (*op_string
== '4')
9638 else if (*op_string
== '2')
9640 else if (*op_string
== '1'
9641 && *(op_string
+1) == '6')
9648 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9653 broadcast_op
.type
= bcst_type
;
9654 broadcast_op
.operand
= this_operand
;
9655 broadcast_op
.bytes
= 0;
9656 i
.broadcast
= &broadcast_op
;
9658 /* Check masking operation. */
9659 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9661 /* k0 can't be used for write mask. */
9662 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9664 as_bad (_("`%s%s' can't be used for write mask"),
9665 register_prefix
, mask
->reg_name
);
9671 mask_op
.mask
= mask
;
9672 mask_op
.zeroing
= 0;
9673 mask_op
.operand
= this_operand
;
9679 goto duplicated_vec_op
;
9681 i
.mask
->mask
= mask
;
9683 /* Only "{z}" is allowed here. No need to check
9684 zeroing mask explicitly. */
9685 if (i
.mask
->operand
!= this_operand
)
9687 as_bad (_("invalid write mask `%s'"), saved
);
9694 /* Check zeroing-flag for masking operation. */
9695 else if (*op_string
== 'z')
9699 mask_op
.mask
= NULL
;
9700 mask_op
.zeroing
= 1;
9701 mask_op
.operand
= this_operand
;
9706 if (i
.mask
->zeroing
)
9709 as_bad (_("duplicated `%s'"), saved
);
9713 i
.mask
->zeroing
= 1;
9715 /* Only "{%k}" is allowed here. No need to check mask
9716 register explicitly. */
9717 if (i
.mask
->operand
!= this_operand
)
9719 as_bad (_("invalid zeroing-masking `%s'"),
9728 goto unknown_vec_op
;
9730 if (*op_string
!= '}')
9732 as_bad (_("missing `}' in `%s'"), saved
);
9737 /* Strip whitespace since the addition of pseudo prefixes
9738 changed how the scrubber treats '{'. */
9739 if (is_space_char (*op_string
))
9745 /* We don't know this one. */
9746 as_bad (_("unknown vector operation: `%s'"), saved
);
9750 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9752 as_bad (_("zeroing-masking only allowed with write mask"));
9760 i386_immediate (char *imm_start
)
9762 char *save_input_line_pointer
;
9763 char *gotfree_input_line
;
9766 i386_operand_type types
;
9768 operand_type_set (&types
, ~0);
9770 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9772 as_bad (_("at most %d immediate operands are allowed"),
9773 MAX_IMMEDIATE_OPERANDS
);
9777 exp
= &im_expressions
[i
.imm_operands
++];
9778 i
.op
[this_operand
].imms
= exp
;
9780 if (is_space_char (*imm_start
))
9783 save_input_line_pointer
= input_line_pointer
;
9784 input_line_pointer
= imm_start
;
9786 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9787 if (gotfree_input_line
)
9788 input_line_pointer
= gotfree_input_line
;
9790 exp_seg
= expression (exp
);
9794 /* Handle vector operations. */
9795 if (*input_line_pointer
== '{')
9797 input_line_pointer
= check_VecOperations (input_line_pointer
,
9799 if (input_line_pointer
== NULL
)
9803 if (*input_line_pointer
)
9804 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9806 input_line_pointer
= save_input_line_pointer
;
9807 if (gotfree_input_line
)
9809 free (gotfree_input_line
);
9811 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9812 exp
->X_op
= O_illegal
;
9815 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9819 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9820 i386_operand_type types
, const char *imm_start
)
9822 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9825 as_bad (_("missing or invalid immediate expression `%s'"),
9829 else if (exp
->X_op
== O_constant
)
9831 /* Size it properly later. */
9832 i
.types
[this_operand
].bitfield
.imm64
= 1;
9833 /* If not 64bit, sign extend val. */
9834 if (flag_code
!= CODE_64BIT
9835 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9837 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9839 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9840 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9841 && exp_seg
!= absolute_section
9842 && exp_seg
!= text_section
9843 && exp_seg
!= data_section
9844 && exp_seg
!= bss_section
9845 && exp_seg
!= undefined_section
9846 && !bfd_is_com_section (exp_seg
))
9848 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9852 else if (!intel_syntax
&& exp_seg
== reg_section
)
9855 as_bad (_("illegal immediate register operand %s"), imm_start
);
9860 /* This is an address. The size of the address will be
9861 determined later, depending on destination register,
9862 suffix, or the default for the section. */
9863 i
.types
[this_operand
].bitfield
.imm8
= 1;
9864 i
.types
[this_operand
].bitfield
.imm16
= 1;
9865 i
.types
[this_operand
].bitfield
.imm32
= 1;
9866 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9867 i
.types
[this_operand
].bitfield
.imm64
= 1;
9868 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9876 i386_scale (char *scale
)
9879 char *save
= input_line_pointer
;
9881 input_line_pointer
= scale
;
9882 val
= get_absolute_expression ();
9887 i
.log2_scale_factor
= 0;
9890 i
.log2_scale_factor
= 1;
9893 i
.log2_scale_factor
= 2;
9896 i
.log2_scale_factor
= 3;
9900 char sep
= *input_line_pointer
;
9902 *input_line_pointer
= '\0';
9903 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9905 *input_line_pointer
= sep
;
9906 input_line_pointer
= save
;
9910 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9912 as_warn (_("scale factor of %d without an index register"),
9913 1 << i
.log2_scale_factor
);
9914 i
.log2_scale_factor
= 0;
9916 scale
= input_line_pointer
;
9917 input_line_pointer
= save
;
9922 i386_displacement (char *disp_start
, char *disp_end
)
9926 char *save_input_line_pointer
;
9927 char *gotfree_input_line
;
9929 i386_operand_type bigdisp
, types
= anydisp
;
9932 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9934 as_bad (_("at most %d displacement operands are allowed"),
9935 MAX_MEMORY_OPERANDS
);
9939 operand_type_set (&bigdisp
, 0);
9941 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9942 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9944 bigdisp
.bitfield
.disp32
= 1;
9945 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9946 if (flag_code
== CODE_64BIT
)
9950 bigdisp
.bitfield
.disp32s
= 1;
9951 bigdisp
.bitfield
.disp64
= 1;
9954 else if ((flag_code
== CODE_16BIT
) ^ override
)
9956 bigdisp
.bitfield
.disp32
= 0;
9957 bigdisp
.bitfield
.disp16
= 1;
9962 /* For PC-relative branches, the width of the displacement
9963 is dependent upon data size, not address size. */
9964 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9965 if (flag_code
== CODE_64BIT
)
9967 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
9968 bigdisp
.bitfield
.disp16
= 1;
9971 bigdisp
.bitfield
.disp32
= 1;
9972 bigdisp
.bitfield
.disp32s
= 1;
9978 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
9980 : LONG_MNEM_SUFFIX
));
9981 bigdisp
.bitfield
.disp32
= 1;
9982 if ((flag_code
== CODE_16BIT
) ^ override
)
9984 bigdisp
.bitfield
.disp32
= 0;
9985 bigdisp
.bitfield
.disp16
= 1;
9989 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9992 exp
= &disp_expressions
[i
.disp_operands
];
9993 i
.op
[this_operand
].disps
= exp
;
9995 save_input_line_pointer
= input_line_pointer
;
9996 input_line_pointer
= disp_start
;
9997 END_STRING_AND_SAVE (disp_end
);
9999 #ifndef GCC_ASM_O_HACK
10000 #define GCC_ASM_O_HACK 0
10003 END_STRING_AND_SAVE (disp_end
+ 1);
10004 if (i
.types
[this_operand
].bitfield
.baseIndex
10005 && displacement_string_end
[-1] == '+')
10007 /* This hack is to avoid a warning when using the "o"
10008 constraint within gcc asm statements.
10011 #define _set_tssldt_desc(n,addr,limit,type) \
10012 __asm__ __volatile__ ( \
10013 "movw %w2,%0\n\t" \
10014 "movw %w1,2+%0\n\t" \
10015 "rorl $16,%1\n\t" \
10016 "movb %b1,4+%0\n\t" \
10017 "movb %4,5+%0\n\t" \
10018 "movb $0,6+%0\n\t" \
10019 "movb %h1,7+%0\n\t" \
10021 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10023 This works great except that the output assembler ends
10024 up looking a bit weird if it turns out that there is
10025 no offset. You end up producing code that looks like:
10038 So here we provide the missing zero. */
10040 *displacement_string_end
= '0';
10043 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10044 if (gotfree_input_line
)
10045 input_line_pointer
= gotfree_input_line
;
10047 exp_seg
= expression (exp
);
10049 SKIP_WHITESPACE ();
10050 if (*input_line_pointer
)
10051 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10053 RESTORE_END_STRING (disp_end
+ 1);
10055 input_line_pointer
= save_input_line_pointer
;
10056 if (gotfree_input_line
)
10058 free (gotfree_input_line
);
10060 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10061 exp
->X_op
= O_illegal
;
10064 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10066 RESTORE_END_STRING (disp_end
);
10072 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10073 i386_operand_type types
, const char *disp_start
)
10075 i386_operand_type bigdisp
;
10078 /* We do this to make sure that the section symbol is in
10079 the symbol table. We will ultimately change the relocation
10080 to be relative to the beginning of the section. */
10081 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10082 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10083 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10085 if (exp
->X_op
!= O_symbol
)
10088 if (S_IS_LOCAL (exp
->X_add_symbol
)
10089 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10090 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10091 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10092 exp
->X_op
= O_subtract
;
10093 exp
->X_op_symbol
= GOT_symbol
;
10094 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10095 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10096 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10097 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10099 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10102 else if (exp
->X_op
== O_absent
10103 || exp
->X_op
== O_illegal
10104 || exp
->X_op
== O_big
)
10107 as_bad (_("missing or invalid displacement expression `%s'"),
10112 else if (flag_code
== CODE_64BIT
10113 && !i
.prefix
[ADDR_PREFIX
]
10114 && exp
->X_op
== O_constant
)
10116 /* Since displacement is signed extended to 64bit, don't allow
10117 disp32 and turn off disp32s if they are out of range. */
10118 i
.types
[this_operand
].bitfield
.disp32
= 0;
10119 if (!fits_in_signed_long (exp
->X_add_number
))
10121 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10122 if (i
.types
[this_operand
].bitfield
.baseindex
)
10124 as_bad (_("0x%lx out range of signed 32bit displacement"),
10125 (long) exp
->X_add_number
);
10131 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10132 else if (exp
->X_op
!= O_constant
10133 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10134 && exp_seg
!= absolute_section
10135 && exp_seg
!= text_section
10136 && exp_seg
!= data_section
10137 && exp_seg
!= bss_section
10138 && exp_seg
!= undefined_section
10139 && !bfd_is_com_section (exp_seg
))
10141 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10146 /* Check if this is a displacement only operand. */
10147 bigdisp
= i
.types
[this_operand
];
10148 bigdisp
.bitfield
.disp8
= 0;
10149 bigdisp
.bitfield
.disp16
= 0;
10150 bigdisp
.bitfield
.disp32
= 0;
10151 bigdisp
.bitfield
.disp32s
= 0;
10152 bigdisp
.bitfield
.disp64
= 0;
10153 if (operand_type_all_zero (&bigdisp
))
10154 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10160 /* Return the active addressing mode, taking address override and
10161 registers forming the address into consideration. Update the
10162 address override prefix if necessary. */
10164 static enum flag_code
10165 i386_addressing_mode (void)
10167 enum flag_code addr_mode
;
10169 if (i
.prefix
[ADDR_PREFIX
])
10170 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10173 addr_mode
= flag_code
;
10175 #if INFER_ADDR_PREFIX
10176 if (i
.mem_operands
== 0)
10178 /* Infer address prefix from the first memory operand. */
10179 const reg_entry
*addr_reg
= i
.base_reg
;
10181 if (addr_reg
== NULL
)
10182 addr_reg
= i
.index_reg
;
10186 if (addr_reg
->reg_type
.bitfield
.dword
)
10187 addr_mode
= CODE_32BIT
;
10188 else if (flag_code
!= CODE_64BIT
10189 && addr_reg
->reg_type
.bitfield
.word
)
10190 addr_mode
= CODE_16BIT
;
10192 if (addr_mode
!= flag_code
)
10194 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10196 /* Change the size of any displacement too. At most one
10197 of Disp16 or Disp32 is set.
10198 FIXME. There doesn't seem to be any real need for
10199 separate Disp16 and Disp32 flags. The same goes for
10200 Imm16 and Imm32. Removing them would probably clean
10201 up the code quite a lot. */
10202 if (flag_code
!= CODE_64BIT
10203 && (i
.types
[this_operand
].bitfield
.disp16
10204 || i
.types
[this_operand
].bitfield
.disp32
))
10205 i
.types
[this_operand
]
10206 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10216 /* Make sure the memory operand we've been dealt is valid.
10217 Return 1 on success, 0 on a failure. */
10220 i386_index_check (const char *operand_string
)
10222 const char *kind
= "base/index";
10223 enum flag_code addr_mode
= i386_addressing_mode ();
10225 if (current_templates
->start
->opcode_modifier
.isstring
10226 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10227 && (current_templates
->end
[-1].opcode_modifier
.isstring
10228 || i
.mem_operands
))
10230 /* Memory operands of string insns are special in that they only allow
10231 a single register (rDI, rSI, or rBX) as their memory address. */
10232 const reg_entry
*expected_reg
;
10233 static const char *di_si
[][2] =
10239 static const char *bx
[] = { "ebx", "bx", "rbx" };
10241 kind
= "string address";
10243 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10245 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10246 - IS_STRING_ES_OP0
;
10249 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10250 || ((!i
.mem_operands
!= !intel_syntax
)
10251 && current_templates
->end
[-1].operand_types
[1]
10252 .bitfield
.baseindex
))
10254 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10257 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10259 if (i
.base_reg
!= expected_reg
10261 || operand_type_check (i
.types
[this_operand
], disp
))
10263 /* The second memory operand must have the same size as
10267 && !((addr_mode
== CODE_64BIT
10268 && i
.base_reg
->reg_type
.bitfield
.qword
)
10269 || (addr_mode
== CODE_32BIT
10270 ? i
.base_reg
->reg_type
.bitfield
.dword
10271 : i
.base_reg
->reg_type
.bitfield
.word
)))
10274 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10276 intel_syntax
? '[' : '(',
10278 expected_reg
->reg_name
,
10279 intel_syntax
? ']' : ')');
10286 as_bad (_("`%s' is not a valid %s expression"),
10287 operand_string
, kind
);
10292 if (addr_mode
!= CODE_16BIT
)
10294 /* 32-bit/64-bit checks. */
10296 && ((addr_mode
== CODE_64BIT
10297 ? !i
.base_reg
->reg_type
.bitfield
.qword
10298 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10299 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10300 || i
.base_reg
->reg_num
== RegIZ
))
10302 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10303 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10304 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10305 && ((addr_mode
== CODE_64BIT
10306 ? !i
.index_reg
->reg_type
.bitfield
.qword
10307 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10308 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10311 /* bndmk, bndldx, and bndstx have special restrictions. */
10312 if (current_templates
->start
->base_opcode
== 0xf30f1b
10313 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10315 /* They cannot use RIP-relative addressing. */
10316 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10318 as_bad (_("`%s' cannot be used here"), operand_string
);
10322 /* bndldx and bndstx ignore their scale factor. */
10323 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10324 && i
.log2_scale_factor
)
10325 as_warn (_("register scaling is being ignored here"));
10330 /* 16-bit checks. */
10332 && (!i
.base_reg
->reg_type
.bitfield
.word
10333 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10335 && (!i
.index_reg
->reg_type
.bitfield
.word
10336 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10338 && i
.base_reg
->reg_num
< 6
10339 && i
.index_reg
->reg_num
>= 6
10340 && i
.log2_scale_factor
== 0))))
10347 /* Handle vector immediates. */
10350 RC_SAE_immediate (const char *imm_start
)
10352 unsigned int match_found
, j
;
10353 const char *pstr
= imm_start
;
10361 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10363 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10367 rc_op
.type
= RC_NamesTable
[j
].type
;
10368 rc_op
.operand
= this_operand
;
10369 i
.rounding
= &rc_op
;
10373 as_bad (_("duplicated `%s'"), imm_start
);
10376 pstr
+= RC_NamesTable
[j
].len
;
10384 if (*pstr
++ != '}')
10386 as_bad (_("Missing '}': '%s'"), imm_start
);
10389 /* RC/SAE immediate string should contain nothing more. */;
10392 as_bad (_("Junk after '}': '%s'"), imm_start
);
10396 exp
= &im_expressions
[i
.imm_operands
++];
10397 i
.op
[this_operand
].imms
= exp
;
10399 exp
->X_op
= O_constant
;
10400 exp
->X_add_number
= 0;
10401 exp
->X_add_symbol
= (symbolS
*) 0;
10402 exp
->X_op_symbol
= (symbolS
*) 0;
10404 i
.types
[this_operand
].bitfield
.imm8
= 1;
10408 /* Only string instructions can have a second memory operand, so
10409 reduce current_templates to just those if it contains any. */
10411 maybe_adjust_templates (void)
10413 const insn_template
*t
;
10415 gas_assert (i
.mem_operands
== 1);
10417 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10418 if (t
->opcode_modifier
.isstring
)
10421 if (t
< current_templates
->end
)
10423 static templates aux_templates
;
10424 bfd_boolean recheck
;
10426 aux_templates
.start
= t
;
10427 for (; t
< current_templates
->end
; ++t
)
10428 if (!t
->opcode_modifier
.isstring
)
10430 aux_templates
.end
= t
;
10432 /* Determine whether to re-check the first memory operand. */
10433 recheck
= (aux_templates
.start
!= current_templates
->start
10434 || t
!= current_templates
->end
);
10436 current_templates
= &aux_templates
;
10440 i
.mem_operands
= 0;
10441 if (i
.memop1_string
!= NULL
10442 && i386_index_check (i
.memop1_string
) == 0)
10444 i
.mem_operands
= 1;
10451 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10455 i386_att_operand (char *operand_string
)
10457 const reg_entry
*r
;
10459 char *op_string
= operand_string
;
10461 if (is_space_char (*op_string
))
10464 /* We check for an absolute prefix (differentiating,
10465 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10466 if (*op_string
== ABSOLUTE_PREFIX
)
10469 if (is_space_char (*op_string
))
10471 i
.jumpabsolute
= TRUE
;
10474 /* Check if operand is a register. */
10475 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10477 i386_operand_type temp
;
10479 /* Check for a segment override by searching for ':' after a
10480 segment register. */
10481 op_string
= end_op
;
10482 if (is_space_char (*op_string
))
10484 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10486 switch (r
->reg_num
)
10489 i
.seg
[i
.mem_operands
] = &es
;
10492 i
.seg
[i
.mem_operands
] = &cs
;
10495 i
.seg
[i
.mem_operands
] = &ss
;
10498 i
.seg
[i
.mem_operands
] = &ds
;
10501 i
.seg
[i
.mem_operands
] = &fs
;
10504 i
.seg
[i
.mem_operands
] = &gs
;
10508 /* Skip the ':' and whitespace. */
10510 if (is_space_char (*op_string
))
10513 if (!is_digit_char (*op_string
)
10514 && !is_identifier_char (*op_string
)
10515 && *op_string
!= '('
10516 && *op_string
!= ABSOLUTE_PREFIX
)
10518 as_bad (_("bad memory operand `%s'"), op_string
);
10521 /* Handle case of %es:*foo. */
10522 if (*op_string
== ABSOLUTE_PREFIX
)
10525 if (is_space_char (*op_string
))
10527 i
.jumpabsolute
= TRUE
;
10529 goto do_memory_reference
;
10532 /* Handle vector operations. */
10533 if (*op_string
== '{')
10535 op_string
= check_VecOperations (op_string
, NULL
);
10536 if (op_string
== NULL
)
10542 as_bad (_("junk `%s' after register"), op_string
);
10545 temp
= r
->reg_type
;
10546 temp
.bitfield
.baseindex
= 0;
10547 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10549 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10550 i
.op
[this_operand
].regs
= r
;
10553 else if (*op_string
== REGISTER_PREFIX
)
10555 as_bad (_("bad register name `%s'"), op_string
);
10558 else if (*op_string
== IMMEDIATE_PREFIX
)
10561 if (i
.jumpabsolute
)
10563 as_bad (_("immediate operand illegal with absolute jump"));
10566 if (!i386_immediate (op_string
))
10569 else if (RC_SAE_immediate (operand_string
))
10571 /* If it is a RC or SAE immediate, do nothing. */
10574 else if (is_digit_char (*op_string
)
10575 || is_identifier_char (*op_string
)
10576 || *op_string
== '"'
10577 || *op_string
== '(')
10579 /* This is a memory reference of some sort. */
10582 /* Start and end of displacement string expression (if found). */
10583 char *displacement_string_start
;
10584 char *displacement_string_end
;
10587 do_memory_reference
:
10588 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10590 if ((i
.mem_operands
== 1
10591 && !current_templates
->start
->opcode_modifier
.isstring
)
10592 || i
.mem_operands
== 2)
10594 as_bad (_("too many memory references for `%s'"),
10595 current_templates
->start
->name
);
10599 /* Check for base index form. We detect the base index form by
10600 looking for an ')' at the end of the operand, searching
10601 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10603 base_string
= op_string
+ strlen (op_string
);
10605 /* Handle vector operations. */
10606 vop_start
= strchr (op_string
, '{');
10607 if (vop_start
&& vop_start
< base_string
)
10609 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10611 base_string
= vop_start
;
10615 if (is_space_char (*base_string
))
10618 /* If we only have a displacement, set-up for it to be parsed later. */
10619 displacement_string_start
= op_string
;
10620 displacement_string_end
= base_string
+ 1;
10622 if (*base_string
== ')')
10625 unsigned int parens_balanced
= 1;
10626 /* We've already checked that the number of left & right ()'s are
10627 equal, so this loop will not be infinite. */
10631 if (*base_string
== ')')
10633 if (*base_string
== '(')
10636 while (parens_balanced
);
10638 temp_string
= base_string
;
10640 /* Skip past '(' and whitespace. */
10642 if (is_space_char (*base_string
))
10645 if (*base_string
== ','
10646 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10649 displacement_string_end
= temp_string
;
10651 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10655 base_string
= end_op
;
10656 if (is_space_char (*base_string
))
10660 /* There may be an index reg or scale factor here. */
10661 if (*base_string
== ',')
10664 if (is_space_char (*base_string
))
10667 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10670 base_string
= end_op
;
10671 if (is_space_char (*base_string
))
10673 if (*base_string
== ',')
10676 if (is_space_char (*base_string
))
10679 else if (*base_string
!= ')')
10681 as_bad (_("expecting `,' or `)' "
10682 "after index register in `%s'"),
10687 else if (*base_string
== REGISTER_PREFIX
)
10689 end_op
= strchr (base_string
, ',');
10692 as_bad (_("bad register name `%s'"), base_string
);
10696 /* Check for scale factor. */
10697 if (*base_string
!= ')')
10699 char *end_scale
= i386_scale (base_string
);
10704 base_string
= end_scale
;
10705 if (is_space_char (*base_string
))
10707 if (*base_string
!= ')')
10709 as_bad (_("expecting `)' "
10710 "after scale factor in `%s'"),
10715 else if (!i
.index_reg
)
10717 as_bad (_("expecting index register or scale factor "
10718 "after `,'; got '%c'"),
10723 else if (*base_string
!= ')')
10725 as_bad (_("expecting `,' or `)' "
10726 "after base register in `%s'"),
10731 else if (*base_string
== REGISTER_PREFIX
)
10733 end_op
= strchr (base_string
, ',');
10736 as_bad (_("bad register name `%s'"), base_string
);
10741 /* If there's an expression beginning the operand, parse it,
10742 assuming displacement_string_start and
10743 displacement_string_end are meaningful. */
10744 if (displacement_string_start
!= displacement_string_end
)
10746 if (!i386_displacement (displacement_string_start
,
10747 displacement_string_end
))
10751 /* Special case for (%dx) while doing input/output op. */
10753 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10754 && i
.base_reg
->reg_type
.bitfield
.word
10755 && i
.index_reg
== 0
10756 && i
.log2_scale_factor
== 0
10757 && i
.seg
[i
.mem_operands
] == 0
10758 && !operand_type_check (i
.types
[this_operand
], disp
))
10760 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10764 if (i386_index_check (operand_string
) == 0)
10766 i
.flags
[this_operand
] |= Operand_Mem
;
10767 if (i
.mem_operands
== 0)
10768 i
.memop1_string
= xstrdup (operand_string
);
10773 /* It's not a memory operand; argh! */
10774 as_bad (_("invalid char %s beginning operand %d `%s'"),
10775 output_invalid (*op_string
),
10780 return 1; /* Normal return. */
10783 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10784 that an rs_machine_dependent frag may reach. */
10787 i386_frag_max_var (fragS
*frag
)
10789 /* The only relaxable frags are for jumps.
10790 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10791 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10792 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10795 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10797 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10799 /* STT_GNU_IFUNC symbol must go through PLT. */
10800 if ((symbol_get_bfdsym (fr_symbol
)->flags
10801 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10804 if (!S_IS_EXTERNAL (fr_symbol
))
10805 /* Symbol may be weak or local. */
10806 return !S_IS_WEAK (fr_symbol
);
10808 /* Global symbols with non-default visibility can't be preempted. */
10809 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10812 if (fr_var
!= NO_RELOC
)
10813 switch ((enum bfd_reloc_code_real
) fr_var
)
10815 case BFD_RELOC_386_PLT32
:
10816 case BFD_RELOC_X86_64_PLT32
:
10817 /* Symbol with PLT relocation may be preempted. */
10823 /* Global symbols with default visibility in a shared library may be
10824 preempted by another definition. */
10829 /* Return the next non-empty frag. */
10832 i386_next_non_empty_frag (fragS
*fragP
)
10834 /* There may be a frag with a ".fill 0" when there is no room in
10835 the current frag for frag_grow in output_insn. */
10836 for (fragP
= fragP
->fr_next
;
10838 && fragP
->fr_type
== rs_fill
10839 && fragP
->fr_fix
== 0);
10840 fragP
= fragP
->fr_next
)
10845 /* Return the next jcc frag after BRANCH_PADDING. */
10848 i386_next_jcc_frag (fragS
*fragP
)
10853 if (fragP
->fr_type
== rs_machine_dependent
10854 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10855 == BRANCH_PADDING
))
10857 fragP
= i386_next_non_empty_frag (fragP
);
10858 if (fragP
->fr_type
!= rs_machine_dependent
)
10860 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10867 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10870 i386_classify_machine_dependent_frag (fragS
*fragP
)
10874 fragS
*branch_fragP
;
10876 unsigned int max_prefix_length
;
10878 if (fragP
->tc_frag_data
.classified
)
10881 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10882 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10883 for (next_fragP
= fragP
;
10884 next_fragP
!= NULL
;
10885 next_fragP
= next_fragP
->fr_next
)
10887 next_fragP
->tc_frag_data
.classified
= 1;
10888 if (next_fragP
->fr_type
== rs_machine_dependent
)
10889 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10891 case BRANCH_PADDING
:
10892 /* The BRANCH_PADDING frag must be followed by a branch
10894 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10895 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10897 case FUSED_JCC_PADDING
:
10898 /* Check if this is a fused jcc:
10900 CMP like instruction
10904 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10905 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10906 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10909 /* The BRANCH_PADDING frag is merged with the
10910 FUSED_JCC_PADDING frag. */
10911 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10912 /* CMP like instruction size. */
10913 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10914 frag_wane (pad_fragP
);
10915 /* Skip to branch_fragP. */
10916 next_fragP
= branch_fragP
;
10918 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10920 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10922 next_fragP
->fr_subtype
10923 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10924 next_fragP
->tc_frag_data
.max_bytes
10925 = next_fragP
->tc_frag_data
.max_prefix_length
;
10926 /* This will be updated in the BRANCH_PREFIX scan. */
10927 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10930 frag_wane (next_fragP
);
10935 /* Stop if there is no BRANCH_PREFIX. */
10936 if (!align_branch_prefix_size
)
10939 /* Scan for BRANCH_PREFIX. */
10940 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10942 if (fragP
->fr_type
!= rs_machine_dependent
10943 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10947 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10948 COND_JUMP_PREFIX. */
10949 max_prefix_length
= 0;
10950 for (next_fragP
= fragP
;
10951 next_fragP
!= NULL
;
10952 next_fragP
= next_fragP
->fr_next
)
10954 if (next_fragP
->fr_type
== rs_fill
)
10955 /* Skip rs_fill frags. */
10957 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10958 /* Stop for all other frags. */
10961 /* rs_machine_dependent frags. */
10962 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10965 /* Count BRANCH_PREFIX frags. */
10966 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
10968 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
10969 frag_wane (next_fragP
);
10973 += next_fragP
->tc_frag_data
.max_bytes
;
10975 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10977 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
10978 == FUSED_JCC_PADDING
))
10980 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
10981 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
10985 /* Stop for other rs_machine_dependent frags. */
10989 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
10991 /* Skip to the next frag. */
10992 fragP
= next_fragP
;
10996 /* Compute padding size for
10999 CMP like instruction
11001 COND_JUMP/UNCOND_JUMP
11006 COND_JUMP/UNCOND_JUMP
11010 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11012 unsigned int offset
, size
, padding_size
;
11013 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11015 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11017 address
= fragP
->fr_address
;
11018 address
+= fragP
->fr_fix
;
11020 /* CMP like instrunction size. */
11021 size
= fragP
->tc_frag_data
.cmp_size
;
11023 /* The base size of the branch frag. */
11024 size
+= branch_fragP
->fr_fix
;
11026 /* Add opcode and displacement bytes for the rs_machine_dependent
11028 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11029 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11031 /* Check if branch is within boundary and doesn't end at the last
11033 offset
= address
& ((1U << align_branch_power
) - 1);
11034 if ((offset
+ size
) >= (1U << align_branch_power
))
11035 /* Padding needed to avoid crossing boundary. */
11036 padding_size
= (1U << align_branch_power
) - offset
;
11038 /* No padding needed. */
11041 /* The return value may be saved in tc_frag_data.length which is
11043 if (!fits_in_unsigned_byte (padding_size
))
11046 return padding_size
;
11049 /* i386_generic_table_relax_frag()
11051 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11052 grow/shrink padding to align branch frags. Hand others to
11056 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11058 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11059 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11061 long padding_size
= i386_branch_padding_size (fragP
, 0);
11062 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11064 /* When the BRANCH_PREFIX frag is used, the computed address
11065 must match the actual address and there should be no padding. */
11066 if (fragP
->tc_frag_data
.padding_address
11067 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11071 /* Update the padding size. */
11073 fragP
->tc_frag_data
.length
= padding_size
;
11077 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11079 fragS
*padding_fragP
, *next_fragP
;
11080 long padding_size
, left_size
, last_size
;
11082 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11083 if (!padding_fragP
)
11084 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11085 return (fragP
->tc_frag_data
.length
11086 - fragP
->tc_frag_data
.last_length
);
11088 /* Compute the relative address of the padding frag in the very
11089 first time where the BRANCH_PREFIX frag sizes are zero. */
11090 if (!fragP
->tc_frag_data
.padding_address
)
11091 fragP
->tc_frag_data
.padding_address
11092 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11094 /* First update the last length from the previous interation. */
11095 left_size
= fragP
->tc_frag_data
.prefix_length
;
11096 for (next_fragP
= fragP
;
11097 next_fragP
!= padding_fragP
;
11098 next_fragP
= next_fragP
->fr_next
)
11099 if (next_fragP
->fr_type
== rs_machine_dependent
11100 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11105 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11109 if (max
> left_size
)
11114 next_fragP
->tc_frag_data
.last_length
= size
;
11118 next_fragP
->tc_frag_data
.last_length
= 0;
11121 /* Check the padding size for the padding frag. */
11122 padding_size
= i386_branch_padding_size
11123 (padding_fragP
, (fragP
->fr_address
11124 + fragP
->tc_frag_data
.padding_address
));
11126 last_size
= fragP
->tc_frag_data
.prefix_length
;
11127 /* Check if there is change from the last interation. */
11128 if (padding_size
== last_size
)
11130 /* Update the expected address of the padding frag. */
11131 padding_fragP
->tc_frag_data
.padding_address
11132 = (fragP
->fr_address
+ padding_size
11133 + fragP
->tc_frag_data
.padding_address
);
11137 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11139 /* No padding if there is no sufficient room. Clear the
11140 expected address of the padding frag. */
11141 padding_fragP
->tc_frag_data
.padding_address
= 0;
11145 /* Store the expected address of the padding frag. */
11146 padding_fragP
->tc_frag_data
.padding_address
11147 = (fragP
->fr_address
+ padding_size
11148 + fragP
->tc_frag_data
.padding_address
);
11150 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11152 /* Update the length for the current interation. */
11153 left_size
= padding_size
;
11154 for (next_fragP
= fragP
;
11155 next_fragP
!= padding_fragP
;
11156 next_fragP
= next_fragP
->fr_next
)
11157 if (next_fragP
->fr_type
== rs_machine_dependent
11158 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11163 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11167 if (max
> left_size
)
11172 next_fragP
->tc_frag_data
.length
= size
;
11176 next_fragP
->tc_frag_data
.length
= 0;
11179 return (fragP
->tc_frag_data
.length
11180 - fragP
->tc_frag_data
.last_length
);
11182 return relax_frag (segment
, fragP
, stretch
);
11185 /* md_estimate_size_before_relax()
11187 Called just before relax() for rs_machine_dependent frags. The x86
11188 assembler uses these frags to handle variable size jump
11191 Any symbol that is now undefined will not become defined.
11192 Return the correct fr_subtype in the frag.
11193 Return the initial "guess for variable size of frag" to caller.
11194 The guess is actually the growth beyond the fixed part. Whatever
11195 we do to grow the fixed or variable part contributes to our
11199 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11201 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11202 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11203 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11205 i386_classify_machine_dependent_frag (fragP
);
11206 return fragP
->tc_frag_data
.length
;
11209 /* We've already got fragP->fr_subtype right; all we have to do is
11210 check for un-relaxable symbols. On an ELF system, we can't relax
11211 an externally visible symbol, because it may be overridden by a
11213 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11214 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11216 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11219 #if defined (OBJ_COFF) && defined (TE_PE)
11220 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11221 && S_IS_WEAK (fragP
->fr_symbol
))
11225 /* Symbol is undefined in this segment, or we need to keep a
11226 reloc so that weak symbols can be overridden. */
11227 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11228 enum bfd_reloc_code_real reloc_type
;
11229 unsigned char *opcode
;
11232 if (fragP
->fr_var
!= NO_RELOC
)
11233 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11234 else if (size
== 2)
11235 reloc_type
= BFD_RELOC_16_PCREL
;
11236 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11237 else if (need_plt32_p (fragP
->fr_symbol
))
11238 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11241 reloc_type
= BFD_RELOC_32_PCREL
;
11243 old_fr_fix
= fragP
->fr_fix
;
11244 opcode
= (unsigned char *) fragP
->fr_opcode
;
11246 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11249 /* Make jmp (0xeb) a (d)word displacement jump. */
11251 fragP
->fr_fix
+= size
;
11252 fix_new (fragP
, old_fr_fix
, size
,
11254 fragP
->fr_offset
, 1,
11260 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11262 /* Negate the condition, and branch past an
11263 unconditional jump. */
11266 /* Insert an unconditional jump. */
11268 /* We added two extra opcode bytes, and have a two byte
11270 fragP
->fr_fix
+= 2 + 2;
11271 fix_new (fragP
, old_fr_fix
+ 2, 2,
11273 fragP
->fr_offset
, 1,
11277 /* Fall through. */
11280 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11284 fragP
->fr_fix
+= 1;
11285 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11287 fragP
->fr_offset
, 1,
11288 BFD_RELOC_8_PCREL
);
11289 fixP
->fx_signed
= 1;
11293 /* This changes the byte-displacement jump 0x7N
11294 to the (d)word-displacement jump 0x0f,0x8N. */
11295 opcode
[1] = opcode
[0] + 0x10;
11296 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11297 /* We've added an opcode byte. */
11298 fragP
->fr_fix
+= 1 + size
;
11299 fix_new (fragP
, old_fr_fix
+ 1, size
,
11301 fragP
->fr_offset
, 1,
11306 BAD_CASE (fragP
->fr_subtype
);
11310 return fragP
->fr_fix
- old_fr_fix
;
11313 /* Guess size depending on current relax state. Initially the relax
11314 state will correspond to a short jump and we return 1, because
11315 the variable part of the frag (the branch offset) is one byte
11316 long. However, we can relax a section more than once and in that
11317 case we must either set fr_subtype back to the unrelaxed state,
11318 or return the value for the appropriate branch. */
11319 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11322 /* Called after relax() is finished.
11324 In: Address of frag.
11325 fr_type == rs_machine_dependent.
11326 fr_subtype is what the address relaxed to.
11328 Out: Any fixSs and constants are set up.
11329 Caller will turn frag into a ".space 0". */
11332 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11335 unsigned char *opcode
;
11336 unsigned char *where_to_put_displacement
= NULL
;
11337 offsetT target_address
;
11338 offsetT opcode_address
;
11339 unsigned int extension
= 0;
11340 offsetT displacement_from_opcode_start
;
11342 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11343 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11344 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11346 /* Generate nop padding. */
11347 unsigned int size
= fragP
->tc_frag_data
.length
;
11350 if (size
> fragP
->tc_frag_data
.max_bytes
)
11356 const char *branch
= "branch";
11357 const char *prefix
= "";
11358 fragS
*padding_fragP
;
11359 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11362 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11363 switch (fragP
->tc_frag_data
.default_prefix
)
11368 case CS_PREFIX_OPCODE
:
11371 case DS_PREFIX_OPCODE
:
11374 case ES_PREFIX_OPCODE
:
11377 case FS_PREFIX_OPCODE
:
11380 case GS_PREFIX_OPCODE
:
11383 case SS_PREFIX_OPCODE
:
11388 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11389 "%s within %d-byte boundary\n");
11391 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11392 "align %s within %d-byte boundary\n");
11396 padding_fragP
= fragP
;
11397 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11398 "%s within %d-byte boundary\n");
11402 switch (padding_fragP
->tc_frag_data
.branch_type
)
11404 case align_branch_jcc
:
11407 case align_branch_fused
:
11408 branch
= "fused jcc";
11410 case align_branch_jmp
:
11413 case align_branch_call
:
11416 case align_branch_indirect
:
11417 branch
= "indiret branch";
11419 case align_branch_ret
:
11426 fprintf (stdout
, msg
,
11427 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11428 (long long) fragP
->fr_address
, branch
,
11429 1 << align_branch_power
);
11431 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11432 memset (fragP
->fr_opcode
,
11433 fragP
->tc_frag_data
.default_prefix
, size
);
11435 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11437 fragP
->fr_fix
+= size
;
11442 opcode
= (unsigned char *) fragP
->fr_opcode
;
11444 /* Address we want to reach in file space. */
11445 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11447 /* Address opcode resides at in file space. */
11448 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11450 /* Displacement from opcode start to fill into instruction. */
11451 displacement_from_opcode_start
= target_address
- opcode_address
;
11453 if ((fragP
->fr_subtype
& BIG
) == 0)
11455 /* Don't have to change opcode. */
11456 extension
= 1; /* 1 opcode + 1 displacement */
11457 where_to_put_displacement
= &opcode
[1];
11461 if (no_cond_jump_promotion
11462 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11463 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11464 _("long jump required"));
11466 switch (fragP
->fr_subtype
)
11468 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11469 extension
= 4; /* 1 opcode + 4 displacement */
11471 where_to_put_displacement
= &opcode
[1];
11474 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11475 extension
= 2; /* 1 opcode + 2 displacement */
11477 where_to_put_displacement
= &opcode
[1];
11480 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11481 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11482 extension
= 5; /* 2 opcode + 4 displacement */
11483 opcode
[1] = opcode
[0] + 0x10;
11484 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11485 where_to_put_displacement
= &opcode
[2];
11488 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11489 extension
= 3; /* 2 opcode + 2 displacement */
11490 opcode
[1] = opcode
[0] + 0x10;
11491 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11492 where_to_put_displacement
= &opcode
[2];
11495 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11500 where_to_put_displacement
= &opcode
[3];
11504 BAD_CASE (fragP
->fr_subtype
);
11509 /* If size if less then four we are sure that the operand fits,
11510 but if it's 4, then it could be that the displacement is larger
11512 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11514 && ((addressT
) (displacement_from_opcode_start
- extension
11515 + ((addressT
) 1 << 31))
11516 > (((addressT
) 2 << 31) - 1)))
11518 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11519 _("jump target out of range"));
11520 /* Make us emit 0. */
11521 displacement_from_opcode_start
= extension
;
11523 /* Now put displacement after opcode. */
11524 md_number_to_chars ((char *) where_to_put_displacement
,
11525 (valueT
) (displacement_from_opcode_start
- extension
),
11526 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11527 fragP
->fr_fix
+= extension
;
11530 /* Apply a fixup (fixP) to segment data, once it has been determined
11531 by our caller that we have all the info we need to fix it up.
11533 Parameter valP is the pointer to the value of the bits.
11535 On the 386, immediates, displacements, and data pointers are all in
11536 the same (little-endian) format, so we don't need to care about which
11537 we are handling. */
11540 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11542 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11543 valueT value
= *valP
;
11545 #if !defined (TE_Mach)
11546 if (fixP
->fx_pcrel
)
11548 switch (fixP
->fx_r_type
)
11554 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11557 case BFD_RELOC_X86_64_32S
:
11558 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11561 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11564 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11569 if (fixP
->fx_addsy
!= NULL
11570 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11571 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11572 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11573 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11574 && !use_rela_relocations
)
11576 /* This is a hack. There should be a better way to handle this.
11577 This covers for the fact that bfd_install_relocation will
11578 subtract the current location (for partial_inplace, PC relative
11579 relocations); see more below. */
11583 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11586 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11588 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11591 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11593 if ((sym_seg
== seg
11594 || (symbol_section_p (fixP
->fx_addsy
)
11595 && sym_seg
!= absolute_section
))
11596 && !generic_force_reloc (fixP
))
11598 /* Yes, we add the values in twice. This is because
11599 bfd_install_relocation subtracts them out again. I think
11600 bfd_install_relocation is broken, but I don't dare change
11602 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11606 #if defined (OBJ_COFF) && defined (TE_PE)
11607 /* For some reason, the PE format does not store a
11608 section address offset for a PC relative symbol. */
11609 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11610 || S_IS_WEAK (fixP
->fx_addsy
))
11611 value
+= md_pcrel_from (fixP
);
11614 #if defined (OBJ_COFF) && defined (TE_PE)
11615 if (fixP
->fx_addsy
!= NULL
11616 && S_IS_WEAK (fixP
->fx_addsy
)
11617 /* PR 16858: Do not modify weak function references. */
11618 && ! fixP
->fx_pcrel
)
11620 #if !defined (TE_PEP)
11621 /* For x86 PE weak function symbols are neither PC-relative
11622 nor do they set S_IS_FUNCTION. So the only reliable way
11623 to detect them is to check the flags of their containing
11625 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11626 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11630 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11634 /* Fix a few things - the dynamic linker expects certain values here,
11635 and we must not disappoint it. */
11636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11637 if (IS_ELF
&& fixP
->fx_addsy
)
11638 switch (fixP
->fx_r_type
)
11640 case BFD_RELOC_386_PLT32
:
11641 case BFD_RELOC_X86_64_PLT32
:
11642 /* Make the jump instruction point to the address of the operand.
11643 At runtime we merely add the offset to the actual PLT entry.
11644 NB: Subtract the offset size only for jump instructions. */
11645 if (fixP
->fx_pcrel
)
11649 case BFD_RELOC_386_TLS_GD
:
11650 case BFD_RELOC_386_TLS_LDM
:
11651 case BFD_RELOC_386_TLS_IE_32
:
11652 case BFD_RELOC_386_TLS_IE
:
11653 case BFD_RELOC_386_TLS_GOTIE
:
11654 case BFD_RELOC_386_TLS_GOTDESC
:
11655 case BFD_RELOC_X86_64_TLSGD
:
11656 case BFD_RELOC_X86_64_TLSLD
:
11657 case BFD_RELOC_X86_64_GOTTPOFF
:
11658 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11659 value
= 0; /* Fully resolved at runtime. No addend. */
11661 case BFD_RELOC_386_TLS_LE
:
11662 case BFD_RELOC_386_TLS_LDO_32
:
11663 case BFD_RELOC_386_TLS_LE_32
:
11664 case BFD_RELOC_X86_64_DTPOFF32
:
11665 case BFD_RELOC_X86_64_DTPOFF64
:
11666 case BFD_RELOC_X86_64_TPOFF32
:
11667 case BFD_RELOC_X86_64_TPOFF64
:
11668 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11671 case BFD_RELOC_386_TLS_DESC_CALL
:
11672 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11673 value
= 0; /* Fully resolved at runtime. No addend. */
11674 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11678 case BFD_RELOC_VTABLE_INHERIT
:
11679 case BFD_RELOC_VTABLE_ENTRY
:
11686 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11688 #endif /* !defined (TE_Mach) */
11690 /* Are we finished with this relocation now? */
11691 if (fixP
->fx_addsy
== NULL
)
11693 #if defined (OBJ_COFF) && defined (TE_PE)
11694 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11697 /* Remember value for tc_gen_reloc. */
11698 fixP
->fx_addnumber
= value
;
11699 /* Clear out the frag for now. */
11703 else if (use_rela_relocations
)
11705 fixP
->fx_no_overflow
= 1;
11706 /* Remember value for tc_gen_reloc. */
11707 fixP
->fx_addnumber
= value
;
11711 md_number_to_chars (p
, value
, fixP
->fx_size
);
11715 md_atof (int type
, char *litP
, int *sizeP
)
11717 /* This outputs the LITTLENUMs in REVERSE order;
11718 in accord with the bigendian 386. */
11719 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11722 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11725 output_invalid (int c
)
11728 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11731 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11732 "(0x%x)", (unsigned char) c
);
11733 return output_invalid_buf
;
11736 /* REG_STRING starts *before* REGISTER_PREFIX. */
11738 static const reg_entry
*
11739 parse_real_register (char *reg_string
, char **end_op
)
11741 char *s
= reg_string
;
11743 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11744 const reg_entry
*r
;
11746 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11747 if (*s
== REGISTER_PREFIX
)
11750 if (is_space_char (*s
))
11753 p
= reg_name_given
;
11754 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11756 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11757 return (const reg_entry
*) NULL
;
11761 /* For naked regs, make sure that we are not dealing with an identifier.
11762 This prevents confusing an identifier like `eax_var' with register
11764 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11765 return (const reg_entry
*) NULL
;
11769 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11771 /* Handle floating point regs, allowing spaces in the (i) part. */
11772 if (r
== i386_regtab
/* %st is first entry of table */)
11774 if (!cpu_arch_flags
.bitfield
.cpu8087
11775 && !cpu_arch_flags
.bitfield
.cpu287
11776 && !cpu_arch_flags
.bitfield
.cpu387
)
11777 return (const reg_entry
*) NULL
;
11779 if (is_space_char (*s
))
11784 if (is_space_char (*s
))
11786 if (*s
>= '0' && *s
<= '7')
11788 int fpr
= *s
- '0';
11790 if (is_space_char (*s
))
11795 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11800 /* We have "%st(" then garbage. */
11801 return (const reg_entry
*) NULL
;
11805 if (r
== NULL
|| allow_pseudo_reg
)
11808 if (operand_type_all_zero (&r
->reg_type
))
11809 return (const reg_entry
*) NULL
;
11811 if ((r
->reg_type
.bitfield
.dword
11812 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11813 || r
->reg_type
.bitfield
.class == RegCR
11814 || r
->reg_type
.bitfield
.class == RegDR
11815 || r
->reg_type
.bitfield
.class == RegTR
)
11816 && !cpu_arch_flags
.bitfield
.cpui386
)
11817 return (const reg_entry
*) NULL
;
11819 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11820 return (const reg_entry
*) NULL
;
11822 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11824 if (r
->reg_type
.bitfield
.zmmword
11825 || r
->reg_type
.bitfield
.class == RegMask
)
11826 return (const reg_entry
*) NULL
;
11828 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11830 if (r
->reg_type
.bitfield
.ymmword
)
11831 return (const reg_entry
*) NULL
;
11833 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11834 return (const reg_entry
*) NULL
;
11838 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11839 return (const reg_entry
*) NULL
;
11841 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11842 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11843 return (const reg_entry
*) NULL
;
11845 /* Upper 16 vector registers are only available with VREX in 64bit
11846 mode, and require EVEX encoding. */
11847 if (r
->reg_flags
& RegVRex
)
11849 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11850 || flag_code
!= CODE_64BIT
)
11851 return (const reg_entry
*) NULL
;
11853 i
.vec_encoding
= vex_encoding_evex
;
11856 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11857 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11858 && flag_code
!= CODE_64BIT
)
11859 return (const reg_entry
*) NULL
;
11861 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11863 return (const reg_entry
*) NULL
;
11868 /* REG_STRING starts *before* REGISTER_PREFIX. */
11870 static const reg_entry
*
11871 parse_register (char *reg_string
, char **end_op
)
11873 const reg_entry
*r
;
11875 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11876 r
= parse_real_register (reg_string
, end_op
);
11881 char *save
= input_line_pointer
;
11885 input_line_pointer
= reg_string
;
11886 c
= get_symbol_name (®_string
);
11887 symbolP
= symbol_find (reg_string
);
11888 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11890 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11892 know (e
->X_op
== O_register
);
11893 know (e
->X_add_number
>= 0
11894 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11895 r
= i386_regtab
+ e
->X_add_number
;
11896 if ((r
->reg_flags
& RegVRex
))
11897 i
.vec_encoding
= vex_encoding_evex
;
11898 *end_op
= input_line_pointer
;
11900 *input_line_pointer
= c
;
11901 input_line_pointer
= save
;
11907 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11909 const reg_entry
*r
;
11910 char *end
= input_line_pointer
;
11913 r
= parse_register (name
, &input_line_pointer
);
11914 if (r
&& end
<= input_line_pointer
)
11916 *nextcharP
= *input_line_pointer
;
11917 *input_line_pointer
= 0;
11918 e
->X_op
= O_register
;
11919 e
->X_add_number
= r
- i386_regtab
;
11922 input_line_pointer
= end
;
11924 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11928 md_operand (expressionS
*e
)
11931 const reg_entry
*r
;
11933 switch (*input_line_pointer
)
11935 case REGISTER_PREFIX
:
11936 r
= parse_real_register (input_line_pointer
, &end
);
11939 e
->X_op
= O_register
;
11940 e
->X_add_number
= r
- i386_regtab
;
11941 input_line_pointer
= end
;
11946 gas_assert (intel_syntax
);
11947 end
= input_line_pointer
++;
11949 if (*input_line_pointer
== ']')
11951 ++input_line_pointer
;
11952 e
->X_op_symbol
= make_expr_symbol (e
);
11953 e
->X_add_symbol
= NULL
;
11954 e
->X_add_number
= 0;
11959 e
->X_op
= O_absent
;
11960 input_line_pointer
= end
;
11967 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11968 const char *md_shortopts
= "kVQ:sqnO::";
11970 const char *md_shortopts
= "qnO::";
11973 #define OPTION_32 (OPTION_MD_BASE + 0)
11974 #define OPTION_64 (OPTION_MD_BASE + 1)
11975 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11976 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11977 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11978 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11979 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11980 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11981 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11982 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11983 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11984 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11985 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11986 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11987 #define OPTION_X32 (OPTION_MD_BASE + 14)
11988 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11989 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11990 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11991 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11992 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11993 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11994 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11995 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11996 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11997 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11998 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11999 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12000 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12001 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12002 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12004 struct option md_longopts
[] =
12006 {"32", no_argument
, NULL
, OPTION_32
},
12007 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12008 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12009 {"64", no_argument
, NULL
, OPTION_64
},
12011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12012 {"x32", no_argument
, NULL
, OPTION_X32
},
12013 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12014 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12016 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12017 {"march", required_argument
, NULL
, OPTION_MARCH
},
12018 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12019 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12020 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12021 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12022 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12023 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12024 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12025 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12026 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12027 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12028 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12029 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12030 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12031 # if defined (TE_PE) || defined (TE_PEP)
12032 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12034 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12035 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12036 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12037 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12038 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12039 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12040 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12041 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12042 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12043 {NULL
, no_argument
, NULL
, 0}
12045 size_t md_longopts_size
= sizeof (md_longopts
);
12048 md_parse_option (int c
, const char *arg
)
12051 char *arch
, *next
, *saved
, *type
;
12056 optimize_align_code
= 0;
12060 quiet_warnings
= 1;
12063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12064 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12065 should be emitted or not. FIXME: Not implemented. */
12067 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12071 /* -V: SVR4 argument to print version ID. */
12073 print_version_id ();
12076 /* -k: Ignore for FreeBSD compatibility. */
12081 /* -s: On i386 Solaris, this tells the native assembler to use
12082 .stab instead of .stab.excl. We always use .stab anyhow. */
12085 case OPTION_MSHARED
:
12089 case OPTION_X86_USED_NOTE
:
12090 if (strcasecmp (arg
, "yes") == 0)
12092 else if (strcasecmp (arg
, "no") == 0)
12095 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12100 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12101 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12104 const char **list
, **l
;
12106 list
= bfd_target_list ();
12107 for (l
= list
; *l
!= NULL
; l
++)
12108 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12109 || strcmp (*l
, "coff-x86-64") == 0
12110 || strcmp (*l
, "pe-x86-64") == 0
12111 || strcmp (*l
, "pei-x86-64") == 0
12112 || strcmp (*l
, "mach-o-x86-64") == 0)
12114 default_arch
= "x86_64";
12118 as_fatal (_("no compiled in support for x86_64"));
12124 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12128 const char **list
, **l
;
12130 list
= bfd_target_list ();
12131 for (l
= list
; *l
!= NULL
; l
++)
12132 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12134 default_arch
= "x86_64:32";
12138 as_fatal (_("no compiled in support for 32bit x86_64"));
12142 as_fatal (_("32bit x86_64 is only supported for ELF"));
12147 default_arch
= "i386";
12150 case OPTION_DIVIDE
:
12151 #ifdef SVR4_COMMENT_CHARS
12156 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12158 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12162 i386_comment_chars
= n
;
12168 saved
= xstrdup (arg
);
12170 /* Allow -march=+nosse. */
12176 as_fatal (_("invalid -march= option: `%s'"), arg
);
12177 next
= strchr (arch
, '+');
12180 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12182 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12185 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12188 cpu_arch_name
= cpu_arch
[j
].name
;
12189 cpu_sub_arch_name
= NULL
;
12190 cpu_arch_flags
= cpu_arch
[j
].flags
;
12191 cpu_arch_isa
= cpu_arch
[j
].type
;
12192 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12193 if (!cpu_arch_tune_set
)
12195 cpu_arch_tune
= cpu_arch_isa
;
12196 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12200 else if (*cpu_arch
[j
].name
== '.'
12201 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12203 /* ISA extension. */
12204 i386_cpu_flags flags
;
12206 flags
= cpu_flags_or (cpu_arch_flags
,
12207 cpu_arch
[j
].flags
);
12209 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12211 if (cpu_sub_arch_name
)
12213 char *name
= cpu_sub_arch_name
;
12214 cpu_sub_arch_name
= concat (name
,
12216 (const char *) NULL
);
12220 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12221 cpu_arch_flags
= flags
;
12222 cpu_arch_isa_flags
= flags
;
12226 = cpu_flags_or (cpu_arch_isa_flags
,
12227 cpu_arch
[j
].flags
);
12232 if (j
>= ARRAY_SIZE (cpu_arch
))
12234 /* Disable an ISA extension. */
12235 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12236 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12238 i386_cpu_flags flags
;
12240 flags
= cpu_flags_and_not (cpu_arch_flags
,
12241 cpu_noarch
[j
].flags
);
12242 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12244 if (cpu_sub_arch_name
)
12246 char *name
= cpu_sub_arch_name
;
12247 cpu_sub_arch_name
= concat (arch
,
12248 (const char *) NULL
);
12252 cpu_sub_arch_name
= xstrdup (arch
);
12253 cpu_arch_flags
= flags
;
12254 cpu_arch_isa_flags
= flags
;
12259 if (j
>= ARRAY_SIZE (cpu_noarch
))
12260 j
= ARRAY_SIZE (cpu_arch
);
12263 if (j
>= ARRAY_SIZE (cpu_arch
))
12264 as_fatal (_("invalid -march= option: `%s'"), arg
);
12268 while (next
!= NULL
);
12274 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12275 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12277 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12279 cpu_arch_tune_set
= 1;
12280 cpu_arch_tune
= cpu_arch
[j
].type
;
12281 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12285 if (j
>= ARRAY_SIZE (cpu_arch
))
12286 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12289 case OPTION_MMNEMONIC
:
12290 if (strcasecmp (arg
, "att") == 0)
12291 intel_mnemonic
= 0;
12292 else if (strcasecmp (arg
, "intel") == 0)
12293 intel_mnemonic
= 1;
12295 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12298 case OPTION_MSYNTAX
:
12299 if (strcasecmp (arg
, "att") == 0)
12301 else if (strcasecmp (arg
, "intel") == 0)
12304 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12307 case OPTION_MINDEX_REG
:
12308 allow_index_reg
= 1;
12311 case OPTION_MNAKED_REG
:
12312 allow_naked_reg
= 1;
12315 case OPTION_MSSE2AVX
:
12319 case OPTION_MSSE_CHECK
:
12320 if (strcasecmp (arg
, "error") == 0)
12321 sse_check
= check_error
;
12322 else if (strcasecmp (arg
, "warning") == 0)
12323 sse_check
= check_warning
;
12324 else if (strcasecmp (arg
, "none") == 0)
12325 sse_check
= check_none
;
12327 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12330 case OPTION_MOPERAND_CHECK
:
12331 if (strcasecmp (arg
, "error") == 0)
12332 operand_check
= check_error
;
12333 else if (strcasecmp (arg
, "warning") == 0)
12334 operand_check
= check_warning
;
12335 else if (strcasecmp (arg
, "none") == 0)
12336 operand_check
= check_none
;
12338 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12341 case OPTION_MAVXSCALAR
:
12342 if (strcasecmp (arg
, "128") == 0)
12343 avxscalar
= vex128
;
12344 else if (strcasecmp (arg
, "256") == 0)
12345 avxscalar
= vex256
;
12347 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12350 case OPTION_MVEXWIG
:
12351 if (strcmp (arg
, "0") == 0)
12353 else if (strcmp (arg
, "1") == 0)
12356 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12359 case OPTION_MADD_BND_PREFIX
:
12360 add_bnd_prefix
= 1;
12363 case OPTION_MEVEXLIG
:
12364 if (strcmp (arg
, "128") == 0)
12365 evexlig
= evexl128
;
12366 else if (strcmp (arg
, "256") == 0)
12367 evexlig
= evexl256
;
12368 else if (strcmp (arg
, "512") == 0)
12369 evexlig
= evexl512
;
12371 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12374 case OPTION_MEVEXRCIG
:
12375 if (strcmp (arg
, "rne") == 0)
12377 else if (strcmp (arg
, "rd") == 0)
12379 else if (strcmp (arg
, "ru") == 0)
12381 else if (strcmp (arg
, "rz") == 0)
12384 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12387 case OPTION_MEVEXWIG
:
12388 if (strcmp (arg
, "0") == 0)
12390 else if (strcmp (arg
, "1") == 0)
12393 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12396 # if defined (TE_PE) || defined (TE_PEP)
12397 case OPTION_MBIG_OBJ
:
12402 case OPTION_MOMIT_LOCK_PREFIX
:
12403 if (strcasecmp (arg
, "yes") == 0)
12404 omit_lock_prefix
= 1;
12405 else if (strcasecmp (arg
, "no") == 0)
12406 omit_lock_prefix
= 0;
12408 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12411 case OPTION_MFENCE_AS_LOCK_ADD
:
12412 if (strcasecmp (arg
, "yes") == 0)
12414 else if (strcasecmp (arg
, "no") == 0)
12417 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12420 case OPTION_MRELAX_RELOCATIONS
:
12421 if (strcasecmp (arg
, "yes") == 0)
12422 generate_relax_relocations
= 1;
12423 else if (strcasecmp (arg
, "no") == 0)
12424 generate_relax_relocations
= 0;
12426 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12429 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12432 long int align
= strtoul (arg
, &end
, 0);
12437 align_branch_power
= 0;
12440 else if (align
>= 16)
12443 for (align_power
= 0;
12445 align
>>= 1, align_power
++)
12447 /* Limit alignment power to 31. */
12448 if (align
== 1 && align_power
< 32)
12450 align_branch_power
= align_power
;
12455 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12459 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12462 int align
= strtoul (arg
, &end
, 0);
12463 /* Some processors only support 5 prefixes. */
12464 if (*end
== '\0' && align
>= 0 && align
< 6)
12466 align_branch_prefix_size
= align
;
12469 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12474 case OPTION_MALIGN_BRANCH
:
12476 saved
= xstrdup (arg
);
12480 next
= strchr (type
, '+');
12483 if (strcasecmp (type
, "jcc") == 0)
12484 align_branch
|= align_branch_jcc_bit
;
12485 else if (strcasecmp (type
, "fused") == 0)
12486 align_branch
|= align_branch_fused_bit
;
12487 else if (strcasecmp (type
, "jmp") == 0)
12488 align_branch
|= align_branch_jmp_bit
;
12489 else if (strcasecmp (type
, "call") == 0)
12490 align_branch
|= align_branch_call_bit
;
12491 else if (strcasecmp (type
, "ret") == 0)
12492 align_branch
|= align_branch_ret_bit
;
12493 else if (strcasecmp (type
, "indirect") == 0)
12494 align_branch
|= align_branch_indirect_bit
;
12496 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12499 while (next
!= NULL
);
12503 case OPTION_MAMD64
:
12507 case OPTION_MINTEL64
:
12515 /* Turn off -Os. */
12516 optimize_for_space
= 0;
12518 else if (*arg
== 's')
12520 optimize_for_space
= 1;
12521 /* Turn on all encoding optimizations. */
12522 optimize
= INT_MAX
;
12526 optimize
= atoi (arg
);
12527 /* Turn off -Os. */
12528 optimize_for_space
= 0;
12538 #define MESSAGE_TEMPLATE \
12542 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12543 int *left_p
, const char *name
, int len
)
12545 int size
= sizeof (MESSAGE_TEMPLATE
);
12546 int left
= *left_p
;
12548 /* Reserve 2 spaces for ", " or ",\0" */
12551 /* Check if there is any room. */
12559 p
= mempcpy (p
, name
, len
);
12563 /* Output the current message now and start a new one. */
12566 fprintf (stream
, "%s\n", message
);
12568 left
= size
- (start
- message
) - len
- 2;
12570 gas_assert (left
>= 0);
12572 p
= mempcpy (p
, name
, len
);
12580 show_arch (FILE *stream
, int ext
, int check
)
12582 static char message
[] = MESSAGE_TEMPLATE
;
12583 char *start
= message
+ 27;
12585 int size
= sizeof (MESSAGE_TEMPLATE
);
12592 left
= size
- (start
- message
);
12593 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12595 /* Should it be skipped? */
12596 if (cpu_arch
[j
].skip
)
12599 name
= cpu_arch
[j
].name
;
12600 len
= cpu_arch
[j
].len
;
12603 /* It is an extension. Skip if we aren't asked to show it. */
12614 /* It is an processor. Skip if we show only extension. */
12617 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12619 /* It is an impossible processor - skip. */
12623 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12626 /* Display disabled extensions. */
12628 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12630 name
= cpu_noarch
[j
].name
;
12631 len
= cpu_noarch
[j
].len
;
12632 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12637 fprintf (stream
, "%s\n", message
);
12641 md_show_usage (FILE *stream
)
12643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12644 fprintf (stream
, _("\
12645 -Qy, -Qn ignored\n\
12646 -V print assembler version number\n\
12649 fprintf (stream
, _("\
12650 -n Do not optimize code alignment\n\
12651 -q quieten some warnings\n"));
12652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12653 fprintf (stream
, _("\
12656 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12657 || defined (TE_PE) || defined (TE_PEP))
12658 fprintf (stream
, _("\
12659 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12661 #ifdef SVR4_COMMENT_CHARS
12662 fprintf (stream
, _("\
12663 --divide do not treat `/' as a comment character\n"));
12665 fprintf (stream
, _("\
12666 --divide ignored\n"));
12668 fprintf (stream
, _("\
12669 -march=CPU[,+EXTENSION...]\n\
12670 generate code for CPU and EXTENSION, CPU is one of:\n"));
12671 show_arch (stream
, 0, 1);
12672 fprintf (stream
, _("\
12673 EXTENSION is combination of:\n"));
12674 show_arch (stream
, 1, 0);
12675 fprintf (stream
, _("\
12676 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12677 show_arch (stream
, 0, 0);
12678 fprintf (stream
, _("\
12679 -msse2avx encode SSE instructions with VEX prefix\n"));
12680 fprintf (stream
, _("\
12681 -msse-check=[none|error|warning] (default: warning)\n\
12682 check SSE instructions\n"));
12683 fprintf (stream
, _("\
12684 -moperand-check=[none|error|warning] (default: warning)\n\
12685 check operand combinations for validity\n"));
12686 fprintf (stream
, _("\
12687 -mavxscalar=[128|256] (default: 128)\n\
12688 encode scalar AVX instructions with specific vector\n\
12690 fprintf (stream
, _("\
12691 -mvexwig=[0|1] (default: 0)\n\
12692 encode VEX instructions with specific VEX.W value\n\
12693 for VEX.W bit ignored instructions\n"));
12694 fprintf (stream
, _("\
12695 -mevexlig=[128|256|512] (default: 128)\n\
12696 encode scalar EVEX instructions with specific vector\n\
12698 fprintf (stream
, _("\
12699 -mevexwig=[0|1] (default: 0)\n\
12700 encode EVEX instructions with specific EVEX.W value\n\
12701 for EVEX.W bit ignored instructions\n"));
12702 fprintf (stream
, _("\
12703 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12704 encode EVEX instructions with specific EVEX.RC value\n\
12705 for SAE-only ignored instructions\n"));
12706 fprintf (stream
, _("\
12707 -mmnemonic=[att|intel] "));
12708 if (SYSV386_COMPAT
)
12709 fprintf (stream
, _("(default: att)\n"));
12711 fprintf (stream
, _("(default: intel)\n"));
12712 fprintf (stream
, _("\
12713 use AT&T/Intel mnemonic\n"));
12714 fprintf (stream
, _("\
12715 -msyntax=[att|intel] (default: att)\n\
12716 use AT&T/Intel syntax\n"));
12717 fprintf (stream
, _("\
12718 -mindex-reg support pseudo index registers\n"));
12719 fprintf (stream
, _("\
12720 -mnaked-reg don't require `%%' prefix for registers\n"));
12721 fprintf (stream
, _("\
12722 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12723 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12724 fprintf (stream
, _("\
12725 -mshared disable branch optimization for shared code\n"));
12726 fprintf (stream
, _("\
12727 -mx86-used-note=[no|yes] "));
12728 if (DEFAULT_X86_USED_NOTE
)
12729 fprintf (stream
, _("(default: yes)\n"));
12731 fprintf (stream
, _("(default: no)\n"));
12732 fprintf (stream
, _("\
12733 generate x86 used ISA and feature properties\n"));
12735 #if defined (TE_PE) || defined (TE_PEP)
12736 fprintf (stream
, _("\
12737 -mbig-obj generate big object files\n"));
12739 fprintf (stream
, _("\
12740 -momit-lock-prefix=[no|yes] (default: no)\n\
12741 strip all lock prefixes\n"));
12742 fprintf (stream
, _("\
12743 -mfence-as-lock-add=[no|yes] (default: no)\n\
12744 encode lfence, mfence and sfence as\n\
12745 lock addl $0x0, (%%{re}sp)\n"));
12746 fprintf (stream
, _("\
12747 -mrelax-relocations=[no|yes] "));
12748 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12749 fprintf (stream
, _("(default: yes)\n"));
12751 fprintf (stream
, _("(default: no)\n"));
12752 fprintf (stream
, _("\
12753 generate relax relocations\n"));
12754 fprintf (stream
, _("\
12755 -malign-branch-boundary=NUM (default: 0)\n\
12756 align branches within NUM byte boundary\n"));
12757 fprintf (stream
, _("\
12758 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12759 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12761 specify types of branches to align\n"));
12762 fprintf (stream
, _("\
12763 -malign-branch-prefix-size=NUM (default: 5)\n\
12764 align branches with NUM prefixes per instruction\n"));
12765 fprintf (stream
, _("\
12766 -mamd64 accept only AMD64 ISA [default]\n"));
12767 fprintf (stream
, _("\
12768 -mintel64 accept only Intel64 ISA\n"));
12771 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12772 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12773 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12775 /* Pick the target format to use. */
12778 i386_target_format (void)
12780 if (!strncmp (default_arch
, "x86_64", 6))
12782 update_code_flag (CODE_64BIT
, 1);
12783 if (default_arch
[6] == '\0')
12784 x86_elf_abi
= X86_64_ABI
;
12786 x86_elf_abi
= X86_64_X32_ABI
;
12788 else if (!strcmp (default_arch
, "i386"))
12789 update_code_flag (CODE_32BIT
, 1);
12790 else if (!strcmp (default_arch
, "iamcu"))
12792 update_code_flag (CODE_32BIT
, 1);
12793 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12795 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12796 cpu_arch_name
= "iamcu";
12797 cpu_sub_arch_name
= NULL
;
12798 cpu_arch_flags
= iamcu_flags
;
12799 cpu_arch_isa
= PROCESSOR_IAMCU
;
12800 cpu_arch_isa_flags
= iamcu_flags
;
12801 if (!cpu_arch_tune_set
)
12803 cpu_arch_tune
= cpu_arch_isa
;
12804 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12807 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12808 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12812 as_fatal (_("unknown architecture"));
12814 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12815 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12816 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12817 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12819 switch (OUTPUT_FLAVOR
)
12821 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12822 case bfd_target_aout_flavour
:
12823 return AOUT_TARGET_FORMAT
;
12825 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12826 # if defined (TE_PE) || defined (TE_PEP)
12827 case bfd_target_coff_flavour
:
12828 if (flag_code
== CODE_64BIT
)
12829 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12832 # elif defined (TE_GO32)
12833 case bfd_target_coff_flavour
:
12834 return "coff-go32";
12836 case bfd_target_coff_flavour
:
12837 return "coff-i386";
12840 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12841 case bfd_target_elf_flavour
:
12843 const char *format
;
12845 switch (x86_elf_abi
)
12848 format
= ELF_TARGET_FORMAT
;
12850 tls_get_addr
= "___tls_get_addr";
12854 use_rela_relocations
= 1;
12857 tls_get_addr
= "__tls_get_addr";
12859 format
= ELF_TARGET_FORMAT64
;
12861 case X86_64_X32_ABI
:
12862 use_rela_relocations
= 1;
12865 tls_get_addr
= "__tls_get_addr";
12867 disallow_64bit_reloc
= 1;
12868 format
= ELF_TARGET_FORMAT32
;
12871 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12873 if (x86_elf_abi
!= X86_64_ABI
)
12874 as_fatal (_("Intel L1OM is 64bit only"));
12875 return ELF_TARGET_L1OM_FORMAT
;
12877 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12879 if (x86_elf_abi
!= X86_64_ABI
)
12880 as_fatal (_("Intel K1OM is 64bit only"));
12881 return ELF_TARGET_K1OM_FORMAT
;
12883 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12885 if (x86_elf_abi
!= I386_ABI
)
12886 as_fatal (_("Intel MCU is 32bit only"));
12887 return ELF_TARGET_IAMCU_FORMAT
;
12893 #if defined (OBJ_MACH_O)
12894 case bfd_target_mach_o_flavour
:
12895 if (flag_code
== CODE_64BIT
)
12897 use_rela_relocations
= 1;
12899 return "mach-o-x86-64";
12902 return "mach-o-i386";
12910 #endif /* OBJ_MAYBE_ more than one */
12913 md_undefined_symbol (char *name
)
12915 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12916 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12917 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12918 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12922 if (symbol_find (name
))
12923 as_bad (_("GOT already in symbol table"));
12924 GOT_symbol
= symbol_new (name
, undefined_section
,
12925 (valueT
) 0, &zero_address_frag
);
12932 /* Round up a section size to the appropriate boundary. */
12935 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12937 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12938 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12940 /* For a.out, force the section size to be aligned. If we don't do
12941 this, BFD will align it for us, but it will not write out the
12942 final bytes of the section. This may be a bug in BFD, but it is
12943 easier to fix it here since that is how the other a.out targets
12947 align
= bfd_section_alignment (segment
);
12948 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
12955 /* On the i386, PC-relative offsets are relative to the start of the
12956 next instruction. That is, the address of the offset, plus its
12957 size, since the offset is always the last part of the insn. */
12960 md_pcrel_from (fixS
*fixP
)
12962 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12968 s_bss (int ignore ATTRIBUTE_UNUSED
)
12972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12974 obj_elf_section_change_hook ();
12976 temp
= get_absolute_expression ();
12977 subseg_set (bss_section
, (subsegT
) temp
);
12978 demand_empty_rest_of_line ();
12983 /* Remember constant directive. */
12986 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
12988 if (last_insn
.kind
!= last_insn_directive
12989 && (bfd_section_flags (now_seg
) & SEC_CODE
))
12991 last_insn
.seg
= now_seg
;
12992 last_insn
.kind
= last_insn_directive
;
12993 last_insn
.name
= "constant directive";
12994 last_insn
.file
= as_where (&last_insn
.line
);
12999 i386_validate_fix (fixS
*fixp
)
13001 if (fixp
->fx_subsy
)
13003 if (fixp
->fx_subsy
== GOT_symbol
)
13005 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13009 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13010 if (fixp
->fx_tcbit2
)
13011 fixp
->fx_r_type
= (fixp
->fx_tcbit
13012 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13013 : BFD_RELOC_X86_64_GOTPCRELX
);
13016 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13021 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13023 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13025 fixp
->fx_subsy
= 0;
13028 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13029 else if (!object_64bit
)
13031 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13032 && fixp
->fx_tcbit2
)
13033 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13039 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13042 bfd_reloc_code_real_type code
;
13044 switch (fixp
->fx_r_type
)
13046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13047 case BFD_RELOC_SIZE32
:
13048 case BFD_RELOC_SIZE64
:
13049 if (S_IS_DEFINED (fixp
->fx_addsy
)
13050 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13052 /* Resolve size relocation against local symbol to size of
13053 the symbol plus addend. */
13054 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13055 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13056 && !fits_in_unsigned_long (value
))
13057 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13058 _("symbol size computation overflow"));
13059 fixp
->fx_addsy
= NULL
;
13060 fixp
->fx_subsy
= NULL
;
13061 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13065 /* Fall through. */
13067 case BFD_RELOC_X86_64_PLT32
:
13068 case BFD_RELOC_X86_64_GOT32
:
13069 case BFD_RELOC_X86_64_GOTPCREL
:
13070 case BFD_RELOC_X86_64_GOTPCRELX
:
13071 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13072 case BFD_RELOC_386_PLT32
:
13073 case BFD_RELOC_386_GOT32
:
13074 case BFD_RELOC_386_GOT32X
:
13075 case BFD_RELOC_386_GOTOFF
:
13076 case BFD_RELOC_386_GOTPC
:
13077 case BFD_RELOC_386_TLS_GD
:
13078 case BFD_RELOC_386_TLS_LDM
:
13079 case BFD_RELOC_386_TLS_LDO_32
:
13080 case BFD_RELOC_386_TLS_IE_32
:
13081 case BFD_RELOC_386_TLS_IE
:
13082 case BFD_RELOC_386_TLS_GOTIE
:
13083 case BFD_RELOC_386_TLS_LE_32
:
13084 case BFD_RELOC_386_TLS_LE
:
13085 case BFD_RELOC_386_TLS_GOTDESC
:
13086 case BFD_RELOC_386_TLS_DESC_CALL
:
13087 case BFD_RELOC_X86_64_TLSGD
:
13088 case BFD_RELOC_X86_64_TLSLD
:
13089 case BFD_RELOC_X86_64_DTPOFF32
:
13090 case BFD_RELOC_X86_64_DTPOFF64
:
13091 case BFD_RELOC_X86_64_GOTTPOFF
:
13092 case BFD_RELOC_X86_64_TPOFF32
:
13093 case BFD_RELOC_X86_64_TPOFF64
:
13094 case BFD_RELOC_X86_64_GOTOFF64
:
13095 case BFD_RELOC_X86_64_GOTPC32
:
13096 case BFD_RELOC_X86_64_GOT64
:
13097 case BFD_RELOC_X86_64_GOTPCREL64
:
13098 case BFD_RELOC_X86_64_GOTPC64
:
13099 case BFD_RELOC_X86_64_GOTPLT64
:
13100 case BFD_RELOC_X86_64_PLTOFF64
:
13101 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13102 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13103 case BFD_RELOC_RVA
:
13104 case BFD_RELOC_VTABLE_ENTRY
:
13105 case BFD_RELOC_VTABLE_INHERIT
:
13107 case BFD_RELOC_32_SECREL
:
13109 code
= fixp
->fx_r_type
;
13111 case BFD_RELOC_X86_64_32S
:
13112 if (!fixp
->fx_pcrel
)
13114 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13115 code
= fixp
->fx_r_type
;
13118 /* Fall through. */
13120 if (fixp
->fx_pcrel
)
13122 switch (fixp
->fx_size
)
13125 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13126 _("can not do %d byte pc-relative relocation"),
13128 code
= BFD_RELOC_32_PCREL
;
13130 case 1: code
= BFD_RELOC_8_PCREL
; break;
13131 case 2: code
= BFD_RELOC_16_PCREL
; break;
13132 case 4: code
= BFD_RELOC_32_PCREL
; break;
13134 case 8: code
= BFD_RELOC_64_PCREL
; break;
13140 switch (fixp
->fx_size
)
13143 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13144 _("can not do %d byte relocation"),
13146 code
= BFD_RELOC_32
;
13148 case 1: code
= BFD_RELOC_8
; break;
13149 case 2: code
= BFD_RELOC_16
; break;
13150 case 4: code
= BFD_RELOC_32
; break;
13152 case 8: code
= BFD_RELOC_64
; break;
13159 if ((code
== BFD_RELOC_32
13160 || code
== BFD_RELOC_32_PCREL
13161 || code
== BFD_RELOC_X86_64_32S
)
13163 && fixp
->fx_addsy
== GOT_symbol
)
13166 code
= BFD_RELOC_386_GOTPC
;
13168 code
= BFD_RELOC_X86_64_GOTPC32
;
13170 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13172 && fixp
->fx_addsy
== GOT_symbol
)
13174 code
= BFD_RELOC_X86_64_GOTPC64
;
13177 rel
= XNEW (arelent
);
13178 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13179 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13181 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13183 if (!use_rela_relocations
)
13185 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13186 vtable entry to be used in the relocation's section offset. */
13187 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13188 rel
->address
= fixp
->fx_offset
;
13189 #if defined (OBJ_COFF) && defined (TE_PE)
13190 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13191 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13196 /* Use the rela in 64bit mode. */
13199 if (disallow_64bit_reloc
)
13202 case BFD_RELOC_X86_64_DTPOFF64
:
13203 case BFD_RELOC_X86_64_TPOFF64
:
13204 case BFD_RELOC_64_PCREL
:
13205 case BFD_RELOC_X86_64_GOTOFF64
:
13206 case BFD_RELOC_X86_64_GOT64
:
13207 case BFD_RELOC_X86_64_GOTPCREL64
:
13208 case BFD_RELOC_X86_64_GOTPC64
:
13209 case BFD_RELOC_X86_64_GOTPLT64
:
13210 case BFD_RELOC_X86_64_PLTOFF64
:
13211 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13212 _("cannot represent relocation type %s in x32 mode"),
13213 bfd_get_reloc_code_name (code
));
13219 if (!fixp
->fx_pcrel
)
13220 rel
->addend
= fixp
->fx_offset
;
13224 case BFD_RELOC_X86_64_PLT32
:
13225 case BFD_RELOC_X86_64_GOT32
:
13226 case BFD_RELOC_X86_64_GOTPCREL
:
13227 case BFD_RELOC_X86_64_GOTPCRELX
:
13228 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13229 case BFD_RELOC_X86_64_TLSGD
:
13230 case BFD_RELOC_X86_64_TLSLD
:
13231 case BFD_RELOC_X86_64_GOTTPOFF
:
13232 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13233 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13234 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13237 rel
->addend
= (section
->vma
13239 + fixp
->fx_addnumber
13240 + md_pcrel_from (fixp
));
13245 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13246 if (rel
->howto
== NULL
)
13248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13249 _("cannot represent relocation type %s"),
13250 bfd_get_reloc_code_name (code
));
13251 /* Set howto to a garbage value so that we can keep going. */
13252 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13253 gas_assert (rel
->howto
!= NULL
);
13259 #include "tc-i386-intel.c"
13262 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13264 int saved_naked_reg
;
13265 char saved_register_dot
;
13267 saved_naked_reg
= allow_naked_reg
;
13268 allow_naked_reg
= 1;
13269 saved_register_dot
= register_chars
['.'];
13270 register_chars
['.'] = '.';
13271 allow_pseudo_reg
= 1;
13272 expression_and_evaluate (exp
);
13273 allow_pseudo_reg
= 0;
13274 register_chars
['.'] = saved_register_dot
;
13275 allow_naked_reg
= saved_naked_reg
;
13277 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13279 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13281 exp
->X_op
= O_constant
;
13282 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13283 .dw2_regnum
[flag_code
>> 1];
13286 exp
->X_op
= O_illegal
;
13291 tc_x86_frame_initial_instructions (void)
13293 static unsigned int sp_regno
[2];
13295 if (!sp_regno
[flag_code
>> 1])
13297 char *saved_input
= input_line_pointer
;
13298 char sp
[][4] = {"esp", "rsp"};
13301 input_line_pointer
= sp
[flag_code
>> 1];
13302 tc_x86_parse_to_dw2regnum (&exp
);
13303 gas_assert (exp
.X_op
== O_constant
);
13304 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13305 input_line_pointer
= saved_input
;
13308 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13309 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13313 x86_dwarf2_addr_size (void)
13315 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13316 if (x86_elf_abi
== X86_64_X32_ABI
)
13319 return bfd_arch_bits_per_address (stdoutput
) / 8;
13323 i386_elf_section_type (const char *str
, size_t len
)
13325 if (flag_code
== CODE_64BIT
13326 && len
== sizeof ("unwind") - 1
13327 && strncmp (str
, "unwind", 6) == 0)
13328 return SHT_X86_64_UNWIND
;
13335 i386_solaris_fix_up_eh_frame (segT sec
)
13337 if (flag_code
== CODE_64BIT
)
13338 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13344 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13348 exp
.X_op
= O_secrel
;
13349 exp
.X_add_symbol
= symbol
;
13350 exp
.X_add_number
= 0;
13351 emit_expr (&exp
, size
);
13355 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13356 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13359 x86_64_section_letter (int letter
, const char **ptr_msg
)
13361 if (flag_code
== CODE_64BIT
)
13364 return SHF_X86_64_LARGE
;
13366 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13369 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13374 x86_64_section_word (char *str
, size_t len
)
13376 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13377 return SHF_X86_64_LARGE
;
13383 handle_large_common (int small ATTRIBUTE_UNUSED
)
13385 if (flag_code
!= CODE_64BIT
)
13387 s_comm_internal (0, elf_common_parse
);
13388 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13392 static segT lbss_section
;
13393 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13394 asection
*saved_bss_section
= bss_section
;
13396 if (lbss_section
== NULL
)
13398 flagword applicable
;
13399 segT seg
= now_seg
;
13400 subsegT subseg
= now_subseg
;
13402 /* The .lbss section is for local .largecomm symbols. */
13403 lbss_section
= subseg_new (".lbss", 0);
13404 applicable
= bfd_applicable_section_flags (stdoutput
);
13405 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13406 seg_info (lbss_section
)->bss
= 1;
13408 subseg_set (seg
, subseg
);
13411 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13412 bss_section
= lbss_section
;
13414 s_comm_internal (0, elf_common_parse
);
13416 elf_com_section_ptr
= saved_com_section_ptr
;
13417 bss_section
= saved_bss_section
;
13420 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */