1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template
*start
;
114 const insn_template
*end
;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem
; /* codes register or memory operand */
122 unsigned int reg
; /* codes register operand (or extended opcode) */
123 unsigned int mode
; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte
;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 enum processor_type type
; /* arch type */
145 i386_cpu_flags flags
; /* cpu feature flags */
146 unsigned int skip
; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name
; /* arch name */
154 unsigned int len
; /* arch string length */
155 i386_cpu_flags flags
; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c
);
172 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
174 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS
*);
179 static int i386_intel_parse_name (const char *, expressionS
*);
180 static const reg_entry
*parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static enum flag_code
i386_addressing_mode (void);
186 static void optimize_imm (void);
187 static void optimize_disp (void);
188 static const insn_template
*match_template (char);
189 static int check_string (void);
190 static int process_suffix (void);
191 static int check_byte_reg (void);
192 static int check_long_reg (void);
193 static int check_qword_reg (void);
194 static int check_word_reg (void);
195 static int finalize_imm (void);
196 static int process_operands (void);
197 static const seg_entry
*build_modrm_byte (void);
198 static void output_insn (void);
199 static void output_imm (fragS
*, offsetT
);
200 static void output_disp (fragS
*, offsetT
);
202 static void s_bss (int);
204 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
205 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
207 /* GNU_PROPERTY_X86_ISA_1_USED. */
208 static unsigned int x86_isa_1_used
;
209 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
210 static unsigned int x86_feature_2_used
;
211 /* Generate x86 used ISA and feature properties. */
212 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
215 static const char *default_arch
= DEFAULT_ARCH
;
217 /* This struct describes rounding control and SAE in the instruction. */
231 static struct RC_Operation rc_op
;
233 /* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236 struct Mask_Operation
238 const reg_entry
*mask
;
239 unsigned int zeroing
;
240 /* The operand where this operation is associated. */
244 static struct Mask_Operation mask_op
;
246 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
248 struct Broadcast_Operation
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
253 /* Index of broadcasted operand. */
256 /* Number of bytes to broadcast. */
260 static struct Broadcast_Operation broadcast_op
;
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes
[4];
268 /* Destination or source register specifier. */
269 const reg_entry
*register_specifier
;
272 /* 'md_assemble ()' gathers together information and puts it into a
279 const reg_entry
*regs
;
284 operand_size_mismatch
,
285 operand_type_mismatch
,
286 register_type_mismatch
,
287 number_of_operands_mismatch
,
288 invalid_instruction_suffix
,
290 unsupported_with_intel_mnemonic
,
293 invalid_vsib_address
,
294 invalid_vector_register_set
,
295 unsupported_vector_index_register
,
296 unsupported_broadcast
,
299 mask_not_on_destination
,
302 rc_sae_operand_not_last_imm
,
303 invalid_register_operand
,
308 /* TM holds the template for the insn were currently assembling. */
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands
;
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
321 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types
[MAX_OPERANDS
];
327 /* Displacement expression, immediate expression, or register for each
329 union i386_op op
[MAX_OPERANDS
];
331 /* Flags for operands. */
332 unsigned int flags
[MAX_OPERANDS
];
333 #define Operand_PCrel 1
334 #define Operand_Mem 2
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry
*base_reg
;
342 const reg_entry
*index_reg
;
343 unsigned int log2_scale_factor
;
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry
*seg
[2];
349 /* Copied first memory operand string, for re-checking. */
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes
;
355 unsigned char prefix
[MAX_PREFIXES
];
357 /* The operand to a branch insn indicates an absolute branch. */
358 bfd_boolean jumpabsolute
;
360 /* Has MMX register operands. */
361 bfd_boolean has_regmmx
;
363 /* Has XMM register operands. */
364 bfd_boolean has_regxmm
;
366 /* Has YMM register operands. */
367 bfd_boolean has_regymm
;
369 /* Has ZMM register operands. */
370 bfd_boolean has_regzmm
;
372 /* Has GOTPC or TLS relocation. */
373 bfd_boolean has_gotpc_tls_reloc
;
375 /* RM and SIB are the modrm byte and the sib byte where the
376 addressing modes of this insn are encoded. */
383 /* Masking attributes. */
384 struct Mask_Operation
*mask
;
386 /* Rounding control and SAE attributes. */
387 struct RC_Operation
*rounding
;
389 /* Broadcasting attributes. */
390 struct Broadcast_Operation
*broadcast
;
392 /* Compressed disp8*N attribute. */
393 unsigned int memshift
;
395 /* Prefer load or store in encoding. */
398 dir_encoding_default
= 0,
404 /* Prefer 8bit or 32bit displacement in encoding. */
407 disp_encoding_default
= 0,
412 /* Prefer the REX byte in encoding. */
413 bfd_boolean rex_encoding
;
415 /* Disable instruction size optimization. */
416 bfd_boolean no_optimize
;
418 /* How to encode vector instructions. */
421 vex_encoding_default
= 0,
428 const char *rep_prefix
;
431 const char *hle_prefix
;
433 /* Have BND prefix. */
434 const char *bnd_prefix
;
436 /* Have NOTRACK prefix. */
437 const char *notrack_prefix
;
440 enum i386_error error
;
443 typedef struct _i386_insn i386_insn
;
445 /* Link RC type with corresponding string, that'll be looked for in
454 static const struct RC_name RC_NamesTable
[] =
456 { rne
, STRING_COMMA_LEN ("rn-sae") },
457 { rd
, STRING_COMMA_LEN ("rd-sae") },
458 { ru
, STRING_COMMA_LEN ("ru-sae") },
459 { rz
, STRING_COMMA_LEN ("rz-sae") },
460 { saeonly
, STRING_COMMA_LEN ("sae") },
463 /* List of chars besides those in app.c:symbol_chars that can start an
464 operand. Used to prevent the scrubber eating vital white-space. */
465 const char extra_symbol_chars
[] = "*%-([{}"
474 #if (defined (TE_I386AIX) \
475 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
476 && !defined (TE_GNU) \
477 && !defined (TE_LINUX) \
478 && !defined (TE_NACL) \
479 && !defined (TE_FreeBSD) \
480 && !defined (TE_DragonFly) \
481 && !defined (TE_NetBSD)))
482 /* This array holds the chars that always start a comment. If the
483 pre-processor is disabled, these aren't very useful. The option
484 --divide will remove '/' from this list. */
485 const char *i386_comment_chars
= "#/";
486 #define SVR4_COMMENT_CHARS 1
487 #define PREFIX_SEPARATOR '\\'
490 const char *i386_comment_chars
= "#";
491 #define PREFIX_SEPARATOR '/'
494 /* This array holds the chars that only start a comment at the beginning of
495 a line. If the line seems to have the form '# 123 filename'
496 .line and .file directives will appear in the pre-processed output.
497 Note that input_file.c hand checks for '#' at the beginning of the
498 first line of the input file. This is because the compiler outputs
499 #NO_APP at the beginning of its output.
500 Also note that comments started like this one will always work if
501 '/' isn't otherwise defined. */
502 const char line_comment_chars
[] = "#/";
504 const char line_separator_chars
[] = ";";
506 /* Chars that can be used to separate mant from exp in floating point
508 const char EXP_CHARS
[] = "eE";
510 /* Chars that mean this number is a floating point constant
513 const char FLT_CHARS
[] = "fFdDxX";
515 /* Tables for lexical analysis. */
516 static char mnemonic_chars
[256];
517 static char register_chars
[256];
518 static char operand_chars
[256];
519 static char identifier_chars
[256];
520 static char digit_chars
[256];
522 /* Lexical macros. */
523 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
524 #define is_operand_char(x) (operand_chars[(unsigned char) x])
525 #define is_register_char(x) (register_chars[(unsigned char) x])
526 #define is_space_char(x) ((x) == ' ')
527 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
528 #define is_digit_char(x) (digit_chars[(unsigned char) x])
530 /* All non-digit non-letter characters that may occur in an operand. */
531 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
533 /* md_assemble() always leaves the strings it's passed unaltered. To
534 effect this we maintain a stack of saved characters that we've smashed
535 with '\0's (indicating end of strings for various sub-fields of the
536 assembler instruction). */
537 static char save_stack
[32];
538 static char *save_stack_p
;
539 #define END_STRING_AND_SAVE(s) \
540 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
541 #define RESTORE_END_STRING(s) \
542 do { *(s) = *--save_stack_p; } while (0)
544 /* The instruction we're assembling. */
547 /* Possible templates for current insn. */
548 static const templates
*current_templates
;
550 /* Per instruction expressionS buffers: max displacements & immediates. */
551 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
552 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
554 /* Current operand we are working on. */
555 static int this_operand
= -1;
557 /* We support four different modes. FLAG_CODE variable is used to distinguish
565 static enum flag_code flag_code
;
566 static unsigned int object_64bit
;
567 static unsigned int disallow_64bit_reloc
;
568 static int use_rela_relocations
= 0;
569 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
570 static const char *tls_get_addr
;
572 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
573 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
574 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
576 /* The ELF ABI to use. */
584 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
587 #if defined (TE_PE) || defined (TE_PEP)
588 /* Use big object file format. */
589 static int use_big_obj
= 0;
592 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
593 /* 1 if generating code for a shared library. */
594 static int shared
= 0;
597 /* 1 for intel syntax,
599 static int intel_syntax
= 0;
601 /* 1 for Intel64 ISA,
605 /* 1 for intel mnemonic,
606 0 if att mnemonic. */
607 static int intel_mnemonic
= !SYSV386_COMPAT
;
609 /* 1 if pseudo registers are permitted. */
610 static int allow_pseudo_reg
= 0;
612 /* 1 if register prefix % not required. */
613 static int allow_naked_reg
= 0;
615 /* 1 if the assembler should add BND prefix for all control-transferring
616 instructions supporting it, even if this prefix wasn't specified
618 static int add_bnd_prefix
= 0;
620 /* 1 if pseudo index register, eiz/riz, is allowed . */
621 static int allow_index_reg
= 0;
623 /* 1 if the assembler should ignore LOCK prefix, even if it was
624 specified explicitly. */
625 static int omit_lock_prefix
= 0;
627 /* 1 if the assembler should encode lfence, mfence, and sfence as
628 "lock addl $0, (%{re}sp)". */
629 static int avoid_fence
= 0;
631 /* Type of the previous instruction. */
646 /* 1 if the assembler should generate relax relocations. */
648 static int generate_relax_relocations
649 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
651 static enum check_kind
657 sse_check
, operand_check
= check_warning
;
659 /* Non-zero if branches should be aligned within power of 2 boundary. */
660 static int align_branch_power
= 0;
662 /* Types of branches to align. */
663 enum align_branch_kind
665 align_branch_none
= 0,
666 align_branch_jcc
= 1,
667 align_branch_fused
= 2,
668 align_branch_jmp
= 3,
669 align_branch_call
= 4,
670 align_branch_indirect
= 5,
674 /* Type bits of branches to align. */
675 enum align_branch_bit
677 align_branch_jcc_bit
= 1 << align_branch_jcc
,
678 align_branch_fused_bit
= 1 << align_branch_fused
,
679 align_branch_jmp_bit
= 1 << align_branch_jmp
,
680 align_branch_call_bit
= 1 << align_branch_call
,
681 align_branch_indirect_bit
= 1 << align_branch_indirect
,
682 align_branch_ret_bit
= 1 << align_branch_ret
685 static unsigned int align_branch
= (align_branch_jcc_bit
686 | align_branch_fused_bit
687 | align_branch_jmp_bit
);
689 /* The maximum padding size for fused jcc. CMP like instruction can
690 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
692 #define MAX_FUSED_JCC_PADDING_SIZE 20
694 /* The maximum number of prefixes added for an instruction. */
695 static unsigned int align_branch_prefix_size
= 5;
698 1. Clear the REX_W bit with register operand if possible.
699 2. Above plus use 128bit vector instruction to clear the full vector
702 static int optimize
= 0;
705 1. Clear the REX_W bit with register operand if possible.
706 2. Above plus use 128bit vector instruction to clear the full vector
708 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
711 static int optimize_for_space
= 0;
713 /* Register prefix used for error message. */
714 static const char *register_prefix
= "%";
716 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
717 leave, push, and pop instructions so that gcc has the same stack
718 frame as in 32 bit mode. */
719 static char stackop_size
= '\0';
721 /* Non-zero to optimize code alignment. */
722 int optimize_align_code
= 1;
724 /* Non-zero to quieten some warnings. */
725 static int quiet_warnings
= 0;
728 static const char *cpu_arch_name
= NULL
;
729 static char *cpu_sub_arch_name
= NULL
;
731 /* CPU feature flags. */
732 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
734 /* If we have selected a cpu we are generating instructions for. */
735 static int cpu_arch_tune_set
= 0;
737 /* Cpu we are generating instructions for. */
738 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
740 /* CPU feature flags of cpu we are generating instructions for. */
741 static i386_cpu_flags cpu_arch_tune_flags
;
743 /* CPU instruction set architecture used. */
744 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
746 /* CPU feature flags of instruction set architecture used. */
747 i386_cpu_flags cpu_arch_isa_flags
;
749 /* If set, conditional jumps are not automatically promoted to handle
750 larger than a byte offset. */
751 static unsigned int no_cond_jump_promotion
= 0;
753 /* Encode SSE instructions with VEX prefix. */
754 static unsigned int sse2avx
;
756 /* Encode scalar AVX instructions with specific vector length. */
763 /* Encode VEX WIG instructions with specific vex.w. */
770 /* Encode scalar EVEX LIG instructions with specific vector length. */
778 /* Encode EVEX WIG instructions with specific evex.w. */
785 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
786 static enum rc_type evexrcig
= rne
;
788 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
789 static symbolS
*GOT_symbol
;
791 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
792 unsigned int x86_dwarf2_return_column
;
794 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
795 int x86_cie_data_alignment
;
797 /* Interface to relax_segment.
798 There are 3 major relax states for 386 jump insns because the
799 different types of jumps add different sizes to frags when we're
800 figuring out what sort of jump to choose to reach a given label.
802 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
803 branches which are handled by md_estimate_size_before_relax() and
804 i386_generic_table_relax_frag(). */
807 #define UNCOND_JUMP 0
809 #define COND_JUMP86 2
810 #define BRANCH_PADDING 3
811 #define BRANCH_PREFIX 4
812 #define FUSED_JCC_PADDING 5
817 #define SMALL16 (SMALL | CODE16)
819 #define BIG16 (BIG | CODE16)
823 #define INLINE __inline__
829 #define ENCODE_RELAX_STATE(type, size) \
830 ((relax_substateT) (((type) << 2) | (size)))
831 #define TYPE_FROM_RELAX_STATE(s) \
833 #define DISP_SIZE_FROM_RELAX_STATE(s) \
834 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
836 /* This table is used by relax_frag to promote short jumps to long
837 ones where necessary. SMALL (short) jumps may be promoted to BIG
838 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
839 don't allow a short jump in a 32 bit code segment to be promoted to
840 a 16 bit offset jump because it's slower (requires data size
841 prefix), and doesn't work, unless the destination is in the bottom
842 64k of the code segment (The top 16 bits of eip are zeroed). */
844 const relax_typeS md_relax_table
[] =
847 1) most positive reach of this state,
848 2) most negative reach of this state,
849 3) how many bytes this mode will have in the variable part of the frag
850 4) which index into the table to try if we can't fit into this one. */
852 /* UNCOND_JUMP states. */
853 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
854 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
855 /* dword jmp adds 4 bytes to frag:
856 0 extra opcode bytes, 4 displacement bytes. */
858 /* word jmp adds 2 byte2 to frag:
859 0 extra opcode bytes, 2 displacement bytes. */
862 /* COND_JUMP states. */
863 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
864 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
865 /* dword conditionals adds 5 bytes to frag:
866 1 extra opcode byte, 4 displacement bytes. */
868 /* word conditionals add 3 bytes to frag:
869 1 extra opcode byte, 2 displacement bytes. */
872 /* COND_JUMP86 states. */
873 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
874 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
875 /* dword conditionals adds 5 bytes to frag:
876 1 extra opcode byte, 4 displacement bytes. */
878 /* word conditionals add 4 bytes to frag:
879 1 displacement byte and a 3 byte long branch insn. */
883 static const arch_entry cpu_arch
[] =
885 /* Do not replace the first two entries - i386_target_format()
886 relies on them being there in this order. */
887 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
888 CPU_GENERIC32_FLAGS
, 0 },
889 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
890 CPU_GENERIC64_FLAGS
, 0 },
891 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
893 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
895 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
897 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
899 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
901 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
903 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
905 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
907 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
908 CPU_PENTIUMPRO_FLAGS
, 0 },
909 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
911 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
913 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
915 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
917 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
918 CPU_NOCONA_FLAGS
, 0 },
919 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
921 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
923 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
924 CPU_CORE2_FLAGS
, 1 },
925 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
926 CPU_CORE2_FLAGS
, 0 },
927 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
928 CPU_COREI7_FLAGS
, 0 },
929 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
931 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
933 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
934 CPU_IAMCU_FLAGS
, 0 },
935 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
937 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
939 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
940 CPU_ATHLON_FLAGS
, 0 },
941 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
943 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
945 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
947 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
948 CPU_AMDFAM10_FLAGS
, 0 },
949 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
950 CPU_BDVER1_FLAGS
, 0 },
951 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
952 CPU_BDVER2_FLAGS
, 0 },
953 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
954 CPU_BDVER3_FLAGS
, 0 },
955 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
956 CPU_BDVER4_FLAGS
, 0 },
957 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
958 CPU_ZNVER1_FLAGS
, 0 },
959 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER
,
960 CPU_ZNVER2_FLAGS
, 0 },
961 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
962 CPU_BTVER1_FLAGS
, 0 },
963 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
964 CPU_BTVER2_FLAGS
, 0 },
965 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
967 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
969 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
971 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN
,
973 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN
,
975 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN
,
977 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
979 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
981 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
983 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
985 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
986 CPU_SSSE3_FLAGS
, 0 },
987 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
988 CPU_SSE4_1_FLAGS
, 0 },
989 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
990 CPU_SSE4_2_FLAGS
, 0 },
991 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
992 CPU_SSE4_2_FLAGS
, 0 },
993 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
995 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
997 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
998 CPU_AVX512F_FLAGS
, 0 },
999 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
1000 CPU_AVX512CD_FLAGS
, 0 },
1001 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
1002 CPU_AVX512ER_FLAGS
, 0 },
1003 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
1004 CPU_AVX512PF_FLAGS
, 0 },
1005 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
1006 CPU_AVX512DQ_FLAGS
, 0 },
1007 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
1008 CPU_AVX512BW_FLAGS
, 0 },
1009 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
1010 CPU_AVX512VL_FLAGS
, 0 },
1011 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
1013 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
1014 CPU_VMFUNC_FLAGS
, 0 },
1015 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
1017 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
1018 CPU_XSAVE_FLAGS
, 0 },
1019 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
1020 CPU_XSAVEOPT_FLAGS
, 0 },
1021 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
1022 CPU_XSAVEC_FLAGS
, 0 },
1023 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
1024 CPU_XSAVES_FLAGS
, 0 },
1025 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
1027 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
1028 CPU_PCLMUL_FLAGS
, 0 },
1029 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
1030 CPU_PCLMUL_FLAGS
, 1 },
1031 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
1032 CPU_FSGSBASE_FLAGS
, 0 },
1033 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
1034 CPU_RDRND_FLAGS
, 0 },
1035 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
1036 CPU_F16C_FLAGS
, 0 },
1037 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
1038 CPU_BMI2_FLAGS
, 0 },
1039 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
1041 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
1042 CPU_FMA4_FLAGS
, 0 },
1043 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
1045 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
1047 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
1048 CPU_MOVBE_FLAGS
, 0 },
1049 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
1050 CPU_CX16_FLAGS
, 0 },
1051 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
1053 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
1054 CPU_LZCNT_FLAGS
, 0 },
1055 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
1057 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
1059 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
1060 CPU_INVPCID_FLAGS
, 0 },
1061 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
1062 CPU_CLFLUSH_FLAGS
, 0 },
1063 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
1065 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
1066 CPU_SYSCALL_FLAGS
, 0 },
1067 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
1068 CPU_RDTSCP_FLAGS
, 0 },
1069 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
1070 CPU_3DNOW_FLAGS
, 0 },
1071 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
1072 CPU_3DNOWA_FLAGS
, 0 },
1073 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
1074 CPU_PADLOCK_FLAGS
, 0 },
1075 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
1076 CPU_SVME_FLAGS
, 1 },
1077 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
1078 CPU_SVME_FLAGS
, 0 },
1079 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
1080 CPU_SSE4A_FLAGS
, 0 },
1081 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
1083 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
1085 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
1087 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
1089 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
1090 CPU_RDSEED_FLAGS
, 0 },
1091 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
1092 CPU_PRFCHW_FLAGS
, 0 },
1093 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
1094 CPU_SMAP_FLAGS
, 0 },
1095 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
1097 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
1099 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
1100 CPU_CLFLUSHOPT_FLAGS
, 0 },
1101 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
1102 CPU_PREFETCHWT1_FLAGS
, 0 },
1103 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
1105 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
1106 CPU_CLWB_FLAGS
, 0 },
1107 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
1108 CPU_AVX512IFMA_FLAGS
, 0 },
1109 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
1110 CPU_AVX512VBMI_FLAGS
, 0 },
1111 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN
,
1112 CPU_AVX512_4FMAPS_FLAGS
, 0 },
1113 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN
,
1114 CPU_AVX512_4VNNIW_FLAGS
, 0 },
1115 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN
,
1116 CPU_AVX512_VPOPCNTDQ_FLAGS
, 0 },
1117 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN
,
1118 CPU_AVX512_VBMI2_FLAGS
, 0 },
1119 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN
,
1120 CPU_AVX512_VNNI_FLAGS
, 0 },
1121 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN
,
1122 CPU_AVX512_BITALG_FLAGS
, 0 },
1123 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
1124 CPU_CLZERO_FLAGS
, 0 },
1125 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
1126 CPU_MWAITX_FLAGS
, 0 },
1127 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
1128 CPU_OSPKE_FLAGS
, 0 },
1129 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
1130 CPU_RDPID_FLAGS
, 0 },
1131 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN
,
1132 CPU_PTWRITE_FLAGS
, 0 },
1133 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN
,
1135 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN
,
1136 CPU_SHSTK_FLAGS
, 0 },
1137 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN
,
1138 CPU_GFNI_FLAGS
, 0 },
1139 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN
,
1140 CPU_VAES_FLAGS
, 0 },
1141 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN
,
1142 CPU_VPCLMULQDQ_FLAGS
, 0 },
1143 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN
,
1144 CPU_WBNOINVD_FLAGS
, 0 },
1145 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN
,
1146 CPU_PCONFIG_FLAGS
, 0 },
1147 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN
,
1148 CPU_WAITPKG_FLAGS
, 0 },
1149 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN
,
1150 CPU_CLDEMOTE_FLAGS
, 0 },
1151 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN
,
1152 CPU_MOVDIRI_FLAGS
, 0 },
1153 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN
,
1154 CPU_MOVDIR64B_FLAGS
, 0 },
1155 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN
,
1156 CPU_AVX512_BF16_FLAGS
, 0 },
1157 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN
,
1158 CPU_AVX512_VP2INTERSECT_FLAGS
, 0 },
1159 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN
,
1160 CPU_ENQCMD_FLAGS
, 0 },
1161 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN
,
1162 CPU_RDPRU_FLAGS
, 0 },
1163 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN
,
1164 CPU_MCOMMIT_FLAGS
, 0 },
1167 static const noarch_entry cpu_noarch
[] =
1169 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
1170 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS
},
1171 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS
},
1172 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS
},
1173 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS
},
1174 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS
},
1175 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
1176 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
1177 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS
},
1178 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS
},
1179 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS
},
1180 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS
},
1181 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS
},
1182 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS
},
1183 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
1184 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS
},
1185 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS
},
1186 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS
},
1187 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS
},
1188 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS
},
1189 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS
},
1190 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS
},
1191 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS
},
1192 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS
},
1193 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS
},
1194 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS
},
1195 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS
},
1196 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS
},
1197 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS
},
1198 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS
},
1199 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS
},
1200 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS
},
1201 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS
},
1202 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS
},
1203 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS
},
1204 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS
},
1205 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS
},
1206 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS
},
1210 /* Like s_lcomm_internal in gas/read.c but the alignment string
1211 is allowed to be optional. */
1214 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1221 && *input_line_pointer
== ',')
1223 align
= parse_align (needs_align
- 1);
1225 if (align
== (addressT
) -1)
1240 bss_alloc (symbolP
, size
, align
);
1245 pe_lcomm (int needs_align
)
1247 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1251 const pseudo_typeS md_pseudo_table
[] =
1253 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1254 {"align", s_align_bytes
, 0},
1256 {"align", s_align_ptwo
, 0},
1258 {"arch", set_cpu_arch
, 0},
1262 {"lcomm", pe_lcomm
, 1},
1264 {"ffloat", float_cons
, 'f'},
1265 {"dfloat", float_cons
, 'd'},
1266 {"tfloat", float_cons
, 'x'},
1268 {"slong", signed_cons
, 4},
1269 {"noopt", s_ignore
, 0},
1270 {"optim", s_ignore
, 0},
1271 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1272 {"code16", set_code_flag
, CODE_16BIT
},
1273 {"code32", set_code_flag
, CODE_32BIT
},
1275 {"code64", set_code_flag
, CODE_64BIT
},
1277 {"intel_syntax", set_intel_syntax
, 1},
1278 {"att_syntax", set_intel_syntax
, 0},
1279 {"intel_mnemonic", set_intel_mnemonic
, 1},
1280 {"att_mnemonic", set_intel_mnemonic
, 0},
1281 {"allow_index_reg", set_allow_index_reg
, 1},
1282 {"disallow_index_reg", set_allow_index_reg
, 0},
1283 {"sse_check", set_check
, 0},
1284 {"operand_check", set_check
, 1},
1285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1286 {"largecomm", handle_large_common
, 0},
1288 {"file", dwarf2_directive_file
, 0},
1289 {"loc", dwarf2_directive_loc
, 0},
1290 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1293 {"secrel32", pe_directive_secrel
, 0},
1298 /* For interface with expression (). */
1299 extern char *input_line_pointer
;
1301 /* Hash table for instruction mnemonic lookup. */
1302 static struct hash_control
*op_hash
;
1304 /* Hash table for register lookup. */
1305 static struct hash_control
*reg_hash
;
1307 /* Various efficient no-op patterns for aligning code labels.
1308 Note: Don't try to assemble the instructions in the comments.
1309 0L and 0w are not legal. */
1310 static const unsigned char f32_1
[] =
1312 static const unsigned char f32_2
[] =
1313 {0x66,0x90}; /* xchg %ax,%ax */
1314 static const unsigned char f32_3
[] =
1315 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1316 static const unsigned char f32_4
[] =
1317 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1318 static const unsigned char f32_6
[] =
1319 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1320 static const unsigned char f32_7
[] =
1321 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1322 static const unsigned char f16_3
[] =
1323 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1324 static const unsigned char f16_4
[] =
1325 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1326 static const unsigned char jump_disp8
[] =
1327 {0xeb}; /* jmp disp8 */
1328 static const unsigned char jump32_disp32
[] =
1329 {0xe9}; /* jmp disp32 */
1330 static const unsigned char jump16_disp32
[] =
1331 {0x66,0xe9}; /* jmp disp32 */
1332 /* 32-bit NOPs patterns. */
1333 static const unsigned char *const f32_patt
[] = {
1334 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1336 /* 16-bit NOPs patterns. */
1337 static const unsigned char *const f16_patt
[] = {
1338 f32_1
, f32_2
, f16_3
, f16_4
1340 /* nopl (%[re]ax) */
1341 static const unsigned char alt_3
[] =
1343 /* nopl 0(%[re]ax) */
1344 static const unsigned char alt_4
[] =
1345 {0x0f,0x1f,0x40,0x00};
1346 /* nopl 0(%[re]ax,%[re]ax,1) */
1347 static const unsigned char alt_5
[] =
1348 {0x0f,0x1f,0x44,0x00,0x00};
1349 /* nopw 0(%[re]ax,%[re]ax,1) */
1350 static const unsigned char alt_6
[] =
1351 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1352 /* nopl 0L(%[re]ax) */
1353 static const unsigned char alt_7
[] =
1354 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1355 /* nopl 0L(%[re]ax,%[re]ax,1) */
1356 static const unsigned char alt_8
[] =
1357 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1358 /* nopw 0L(%[re]ax,%[re]ax,1) */
1359 static const unsigned char alt_9
[] =
1360 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1361 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1362 static const unsigned char alt_10
[] =
1363 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1364 /* data16 nopw %cs:0L(%eax,%eax,1) */
1365 static const unsigned char alt_11
[] =
1366 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1367 /* 32-bit and 64-bit NOPs patterns. */
1368 static const unsigned char *const alt_patt
[] = {
1369 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1370 alt_9
, alt_10
, alt_11
1373 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1374 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1377 i386_output_nops (char *where
, const unsigned char *const *patt
,
1378 int count
, int max_single_nop_size
)
1381 /* Place the longer NOP first. */
1384 const unsigned char *nops
;
1386 if (max_single_nop_size
< 1)
1388 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1389 max_single_nop_size
);
1393 nops
= patt
[max_single_nop_size
- 1];
1395 /* Use the smaller one if the requsted one isn't available. */
1398 max_single_nop_size
--;
1399 nops
= patt
[max_single_nop_size
- 1];
1402 last
= count
% max_single_nop_size
;
1405 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1406 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1410 nops
= patt
[last
- 1];
1413 /* Use the smaller one plus one-byte NOP if the needed one
1416 nops
= patt
[last
- 1];
1417 memcpy (where
+ offset
, nops
, last
);
1418 where
[offset
+ last
] = *patt
[0];
1421 memcpy (where
+ offset
, nops
, last
);
1426 fits_in_imm7 (offsetT num
)
1428 return (num
& 0x7f) == num
;
1432 fits_in_imm31 (offsetT num
)
1434 return (num
& 0x7fffffff) == num
;
1437 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1438 single NOP instruction LIMIT. */
1441 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1443 const unsigned char *const *patt
= NULL
;
1444 int max_single_nop_size
;
1445 /* Maximum number of NOPs before switching to jump over NOPs. */
1446 int max_number_of_nops
;
1448 switch (fragP
->fr_type
)
1453 case rs_machine_dependent
:
1454 /* Allow NOP padding for jumps and calls. */
1455 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1456 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1463 /* We need to decide which NOP sequence to use for 32bit and
1464 64bit. When -mtune= is used:
1466 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1467 PROCESSOR_GENERIC32, f32_patt will be used.
1468 2. For the rest, alt_patt will be used.
1470 When -mtune= isn't used, alt_patt will be used if
1471 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1474 When -march= or .arch is used, we can't use anything beyond
1475 cpu_arch_isa_flags. */
1477 if (flag_code
== CODE_16BIT
)
1480 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1481 /* Limit number of NOPs to 2 in 16-bit mode. */
1482 max_number_of_nops
= 2;
1486 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1488 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1489 switch (cpu_arch_tune
)
1491 case PROCESSOR_UNKNOWN
:
1492 /* We use cpu_arch_isa_flags to check if we SHOULD
1493 optimize with nops. */
1494 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1499 case PROCESSOR_PENTIUM4
:
1500 case PROCESSOR_NOCONA
:
1501 case PROCESSOR_CORE
:
1502 case PROCESSOR_CORE2
:
1503 case PROCESSOR_COREI7
:
1504 case PROCESSOR_L1OM
:
1505 case PROCESSOR_K1OM
:
1506 case PROCESSOR_GENERIC64
:
1508 case PROCESSOR_ATHLON
:
1510 case PROCESSOR_AMDFAM10
:
1512 case PROCESSOR_ZNVER
:
1516 case PROCESSOR_I386
:
1517 case PROCESSOR_I486
:
1518 case PROCESSOR_PENTIUM
:
1519 case PROCESSOR_PENTIUMPRO
:
1520 case PROCESSOR_IAMCU
:
1521 case PROCESSOR_GENERIC32
:
1528 switch (fragP
->tc_frag_data
.tune
)
1530 case PROCESSOR_UNKNOWN
:
1531 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1532 PROCESSOR_UNKNOWN. */
1536 case PROCESSOR_I386
:
1537 case PROCESSOR_I486
:
1538 case PROCESSOR_PENTIUM
:
1539 case PROCESSOR_IAMCU
:
1541 case PROCESSOR_ATHLON
:
1543 case PROCESSOR_AMDFAM10
:
1545 case PROCESSOR_ZNVER
:
1547 case PROCESSOR_GENERIC32
:
1548 /* We use cpu_arch_isa_flags to check if we CAN optimize
1550 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1555 case PROCESSOR_PENTIUMPRO
:
1556 case PROCESSOR_PENTIUM4
:
1557 case PROCESSOR_NOCONA
:
1558 case PROCESSOR_CORE
:
1559 case PROCESSOR_CORE2
:
1560 case PROCESSOR_COREI7
:
1561 case PROCESSOR_L1OM
:
1562 case PROCESSOR_K1OM
:
1563 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1568 case PROCESSOR_GENERIC64
:
1574 if (patt
== f32_patt
)
1576 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1577 /* Limit number of NOPs to 2 for older processors. */
1578 max_number_of_nops
= 2;
1582 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1583 /* Limit number of NOPs to 7 for newer processors. */
1584 max_number_of_nops
= 7;
1589 limit
= max_single_nop_size
;
1591 if (fragP
->fr_type
== rs_fill_nop
)
1593 /* Output NOPs for .nop directive. */
1594 if (limit
> max_single_nop_size
)
1596 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1597 _("invalid single nop size: %d "
1598 "(expect within [0, %d])"),
1599 limit
, max_single_nop_size
);
1603 else if (fragP
->fr_type
!= rs_machine_dependent
)
1604 fragP
->fr_var
= count
;
1606 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1608 /* Generate jump over NOPs. */
1609 offsetT disp
= count
- 2;
1610 if (fits_in_imm7 (disp
))
1612 /* Use "jmp disp8" if possible. */
1614 where
[0] = jump_disp8
[0];
1620 unsigned int size_of_jump
;
1622 if (flag_code
== CODE_16BIT
)
1624 where
[0] = jump16_disp32
[0];
1625 where
[1] = jump16_disp32
[1];
1630 where
[0] = jump32_disp32
[0];
1634 count
-= size_of_jump
+ 4;
1635 if (!fits_in_imm31 (count
))
1637 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1638 _("jump over nop padding out of range"));
1642 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1643 where
+= size_of_jump
+ 4;
1647 /* Generate multiple NOPs. */
1648 i386_output_nops (where
, patt
, count
, limit
);
1652 operand_type_all_zero (const union i386_operand_type
*x
)
1654 switch (ARRAY_SIZE(x
->array
))
1665 return !x
->array
[0];
1672 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1674 switch (ARRAY_SIZE(x
->array
))
1690 x
->bitfield
.class = ClassNone
;
1691 x
->bitfield
.instance
= InstanceNone
;
1695 operand_type_equal (const union i386_operand_type
*x
,
1696 const union i386_operand_type
*y
)
1698 switch (ARRAY_SIZE(x
->array
))
1701 if (x
->array
[2] != y
->array
[2])
1705 if (x
->array
[1] != y
->array
[1])
1709 return x
->array
[0] == y
->array
[0];
1717 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1719 switch (ARRAY_SIZE(x
->array
))
1734 return !x
->array
[0];
1741 cpu_flags_equal (const union i386_cpu_flags
*x
,
1742 const union i386_cpu_flags
*y
)
1744 switch (ARRAY_SIZE(x
->array
))
1747 if (x
->array
[3] != y
->array
[3])
1751 if (x
->array
[2] != y
->array
[2])
1755 if (x
->array
[1] != y
->array
[1])
1759 return x
->array
[0] == y
->array
[0];
1767 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1769 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1770 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1773 static INLINE i386_cpu_flags
1774 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1776 switch (ARRAY_SIZE (x
.array
))
1779 x
.array
[3] &= y
.array
[3];
1782 x
.array
[2] &= y
.array
[2];
1785 x
.array
[1] &= y
.array
[1];
1788 x
.array
[0] &= y
.array
[0];
1796 static INLINE i386_cpu_flags
1797 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1799 switch (ARRAY_SIZE (x
.array
))
1802 x
.array
[3] |= y
.array
[3];
1805 x
.array
[2] |= y
.array
[2];
1808 x
.array
[1] |= y
.array
[1];
1811 x
.array
[0] |= y
.array
[0];
1819 static INLINE i386_cpu_flags
1820 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1822 switch (ARRAY_SIZE (x
.array
))
1825 x
.array
[3] &= ~y
.array
[3];
1828 x
.array
[2] &= ~y
.array
[2];
1831 x
.array
[1] &= ~y
.array
[1];
1834 x
.array
[0] &= ~y
.array
[0];
1842 #define CPU_FLAGS_ARCH_MATCH 0x1
1843 #define CPU_FLAGS_64BIT_MATCH 0x2
1845 #define CPU_FLAGS_PERFECT_MATCH \
1846 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1848 /* Return CPU flags match bits. */
1851 cpu_flags_match (const insn_template
*t
)
1853 i386_cpu_flags x
= t
->cpu_flags
;
1854 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1856 x
.bitfield
.cpu64
= 0;
1857 x
.bitfield
.cpuno64
= 0;
1859 if (cpu_flags_all_zero (&x
))
1861 /* This instruction is available on all archs. */
1862 match
|= CPU_FLAGS_ARCH_MATCH
;
1866 /* This instruction is available only on some archs. */
1867 i386_cpu_flags cpu
= cpu_arch_flags
;
1869 /* AVX512VL is no standalone feature - match it and then strip it. */
1870 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1872 x
.bitfield
.cpuavx512vl
= 0;
1874 cpu
= cpu_flags_and (x
, cpu
);
1875 if (!cpu_flags_all_zero (&cpu
))
1877 if (x
.bitfield
.cpuavx
)
1879 /* We need to check a few extra flags with AVX. */
1880 if (cpu
.bitfield
.cpuavx
1881 && (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1882 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1883 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1884 && (!x
.bitfield
.cpupclmul
|| cpu
.bitfield
.cpupclmul
))
1885 match
|= CPU_FLAGS_ARCH_MATCH
;
1887 else if (x
.bitfield
.cpuavx512f
)
1889 /* We need to check a few extra flags with AVX512F. */
1890 if (cpu
.bitfield
.cpuavx512f
1891 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1892 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1893 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1894 match
|= CPU_FLAGS_ARCH_MATCH
;
1897 match
|= CPU_FLAGS_ARCH_MATCH
;
1903 static INLINE i386_operand_type
1904 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1906 if (x
.bitfield
.class != y
.bitfield
.class)
1907 x
.bitfield
.class = ClassNone
;
1908 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1909 x
.bitfield
.instance
= InstanceNone
;
1911 switch (ARRAY_SIZE (x
.array
))
1914 x
.array
[2] &= y
.array
[2];
1917 x
.array
[1] &= y
.array
[1];
1920 x
.array
[0] &= y
.array
[0];
1928 static INLINE i386_operand_type
1929 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1931 gas_assert (y
.bitfield
.class == ClassNone
);
1932 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1934 switch (ARRAY_SIZE (x
.array
))
1937 x
.array
[2] &= ~y
.array
[2];
1940 x
.array
[1] &= ~y
.array
[1];
1943 x
.array
[0] &= ~y
.array
[0];
1951 static INLINE i386_operand_type
1952 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1954 gas_assert (x
.bitfield
.class == ClassNone
||
1955 y
.bitfield
.class == ClassNone
||
1956 x
.bitfield
.class == y
.bitfield
.class);
1957 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1958 y
.bitfield
.instance
== InstanceNone
||
1959 x
.bitfield
.instance
== y
.bitfield
.instance
);
1961 switch (ARRAY_SIZE (x
.array
))
1964 x
.array
[2] |= y
.array
[2];
1967 x
.array
[1] |= y
.array
[1];
1970 x
.array
[0] |= y
.array
[0];
1978 static INLINE i386_operand_type
1979 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1981 gas_assert (y
.bitfield
.class == ClassNone
);
1982 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1984 switch (ARRAY_SIZE (x
.array
))
1987 x
.array
[2] ^= y
.array
[2];
1990 x
.array
[1] ^= y
.array
[1];
1993 x
.array
[0] ^= y
.array
[0];
2001 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
2002 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
2003 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
2004 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
2005 static const i386_operand_type anydisp
= OPERAND_TYPE_ANYDISP
;
2006 static const i386_operand_type anyimm
= OPERAND_TYPE_ANYIMM
;
2007 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
2008 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
2009 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
2010 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
2011 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
2012 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
2013 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
2014 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
2015 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
2016 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
2017 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
2028 operand_type_check (i386_operand_type t
, enum operand_type c
)
2033 return t
.bitfield
.class == Reg
;
2036 return (t
.bitfield
.imm8
2040 || t
.bitfield
.imm32s
2041 || t
.bitfield
.imm64
);
2044 return (t
.bitfield
.disp8
2045 || t
.bitfield
.disp16
2046 || t
.bitfield
.disp32
2047 || t
.bitfield
.disp32s
2048 || t
.bitfield
.disp64
);
2051 return (t
.bitfield
.disp8
2052 || t
.bitfield
.disp16
2053 || t
.bitfield
.disp32
2054 || t
.bitfield
.disp32s
2055 || t
.bitfield
.disp64
2056 || t
.bitfield
.baseindex
);
2065 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2066 between operand GIVEN and opeand WANTED for instruction template T. */
2069 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2072 return !((i
.types
[given
].bitfield
.byte
2073 && !t
->operand_types
[wanted
].bitfield
.byte
)
2074 || (i
.types
[given
].bitfield
.word
2075 && !t
->operand_types
[wanted
].bitfield
.word
)
2076 || (i
.types
[given
].bitfield
.dword
2077 && !t
->operand_types
[wanted
].bitfield
.dword
)
2078 || (i
.types
[given
].bitfield
.qword
2079 && !t
->operand_types
[wanted
].bitfield
.qword
)
2080 || (i
.types
[given
].bitfield
.tbyte
2081 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2084 /* Return 1 if there is no conflict in SIMD register between operand
2085 GIVEN and opeand WANTED for instruction template T. */
2088 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2091 return !((i
.types
[given
].bitfield
.xmmword
2092 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2093 || (i
.types
[given
].bitfield
.ymmword
2094 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2095 || (i
.types
[given
].bitfield
.zmmword
2096 && !t
->operand_types
[wanted
].bitfield
.zmmword
));
2099 /* Return 1 if there is no conflict in any size between operand GIVEN
2100 and opeand WANTED for instruction template T. */
2103 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2106 return (match_operand_size (t
, wanted
, given
)
2107 && !((i
.types
[given
].bitfield
.unspecified
2109 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2110 || (i
.types
[given
].bitfield
.fword
2111 && !t
->operand_types
[wanted
].bitfield
.fword
)
2112 /* For scalar opcode templates to allow register and memory
2113 operands at the same time, some special casing is needed
2114 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2115 down-conversion vpmov*. */
2116 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2117 && !t
->opcode_modifier
.broadcast
2118 && (t
->operand_types
[wanted
].bitfield
.byte
2119 || t
->operand_types
[wanted
].bitfield
.word
2120 || t
->operand_types
[wanted
].bitfield
.dword
2121 || t
->operand_types
[wanted
].bitfield
.qword
))
2122 ? (i
.types
[given
].bitfield
.xmmword
2123 || i
.types
[given
].bitfield
.ymmword
2124 || i
.types
[given
].bitfield
.zmmword
)
2125 : !match_simd_size(t
, wanted
, given
))));
2128 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2129 operands for instruction template T, and it has MATCH_REVERSE set if there
2130 is no size conflict on any operands for the template with operands reversed
2131 (and the template allows for reversing in the first place). */
2133 #define MATCH_STRAIGHT 1
2134 #define MATCH_REVERSE 2
2136 static INLINE
unsigned int
2137 operand_size_match (const insn_template
*t
)
2139 unsigned int j
, match
= MATCH_STRAIGHT
;
2141 /* Don't check non-absolute jump instructions. */
2142 if (t
->opcode_modifier
.jump
2143 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2146 /* Check memory and accumulator operand size. */
2147 for (j
= 0; j
< i
.operands
; j
++)
2149 if (i
.types
[j
].bitfield
.class != Reg
2150 && i
.types
[j
].bitfield
.class != RegSIMD
2151 && t
->opcode_modifier
.anysize
)
2154 if (t
->operand_types
[j
].bitfield
.class == Reg
2155 && !match_operand_size (t
, j
, j
))
2161 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2162 && !match_simd_size (t
, j
, j
))
2168 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2169 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2175 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2182 if (!t
->opcode_modifier
.d
)
2186 i
.error
= operand_size_mismatch
;
2190 /* Check reverse. */
2191 gas_assert (i
.operands
>= 2 && i
.operands
<= 3);
2193 for (j
= 0; j
< i
.operands
; j
++)
2195 unsigned int given
= i
.operands
- j
- 1;
2197 if (t
->operand_types
[j
].bitfield
.class == Reg
2198 && !match_operand_size (t
, j
, given
))
2201 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2202 && !match_simd_size (t
, j
, given
))
2205 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2206 && (!match_operand_size (t
, j
, given
)
2207 || !match_simd_size (t
, j
, given
)))
2210 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2214 return match
| MATCH_REVERSE
;
2218 operand_type_match (i386_operand_type overlap
,
2219 i386_operand_type given
)
2221 i386_operand_type temp
= overlap
;
2223 temp
.bitfield
.unspecified
= 0;
2224 temp
.bitfield
.byte
= 0;
2225 temp
.bitfield
.word
= 0;
2226 temp
.bitfield
.dword
= 0;
2227 temp
.bitfield
.fword
= 0;
2228 temp
.bitfield
.qword
= 0;
2229 temp
.bitfield
.tbyte
= 0;
2230 temp
.bitfield
.xmmword
= 0;
2231 temp
.bitfield
.ymmword
= 0;
2232 temp
.bitfield
.zmmword
= 0;
2233 if (operand_type_all_zero (&temp
))
2236 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2240 i
.error
= operand_type_mismatch
;
2244 /* If given types g0 and g1 are registers they must be of the same type
2245 unless the expected operand type register overlap is null.
2246 Memory operand size of certain SIMD instructions is also being checked
2250 operand_type_register_match (i386_operand_type g0
,
2251 i386_operand_type t0
,
2252 i386_operand_type g1
,
2253 i386_operand_type t1
)
2255 if (g0
.bitfield
.class != Reg
2256 && g0
.bitfield
.class != RegSIMD
2257 && (!operand_type_check (g0
, anymem
)
2258 || g0
.bitfield
.unspecified
2259 || t0
.bitfield
.class != RegSIMD
))
2262 if (g1
.bitfield
.class != Reg
2263 && g1
.bitfield
.class != RegSIMD
2264 && (!operand_type_check (g1
, anymem
)
2265 || g1
.bitfield
.unspecified
2266 || t1
.bitfield
.class != RegSIMD
))
2269 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2270 && g0
.bitfield
.word
== g1
.bitfield
.word
2271 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2272 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2273 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2274 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2275 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2278 if (!(t0
.bitfield
.byte
& t1
.bitfield
.byte
)
2279 && !(t0
.bitfield
.word
& t1
.bitfield
.word
)
2280 && !(t0
.bitfield
.dword
& t1
.bitfield
.dword
)
2281 && !(t0
.bitfield
.qword
& t1
.bitfield
.qword
)
2282 && !(t0
.bitfield
.xmmword
& t1
.bitfield
.xmmword
)
2283 && !(t0
.bitfield
.ymmword
& t1
.bitfield
.ymmword
)
2284 && !(t0
.bitfield
.zmmword
& t1
.bitfield
.zmmword
))
2287 i
.error
= register_type_mismatch
;
2292 static INLINE
unsigned int
2293 register_number (const reg_entry
*r
)
2295 unsigned int nr
= r
->reg_num
;
2297 if (r
->reg_flags
& RegRex
)
2300 if (r
->reg_flags
& RegVRex
)
2306 static INLINE
unsigned int
2307 mode_from_disp_size (i386_operand_type t
)
2309 if (t
.bitfield
.disp8
)
2311 else if (t
.bitfield
.disp16
2312 || t
.bitfield
.disp32
2313 || t
.bitfield
.disp32s
)
2320 fits_in_signed_byte (addressT num
)
2322 return num
+ 0x80 <= 0xff;
2326 fits_in_unsigned_byte (addressT num
)
2332 fits_in_unsigned_word (addressT num
)
2334 return num
<= 0xffff;
2338 fits_in_signed_word (addressT num
)
2340 return num
+ 0x8000 <= 0xffff;
2344 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2349 return num
+ 0x80000000 <= 0xffffffff;
2351 } /* fits_in_signed_long() */
2354 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2359 return num
<= 0xffffffff;
2361 } /* fits_in_unsigned_long() */
2364 fits_in_disp8 (offsetT num
)
2366 int shift
= i
.memshift
;
2372 mask
= (1 << shift
) - 1;
2374 /* Return 0 if NUM isn't properly aligned. */
2378 /* Check if NUM will fit in 8bit after shift. */
2379 return fits_in_signed_byte (num
>> shift
);
2383 fits_in_imm4 (offsetT num
)
2385 return (num
& 0xf) == num
;
2388 static i386_operand_type
2389 smallest_imm_type (offsetT num
)
2391 i386_operand_type t
;
2393 operand_type_set (&t
, 0);
2394 t
.bitfield
.imm64
= 1;
2396 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2398 /* This code is disabled on the 486 because all the Imm1 forms
2399 in the opcode table are slower on the i486. They're the
2400 versions with the implicitly specified single-position
2401 displacement, which has another syntax if you really want to
2403 t
.bitfield
.imm1
= 1;
2404 t
.bitfield
.imm8
= 1;
2405 t
.bitfield
.imm8s
= 1;
2406 t
.bitfield
.imm16
= 1;
2407 t
.bitfield
.imm32
= 1;
2408 t
.bitfield
.imm32s
= 1;
2410 else if (fits_in_signed_byte (num
))
2412 t
.bitfield
.imm8
= 1;
2413 t
.bitfield
.imm8s
= 1;
2414 t
.bitfield
.imm16
= 1;
2415 t
.bitfield
.imm32
= 1;
2416 t
.bitfield
.imm32s
= 1;
2418 else if (fits_in_unsigned_byte (num
))
2420 t
.bitfield
.imm8
= 1;
2421 t
.bitfield
.imm16
= 1;
2422 t
.bitfield
.imm32
= 1;
2423 t
.bitfield
.imm32s
= 1;
2425 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2427 t
.bitfield
.imm16
= 1;
2428 t
.bitfield
.imm32
= 1;
2429 t
.bitfield
.imm32s
= 1;
2431 else if (fits_in_signed_long (num
))
2433 t
.bitfield
.imm32
= 1;
2434 t
.bitfield
.imm32s
= 1;
2436 else if (fits_in_unsigned_long (num
))
2437 t
.bitfield
.imm32
= 1;
2443 offset_in_range (offsetT val
, int size
)
2449 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2450 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2451 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2453 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2459 /* If BFD64, sign extend val for 32bit address mode. */
2460 if (flag_code
!= CODE_64BIT
2461 || i
.prefix
[ADDR_PREFIX
])
2462 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2463 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2466 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2468 char buf1
[40], buf2
[40];
2470 sprint_value (buf1
, val
);
2471 sprint_value (buf2
, val
& mask
);
2472 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2487 a. PREFIX_EXIST if attempting to add a prefix where one from the
2488 same class already exists.
2489 b. PREFIX_LOCK if lock prefix is added.
2490 c. PREFIX_REP if rep/repne prefix is added.
2491 d. PREFIX_DS if ds prefix is added.
2492 e. PREFIX_OTHER if other prefix is added.
2495 static enum PREFIX_GROUP
2496 add_prefix (unsigned int prefix
)
2498 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2501 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2502 && flag_code
== CODE_64BIT
)
2504 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2505 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2506 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2507 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2518 case DS_PREFIX_OPCODE
:
2521 case CS_PREFIX_OPCODE
:
2522 case ES_PREFIX_OPCODE
:
2523 case FS_PREFIX_OPCODE
:
2524 case GS_PREFIX_OPCODE
:
2525 case SS_PREFIX_OPCODE
:
2529 case REPNE_PREFIX_OPCODE
:
2530 case REPE_PREFIX_OPCODE
:
2535 case LOCK_PREFIX_OPCODE
:
2544 case ADDR_PREFIX_OPCODE
:
2548 case DATA_PREFIX_OPCODE
:
2552 if (i
.prefix
[q
] != 0)
2560 i
.prefix
[q
] |= prefix
;
2563 as_bad (_("same type of prefix used twice"));
2569 update_code_flag (int value
, int check
)
2571 PRINTF_LIKE ((*as_error
));
2573 flag_code
= (enum flag_code
) value
;
2574 if (flag_code
== CODE_64BIT
)
2576 cpu_arch_flags
.bitfield
.cpu64
= 1;
2577 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2581 cpu_arch_flags
.bitfield
.cpu64
= 0;
2582 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2584 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2587 as_error
= as_fatal
;
2590 (*as_error
) (_("64bit mode not supported on `%s'."),
2591 cpu_arch_name
? cpu_arch_name
: default_arch
);
2593 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2596 as_error
= as_fatal
;
2599 (*as_error
) (_("32bit mode not supported on `%s'."),
2600 cpu_arch_name
? cpu_arch_name
: default_arch
);
2602 stackop_size
= '\0';
2606 set_code_flag (int value
)
2608 update_code_flag (value
, 0);
2612 set_16bit_gcc_code_flag (int new_code_flag
)
2614 flag_code
= (enum flag_code
) new_code_flag
;
2615 if (flag_code
!= CODE_16BIT
)
2617 cpu_arch_flags
.bitfield
.cpu64
= 0;
2618 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2619 stackop_size
= LONG_MNEM_SUFFIX
;
2623 set_intel_syntax (int syntax_flag
)
2625 /* Find out if register prefixing is specified. */
2626 int ask_naked_reg
= 0;
2629 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2632 int e
= get_symbol_name (&string
);
2634 if (strcmp (string
, "prefix") == 0)
2636 else if (strcmp (string
, "noprefix") == 0)
2639 as_bad (_("bad argument to syntax directive."));
2640 (void) restore_line_pointer (e
);
2642 demand_empty_rest_of_line ();
2644 intel_syntax
= syntax_flag
;
2646 if (ask_naked_reg
== 0)
2647 allow_naked_reg
= (intel_syntax
2648 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2650 allow_naked_reg
= (ask_naked_reg
< 0);
2652 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2654 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2655 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2656 register_prefix
= allow_naked_reg
? "" : "%";
2660 set_intel_mnemonic (int mnemonic_flag
)
2662 intel_mnemonic
= mnemonic_flag
;
2666 set_allow_index_reg (int flag
)
2668 allow_index_reg
= flag
;
2672 set_check (int what
)
2674 enum check_kind
*kind
;
2679 kind
= &operand_check
;
2690 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2693 int e
= get_symbol_name (&string
);
2695 if (strcmp (string
, "none") == 0)
2697 else if (strcmp (string
, "warning") == 0)
2698 *kind
= check_warning
;
2699 else if (strcmp (string
, "error") == 0)
2700 *kind
= check_error
;
2702 as_bad (_("bad argument to %s_check directive."), str
);
2703 (void) restore_line_pointer (e
);
2706 as_bad (_("missing argument for %s_check directive"), str
);
2708 demand_empty_rest_of_line ();
2712 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2713 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2715 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2716 static const char *arch
;
2718 /* Intel LIOM is only supported on ELF. */
2724 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2725 use default_arch. */
2726 arch
= cpu_arch_name
;
2728 arch
= default_arch
;
2731 /* If we are targeting Intel MCU, we must enable it. */
2732 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2733 || new_flag
.bitfield
.cpuiamcu
)
2736 /* If we are targeting Intel L1OM, we must enable it. */
2737 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2738 || new_flag
.bitfield
.cpul1om
)
2741 /* If we are targeting Intel K1OM, we must enable it. */
2742 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2743 || new_flag
.bitfield
.cpuk1om
)
2746 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2751 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2755 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2758 int e
= get_symbol_name (&string
);
2760 i386_cpu_flags flags
;
2762 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2764 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2766 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2770 cpu_arch_name
= cpu_arch
[j
].name
;
2771 cpu_sub_arch_name
= NULL
;
2772 cpu_arch_flags
= cpu_arch
[j
].flags
;
2773 if (flag_code
== CODE_64BIT
)
2775 cpu_arch_flags
.bitfield
.cpu64
= 1;
2776 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2780 cpu_arch_flags
.bitfield
.cpu64
= 0;
2781 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2783 cpu_arch_isa
= cpu_arch
[j
].type
;
2784 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2785 if (!cpu_arch_tune_set
)
2787 cpu_arch_tune
= cpu_arch_isa
;
2788 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2793 flags
= cpu_flags_or (cpu_arch_flags
,
2796 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2798 if (cpu_sub_arch_name
)
2800 char *name
= cpu_sub_arch_name
;
2801 cpu_sub_arch_name
= concat (name
,
2803 (const char *) NULL
);
2807 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2808 cpu_arch_flags
= flags
;
2809 cpu_arch_isa_flags
= flags
;
2813 = cpu_flags_or (cpu_arch_isa_flags
,
2815 (void) restore_line_pointer (e
);
2816 demand_empty_rest_of_line ();
2821 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2823 /* Disable an ISA extension. */
2824 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2825 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2827 flags
= cpu_flags_and_not (cpu_arch_flags
,
2828 cpu_noarch
[j
].flags
);
2829 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2831 if (cpu_sub_arch_name
)
2833 char *name
= cpu_sub_arch_name
;
2834 cpu_sub_arch_name
= concat (name
, string
,
2835 (const char *) NULL
);
2839 cpu_sub_arch_name
= xstrdup (string
);
2840 cpu_arch_flags
= flags
;
2841 cpu_arch_isa_flags
= flags
;
2843 (void) restore_line_pointer (e
);
2844 demand_empty_rest_of_line ();
2848 j
= ARRAY_SIZE (cpu_arch
);
2851 if (j
>= ARRAY_SIZE (cpu_arch
))
2852 as_bad (_("no such architecture: `%s'"), string
);
2854 *input_line_pointer
= e
;
2857 as_bad (_("missing cpu architecture"));
2859 no_cond_jump_promotion
= 0;
2860 if (*input_line_pointer
== ','
2861 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2866 ++input_line_pointer
;
2867 e
= get_symbol_name (&string
);
2869 if (strcmp (string
, "nojumps") == 0)
2870 no_cond_jump_promotion
= 1;
2871 else if (strcmp (string
, "jumps") == 0)
2874 as_bad (_("no such architecture modifier: `%s'"), string
);
2876 (void) restore_line_pointer (e
);
2879 demand_empty_rest_of_line ();
2882 enum bfd_architecture
2885 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2887 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2888 || flag_code
!= CODE_64BIT
)
2889 as_fatal (_("Intel L1OM is 64bit ELF only"));
2890 return bfd_arch_l1om
;
2892 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2894 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2895 || flag_code
!= CODE_64BIT
)
2896 as_fatal (_("Intel K1OM is 64bit ELF only"));
2897 return bfd_arch_k1om
;
2899 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2901 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2902 || flag_code
== CODE_64BIT
)
2903 as_fatal (_("Intel MCU is 32bit ELF only"));
2904 return bfd_arch_iamcu
;
2907 return bfd_arch_i386
;
2913 if (!strncmp (default_arch
, "x86_64", 6))
2915 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2917 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2918 || default_arch
[6] != '\0')
2919 as_fatal (_("Intel L1OM is 64bit ELF only"));
2920 return bfd_mach_l1om
;
2922 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2924 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2925 || default_arch
[6] != '\0')
2926 as_fatal (_("Intel K1OM is 64bit ELF only"));
2927 return bfd_mach_k1om
;
2929 else if (default_arch
[6] == '\0')
2930 return bfd_mach_x86_64
;
2932 return bfd_mach_x64_32
;
2934 else if (!strcmp (default_arch
, "i386")
2935 || !strcmp (default_arch
, "iamcu"))
2937 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2939 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2940 as_fatal (_("Intel MCU is 32bit ELF only"));
2941 return bfd_mach_i386_iamcu
;
2944 return bfd_mach_i386_i386
;
2947 as_fatal (_("unknown architecture"));
2953 const char *hash_err
;
2955 /* Support pseudo prefixes like {disp32}. */
2956 lex_type
['{'] = LEX_BEGIN_NAME
;
2958 /* Initialize op_hash hash table. */
2959 op_hash
= hash_new ();
2962 const insn_template
*optab
;
2963 templates
*core_optab
;
2965 /* Setup for loop. */
2967 core_optab
= XNEW (templates
);
2968 core_optab
->start
= optab
;
2973 if (optab
->name
== NULL
2974 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2976 /* different name --> ship out current template list;
2977 add to hash table; & begin anew. */
2978 core_optab
->end
= optab
;
2979 hash_err
= hash_insert (op_hash
,
2981 (void *) core_optab
);
2984 as_fatal (_("can't hash %s: %s"),
2988 if (optab
->name
== NULL
)
2990 core_optab
= XNEW (templates
);
2991 core_optab
->start
= optab
;
2996 /* Initialize reg_hash hash table. */
2997 reg_hash
= hash_new ();
2999 const reg_entry
*regtab
;
3000 unsigned int regtab_size
= i386_regtab_size
;
3002 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3004 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
3006 as_fatal (_("can't hash %s: %s"),
3012 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3017 for (c
= 0; c
< 256; c
++)
3022 mnemonic_chars
[c
] = c
;
3023 register_chars
[c
] = c
;
3024 operand_chars
[c
] = c
;
3026 else if (ISLOWER (c
))
3028 mnemonic_chars
[c
] = c
;
3029 register_chars
[c
] = c
;
3030 operand_chars
[c
] = c
;
3032 else if (ISUPPER (c
))
3034 mnemonic_chars
[c
] = TOLOWER (c
);
3035 register_chars
[c
] = mnemonic_chars
[c
];
3036 operand_chars
[c
] = c
;
3038 else if (c
== '{' || c
== '}')
3040 mnemonic_chars
[c
] = c
;
3041 operand_chars
[c
] = c
;
3044 if (ISALPHA (c
) || ISDIGIT (c
))
3045 identifier_chars
[c
] = c
;
3048 identifier_chars
[c
] = c
;
3049 operand_chars
[c
] = c
;
3054 identifier_chars
['@'] = '@';
3057 identifier_chars
['?'] = '?';
3058 operand_chars
['?'] = '?';
3060 digit_chars
['-'] = '-';
3061 mnemonic_chars
['_'] = '_';
3062 mnemonic_chars
['-'] = '-';
3063 mnemonic_chars
['.'] = '.';
3064 identifier_chars
['_'] = '_';
3065 identifier_chars
['.'] = '.';
3067 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3068 operand_chars
[(unsigned char) *p
] = *p
;
3071 if (flag_code
== CODE_64BIT
)
3073 #if defined (OBJ_COFF) && defined (TE_PE)
3074 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3077 x86_dwarf2_return_column
= 16;
3079 x86_cie_data_alignment
= -8;
3083 x86_dwarf2_return_column
= 8;
3084 x86_cie_data_alignment
= -4;
3087 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3088 can be turned into BRANCH_PREFIX frag. */
3089 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3094 i386_print_statistics (FILE *file
)
3096 hash_print_statistics (file
, "i386 opcode", op_hash
);
3097 hash_print_statistics (file
, "i386 register", reg_hash
);
3102 /* Debugging routines for md_assemble. */
3103 static void pte (insn_template
*);
3104 static void pt (i386_operand_type
);
3105 static void pe (expressionS
*);
3106 static void ps (symbolS
*);
3109 pi (const char *line
, i386_insn
*x
)
3113 fprintf (stdout
, "%s: template ", line
);
3115 fprintf (stdout
, " address: base %s index %s scale %x\n",
3116 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3117 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3118 x
->log2_scale_factor
);
3119 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3120 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3121 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3122 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3123 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3124 (x
->rex
& REX_W
) != 0,
3125 (x
->rex
& REX_R
) != 0,
3126 (x
->rex
& REX_X
) != 0,
3127 (x
->rex
& REX_B
) != 0);
3128 for (j
= 0; j
< x
->operands
; j
++)
3130 fprintf (stdout
, " #%d: ", j
+ 1);
3132 fprintf (stdout
, "\n");
3133 if (x
->types
[j
].bitfield
.class == Reg
3134 || x
->types
[j
].bitfield
.class == RegMMX
3135 || x
->types
[j
].bitfield
.class == RegSIMD
3136 || x
->types
[j
].bitfield
.class == SReg
3137 || x
->types
[j
].bitfield
.class == RegCR
3138 || x
->types
[j
].bitfield
.class == RegDR
3139 || x
->types
[j
].bitfield
.class == RegTR
)
3140 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3141 if (operand_type_check (x
->types
[j
], imm
))
3143 if (operand_type_check (x
->types
[j
], disp
))
3144 pe (x
->op
[j
].disps
);
3149 pte (insn_template
*t
)
3152 fprintf (stdout
, " %d operands ", t
->operands
);
3153 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3154 if (t
->extension_opcode
!= None
)
3155 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3156 if (t
->opcode_modifier
.d
)
3157 fprintf (stdout
, "D");
3158 if (t
->opcode_modifier
.w
)
3159 fprintf (stdout
, "W");
3160 fprintf (stdout
, "\n");
3161 for (j
= 0; j
< t
->operands
; j
++)
3163 fprintf (stdout
, " #%d type ", j
+ 1);
3164 pt (t
->operand_types
[j
]);
3165 fprintf (stdout
, "\n");
3172 fprintf (stdout
, " operation %d\n", e
->X_op
);
3173 fprintf (stdout
, " add_number %ld (%lx)\n",
3174 (long) e
->X_add_number
, (long) e
->X_add_number
);
3175 if (e
->X_add_symbol
)
3177 fprintf (stdout
, " add_symbol ");
3178 ps (e
->X_add_symbol
);
3179 fprintf (stdout
, "\n");
3183 fprintf (stdout
, " op_symbol ");
3184 ps (e
->X_op_symbol
);
3185 fprintf (stdout
, "\n");
3192 fprintf (stdout
, "%s type %s%s",
3194 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3195 segment_name (S_GET_SEGMENT (s
)));
3198 static struct type_name
3200 i386_operand_type mask
;
3203 const type_names
[] =
3205 { OPERAND_TYPE_REG8
, "r8" },
3206 { OPERAND_TYPE_REG16
, "r16" },
3207 { OPERAND_TYPE_REG32
, "r32" },
3208 { OPERAND_TYPE_REG64
, "r64" },
3209 { OPERAND_TYPE_ACC8
, "acc8" },
3210 { OPERAND_TYPE_ACC16
, "acc16" },
3211 { OPERAND_TYPE_ACC32
, "acc32" },
3212 { OPERAND_TYPE_ACC64
, "acc64" },
3213 { OPERAND_TYPE_IMM8
, "i8" },
3214 { OPERAND_TYPE_IMM8
, "i8s" },
3215 { OPERAND_TYPE_IMM16
, "i16" },
3216 { OPERAND_TYPE_IMM32
, "i32" },
3217 { OPERAND_TYPE_IMM32S
, "i32s" },
3218 { OPERAND_TYPE_IMM64
, "i64" },
3219 { OPERAND_TYPE_IMM1
, "i1" },
3220 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
3221 { OPERAND_TYPE_DISP8
, "d8" },
3222 { OPERAND_TYPE_DISP16
, "d16" },
3223 { OPERAND_TYPE_DISP32
, "d32" },
3224 { OPERAND_TYPE_DISP32S
, "d32s" },
3225 { OPERAND_TYPE_DISP64
, "d64" },
3226 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
3227 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
3228 { OPERAND_TYPE_CONTROL
, "control reg" },
3229 { OPERAND_TYPE_TEST
, "test reg" },
3230 { OPERAND_TYPE_DEBUG
, "debug reg" },
3231 { OPERAND_TYPE_FLOATREG
, "FReg" },
3232 { OPERAND_TYPE_FLOATACC
, "FAcc" },
3233 { OPERAND_TYPE_SREG
, "SReg" },
3234 { OPERAND_TYPE_REGMMX
, "rMMX" },
3235 { OPERAND_TYPE_REGXMM
, "rXMM" },
3236 { OPERAND_TYPE_REGYMM
, "rYMM" },
3237 { OPERAND_TYPE_REGZMM
, "rZMM" },
3238 { OPERAND_TYPE_REGMASK
, "Mask reg" },
3242 pt (i386_operand_type t
)
3245 i386_operand_type a
;
3247 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3249 a
= operand_type_and (t
, type_names
[j
].mask
);
3250 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3251 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3256 #endif /* DEBUG386 */
3258 static bfd_reloc_code_real_type
3259 reloc (unsigned int size
,
3262 bfd_reloc_code_real_type other
)
3264 if (other
!= NO_RELOC
)
3266 reloc_howto_type
*rel
;
3271 case BFD_RELOC_X86_64_GOT32
:
3272 return BFD_RELOC_X86_64_GOT64
;
3274 case BFD_RELOC_X86_64_GOTPLT64
:
3275 return BFD_RELOC_X86_64_GOTPLT64
;
3277 case BFD_RELOC_X86_64_PLTOFF64
:
3278 return BFD_RELOC_X86_64_PLTOFF64
;
3280 case BFD_RELOC_X86_64_GOTPC32
:
3281 other
= BFD_RELOC_X86_64_GOTPC64
;
3283 case BFD_RELOC_X86_64_GOTPCREL
:
3284 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3286 case BFD_RELOC_X86_64_TPOFF32
:
3287 other
= BFD_RELOC_X86_64_TPOFF64
;
3289 case BFD_RELOC_X86_64_DTPOFF32
:
3290 other
= BFD_RELOC_X86_64_DTPOFF64
;
3296 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3297 if (other
== BFD_RELOC_SIZE32
)
3300 other
= BFD_RELOC_SIZE64
;
3303 as_bad (_("there are no pc-relative size relocations"));
3309 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3310 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3313 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3315 as_bad (_("unknown relocation (%u)"), other
);
3316 else if (size
!= bfd_get_reloc_size (rel
))
3317 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3318 bfd_get_reloc_size (rel
),
3320 else if (pcrel
&& !rel
->pc_relative
)
3321 as_bad (_("non-pc-relative relocation for pc-relative field"));
3322 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3324 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3326 as_bad (_("relocated field and relocation type differ in signedness"));
3335 as_bad (_("there are no unsigned pc-relative relocations"));
3338 case 1: return BFD_RELOC_8_PCREL
;
3339 case 2: return BFD_RELOC_16_PCREL
;
3340 case 4: return BFD_RELOC_32_PCREL
;
3341 case 8: return BFD_RELOC_64_PCREL
;
3343 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3350 case 4: return BFD_RELOC_X86_64_32S
;
3355 case 1: return BFD_RELOC_8
;
3356 case 2: return BFD_RELOC_16
;
3357 case 4: return BFD_RELOC_32
;
3358 case 8: return BFD_RELOC_64
;
3360 as_bad (_("cannot do %s %u byte relocation"),
3361 sign
> 0 ? "signed" : "unsigned", size
);
3367 /* Here we decide which fixups can be adjusted to make them relative to
3368 the beginning of the section instead of the symbol. Basically we need
3369 to make sure that the dynamic relocations are done correctly, so in
3370 some cases we force the original symbol to be used. */
3373 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3379 /* Don't adjust pc-relative references to merge sections in 64-bit
3381 if (use_rela_relocations
3382 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3386 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3387 and changed later by validate_fix. */
3388 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3389 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3392 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3393 for size relocations. */
3394 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3395 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3396 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3397 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3398 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3399 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3400 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3401 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3402 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3403 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3404 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3405 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3406 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3407 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3408 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3409 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3410 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3411 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3412 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3413 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3414 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3415 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3416 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3417 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3418 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3419 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3420 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3421 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3422 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3423 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3424 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3425 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3426 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3433 intel_float_operand (const char *mnemonic
)
3435 /* Note that the value returned is meaningful only for opcodes with (memory)
3436 operands, hence the code here is free to improperly handle opcodes that
3437 have no operands (for better performance and smaller code). */
3439 if (mnemonic
[0] != 'f')
3440 return 0; /* non-math */
3442 switch (mnemonic
[1])
3444 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3445 the fs segment override prefix not currently handled because no
3446 call path can make opcodes without operands get here */
3448 return 2 /* integer op */;
3450 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3451 return 3; /* fldcw/fldenv */
3454 if (mnemonic
[2] != 'o' /* fnop */)
3455 return 3; /* non-waiting control op */
3458 if (mnemonic
[2] == 's')
3459 return 3; /* frstor/frstpm */
3462 if (mnemonic
[2] == 'a')
3463 return 3; /* fsave */
3464 if (mnemonic
[2] == 't')
3466 switch (mnemonic
[3])
3468 case 'c': /* fstcw */
3469 case 'd': /* fstdw */
3470 case 'e': /* fstenv */
3471 case 's': /* fsts[gw] */
3477 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3478 return 0; /* fxsave/fxrstor are not really math ops */
3485 /* Build the VEX prefix. */
3488 build_vex_prefix (const insn_template
*t
)
3490 unsigned int register_specifier
;
3491 unsigned int implied_prefix
;
3492 unsigned int vector_length
;
3495 /* Check register specifier. */
3496 if (i
.vex
.register_specifier
)
3498 register_specifier
=
3499 ~register_number (i
.vex
.register_specifier
) & 0xf;
3500 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3503 register_specifier
= 0xf;
3505 /* Use 2-byte VEX prefix by swapping destination and source operand
3506 if there are more than 1 register operand. */
3507 if (i
.reg_operands
> 1
3508 && i
.vec_encoding
!= vex_encoding_vex3
3509 && i
.dir_encoding
== dir_encoding_default
3510 && i
.operands
== i
.reg_operands
3511 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3512 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3513 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3516 unsigned int xchg
= i
.operands
- 1;
3517 union i386_op temp_op
;
3518 i386_operand_type temp_type
;
3520 temp_type
= i
.types
[xchg
];
3521 i
.types
[xchg
] = i
.types
[0];
3522 i
.types
[0] = temp_type
;
3523 temp_op
= i
.op
[xchg
];
3524 i
.op
[xchg
] = i
.op
[0];
3527 gas_assert (i
.rm
.mode
== 3);
3531 i
.rm
.regmem
= i
.rm
.reg
;
3534 if (i
.tm
.opcode_modifier
.d
)
3535 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3536 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
3537 else /* Use the next insn. */
3541 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3542 are no memory operands and at least 3 register ones. */
3543 if (i
.reg_operands
>= 3
3544 && i
.vec_encoding
!= vex_encoding_vex3
3545 && i
.reg_operands
== i
.operands
- i
.imm_operands
3546 && i
.tm
.opcode_modifier
.vex
3547 && i
.tm
.opcode_modifier
.commutative
3548 && (i
.tm
.opcode_modifier
.sse2avx
|| optimize
> 1)
3550 && i
.vex
.register_specifier
3551 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3553 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3554 union i386_op temp_op
;
3555 i386_operand_type temp_type
;
3557 gas_assert (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
);
3558 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3559 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3560 &i
.types
[i
.operands
- 3]));
3561 gas_assert (i
.rm
.mode
== 3);
3563 temp_type
= i
.types
[xchg
];
3564 i
.types
[xchg
] = i
.types
[xchg
+ 1];
3565 i
.types
[xchg
+ 1] = temp_type
;
3566 temp_op
= i
.op
[xchg
];
3567 i
.op
[xchg
] = i
.op
[xchg
+ 1];
3568 i
.op
[xchg
+ 1] = temp_op
;
3571 xchg
= i
.rm
.regmem
| 8;
3572 i
.rm
.regmem
= ~register_specifier
& 0xf;
3573 gas_assert (!(i
.rm
.regmem
& 8));
3574 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3575 register_specifier
= ~xchg
& 0xf;
3578 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3579 vector_length
= avxscalar
;
3580 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3586 /* Determine vector length from the last multi-length vector
3589 for (op
= t
->operands
; op
--;)
3590 if (t
->operand_types
[op
].bitfield
.xmmword
3591 && t
->operand_types
[op
].bitfield
.ymmword
3592 && i
.types
[op
].bitfield
.ymmword
)
3599 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3604 case DATA_PREFIX_OPCODE
:
3607 case REPE_PREFIX_OPCODE
:
3610 case REPNE_PREFIX_OPCODE
:
3617 /* Check the REX.W bit and VEXW. */
3618 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3619 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3620 else if (i
.tm
.opcode_modifier
.vexw
)
3621 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3623 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3625 /* Use 2-byte VEX prefix if possible. */
3627 && i
.vec_encoding
!= vex_encoding_vex3
3628 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3629 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3631 /* 2-byte VEX prefix. */
3635 i
.vex
.bytes
[0] = 0xc5;
3637 /* Check the REX.R bit. */
3638 r
= (i
.rex
& REX_R
) ? 0 : 1;
3639 i
.vex
.bytes
[1] = (r
<< 7
3640 | register_specifier
<< 3
3641 | vector_length
<< 2
3646 /* 3-byte VEX prefix. */
3651 switch (i
.tm
.opcode_modifier
.vexopcode
)
3655 i
.vex
.bytes
[0] = 0xc4;
3659 i
.vex
.bytes
[0] = 0xc4;
3663 i
.vex
.bytes
[0] = 0xc4;
3667 i
.vex
.bytes
[0] = 0x8f;
3671 i
.vex
.bytes
[0] = 0x8f;
3675 i
.vex
.bytes
[0] = 0x8f;
3681 /* The high 3 bits of the second VEX byte are 1's compliment
3682 of RXB bits from REX. */
3683 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3685 i
.vex
.bytes
[2] = (w
<< 7
3686 | register_specifier
<< 3
3687 | vector_length
<< 2
3692 static INLINE bfd_boolean
3693 is_evex_encoding (const insn_template
*t
)
3695 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3696 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3697 || t
->opcode_modifier
.sae
;
3700 static INLINE bfd_boolean
3701 is_any_vex_encoding (const insn_template
*t
)
3703 return t
->opcode_modifier
.vex
|| t
->opcode_modifier
.vexopcode
3704 || is_evex_encoding (t
);
3707 /* Build the EVEX prefix. */
3710 build_evex_prefix (void)
3712 unsigned int register_specifier
;
3713 unsigned int implied_prefix
;
3715 rex_byte vrex_used
= 0;
3717 /* Check register specifier. */
3718 if (i
.vex
.register_specifier
)
3720 gas_assert ((i
.vrex
& REX_X
) == 0);
3722 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3723 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3724 register_specifier
+= 8;
3725 /* The upper 16 registers are encoded in the fourth byte of the
3727 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3728 i
.vex
.bytes
[3] = 0x8;
3729 register_specifier
= ~register_specifier
& 0xf;
3733 register_specifier
= 0xf;
3735 /* Encode upper 16 vector index register in the fourth byte of
3737 if (!(i
.vrex
& REX_X
))
3738 i
.vex
.bytes
[3] = 0x8;
3743 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3748 case DATA_PREFIX_OPCODE
:
3751 case REPE_PREFIX_OPCODE
:
3754 case REPNE_PREFIX_OPCODE
:
3761 /* 4 byte EVEX prefix. */
3763 i
.vex
.bytes
[0] = 0x62;
3766 switch (i
.tm
.opcode_modifier
.vexopcode
)
3782 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3784 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3786 /* The fifth bit of the second EVEX byte is 1's compliment of the
3787 REX_R bit in VREX. */
3788 if (!(i
.vrex
& REX_R
))
3789 i
.vex
.bytes
[1] |= 0x10;
3793 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3795 /* When all operands are registers, the REX_X bit in REX is not
3796 used. We reuse it to encode the upper 16 registers, which is
3797 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3798 as 1's compliment. */
3799 if ((i
.vrex
& REX_B
))
3802 i
.vex
.bytes
[1] &= ~0x40;
3806 /* EVEX instructions shouldn't need the REX prefix. */
3807 i
.vrex
&= ~vrex_used
;
3808 gas_assert (i
.vrex
== 0);
3810 /* Check the REX.W bit and VEXW. */
3811 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3812 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3813 else if (i
.tm
.opcode_modifier
.vexw
)
3814 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3816 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3818 /* Encode the U bit. */
3819 implied_prefix
|= 0x4;
3821 /* The third byte of the EVEX prefix. */
3822 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3824 /* The fourth byte of the EVEX prefix. */
3825 /* The zeroing-masking bit. */
3826 if (i
.mask
&& i
.mask
->zeroing
)
3827 i
.vex
.bytes
[3] |= 0x80;
3829 /* Don't always set the broadcast bit if there is no RC. */
3832 /* Encode the vector length. */
3833 unsigned int vec_length
;
3835 if (!i
.tm
.opcode_modifier
.evex
3836 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
3840 /* Determine vector length from the last multi-length vector
3843 for (op
= i
.operands
; op
--;)
3844 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
3845 + i
.tm
.operand_types
[op
].bitfield
.ymmword
3846 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
3848 if (i
.types
[op
].bitfield
.zmmword
)
3850 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3853 else if (i
.types
[op
].bitfield
.ymmword
)
3855 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3858 else if (i
.types
[op
].bitfield
.xmmword
)
3860 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3863 else if (i
.broadcast
&& (int) op
== i
.broadcast
->operand
)
3865 switch (i
.broadcast
->bytes
)
3868 i
.tm
.opcode_modifier
.evex
= EVEX512
;
3871 i
.tm
.opcode_modifier
.evex
= EVEX256
;
3874 i
.tm
.opcode_modifier
.evex
= EVEX128
;
3883 if (op
>= MAX_OPERANDS
)
3887 switch (i
.tm
.opcode_modifier
.evex
)
3889 case EVEXLIG
: /* LL' is ignored */
3890 vec_length
= evexlig
<< 5;
3893 vec_length
= 0 << 5;
3896 vec_length
= 1 << 5;
3899 vec_length
= 2 << 5;
3905 i
.vex
.bytes
[3] |= vec_length
;
3906 /* Encode the broadcast bit. */
3908 i
.vex
.bytes
[3] |= 0x10;
3912 if (i
.rounding
->type
!= saeonly
)
3913 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3915 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3918 if (i
.mask
&& i
.mask
->mask
)
3919 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3923 process_immext (void)
3927 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3928 which is coded in the same place as an 8-bit immediate field
3929 would be. Here we fake an 8-bit immediate operand from the
3930 opcode suffix stored in tm.extension_opcode.
3932 AVX instructions also use this encoding, for some of
3933 3 argument instructions. */
3935 gas_assert (i
.imm_operands
<= 1
3937 || (is_any_vex_encoding (&i
.tm
)
3938 && i
.operands
<= 4)));
3940 exp
= &im_expressions
[i
.imm_operands
++];
3941 i
.op
[i
.operands
].imms
= exp
;
3942 i
.types
[i
.operands
] = imm8
;
3944 exp
->X_op
= O_constant
;
3945 exp
->X_add_number
= i
.tm
.extension_opcode
;
3946 i
.tm
.extension_opcode
= None
;
3953 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3958 as_bad (_("invalid instruction `%s' after `%s'"),
3959 i
.tm
.name
, i
.hle_prefix
);
3962 if (i
.prefix
[LOCK_PREFIX
])
3964 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3968 case HLEPrefixRelease
:
3969 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3971 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3975 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
3977 as_bad (_("memory destination needed for instruction `%s'"
3978 " after `xrelease'"), i
.tm
.name
);
3985 /* Try the shortest encoding by shortening operand size. */
3988 optimize_encoding (void)
3992 if (optimize_for_space
3993 && i
.reg_operands
== 1
3994 && i
.imm_operands
== 1
3995 && !i
.types
[1].bitfield
.byte
3996 && i
.op
[0].imms
->X_op
== O_constant
3997 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
3998 && ((i
.tm
.base_opcode
== 0xa8
3999 && i
.tm
.extension_opcode
== None
)
4000 || (i
.tm
.base_opcode
== 0xf6
4001 && i
.tm
.extension_opcode
== 0x0)))
4004 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4006 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4007 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4009 i
.types
[1].bitfield
.byte
= 1;
4010 /* Ignore the suffix. */
4012 /* Convert to byte registers. */
4013 if (i
.types
[1].bitfield
.word
)
4015 else if (i
.types
[1].bitfield
.dword
)
4019 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4024 else if (flag_code
== CODE_64BIT
4025 && ((i
.types
[1].bitfield
.qword
4026 && i
.reg_operands
== 1
4027 && i
.imm_operands
== 1
4028 && i
.op
[0].imms
->X_op
== O_constant
4029 && ((i
.tm
.base_opcode
== 0xb8
4030 && i
.tm
.extension_opcode
== None
4031 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4032 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4033 && (((i
.tm
.base_opcode
== 0x24
4034 || i
.tm
.base_opcode
== 0xa8)
4035 && i
.tm
.extension_opcode
== None
)
4036 || (i
.tm
.base_opcode
== 0x80
4037 && i
.tm
.extension_opcode
== 0x4)
4038 || ((i
.tm
.base_opcode
== 0xf6
4039 || (i
.tm
.base_opcode
| 1) == 0xc7)
4040 && i
.tm
.extension_opcode
== 0x0)))
4041 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4042 && i
.tm
.base_opcode
== 0x83
4043 && i
.tm
.extension_opcode
== 0x4)))
4044 || (i
.types
[0].bitfield
.qword
4045 && ((i
.reg_operands
== 2
4046 && i
.op
[0].regs
== i
.op
[1].regs
4047 && ((i
.tm
.base_opcode
== 0x30
4048 || i
.tm
.base_opcode
== 0x28)
4049 && i
.tm
.extension_opcode
== None
))
4050 || (i
.reg_operands
== 1
4052 && i
.tm
.base_opcode
== 0x30
4053 && i
.tm
.extension_opcode
== None
)))))
4056 andq $imm31, %r64 -> andl $imm31, %r32
4057 andq $imm7, %r64 -> andl $imm7, %r32
4058 testq $imm31, %r64 -> testl $imm31, %r32
4059 xorq %r64, %r64 -> xorl %r32, %r32
4060 subq %r64, %r64 -> subl %r32, %r32
4061 movq $imm31, %r64 -> movl $imm31, %r32
4062 movq $imm32, %r64 -> movl $imm32, %r32
4064 i
.tm
.opcode_modifier
.norex64
= 1;
4065 if (i
.tm
.base_opcode
== 0xb8 || (i
.tm
.base_opcode
| 1) == 0xc7)
4068 movq $imm31, %r64 -> movl $imm31, %r32
4069 movq $imm32, %r64 -> movl $imm32, %r32
4071 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4072 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4073 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4074 i
.types
[0].bitfield
.imm32
= 1;
4075 i
.types
[0].bitfield
.imm32s
= 0;
4076 i
.types
[0].bitfield
.imm64
= 0;
4077 i
.types
[1].bitfield
.dword
= 1;
4078 i
.types
[1].bitfield
.qword
= 0;
4079 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4082 movq $imm31, %r64 -> movl $imm31, %r32
4084 i
.tm
.base_opcode
= 0xb8;
4085 i
.tm
.extension_opcode
= None
;
4086 i
.tm
.opcode_modifier
.w
= 0;
4087 i
.tm
.opcode_modifier
.shortform
= 1;
4088 i
.tm
.opcode_modifier
.modrm
= 0;
4092 else if (optimize
> 1
4093 && !optimize_for_space
4094 && i
.reg_operands
== 2
4095 && i
.op
[0].regs
== i
.op
[1].regs
4096 && ((i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x8
4097 || (i
.tm
.base_opcode
& ~(Opcode_D
| 1)) == 0x20)
4098 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4101 andb %rN, %rN -> testb %rN, %rN
4102 andw %rN, %rN -> testw %rN, %rN
4103 andq %rN, %rN -> testq %rN, %rN
4104 orb %rN, %rN -> testb %rN, %rN
4105 orw %rN, %rN -> testw %rN, %rN
4106 orq %rN, %rN -> testq %rN, %rN
4108 and outside of 64-bit mode
4110 andl %rN, %rN -> testl %rN, %rN
4111 orl %rN, %rN -> testl %rN, %rN
4113 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4115 else if (i
.reg_operands
== 3
4116 && i
.op
[0].regs
== i
.op
[1].regs
4117 && !i
.types
[2].bitfield
.xmmword
4118 && (i
.tm
.opcode_modifier
.vex
4119 || ((!i
.mask
|| i
.mask
->zeroing
)
4121 && is_evex_encoding (&i
.tm
)
4122 && (i
.vec_encoding
!= vex_encoding_evex
4123 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4124 || i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
4125 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4126 && i
.types
[2].bitfield
.ymmword
))))
4127 && ((i
.tm
.base_opcode
== 0x55
4128 || i
.tm
.base_opcode
== 0x6655
4129 || i
.tm
.base_opcode
== 0x66df
4130 || i
.tm
.base_opcode
== 0x57
4131 || i
.tm
.base_opcode
== 0x6657
4132 || i
.tm
.base_opcode
== 0x66ef
4133 || i
.tm
.base_opcode
== 0x66f8
4134 || i
.tm
.base_opcode
== 0x66f9
4135 || i
.tm
.base_opcode
== 0x66fa
4136 || i
.tm
.base_opcode
== 0x66fb
4137 || i
.tm
.base_opcode
== 0x42
4138 || i
.tm
.base_opcode
== 0x6642
4139 || i
.tm
.base_opcode
== 0x47
4140 || i
.tm
.base_opcode
== 0x6647)
4141 && i
.tm
.extension_opcode
== None
))
4144 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4146 EVEX VOP %zmmM, %zmmM, %zmmN
4147 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4148 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4149 EVEX VOP %ymmM, %ymmM, %ymmN
4150 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4151 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4152 VEX VOP %ymmM, %ymmM, %ymmN
4153 -> VEX VOP %xmmM, %xmmM, %xmmN
4154 VOP, one of vpandn and vpxor:
4155 VEX VOP %ymmM, %ymmM, %ymmN
4156 -> VEX VOP %xmmM, %xmmM, %xmmN
4157 VOP, one of vpandnd and vpandnq:
4158 EVEX VOP %zmmM, %zmmM, %zmmN
4159 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4160 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4161 EVEX VOP %ymmM, %ymmM, %ymmN
4162 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4163 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4164 VOP, one of vpxord and vpxorq:
4165 EVEX VOP %zmmM, %zmmM, %zmmN
4166 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4167 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4168 EVEX VOP %ymmM, %ymmM, %ymmN
4169 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4170 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4171 VOP, one of kxord and kxorq:
4172 VEX VOP %kM, %kM, %kN
4173 -> VEX kxorw %kM, %kM, %kN
4174 VOP, one of kandnd and kandnq:
4175 VEX VOP %kM, %kM, %kN
4176 -> VEX kandnw %kM, %kM, %kN
4178 if (is_evex_encoding (&i
.tm
))
4180 if (i
.vec_encoding
!= vex_encoding_evex
)
4182 i
.tm
.opcode_modifier
.vex
= VEX128
;
4183 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4184 i
.tm
.opcode_modifier
.evex
= 0;
4186 else if (optimize
> 1)
4187 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4191 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4193 i
.tm
.base_opcode
&= 0xff;
4194 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4197 i
.tm
.opcode_modifier
.vex
= VEX128
;
4199 if (i
.tm
.opcode_modifier
.vex
)
4200 for (j
= 0; j
< 3; j
++)
4202 i
.types
[j
].bitfield
.xmmword
= 1;
4203 i
.types
[j
].bitfield
.ymmword
= 0;
4206 else if (i
.vec_encoding
!= vex_encoding_evex
4207 && !i
.types
[0].bitfield
.zmmword
4208 && !i
.types
[1].bitfield
.zmmword
4211 && is_evex_encoding (&i
.tm
)
4212 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x666f
4213 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf36f
4214 || (i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f
4215 || (i
.tm
.base_opcode
& ~4) == 0x66db
4216 || (i
.tm
.base_opcode
& ~4) == 0x66eb)
4217 && i
.tm
.extension_opcode
== None
)
4220 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4221 vmovdqu32 and vmovdqu64:
4222 EVEX VOP %xmmM, %xmmN
4223 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4224 EVEX VOP %ymmM, %ymmN
4225 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4227 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4229 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4231 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4233 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4234 VOP, one of vpand, vpandn, vpor, vpxor:
4235 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4236 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4237 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4238 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4239 EVEX VOP{d,q} mem, %xmmM, %xmmN
4240 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4241 EVEX VOP{d,q} mem, %ymmM, %ymmN
4242 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4244 for (j
= 0; j
< i
.operands
; j
++)
4245 if (operand_type_check (i
.types
[j
], disp
)
4246 && i
.op
[j
].disps
->X_op
== O_constant
)
4248 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4249 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4250 bytes, we choose EVEX Disp8 over VEX Disp32. */
4251 int evex_disp8
, vex_disp8
;
4252 unsigned int memshift
= i
.memshift
;
4253 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4255 evex_disp8
= fits_in_disp8 (n
);
4257 vex_disp8
= fits_in_disp8 (n
);
4258 if (evex_disp8
!= vex_disp8
)
4260 i
.memshift
= memshift
;
4264 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4267 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0xf26f)
4268 i
.tm
.base_opcode
^= 0xf36f ^ 0xf26f;
4269 i
.tm
.opcode_modifier
.vex
4270 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4271 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4272 /* VPAND, VPOR, and VPXOR are commutative. */
4273 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0x66df)
4274 i
.tm
.opcode_modifier
.commutative
= 1;
4275 i
.tm
.opcode_modifier
.evex
= 0;
4276 i
.tm
.opcode_modifier
.masking
= 0;
4277 i
.tm
.opcode_modifier
.broadcast
= 0;
4278 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4281 i
.types
[j
].bitfield
.disp8
4282 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4286 /* This is the guts of the machine-dependent assembler. LINE points to a
4287 machine dependent instruction. This function is supposed to emit
4288 the frags/bytes it assembles to. */
4291 md_assemble (char *line
)
4294 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
;
4295 const insn_template
*t
;
4297 /* Initialize globals. */
4298 memset (&i
, '\0', sizeof (i
));
4299 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4300 i
.reloc
[j
] = NO_RELOC
;
4301 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
4302 memset (im_expressions
, '\0', sizeof (im_expressions
));
4303 save_stack_p
= save_stack
;
4305 /* First parse an instruction mnemonic & call i386_operand for the operands.
4306 We assume that the scrubber has arranged it so that line[0] is the valid
4307 start of a (possibly prefixed) mnemonic. */
4309 line
= parse_insn (line
, mnemonic
);
4312 mnem_suffix
= i
.suffix
;
4314 line
= parse_operands (line
, mnemonic
);
4316 xfree (i
.memop1_string
);
4317 i
.memop1_string
= NULL
;
4321 /* Now we've parsed the mnemonic into a set of templates, and have the
4322 operands at hand. */
4324 /* All intel opcodes have reversed operands except for "bound" and
4325 "enter". We also don't reverse intersegment "jmp" and "call"
4326 instructions with 2 immediate operands so that the immediate segment
4327 precedes the offset, as it does when in AT&T mode. */
4330 && (strcmp (mnemonic
, "bound") != 0)
4331 && (strcmp (mnemonic
, "invlpga") != 0)
4332 && !(operand_type_check (i
.types
[0], imm
)
4333 && operand_type_check (i
.types
[1], imm
)))
4336 /* The order of the immediates should be reversed
4337 for 2 immediates extrq and insertq instructions */
4338 if (i
.imm_operands
== 2
4339 && (strcmp (mnemonic
, "extrq") == 0
4340 || strcmp (mnemonic
, "insertq") == 0))
4341 swap_2_operands (0, 1);
4346 /* Don't optimize displacement for movabs since it only takes 64bit
4349 && i
.disp_encoding
!= disp_encoding_32bit
4350 && (flag_code
!= CODE_64BIT
4351 || strcmp (mnemonic
, "movabs") != 0))
4354 /* Next, we find a template that matches the given insn,
4355 making sure the overlap of the given operands types is consistent
4356 with the template operand types. */
4358 if (!(t
= match_template (mnem_suffix
)))
4361 if (sse_check
!= check_none
4362 && !i
.tm
.opcode_modifier
.noavx
4363 && !i
.tm
.cpu_flags
.bitfield
.cpuavx
4364 && !i
.tm
.cpu_flags
.bitfield
.cpuavx512f
4365 && (i
.tm
.cpu_flags
.bitfield
.cpusse
4366 || i
.tm
.cpu_flags
.bitfield
.cpusse2
4367 || i
.tm
.cpu_flags
.bitfield
.cpusse3
4368 || i
.tm
.cpu_flags
.bitfield
.cpussse3
4369 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
4370 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
4371 || i
.tm
.cpu_flags
.bitfield
.cpusse4a
4372 || i
.tm
.cpu_flags
.bitfield
.cpupclmul
4373 || i
.tm
.cpu_flags
.bitfield
.cpuaes
4374 || i
.tm
.cpu_flags
.bitfield
.cpusha
4375 || i
.tm
.cpu_flags
.bitfield
.cpugfni
))
4377 (sse_check
== check_warning
4379 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
4382 /* Zap movzx and movsx suffix. The suffix has been set from
4383 "word ptr" or "byte ptr" on the source operand in Intel syntax
4384 or extracted from mnemonic in AT&T syntax. But we'll use
4385 the destination register to choose the suffix for encoding. */
4386 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
4388 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4389 there is no suffix, the default will be byte extension. */
4390 if (i
.reg_operands
!= 2
4393 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4398 if (i
.tm
.opcode_modifier
.fwait
)
4399 if (!add_prefix (FWAIT_OPCODE
))
4402 /* Check if REP prefix is OK. */
4403 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
4405 as_bad (_("invalid instruction `%s' after `%s'"),
4406 i
.tm
.name
, i
.rep_prefix
);
4410 /* Check for lock without a lockable instruction. Destination operand
4411 must be memory unless it is xchg (0x86). */
4412 if (i
.prefix
[LOCK_PREFIX
]
4413 && (!i
.tm
.opcode_modifier
.islockable
4414 || i
.mem_operands
== 0
4415 || (i
.tm
.base_opcode
!= 0x86
4416 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
))))
4418 as_bad (_("expecting lockable instruction after `lock'"));
4422 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4423 if (i
.prefix
[DATA_PREFIX
] && is_any_vex_encoding (&i
.tm
))
4425 as_bad (_("data size prefix invalid with `%s'"), i
.tm
.name
);
4429 /* Check if HLE prefix is OK. */
4430 if (i
.hle_prefix
&& !check_hle ())
4433 /* Check BND prefix. */
4434 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
4435 as_bad (_("expecting valid branch instruction after `bnd'"));
4437 /* Check NOTRACK prefix. */
4438 if (i
.notrack_prefix
&& !i
.tm
.opcode_modifier
.notrackprefixok
)
4439 as_bad (_("expecting indirect branch instruction after `notrack'"));
4441 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
)
4443 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4444 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4445 else if (flag_code
!= CODE_16BIT
4446 ? i
.prefix
[ADDR_PREFIX
]
4447 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
4448 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4451 /* Insert BND prefix. */
4452 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
4454 if (!i
.prefix
[BND_PREFIX
])
4455 add_prefix (BND_PREFIX_OPCODE
);
4456 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
4458 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4459 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
4463 /* Check string instruction segment overrides. */
4464 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
4466 gas_assert (i
.mem_operands
);
4467 if (!check_string ())
4469 i
.disp_operands
= 0;
4472 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
4473 optimize_encoding ();
4475 if (!process_suffix ())
4478 /* Update operand types. */
4479 for (j
= 0; j
< i
.operands
; j
++)
4480 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4482 /* Make still unresolved immediate matches conform to size of immediate
4483 given in i.suffix. */
4484 if (!finalize_imm ())
4487 if (i
.types
[0].bitfield
.imm1
)
4488 i
.imm_operands
= 0; /* kludge for shift insns. */
4490 /* We only need to check those implicit registers for instructions
4491 with 3 operands or less. */
4492 if (i
.operands
<= 3)
4493 for (j
= 0; j
< i
.operands
; j
++)
4494 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
4495 && !i
.types
[j
].bitfield
.xmmword
)
4498 /* ImmExt should be processed after SSE2AVX. */
4499 if (!i
.tm
.opcode_modifier
.sse2avx
4500 && i
.tm
.opcode_modifier
.immext
)
4503 /* For insns with operands there are more diddles to do to the opcode. */
4506 if (!process_operands ())
4509 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4511 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4512 as_warn (_("translating to `%sp'"), i
.tm
.name
);
4515 if (is_any_vex_encoding (&i
.tm
))
4517 if (!cpu_arch_flags
.bitfield
.cpui286
)
4519 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4524 if (i
.tm
.opcode_modifier
.vex
)
4525 build_vex_prefix (t
);
4527 build_evex_prefix ();
4530 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4531 instructions may define INT_OPCODE as well, so avoid this corner
4532 case for those instructions that use MODRM. */
4533 if (i
.tm
.base_opcode
== INT_OPCODE
4534 && !i
.tm
.opcode_modifier
.modrm
4535 && i
.op
[0].imms
->X_add_number
== 3)
4537 i
.tm
.base_opcode
= INT3_OPCODE
;
4541 if ((i
.tm
.opcode_modifier
.jump
== JUMP
4542 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
4543 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
4544 && i
.op
[0].disps
->X_op
== O_constant
)
4546 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4547 the absolute address given by the constant. Since ix86 jumps and
4548 calls are pc relative, we need to generate a reloc. */
4549 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
4550 i
.op
[0].disps
->X_op
= O_symbol
;
4553 if (i
.tm
.opcode_modifier
.rex64
)
4556 /* For 8 bit registers we need an empty rex prefix. Also if the
4557 instruction already has a prefix, we need to convert old
4558 registers to new ones. */
4560 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
4561 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
4562 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
4563 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
4564 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
4565 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
4570 i
.rex
|= REX_OPCODE
;
4571 for (x
= 0; x
< 2; x
++)
4573 /* Look for 8 bit operand that uses old registers. */
4574 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
4575 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
4577 /* In case it is "hi" register, give up. */
4578 if (i
.op
[x
].regs
->reg_num
> 3)
4579 as_bad (_("can't encode register '%s%s' in an "
4580 "instruction requiring REX prefix."),
4581 register_prefix
, i
.op
[x
].regs
->reg_name
);
4583 /* Otherwise it is equivalent to the extended register.
4584 Since the encoding doesn't change this is merely
4585 cosmetic cleanup for debug output. */
4587 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
4592 if (i
.rex
== 0 && i
.rex_encoding
)
4594 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4595 that uses legacy register. If it is "hi" register, don't add
4596 the REX_OPCODE byte. */
4598 for (x
= 0; x
< 2; x
++)
4599 if (i
.types
[x
].bitfield
.class == Reg
4600 && i
.types
[x
].bitfield
.byte
4601 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
4602 && i
.op
[x
].regs
->reg_num
> 3)
4604 i
.rex_encoding
= FALSE
;
4613 add_prefix (REX_OPCODE
| i
.rex
);
4615 /* We are ready to output the insn. */
4618 last_insn
.seg
= now_seg
;
4620 if (i
.tm
.opcode_modifier
.isprefix
)
4622 last_insn
.kind
= last_insn_prefix
;
4623 last_insn
.name
= i
.tm
.name
;
4624 last_insn
.file
= as_where (&last_insn
.line
);
4627 last_insn
.kind
= last_insn_other
;
4631 parse_insn (char *line
, char *mnemonic
)
4634 char *token_start
= l
;
4637 const insn_template
*t
;
4643 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
4648 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
4650 as_bad (_("no such instruction: `%s'"), token_start
);
4655 if (!is_space_char (*l
)
4656 && *l
!= END_OF_INSN
4658 || (*l
!= PREFIX_SEPARATOR
4661 as_bad (_("invalid character %s in mnemonic"),
4662 output_invalid (*l
));
4665 if (token_start
== l
)
4667 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
4668 as_bad (_("expecting prefix; got nothing"));
4670 as_bad (_("expecting mnemonic; got nothing"));
4674 /* Look up instruction (or prefix) via hash table. */
4675 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4677 if (*l
!= END_OF_INSN
4678 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
4679 && current_templates
4680 && current_templates
->start
->opcode_modifier
.isprefix
)
4682 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
4684 as_bad ((flag_code
!= CODE_64BIT
4685 ? _("`%s' is only supported in 64-bit mode")
4686 : _("`%s' is not supported in 64-bit mode")),
4687 current_templates
->start
->name
);
4690 /* If we are in 16-bit mode, do not allow addr16 or data16.
4691 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4692 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
4693 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4694 && flag_code
!= CODE_64BIT
4695 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
4696 ^ (flag_code
== CODE_16BIT
)))
4698 as_bad (_("redundant %s prefix"),
4699 current_templates
->start
->name
);
4702 if (current_templates
->start
->opcode_length
== 0)
4704 /* Handle pseudo prefixes. */
4705 switch (current_templates
->start
->base_opcode
)
4709 i
.disp_encoding
= disp_encoding_8bit
;
4713 i
.disp_encoding
= disp_encoding_32bit
;
4717 i
.dir_encoding
= dir_encoding_load
;
4721 i
.dir_encoding
= dir_encoding_store
;
4725 i
.vec_encoding
= vex_encoding_vex2
;
4729 i
.vec_encoding
= vex_encoding_vex3
;
4733 i
.vec_encoding
= vex_encoding_evex
;
4737 i
.rex_encoding
= TRUE
;
4741 i
.no_optimize
= TRUE
;
4749 /* Add prefix, checking for repeated prefixes. */
4750 switch (add_prefix (current_templates
->start
->base_opcode
))
4755 if (current_templates
->start
->cpu_flags
.bitfield
.cpuibt
)
4756 i
.notrack_prefix
= current_templates
->start
->name
;
4759 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
4760 i
.hle_prefix
= current_templates
->start
->name
;
4761 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
4762 i
.bnd_prefix
= current_templates
->start
->name
;
4764 i
.rep_prefix
= current_templates
->start
->name
;
4770 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4777 if (!current_templates
)
4779 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4780 Check if we should swap operand or force 32bit displacement in
4782 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
4783 i
.dir_encoding
= dir_encoding_swap
;
4784 else if (mnem_p
- 3 == dot_p
4787 i
.disp_encoding
= disp_encoding_8bit
;
4788 else if (mnem_p
- 4 == dot_p
4792 i
.disp_encoding
= disp_encoding_32bit
;
4797 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
4800 if (!current_templates
)
4803 if (mnem_p
> mnemonic
)
4805 /* See if we can get a match by trimming off a suffix. */
4808 case WORD_MNEM_SUFFIX
:
4809 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
4810 i
.suffix
= SHORT_MNEM_SUFFIX
;
4813 case BYTE_MNEM_SUFFIX
:
4814 case QWORD_MNEM_SUFFIX
:
4815 i
.suffix
= mnem_p
[-1];
4817 current_templates
= (const templates
*) hash_find (op_hash
,
4820 case SHORT_MNEM_SUFFIX
:
4821 case LONG_MNEM_SUFFIX
:
4824 i
.suffix
= mnem_p
[-1];
4826 current_templates
= (const templates
*) hash_find (op_hash
,
4835 if (intel_float_operand (mnemonic
) == 1)
4836 i
.suffix
= SHORT_MNEM_SUFFIX
;
4838 i
.suffix
= LONG_MNEM_SUFFIX
;
4840 current_templates
= (const templates
*) hash_find (op_hash
,
4847 if (!current_templates
)
4849 as_bad (_("no such instruction: `%s'"), token_start
);
4854 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
4855 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
4857 /* Check for a branch hint. We allow ",pt" and ",pn" for
4858 predict taken and predict not taken respectively.
4859 I'm not sure that branch hints actually do anything on loop
4860 and jcxz insns (JumpByte) for current Pentium4 chips. They
4861 may work in the future and it doesn't hurt to accept them
4863 if (l
[0] == ',' && l
[1] == 'p')
4867 if (!add_prefix (DS_PREFIX_OPCODE
))
4871 else if (l
[2] == 'n')
4873 if (!add_prefix (CS_PREFIX_OPCODE
))
4879 /* Any other comma loses. */
4882 as_bad (_("invalid character %s in mnemonic"),
4883 output_invalid (*l
));
4887 /* Check if instruction is supported on specified architecture. */
4889 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
4891 supported
|= cpu_flags_match (t
);
4892 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4894 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
))
4895 as_warn (_("use .code16 to ensure correct addressing mode"));
4901 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4902 as_bad (flag_code
== CODE_64BIT
4903 ? _("`%s' is not supported in 64-bit mode")
4904 : _("`%s' is only supported in 64-bit mode"),
4905 current_templates
->start
->name
);
4907 as_bad (_("`%s' is not supported on `%s%s'"),
4908 current_templates
->start
->name
,
4909 cpu_arch_name
? cpu_arch_name
: default_arch
,
4910 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4916 parse_operands (char *l
, const char *mnemonic
)
4920 /* 1 if operand is pending after ','. */
4921 unsigned int expecting_operand
= 0;
4923 /* Non-zero if operand parens not balanced. */
4924 unsigned int paren_not_balanced
;
4926 while (*l
!= END_OF_INSN
)
4928 /* Skip optional white space before operand. */
4929 if (is_space_char (*l
))
4931 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4933 as_bad (_("invalid character %s before operand %d"),
4934 output_invalid (*l
),
4938 token_start
= l
; /* After white space. */
4939 paren_not_balanced
= 0;
4940 while (paren_not_balanced
|| *l
!= ',')
4942 if (*l
== END_OF_INSN
)
4944 if (paren_not_balanced
)
4947 as_bad (_("unbalanced parenthesis in operand %d."),
4950 as_bad (_("unbalanced brackets in operand %d."),
4955 break; /* we are done */
4957 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4959 as_bad (_("invalid character %s in operand %d"),
4960 output_invalid (*l
),
4967 ++paren_not_balanced
;
4969 --paren_not_balanced
;
4974 ++paren_not_balanced
;
4976 --paren_not_balanced
;
4980 if (l
!= token_start
)
4981 { /* Yes, we've read in another operand. */
4982 unsigned int operand_ok
;
4983 this_operand
= i
.operands
++;
4984 if (i
.operands
> MAX_OPERANDS
)
4986 as_bad (_("spurious operands; (%d operands/instruction max)"),
4990 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4991 /* Now parse operand adding info to 'i' as we go along. */
4992 END_STRING_AND_SAVE (l
);
4994 if (i
.mem_operands
> 1)
4996 as_bad (_("too many memory references for `%s'"),
5003 i386_intel_operand (token_start
,
5004 intel_float_operand (mnemonic
));
5006 operand_ok
= i386_att_operand (token_start
);
5008 RESTORE_END_STRING (l
);
5014 if (expecting_operand
)
5016 expecting_operand_after_comma
:
5017 as_bad (_("expecting operand after ','; got nothing"));
5022 as_bad (_("expecting operand before ','; got nothing"));
5027 /* Now *l must be either ',' or END_OF_INSN. */
5030 if (*++l
== END_OF_INSN
)
5032 /* Just skip it, if it's \n complain. */
5033 goto expecting_operand_after_comma
;
5035 expecting_operand
= 1;
5042 swap_2_operands (int xchg1
, int xchg2
)
5044 union i386_op temp_op
;
5045 i386_operand_type temp_type
;
5046 unsigned int temp_flags
;
5047 enum bfd_reloc_code_real temp_reloc
;
5049 temp_type
= i
.types
[xchg2
];
5050 i
.types
[xchg2
] = i
.types
[xchg1
];
5051 i
.types
[xchg1
] = temp_type
;
5053 temp_flags
= i
.flags
[xchg2
];
5054 i
.flags
[xchg2
] = i
.flags
[xchg1
];
5055 i
.flags
[xchg1
] = temp_flags
;
5057 temp_op
= i
.op
[xchg2
];
5058 i
.op
[xchg2
] = i
.op
[xchg1
];
5059 i
.op
[xchg1
] = temp_op
;
5061 temp_reloc
= i
.reloc
[xchg2
];
5062 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
5063 i
.reloc
[xchg1
] = temp_reloc
;
5067 if (i
.mask
->operand
== xchg1
)
5068 i
.mask
->operand
= xchg2
;
5069 else if (i
.mask
->operand
== xchg2
)
5070 i
.mask
->operand
= xchg1
;
5074 if (i
.broadcast
->operand
== xchg1
)
5075 i
.broadcast
->operand
= xchg2
;
5076 else if (i
.broadcast
->operand
== xchg2
)
5077 i
.broadcast
->operand
= xchg1
;
5081 if (i
.rounding
->operand
== xchg1
)
5082 i
.rounding
->operand
= xchg2
;
5083 else if (i
.rounding
->operand
== xchg2
)
5084 i
.rounding
->operand
= xchg1
;
5089 swap_operands (void)
5095 swap_2_operands (1, i
.operands
- 2);
5099 swap_2_operands (0, i
.operands
- 1);
5105 if (i
.mem_operands
== 2)
5107 const seg_entry
*temp_seg
;
5108 temp_seg
= i
.seg
[0];
5109 i
.seg
[0] = i
.seg
[1];
5110 i
.seg
[1] = temp_seg
;
5114 /* Try to ensure constant immediates are represented in the smallest
5119 char guess_suffix
= 0;
5123 guess_suffix
= i
.suffix
;
5124 else if (i
.reg_operands
)
5126 /* Figure out a suffix from the last register operand specified.
5127 We can't do this properly yet, i.e. excluding special register
5128 instances, but the following works for instructions with
5129 immediates. In any case, we can't set i.suffix yet. */
5130 for (op
= i
.operands
; --op
>= 0;)
5131 if (i
.types
[op
].bitfield
.class != Reg
)
5133 else if (i
.types
[op
].bitfield
.byte
)
5135 guess_suffix
= BYTE_MNEM_SUFFIX
;
5138 else if (i
.types
[op
].bitfield
.word
)
5140 guess_suffix
= WORD_MNEM_SUFFIX
;
5143 else if (i
.types
[op
].bitfield
.dword
)
5145 guess_suffix
= LONG_MNEM_SUFFIX
;
5148 else if (i
.types
[op
].bitfield
.qword
)
5150 guess_suffix
= QWORD_MNEM_SUFFIX
;
5154 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5155 guess_suffix
= WORD_MNEM_SUFFIX
;
5157 for (op
= i
.operands
; --op
>= 0;)
5158 if (operand_type_check (i
.types
[op
], imm
))
5160 switch (i
.op
[op
].imms
->X_op
)
5163 /* If a suffix is given, this operand may be shortened. */
5164 switch (guess_suffix
)
5166 case LONG_MNEM_SUFFIX
:
5167 i
.types
[op
].bitfield
.imm32
= 1;
5168 i
.types
[op
].bitfield
.imm64
= 1;
5170 case WORD_MNEM_SUFFIX
:
5171 i
.types
[op
].bitfield
.imm16
= 1;
5172 i
.types
[op
].bitfield
.imm32
= 1;
5173 i
.types
[op
].bitfield
.imm32s
= 1;
5174 i
.types
[op
].bitfield
.imm64
= 1;
5176 case BYTE_MNEM_SUFFIX
:
5177 i
.types
[op
].bitfield
.imm8
= 1;
5178 i
.types
[op
].bitfield
.imm8s
= 1;
5179 i
.types
[op
].bitfield
.imm16
= 1;
5180 i
.types
[op
].bitfield
.imm32
= 1;
5181 i
.types
[op
].bitfield
.imm32s
= 1;
5182 i
.types
[op
].bitfield
.imm64
= 1;
5186 /* If this operand is at most 16 bits, convert it
5187 to a signed 16 bit number before trying to see
5188 whether it will fit in an even smaller size.
5189 This allows a 16-bit operand such as $0xffe0 to
5190 be recognised as within Imm8S range. */
5191 if ((i
.types
[op
].bitfield
.imm16
)
5192 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
5194 i
.op
[op
].imms
->X_add_number
=
5195 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
5198 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5199 if ((i
.types
[op
].bitfield
.imm32
)
5200 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
5203 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
5204 ^ ((offsetT
) 1 << 31))
5205 - ((offsetT
) 1 << 31));
5209 = operand_type_or (i
.types
[op
],
5210 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
5212 /* We must avoid matching of Imm32 templates when 64bit
5213 only immediate is available. */
5214 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
5215 i
.types
[op
].bitfield
.imm32
= 0;
5222 /* Symbols and expressions. */
5224 /* Convert symbolic operand to proper sizes for matching, but don't
5225 prevent matching a set of insns that only supports sizes other
5226 than those matching the insn suffix. */
5228 i386_operand_type mask
, allowed
;
5229 const insn_template
*t
;
5231 operand_type_set (&mask
, 0);
5232 operand_type_set (&allowed
, 0);
5234 for (t
= current_templates
->start
;
5235 t
< current_templates
->end
;
5238 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
5239 allowed
= operand_type_and (allowed
, anyimm
);
5241 switch (guess_suffix
)
5243 case QWORD_MNEM_SUFFIX
:
5244 mask
.bitfield
.imm64
= 1;
5245 mask
.bitfield
.imm32s
= 1;
5247 case LONG_MNEM_SUFFIX
:
5248 mask
.bitfield
.imm32
= 1;
5250 case WORD_MNEM_SUFFIX
:
5251 mask
.bitfield
.imm16
= 1;
5253 case BYTE_MNEM_SUFFIX
:
5254 mask
.bitfield
.imm8
= 1;
5259 allowed
= operand_type_and (mask
, allowed
);
5260 if (!operand_type_all_zero (&allowed
))
5261 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
5268 /* Try to use the smallest displacement type too. */
5270 optimize_disp (void)
5274 for (op
= i
.operands
; --op
>= 0;)
5275 if (operand_type_check (i
.types
[op
], disp
))
5277 if (i
.op
[op
].disps
->X_op
== O_constant
)
5279 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
5281 if (i
.types
[op
].bitfield
.disp16
5282 && (op_disp
& ~(offsetT
) 0xffff) == 0)
5284 /* If this operand is at most 16 bits, convert
5285 to a signed 16 bit number and don't use 64bit
5287 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
5288 i
.types
[op
].bitfield
.disp64
= 0;
5291 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5292 if (i
.types
[op
].bitfield
.disp32
5293 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
5295 /* If this operand is at most 32 bits, convert
5296 to a signed 32 bit number and don't use 64bit
5298 op_disp
&= (((offsetT
) 2 << 31) - 1);
5299 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
5300 i
.types
[op
].bitfield
.disp64
= 0;
5303 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
5305 i
.types
[op
].bitfield
.disp8
= 0;
5306 i
.types
[op
].bitfield
.disp16
= 0;
5307 i
.types
[op
].bitfield
.disp32
= 0;
5308 i
.types
[op
].bitfield
.disp32s
= 0;
5309 i
.types
[op
].bitfield
.disp64
= 0;
5313 else if (flag_code
== CODE_64BIT
)
5315 if (fits_in_signed_long (op_disp
))
5317 i
.types
[op
].bitfield
.disp64
= 0;
5318 i
.types
[op
].bitfield
.disp32s
= 1;
5320 if (i
.prefix
[ADDR_PREFIX
]
5321 && fits_in_unsigned_long (op_disp
))
5322 i
.types
[op
].bitfield
.disp32
= 1;
5324 if ((i
.types
[op
].bitfield
.disp32
5325 || i
.types
[op
].bitfield
.disp32s
5326 || i
.types
[op
].bitfield
.disp16
)
5327 && fits_in_disp8 (op_disp
))
5328 i
.types
[op
].bitfield
.disp8
= 1;
5330 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5331 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
5333 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
5334 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
5335 i
.types
[op
].bitfield
.disp8
= 0;
5336 i
.types
[op
].bitfield
.disp16
= 0;
5337 i
.types
[op
].bitfield
.disp32
= 0;
5338 i
.types
[op
].bitfield
.disp32s
= 0;
5339 i
.types
[op
].bitfield
.disp64
= 0;
5342 /* We only support 64bit displacement on constants. */
5343 i
.types
[op
].bitfield
.disp64
= 0;
5347 /* Return 1 if there is a match in broadcast bytes between operand
5348 GIVEN and instruction template T. */
5351 match_broadcast_size (const insn_template
*t
, unsigned int given
)
5353 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
5354 && i
.types
[given
].bitfield
.byte
)
5355 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
5356 && i
.types
[given
].bitfield
.word
)
5357 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
5358 && i
.types
[given
].bitfield
.dword
)
5359 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
5360 && i
.types
[given
].bitfield
.qword
));
5363 /* Check if operands are valid for the instruction. */
5366 check_VecOperands (const insn_template
*t
)
5370 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
5372 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5373 any one operand are implicity requiring AVX512VL support if the actual
5374 operand size is YMMword or XMMword. Since this function runs after
5375 template matching, there's no need to check for YMMword/XMMword in
5377 cpu
= cpu_flags_and (t
->cpu_flags
, avx512
);
5378 if (!cpu_flags_all_zero (&cpu
)
5379 && !t
->cpu_flags
.bitfield
.cpuavx512vl
5380 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
5382 for (op
= 0; op
< t
->operands
; ++op
)
5384 if (t
->operand_types
[op
].bitfield
.zmmword
5385 && (i
.types
[op
].bitfield
.ymmword
5386 || i
.types
[op
].bitfield
.xmmword
))
5388 i
.error
= unsupported
;
5394 /* Without VSIB byte, we can't have a vector register for index. */
5395 if (!t
->opcode_modifier
.vecsib
5397 && (i
.index_reg
->reg_type
.bitfield
.xmmword
5398 || i
.index_reg
->reg_type
.bitfield
.ymmword
5399 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
5401 i
.error
= unsupported_vector_index_register
;
5405 /* Check if default mask is allowed. */
5406 if (t
->opcode_modifier
.nodefmask
5407 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
5409 i
.error
= no_default_mask
;
5413 /* For VSIB byte, we need a vector register for index, and all vector
5414 registers must be distinct. */
5415 if (t
->opcode_modifier
.vecsib
)
5418 || !((t
->opcode_modifier
.vecsib
== VecSIB128
5419 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
5420 || (t
->opcode_modifier
.vecsib
== VecSIB256
5421 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
5422 || (t
->opcode_modifier
.vecsib
== VecSIB512
5423 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
5425 i
.error
= invalid_vsib_address
;
5429 gas_assert (i
.reg_operands
== 2 || i
.mask
);
5430 if (i
.reg_operands
== 2 && !i
.mask
)
5432 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
5433 gas_assert (i
.types
[0].bitfield
.xmmword
5434 || i
.types
[0].bitfield
.ymmword
);
5435 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
5436 gas_assert (i
.types
[2].bitfield
.xmmword
5437 || i
.types
[2].bitfield
.ymmword
);
5438 if (operand_check
== check_none
)
5440 if (register_number (i
.op
[0].regs
)
5441 != register_number (i
.index_reg
)
5442 && register_number (i
.op
[2].regs
)
5443 != register_number (i
.index_reg
)
5444 && register_number (i
.op
[0].regs
)
5445 != register_number (i
.op
[2].regs
))
5447 if (operand_check
== check_error
)
5449 i
.error
= invalid_vector_register_set
;
5452 as_warn (_("mask, index, and destination registers should be distinct"));
5454 else if (i
.reg_operands
== 1 && i
.mask
)
5456 if (i
.types
[1].bitfield
.class == RegSIMD
5457 && (i
.types
[1].bitfield
.xmmword
5458 || i
.types
[1].bitfield
.ymmword
5459 || i
.types
[1].bitfield
.zmmword
)
5460 && (register_number (i
.op
[1].regs
)
5461 == register_number (i
.index_reg
)))
5463 if (operand_check
== check_error
)
5465 i
.error
= invalid_vector_register_set
;
5468 if (operand_check
!= check_none
)
5469 as_warn (_("index and destination registers should be distinct"));
5474 /* Check if broadcast is supported by the instruction and is applied
5475 to the memory operand. */
5478 i386_operand_type type
, overlap
;
5480 /* Check if specified broadcast is supported in this instruction,
5481 and its broadcast bytes match the memory operand. */
5482 op
= i
.broadcast
->operand
;
5483 if (!t
->opcode_modifier
.broadcast
5484 || !(i
.flags
[op
] & Operand_Mem
)
5485 || (!i
.types
[op
].bitfield
.unspecified
5486 && !match_broadcast_size (t
, op
)))
5489 i
.error
= unsupported_broadcast
;
5493 i
.broadcast
->bytes
= ((1 << (t
->opcode_modifier
.broadcast
- 1))
5494 * i
.broadcast
->type
);
5495 operand_type_set (&type
, 0);
5496 switch (i
.broadcast
->bytes
)
5499 type
.bitfield
.word
= 1;
5502 type
.bitfield
.dword
= 1;
5505 type
.bitfield
.qword
= 1;
5508 type
.bitfield
.xmmword
= 1;
5511 type
.bitfield
.ymmword
= 1;
5514 type
.bitfield
.zmmword
= 1;
5520 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
5521 if (operand_type_all_zero (&overlap
))
5524 if (t
->opcode_modifier
.checkregsize
)
5528 type
.bitfield
.baseindex
= 1;
5529 for (j
= 0; j
< i
.operands
; ++j
)
5532 && !operand_type_register_match(i
.types
[j
],
5533 t
->operand_types
[j
],
5535 t
->operand_types
[op
]))
5540 /* If broadcast is supported in this instruction, we need to check if
5541 operand of one-element size isn't specified without broadcast. */
5542 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
5544 /* Find memory operand. */
5545 for (op
= 0; op
< i
.operands
; op
++)
5546 if (i
.flags
[op
] & Operand_Mem
)
5548 gas_assert (op
< i
.operands
);
5549 /* Check size of the memory operand. */
5550 if (match_broadcast_size (t
, op
))
5552 i
.error
= broadcast_needed
;
5557 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
5559 /* Check if requested masking is supported. */
5562 switch (t
->opcode_modifier
.masking
)
5566 case MERGING_MASKING
:
5567 if (i
.mask
->zeroing
)
5570 i
.error
= unsupported_masking
;
5574 case DYNAMIC_MASKING
:
5575 /* Memory destinations allow only merging masking. */
5576 if (i
.mask
->zeroing
&& i
.mem_operands
)
5578 /* Find memory operand. */
5579 for (op
= 0; op
< i
.operands
; op
++)
5580 if (i
.flags
[op
] & Operand_Mem
)
5582 gas_assert (op
< i
.operands
);
5583 if (op
== i
.operands
- 1)
5585 i
.error
= unsupported_masking
;
5595 /* Check if masking is applied to dest operand. */
5596 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
5598 i
.error
= mask_not_on_destination
;
5605 if (!t
->opcode_modifier
.sae
5606 || (i
.rounding
->type
!= saeonly
&& !t
->opcode_modifier
.staticrounding
))
5608 i
.error
= unsupported_rc_sae
;
5611 /* If the instruction has several immediate operands and one of
5612 them is rounding, the rounding operand should be the last
5613 immediate operand. */
5614 if (i
.imm_operands
> 1
5615 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
5617 i
.error
= rc_sae_operand_not_last_imm
;
5622 /* Check vector Disp8 operand. */
5623 if (t
->opcode_modifier
.disp8memshift
5624 && i
.disp_encoding
!= disp_encoding_32bit
)
5627 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
5628 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
5629 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
5632 const i386_operand_type
*type
= NULL
;
5635 for (op
= 0; op
< i
.operands
; op
++)
5636 if (i
.flags
[op
] & Operand_Mem
)
5638 if (t
->opcode_modifier
.evex
== EVEXLIG
)
5639 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
5640 else if (t
->operand_types
[op
].bitfield
.xmmword
5641 + t
->operand_types
[op
].bitfield
.ymmword
5642 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
5643 type
= &t
->operand_types
[op
];
5644 else if (!i
.types
[op
].bitfield
.unspecified
)
5645 type
= &i
.types
[op
];
5647 else if (i
.types
[op
].bitfield
.class == RegSIMD
5648 && t
->opcode_modifier
.evex
!= EVEXLIG
)
5650 if (i
.types
[op
].bitfield
.zmmword
)
5652 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
5654 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
5660 if (type
->bitfield
.zmmword
)
5662 else if (type
->bitfield
.ymmword
)
5664 else if (type
->bitfield
.xmmword
)
5668 /* For the check in fits_in_disp8(). */
5669 if (i
.memshift
== 0)
5673 for (op
= 0; op
< i
.operands
; op
++)
5674 if (operand_type_check (i
.types
[op
], disp
)
5675 && i
.op
[op
].disps
->X_op
== O_constant
)
5677 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
5679 i
.types
[op
].bitfield
.disp8
= 1;
5682 i
.types
[op
].bitfield
.disp8
= 0;
5691 /* Check if operands are valid for the instruction. Update VEX
5695 VEX_check_operands (const insn_template
*t
)
5697 if (i
.vec_encoding
== vex_encoding_evex
)
5699 /* This instruction must be encoded with EVEX prefix. */
5700 if (!is_evex_encoding (t
))
5702 i
.error
= unsupported
;
5708 if (!t
->opcode_modifier
.vex
)
5710 /* This instruction template doesn't have VEX prefix. */
5711 if (i
.vec_encoding
!= vex_encoding_default
)
5713 i
.error
= unsupported
;
5719 /* Check the special Imm4 cases; must be the first operand. */
5720 if (t
->cpu_flags
.bitfield
.cpuxop
&& t
->operands
== 5)
5722 if (i
.op
[0].imms
->X_op
!= O_constant
5723 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
5729 /* Turn off Imm<N> so that update_imm won't complain. */
5730 operand_type_set (&i
.types
[0], 0);
5736 static const insn_template
*
5737 match_template (char mnem_suffix
)
5739 /* Points to template once we've found it. */
5740 const insn_template
*t
;
5741 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
5742 i386_operand_type overlap4
;
5743 unsigned int found_reverse_match
;
5744 i386_opcode_modifier suffix_check
;
5745 i386_operand_type operand_types
[MAX_OPERANDS
];
5746 int addr_prefix_disp
;
5748 unsigned int found_cpu_match
, size_match
;
5749 unsigned int check_register
;
5750 enum i386_error specific_error
= 0;
5752 #if MAX_OPERANDS != 5
5753 # error "MAX_OPERANDS must be 5."
5756 found_reverse_match
= 0;
5757 addr_prefix_disp
= -1;
5759 /* Prepare for mnemonic suffix check. */
5760 memset (&suffix_check
, 0, sizeof (suffix_check
));
5761 switch (mnem_suffix
)
5763 case BYTE_MNEM_SUFFIX
:
5764 suffix_check
.no_bsuf
= 1;
5766 case WORD_MNEM_SUFFIX
:
5767 suffix_check
.no_wsuf
= 1;
5769 case SHORT_MNEM_SUFFIX
:
5770 suffix_check
.no_ssuf
= 1;
5772 case LONG_MNEM_SUFFIX
:
5773 suffix_check
.no_lsuf
= 1;
5775 case QWORD_MNEM_SUFFIX
:
5776 suffix_check
.no_qsuf
= 1;
5779 /* NB: In Intel syntax, normally we can check for memory operand
5780 size when there is no mnemonic suffix. But jmp and call have
5781 2 different encodings with Dword memory operand size, one with
5782 No_ldSuf and the other without. i.suffix is set to
5783 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
5784 if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
5785 suffix_check
.no_ldsuf
= 1;
5788 /* Must have right number of operands. */
5789 i
.error
= number_of_operands_mismatch
;
5791 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
5793 addr_prefix_disp
= -1;
5794 found_reverse_match
= 0;
5796 if (i
.operands
!= t
->operands
)
5799 /* Check processor support. */
5800 i
.error
= unsupported
;
5801 found_cpu_match
= (cpu_flags_match (t
)
5802 == CPU_FLAGS_PERFECT_MATCH
);
5803 if (!found_cpu_match
)
5806 /* Check AT&T mnemonic. */
5807 i
.error
= unsupported_with_intel_mnemonic
;
5808 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
5811 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5812 i
.error
= unsupported_syntax
;
5813 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
5814 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
)
5815 || (intel64
&& t
->opcode_modifier
.amd64
)
5816 || (!intel64
&& t
->opcode_modifier
.intel64
))
5819 /* Check the suffix. */
5820 i
.error
= invalid_instruction_suffix
;
5821 if ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
5822 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
5823 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
5824 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
5825 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
5826 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
))
5829 size_match
= operand_size_match (t
);
5833 /* This is intentionally not
5835 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
5837 as the case of a missing * on the operand is accepted (perhaps with
5838 a warning, issued further down). */
5839 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
5841 i
.error
= operand_type_mismatch
;
5845 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5846 operand_types
[j
] = t
->operand_types
[j
];
5848 /* In general, don't allow 64-bit operands in 32-bit mode. */
5849 if (i
.suffix
== QWORD_MNEM_SUFFIX
5850 && flag_code
!= CODE_64BIT
5852 ? (!t
->opcode_modifier
.ignoresize
5853 && !t
->opcode_modifier
.broadcast
5854 && !intel_float_operand (t
->name
))
5855 : intel_float_operand (t
->name
) != 2)
5856 && ((operand_types
[0].bitfield
.class != RegMMX
5857 && operand_types
[0].bitfield
.class != RegSIMD
)
5858 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5859 && operand_types
[t
->operands
> 1].bitfield
.class != RegSIMD
))
5860 && (t
->base_opcode
!= 0x0fc7
5861 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
5864 /* In general, don't allow 32-bit operands on pre-386. */
5865 else if (i
.suffix
== LONG_MNEM_SUFFIX
5866 && !cpu_arch_flags
.bitfield
.cpui386
5868 ? (!t
->opcode_modifier
.ignoresize
5869 && !intel_float_operand (t
->name
))
5870 : intel_float_operand (t
->name
) != 2)
5871 && ((operand_types
[0].bitfield
.class != RegMMX
5872 && operand_types
[0].bitfield
.class != RegSIMD
)
5873 || (operand_types
[t
->operands
> 1].bitfield
.class != RegMMX
5874 && operand_types
[t
->operands
> 1].bitfield
.class
5878 /* Do not verify operands when there are none. */
5882 /* We've found a match; break out of loop. */
5886 if (!t
->opcode_modifier
.jump
5887 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
5889 /* There should be only one Disp operand. */
5890 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5891 if (operand_type_check (operand_types
[j
], disp
))
5893 if (j
< MAX_OPERANDS
)
5895 bfd_boolean override
= (i
.prefix
[ADDR_PREFIX
] != 0);
5897 addr_prefix_disp
= j
;
5899 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
5900 operand into Disp32/Disp32/Disp16/Disp32 operand. */
5904 override
= !override
;
5907 if (operand_types
[j
].bitfield
.disp32
5908 && operand_types
[j
].bitfield
.disp16
)
5910 operand_types
[j
].bitfield
.disp16
= override
;
5911 operand_types
[j
].bitfield
.disp32
= !override
;
5913 operand_types
[j
].bitfield
.disp32s
= 0;
5914 operand_types
[j
].bitfield
.disp64
= 0;
5918 if (operand_types
[j
].bitfield
.disp32s
5919 || operand_types
[j
].bitfield
.disp64
)
5921 operand_types
[j
].bitfield
.disp64
&= !override
;
5922 operand_types
[j
].bitfield
.disp32s
&= !override
;
5923 operand_types
[j
].bitfield
.disp32
= override
;
5925 operand_types
[j
].bitfield
.disp16
= 0;
5931 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5932 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
5935 /* We check register size if needed. */
5936 if (t
->opcode_modifier
.checkregsize
)
5938 check_register
= (1 << t
->operands
) - 1;
5940 check_register
&= ~(1 << i
.broadcast
->operand
);
5945 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
5946 switch (t
->operands
)
5949 if (!operand_type_match (overlap0
, i
.types
[0]))
5953 /* xchg %eax, %eax is a special case. It is an alias for nop
5954 only in 32bit mode and we can use opcode 0x90. In 64bit
5955 mode, we can't use 0x90 for xchg %eax, %eax since it should
5956 zero-extend %eax to %rax. */
5957 if (flag_code
== CODE_64BIT
5958 && t
->base_opcode
== 0x90
5959 && i
.types
[0].bitfield
.instance
== Accum
5960 && i
.types
[0].bitfield
.dword
5961 && i
.types
[1].bitfield
.instance
== Accum
5962 && i
.types
[1].bitfield
.dword
)
5964 /* xrelease mov %eax, <disp> is another special case. It must not
5965 match the accumulator-only encoding of mov. */
5966 if (flag_code
!= CODE_64BIT
5968 && t
->base_opcode
== 0xa0
5969 && i
.types
[0].bitfield
.instance
== Accum
5970 && (i
.flags
[1] & Operand_Mem
))
5975 if (!(size_match
& MATCH_STRAIGHT
))
5977 /* Reverse direction of operands if swapping is possible in the first
5978 place (operands need to be symmetric) and
5979 - the load form is requested, and the template is a store form,
5980 - the store form is requested, and the template is a load form,
5981 - the non-default (swapped) form is requested. */
5982 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
5983 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
5984 && !operand_type_all_zero (&overlap1
))
5985 switch (i
.dir_encoding
)
5987 case dir_encoding_load
:
5988 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5989 || t
->opcode_modifier
.regmem
)
5993 case dir_encoding_store
:
5994 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
5995 && !t
->opcode_modifier
.regmem
)
5999 case dir_encoding_swap
:
6002 case dir_encoding_default
:
6005 /* If we want store form, we skip the current load. */
6006 if ((i
.dir_encoding
== dir_encoding_store
6007 || i
.dir_encoding
== dir_encoding_swap
)
6008 && i
.mem_operands
== 0
6009 && t
->opcode_modifier
.load
)
6014 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
6015 if (!operand_type_match (overlap0
, i
.types
[0])
6016 || !operand_type_match (overlap1
, i
.types
[1])
6017 || ((check_register
& 3) == 3
6018 && !operand_type_register_match (i
.types
[0],
6023 /* Check if other direction is valid ... */
6024 if (!t
->opcode_modifier
.d
)
6028 if (!(size_match
& MATCH_REVERSE
))
6030 /* Try reversing direction of operands. */
6031 overlap0
= operand_type_and (i
.types
[0], operand_types
[i
.operands
- 1]);
6032 overlap1
= operand_type_and (i
.types
[i
.operands
- 1], operand_types
[0]);
6033 if (!operand_type_match (overlap0
, i
.types
[0])
6034 || !operand_type_match (overlap1
, i
.types
[i
.operands
- 1])
6036 && !operand_type_register_match (i
.types
[0],
6037 operand_types
[i
.operands
- 1],
6038 i
.types
[i
.operands
- 1],
6041 /* Does not match either direction. */
6044 /* found_reverse_match holds which of D or FloatR
6046 if (!t
->opcode_modifier
.d
)
6047 found_reverse_match
= 0;
6048 else if (operand_types
[0].bitfield
.tbyte
)
6049 found_reverse_match
= Opcode_FloatD
;
6050 else if (operand_types
[0].bitfield
.xmmword
6051 || operand_types
[i
.operands
- 1].bitfield
.xmmword
6052 || operand_types
[0].bitfield
.class == RegMMX
6053 || operand_types
[i
.operands
- 1].bitfield
.class == RegMMX
6054 || is_any_vex_encoding(t
))
6055 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
6056 ? Opcode_SIMD_FloatD
: Opcode_SIMD_IntD
;
6058 found_reverse_match
= Opcode_D
;
6059 if (t
->opcode_modifier
.floatr
)
6060 found_reverse_match
|= Opcode_FloatR
;
6064 /* Found a forward 2 operand match here. */
6065 switch (t
->operands
)
6068 overlap4
= operand_type_and (i
.types
[4],
6072 overlap3
= operand_type_and (i
.types
[3],
6076 overlap2
= operand_type_and (i
.types
[2],
6081 switch (t
->operands
)
6084 if (!operand_type_match (overlap4
, i
.types
[4])
6085 || !operand_type_register_match (i
.types
[3],
6092 if (!operand_type_match (overlap3
, i
.types
[3])
6093 || ((check_register
& 0xa) == 0xa
6094 && !operand_type_register_match (i
.types
[1],
6098 || ((check_register
& 0xc) == 0xc
6099 && !operand_type_register_match (i
.types
[2],
6106 /* Here we make use of the fact that there are no
6107 reverse match 3 operand instructions. */
6108 if (!operand_type_match (overlap2
, i
.types
[2])
6109 || ((check_register
& 5) == 5
6110 && !operand_type_register_match (i
.types
[0],
6114 || ((check_register
& 6) == 6
6115 && !operand_type_register_match (i
.types
[1],
6123 /* Found either forward/reverse 2, 3 or 4 operand match here:
6124 slip through to break. */
6126 if (!found_cpu_match
)
6129 /* Check if vector and VEX operands are valid. */
6130 if (check_VecOperands (t
) || VEX_check_operands (t
))
6132 specific_error
= i
.error
;
6136 /* We've found a match; break out of loop. */
6140 if (t
== current_templates
->end
)
6142 /* We found no match. */
6143 const char *err_msg
;
6144 switch (specific_error
? specific_error
: i
.error
)
6148 case operand_size_mismatch
:
6149 err_msg
= _("operand size mismatch");
6151 case operand_type_mismatch
:
6152 err_msg
= _("operand type mismatch");
6154 case register_type_mismatch
:
6155 err_msg
= _("register type mismatch");
6157 case number_of_operands_mismatch
:
6158 err_msg
= _("number of operands mismatch");
6160 case invalid_instruction_suffix
:
6161 err_msg
= _("invalid instruction suffix");
6164 err_msg
= _("constant doesn't fit in 4 bits");
6166 case unsupported_with_intel_mnemonic
:
6167 err_msg
= _("unsupported with Intel mnemonic");
6169 case unsupported_syntax
:
6170 err_msg
= _("unsupported syntax");
6173 as_bad (_("unsupported instruction `%s'"),
6174 current_templates
->start
->name
);
6176 case invalid_vsib_address
:
6177 err_msg
= _("invalid VSIB address");
6179 case invalid_vector_register_set
:
6180 err_msg
= _("mask, index, and destination registers must be distinct");
6182 case unsupported_vector_index_register
:
6183 err_msg
= _("unsupported vector index register");
6185 case unsupported_broadcast
:
6186 err_msg
= _("unsupported broadcast");
6188 case broadcast_needed
:
6189 err_msg
= _("broadcast is needed for operand of such type");
6191 case unsupported_masking
:
6192 err_msg
= _("unsupported masking");
6194 case mask_not_on_destination
:
6195 err_msg
= _("mask not on destination operand");
6197 case no_default_mask
:
6198 err_msg
= _("default mask isn't allowed");
6200 case unsupported_rc_sae
:
6201 err_msg
= _("unsupported static rounding/sae");
6203 case rc_sae_operand_not_last_imm
:
6205 err_msg
= _("RC/SAE operand must precede immediate operands");
6207 err_msg
= _("RC/SAE operand must follow immediate operands");
6209 case invalid_register_operand
:
6210 err_msg
= _("invalid register operand");
6213 as_bad (_("%s for `%s'"), err_msg
,
6214 current_templates
->start
->name
);
6218 if (!quiet_warnings
)
6221 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
6222 as_warn (_("indirect %s without `*'"), t
->name
);
6224 if (t
->opcode_modifier
.isprefix
6225 && t
->opcode_modifier
.ignoresize
)
6227 /* Warn them that a data or address size prefix doesn't
6228 affect assembly of the next line of code. */
6229 as_warn (_("stand-alone `%s' prefix"), t
->name
);
6233 /* Copy the template we found. */
6236 if (addr_prefix_disp
!= -1)
6237 i
.tm
.operand_types
[addr_prefix_disp
]
6238 = operand_types
[addr_prefix_disp
];
6240 if (found_reverse_match
)
6242 /* If we found a reverse match we must alter the opcode direction
6243 bit and clear/flip the regmem modifier one. found_reverse_match
6244 holds bits to change (different for int & float insns). */
6246 i
.tm
.base_opcode
^= found_reverse_match
;
6248 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
6249 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
6251 /* Certain SIMD insns have their load forms specified in the opcode
6252 table, and hence we need to _set_ RegMem instead of clearing it.
6253 We need to avoid setting the bit though on insns like KMOVW. */
6254 i
.tm
.opcode_modifier
.regmem
6255 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
6256 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
6257 && !i
.tm
.opcode_modifier
.regmem
;
6266 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
6267 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
6269 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != &es
)
6271 as_bad (_("`%s' operand %u must use `%ses' segment"),
6273 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
6278 /* There's only ever one segment override allowed per instruction.
6279 This instruction possibly has a legal segment override on the
6280 second operand, so copy the segment to where non-string
6281 instructions store it, allowing common code. */
6282 i
.seg
[op
] = i
.seg
[1];
6288 process_suffix (void)
6290 /* If matched instruction specifies an explicit instruction mnemonic
6292 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
6293 i
.suffix
= WORD_MNEM_SUFFIX
;
6294 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
6295 i
.suffix
= LONG_MNEM_SUFFIX
;
6296 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
6297 i
.suffix
= QWORD_MNEM_SUFFIX
;
6298 else if (i
.reg_operands
6299 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
))
6301 /* If there's no instruction mnemonic suffix we try to invent one
6302 based on GPR operands. */
6305 /* We take i.suffix from the last register operand specified,
6306 Destination register type is more significant than source
6307 register type. crc32 in SSE4.2 prefers source register
6309 if (i
.tm
.base_opcode
== 0xf20f38f0
6310 && i
.types
[0].bitfield
.class == Reg
)
6312 if (i
.types
[0].bitfield
.byte
)
6313 i
.suffix
= BYTE_MNEM_SUFFIX
;
6314 else if (i
.types
[0].bitfield
.word
)
6315 i
.suffix
= WORD_MNEM_SUFFIX
;
6316 else if (i
.types
[0].bitfield
.dword
)
6317 i
.suffix
= LONG_MNEM_SUFFIX
;
6318 else if (i
.types
[0].bitfield
.qword
)
6319 i
.suffix
= QWORD_MNEM_SUFFIX
;
6326 if (i
.tm
.base_opcode
== 0xf20f38f0)
6328 /* We have to know the operand size for crc32. */
6329 as_bad (_("ambiguous memory operand size for `%s`"),
6334 for (op
= i
.operands
; --op
>= 0;)
6335 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
6336 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6338 if (i
.types
[op
].bitfield
.class != Reg
)
6340 if (i
.types
[op
].bitfield
.byte
)
6341 i
.suffix
= BYTE_MNEM_SUFFIX
;
6342 else if (i
.types
[op
].bitfield
.word
)
6343 i
.suffix
= WORD_MNEM_SUFFIX
;
6344 else if (i
.types
[op
].bitfield
.dword
)
6345 i
.suffix
= LONG_MNEM_SUFFIX
;
6346 else if (i
.types
[op
].bitfield
.qword
)
6347 i
.suffix
= QWORD_MNEM_SUFFIX
;
6354 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6357 && i
.tm
.opcode_modifier
.ignoresize
6358 && i
.tm
.opcode_modifier
.no_bsuf
)
6360 else if (!check_byte_reg ())
6363 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
6366 && i
.tm
.opcode_modifier
.ignoresize
6367 && i
.tm
.opcode_modifier
.no_lsuf
6368 && !i
.tm
.opcode_modifier
.todword
6369 && !i
.tm
.opcode_modifier
.toqword
)
6371 else if (!check_long_reg ())
6374 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6377 && i
.tm
.opcode_modifier
.ignoresize
6378 && i
.tm
.opcode_modifier
.no_qsuf
6379 && !i
.tm
.opcode_modifier
.todword
6380 && !i
.tm
.opcode_modifier
.toqword
)
6382 else if (!check_qword_reg ())
6385 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6388 && i
.tm
.opcode_modifier
.ignoresize
6389 && i
.tm
.opcode_modifier
.no_wsuf
)
6391 else if (!check_word_reg ())
6394 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
6395 /* Do nothing if the instruction is going to ignore the prefix. */
6400 else if (i
.tm
.opcode_modifier
.defaultsize
6402 /* exclude fldenv/frstor/fsave/fstenv */
6403 && i
.tm
.opcode_modifier
.no_ssuf
6404 /* exclude sysret */
6405 && i
.tm
.base_opcode
!= 0x0f07)
6407 i
.suffix
= stackop_size
;
6408 if (stackop_size
== LONG_MNEM_SUFFIX
)
6410 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6411 .code16gcc directive to support 16-bit mode with
6412 32-bit address. For IRET without a suffix, generate
6413 16-bit IRET (opcode 0xcf) to return from an interrupt
6415 if (i
.tm
.base_opcode
== 0xcf)
6417 i
.suffix
= WORD_MNEM_SUFFIX
;
6418 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6420 /* Warn about changed behavior for segment register push/pop. */
6421 else if ((i
.tm
.base_opcode
| 1) == 0x07)
6422 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6426 else if (intel_syntax
6428 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
6429 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
6430 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
6431 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
6432 && i
.tm
.extension_opcode
<= 3)))
6437 if (!i
.tm
.opcode_modifier
.no_qsuf
)
6439 i
.suffix
= QWORD_MNEM_SUFFIX
;
6444 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6445 i
.suffix
= LONG_MNEM_SUFFIX
;
6448 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6449 i
.suffix
= WORD_MNEM_SUFFIX
;
6458 if (i
.tm
.opcode_modifier
.w
)
6460 as_bad (_("no instruction mnemonic suffix given and "
6461 "no register operands; can't size instruction"));
6467 unsigned int suffixes
;
6469 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
6470 if (!i
.tm
.opcode_modifier
.no_wsuf
)
6472 if (!i
.tm
.opcode_modifier
.no_lsuf
)
6474 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
6476 if (!i
.tm
.opcode_modifier
.no_ssuf
)
6478 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
6481 /* There are more than suffix matches. */
6482 if (i
.tm
.opcode_modifier
.w
6483 || ((suffixes
& (suffixes
- 1))
6484 && !i
.tm
.opcode_modifier
.defaultsize
6485 && !i
.tm
.opcode_modifier
.ignoresize
))
6487 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
6493 /* Change the opcode based on the operand size given by i.suffix. */
6496 /* Size floating point instruction. */
6497 case LONG_MNEM_SUFFIX
:
6498 if (i
.tm
.opcode_modifier
.floatmf
)
6500 i
.tm
.base_opcode
^= 4;
6504 case WORD_MNEM_SUFFIX
:
6505 case QWORD_MNEM_SUFFIX
:
6506 /* It's not a byte, select word/dword operation. */
6507 if (i
.tm
.opcode_modifier
.w
)
6509 if (i
.tm
.opcode_modifier
.shortform
)
6510 i
.tm
.base_opcode
|= 8;
6512 i
.tm
.base_opcode
|= 1;
6515 case SHORT_MNEM_SUFFIX
:
6516 /* Now select between word & dword operations via the operand
6517 size prefix, except for instructions that will ignore this
6519 if (i
.reg_operands
> 0
6520 && i
.types
[0].bitfield
.class == Reg
6521 && i
.tm
.opcode_modifier
.addrprefixopreg
6522 && (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6523 || i
.operands
== 1))
6525 /* The address size override prefix changes the size of the
6527 if ((flag_code
== CODE_32BIT
6528 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
6529 || (flag_code
!= CODE_32BIT
6530 && i
.op
[0].regs
->reg_type
.bitfield
.dword
))
6531 if (!add_prefix (ADDR_PREFIX_OPCODE
))
6534 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
6535 && !i
.tm
.opcode_modifier
.ignoresize
6536 && !i
.tm
.opcode_modifier
.floatmf
6537 && !is_any_vex_encoding (&i
.tm
)
6538 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
6539 || (flag_code
== CODE_64BIT
6540 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
6542 unsigned int prefix
= DATA_PREFIX_OPCODE
;
6544 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
6545 prefix
= ADDR_PREFIX_OPCODE
;
6547 if (!add_prefix (prefix
))
6551 /* Set mode64 for an operand. */
6552 if (i
.suffix
== QWORD_MNEM_SUFFIX
6553 && flag_code
== CODE_64BIT
6554 && !i
.tm
.opcode_modifier
.norex64
6555 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6557 && ! (i
.operands
== 2
6558 && i
.tm
.base_opcode
== 0x90
6559 && i
.tm
.extension_opcode
== None
6560 && i
.types
[0].bitfield
.instance
== Accum
6561 && i
.types
[0].bitfield
.qword
6562 && i
.types
[1].bitfield
.instance
== Accum
6563 && i
.types
[1].bitfield
.qword
))
6569 if (i
.reg_operands
!= 0
6571 && i
.tm
.opcode_modifier
.addrprefixopreg
6572 && i
.tm
.operand_types
[0].bitfield
.instance
!= Accum
)
6574 /* Check invalid register operand when the address size override
6575 prefix changes the size of register operands. */
6577 enum { need_word
, need_dword
, need_qword
} need
;
6579 if (flag_code
== CODE_32BIT
)
6580 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
6583 if (i
.prefix
[ADDR_PREFIX
])
6586 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
6589 for (op
= 0; op
< i
.operands
; op
++)
6590 if (i
.types
[op
].bitfield
.class == Reg
6591 && ((need
== need_word
6592 && !i
.op
[op
].regs
->reg_type
.bitfield
.word
)
6593 || (need
== need_dword
6594 && !i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
6595 || (need
== need_qword
6596 && !i
.op
[op
].regs
->reg_type
.bitfield
.qword
)))
6598 as_bad (_("invalid register operand size for `%s'"),
6608 check_byte_reg (void)
6612 for (op
= i
.operands
; --op
>= 0;)
6614 /* Skip non-register operands. */
6615 if (i
.types
[op
].bitfield
.class != Reg
)
6618 /* If this is an eight bit register, it's OK. If it's the 16 or
6619 32 bit version of an eight bit register, we will just use the
6620 low portion, and that's OK too. */
6621 if (i
.types
[op
].bitfield
.byte
)
6624 /* I/O port address operands are OK too. */
6625 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
6626 && i
.tm
.operand_types
[op
].bitfield
.word
)
6629 /* crc32 doesn't generate this warning. */
6630 if (i
.tm
.base_opcode
== 0xf20f38f0)
6633 if ((i
.types
[op
].bitfield
.word
6634 || i
.types
[op
].bitfield
.dword
6635 || i
.types
[op
].bitfield
.qword
)
6636 && i
.op
[op
].regs
->reg_num
< 4
6637 /* Prohibit these changes in 64bit mode, since the lowering
6638 would be more complicated. */
6639 && flag_code
!= CODE_64BIT
)
6641 #if REGISTER_WARNINGS
6642 if (!quiet_warnings
)
6643 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6645 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.word
6646 ? REGNAM_AL
- REGNAM_AX
6647 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
6649 i
.op
[op
].regs
->reg_name
,
6654 /* Any other register is bad. */
6655 if (i
.types
[op
].bitfield
.class == Reg
6656 || i
.types
[op
].bitfield
.class == RegMMX
6657 || i
.types
[op
].bitfield
.class == RegSIMD
6658 || i
.types
[op
].bitfield
.class == SReg
6659 || i
.types
[op
].bitfield
.class == RegCR
6660 || i
.types
[op
].bitfield
.class == RegDR
6661 || i
.types
[op
].bitfield
.class == RegTR
)
6663 as_bad (_("`%s%s' not allowed with `%s%c'"),
6665 i
.op
[op
].regs
->reg_name
,
6675 check_long_reg (void)
6679 for (op
= i
.operands
; --op
>= 0;)
6680 /* Skip non-register operands. */
6681 if (i
.types
[op
].bitfield
.class != Reg
)
6683 /* Reject eight bit registers, except where the template requires
6684 them. (eg. movzb) */
6685 else if (i
.types
[op
].bitfield
.byte
6686 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6687 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6688 && (i
.tm
.operand_types
[op
].bitfield
.word
6689 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6691 as_bad (_("`%s%s' not allowed with `%s%c'"),
6693 i
.op
[op
].regs
->reg_name
,
6698 /* Warn if the e prefix on a general reg is missing. */
6699 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6700 && i
.types
[op
].bitfield
.word
6701 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6702 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6703 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6705 /* Prohibit these changes in the 64bit mode, since the
6706 lowering is more complicated. */
6707 if (flag_code
== CODE_64BIT
)
6709 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6710 register_prefix
, i
.op
[op
].regs
->reg_name
,
6714 #if REGISTER_WARNINGS
6715 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6717 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
6718 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6721 /* Warn if the r prefix on a general reg is present. */
6722 else if (i
.types
[op
].bitfield
.qword
6723 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6724 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6725 && i
.tm
.operand_types
[op
].bitfield
.dword
)
6728 && i
.tm
.opcode_modifier
.toqword
6729 && i
.types
[0].bitfield
.class != RegSIMD
)
6731 /* Convert to QWORD. We want REX byte. */
6732 i
.suffix
= QWORD_MNEM_SUFFIX
;
6736 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6737 register_prefix
, i
.op
[op
].regs
->reg_name
,
6746 check_qword_reg (void)
6750 for (op
= i
.operands
; --op
>= 0; )
6751 /* Skip non-register operands. */
6752 if (i
.types
[op
].bitfield
.class != Reg
)
6754 /* Reject eight bit registers, except where the template requires
6755 them. (eg. movzb) */
6756 else if (i
.types
[op
].bitfield
.byte
6757 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6758 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6759 && (i
.tm
.operand_types
[op
].bitfield
.word
6760 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6762 as_bad (_("`%s%s' not allowed with `%s%c'"),
6764 i
.op
[op
].regs
->reg_name
,
6769 /* Warn if the r prefix on a general reg is missing. */
6770 else if ((i
.types
[op
].bitfield
.word
6771 || i
.types
[op
].bitfield
.dword
)
6772 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6773 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6774 && i
.tm
.operand_types
[op
].bitfield
.qword
)
6776 /* Prohibit these changes in the 64bit mode, since the
6777 lowering is more complicated. */
6779 && i
.tm
.opcode_modifier
.todword
6780 && i
.types
[0].bitfield
.class != RegSIMD
)
6782 /* Convert to DWORD. We don't want REX byte. */
6783 i
.suffix
= LONG_MNEM_SUFFIX
;
6787 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6788 register_prefix
, i
.op
[op
].regs
->reg_name
,
6797 check_word_reg (void)
6800 for (op
= i
.operands
; --op
>= 0;)
6801 /* Skip non-register operands. */
6802 if (i
.types
[op
].bitfield
.class != Reg
)
6804 /* Reject eight bit registers, except where the template requires
6805 them. (eg. movzb) */
6806 else if (i
.types
[op
].bitfield
.byte
6807 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6808 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6809 && (i
.tm
.operand_types
[op
].bitfield
.word
6810 || i
.tm
.operand_types
[op
].bitfield
.dword
))
6812 as_bad (_("`%s%s' not allowed with `%s%c'"),
6814 i
.op
[op
].regs
->reg_name
,
6819 /* Warn if the e or r prefix on a general reg is present. */
6820 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
6821 && (i
.types
[op
].bitfield
.dword
6822 || i
.types
[op
].bitfield
.qword
)
6823 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
6824 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
6825 && i
.tm
.operand_types
[op
].bitfield
.word
)
6827 /* Prohibit these changes in the 64bit mode, since the
6828 lowering is more complicated. */
6829 if (flag_code
== CODE_64BIT
)
6831 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6832 register_prefix
, i
.op
[op
].regs
->reg_name
,
6836 #if REGISTER_WARNINGS
6837 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6839 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
6840 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
6847 update_imm (unsigned int j
)
6849 i386_operand_type overlap
= i
.types
[j
];
6850 if ((overlap
.bitfield
.imm8
6851 || overlap
.bitfield
.imm8s
6852 || overlap
.bitfield
.imm16
6853 || overlap
.bitfield
.imm32
6854 || overlap
.bitfield
.imm32s
6855 || overlap
.bitfield
.imm64
)
6856 && !operand_type_equal (&overlap
, &imm8
)
6857 && !operand_type_equal (&overlap
, &imm8s
)
6858 && !operand_type_equal (&overlap
, &imm16
)
6859 && !operand_type_equal (&overlap
, &imm32
)
6860 && !operand_type_equal (&overlap
, &imm32s
)
6861 && !operand_type_equal (&overlap
, &imm64
))
6865 i386_operand_type temp
;
6867 operand_type_set (&temp
, 0);
6868 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
6870 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
6871 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
6873 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
6874 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
6875 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
6877 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
6878 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
6881 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
6884 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
6885 || operand_type_equal (&overlap
, &imm16_32
)
6886 || operand_type_equal (&overlap
, &imm16_32s
))
6888 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6893 if (!operand_type_equal (&overlap
, &imm8
)
6894 && !operand_type_equal (&overlap
, &imm8s
)
6895 && !operand_type_equal (&overlap
, &imm16
)
6896 && !operand_type_equal (&overlap
, &imm32
)
6897 && !operand_type_equal (&overlap
, &imm32s
)
6898 && !operand_type_equal (&overlap
, &imm64
))
6900 as_bad (_("no instruction mnemonic suffix given; "
6901 "can't determine immediate size"));
6905 i
.types
[j
] = overlap
;
6915 /* Update the first 2 immediate operands. */
6916 n
= i
.operands
> 2 ? 2 : i
.operands
;
6919 for (j
= 0; j
< n
; j
++)
6920 if (update_imm (j
) == 0)
6923 /* The 3rd operand can't be immediate operand. */
6924 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
6931 process_operands (void)
6933 /* Default segment register this instruction will use for memory
6934 accesses. 0 means unknown. This is only for optimizing out
6935 unnecessary segment overrides. */
6936 const seg_entry
*default_seg
= 0;
6938 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
6940 unsigned int dupl
= i
.operands
;
6941 unsigned int dest
= dupl
- 1;
6944 /* The destination must be an xmm register. */
6945 gas_assert (i
.reg_operands
6946 && MAX_OPERANDS
> dupl
6947 && operand_type_equal (&i
.types
[dest
], ®xmm
));
6949 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
6950 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
6952 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
6954 /* Keep xmm0 for instructions with VEX prefix and 3
6956 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
6957 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
6962 /* We remove the first xmm0 and keep the number of
6963 operands unchanged, which in fact duplicates the
6965 for (j
= 1; j
< i
.operands
; j
++)
6967 i
.op
[j
- 1] = i
.op
[j
];
6968 i
.types
[j
- 1] = i
.types
[j
];
6969 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
6970 i
.flags
[j
- 1] = i
.flags
[j
];
6974 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
6976 gas_assert ((MAX_OPERANDS
- 1) > dupl
6977 && (i
.tm
.opcode_modifier
.vexsources
6980 /* Add the implicit xmm0 for instructions with VEX prefix
6982 for (j
= i
.operands
; j
> 0; j
--)
6984 i
.op
[j
] = i
.op
[j
- 1];
6985 i
.types
[j
] = i
.types
[j
- 1];
6986 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
6987 i
.flags
[j
] = i
.flags
[j
- 1];
6990 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
6991 i
.types
[0] = regxmm
;
6992 i
.tm
.operand_types
[0] = regxmm
;
6995 i
.reg_operands
+= 2;
7000 i
.op
[dupl
] = i
.op
[dest
];
7001 i
.types
[dupl
] = i
.types
[dest
];
7002 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7003 i
.flags
[dupl
] = i
.flags
[dest
];
7012 i
.op
[dupl
] = i
.op
[dest
];
7013 i
.types
[dupl
] = i
.types
[dest
];
7014 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
7015 i
.flags
[dupl
] = i
.flags
[dest
];
7018 if (i
.tm
.opcode_modifier
.immext
)
7021 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7022 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
7026 for (j
= 1; j
< i
.operands
; j
++)
7028 i
.op
[j
- 1] = i
.op
[j
];
7029 i
.types
[j
- 1] = i
.types
[j
];
7031 /* We need to adjust fields in i.tm since they are used by
7032 build_modrm_byte. */
7033 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
7035 i
.flags
[j
- 1] = i
.flags
[j
];
7042 else if (i
.tm
.opcode_modifier
.implicitquadgroup
)
7044 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
7046 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7047 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
7048 regnum
= register_number (i
.op
[1].regs
);
7049 first_reg_in_group
= regnum
& ~3;
7050 last_reg_in_group
= first_reg_in_group
+ 3;
7051 if (regnum
!= first_reg_in_group
)
7052 as_warn (_("source register `%s%s' implicitly denotes"
7053 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7054 register_prefix
, i
.op
[1].regs
->reg_name
,
7055 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
7056 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
7059 else if (i
.tm
.opcode_modifier
.regkludge
)
7061 /* The imul $imm, %reg instruction is converted into
7062 imul $imm, %reg, %reg, and the clr %reg instruction
7063 is converted into xor %reg, %reg. */
7065 unsigned int first_reg_op
;
7067 if (operand_type_check (i
.types
[0], reg
))
7071 /* Pretend we saw the extra register operand. */
7072 gas_assert (i
.reg_operands
== 1
7073 && i
.op
[first_reg_op
+ 1].regs
== 0);
7074 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
7075 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
7080 if (i
.tm
.opcode_modifier
.modrm
)
7082 /* The opcode is completed (modulo i.tm.extension_opcode which
7083 must be put into the modrm byte). Now, we make the modrm and
7084 index base bytes based on all the info we've collected. */
7086 default_seg
= build_modrm_byte ();
7088 else if (i
.types
[0].bitfield
.class == SReg
)
7090 if (flag_code
!= CODE_64BIT
7091 ? i
.tm
.base_opcode
== POP_SEG_SHORT
7092 && i
.op
[0].regs
->reg_num
== 1
7093 : (i
.tm
.base_opcode
| 1) == POP_SEG386_SHORT
7094 && i
.op
[0].regs
->reg_num
< 4)
7096 as_bad (_("you can't `%s %s%s'"),
7097 i
.tm
.name
, register_prefix
, i
.op
[0].regs
->reg_name
);
7100 if ( i
.op
[0].regs
->reg_num
> 3 && i
.tm
.opcode_length
== 1 )
7102 i
.tm
.base_opcode
^= POP_SEG_SHORT
^ POP_SEG386_SHORT
;
7103 i
.tm
.opcode_length
= 2;
7105 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
7107 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
7111 else if (i
.tm
.opcode_modifier
.isstring
)
7113 /* For the string instructions that allow a segment override
7114 on one of their operands, the default segment is ds. */
7117 else if (i
.tm
.opcode_modifier
.shortform
)
7119 /* The register or float register operand is in operand
7121 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.class != Reg
;
7123 /* Register goes in low 3 bits of opcode. */
7124 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
7125 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7127 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
7129 /* Warn about some common errors, but press on regardless.
7130 The first case can be generated by gcc (<= 2.8.1). */
7131 if (i
.operands
== 2)
7133 /* Reversed arguments on faddp, fsubp, etc. */
7134 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
7135 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
7136 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
7140 /* Extraneous `l' suffix on fp insn. */
7141 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
7142 register_prefix
, i
.op
[0].regs
->reg_name
);
7147 if (i
.tm
.base_opcode
== 0x8d /* lea */
7150 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
7152 /* If a segment was explicitly specified, and the specified segment
7153 is not the default, use an opcode prefix to select it. If we
7154 never figured out what the default segment is, then default_seg
7155 will be zero at this point, and the specified segment prefix will
7157 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
7159 if (!add_prefix (i
.seg
[0]->seg_prefix
))
7165 static const seg_entry
*
7166 build_modrm_byte (void)
7168 const seg_entry
*default_seg
= 0;
7169 unsigned int source
, dest
;
7172 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
7175 unsigned int nds
, reg_slot
;
7178 dest
= i
.operands
- 1;
7181 /* There are 2 kinds of instructions:
7182 1. 5 operands: 4 register operands or 3 register operands
7183 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7184 VexW0 or VexW1. The destination must be either XMM, YMM or
7186 2. 4 operands: 4 register operands or 3 register operands
7187 plus 1 memory operand, with VexXDS. */
7188 gas_assert ((i
.reg_operands
== 4
7189 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
7190 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7191 && i
.tm
.opcode_modifier
.vexw
7192 && i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
7194 /* If VexW1 is set, the first non-immediate operand is the source and
7195 the second non-immediate one is encoded in the immediate operand. */
7196 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
7198 source
= i
.imm_operands
;
7199 reg_slot
= i
.imm_operands
+ 1;
7203 source
= i
.imm_operands
+ 1;
7204 reg_slot
= i
.imm_operands
;
7207 if (i
.imm_operands
== 0)
7209 /* When there is no immediate operand, generate an 8bit
7210 immediate operand to encode the first operand. */
7211 exp
= &im_expressions
[i
.imm_operands
++];
7212 i
.op
[i
.operands
].imms
= exp
;
7213 i
.types
[i
.operands
] = imm8
;
7216 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7217 exp
->X_op
= O_constant
;
7218 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
7219 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7223 gas_assert (i
.imm_operands
== 1);
7224 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
7225 gas_assert (!i
.tm
.opcode_modifier
.immext
);
7227 /* Turn on Imm8 again so that output_imm will generate it. */
7228 i
.types
[0].bitfield
.imm8
= 1;
7230 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
7231 i
.op
[0].imms
->X_add_number
7232 |= register_number (i
.op
[reg_slot
].regs
) << 4;
7233 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
7236 gas_assert (i
.tm
.operand_types
[nds
].bitfield
.class == RegSIMD
);
7237 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
7242 /* i.reg_operands MUST be the number of real register operands;
7243 implicit registers do not count. If there are 3 register
7244 operands, it must be a instruction with VexNDS. For a
7245 instruction with VexNDD, the destination register is encoded
7246 in VEX prefix. If there are 4 register operands, it must be
7247 a instruction with VEX prefix and 3 sources. */
7248 if (i
.mem_operands
== 0
7249 && ((i
.reg_operands
== 2
7250 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
7251 || (i
.reg_operands
== 3
7252 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7253 || (i
.reg_operands
== 4 && vex_3_sources
)))
7261 /* When there are 3 operands, one of them may be immediate,
7262 which may be the first or the last operand. Otherwise,
7263 the first operand must be shift count register (cl) or it
7264 is an instruction with VexNDS. */
7265 gas_assert (i
.imm_operands
== 1
7266 || (i
.imm_operands
== 0
7267 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7268 || (i
.types
[0].bitfield
.instance
== RegC
7269 && i
.types
[0].bitfield
.byte
))));
7270 if (operand_type_check (i
.types
[0], imm
)
7271 || (i
.types
[0].bitfield
.instance
== RegC
7272 && i
.types
[0].bitfield
.byte
))
7278 /* When there are 4 operands, the first two must be 8bit
7279 immediate operands. The source operand will be the 3rd
7282 For instructions with VexNDS, if the first operand
7283 an imm8, the source operand is the 2nd one. If the last
7284 operand is imm8, the source operand is the first one. */
7285 gas_assert ((i
.imm_operands
== 2
7286 && i
.types
[0].bitfield
.imm8
7287 && i
.types
[1].bitfield
.imm8
)
7288 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
7289 && i
.imm_operands
== 1
7290 && (i
.types
[0].bitfield
.imm8
7291 || i
.types
[i
.operands
- 1].bitfield
.imm8
7293 if (i
.imm_operands
== 2)
7297 if (i
.types
[0].bitfield
.imm8
)
7304 if (is_evex_encoding (&i
.tm
))
7306 /* For EVEX instructions, when there are 5 operands, the
7307 first one must be immediate operand. If the second one
7308 is immediate operand, the source operand is the 3th
7309 one. If the last one is immediate operand, the source
7310 operand is the 2nd one. */
7311 gas_assert (i
.imm_operands
== 2
7312 && i
.tm
.opcode_modifier
.sae
7313 && operand_type_check (i
.types
[0], imm
));
7314 if (operand_type_check (i
.types
[1], imm
))
7316 else if (operand_type_check (i
.types
[4], imm
))
7330 /* RC/SAE operand could be between DEST and SRC. That happens
7331 when one operand is GPR and the other one is XMM/YMM/ZMM
7333 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
7336 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7338 /* For instructions with VexNDS, the register-only source
7339 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7340 register. It is encoded in VEX prefix. */
7342 i386_operand_type op
;
7345 /* Check register-only source operand when two source
7346 operands are swapped. */
7347 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
7348 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
7356 op
= i
.tm
.operand_types
[vvvv
];
7357 if ((dest
+ 1) >= i
.operands
7358 || ((op
.bitfield
.class != Reg
7359 || (!op
.bitfield
.dword
&& !op
.bitfield
.qword
))
7360 && op
.bitfield
.class != RegSIMD
7361 && !operand_type_equal (&op
, ®mask
)))
7363 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
7369 /* One of the register operands will be encoded in the i.rm.reg
7370 field, the other in the combined i.rm.mode and i.rm.regmem
7371 fields. If no form of this instruction supports a memory
7372 destination operand, then we assume the source operand may
7373 sometimes be a memory operand and so we need to store the
7374 destination in the i.rm.reg field. */
7375 if (!i
.tm
.opcode_modifier
.regmem
7376 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
7378 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
7379 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
7380 if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegMMX
7381 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegMMX
)
7382 i
.has_regmmx
= TRUE
;
7383 else if (i
.op
[dest
].regs
->reg_type
.bitfield
.class == RegSIMD
7384 || i
.op
[source
].regs
->reg_type
.bitfield
.class == RegSIMD
)
7386 if (i
.types
[dest
].bitfield
.zmmword
7387 || i
.types
[source
].bitfield
.zmmword
)
7388 i
.has_regzmm
= TRUE
;
7389 else if (i
.types
[dest
].bitfield
.ymmword
7390 || i
.types
[source
].bitfield
.ymmword
)
7391 i
.has_regymm
= TRUE
;
7393 i
.has_regxmm
= TRUE
;
7395 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7397 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7399 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7401 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7406 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
7407 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
7408 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
7410 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
7412 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
7414 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
7417 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
7419 if (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class != RegCR
)
7422 add_prefix (LOCK_PREFIX_OPCODE
);
7426 { /* If it's not 2 reg operands... */
7431 unsigned int fake_zero_displacement
= 0;
7434 for (op
= 0; op
< i
.operands
; op
++)
7435 if (i
.flags
[op
] & Operand_Mem
)
7437 gas_assert (op
< i
.operands
);
7439 if (i
.tm
.opcode_modifier
.vecsib
)
7441 if (i
.index_reg
->reg_num
== RegIZ
)
7444 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7447 i
.sib
.base
= NO_BASE_REGISTER
;
7448 i
.sib
.scale
= i
.log2_scale_factor
;
7449 i
.types
[op
].bitfield
.disp8
= 0;
7450 i
.types
[op
].bitfield
.disp16
= 0;
7451 i
.types
[op
].bitfield
.disp64
= 0;
7452 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7454 /* Must be 32 bit */
7455 i
.types
[op
].bitfield
.disp32
= 1;
7456 i
.types
[op
].bitfield
.disp32s
= 0;
7460 i
.types
[op
].bitfield
.disp32
= 0;
7461 i
.types
[op
].bitfield
.disp32s
= 1;
7464 i
.sib
.index
= i
.index_reg
->reg_num
;
7465 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7467 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
7473 if (i
.base_reg
== 0)
7476 if (!i
.disp_operands
)
7477 fake_zero_displacement
= 1;
7478 if (i
.index_reg
== 0)
7480 i386_operand_type newdisp
;
7482 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7483 /* Operand is just <disp> */
7484 if (flag_code
== CODE_64BIT
)
7486 /* 64bit mode overwrites the 32bit absolute
7487 addressing by RIP relative addressing and
7488 absolute addressing is encoded by one of the
7489 redundant SIB forms. */
7490 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7491 i
.sib
.base
= NO_BASE_REGISTER
;
7492 i
.sib
.index
= NO_INDEX_REGISTER
;
7493 newdisp
= (!i
.prefix
[ADDR_PREFIX
] ? disp32s
: disp32
);
7495 else if ((flag_code
== CODE_16BIT
)
7496 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7498 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
7503 i
.rm
.regmem
= NO_BASE_REGISTER
;
7506 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
7507 i
.types
[op
] = operand_type_or (i
.types
[op
], newdisp
);
7509 else if (!i
.tm
.opcode_modifier
.vecsib
)
7511 /* !i.base_reg && i.index_reg */
7512 if (i
.index_reg
->reg_num
== RegIZ
)
7513 i
.sib
.index
= NO_INDEX_REGISTER
;
7515 i
.sib
.index
= i
.index_reg
->reg_num
;
7516 i
.sib
.base
= NO_BASE_REGISTER
;
7517 i
.sib
.scale
= i
.log2_scale_factor
;
7518 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7519 i
.types
[op
].bitfield
.disp8
= 0;
7520 i
.types
[op
].bitfield
.disp16
= 0;
7521 i
.types
[op
].bitfield
.disp64
= 0;
7522 if (flag_code
!= CODE_64BIT
|| i
.prefix
[ADDR_PREFIX
])
7524 /* Must be 32 bit */
7525 i
.types
[op
].bitfield
.disp32
= 1;
7526 i
.types
[op
].bitfield
.disp32s
= 0;
7530 i
.types
[op
].bitfield
.disp32
= 0;
7531 i
.types
[op
].bitfield
.disp32s
= 1;
7533 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7537 /* RIP addressing for 64bit mode. */
7538 else if (i
.base_reg
->reg_num
== RegIP
)
7540 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7541 i
.rm
.regmem
= NO_BASE_REGISTER
;
7542 i
.types
[op
].bitfield
.disp8
= 0;
7543 i
.types
[op
].bitfield
.disp16
= 0;
7544 i
.types
[op
].bitfield
.disp32
= 0;
7545 i
.types
[op
].bitfield
.disp32s
= 1;
7546 i
.types
[op
].bitfield
.disp64
= 0;
7547 i
.flags
[op
] |= Operand_PCrel
;
7548 if (! i
.disp_operands
)
7549 fake_zero_displacement
= 1;
7551 else if (i
.base_reg
->reg_type
.bitfield
.word
)
7553 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7554 switch (i
.base_reg
->reg_num
)
7557 if (i
.index_reg
== 0)
7559 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7560 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
7564 if (i
.index_reg
== 0)
7567 if (operand_type_check (i
.types
[op
], disp
) == 0)
7569 /* fake (%bp) into 0(%bp) */
7570 i
.types
[op
].bitfield
.disp8
= 1;
7571 fake_zero_displacement
= 1;
7574 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7575 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
7577 default: /* (%si) -> 4 or (%di) -> 5 */
7578 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
7580 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7582 else /* i.base_reg and 32/64 bit mode */
7584 if (flag_code
== CODE_64BIT
7585 && operand_type_check (i
.types
[op
], disp
))
7587 i
.types
[op
].bitfield
.disp16
= 0;
7588 i
.types
[op
].bitfield
.disp64
= 0;
7589 if (i
.prefix
[ADDR_PREFIX
] == 0)
7591 i
.types
[op
].bitfield
.disp32
= 0;
7592 i
.types
[op
].bitfield
.disp32s
= 1;
7596 i
.types
[op
].bitfield
.disp32
= 1;
7597 i
.types
[op
].bitfield
.disp32s
= 0;
7601 if (!i
.tm
.opcode_modifier
.vecsib
)
7602 i
.rm
.regmem
= i
.base_reg
->reg_num
;
7603 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
7605 i
.sib
.base
= i
.base_reg
->reg_num
;
7606 /* x86-64 ignores REX prefix bit here to avoid decoder
7608 if (!(i
.base_reg
->reg_flags
& RegRex
)
7609 && (i
.base_reg
->reg_num
== EBP_REG_NUM
7610 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
7612 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
7614 fake_zero_displacement
= 1;
7615 i
.types
[op
].bitfield
.disp8
= 1;
7617 i
.sib
.scale
= i
.log2_scale_factor
;
7618 if (i
.index_reg
== 0)
7620 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
7621 /* <disp>(%esp) becomes two byte modrm with no index
7622 register. We've already stored the code for esp
7623 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7624 Any base register besides %esp will not use the
7625 extra modrm byte. */
7626 i
.sib
.index
= NO_INDEX_REGISTER
;
7628 else if (!i
.tm
.opcode_modifier
.vecsib
)
7630 if (i
.index_reg
->reg_num
== RegIZ
)
7631 i
.sib
.index
= NO_INDEX_REGISTER
;
7633 i
.sib
.index
= i
.index_reg
->reg_num
;
7634 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
7635 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
7640 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
7641 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
7645 if (!fake_zero_displacement
7649 fake_zero_displacement
= 1;
7650 if (i
.disp_encoding
== disp_encoding_8bit
)
7651 i
.types
[op
].bitfield
.disp8
= 1;
7653 i
.types
[op
].bitfield
.disp32
= 1;
7655 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
7659 if (fake_zero_displacement
)
7661 /* Fakes a zero displacement assuming that i.types[op]
7662 holds the correct displacement size. */
7665 gas_assert (i
.op
[op
].disps
== 0);
7666 exp
= &disp_expressions
[i
.disp_operands
++];
7667 i
.op
[op
].disps
= exp
;
7668 exp
->X_op
= O_constant
;
7669 exp
->X_add_number
= 0;
7670 exp
->X_add_symbol
= (symbolS
*) 0;
7671 exp
->X_op_symbol
= (symbolS
*) 0;
7679 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
7681 if (operand_type_check (i
.types
[0], imm
))
7682 i
.vex
.register_specifier
= NULL
;
7685 /* VEX.vvvv encodes one of the sources when the first
7686 operand is not an immediate. */
7687 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7688 i
.vex
.register_specifier
= i
.op
[0].regs
;
7690 i
.vex
.register_specifier
= i
.op
[1].regs
;
7693 /* Destination is a XMM register encoded in the ModRM.reg
7695 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
7696 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
7699 /* ModRM.rm and VEX.B encodes the other source. */
7700 if (!i
.mem_operands
)
7704 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
7705 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7707 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
7709 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7713 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
7715 i
.vex
.register_specifier
= i
.op
[2].regs
;
7716 if (!i
.mem_operands
)
7719 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
7720 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
7724 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7725 (if any) based on i.tm.extension_opcode. Again, we must be
7726 careful to make sure that segment/control/debug/test/MMX
7727 registers are coded into the i.rm.reg field. */
7728 else if (i
.reg_operands
)
7731 unsigned int vex_reg
= ~0;
7733 for (op
= 0; op
< i
.operands
; op
++)
7735 if (i
.types
[op
].bitfield
.class == Reg
7736 || i
.types
[op
].bitfield
.class == RegBND
7737 || i
.types
[op
].bitfield
.class == RegMask
7738 || i
.types
[op
].bitfield
.class == SReg
7739 || i
.types
[op
].bitfield
.class == RegCR
7740 || i
.types
[op
].bitfield
.class == RegDR
7741 || i
.types
[op
].bitfield
.class == RegTR
)
7743 if (i
.types
[op
].bitfield
.class == RegSIMD
)
7745 if (i
.types
[op
].bitfield
.zmmword
)
7746 i
.has_regzmm
= TRUE
;
7747 else if (i
.types
[op
].bitfield
.ymmword
)
7748 i
.has_regymm
= TRUE
;
7750 i
.has_regxmm
= TRUE
;
7753 if (i
.types
[op
].bitfield
.class == RegMMX
)
7755 i
.has_regmmx
= TRUE
;
7762 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
7764 /* For instructions with VexNDS, the register-only
7765 source operand is encoded in VEX prefix. */
7766 gas_assert (mem
!= (unsigned int) ~0);
7771 gas_assert (op
< i
.operands
);
7775 /* Check register-only source operand when two source
7776 operands are swapped. */
7777 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
7778 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
7782 gas_assert (mem
== (vex_reg
+ 1)
7783 && op
< i
.operands
);
7788 gas_assert (vex_reg
< i
.operands
);
7792 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
7794 /* For instructions with VexNDD, the register destination
7795 is encoded in VEX prefix. */
7796 if (i
.mem_operands
== 0)
7798 /* There is no memory operand. */
7799 gas_assert ((op
+ 2) == i
.operands
);
7804 /* There are only 2 non-immediate operands. */
7805 gas_assert (op
< i
.imm_operands
+ 2
7806 && i
.operands
== i
.imm_operands
+ 2);
7807 vex_reg
= i
.imm_operands
+ 1;
7811 gas_assert (op
< i
.operands
);
7813 if (vex_reg
!= (unsigned int) ~0)
7815 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
7817 if ((type
->bitfield
.class != Reg
7818 || (!type
->bitfield
.dword
&& !type
->bitfield
.qword
))
7819 && type
->bitfield
.class != RegSIMD
7820 && !operand_type_equal (type
, ®mask
))
7823 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
7826 /* Don't set OP operand twice. */
7829 /* If there is an extension opcode to put here, the
7830 register number must be put into the regmem field. */
7831 if (i
.tm
.extension_opcode
!= None
)
7833 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
7834 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7836 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7841 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
7842 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
7844 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
7849 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7850 must set it to 3 to indicate this is a register operand
7851 in the regmem field. */
7852 if (!i
.mem_operands
)
7856 /* Fill in i.rm.reg field with extension opcode (if any). */
7857 if (i
.tm
.extension_opcode
!= None
)
7858 i
.rm
.reg
= i
.tm
.extension_opcode
;
7864 flip_code16 (unsigned int code16
)
7866 gas_assert (i
.tm
.operands
== 1);
7868 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
7869 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
7870 || i
.tm
.operand_types
[0].bitfield
.disp32s
7871 : i
.tm
.operand_types
[0].bitfield
.disp16
)
7876 output_branch (void)
7882 relax_substateT subtype
;
7886 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
7887 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
7890 if (i
.prefix
[DATA_PREFIX
] != 0)
7894 code16
^= flip_code16(code16
);
7896 /* Pentium4 branch hints. */
7897 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
7898 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
7903 if (i
.prefix
[REX_PREFIX
] != 0)
7909 /* BND prefixed jump. */
7910 if (i
.prefix
[BND_PREFIX
] != 0)
7916 if (i
.prefixes
!= 0)
7917 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
7919 /* It's always a symbol; End frag & setup for relax.
7920 Make sure there is enough room in this frag for the largest
7921 instruction we may generate in md_convert_frag. This is 2
7922 bytes for the opcode and room for the prefix and largest
7924 frag_grow (prefix
+ 2 + 4);
7925 /* Prefix and 1 opcode byte go in fr_fix. */
7926 p
= frag_more (prefix
+ 1);
7927 if (i
.prefix
[DATA_PREFIX
] != 0)
7928 *p
++ = DATA_PREFIX_OPCODE
;
7929 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
7930 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
7931 *p
++ = i
.prefix
[SEG_PREFIX
];
7932 if (i
.prefix
[BND_PREFIX
] != 0)
7933 *p
++ = BND_PREFIX_OPCODE
;
7934 if (i
.prefix
[REX_PREFIX
] != 0)
7935 *p
++ = i
.prefix
[REX_PREFIX
];
7936 *p
= i
.tm
.base_opcode
;
7938 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
7939 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
7940 else if (cpu_arch_flags
.bitfield
.cpui386
)
7941 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
7943 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
7946 sym
= i
.op
[0].disps
->X_add_symbol
;
7947 off
= i
.op
[0].disps
->X_add_number
;
7949 if (i
.op
[0].disps
->X_op
!= O_constant
7950 && i
.op
[0].disps
->X_op
!= O_symbol
)
7952 /* Handle complex expressions. */
7953 sym
= make_expr_symbol (i
.op
[0].disps
);
7957 /* 1 possible extra opcode + 4 byte displacement go in var part.
7958 Pass reloc in fr_var. */
7959 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
7962 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7963 /* Return TRUE iff PLT32 relocation should be used for branching to
7967 need_plt32_p (symbolS
*s
)
7969 /* PLT32 relocation is ELF only. */
7974 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7975 krtld support it. */
7979 /* Since there is no need to prepare for PLT branch on x86-64, we
7980 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7981 be used as a marker for 32-bit PC-relative branches. */
7985 /* Weak or undefined symbol need PLT32 relocation. */
7986 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
7989 /* Non-global symbol doesn't need PLT32 relocation. */
7990 if (! S_IS_EXTERNAL (s
))
7993 /* Other global symbols need PLT32 relocation. NB: Symbol with
7994 non-default visibilities are treated as normal global symbol
7995 so that PLT32 relocation can be used as a marker for 32-bit
7996 PC-relative branches. It is useful for linker relaxation. */
8007 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
8009 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
8011 /* This is a loop or jecxz type instruction. */
8013 if (i
.prefix
[ADDR_PREFIX
] != 0)
8015 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
8018 /* Pentium4 branch hints. */
8019 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8020 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8022 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
8031 if (flag_code
== CODE_16BIT
)
8034 if (i
.prefix
[DATA_PREFIX
] != 0)
8036 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
8038 code16
^= flip_code16(code16
);
8046 /* BND prefixed jump. */
8047 if (i
.prefix
[BND_PREFIX
] != 0)
8049 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
8053 if (i
.prefix
[REX_PREFIX
] != 0)
8055 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
8059 if (i
.prefixes
!= 0)
8060 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8062 p
= frag_more (i
.tm
.opcode_length
+ size
);
8063 switch (i
.tm
.opcode_length
)
8066 *p
++ = i
.tm
.base_opcode
>> 8;
8069 *p
++ = i
.tm
.base_opcode
;
8075 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8077 && jump_reloc
== NO_RELOC
8078 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
8079 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
8082 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
8084 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8085 i
.op
[0].disps
, 1, jump_reloc
);
8087 /* All jumps handled here are signed, but don't use a signed limit
8088 check for 32 and 16 bit jumps as we want to allow wrap around at
8089 4G and 64k respectively. */
8091 fixP
->fx_signed
= 1;
8095 output_interseg_jump (void)
8103 if (flag_code
== CODE_16BIT
)
8107 if (i
.prefix
[DATA_PREFIX
] != 0)
8114 gas_assert (!i
.prefix
[REX_PREFIX
]);
8120 if (i
.prefixes
!= 0)
8121 as_warn (_("skipping prefixes on `%s'"), i
.tm
.name
);
8123 /* 1 opcode; 2 segment; offset */
8124 p
= frag_more (prefix
+ 1 + 2 + size
);
8126 if (i
.prefix
[DATA_PREFIX
] != 0)
8127 *p
++ = DATA_PREFIX_OPCODE
;
8129 if (i
.prefix
[REX_PREFIX
] != 0)
8130 *p
++ = i
.prefix
[REX_PREFIX
];
8132 *p
++ = i
.tm
.base_opcode
;
8133 if (i
.op
[1].imms
->X_op
== O_constant
)
8135 offsetT n
= i
.op
[1].imms
->X_add_number
;
8138 && !fits_in_unsigned_word (n
)
8139 && !fits_in_signed_word (n
))
8141 as_bad (_("16-bit jump out of range"));
8144 md_number_to_chars (p
, n
, size
);
8147 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
8148 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
8149 if (i
.op
[0].imms
->X_op
!= O_constant
)
8150 as_bad (_("can't handle non absolute segment in `%s'"),
8152 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
8155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8160 asection
*seg
= now_seg
;
8161 subsegT subseg
= now_subseg
;
8163 unsigned int alignment
, align_size_1
;
8164 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
8165 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
8166 unsigned int padding
;
8168 if (!IS_ELF
|| !x86_used_note
)
8171 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
8173 /* The .note.gnu.property section layout:
8175 Field Length Contents
8178 n_descsz 4 The note descriptor size
8179 n_type 4 NT_GNU_PROPERTY_TYPE_0
8181 n_desc n_descsz The program property array
8185 /* Create the .note.gnu.property section. */
8186 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
8187 bfd_set_section_flags (sec
,
8194 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
8205 bfd_set_section_alignment (sec
, alignment
);
8206 elf_section_type (sec
) = SHT_NOTE
;
8208 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8210 isa_1_descsz_raw
= 4 + 4 + 4;
8211 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8212 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
8214 feature_2_descsz_raw
= isa_1_descsz
;
8215 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8217 feature_2_descsz_raw
+= 4 + 4 + 4;
8218 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8219 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
8222 descsz
= feature_2_descsz
;
8223 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8224 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
8226 /* Write n_namsz. */
8227 md_number_to_chars (p
, (valueT
) 4, 4);
8229 /* Write n_descsz. */
8230 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
8233 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
8236 memcpy (p
+ 4 * 3, "GNU", 4);
8238 /* Write 4-byte type. */
8239 md_number_to_chars (p
+ 4 * 4,
8240 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
8242 /* Write 4-byte data size. */
8243 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
8245 /* Write 4-byte data. */
8246 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
8248 /* Zero out paddings. */
8249 padding
= isa_1_descsz
- isa_1_descsz_raw
;
8251 memset (p
+ 4 * 7, 0, padding
);
8253 /* Write 4-byte type. */
8254 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
8255 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
8257 /* Write 4-byte data size. */
8258 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
8260 /* Write 4-byte data. */
8261 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
8262 (valueT
) x86_feature_2_used
, 4);
8264 /* Zero out paddings. */
8265 padding
= feature_2_descsz
- feature_2_descsz_raw
;
8267 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
8269 /* We probably can't restore the current segment, for there likely
8272 subseg_set (seg
, subseg
);
8277 encoding_length (const fragS
*start_frag
, offsetT start_off
,
8278 const char *frag_now_ptr
)
8280 unsigned int len
= 0;
8282 if (start_frag
!= frag_now
)
8284 const fragS
*fr
= start_frag
;
8289 } while (fr
&& fr
!= frag_now
);
8292 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
8295 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
8296 be macro-fused with conditional jumps. */
8299 maybe_fused_with_jcc_p (void)
8301 /* No RIP address. */
8302 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
8305 /* No VEX/EVEX encoding. */
8306 if (is_any_vex_encoding (&i
.tm
))
8309 /* and, add, sub with destination register. */
8310 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
8311 || i
.tm
.base_opcode
<= 5
8312 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
8313 || ((i
.tm
.base_opcode
| 3) == 0x83
8314 && ((i
.tm
.extension_opcode
| 1) == 0x5
8315 || i
.tm
.extension_opcode
== 0x0)))
8316 return (i
.types
[1].bitfield
.class == Reg
8317 || i
.types
[1].bitfield
.instance
== Accum
);
8319 /* test, cmp with any register. */
8320 if ((i
.tm
.base_opcode
| 1) == 0x85
8321 || (i
.tm
.base_opcode
| 1) == 0xa9
8322 || ((i
.tm
.base_opcode
| 1) == 0xf7
8323 && i
.tm
.extension_opcode
== 0)
8324 || (i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
8325 || ((i
.tm
.base_opcode
| 3) == 0x83
8326 && (i
.tm
.extension_opcode
== 0x7)))
8327 return (i
.types
[0].bitfield
.class == Reg
8328 || i
.types
[0].bitfield
.instance
== Accum
8329 || i
.types
[1].bitfield
.class == Reg
8330 || i
.types
[1].bitfield
.instance
== Accum
);
8332 /* inc, dec with any register. */
8333 if ((i
.tm
.cpu_flags
.bitfield
.cpuno64
8334 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
8335 || ((i
.tm
.base_opcode
| 1) == 0xff
8336 && i
.tm
.extension_opcode
<= 0x1))
8337 return (i
.types
[0].bitfield
.class == Reg
8338 || i
.types
[0].bitfield
.instance
== Accum
);
8343 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8346 add_fused_jcc_padding_frag_p (void)
8348 /* NB: Don't work with COND_JUMP86 without i386. */
8349 if (!align_branch_power
8350 || now_seg
== absolute_section
8351 || !cpu_arch_flags
.bitfield
.cpui386
8352 || !(align_branch
& align_branch_fused_bit
))
8355 if (maybe_fused_with_jcc_p ())
8357 if (last_insn
.kind
== last_insn_other
8358 || last_insn
.seg
!= now_seg
)
8361 as_warn_where (last_insn
.file
, last_insn
.line
,
8362 _("`%s` skips -malign-branch-boundary on `%s`"),
8363 last_insn
.name
, i
.tm
.name
);
8369 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
8372 add_branch_prefix_frag_p (void)
8374 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8375 to PadLock instructions since they include prefixes in opcode. */
8376 if (!align_branch_power
8377 || !align_branch_prefix_size
8378 || now_seg
== absolute_section
8379 || i
.tm
.cpu_flags
.bitfield
.cpupadlock
8380 || !cpu_arch_flags
.bitfield
.cpui386
)
8383 /* Don't add prefix if it is a prefix or there is no operand in case
8384 that segment prefix is special. */
8385 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
8388 if (last_insn
.kind
== last_insn_other
8389 || last_insn
.seg
!= now_seg
)
8393 as_warn_where (last_insn
.file
, last_insn
.line
,
8394 _("`%s` skips -malign-branch-boundary on `%s`"),
8395 last_insn
.name
, i
.tm
.name
);
8400 /* Return 1 if a BRANCH_PADDING frag should be generated. */
8403 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
)
8407 /* NB: Don't work with COND_JUMP86 without i386. */
8408 if (!align_branch_power
8409 || now_seg
== absolute_section
8410 || !cpu_arch_flags
.bitfield
.cpui386
)
8415 /* Check for jcc and direct jmp. */
8416 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8418 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
8420 *branch_p
= align_branch_jmp
;
8421 add_padding
= align_branch
& align_branch_jmp_bit
;
8425 *branch_p
= align_branch_jcc
;
8426 if ((align_branch
& align_branch_jcc_bit
))
8430 else if (is_any_vex_encoding (&i
.tm
))
8432 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
8435 *branch_p
= align_branch_ret
;
8436 if ((align_branch
& align_branch_ret_bit
))
8441 /* Check for indirect jmp, direct and indirect calls. */
8442 if (i
.tm
.base_opcode
== 0xe8)
8445 *branch_p
= align_branch_call
;
8446 if ((align_branch
& align_branch_call_bit
))
8449 else if (i
.tm
.base_opcode
== 0xff
8450 && (i
.tm
.extension_opcode
== 2
8451 || i
.tm
.extension_opcode
== 4))
8453 /* Indirect call and jmp. */
8454 *branch_p
= align_branch_indirect
;
8455 if ((align_branch
& align_branch_indirect_bit
))
8462 && (i
.op
[0].disps
->X_op
== O_symbol
8463 || (i
.op
[0].disps
->X_op
== O_subtract
8464 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
8466 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
8467 /* No padding to call to global or undefined tls_get_addr. */
8468 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
8469 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
8475 && last_insn
.kind
!= last_insn_other
8476 && last_insn
.seg
== now_seg
)
8479 as_warn_where (last_insn
.file
, last_insn
.line
,
8480 _("`%s` skips -malign-branch-boundary on `%s`"),
8481 last_insn
.name
, i
.tm
.name
);
8491 fragS
*insn_start_frag
;
8492 offsetT insn_start_off
;
8493 fragS
*fragP
= NULL
;
8494 enum align_branch_kind branch
= align_branch_none
;
8496 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8497 if (IS_ELF
&& x86_used_note
)
8499 if (i
.tm
.cpu_flags
.bitfield
.cpucmov
)
8500 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_CMOV
;
8501 if (i
.tm
.cpu_flags
.bitfield
.cpusse
)
8502 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE
;
8503 if (i
.tm
.cpu_flags
.bitfield
.cpusse2
)
8504 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE2
;
8505 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
)
8506 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE3
;
8507 if (i
.tm
.cpu_flags
.bitfield
.cpussse3
)
8508 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSSE3
;
8509 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_1
)
8510 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_1
;
8511 if (i
.tm
.cpu_flags
.bitfield
.cpusse4_2
)
8512 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_SSE4_2
;
8513 if (i
.tm
.cpu_flags
.bitfield
.cpuavx
)
8514 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX
;
8515 if (i
.tm
.cpu_flags
.bitfield
.cpuavx2
)
8516 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX2
;
8517 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
8518 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_FMA
;
8519 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512f
)
8520 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512F
;
8521 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512cd
)
8522 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512CD
;
8523 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512er
)
8524 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512ER
;
8525 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512pf
)
8526 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512PF
;
8527 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vl
)
8528 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512VL
;
8529 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512dq
)
8530 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512DQ
;
8531 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512bw
)
8532 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512BW
;
8533 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4fmaps
)
8534 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS
;
8535 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_4vnniw
)
8536 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW
;
8537 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bitalg
)
8538 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG
;
8539 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512ifma
)
8540 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA
;
8541 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512vbmi
)
8542 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI
;
8543 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vbmi2
)
8544 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2
;
8545 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_vnni
)
8546 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI
;
8547 if (i
.tm
.cpu_flags
.bitfield
.cpuavx512_bf16
)
8548 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_AVX512_BF16
;
8550 if (i
.tm
.cpu_flags
.bitfield
.cpu8087
8551 || i
.tm
.cpu_flags
.bitfield
.cpu287
8552 || i
.tm
.cpu_flags
.bitfield
.cpu387
8553 || i
.tm
.cpu_flags
.bitfield
.cpu687
8554 || i
.tm
.cpu_flags
.bitfield
.cpufisttp
)
8555 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
8557 || i
.tm
.base_opcode
== 0xf77 /* emms */
8558 || i
.tm
.base_opcode
== 0xf0e /* femms */)
8559 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
8561 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
8563 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
8565 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
8566 if (i
.tm
.cpu_flags
.bitfield
.cpufxsr
)
8567 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
8568 if (i
.tm
.cpu_flags
.bitfield
.cpuxsave
)
8569 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
8570 if (i
.tm
.cpu_flags
.bitfield
.cpuxsaveopt
)
8571 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
8572 if (i
.tm
.cpu_flags
.bitfield
.cpuxsavec
)
8573 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
8577 /* Tie dwarf2 debug info to the address at the start of the insn.
8578 We can't do this after the insn has been output as the current
8579 frag may have been closed off. eg. by frag_var. */
8580 dwarf2_emit_insn (0);
8582 insn_start_frag
= frag_now
;
8583 insn_start_off
= frag_now_fix ();
8585 if (add_branch_padding_frag_p (&branch
))
8588 /* Branch can be 8 bytes. Leave some room for prefixes. */
8589 unsigned int max_branch_padding_size
= 14;
8591 /* Align section to boundary. */
8592 record_alignment (now_seg
, align_branch_power
);
8594 /* Make room for padding. */
8595 frag_grow (max_branch_padding_size
);
8597 /* Start of the padding. */
8602 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
8603 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
8606 fragP
->tc_frag_data
.branch_type
= branch
;
8607 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
8611 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
8613 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
8614 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
8616 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
8617 output_interseg_jump ();
8620 /* Output normal instructions here. */
8624 unsigned int prefix
;
8627 && (i
.tm
.base_opcode
== 0xfaee8
8628 || i
.tm
.base_opcode
== 0xfaef0
8629 || i
.tm
.base_opcode
== 0xfaef8))
8631 /* Encode lfence, mfence, and sfence as
8632 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8633 offsetT val
= 0x240483f0ULL
;
8635 md_number_to_chars (p
, val
, 5);
8639 /* Some processors fail on LOCK prefix. This options makes
8640 assembler ignore LOCK prefix and serves as a workaround. */
8641 if (omit_lock_prefix
)
8643 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
8645 i
.prefix
[LOCK_PREFIX
] = 0;
8649 /* Skip if this is a branch. */
8651 else if (add_fused_jcc_padding_frag_p ())
8653 /* Make room for padding. */
8654 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
8659 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
8660 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
8663 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
8664 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
8666 else if (add_branch_prefix_frag_p ())
8668 unsigned int max_prefix_size
= align_branch_prefix_size
;
8670 /* Make room for padding. */
8671 frag_grow (max_prefix_size
);
8676 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
8677 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
8680 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
8683 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8684 don't need the explicit prefix. */
8685 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
8687 switch (i
.tm
.opcode_length
)
8690 if (i
.tm
.base_opcode
& 0xff000000)
8692 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
8693 if (!i
.tm
.cpu_flags
.bitfield
.cpupadlock
8694 || prefix
!= REPE_PREFIX_OPCODE
8695 || (i
.prefix
[REP_PREFIX
] != REPE_PREFIX_OPCODE
))
8696 add_prefix (prefix
);
8700 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
8702 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
8703 add_prefix (prefix
);
8709 /* Check for pseudo prefixes. */
8710 as_bad_where (insn_start_frag
->fr_file
,
8711 insn_start_frag
->fr_line
,
8712 _("pseudo prefix without instruction"));
8718 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8719 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8720 R_X86_64_GOTTPOFF relocation so that linker can safely
8721 perform IE->LE optimization. */
8722 if (x86_elf_abi
== X86_64_X32_ABI
8724 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
8725 && i
.prefix
[REX_PREFIX
] == 0)
8726 add_prefix (REX_OPCODE
);
8729 /* The prefix bytes. */
8730 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
8732 FRAG_APPEND_1_CHAR (*q
);
8736 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
8741 /* REX byte is encoded in VEX prefix. */
8745 FRAG_APPEND_1_CHAR (*q
);
8748 /* There should be no other prefixes for instructions
8753 /* For EVEX instructions i.vrex should become 0 after
8754 build_evex_prefix. For VEX instructions upper 16 registers
8755 aren't available, so VREX should be 0. */
8758 /* Now the VEX prefix. */
8759 p
= frag_more (i
.vex
.length
);
8760 for (j
= 0; j
< i
.vex
.length
; j
++)
8761 p
[j
] = i
.vex
.bytes
[j
];
8764 /* Now the opcode; be careful about word order here! */
8765 if (i
.tm
.opcode_length
== 1)
8767 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
8771 switch (i
.tm
.opcode_length
)
8775 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
8776 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8780 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
8790 /* Put out high byte first: can't use md_number_to_chars! */
8791 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
8792 *p
= i
.tm
.base_opcode
& 0xff;
8795 /* Now the modrm byte and sib byte (if present). */
8796 if (i
.tm
.opcode_modifier
.modrm
)
8798 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
8801 /* If i.rm.regmem == ESP (4)
8802 && i.rm.mode != (Register mode)
8804 ==> need second modrm byte. */
8805 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
8807 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
8808 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
8810 | i
.sib
.scale
<< 6));
8813 if (i
.disp_operands
)
8814 output_disp (insn_start_frag
, insn_start_off
);
8817 output_imm (insn_start_frag
, insn_start_off
);
8820 * frag_now_fix () returning plain abs_section_offset when we're in the
8821 * absolute section, and abs_section_offset not getting updated as data
8822 * gets added to the frag breaks the logic below.
8824 if (now_seg
!= absolute_section
)
8826 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
8828 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8832 /* NB: Don't add prefix with GOTPC relocation since
8833 output_disp() above depends on the fixed encoding
8834 length. Can't add prefix with TLS relocation since
8835 it breaks TLS linker optimization. */
8836 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
8837 /* Prefix count on the current instruction. */
8838 unsigned int count
= i
.vex
.length
;
8840 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
8841 /* REX byte is encoded in VEX/EVEX prefix. */
8842 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
8845 /* Count prefixes for extended opcode maps. */
8847 switch (i
.tm
.opcode_length
)
8850 if (((i
.tm
.base_opcode
>> 16) & 0xff) == 0xf)
8853 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
8865 if (((i
.tm
.base_opcode
>> 8) & 0xff) == 0xf)
8874 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
8877 /* Set the maximum prefix size in BRANCH_PREFIX
8879 if (fragP
->tc_frag_data
.max_bytes
> max
)
8880 fragP
->tc_frag_data
.max_bytes
= max
;
8881 if (fragP
->tc_frag_data
.max_bytes
> count
)
8882 fragP
->tc_frag_data
.max_bytes
-= count
;
8884 fragP
->tc_frag_data
.max_bytes
= 0;
8888 /* Remember the maximum prefix size in FUSED_JCC_PADDING
8890 unsigned int max_prefix_size
;
8891 if (align_branch_prefix_size
> max
)
8892 max_prefix_size
= max
;
8894 max_prefix_size
= align_branch_prefix_size
;
8895 if (max_prefix_size
> count
)
8896 fragP
->tc_frag_data
.max_prefix_length
8897 = max_prefix_size
- count
;
8900 /* Use existing segment prefix if possible. Use CS
8901 segment prefix in 64-bit mode. In 32-bit mode, use SS
8902 segment prefix with ESP/EBP base register and use DS
8903 segment prefix without ESP/EBP base register. */
8904 if (i
.prefix
[SEG_PREFIX
])
8905 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
8906 else if (flag_code
== CODE_64BIT
)
8907 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
8909 && (i
.base_reg
->reg_num
== 4
8910 || i
.base_reg
->reg_num
== 5))
8911 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
8913 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
8918 /* NB: Don't work with COND_JUMP86 without i386. */
8919 if (align_branch_power
8920 && now_seg
!= absolute_section
8921 && cpu_arch_flags
.bitfield
.cpui386
)
8923 /* Terminate each frag so that we can add prefix and check for
8925 frag_wane (frag_now
);
8932 pi ("" /*line*/, &i
);
8934 #endif /* DEBUG386 */
8937 /* Return the size of the displacement operand N. */
8940 disp_size (unsigned int n
)
8944 if (i
.types
[n
].bitfield
.disp64
)
8946 else if (i
.types
[n
].bitfield
.disp8
)
8948 else if (i
.types
[n
].bitfield
.disp16
)
8953 /* Return the size of the immediate operand N. */
8956 imm_size (unsigned int n
)
8959 if (i
.types
[n
].bitfield
.imm64
)
8961 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
8963 else if (i
.types
[n
].bitfield
.imm16
)
8969 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
8974 for (n
= 0; n
< i
.operands
; n
++)
8976 if (operand_type_check (i
.types
[n
], disp
))
8978 if (i
.op
[n
].disps
->X_op
== O_constant
)
8980 int size
= disp_size (n
);
8981 offsetT val
= i
.op
[n
].disps
->X_add_number
;
8983 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
8985 p
= frag_more (size
);
8986 md_number_to_chars (p
, val
, size
);
8990 enum bfd_reloc_code_real reloc_type
;
8991 int size
= disp_size (n
);
8992 int sign
= i
.types
[n
].bitfield
.disp32s
;
8993 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
8996 /* We can't have 8 bit displacement here. */
8997 gas_assert (!i
.types
[n
].bitfield
.disp8
);
8999 /* The PC relative address is computed relative
9000 to the instruction boundary, so in case immediate
9001 fields follows, we need to adjust the value. */
9002 if (pcrel
&& i
.imm_operands
)
9007 for (n1
= 0; n1
< i
.operands
; n1
++)
9008 if (operand_type_check (i
.types
[n1
], imm
))
9010 /* Only one immediate is allowed for PC
9011 relative address. */
9012 gas_assert (sz
== 0);
9014 i
.op
[n
].disps
->X_add_number
-= sz
;
9016 /* We should find the immediate. */
9017 gas_assert (sz
!= 0);
9020 p
= frag_more (size
);
9021 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
9023 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
9024 && (((reloc_type
== BFD_RELOC_32
9025 || reloc_type
== BFD_RELOC_X86_64_32S
9026 || (reloc_type
== BFD_RELOC_64
9028 && (i
.op
[n
].disps
->X_op
== O_symbol
9029 || (i
.op
[n
].disps
->X_op
== O_add
9030 && ((symbol_get_value_expression
9031 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
9033 || reloc_type
== BFD_RELOC_32_PCREL
))
9037 reloc_type
= BFD_RELOC_386_GOTPC
;
9038 i
.has_gotpc_tls_reloc
= TRUE
;
9039 i
.op
[n
].imms
->X_add_number
+=
9040 encoding_length (insn_start_frag
, insn_start_off
, p
);
9042 else if (reloc_type
== BFD_RELOC_64
)
9043 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9045 /* Don't do the adjustment for x86-64, as there
9046 the pcrel addressing is relative to the _next_
9047 insn, and that is taken care of in other code. */
9048 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9050 else if (align_branch_power
)
9054 case BFD_RELOC_386_TLS_GD
:
9055 case BFD_RELOC_386_TLS_LDM
:
9056 case BFD_RELOC_386_TLS_IE
:
9057 case BFD_RELOC_386_TLS_IE_32
:
9058 case BFD_RELOC_386_TLS_GOTIE
:
9059 case BFD_RELOC_386_TLS_GOTDESC
:
9060 case BFD_RELOC_386_TLS_DESC_CALL
:
9061 case BFD_RELOC_X86_64_TLSGD
:
9062 case BFD_RELOC_X86_64_TLSLD
:
9063 case BFD_RELOC_X86_64_GOTTPOFF
:
9064 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9065 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9066 i
.has_gotpc_tls_reloc
= TRUE
;
9071 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
9072 size
, i
.op
[n
].disps
, pcrel
,
9074 /* Check for "call/jmp *mem", "mov mem, %reg",
9075 "test %reg, mem" and "binop mem, %reg" where binop
9076 is one of adc, add, and, cmp, or, sbb, sub, xor
9077 instructions without data prefix. Always generate
9078 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9079 if (i
.prefix
[DATA_PREFIX
] == 0
9080 && (generate_relax_relocations
9083 && i
.rm
.regmem
== 5))
9085 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
9086 && ((i
.operands
== 1
9087 && i
.tm
.base_opcode
== 0xff
9088 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
9090 && (i
.tm
.base_opcode
== 0x8b
9091 || i
.tm
.base_opcode
== 0x85
9092 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
9096 fixP
->fx_tcbit
= i
.rex
!= 0;
9098 && (i
.base_reg
->reg_num
== RegIP
))
9099 fixP
->fx_tcbit2
= 1;
9102 fixP
->fx_tcbit2
= 1;
9110 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
9115 for (n
= 0; n
< i
.operands
; n
++)
9117 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9118 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
9121 if (operand_type_check (i
.types
[n
], imm
))
9123 if (i
.op
[n
].imms
->X_op
== O_constant
)
9125 int size
= imm_size (n
);
9128 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
9130 p
= frag_more (size
);
9131 md_number_to_chars (p
, val
, size
);
9135 /* Not absolute_section.
9136 Need a 32-bit fixup (don't support 8bit
9137 non-absolute imms). Try to support other
9139 enum bfd_reloc_code_real reloc_type
;
9140 int size
= imm_size (n
);
9143 if (i
.types
[n
].bitfield
.imm32s
9144 && (i
.suffix
== QWORD_MNEM_SUFFIX
9145 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
9150 p
= frag_more (size
);
9151 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
9153 /* This is tough to explain. We end up with this one if we
9154 * have operands that look like
9155 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9156 * obtain the absolute address of the GOT, and it is strongly
9157 * preferable from a performance point of view to avoid using
9158 * a runtime relocation for this. The actual sequence of
9159 * instructions often look something like:
9164 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9166 * The call and pop essentially return the absolute address
9167 * of the label .L66 and store it in %ebx. The linker itself
9168 * will ultimately change the first operand of the addl so
9169 * that %ebx points to the GOT, but to keep things simple, the
9170 * .o file must have this operand set so that it generates not
9171 * the absolute address of .L66, but the absolute address of
9172 * itself. This allows the linker itself simply treat a GOTPC
9173 * relocation as asking for a pcrel offset to the GOT to be
9174 * added in, and the addend of the relocation is stored in the
9175 * operand field for the instruction itself.
9177 * Our job here is to fix the operand so that it would add
9178 * the correct offset so that %ebx would point to itself. The
9179 * thing that is tricky is that .-.L66 will point to the
9180 * beginning of the instruction, so we need to further modify
9181 * the operand so that it will point to itself. There are
9182 * other cases where you have something like:
9184 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9186 * and here no correction would be required. Internally in
9187 * the assembler we treat operands of this form as not being
9188 * pcrel since the '.' is explicitly mentioned, and I wonder
9189 * whether it would simplify matters to do it this way. Who
9190 * knows. In earlier versions of the PIC patches, the
9191 * pcrel_adjust field was used to store the correction, but
9192 * since the expression is not pcrel, I felt it would be
9193 * confusing to do it this way. */
9195 if ((reloc_type
== BFD_RELOC_32
9196 || reloc_type
== BFD_RELOC_X86_64_32S
9197 || reloc_type
== BFD_RELOC_64
)
9199 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
9200 && (i
.op
[n
].imms
->X_op
== O_symbol
9201 || (i
.op
[n
].imms
->X_op
== O_add
9202 && ((symbol_get_value_expression
9203 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
9207 reloc_type
= BFD_RELOC_386_GOTPC
;
9209 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
9211 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
9212 i
.has_gotpc_tls_reloc
= TRUE
;
9213 i
.op
[n
].imms
->X_add_number
+=
9214 encoding_length (insn_start_frag
, insn_start_off
, p
);
9216 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9217 i
.op
[n
].imms
, 0, reloc_type
);
9223 /* x86_cons_fix_new is called via the expression parsing code when a
9224 reloc is needed. We use this hook to get the correct .got reloc. */
9225 static int cons_sign
= -1;
9228 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
9229 expressionS
*exp
, bfd_reloc_code_real_type r
)
9231 r
= reloc (len
, 0, cons_sign
, r
);
9234 if (exp
->X_op
== O_secrel
)
9236 exp
->X_op
= O_symbol
;
9237 r
= BFD_RELOC_32_SECREL
;
9241 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
9244 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9245 purpose of the `.dc.a' internal pseudo-op. */
9248 x86_address_bytes (void)
9250 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
9252 return stdoutput
->arch_info
->bits_per_address
/ 8;
9255 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9257 # define lex_got(reloc, adjust, types) NULL
9259 /* Parse operands of the form
9260 <symbol>@GOTOFF+<nnn>
9261 and similar .plt or .got references.
9263 If we find one, set up the correct relocation in RELOC and copy the
9264 input string, minus the `@GOTOFF' into a malloc'd buffer for
9265 parsing by the calling routine. Return this buffer, and if ADJUST
9266 is non-null set it to the length of the string we removed from the
9267 input line. Otherwise return NULL. */
9269 lex_got (enum bfd_reloc_code_real
*rel
,
9271 i386_operand_type
*types
)
9273 /* Some of the relocations depend on the size of what field is to
9274 be relocated. But in our callers i386_immediate and i386_displacement
9275 we don't yet know the operand size (this will be set by insn
9276 matching). Hence we record the word32 relocation here,
9277 and adjust the reloc according to the real size in reloc(). */
9278 static const struct {
9281 const enum bfd_reloc_code_real rel
[2];
9282 const i386_operand_type types64
;
9284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9285 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
9287 OPERAND_TYPE_IMM32_64
},
9289 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
9290 BFD_RELOC_X86_64_PLTOFF64
},
9291 OPERAND_TYPE_IMM64
},
9292 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
9293 BFD_RELOC_X86_64_PLT32
},
9294 OPERAND_TYPE_IMM32_32S_DISP32
},
9295 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
9296 BFD_RELOC_X86_64_GOTPLT64
},
9297 OPERAND_TYPE_IMM64_DISP64
},
9298 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
9299 BFD_RELOC_X86_64_GOTOFF64
},
9300 OPERAND_TYPE_IMM64_DISP64
},
9301 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
9302 BFD_RELOC_X86_64_GOTPCREL
},
9303 OPERAND_TYPE_IMM32_32S_DISP32
},
9304 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
9305 BFD_RELOC_X86_64_TLSGD
},
9306 OPERAND_TYPE_IMM32_32S_DISP32
},
9307 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
9308 _dummy_first_bfd_reloc_code_real
},
9309 OPERAND_TYPE_NONE
},
9310 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
9311 BFD_RELOC_X86_64_TLSLD
},
9312 OPERAND_TYPE_IMM32_32S_DISP32
},
9313 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
9314 BFD_RELOC_X86_64_GOTTPOFF
},
9315 OPERAND_TYPE_IMM32_32S_DISP32
},
9316 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
9317 BFD_RELOC_X86_64_TPOFF32
},
9318 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9319 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
9320 _dummy_first_bfd_reloc_code_real
},
9321 OPERAND_TYPE_NONE
},
9322 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
9323 BFD_RELOC_X86_64_DTPOFF32
},
9324 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9325 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
9326 _dummy_first_bfd_reloc_code_real
},
9327 OPERAND_TYPE_NONE
},
9328 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
9329 _dummy_first_bfd_reloc_code_real
},
9330 OPERAND_TYPE_NONE
},
9331 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
9332 BFD_RELOC_X86_64_GOT32
},
9333 OPERAND_TYPE_IMM32_32S_64_DISP32
},
9334 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
9335 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
9336 OPERAND_TYPE_IMM32_32S_DISP32
},
9337 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
9338 BFD_RELOC_X86_64_TLSDESC_CALL
},
9339 OPERAND_TYPE_IMM32_32S_DISP32
},
9344 #if defined (OBJ_MAYBE_ELF)
9349 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9350 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9353 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9355 int len
= gotrel
[j
].len
;
9356 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9358 if (gotrel
[j
].rel
[object_64bit
] != 0)
9361 char *tmpbuf
, *past_reloc
;
9363 *rel
= gotrel
[j
].rel
[object_64bit
];
9367 if (flag_code
!= CODE_64BIT
)
9369 types
->bitfield
.imm32
= 1;
9370 types
->bitfield
.disp32
= 1;
9373 *types
= gotrel
[j
].types64
;
9376 if (j
!= 0 && GOT_symbol
== NULL
)
9377 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
9379 /* The length of the first part of our input line. */
9380 first
= cp
- input_line_pointer
;
9382 /* The second part goes from after the reloc token until
9383 (and including) an end_of_line char or comma. */
9384 past_reloc
= cp
+ 1 + len
;
9386 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9388 second
= cp
+ 1 - past_reloc
;
9390 /* Allocate and copy string. The trailing NUL shouldn't
9391 be necessary, but be safe. */
9392 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9393 memcpy (tmpbuf
, input_line_pointer
, first
);
9394 if (second
!= 0 && *past_reloc
!= ' ')
9395 /* Replace the relocation token with ' ', so that
9396 errors like foo@GOTOFF1 will be detected. */
9397 tmpbuf
[first
++] = ' ';
9399 /* Increment length by 1 if the relocation token is
9404 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9405 tmpbuf
[first
+ second
] = '\0';
9409 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9410 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9415 /* Might be a symbol version string. Don't as_bad here. */
9424 /* Parse operands of the form
9425 <symbol>@SECREL32+<nnn>
9427 If we find one, set up the correct relocation in RELOC and copy the
9428 input string, minus the `@SECREL32' into a malloc'd buffer for
9429 parsing by the calling routine. Return this buffer, and if ADJUST
9430 is non-null set it to the length of the string we removed from the
9431 input line. Otherwise return NULL.
9433 This function is copied from the ELF version above adjusted for PE targets. */
9436 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
9437 int *adjust ATTRIBUTE_UNUSED
,
9438 i386_operand_type
*types
)
9444 const enum bfd_reloc_code_real rel
[2];
9445 const i386_operand_type types64
;
9449 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
9450 BFD_RELOC_32_SECREL
},
9451 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
9457 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
9458 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
9461 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
9463 int len
= gotrel
[j
].len
;
9465 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
9467 if (gotrel
[j
].rel
[object_64bit
] != 0)
9470 char *tmpbuf
, *past_reloc
;
9472 *rel
= gotrel
[j
].rel
[object_64bit
];
9478 if (flag_code
!= CODE_64BIT
)
9480 types
->bitfield
.imm32
= 1;
9481 types
->bitfield
.disp32
= 1;
9484 *types
= gotrel
[j
].types64
;
9487 /* The length of the first part of our input line. */
9488 first
= cp
- input_line_pointer
;
9490 /* The second part goes from after the reloc token until
9491 (and including) an end_of_line char or comma. */
9492 past_reloc
= cp
+ 1 + len
;
9494 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
9496 second
= cp
+ 1 - past_reloc
;
9498 /* Allocate and copy string. The trailing NUL shouldn't
9499 be necessary, but be safe. */
9500 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
9501 memcpy (tmpbuf
, input_line_pointer
, first
);
9502 if (second
!= 0 && *past_reloc
!= ' ')
9503 /* Replace the relocation token with ' ', so that
9504 errors like foo@SECLREL321 will be detected. */
9505 tmpbuf
[first
++] = ' ';
9506 memcpy (tmpbuf
+ first
, past_reloc
, second
);
9507 tmpbuf
[first
+ second
] = '\0';
9511 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9512 gotrel
[j
].str
, 1 << (5 + object_64bit
));
9517 /* Might be a symbol version string. Don't as_bad here. */
9523 bfd_reloc_code_real_type
9524 x86_cons (expressionS
*exp
, int size
)
9526 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
9528 intel_syntax
= -intel_syntax
;
9531 if (size
== 4 || (object_64bit
&& size
== 8))
9533 /* Handle @GOTOFF and the like in an expression. */
9535 char *gotfree_input_line
;
9538 save
= input_line_pointer
;
9539 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
9540 if (gotfree_input_line
)
9541 input_line_pointer
= gotfree_input_line
;
9545 if (gotfree_input_line
)
9547 /* expression () has merrily parsed up to the end of line,
9548 or a comma - in the wrong buffer. Transfer how far
9549 input_line_pointer has moved to the right buffer. */
9550 input_line_pointer
= (save
9551 + (input_line_pointer
- gotfree_input_line
)
9553 free (gotfree_input_line
);
9554 if (exp
->X_op
== O_constant
9555 || exp
->X_op
== O_absent
9556 || exp
->X_op
== O_illegal
9557 || exp
->X_op
== O_register
9558 || exp
->X_op
== O_big
)
9560 char c
= *input_line_pointer
;
9561 *input_line_pointer
= 0;
9562 as_bad (_("missing or invalid expression `%s'"), save
);
9563 *input_line_pointer
= c
;
9565 else if ((got_reloc
== BFD_RELOC_386_PLT32
9566 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
9567 && exp
->X_op
!= O_symbol
)
9569 char c
= *input_line_pointer
;
9570 *input_line_pointer
= 0;
9571 as_bad (_("invalid PLT expression `%s'"), save
);
9572 *input_line_pointer
= c
;
9579 intel_syntax
= -intel_syntax
;
9582 i386_intel_simplify (exp
);
9588 signed_cons (int size
)
9590 if (flag_code
== CODE_64BIT
)
9598 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
9605 if (exp
.X_op
== O_symbol
)
9606 exp
.X_op
= O_secrel
;
9608 emit_expr (&exp
, 4);
9610 while (*input_line_pointer
++ == ',');
9612 input_line_pointer
--;
9613 demand_empty_rest_of_line ();
9617 /* Handle Vector operations. */
9620 check_VecOperations (char *op_string
, char *op_end
)
9622 const reg_entry
*mask
;
9627 && (op_end
== NULL
|| op_string
< op_end
))
9630 if (*op_string
== '{')
9634 /* Check broadcasts. */
9635 if (strncmp (op_string
, "1to", 3) == 0)
9640 goto duplicated_vec_op
;
9643 if (*op_string
== '8')
9645 else if (*op_string
== '4')
9647 else if (*op_string
== '2')
9649 else if (*op_string
== '1'
9650 && *(op_string
+1) == '6')
9657 as_bad (_("Unsupported broadcast: `%s'"), saved
);
9662 broadcast_op
.type
= bcst_type
;
9663 broadcast_op
.operand
= this_operand
;
9664 broadcast_op
.bytes
= 0;
9665 i
.broadcast
= &broadcast_op
;
9667 /* Check masking operation. */
9668 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
9670 /* k0 can't be used for write mask. */
9671 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
9673 as_bad (_("`%s%s' can't be used for write mask"),
9674 register_prefix
, mask
->reg_name
);
9680 mask_op
.mask
= mask
;
9681 mask_op
.zeroing
= 0;
9682 mask_op
.operand
= this_operand
;
9688 goto duplicated_vec_op
;
9690 i
.mask
->mask
= mask
;
9692 /* Only "{z}" is allowed here. No need to check
9693 zeroing mask explicitly. */
9694 if (i
.mask
->operand
!= this_operand
)
9696 as_bad (_("invalid write mask `%s'"), saved
);
9703 /* Check zeroing-flag for masking operation. */
9704 else if (*op_string
== 'z')
9708 mask_op
.mask
= NULL
;
9709 mask_op
.zeroing
= 1;
9710 mask_op
.operand
= this_operand
;
9715 if (i
.mask
->zeroing
)
9718 as_bad (_("duplicated `%s'"), saved
);
9722 i
.mask
->zeroing
= 1;
9724 /* Only "{%k}" is allowed here. No need to check mask
9725 register explicitly. */
9726 if (i
.mask
->operand
!= this_operand
)
9728 as_bad (_("invalid zeroing-masking `%s'"),
9737 goto unknown_vec_op
;
9739 if (*op_string
!= '}')
9741 as_bad (_("missing `}' in `%s'"), saved
);
9746 /* Strip whitespace since the addition of pseudo prefixes
9747 changed how the scrubber treats '{'. */
9748 if (is_space_char (*op_string
))
9754 /* We don't know this one. */
9755 as_bad (_("unknown vector operation: `%s'"), saved
);
9759 if (i
.mask
&& i
.mask
->zeroing
&& !i
.mask
->mask
)
9761 as_bad (_("zeroing-masking only allowed with write mask"));
9769 i386_immediate (char *imm_start
)
9771 char *save_input_line_pointer
;
9772 char *gotfree_input_line
;
9775 i386_operand_type types
;
9777 operand_type_set (&types
, ~0);
9779 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
9781 as_bad (_("at most %d immediate operands are allowed"),
9782 MAX_IMMEDIATE_OPERANDS
);
9786 exp
= &im_expressions
[i
.imm_operands
++];
9787 i
.op
[this_operand
].imms
= exp
;
9789 if (is_space_char (*imm_start
))
9792 save_input_line_pointer
= input_line_pointer
;
9793 input_line_pointer
= imm_start
;
9795 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
9796 if (gotfree_input_line
)
9797 input_line_pointer
= gotfree_input_line
;
9799 exp_seg
= expression (exp
);
9803 /* Handle vector operations. */
9804 if (*input_line_pointer
== '{')
9806 input_line_pointer
= check_VecOperations (input_line_pointer
,
9808 if (input_line_pointer
== NULL
)
9812 if (*input_line_pointer
)
9813 as_bad (_("junk `%s' after expression"), input_line_pointer
);
9815 input_line_pointer
= save_input_line_pointer
;
9816 if (gotfree_input_line
)
9818 free (gotfree_input_line
);
9820 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
9821 exp
->X_op
= O_illegal
;
9824 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
9828 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
9829 i386_operand_type types
, const char *imm_start
)
9831 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
9834 as_bad (_("missing or invalid immediate expression `%s'"),
9838 else if (exp
->X_op
== O_constant
)
9840 /* Size it properly later. */
9841 i
.types
[this_operand
].bitfield
.imm64
= 1;
9842 /* If not 64bit, sign extend val. */
9843 if (flag_code
!= CODE_64BIT
9844 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
9846 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
9848 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9849 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
9850 && exp_seg
!= absolute_section
9851 && exp_seg
!= text_section
9852 && exp_seg
!= data_section
9853 && exp_seg
!= bss_section
9854 && exp_seg
!= undefined_section
9855 && !bfd_is_com_section (exp_seg
))
9857 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
9861 else if (!intel_syntax
&& exp_seg
== reg_section
)
9864 as_bad (_("illegal immediate register operand %s"), imm_start
);
9869 /* This is an address. The size of the address will be
9870 determined later, depending on destination register,
9871 suffix, or the default for the section. */
9872 i
.types
[this_operand
].bitfield
.imm8
= 1;
9873 i
.types
[this_operand
].bitfield
.imm16
= 1;
9874 i
.types
[this_operand
].bitfield
.imm32
= 1;
9875 i
.types
[this_operand
].bitfield
.imm32s
= 1;
9876 i
.types
[this_operand
].bitfield
.imm64
= 1;
9877 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
9885 i386_scale (char *scale
)
9888 char *save
= input_line_pointer
;
9890 input_line_pointer
= scale
;
9891 val
= get_absolute_expression ();
9896 i
.log2_scale_factor
= 0;
9899 i
.log2_scale_factor
= 1;
9902 i
.log2_scale_factor
= 2;
9905 i
.log2_scale_factor
= 3;
9909 char sep
= *input_line_pointer
;
9911 *input_line_pointer
= '\0';
9912 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9914 *input_line_pointer
= sep
;
9915 input_line_pointer
= save
;
9919 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
9921 as_warn (_("scale factor of %d without an index register"),
9922 1 << i
.log2_scale_factor
);
9923 i
.log2_scale_factor
= 0;
9925 scale
= input_line_pointer
;
9926 input_line_pointer
= save
;
9931 i386_displacement (char *disp_start
, char *disp_end
)
9935 char *save_input_line_pointer
;
9936 char *gotfree_input_line
;
9938 i386_operand_type bigdisp
, types
= anydisp
;
9941 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
9943 as_bad (_("at most %d displacement operands are allowed"),
9944 MAX_MEMORY_OPERANDS
);
9948 operand_type_set (&bigdisp
, 0);
9950 || i
.types
[this_operand
].bitfield
.baseindex
9951 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
9952 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
9954 i386_addressing_mode ();
9955 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
9956 if (flag_code
== CODE_64BIT
)
9960 bigdisp
.bitfield
.disp32s
= 1;
9961 bigdisp
.bitfield
.disp64
= 1;
9964 bigdisp
.bitfield
.disp32
= 1;
9966 else if ((flag_code
== CODE_16BIT
) ^ override
)
9967 bigdisp
.bitfield
.disp16
= 1;
9969 bigdisp
.bitfield
.disp32
= 1;
9973 /* For PC-relative branches, the width of the displacement may be
9974 dependent upon data size, but is never dependent upon address size.
9975 Also make sure to not unintentionally match against a non-PC-relative
9977 static templates aux_templates
;
9978 const insn_template
*t
= current_templates
->start
;
9979 bfd_boolean has_intel64
= FALSE
;
9981 aux_templates
.start
= t
;
9982 while (++t
< current_templates
->end
)
9984 if (t
->opcode_modifier
.jump
9985 != current_templates
->start
->opcode_modifier
.jump
)
9987 if (t
->opcode_modifier
.intel64
)
9990 if (t
< current_templates
->end
)
9992 aux_templates
.end
= t
;
9993 current_templates
= &aux_templates
;
9996 override
= (i
.prefix
[DATA_PREFIX
] != 0);
9997 if (flag_code
== CODE_64BIT
)
9999 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
10000 && (!intel64
|| !has_intel64
))
10001 bigdisp
.bitfield
.disp16
= 1;
10003 bigdisp
.bitfield
.disp32s
= 1;
10008 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
10010 : LONG_MNEM_SUFFIX
));
10011 bigdisp
.bitfield
.disp32
= 1;
10012 if ((flag_code
== CODE_16BIT
) ^ override
)
10014 bigdisp
.bitfield
.disp32
= 0;
10015 bigdisp
.bitfield
.disp16
= 1;
10019 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10022 exp
= &disp_expressions
[i
.disp_operands
];
10023 i
.op
[this_operand
].disps
= exp
;
10025 save_input_line_pointer
= input_line_pointer
;
10026 input_line_pointer
= disp_start
;
10027 END_STRING_AND_SAVE (disp_end
);
10029 #ifndef GCC_ASM_O_HACK
10030 #define GCC_ASM_O_HACK 0
10033 END_STRING_AND_SAVE (disp_end
+ 1);
10034 if (i
.types
[this_operand
].bitfield
.baseIndex
10035 && displacement_string_end
[-1] == '+')
10037 /* This hack is to avoid a warning when using the "o"
10038 constraint within gcc asm statements.
10041 #define _set_tssldt_desc(n,addr,limit,type) \
10042 __asm__ __volatile__ ( \
10043 "movw %w2,%0\n\t" \
10044 "movw %w1,2+%0\n\t" \
10045 "rorl $16,%1\n\t" \
10046 "movb %b1,4+%0\n\t" \
10047 "movb %4,5+%0\n\t" \
10048 "movb $0,6+%0\n\t" \
10049 "movb %h1,7+%0\n\t" \
10051 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10053 This works great except that the output assembler ends
10054 up looking a bit weird if it turns out that there is
10055 no offset. You end up producing code that looks like:
10068 So here we provide the missing zero. */
10070 *displacement_string_end
= '0';
10073 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
10074 if (gotfree_input_line
)
10075 input_line_pointer
= gotfree_input_line
;
10077 exp_seg
= expression (exp
);
10079 SKIP_WHITESPACE ();
10080 if (*input_line_pointer
)
10081 as_bad (_("junk `%s' after expression"), input_line_pointer
);
10083 RESTORE_END_STRING (disp_end
+ 1);
10085 input_line_pointer
= save_input_line_pointer
;
10086 if (gotfree_input_line
)
10088 free (gotfree_input_line
);
10090 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
10091 exp
->X_op
= O_illegal
;
10094 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
10096 RESTORE_END_STRING (disp_end
);
10102 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
10103 i386_operand_type types
, const char *disp_start
)
10105 i386_operand_type bigdisp
;
10108 /* We do this to make sure that the section symbol is in
10109 the symbol table. We will ultimately change the relocation
10110 to be relative to the beginning of the section. */
10111 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
10112 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
10113 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10115 if (exp
->X_op
!= O_symbol
)
10118 if (S_IS_LOCAL (exp
->X_add_symbol
)
10119 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
10120 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
10121 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
10122 exp
->X_op
= O_subtract
;
10123 exp
->X_op_symbol
= GOT_symbol
;
10124 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
10125 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
10126 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
10127 i
.reloc
[this_operand
] = BFD_RELOC_64
;
10129 i
.reloc
[this_operand
] = BFD_RELOC_32
;
10132 else if (exp
->X_op
== O_absent
10133 || exp
->X_op
== O_illegal
10134 || exp
->X_op
== O_big
)
10137 as_bad (_("missing or invalid displacement expression `%s'"),
10142 else if (flag_code
== CODE_64BIT
10143 && !i
.prefix
[ADDR_PREFIX
]
10144 && exp
->X_op
== O_constant
)
10146 /* Since displacement is signed extended to 64bit, don't allow
10147 disp32 and turn off disp32s if they are out of range. */
10148 i
.types
[this_operand
].bitfield
.disp32
= 0;
10149 if (!fits_in_signed_long (exp
->X_add_number
))
10151 i
.types
[this_operand
].bitfield
.disp32s
= 0;
10152 if (i
.types
[this_operand
].bitfield
.baseindex
)
10154 as_bad (_("0x%lx out range of signed 32bit displacement"),
10155 (long) exp
->X_add_number
);
10161 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10162 else if (exp
->X_op
!= O_constant
10163 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
10164 && exp_seg
!= absolute_section
10165 && exp_seg
!= text_section
10166 && exp_seg
!= data_section
10167 && exp_seg
!= bss_section
10168 && exp_seg
!= undefined_section
10169 && !bfd_is_com_section (exp_seg
))
10171 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
10176 if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
10177 /* Constants get taken care of by optimize_disp(). */
10178 && exp
->X_op
!= O_constant
)
10179 i
.types
[this_operand
].bitfield
.disp8
= 1;
10181 /* Check if this is a displacement only operand. */
10182 bigdisp
= i
.types
[this_operand
];
10183 bigdisp
.bitfield
.disp8
= 0;
10184 bigdisp
.bitfield
.disp16
= 0;
10185 bigdisp
.bitfield
.disp32
= 0;
10186 bigdisp
.bitfield
.disp32s
= 0;
10187 bigdisp
.bitfield
.disp64
= 0;
10188 if (operand_type_all_zero (&bigdisp
))
10189 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
10195 /* Return the active addressing mode, taking address override and
10196 registers forming the address into consideration. Update the
10197 address override prefix if necessary. */
10199 static enum flag_code
10200 i386_addressing_mode (void)
10202 enum flag_code addr_mode
;
10204 if (i
.prefix
[ADDR_PREFIX
])
10205 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
10208 addr_mode
= flag_code
;
10210 #if INFER_ADDR_PREFIX
10211 if (i
.mem_operands
== 0)
10213 /* Infer address prefix from the first memory operand. */
10214 const reg_entry
*addr_reg
= i
.base_reg
;
10216 if (addr_reg
== NULL
)
10217 addr_reg
= i
.index_reg
;
10221 if (addr_reg
->reg_type
.bitfield
.dword
)
10222 addr_mode
= CODE_32BIT
;
10223 else if (flag_code
!= CODE_64BIT
10224 && addr_reg
->reg_type
.bitfield
.word
)
10225 addr_mode
= CODE_16BIT
;
10227 if (addr_mode
!= flag_code
)
10229 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
10231 /* Change the size of any displacement too. At most one
10232 of Disp16 or Disp32 is set.
10233 FIXME. There doesn't seem to be any real need for
10234 separate Disp16 and Disp32 flags. The same goes for
10235 Imm16 and Imm32. Removing them would probably clean
10236 up the code quite a lot. */
10237 if (flag_code
!= CODE_64BIT
10238 && (i
.types
[this_operand
].bitfield
.disp16
10239 || i
.types
[this_operand
].bitfield
.disp32
))
10240 i
.types
[this_operand
]
10241 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
10251 /* Make sure the memory operand we've been dealt is valid.
10252 Return 1 on success, 0 on a failure. */
10255 i386_index_check (const char *operand_string
)
10257 const char *kind
= "base/index";
10258 enum flag_code addr_mode
= i386_addressing_mode ();
10260 if (current_templates
->start
->opcode_modifier
.isstring
10261 && !current_templates
->start
->cpu_flags
.bitfield
.cpupadlock
10262 && (current_templates
->end
[-1].opcode_modifier
.isstring
10263 || i
.mem_operands
))
10265 /* Memory operands of string insns are special in that they only allow
10266 a single register (rDI, rSI, or rBX) as their memory address. */
10267 const reg_entry
*expected_reg
;
10268 static const char *di_si
[][2] =
10274 static const char *bx
[] = { "ebx", "bx", "rbx" };
10276 kind
= "string address";
10278 if (current_templates
->start
->opcode_modifier
.repprefixok
)
10280 int es_op
= current_templates
->end
[-1].opcode_modifier
.isstring
10281 - IS_STRING_ES_OP0
;
10284 if (!current_templates
->end
[-1].operand_types
[0].bitfield
.baseindex
10285 || ((!i
.mem_operands
!= !intel_syntax
)
10286 && current_templates
->end
[-1].operand_types
[1]
10287 .bitfield
.baseindex
))
10289 expected_reg
= hash_find (reg_hash
, di_si
[addr_mode
][op
== es_op
]);
10292 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
10294 if (i
.base_reg
!= expected_reg
10296 || operand_type_check (i
.types
[this_operand
], disp
))
10298 /* The second memory operand must have the same size as
10302 && !((addr_mode
== CODE_64BIT
10303 && i
.base_reg
->reg_type
.bitfield
.qword
)
10304 || (addr_mode
== CODE_32BIT
10305 ? i
.base_reg
->reg_type
.bitfield
.dword
10306 : i
.base_reg
->reg_type
.bitfield
.word
)))
10309 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10311 intel_syntax
? '[' : '(',
10313 expected_reg
->reg_name
,
10314 intel_syntax
? ']' : ')');
10321 as_bad (_("`%s' is not a valid %s expression"),
10322 operand_string
, kind
);
10327 if (addr_mode
!= CODE_16BIT
)
10329 /* 32-bit/64-bit checks. */
10331 && ((addr_mode
== CODE_64BIT
10332 ? !i
.base_reg
->reg_type
.bitfield
.qword
10333 : !i
.base_reg
->reg_type
.bitfield
.dword
)
10334 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
10335 || i
.base_reg
->reg_num
== RegIZ
))
10337 && !i
.index_reg
->reg_type
.bitfield
.xmmword
10338 && !i
.index_reg
->reg_type
.bitfield
.ymmword
10339 && !i
.index_reg
->reg_type
.bitfield
.zmmword
10340 && ((addr_mode
== CODE_64BIT
10341 ? !i
.index_reg
->reg_type
.bitfield
.qword
10342 : !i
.index_reg
->reg_type
.bitfield
.dword
)
10343 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
10346 /* bndmk, bndldx, and bndstx have special restrictions. */
10347 if (current_templates
->start
->base_opcode
== 0xf30f1b
10348 || (current_templates
->start
->base_opcode
& ~1) == 0x0f1a)
10350 /* They cannot use RIP-relative addressing. */
10351 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
10353 as_bad (_("`%s' cannot be used here"), operand_string
);
10357 /* bndldx and bndstx ignore their scale factor. */
10358 if (current_templates
->start
->base_opcode
!= 0xf30f1b
10359 && i
.log2_scale_factor
)
10360 as_warn (_("register scaling is being ignored here"));
10365 /* 16-bit checks. */
10367 && (!i
.base_reg
->reg_type
.bitfield
.word
10368 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
10370 && (!i
.index_reg
->reg_type
.bitfield
.word
10371 || !i
.index_reg
->reg_type
.bitfield
.baseindex
10373 && i
.base_reg
->reg_num
< 6
10374 && i
.index_reg
->reg_num
>= 6
10375 && i
.log2_scale_factor
== 0))))
10382 /* Handle vector immediates. */
10385 RC_SAE_immediate (const char *imm_start
)
10387 unsigned int match_found
, j
;
10388 const char *pstr
= imm_start
;
10396 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
10398 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
10402 rc_op
.type
= RC_NamesTable
[j
].type
;
10403 rc_op
.operand
= this_operand
;
10404 i
.rounding
= &rc_op
;
10408 as_bad (_("duplicated `%s'"), imm_start
);
10411 pstr
+= RC_NamesTable
[j
].len
;
10419 if (*pstr
++ != '}')
10421 as_bad (_("Missing '}': '%s'"), imm_start
);
10424 /* RC/SAE immediate string should contain nothing more. */;
10427 as_bad (_("Junk after '}': '%s'"), imm_start
);
10431 exp
= &im_expressions
[i
.imm_operands
++];
10432 i
.op
[this_operand
].imms
= exp
;
10434 exp
->X_op
= O_constant
;
10435 exp
->X_add_number
= 0;
10436 exp
->X_add_symbol
= (symbolS
*) 0;
10437 exp
->X_op_symbol
= (symbolS
*) 0;
10439 i
.types
[this_operand
].bitfield
.imm8
= 1;
10443 /* Only string instructions can have a second memory operand, so
10444 reduce current_templates to just those if it contains any. */
10446 maybe_adjust_templates (void)
10448 const insn_template
*t
;
10450 gas_assert (i
.mem_operands
== 1);
10452 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
10453 if (t
->opcode_modifier
.isstring
)
10456 if (t
< current_templates
->end
)
10458 static templates aux_templates
;
10459 bfd_boolean recheck
;
10461 aux_templates
.start
= t
;
10462 for (; t
< current_templates
->end
; ++t
)
10463 if (!t
->opcode_modifier
.isstring
)
10465 aux_templates
.end
= t
;
10467 /* Determine whether to re-check the first memory operand. */
10468 recheck
= (aux_templates
.start
!= current_templates
->start
10469 || t
!= current_templates
->end
);
10471 current_templates
= &aux_templates
;
10475 i
.mem_operands
= 0;
10476 if (i
.memop1_string
!= NULL
10477 && i386_index_check (i
.memop1_string
) == 0)
10479 i
.mem_operands
= 1;
10486 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10490 i386_att_operand (char *operand_string
)
10492 const reg_entry
*r
;
10494 char *op_string
= operand_string
;
10496 if (is_space_char (*op_string
))
10499 /* We check for an absolute prefix (differentiating,
10500 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10501 if (*op_string
== ABSOLUTE_PREFIX
)
10504 if (is_space_char (*op_string
))
10506 i
.jumpabsolute
= TRUE
;
10509 /* Check if operand is a register. */
10510 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
10512 i386_operand_type temp
;
10514 /* Check for a segment override by searching for ':' after a
10515 segment register. */
10516 op_string
= end_op
;
10517 if (is_space_char (*op_string
))
10519 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
10521 switch (r
->reg_num
)
10524 i
.seg
[i
.mem_operands
] = &es
;
10527 i
.seg
[i
.mem_operands
] = &cs
;
10530 i
.seg
[i
.mem_operands
] = &ss
;
10533 i
.seg
[i
.mem_operands
] = &ds
;
10536 i
.seg
[i
.mem_operands
] = &fs
;
10539 i
.seg
[i
.mem_operands
] = &gs
;
10543 /* Skip the ':' and whitespace. */
10545 if (is_space_char (*op_string
))
10548 if (!is_digit_char (*op_string
)
10549 && !is_identifier_char (*op_string
)
10550 && *op_string
!= '('
10551 && *op_string
!= ABSOLUTE_PREFIX
)
10553 as_bad (_("bad memory operand `%s'"), op_string
);
10556 /* Handle case of %es:*foo. */
10557 if (*op_string
== ABSOLUTE_PREFIX
)
10560 if (is_space_char (*op_string
))
10562 i
.jumpabsolute
= TRUE
;
10564 goto do_memory_reference
;
10567 /* Handle vector operations. */
10568 if (*op_string
== '{')
10570 op_string
= check_VecOperations (op_string
, NULL
);
10571 if (op_string
== NULL
)
10577 as_bad (_("junk `%s' after register"), op_string
);
10580 temp
= r
->reg_type
;
10581 temp
.bitfield
.baseindex
= 0;
10582 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
10584 i
.types
[this_operand
].bitfield
.unspecified
= 0;
10585 i
.op
[this_operand
].regs
= r
;
10588 else if (*op_string
== REGISTER_PREFIX
)
10590 as_bad (_("bad register name `%s'"), op_string
);
10593 else if (*op_string
== IMMEDIATE_PREFIX
)
10596 if (i
.jumpabsolute
)
10598 as_bad (_("immediate operand illegal with absolute jump"));
10601 if (!i386_immediate (op_string
))
10604 else if (RC_SAE_immediate (operand_string
))
10606 /* If it is a RC or SAE immediate, do nothing. */
10609 else if (is_digit_char (*op_string
)
10610 || is_identifier_char (*op_string
)
10611 || *op_string
== '"'
10612 || *op_string
== '(')
10614 /* This is a memory reference of some sort. */
10617 /* Start and end of displacement string expression (if found). */
10618 char *displacement_string_start
;
10619 char *displacement_string_end
;
10622 do_memory_reference
:
10623 if (i
.mem_operands
== 1 && !maybe_adjust_templates ())
10625 if ((i
.mem_operands
== 1
10626 && !current_templates
->start
->opcode_modifier
.isstring
)
10627 || i
.mem_operands
== 2)
10629 as_bad (_("too many memory references for `%s'"),
10630 current_templates
->start
->name
);
10634 /* Check for base index form. We detect the base index form by
10635 looking for an ')' at the end of the operand, searching
10636 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10638 base_string
= op_string
+ strlen (op_string
);
10640 /* Handle vector operations. */
10641 vop_start
= strchr (op_string
, '{');
10642 if (vop_start
&& vop_start
< base_string
)
10644 if (check_VecOperations (vop_start
, base_string
) == NULL
)
10646 base_string
= vop_start
;
10650 if (is_space_char (*base_string
))
10653 /* If we only have a displacement, set-up for it to be parsed later. */
10654 displacement_string_start
= op_string
;
10655 displacement_string_end
= base_string
+ 1;
10657 if (*base_string
== ')')
10660 unsigned int parens_balanced
= 1;
10661 /* We've already checked that the number of left & right ()'s are
10662 equal, so this loop will not be infinite. */
10666 if (*base_string
== ')')
10668 if (*base_string
== '(')
10671 while (parens_balanced
);
10673 temp_string
= base_string
;
10675 /* Skip past '(' and whitespace. */
10677 if (is_space_char (*base_string
))
10680 if (*base_string
== ','
10681 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
10684 displacement_string_end
= temp_string
;
10686 i
.types
[this_operand
].bitfield
.baseindex
= 1;
10690 base_string
= end_op
;
10691 if (is_space_char (*base_string
))
10695 /* There may be an index reg or scale factor here. */
10696 if (*base_string
== ',')
10699 if (is_space_char (*base_string
))
10702 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
10705 base_string
= end_op
;
10706 if (is_space_char (*base_string
))
10708 if (*base_string
== ',')
10711 if (is_space_char (*base_string
))
10714 else if (*base_string
!= ')')
10716 as_bad (_("expecting `,' or `)' "
10717 "after index register in `%s'"),
10722 else if (*base_string
== REGISTER_PREFIX
)
10724 end_op
= strchr (base_string
, ',');
10727 as_bad (_("bad register name `%s'"), base_string
);
10731 /* Check for scale factor. */
10732 if (*base_string
!= ')')
10734 char *end_scale
= i386_scale (base_string
);
10739 base_string
= end_scale
;
10740 if (is_space_char (*base_string
))
10742 if (*base_string
!= ')')
10744 as_bad (_("expecting `)' "
10745 "after scale factor in `%s'"),
10750 else if (!i
.index_reg
)
10752 as_bad (_("expecting index register or scale factor "
10753 "after `,'; got '%c'"),
10758 else if (*base_string
!= ')')
10760 as_bad (_("expecting `,' or `)' "
10761 "after base register in `%s'"),
10766 else if (*base_string
== REGISTER_PREFIX
)
10768 end_op
= strchr (base_string
, ',');
10771 as_bad (_("bad register name `%s'"), base_string
);
10776 /* If there's an expression beginning the operand, parse it,
10777 assuming displacement_string_start and
10778 displacement_string_end are meaningful. */
10779 if (displacement_string_start
!= displacement_string_end
)
10781 if (!i386_displacement (displacement_string_start
,
10782 displacement_string_end
))
10786 /* Special case for (%dx) while doing input/output op. */
10788 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
10789 && i
.base_reg
->reg_type
.bitfield
.word
10790 && i
.index_reg
== 0
10791 && i
.log2_scale_factor
== 0
10792 && i
.seg
[i
.mem_operands
] == 0
10793 && !operand_type_check (i
.types
[this_operand
], disp
))
10795 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
10799 if (i386_index_check (operand_string
) == 0)
10801 i
.flags
[this_operand
] |= Operand_Mem
;
10802 if (i
.mem_operands
== 0)
10803 i
.memop1_string
= xstrdup (operand_string
);
10808 /* It's not a memory operand; argh! */
10809 as_bad (_("invalid char %s beginning operand %d `%s'"),
10810 output_invalid (*op_string
),
10815 return 1; /* Normal return. */
10818 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10819 that an rs_machine_dependent frag may reach. */
10822 i386_frag_max_var (fragS
*frag
)
10824 /* The only relaxable frags are for jumps.
10825 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10826 gas_assert (frag
->fr_type
== rs_machine_dependent
);
10827 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
10830 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10832 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
10834 /* STT_GNU_IFUNC symbol must go through PLT. */
10835 if ((symbol_get_bfdsym (fr_symbol
)->flags
10836 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
10839 if (!S_IS_EXTERNAL (fr_symbol
))
10840 /* Symbol may be weak or local. */
10841 return !S_IS_WEAK (fr_symbol
);
10843 /* Global symbols with non-default visibility can't be preempted. */
10844 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
10847 if (fr_var
!= NO_RELOC
)
10848 switch ((enum bfd_reloc_code_real
) fr_var
)
10850 case BFD_RELOC_386_PLT32
:
10851 case BFD_RELOC_X86_64_PLT32
:
10852 /* Symbol with PLT relocation may be preempted. */
10858 /* Global symbols with default visibility in a shared library may be
10859 preempted by another definition. */
10864 /* Return the next non-empty frag. */
10867 i386_next_non_empty_frag (fragS
*fragP
)
10869 /* There may be a frag with a ".fill 0" when there is no room in
10870 the current frag for frag_grow in output_insn. */
10871 for (fragP
= fragP
->fr_next
;
10873 && fragP
->fr_type
== rs_fill
10874 && fragP
->fr_fix
== 0);
10875 fragP
= fragP
->fr_next
)
10880 /* Return the next jcc frag after BRANCH_PADDING. */
10883 i386_next_jcc_frag (fragS
*fragP
)
10888 if (fragP
->fr_type
== rs_machine_dependent
10889 && (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10890 == BRANCH_PADDING
))
10892 fragP
= i386_next_non_empty_frag (fragP
);
10893 if (fragP
->fr_type
!= rs_machine_dependent
)
10895 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == COND_JUMP
)
10902 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
10905 i386_classify_machine_dependent_frag (fragS
*fragP
)
10909 fragS
*branch_fragP
;
10911 unsigned int max_prefix_length
;
10913 if (fragP
->tc_frag_data
.classified
)
10916 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
10917 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
10918 for (next_fragP
= fragP
;
10919 next_fragP
!= NULL
;
10920 next_fragP
= next_fragP
->fr_next
)
10922 next_fragP
->tc_frag_data
.classified
= 1;
10923 if (next_fragP
->fr_type
== rs_machine_dependent
)
10924 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
10926 case BRANCH_PADDING
:
10927 /* The BRANCH_PADDING frag must be followed by a branch
10929 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
10930 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10932 case FUSED_JCC_PADDING
:
10933 /* Check if this is a fused jcc:
10935 CMP like instruction
10939 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
10940 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
10941 branch_fragP
= i386_next_jcc_frag (pad_fragP
);
10944 /* The BRANCH_PADDING frag is merged with the
10945 FUSED_JCC_PADDING frag. */
10946 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
10947 /* CMP like instruction size. */
10948 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
10949 frag_wane (pad_fragP
);
10950 /* Skip to branch_fragP. */
10951 next_fragP
= branch_fragP
;
10953 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
10955 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
10957 next_fragP
->fr_subtype
10958 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
10959 next_fragP
->tc_frag_data
.max_bytes
10960 = next_fragP
->tc_frag_data
.max_prefix_length
;
10961 /* This will be updated in the BRANCH_PREFIX scan. */
10962 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
10965 frag_wane (next_fragP
);
10970 /* Stop if there is no BRANCH_PREFIX. */
10971 if (!align_branch_prefix_size
)
10974 /* Scan for BRANCH_PREFIX. */
10975 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
10977 if (fragP
->fr_type
!= rs_machine_dependent
10978 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10982 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
10983 COND_JUMP_PREFIX. */
10984 max_prefix_length
= 0;
10985 for (next_fragP
= fragP
;
10986 next_fragP
!= NULL
;
10987 next_fragP
= next_fragP
->fr_next
)
10989 if (next_fragP
->fr_type
== rs_fill
)
10990 /* Skip rs_fill frags. */
10992 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
10993 /* Stop for all other frags. */
10996 /* rs_machine_dependent frags. */
10997 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11000 /* Count BRANCH_PREFIX frags. */
11001 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
11003 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
11004 frag_wane (next_fragP
);
11008 += next_fragP
->tc_frag_data
.max_bytes
;
11010 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11012 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11013 == FUSED_JCC_PADDING
))
11015 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11016 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
11020 /* Stop for other rs_machine_dependent frags. */
11024 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
11026 /* Skip to the next frag. */
11027 fragP
= next_fragP
;
11031 /* Compute padding size for
11034 CMP like instruction
11036 COND_JUMP/UNCOND_JUMP
11041 COND_JUMP/UNCOND_JUMP
11045 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
11047 unsigned int offset
, size
, padding_size
;
11048 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
11050 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11052 address
= fragP
->fr_address
;
11053 address
+= fragP
->fr_fix
;
11055 /* CMP like instrunction size. */
11056 size
= fragP
->tc_frag_data
.cmp_size
;
11058 /* The base size of the branch frag. */
11059 size
+= branch_fragP
->fr_fix
;
11061 /* Add opcode and displacement bytes for the rs_machine_dependent
11063 if (branch_fragP
->fr_type
== rs_machine_dependent
)
11064 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
11066 /* Check if branch is within boundary and doesn't end at the last
11068 offset
= address
& ((1U << align_branch_power
) - 1);
11069 if ((offset
+ size
) >= (1U << align_branch_power
))
11070 /* Padding needed to avoid crossing boundary. */
11071 padding_size
= (1U << align_branch_power
) - offset
;
11073 /* No padding needed. */
11076 /* The return value may be saved in tc_frag_data.length which is
11078 if (!fits_in_unsigned_byte (padding_size
))
11081 return padding_size
;
11084 /* i386_generic_table_relax_frag()
11086 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11087 grow/shrink padding to align branch frags. Hand others to
11091 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
11093 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11094 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11096 long padding_size
= i386_branch_padding_size (fragP
, 0);
11097 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
11099 /* When the BRANCH_PREFIX frag is used, the computed address
11100 must match the actual address and there should be no padding. */
11101 if (fragP
->tc_frag_data
.padding_address
11102 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
11106 /* Update the padding size. */
11108 fragP
->tc_frag_data
.length
= padding_size
;
11112 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11114 fragS
*padding_fragP
, *next_fragP
;
11115 long padding_size
, left_size
, last_size
;
11117 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11118 if (!padding_fragP
)
11119 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11120 return (fragP
->tc_frag_data
.length
11121 - fragP
->tc_frag_data
.last_length
);
11123 /* Compute the relative address of the padding frag in the very
11124 first time where the BRANCH_PREFIX frag sizes are zero. */
11125 if (!fragP
->tc_frag_data
.padding_address
)
11126 fragP
->tc_frag_data
.padding_address
11127 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
11129 /* First update the last length from the previous interation. */
11130 left_size
= fragP
->tc_frag_data
.prefix_length
;
11131 for (next_fragP
= fragP
;
11132 next_fragP
!= padding_fragP
;
11133 next_fragP
= next_fragP
->fr_next
)
11134 if (next_fragP
->fr_type
== rs_machine_dependent
11135 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11140 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11144 if (max
> left_size
)
11149 next_fragP
->tc_frag_data
.last_length
= size
;
11153 next_fragP
->tc_frag_data
.last_length
= 0;
11156 /* Check the padding size for the padding frag. */
11157 padding_size
= i386_branch_padding_size
11158 (padding_fragP
, (fragP
->fr_address
11159 + fragP
->tc_frag_data
.padding_address
));
11161 last_size
= fragP
->tc_frag_data
.prefix_length
;
11162 /* Check if there is change from the last interation. */
11163 if (padding_size
== last_size
)
11165 /* Update the expected address of the padding frag. */
11166 padding_fragP
->tc_frag_data
.padding_address
11167 = (fragP
->fr_address
+ padding_size
11168 + fragP
->tc_frag_data
.padding_address
);
11172 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
11174 /* No padding if there is no sufficient room. Clear the
11175 expected address of the padding frag. */
11176 padding_fragP
->tc_frag_data
.padding_address
= 0;
11180 /* Store the expected address of the padding frag. */
11181 padding_fragP
->tc_frag_data
.padding_address
11182 = (fragP
->fr_address
+ padding_size
11183 + fragP
->tc_frag_data
.padding_address
);
11185 fragP
->tc_frag_data
.prefix_length
= padding_size
;
11187 /* Update the length for the current interation. */
11188 left_size
= padding_size
;
11189 for (next_fragP
= fragP
;
11190 next_fragP
!= padding_fragP
;
11191 next_fragP
= next_fragP
->fr_next
)
11192 if (next_fragP
->fr_type
== rs_machine_dependent
11193 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
11198 int max
= next_fragP
->tc_frag_data
.max_bytes
;
11202 if (max
> left_size
)
11207 next_fragP
->tc_frag_data
.length
= size
;
11211 next_fragP
->tc_frag_data
.length
= 0;
11214 return (fragP
->tc_frag_data
.length
11215 - fragP
->tc_frag_data
.last_length
);
11217 return relax_frag (segment
, fragP
, stretch
);
11220 /* md_estimate_size_before_relax()
11222 Called just before relax() for rs_machine_dependent frags. The x86
11223 assembler uses these frags to handle variable size jump
11226 Any symbol that is now undefined will not become defined.
11227 Return the correct fr_subtype in the frag.
11228 Return the initial "guess for variable size of frag" to caller.
11229 The guess is actually the growth beyond the fixed part. Whatever
11230 we do to grow the fixed or variable part contributes to our
11234 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
11236 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11237 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
11238 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
11240 i386_classify_machine_dependent_frag (fragP
);
11241 return fragP
->tc_frag_data
.length
;
11244 /* We've already got fragP->fr_subtype right; all we have to do is
11245 check for un-relaxable symbols. On an ELF system, we can't relax
11246 an externally visible symbol, because it may be overridden by a
11248 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
11249 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11251 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
11254 #if defined (OBJ_COFF) && defined (TE_PE)
11255 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
11256 && S_IS_WEAK (fragP
->fr_symbol
))
11260 /* Symbol is undefined in this segment, or we need to keep a
11261 reloc so that weak symbols can be overridden. */
11262 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
11263 enum bfd_reloc_code_real reloc_type
;
11264 unsigned char *opcode
;
11267 if (fragP
->fr_var
!= NO_RELOC
)
11268 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
11269 else if (size
== 2)
11270 reloc_type
= BFD_RELOC_16_PCREL
;
11271 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11272 else if (need_plt32_p (fragP
->fr_symbol
))
11273 reloc_type
= BFD_RELOC_X86_64_PLT32
;
11276 reloc_type
= BFD_RELOC_32_PCREL
;
11278 old_fr_fix
= fragP
->fr_fix
;
11279 opcode
= (unsigned char *) fragP
->fr_opcode
;
11281 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
11284 /* Make jmp (0xeb) a (d)word displacement jump. */
11286 fragP
->fr_fix
+= size
;
11287 fix_new (fragP
, old_fr_fix
, size
,
11289 fragP
->fr_offset
, 1,
11295 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
11297 /* Negate the condition, and branch past an
11298 unconditional jump. */
11301 /* Insert an unconditional jump. */
11303 /* We added two extra opcode bytes, and have a two byte
11305 fragP
->fr_fix
+= 2 + 2;
11306 fix_new (fragP
, old_fr_fix
+ 2, 2,
11308 fragP
->fr_offset
, 1,
11312 /* Fall through. */
11315 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
11319 fragP
->fr_fix
+= 1;
11320 fixP
= fix_new (fragP
, old_fr_fix
, 1,
11322 fragP
->fr_offset
, 1,
11323 BFD_RELOC_8_PCREL
);
11324 fixP
->fx_signed
= 1;
11328 /* This changes the byte-displacement jump 0x7N
11329 to the (d)word-displacement jump 0x0f,0x8N. */
11330 opcode
[1] = opcode
[0] + 0x10;
11331 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11332 /* We've added an opcode byte. */
11333 fragP
->fr_fix
+= 1 + size
;
11334 fix_new (fragP
, old_fr_fix
+ 1, size
,
11336 fragP
->fr_offset
, 1,
11341 BAD_CASE (fragP
->fr_subtype
);
11345 return fragP
->fr_fix
- old_fr_fix
;
11348 /* Guess size depending on current relax state. Initially the relax
11349 state will correspond to a short jump and we return 1, because
11350 the variable part of the frag (the branch offset) is one byte
11351 long. However, we can relax a section more than once and in that
11352 case we must either set fr_subtype back to the unrelaxed state,
11353 or return the value for the appropriate branch. */
11354 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
11357 /* Called after relax() is finished.
11359 In: Address of frag.
11360 fr_type == rs_machine_dependent.
11361 fr_subtype is what the address relaxed to.
11363 Out: Any fixSs and constants are set up.
11364 Caller will turn frag into a ".space 0". */
11367 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
11370 unsigned char *opcode
;
11371 unsigned char *where_to_put_displacement
= NULL
;
11372 offsetT target_address
;
11373 offsetT opcode_address
;
11374 unsigned int extension
= 0;
11375 offsetT displacement_from_opcode_start
;
11377 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
11378 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
11379 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11381 /* Generate nop padding. */
11382 unsigned int size
= fragP
->tc_frag_data
.length
;
11385 if (size
> fragP
->tc_frag_data
.max_bytes
)
11391 const char *branch
= "branch";
11392 const char *prefix
= "";
11393 fragS
*padding_fragP
;
11394 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
11397 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
11398 switch (fragP
->tc_frag_data
.default_prefix
)
11403 case CS_PREFIX_OPCODE
:
11406 case DS_PREFIX_OPCODE
:
11409 case ES_PREFIX_OPCODE
:
11412 case FS_PREFIX_OPCODE
:
11415 case GS_PREFIX_OPCODE
:
11418 case SS_PREFIX_OPCODE
:
11423 msg
= _("%s:%u: add %d%s at 0x%llx to align "
11424 "%s within %d-byte boundary\n");
11426 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
11427 "align %s within %d-byte boundary\n");
11431 padding_fragP
= fragP
;
11432 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
11433 "%s within %d-byte boundary\n");
11437 switch (padding_fragP
->tc_frag_data
.branch_type
)
11439 case align_branch_jcc
:
11442 case align_branch_fused
:
11443 branch
= "fused jcc";
11445 case align_branch_jmp
:
11448 case align_branch_call
:
11451 case align_branch_indirect
:
11452 branch
= "indiret branch";
11454 case align_branch_ret
:
11461 fprintf (stdout
, msg
,
11462 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
11463 (long long) fragP
->fr_address
, branch
,
11464 1 << align_branch_power
);
11466 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
11467 memset (fragP
->fr_opcode
,
11468 fragP
->tc_frag_data
.default_prefix
, size
);
11470 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
11472 fragP
->fr_fix
+= size
;
11477 opcode
= (unsigned char *) fragP
->fr_opcode
;
11479 /* Address we want to reach in file space. */
11480 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
11482 /* Address opcode resides at in file space. */
11483 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
11485 /* Displacement from opcode start to fill into instruction. */
11486 displacement_from_opcode_start
= target_address
- opcode_address
;
11488 if ((fragP
->fr_subtype
& BIG
) == 0)
11490 /* Don't have to change opcode. */
11491 extension
= 1; /* 1 opcode + 1 displacement */
11492 where_to_put_displacement
= &opcode
[1];
11496 if (no_cond_jump_promotion
11497 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
11498 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
11499 _("long jump required"));
11501 switch (fragP
->fr_subtype
)
11503 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
11504 extension
= 4; /* 1 opcode + 4 displacement */
11506 where_to_put_displacement
= &opcode
[1];
11509 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
11510 extension
= 2; /* 1 opcode + 2 displacement */
11512 where_to_put_displacement
= &opcode
[1];
11515 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
11516 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
11517 extension
= 5; /* 2 opcode + 4 displacement */
11518 opcode
[1] = opcode
[0] + 0x10;
11519 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11520 where_to_put_displacement
= &opcode
[2];
11523 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
11524 extension
= 3; /* 2 opcode + 2 displacement */
11525 opcode
[1] = opcode
[0] + 0x10;
11526 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
11527 where_to_put_displacement
= &opcode
[2];
11530 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
11535 where_to_put_displacement
= &opcode
[3];
11539 BAD_CASE (fragP
->fr_subtype
);
11544 /* If size if less then four we are sure that the operand fits,
11545 but if it's 4, then it could be that the displacement is larger
11547 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
11549 && ((addressT
) (displacement_from_opcode_start
- extension
11550 + ((addressT
) 1 << 31))
11551 > (((addressT
) 2 << 31) - 1)))
11553 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11554 _("jump target out of range"));
11555 /* Make us emit 0. */
11556 displacement_from_opcode_start
= extension
;
11558 /* Now put displacement after opcode. */
11559 md_number_to_chars ((char *) where_to_put_displacement
,
11560 (valueT
) (displacement_from_opcode_start
- extension
),
11561 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
11562 fragP
->fr_fix
+= extension
;
11565 /* Apply a fixup (fixP) to segment data, once it has been determined
11566 by our caller that we have all the info we need to fix it up.
11568 Parameter valP is the pointer to the value of the bits.
11570 On the 386, immediates, displacements, and data pointers are all in
11571 the same (little-endian) format, so we don't need to care about which
11572 we are handling. */
11575 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11577 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
11578 valueT value
= *valP
;
11580 #if !defined (TE_Mach)
11581 if (fixP
->fx_pcrel
)
11583 switch (fixP
->fx_r_type
)
11589 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
11592 case BFD_RELOC_X86_64_32S
:
11593 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
11596 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
11599 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
11604 if (fixP
->fx_addsy
!= NULL
11605 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
11606 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
11607 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
11608 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
11609 && !use_rela_relocations
)
11611 /* This is a hack. There should be a better way to handle this.
11612 This covers for the fact that bfd_install_relocation will
11613 subtract the current location (for partial_inplace, PC relative
11614 relocations); see more below. */
11618 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
11621 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11623 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11626 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
11628 if ((sym_seg
== seg
11629 || (symbol_section_p (fixP
->fx_addsy
)
11630 && sym_seg
!= absolute_section
))
11631 && !generic_force_reloc (fixP
))
11633 /* Yes, we add the values in twice. This is because
11634 bfd_install_relocation subtracts them out again. I think
11635 bfd_install_relocation is broken, but I don't dare change
11637 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11641 #if defined (OBJ_COFF) && defined (TE_PE)
11642 /* For some reason, the PE format does not store a
11643 section address offset for a PC relative symbol. */
11644 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
11645 || S_IS_WEAK (fixP
->fx_addsy
))
11646 value
+= md_pcrel_from (fixP
);
11649 #if defined (OBJ_COFF) && defined (TE_PE)
11650 if (fixP
->fx_addsy
!= NULL
11651 && S_IS_WEAK (fixP
->fx_addsy
)
11652 /* PR 16858: Do not modify weak function references. */
11653 && ! fixP
->fx_pcrel
)
11655 #if !defined (TE_PEP)
11656 /* For x86 PE weak function symbols are neither PC-relative
11657 nor do they set S_IS_FUNCTION. So the only reliable way
11658 to detect them is to check the flags of their containing
11660 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
11661 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
11665 value
-= S_GET_VALUE (fixP
->fx_addsy
);
11669 /* Fix a few things - the dynamic linker expects certain values here,
11670 and we must not disappoint it. */
11671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11672 if (IS_ELF
&& fixP
->fx_addsy
)
11673 switch (fixP
->fx_r_type
)
11675 case BFD_RELOC_386_PLT32
:
11676 case BFD_RELOC_X86_64_PLT32
:
11677 /* Make the jump instruction point to the address of the operand.
11678 At runtime we merely add the offset to the actual PLT entry.
11679 NB: Subtract the offset size only for jump instructions. */
11680 if (fixP
->fx_pcrel
)
11684 case BFD_RELOC_386_TLS_GD
:
11685 case BFD_RELOC_386_TLS_LDM
:
11686 case BFD_RELOC_386_TLS_IE_32
:
11687 case BFD_RELOC_386_TLS_IE
:
11688 case BFD_RELOC_386_TLS_GOTIE
:
11689 case BFD_RELOC_386_TLS_GOTDESC
:
11690 case BFD_RELOC_X86_64_TLSGD
:
11691 case BFD_RELOC_X86_64_TLSLD
:
11692 case BFD_RELOC_X86_64_GOTTPOFF
:
11693 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
11694 value
= 0; /* Fully resolved at runtime. No addend. */
11696 case BFD_RELOC_386_TLS_LE
:
11697 case BFD_RELOC_386_TLS_LDO_32
:
11698 case BFD_RELOC_386_TLS_LE_32
:
11699 case BFD_RELOC_X86_64_DTPOFF32
:
11700 case BFD_RELOC_X86_64_DTPOFF64
:
11701 case BFD_RELOC_X86_64_TPOFF32
:
11702 case BFD_RELOC_X86_64_TPOFF64
:
11703 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11706 case BFD_RELOC_386_TLS_DESC_CALL
:
11707 case BFD_RELOC_X86_64_TLSDESC_CALL
:
11708 value
= 0; /* Fully resolved at runtime. No addend. */
11709 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11713 case BFD_RELOC_VTABLE_INHERIT
:
11714 case BFD_RELOC_VTABLE_ENTRY
:
11721 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
11723 #endif /* !defined (TE_Mach) */
11725 /* Are we finished with this relocation now? */
11726 if (fixP
->fx_addsy
== NULL
)
11728 #if defined (OBJ_COFF) && defined (TE_PE)
11729 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
11732 /* Remember value for tc_gen_reloc. */
11733 fixP
->fx_addnumber
= value
;
11734 /* Clear out the frag for now. */
11738 else if (use_rela_relocations
)
11740 fixP
->fx_no_overflow
= 1;
11741 /* Remember value for tc_gen_reloc. */
11742 fixP
->fx_addnumber
= value
;
11746 md_number_to_chars (p
, value
, fixP
->fx_size
);
11750 md_atof (int type
, char *litP
, int *sizeP
)
11752 /* This outputs the LITTLENUMs in REVERSE order;
11753 in accord with the bigendian 386. */
11754 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
11757 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
11760 output_invalid (int c
)
11763 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11766 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
11767 "(0x%x)", (unsigned char) c
);
11768 return output_invalid_buf
;
11771 /* REG_STRING starts *before* REGISTER_PREFIX. */
11773 static const reg_entry
*
11774 parse_real_register (char *reg_string
, char **end_op
)
11776 char *s
= reg_string
;
11778 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
11779 const reg_entry
*r
;
11781 /* Skip possible REGISTER_PREFIX and possible whitespace. */
11782 if (*s
== REGISTER_PREFIX
)
11785 if (is_space_char (*s
))
11788 p
= reg_name_given
;
11789 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
11791 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
11792 return (const reg_entry
*) NULL
;
11796 /* For naked regs, make sure that we are not dealing with an identifier.
11797 This prevents confusing an identifier like `eax_var' with register
11799 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
11800 return (const reg_entry
*) NULL
;
11804 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
11806 /* Handle floating point regs, allowing spaces in the (i) part. */
11807 if (r
== i386_regtab
/* %st is first entry of table */)
11809 if (!cpu_arch_flags
.bitfield
.cpu8087
11810 && !cpu_arch_flags
.bitfield
.cpu287
11811 && !cpu_arch_flags
.bitfield
.cpu387
)
11812 return (const reg_entry
*) NULL
;
11814 if (is_space_char (*s
))
11819 if (is_space_char (*s
))
11821 if (*s
>= '0' && *s
<= '7')
11823 int fpr
= *s
- '0';
11825 if (is_space_char (*s
))
11830 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
11835 /* We have "%st(" then garbage. */
11836 return (const reg_entry
*) NULL
;
11840 if (r
== NULL
|| allow_pseudo_reg
)
11843 if (operand_type_all_zero (&r
->reg_type
))
11844 return (const reg_entry
*) NULL
;
11846 if ((r
->reg_type
.bitfield
.dword
11847 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
11848 || r
->reg_type
.bitfield
.class == RegCR
11849 || r
->reg_type
.bitfield
.class == RegDR
11850 || r
->reg_type
.bitfield
.class == RegTR
)
11851 && !cpu_arch_flags
.bitfield
.cpui386
)
11852 return (const reg_entry
*) NULL
;
11854 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
11855 return (const reg_entry
*) NULL
;
11857 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
11859 if (r
->reg_type
.bitfield
.zmmword
11860 || r
->reg_type
.bitfield
.class == RegMask
)
11861 return (const reg_entry
*) NULL
;
11863 if (!cpu_arch_flags
.bitfield
.cpuavx
)
11865 if (r
->reg_type
.bitfield
.ymmword
)
11866 return (const reg_entry
*) NULL
;
11868 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
11869 return (const reg_entry
*) NULL
;
11873 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
11874 return (const reg_entry
*) NULL
;
11876 /* Don't allow fake index register unless allow_index_reg isn't 0. */
11877 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
11878 return (const reg_entry
*) NULL
;
11880 /* Upper 16 vector registers are only available with VREX in 64bit
11881 mode, and require EVEX encoding. */
11882 if (r
->reg_flags
& RegVRex
)
11884 if (!cpu_arch_flags
.bitfield
.cpuavx512f
11885 || flag_code
!= CODE_64BIT
)
11886 return (const reg_entry
*) NULL
;
11888 i
.vec_encoding
= vex_encoding_evex
;
11891 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
11892 && (!cpu_arch_flags
.bitfield
.cpulm
|| r
->reg_type
.bitfield
.class != RegCR
)
11893 && flag_code
!= CODE_64BIT
)
11894 return (const reg_entry
*) NULL
;
11896 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
11898 return (const reg_entry
*) NULL
;
11903 /* REG_STRING starts *before* REGISTER_PREFIX. */
11905 static const reg_entry
*
11906 parse_register (char *reg_string
, char **end_op
)
11908 const reg_entry
*r
;
11910 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
11911 r
= parse_real_register (reg_string
, end_op
);
11916 char *save
= input_line_pointer
;
11920 input_line_pointer
= reg_string
;
11921 c
= get_symbol_name (®_string
);
11922 symbolP
= symbol_find (reg_string
);
11923 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
11925 const expressionS
*e
= symbol_get_value_expression (symbolP
);
11927 know (e
->X_op
== O_register
);
11928 know (e
->X_add_number
>= 0
11929 && (valueT
) e
->X_add_number
< i386_regtab_size
);
11930 r
= i386_regtab
+ e
->X_add_number
;
11931 if ((r
->reg_flags
& RegVRex
))
11932 i
.vec_encoding
= vex_encoding_evex
;
11933 *end_op
= input_line_pointer
;
11935 *input_line_pointer
= c
;
11936 input_line_pointer
= save
;
11942 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
11944 const reg_entry
*r
;
11945 char *end
= input_line_pointer
;
11948 r
= parse_register (name
, &input_line_pointer
);
11949 if (r
&& end
<= input_line_pointer
)
11951 *nextcharP
= *input_line_pointer
;
11952 *input_line_pointer
= 0;
11953 e
->X_op
= O_register
;
11954 e
->X_add_number
= r
- i386_regtab
;
11957 input_line_pointer
= end
;
11959 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
11963 md_operand (expressionS
*e
)
11966 const reg_entry
*r
;
11968 switch (*input_line_pointer
)
11970 case REGISTER_PREFIX
:
11971 r
= parse_real_register (input_line_pointer
, &end
);
11974 e
->X_op
= O_register
;
11975 e
->X_add_number
= r
- i386_regtab
;
11976 input_line_pointer
= end
;
11981 gas_assert (intel_syntax
);
11982 end
= input_line_pointer
++;
11984 if (*input_line_pointer
== ']')
11986 ++input_line_pointer
;
11987 e
->X_op_symbol
= make_expr_symbol (e
);
11988 e
->X_add_symbol
= NULL
;
11989 e
->X_add_number
= 0;
11994 e
->X_op
= O_absent
;
11995 input_line_pointer
= end
;
12002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12003 const char *md_shortopts
= "kVQ:sqnO::";
12005 const char *md_shortopts
= "qnO::";
12008 #define OPTION_32 (OPTION_MD_BASE + 0)
12009 #define OPTION_64 (OPTION_MD_BASE + 1)
12010 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12011 #define OPTION_MARCH (OPTION_MD_BASE + 3)
12012 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
12013 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12014 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12015 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12016 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12017 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12018 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12019 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12020 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12021 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12022 #define OPTION_X32 (OPTION_MD_BASE + 14)
12023 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12024 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12025 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12026 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12027 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12028 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12029 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
12030 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12031 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12032 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12033 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12034 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12035 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12036 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12037 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12038 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12040 struct option md_longopts
[] =
12042 {"32", no_argument
, NULL
, OPTION_32
},
12043 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12044 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12045 {"64", no_argument
, NULL
, OPTION_64
},
12047 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12048 {"x32", no_argument
, NULL
, OPTION_X32
},
12049 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
12050 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
12052 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
12053 {"march", required_argument
, NULL
, OPTION_MARCH
},
12054 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
12055 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
12056 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
12057 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
12058 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
12059 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
12060 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
12061 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
12062 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
12063 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
12064 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
12065 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
12066 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
12067 # if defined (TE_PE) || defined (TE_PEP)
12068 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
12070 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
12071 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
12072 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
12073 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
12074 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
12075 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
12076 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
12077 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
12078 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
12079 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
12080 {NULL
, no_argument
, NULL
, 0}
12082 size_t md_longopts_size
= sizeof (md_longopts
);
12085 md_parse_option (int c
, const char *arg
)
12088 char *arch
, *next
, *saved
, *type
;
12093 optimize_align_code
= 0;
12097 quiet_warnings
= 1;
12100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12101 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12102 should be emitted or not. FIXME: Not implemented. */
12104 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
12108 /* -V: SVR4 argument to print version ID. */
12110 print_version_id ();
12113 /* -k: Ignore for FreeBSD compatibility. */
12118 /* -s: On i386 Solaris, this tells the native assembler to use
12119 .stab instead of .stab.excl. We always use .stab anyhow. */
12122 case OPTION_MSHARED
:
12126 case OPTION_X86_USED_NOTE
:
12127 if (strcasecmp (arg
, "yes") == 0)
12129 else if (strcasecmp (arg
, "no") == 0)
12132 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
12137 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12138 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12141 const char **list
, **l
;
12143 list
= bfd_target_list ();
12144 for (l
= list
; *l
!= NULL
; l
++)
12145 if (CONST_STRNEQ (*l
, "elf64-x86-64")
12146 || strcmp (*l
, "coff-x86-64") == 0
12147 || strcmp (*l
, "pe-x86-64") == 0
12148 || strcmp (*l
, "pei-x86-64") == 0
12149 || strcmp (*l
, "mach-o-x86-64") == 0)
12151 default_arch
= "x86_64";
12155 as_fatal (_("no compiled in support for x86_64"));
12161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12165 const char **list
, **l
;
12167 list
= bfd_target_list ();
12168 for (l
= list
; *l
!= NULL
; l
++)
12169 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
12171 default_arch
= "x86_64:32";
12175 as_fatal (_("no compiled in support for 32bit x86_64"));
12179 as_fatal (_("32bit x86_64 is only supported for ELF"));
12184 default_arch
= "i386";
12187 case OPTION_DIVIDE
:
12188 #ifdef SVR4_COMMENT_CHARS
12193 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
12195 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
12199 i386_comment_chars
= n
;
12205 saved
= xstrdup (arg
);
12207 /* Allow -march=+nosse. */
12213 as_fatal (_("invalid -march= option: `%s'"), arg
);
12214 next
= strchr (arch
, '+');
12217 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12219 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
12222 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12225 cpu_arch_name
= cpu_arch
[j
].name
;
12226 cpu_sub_arch_name
= NULL
;
12227 cpu_arch_flags
= cpu_arch
[j
].flags
;
12228 cpu_arch_isa
= cpu_arch
[j
].type
;
12229 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
12230 if (!cpu_arch_tune_set
)
12232 cpu_arch_tune
= cpu_arch_isa
;
12233 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12237 else if (*cpu_arch
[j
].name
== '.'
12238 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
12240 /* ISA extension. */
12241 i386_cpu_flags flags
;
12243 flags
= cpu_flags_or (cpu_arch_flags
,
12244 cpu_arch
[j
].flags
);
12246 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12248 if (cpu_sub_arch_name
)
12250 char *name
= cpu_sub_arch_name
;
12251 cpu_sub_arch_name
= concat (name
,
12253 (const char *) NULL
);
12257 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
12258 cpu_arch_flags
= flags
;
12259 cpu_arch_isa_flags
= flags
;
12263 = cpu_flags_or (cpu_arch_isa_flags
,
12264 cpu_arch
[j
].flags
);
12269 if (j
>= ARRAY_SIZE (cpu_arch
))
12271 /* Disable an ISA extension. */
12272 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12273 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
12275 i386_cpu_flags flags
;
12277 flags
= cpu_flags_and_not (cpu_arch_flags
,
12278 cpu_noarch
[j
].flags
);
12279 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
12281 if (cpu_sub_arch_name
)
12283 char *name
= cpu_sub_arch_name
;
12284 cpu_sub_arch_name
= concat (arch
,
12285 (const char *) NULL
);
12289 cpu_sub_arch_name
= xstrdup (arch
);
12290 cpu_arch_flags
= flags
;
12291 cpu_arch_isa_flags
= flags
;
12296 if (j
>= ARRAY_SIZE (cpu_noarch
))
12297 j
= ARRAY_SIZE (cpu_arch
);
12300 if (j
>= ARRAY_SIZE (cpu_arch
))
12301 as_fatal (_("invalid -march= option: `%s'"), arg
);
12305 while (next
!= NULL
);
12311 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12312 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12314 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
12316 cpu_arch_tune_set
= 1;
12317 cpu_arch_tune
= cpu_arch
[j
].type
;
12318 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
12322 if (j
>= ARRAY_SIZE (cpu_arch
))
12323 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
12326 case OPTION_MMNEMONIC
:
12327 if (strcasecmp (arg
, "att") == 0)
12328 intel_mnemonic
= 0;
12329 else if (strcasecmp (arg
, "intel") == 0)
12330 intel_mnemonic
= 1;
12332 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
12335 case OPTION_MSYNTAX
:
12336 if (strcasecmp (arg
, "att") == 0)
12338 else if (strcasecmp (arg
, "intel") == 0)
12341 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
12344 case OPTION_MINDEX_REG
:
12345 allow_index_reg
= 1;
12348 case OPTION_MNAKED_REG
:
12349 allow_naked_reg
= 1;
12352 case OPTION_MSSE2AVX
:
12356 case OPTION_MSSE_CHECK
:
12357 if (strcasecmp (arg
, "error") == 0)
12358 sse_check
= check_error
;
12359 else if (strcasecmp (arg
, "warning") == 0)
12360 sse_check
= check_warning
;
12361 else if (strcasecmp (arg
, "none") == 0)
12362 sse_check
= check_none
;
12364 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
12367 case OPTION_MOPERAND_CHECK
:
12368 if (strcasecmp (arg
, "error") == 0)
12369 operand_check
= check_error
;
12370 else if (strcasecmp (arg
, "warning") == 0)
12371 operand_check
= check_warning
;
12372 else if (strcasecmp (arg
, "none") == 0)
12373 operand_check
= check_none
;
12375 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
12378 case OPTION_MAVXSCALAR
:
12379 if (strcasecmp (arg
, "128") == 0)
12380 avxscalar
= vex128
;
12381 else if (strcasecmp (arg
, "256") == 0)
12382 avxscalar
= vex256
;
12384 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
12387 case OPTION_MVEXWIG
:
12388 if (strcmp (arg
, "0") == 0)
12390 else if (strcmp (arg
, "1") == 0)
12393 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
12396 case OPTION_MADD_BND_PREFIX
:
12397 add_bnd_prefix
= 1;
12400 case OPTION_MEVEXLIG
:
12401 if (strcmp (arg
, "128") == 0)
12402 evexlig
= evexl128
;
12403 else if (strcmp (arg
, "256") == 0)
12404 evexlig
= evexl256
;
12405 else if (strcmp (arg
, "512") == 0)
12406 evexlig
= evexl512
;
12408 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
12411 case OPTION_MEVEXRCIG
:
12412 if (strcmp (arg
, "rne") == 0)
12414 else if (strcmp (arg
, "rd") == 0)
12416 else if (strcmp (arg
, "ru") == 0)
12418 else if (strcmp (arg
, "rz") == 0)
12421 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
12424 case OPTION_MEVEXWIG
:
12425 if (strcmp (arg
, "0") == 0)
12427 else if (strcmp (arg
, "1") == 0)
12430 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
12433 # if defined (TE_PE) || defined (TE_PEP)
12434 case OPTION_MBIG_OBJ
:
12439 case OPTION_MOMIT_LOCK_PREFIX
:
12440 if (strcasecmp (arg
, "yes") == 0)
12441 omit_lock_prefix
= 1;
12442 else if (strcasecmp (arg
, "no") == 0)
12443 omit_lock_prefix
= 0;
12445 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
12448 case OPTION_MFENCE_AS_LOCK_ADD
:
12449 if (strcasecmp (arg
, "yes") == 0)
12451 else if (strcasecmp (arg
, "no") == 0)
12454 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
12457 case OPTION_MRELAX_RELOCATIONS
:
12458 if (strcasecmp (arg
, "yes") == 0)
12459 generate_relax_relocations
= 1;
12460 else if (strcasecmp (arg
, "no") == 0)
12461 generate_relax_relocations
= 0;
12463 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
12466 case OPTION_MALIGN_BRANCH_BOUNDARY
:
12469 long int align
= strtoul (arg
, &end
, 0);
12474 align_branch_power
= 0;
12477 else if (align
>= 16)
12480 for (align_power
= 0;
12482 align
>>= 1, align_power
++)
12484 /* Limit alignment power to 31. */
12485 if (align
== 1 && align_power
< 32)
12487 align_branch_power
= align_power
;
12492 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
12496 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
12499 int align
= strtoul (arg
, &end
, 0);
12500 /* Some processors only support 5 prefixes. */
12501 if (*end
== '\0' && align
>= 0 && align
< 6)
12503 align_branch_prefix_size
= align
;
12506 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
12511 case OPTION_MALIGN_BRANCH
:
12513 saved
= xstrdup (arg
);
12517 next
= strchr (type
, '+');
12520 if (strcasecmp (type
, "jcc") == 0)
12521 align_branch
|= align_branch_jcc_bit
;
12522 else if (strcasecmp (type
, "fused") == 0)
12523 align_branch
|= align_branch_fused_bit
;
12524 else if (strcasecmp (type
, "jmp") == 0)
12525 align_branch
|= align_branch_jmp_bit
;
12526 else if (strcasecmp (type
, "call") == 0)
12527 align_branch
|= align_branch_call_bit
;
12528 else if (strcasecmp (type
, "ret") == 0)
12529 align_branch
|= align_branch_ret_bit
;
12530 else if (strcasecmp (type
, "indirect") == 0)
12531 align_branch
|= align_branch_indirect_bit
;
12533 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
12536 while (next
!= NULL
);
12540 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
12541 align_branch_power
= 5;
12542 align_branch_prefix_size
= 5;
12543 align_branch
= (align_branch_jcc_bit
12544 | align_branch_fused_bit
12545 | align_branch_jmp_bit
);
12548 case OPTION_MAMD64
:
12552 case OPTION_MINTEL64
:
12560 /* Turn off -Os. */
12561 optimize_for_space
= 0;
12563 else if (*arg
== 's')
12565 optimize_for_space
= 1;
12566 /* Turn on all encoding optimizations. */
12567 optimize
= INT_MAX
;
12571 optimize
= atoi (arg
);
12572 /* Turn off -Os. */
12573 optimize_for_space
= 0;
12583 #define MESSAGE_TEMPLATE \
12587 output_message (FILE *stream
, char *p
, char *message
, char *start
,
12588 int *left_p
, const char *name
, int len
)
12590 int size
= sizeof (MESSAGE_TEMPLATE
);
12591 int left
= *left_p
;
12593 /* Reserve 2 spaces for ", " or ",\0" */
12596 /* Check if there is any room. */
12604 p
= mempcpy (p
, name
, len
);
12608 /* Output the current message now and start a new one. */
12611 fprintf (stream
, "%s\n", message
);
12613 left
= size
- (start
- message
) - len
- 2;
12615 gas_assert (left
>= 0);
12617 p
= mempcpy (p
, name
, len
);
12625 show_arch (FILE *stream
, int ext
, int check
)
12627 static char message
[] = MESSAGE_TEMPLATE
;
12628 char *start
= message
+ 27;
12630 int size
= sizeof (MESSAGE_TEMPLATE
);
12637 left
= size
- (start
- message
);
12638 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
12640 /* Should it be skipped? */
12641 if (cpu_arch
[j
].skip
)
12644 name
= cpu_arch
[j
].name
;
12645 len
= cpu_arch
[j
].len
;
12648 /* It is an extension. Skip if we aren't asked to show it. */
12659 /* It is an processor. Skip if we show only extension. */
12662 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
12664 /* It is an impossible processor - skip. */
12668 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
12671 /* Display disabled extensions. */
12673 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
12675 name
= cpu_noarch
[j
].name
;
12676 len
= cpu_noarch
[j
].len
;
12677 p
= output_message (stream
, p
, message
, start
, &left
, name
,
12682 fprintf (stream
, "%s\n", message
);
12686 md_show_usage (FILE *stream
)
12688 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12689 fprintf (stream
, _("\
12690 -Qy, -Qn ignored\n\
12691 -V print assembler version number\n\
12694 fprintf (stream
, _("\
12695 -n Do not optimize code alignment\n\
12696 -q quieten some warnings\n"));
12697 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12698 fprintf (stream
, _("\
12701 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12702 || defined (TE_PE) || defined (TE_PEP))
12703 fprintf (stream
, _("\
12704 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
12706 #ifdef SVR4_COMMENT_CHARS
12707 fprintf (stream
, _("\
12708 --divide do not treat `/' as a comment character\n"));
12710 fprintf (stream
, _("\
12711 --divide ignored\n"));
12713 fprintf (stream
, _("\
12714 -march=CPU[,+EXTENSION...]\n\
12715 generate code for CPU and EXTENSION, CPU is one of:\n"));
12716 show_arch (stream
, 0, 1);
12717 fprintf (stream
, _("\
12718 EXTENSION is combination of:\n"));
12719 show_arch (stream
, 1, 0);
12720 fprintf (stream
, _("\
12721 -mtune=CPU optimize for CPU, CPU is one of:\n"));
12722 show_arch (stream
, 0, 0);
12723 fprintf (stream
, _("\
12724 -msse2avx encode SSE instructions with VEX prefix\n"));
12725 fprintf (stream
, _("\
12726 -msse-check=[none|error|warning] (default: warning)\n\
12727 check SSE instructions\n"));
12728 fprintf (stream
, _("\
12729 -moperand-check=[none|error|warning] (default: warning)\n\
12730 check operand combinations for validity\n"));
12731 fprintf (stream
, _("\
12732 -mavxscalar=[128|256] (default: 128)\n\
12733 encode scalar AVX instructions with specific vector\n\
12735 fprintf (stream
, _("\
12736 -mvexwig=[0|1] (default: 0)\n\
12737 encode VEX instructions with specific VEX.W value\n\
12738 for VEX.W bit ignored instructions\n"));
12739 fprintf (stream
, _("\
12740 -mevexlig=[128|256|512] (default: 128)\n\
12741 encode scalar EVEX instructions with specific vector\n\
12743 fprintf (stream
, _("\
12744 -mevexwig=[0|1] (default: 0)\n\
12745 encode EVEX instructions with specific EVEX.W value\n\
12746 for EVEX.W bit ignored instructions\n"));
12747 fprintf (stream
, _("\
12748 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
12749 encode EVEX instructions with specific EVEX.RC value\n\
12750 for SAE-only ignored instructions\n"));
12751 fprintf (stream
, _("\
12752 -mmnemonic=[att|intel] "));
12753 if (SYSV386_COMPAT
)
12754 fprintf (stream
, _("(default: att)\n"));
12756 fprintf (stream
, _("(default: intel)\n"));
12757 fprintf (stream
, _("\
12758 use AT&T/Intel mnemonic\n"));
12759 fprintf (stream
, _("\
12760 -msyntax=[att|intel] (default: att)\n\
12761 use AT&T/Intel syntax\n"));
12762 fprintf (stream
, _("\
12763 -mindex-reg support pseudo index registers\n"));
12764 fprintf (stream
, _("\
12765 -mnaked-reg don't require `%%' prefix for registers\n"));
12766 fprintf (stream
, _("\
12767 -madd-bnd-prefix add BND prefix for all valid branches\n"));
12768 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12769 fprintf (stream
, _("\
12770 -mshared disable branch optimization for shared code\n"));
12771 fprintf (stream
, _("\
12772 -mx86-used-note=[no|yes] "));
12773 if (DEFAULT_X86_USED_NOTE
)
12774 fprintf (stream
, _("(default: yes)\n"));
12776 fprintf (stream
, _("(default: no)\n"));
12777 fprintf (stream
, _("\
12778 generate x86 used ISA and feature properties\n"));
12780 #if defined (TE_PE) || defined (TE_PEP)
12781 fprintf (stream
, _("\
12782 -mbig-obj generate big object files\n"));
12784 fprintf (stream
, _("\
12785 -momit-lock-prefix=[no|yes] (default: no)\n\
12786 strip all lock prefixes\n"));
12787 fprintf (stream
, _("\
12788 -mfence-as-lock-add=[no|yes] (default: no)\n\
12789 encode lfence, mfence and sfence as\n\
12790 lock addl $0x0, (%%{re}sp)\n"));
12791 fprintf (stream
, _("\
12792 -mrelax-relocations=[no|yes] "));
12793 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
12794 fprintf (stream
, _("(default: yes)\n"));
12796 fprintf (stream
, _("(default: no)\n"));
12797 fprintf (stream
, _("\
12798 generate relax relocations\n"));
12799 fprintf (stream
, _("\
12800 -malign-branch-boundary=NUM (default: 0)\n\
12801 align branches within NUM byte boundary\n"));
12802 fprintf (stream
, _("\
12803 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
12804 TYPE is combination of jcc, fused, jmp, call, ret,\n\
12806 specify types of branches to align\n"));
12807 fprintf (stream
, _("\
12808 -malign-branch-prefix-size=NUM (default: 5)\n\
12809 align branches with NUM prefixes per instruction\n"));
12810 fprintf (stream
, _("\
12811 -mbranches-within-32B-boundaries\n\
12812 align branches within 32 byte boundary\n"));
12813 fprintf (stream
, _("\
12814 -mamd64 accept only AMD64 ISA [default]\n"));
12815 fprintf (stream
, _("\
12816 -mintel64 accept only Intel64 ISA\n"));
12819 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
12820 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12821 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12823 /* Pick the target format to use. */
12826 i386_target_format (void)
12828 if (!strncmp (default_arch
, "x86_64", 6))
12830 update_code_flag (CODE_64BIT
, 1);
12831 if (default_arch
[6] == '\0')
12832 x86_elf_abi
= X86_64_ABI
;
12834 x86_elf_abi
= X86_64_X32_ABI
;
12836 else if (!strcmp (default_arch
, "i386"))
12837 update_code_flag (CODE_32BIT
, 1);
12838 else if (!strcmp (default_arch
, "iamcu"))
12840 update_code_flag (CODE_32BIT
, 1);
12841 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
12843 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
12844 cpu_arch_name
= "iamcu";
12845 cpu_sub_arch_name
= NULL
;
12846 cpu_arch_flags
= iamcu_flags
;
12847 cpu_arch_isa
= PROCESSOR_IAMCU
;
12848 cpu_arch_isa_flags
= iamcu_flags
;
12849 if (!cpu_arch_tune_set
)
12851 cpu_arch_tune
= cpu_arch_isa
;
12852 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
12855 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
12856 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
12860 as_fatal (_("unknown architecture"));
12862 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
12863 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12864 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
12865 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
12867 switch (OUTPUT_FLAVOR
)
12869 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
12870 case bfd_target_aout_flavour
:
12871 return AOUT_TARGET_FORMAT
;
12873 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
12874 # if defined (TE_PE) || defined (TE_PEP)
12875 case bfd_target_coff_flavour
:
12876 if (flag_code
== CODE_64BIT
)
12877 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
12880 # elif defined (TE_GO32)
12881 case bfd_target_coff_flavour
:
12882 return "coff-go32";
12884 case bfd_target_coff_flavour
:
12885 return "coff-i386";
12888 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12889 case bfd_target_elf_flavour
:
12891 const char *format
;
12893 switch (x86_elf_abi
)
12896 format
= ELF_TARGET_FORMAT
;
12898 tls_get_addr
= "___tls_get_addr";
12902 use_rela_relocations
= 1;
12905 tls_get_addr
= "__tls_get_addr";
12907 format
= ELF_TARGET_FORMAT64
;
12909 case X86_64_X32_ABI
:
12910 use_rela_relocations
= 1;
12913 tls_get_addr
= "__tls_get_addr";
12915 disallow_64bit_reloc
= 1;
12916 format
= ELF_TARGET_FORMAT32
;
12919 if (cpu_arch_isa
== PROCESSOR_L1OM
)
12921 if (x86_elf_abi
!= X86_64_ABI
)
12922 as_fatal (_("Intel L1OM is 64bit only"));
12923 return ELF_TARGET_L1OM_FORMAT
;
12925 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
12927 if (x86_elf_abi
!= X86_64_ABI
)
12928 as_fatal (_("Intel K1OM is 64bit only"));
12929 return ELF_TARGET_K1OM_FORMAT
;
12931 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
12933 if (x86_elf_abi
!= I386_ABI
)
12934 as_fatal (_("Intel MCU is 32bit only"));
12935 return ELF_TARGET_IAMCU_FORMAT
;
12941 #if defined (OBJ_MACH_O)
12942 case bfd_target_mach_o_flavour
:
12943 if (flag_code
== CODE_64BIT
)
12945 use_rela_relocations
= 1;
12947 return "mach-o-x86-64";
12950 return "mach-o-i386";
12958 #endif /* OBJ_MAYBE_ more than one */
12961 md_undefined_symbol (char *name
)
12963 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
12964 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
12965 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
12966 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
12970 if (symbol_find (name
))
12971 as_bad (_("GOT already in symbol table"));
12972 GOT_symbol
= symbol_new (name
, undefined_section
,
12973 (valueT
) 0, &zero_address_frag
);
12980 /* Round up a section size to the appropriate boundary. */
12983 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
12985 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12986 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
12988 /* For a.out, force the section size to be aligned. If we don't do
12989 this, BFD will align it for us, but it will not write out the
12990 final bytes of the section. This may be a bug in BFD, but it is
12991 easier to fix it here since that is how the other a.out targets
12995 align
= bfd_section_alignment (segment
);
12996 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
13003 /* On the i386, PC-relative offsets are relative to the start of the
13004 next instruction. That is, the address of the offset, plus its
13005 size, since the offset is always the last part of the insn. */
13008 md_pcrel_from (fixS
*fixP
)
13010 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13016 s_bss (int ignore ATTRIBUTE_UNUSED
)
13020 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13022 obj_elf_section_change_hook ();
13024 temp
= get_absolute_expression ();
13025 subseg_set (bss_section
, (subsegT
) temp
);
13026 demand_empty_rest_of_line ();
13031 /* Remember constant directive. */
13034 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
13036 if (last_insn
.kind
!= last_insn_directive
13037 && (bfd_section_flags (now_seg
) & SEC_CODE
))
13039 last_insn
.seg
= now_seg
;
13040 last_insn
.kind
= last_insn_directive
;
13041 last_insn
.name
= "constant directive";
13042 last_insn
.file
= as_where (&last_insn
.line
);
13047 i386_validate_fix (fixS
*fixp
)
13049 if (fixp
->fx_subsy
)
13051 if (fixp
->fx_subsy
== GOT_symbol
)
13053 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
13057 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13058 if (fixp
->fx_tcbit2
)
13059 fixp
->fx_r_type
= (fixp
->fx_tcbit
13060 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13061 : BFD_RELOC_X86_64_GOTPCRELX
);
13064 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
13069 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
13071 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
13073 fixp
->fx_subsy
= 0;
13076 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13077 else if (!object_64bit
)
13079 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
13080 && fixp
->fx_tcbit2
)
13081 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
13087 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13090 bfd_reloc_code_real_type code
;
13092 switch (fixp
->fx_r_type
)
13094 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13095 case BFD_RELOC_SIZE32
:
13096 case BFD_RELOC_SIZE64
:
13097 if (S_IS_DEFINED (fixp
->fx_addsy
)
13098 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
13100 /* Resolve size relocation against local symbol to size of
13101 the symbol plus addend. */
13102 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
13103 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
13104 && !fits_in_unsigned_long (value
))
13105 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13106 _("symbol size computation overflow"));
13107 fixp
->fx_addsy
= NULL
;
13108 fixp
->fx_subsy
= NULL
;
13109 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
13113 /* Fall through. */
13115 case BFD_RELOC_X86_64_PLT32
:
13116 case BFD_RELOC_X86_64_GOT32
:
13117 case BFD_RELOC_X86_64_GOTPCREL
:
13118 case BFD_RELOC_X86_64_GOTPCRELX
:
13119 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13120 case BFD_RELOC_386_PLT32
:
13121 case BFD_RELOC_386_GOT32
:
13122 case BFD_RELOC_386_GOT32X
:
13123 case BFD_RELOC_386_GOTOFF
:
13124 case BFD_RELOC_386_GOTPC
:
13125 case BFD_RELOC_386_TLS_GD
:
13126 case BFD_RELOC_386_TLS_LDM
:
13127 case BFD_RELOC_386_TLS_LDO_32
:
13128 case BFD_RELOC_386_TLS_IE_32
:
13129 case BFD_RELOC_386_TLS_IE
:
13130 case BFD_RELOC_386_TLS_GOTIE
:
13131 case BFD_RELOC_386_TLS_LE_32
:
13132 case BFD_RELOC_386_TLS_LE
:
13133 case BFD_RELOC_386_TLS_GOTDESC
:
13134 case BFD_RELOC_386_TLS_DESC_CALL
:
13135 case BFD_RELOC_X86_64_TLSGD
:
13136 case BFD_RELOC_X86_64_TLSLD
:
13137 case BFD_RELOC_X86_64_DTPOFF32
:
13138 case BFD_RELOC_X86_64_DTPOFF64
:
13139 case BFD_RELOC_X86_64_GOTTPOFF
:
13140 case BFD_RELOC_X86_64_TPOFF32
:
13141 case BFD_RELOC_X86_64_TPOFF64
:
13142 case BFD_RELOC_X86_64_GOTOFF64
:
13143 case BFD_RELOC_X86_64_GOTPC32
:
13144 case BFD_RELOC_X86_64_GOT64
:
13145 case BFD_RELOC_X86_64_GOTPCREL64
:
13146 case BFD_RELOC_X86_64_GOTPC64
:
13147 case BFD_RELOC_X86_64_GOTPLT64
:
13148 case BFD_RELOC_X86_64_PLTOFF64
:
13149 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13150 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13151 case BFD_RELOC_RVA
:
13152 case BFD_RELOC_VTABLE_ENTRY
:
13153 case BFD_RELOC_VTABLE_INHERIT
:
13155 case BFD_RELOC_32_SECREL
:
13157 code
= fixp
->fx_r_type
;
13159 case BFD_RELOC_X86_64_32S
:
13160 if (!fixp
->fx_pcrel
)
13162 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13163 code
= fixp
->fx_r_type
;
13166 /* Fall through. */
13168 if (fixp
->fx_pcrel
)
13170 switch (fixp
->fx_size
)
13173 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13174 _("can not do %d byte pc-relative relocation"),
13176 code
= BFD_RELOC_32_PCREL
;
13178 case 1: code
= BFD_RELOC_8_PCREL
; break;
13179 case 2: code
= BFD_RELOC_16_PCREL
; break;
13180 case 4: code
= BFD_RELOC_32_PCREL
; break;
13182 case 8: code
= BFD_RELOC_64_PCREL
; break;
13188 switch (fixp
->fx_size
)
13191 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13192 _("can not do %d byte relocation"),
13194 code
= BFD_RELOC_32
;
13196 case 1: code
= BFD_RELOC_8
; break;
13197 case 2: code
= BFD_RELOC_16
; break;
13198 case 4: code
= BFD_RELOC_32
; break;
13200 case 8: code
= BFD_RELOC_64
; break;
13207 if ((code
== BFD_RELOC_32
13208 || code
== BFD_RELOC_32_PCREL
13209 || code
== BFD_RELOC_X86_64_32S
)
13211 && fixp
->fx_addsy
== GOT_symbol
)
13214 code
= BFD_RELOC_386_GOTPC
;
13216 code
= BFD_RELOC_X86_64_GOTPC32
;
13218 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
13220 && fixp
->fx_addsy
== GOT_symbol
)
13222 code
= BFD_RELOC_X86_64_GOTPC64
;
13225 rel
= XNEW (arelent
);
13226 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
13227 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13229 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13231 if (!use_rela_relocations
)
13233 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13234 vtable entry to be used in the relocation's section offset. */
13235 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13236 rel
->address
= fixp
->fx_offset
;
13237 #if defined (OBJ_COFF) && defined (TE_PE)
13238 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
13239 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
13244 /* Use the rela in 64bit mode. */
13247 if (disallow_64bit_reloc
)
13250 case BFD_RELOC_X86_64_DTPOFF64
:
13251 case BFD_RELOC_X86_64_TPOFF64
:
13252 case BFD_RELOC_64_PCREL
:
13253 case BFD_RELOC_X86_64_GOTOFF64
:
13254 case BFD_RELOC_X86_64_GOT64
:
13255 case BFD_RELOC_X86_64_GOTPCREL64
:
13256 case BFD_RELOC_X86_64_GOTPC64
:
13257 case BFD_RELOC_X86_64_GOTPLT64
:
13258 case BFD_RELOC_X86_64_PLTOFF64
:
13259 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13260 _("cannot represent relocation type %s in x32 mode"),
13261 bfd_get_reloc_code_name (code
));
13267 if (!fixp
->fx_pcrel
)
13268 rel
->addend
= fixp
->fx_offset
;
13272 case BFD_RELOC_X86_64_PLT32
:
13273 case BFD_RELOC_X86_64_GOT32
:
13274 case BFD_RELOC_X86_64_GOTPCREL
:
13275 case BFD_RELOC_X86_64_GOTPCRELX
:
13276 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
13277 case BFD_RELOC_X86_64_TLSGD
:
13278 case BFD_RELOC_X86_64_TLSLD
:
13279 case BFD_RELOC_X86_64_GOTTPOFF
:
13280 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13281 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13282 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
13285 rel
->addend
= (section
->vma
13287 + fixp
->fx_addnumber
13288 + md_pcrel_from (fixp
));
13293 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13294 if (rel
->howto
== NULL
)
13296 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13297 _("cannot represent relocation type %s"),
13298 bfd_get_reloc_code_name (code
));
13299 /* Set howto to a garbage value so that we can keep going. */
13300 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
13301 gas_assert (rel
->howto
!= NULL
);
13307 #include "tc-i386-intel.c"
13310 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
13312 int saved_naked_reg
;
13313 char saved_register_dot
;
13315 saved_naked_reg
= allow_naked_reg
;
13316 allow_naked_reg
= 1;
13317 saved_register_dot
= register_chars
['.'];
13318 register_chars
['.'] = '.';
13319 allow_pseudo_reg
= 1;
13320 expression_and_evaluate (exp
);
13321 allow_pseudo_reg
= 0;
13322 register_chars
['.'] = saved_register_dot
;
13323 allow_naked_reg
= saved_naked_reg
;
13325 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
13327 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
13329 exp
->X_op
= O_constant
;
13330 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
13331 .dw2_regnum
[flag_code
>> 1];
13334 exp
->X_op
= O_illegal
;
13339 tc_x86_frame_initial_instructions (void)
13341 static unsigned int sp_regno
[2];
13343 if (!sp_regno
[flag_code
>> 1])
13345 char *saved_input
= input_line_pointer
;
13346 char sp
[][4] = {"esp", "rsp"};
13349 input_line_pointer
= sp
[flag_code
>> 1];
13350 tc_x86_parse_to_dw2regnum (&exp
);
13351 gas_assert (exp
.X_op
== O_constant
);
13352 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
13353 input_line_pointer
= saved_input
;
13356 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
13357 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
13361 x86_dwarf2_addr_size (void)
13363 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13364 if (x86_elf_abi
== X86_64_X32_ABI
)
13367 return bfd_arch_bits_per_address (stdoutput
) / 8;
13371 i386_elf_section_type (const char *str
, size_t len
)
13373 if (flag_code
== CODE_64BIT
13374 && len
== sizeof ("unwind") - 1
13375 && strncmp (str
, "unwind", 6) == 0)
13376 return SHT_X86_64_UNWIND
;
13383 i386_solaris_fix_up_eh_frame (segT sec
)
13385 if (flag_code
== CODE_64BIT
)
13386 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
13392 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
13396 exp
.X_op
= O_secrel
;
13397 exp
.X_add_symbol
= symbol
;
13398 exp
.X_add_number
= 0;
13399 emit_expr (&exp
, size
);
13403 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13404 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
13407 x86_64_section_letter (int letter
, const char **ptr_msg
)
13409 if (flag_code
== CODE_64BIT
)
13412 return SHF_X86_64_LARGE
;
13414 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
13417 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
13422 x86_64_section_word (char *str
, size_t len
)
13424 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
13425 return SHF_X86_64_LARGE
;
13431 handle_large_common (int small ATTRIBUTE_UNUSED
)
13433 if (flag_code
!= CODE_64BIT
)
13435 s_comm_internal (0, elf_common_parse
);
13436 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
13440 static segT lbss_section
;
13441 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
13442 asection
*saved_bss_section
= bss_section
;
13444 if (lbss_section
== NULL
)
13446 flagword applicable
;
13447 segT seg
= now_seg
;
13448 subsegT subseg
= now_subseg
;
13450 /* The .lbss section is for local .largecomm symbols. */
13451 lbss_section
= subseg_new (".lbss", 0);
13452 applicable
= bfd_applicable_section_flags (stdoutput
);
13453 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
13454 seg_info (lbss_section
)->bss
= 1;
13456 subseg_set (seg
, subseg
);
13459 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
13460 bss_section
= lbss_section
;
13462 s_comm_internal (0, elf_common_parse
);
13464 elf_com_section_ptr
= saved_com_section_ptr
;
13465 bss_section
= saved_bss_section
;
13468 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */