gdb: add target_ops::supports_displaced_step
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.h
1 /* Common target dependent code for GDB on AArch64 systems.
2
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21
22 #ifndef AARCH64_TDEP_H
23 #define AARCH64_TDEP_H
24
25 #include "arch/aarch64.h"
26 #include "infrun.h"
27
28 /* Forward declarations. */
29 struct gdbarch;
30 struct regset;
31
32 /* AArch64 Dwarf register numbering. */
33 #define AARCH64_DWARF_X0 0
34 #define AARCH64_DWARF_SP 31
35 #define AARCH64_DWARF_PAUTH_RA_STATE 34
36 #define AARCH64_DWARF_PAUTH_DMASK 35
37 #define AARCH64_DWARF_PAUTH_CMASK 36
38 #define AARCH64_DWARF_V0 64
39 #define AARCH64_DWARF_SVE_VG 46
40 #define AARCH64_DWARF_SVE_FFR 47
41 #define AARCH64_DWARF_SVE_P0 48
42 #define AARCH64_DWARF_SVE_Z0 96
43
44 /* Size of integer registers. */
45 #define X_REGISTER_SIZE 8
46 #define B_REGISTER_SIZE 1
47 #define H_REGISTER_SIZE 2
48 #define S_REGISTER_SIZE 4
49 #define D_REGISTER_SIZE 8
50 #define V_REGISTER_SIZE 16
51 #define Q_REGISTER_SIZE 16
52
53 /* Total number of general (X) registers. */
54 #define AARCH64_X_REGISTER_COUNT 32
55 /* Total number of D registers. */
56 #define AARCH64_D_REGISTER_COUNT 32
57
58 /* The maximum number of modified instructions generated for one
59 single-stepped instruction. */
60 #define AARCH64_DISPLACED_MODIFIED_INSNS 1
61
62 /* Target-dependent structure in gdbarch. */
63 struct gdbarch_tdep
64 {
65 /* Lowest address at which instructions will appear. */
66 CORE_ADDR lowest_pc;
67
68 /* Offset to PC value in jump buffer. If this is negative, longjmp
69 support will be disabled. */
70 int jb_pc;
71
72 /* And the size of each entry in the buf. */
73 size_t jb_elt_size;
74
75 /* Types for AdvSISD registers. */
76 struct type *vnq_type;
77 struct type *vnd_type;
78 struct type *vns_type;
79 struct type *vnh_type;
80 struct type *vnb_type;
81 struct type *vnv_type;
82
83 /* syscall record. */
84 int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
85
86 /* The VQ value for SVE targets, or zero if SVE is not supported. */
87 uint64_t vq;
88
89 /* Returns true if the target supports SVE. */
90 bool has_sve () const
91 {
92 return vq != 0;
93 }
94
95 int pauth_reg_base;
96 int pauth_ra_state_regnum;
97
98 /* Returns true if the target supports pauth. */
99 bool has_pauth () const
100 {
101 return pauth_reg_base != -1;
102 }
103 };
104
105 const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p);
106
107 extern int aarch64_process_record (struct gdbarch *gdbarch,
108 struct regcache *regcache, CORE_ADDR addr);
109
110 displaced_step_copy_insn_closure_up
111 aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
112 CORE_ADDR from, CORE_ADDR to,
113 struct regcache *regs);
114
115 void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
116 struct displaced_step_copy_insn_closure *dsc,
117 CORE_ADDR from, CORE_ADDR to,
118 struct regcache *regs);
119
120 int aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
121 struct displaced_step_copy_insn_closure *closure);
122
123 #endif /* aarch64-tdep.h */
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