gdb/ia64-tdep.c

   1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
   2
   3    Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
   4    2009 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "inferior.h"
  23 #include "gdbcore.h"
  24 #include "arch-utils.h"
  25 #include "floatformat.h"
  26 #include "gdbtypes.h"
  27 #include "regcache.h"
  28 #include "reggroups.h"
  29 #include "frame.h"
  30 #include "frame-base.h"
  31 #include "frame-unwind.h"
  32 #include "doublest.h"
  33 #include "value.h"
  34 #include "gdb_assert.h"
  35 #include "objfiles.h"
  36 #include "elf/common.h"         /* for DT_PLTGOT value */
  37 #include "elf-bfd.h"
  38 #include "dis-asm.h"
  39 #include "infcall.h"
  40 #include "osabi.h"
  41 #include "ia64-tdep.h"
  42 #include "cp-abi.h"
  43
  44 #ifdef HAVE_LIBUNWIND_IA64_H
  45 #include "elf/ia64.h"           /* for PT_IA_64_UNWIND value */
  46 #include "libunwind-frame.h"
  47 #include "libunwind-ia64.h"
  48
  49 /* Note: KERNEL_START is supposed to be an address which is not going
  50          to ever contain any valid unwind info.  For ia64 linux, the choice
  51          of 0xc000000000000000 is fairly safe since that's uncached space.
  52
  53          We use KERNEL_START as follows: after obtaining the kernel's
  54          unwind table via getunwind(), we project its unwind data into
  55          address-range KERNEL_START-(KERNEL_START+ktab_size) and then
  56          when ia64_access_mem() sees a memory access to this
  57          address-range, we redirect it to ktab instead.
  58
  59          None of this hackery is needed with a modern kernel/libcs
  60          which uses the kernel virtual DSO to provide access to the
  61          kernel's unwind info.  In that case, ktab_size remains 0 and
  62          hence the value of KERNEL_START doesn't matter.  */
  63
  64 #define KERNEL_START 0xc000000000000000ULL
  65
  66 static size_t ktab_size = 0;
  67 struct ia64_table_entry
  68   {
  69     uint64_t start_offset;
  70     uint64_t end_offset;
  71     uint64_t info_offset;
  72   };
  73
  74 static struct ia64_table_entry *ktab = NULL;
  75
  76 #endif
  77
  78 /* An enumeration of the different IA-64 instruction types.  */
  79
  80 typedef enum instruction_type
  81 {
  82   A,                    /* Integer ALU ;    I-unit or M-unit */
  83   I,                    /* Non-ALU integer; I-unit */
  84   M,                    /* Memory ;         M-unit */
  85   F,                    /* Floating-point ; F-unit */
  86   B,                    /* Branch ;         B-unit */
  87   L,                    /* Extended (L+X) ; I-unit */
  88   X,                    /* Extended (L+X) ; I-unit */
  89   undefined             /* undefined or reserved */
  90 } instruction_type;
  91
  92 /* We represent IA-64 PC addresses as the value of the instruction
  93    pointer or'd with some bit combination in the low nibble which
  94    represents the slot number in the bundle addressed by the
  95    instruction pointer.  The problem is that the Linux kernel
  96    multiplies its slot numbers (for exceptions) by one while the
  97    disassembler multiplies its slot numbers by 6.  In addition, I've
  98    heard it said that the simulator uses 1 as the multiplier.
  99
 100    I've fixed the disassembler so that the bytes_per_line field will
 101    be the slot multiplier.  If bytes_per_line comes in as zero, it
 102    is set to six (which is how it was set up initially). -- objdump
 103    displays pretty disassembly dumps with this value.  For our purposes,
 104    we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
 105    never want to also display the raw bytes the way objdump does. */
 106
 107 #define SLOT_MULTIPLIER 1
 108
 109 /* Length in bytes of an instruction bundle */
 110
 111 #define BUNDLE_LEN 16
 112
 113 /* See the saved memory layout comment for ia64_memory_insert_breakpoint.  */
 114
 115 #if BREAKPOINT_MAX < BUNDLE_LEN - 2
 116 # error "BREAKPOINT_MAX < BUNDLE_LEN - 2"
 117 #endif
 118
 119 static gdbarch_init_ftype ia64_gdbarch_init;
 120
 121 static gdbarch_register_name_ftype ia64_register_name;
 122 static gdbarch_register_type_ftype ia64_register_type;
 123 static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
 124 static gdbarch_skip_prologue_ftype ia64_skip_prologue;
 125 static struct type *is_float_or_hfa_type (struct type *t);
 126 static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
 127
 128 static struct type *builtin_type_ia64_ext;
 129
 130 #define NUM_IA64_RAW_REGS 462
 131
 132 static int sp_regnum = IA64_GR12_REGNUM;
 133 static int fp_regnum = IA64_VFP_REGNUM;
 134 static int lr_regnum = IA64_VRAP_REGNUM;
 135
 136 /* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
 137    they may not be accessible via the ptrace register get/set interfaces.  */
 138 enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
 139                    V127_REGNUM = V32_REGNUM + 95,
 140                    VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
 141
 142 /* Array of register names; There should be ia64_num_regs strings in
 143    the initializer.  */
 144
 145 static char *ia64_register_names[] =
 146 { "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
 147   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
 148   "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
 149   "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
 150   "",     "",     "",     "",     "",     "",     "",     "",
 151   "",     "",     "",     "",     "",     "",     "",     "",
 152   "",     "",     "",     "",     "",     "",     "",     "",
 153   "",     "",     "",     "",     "",     "",     "",     "",
 154   "",     "",     "",     "",     "",     "",     "",     "",
 155   "",     "",     "",     "",     "",     "",     "",     "",
 156   "",     "",     "",     "",     "",     "",     "",     "",
 157   "",     "",     "",     "",     "",     "",     "",     "",
 158   "",     "",     "",     "",     "",     "",     "",     "",
 159   "",     "",     "",     "",     "",     "",     "",     "",
 160   "",     "",     "",     "",     "",     "",     "",     "",
 161   "",     "",     "",     "",     "",     "",     "",     "",
 162
 163   "f0",   "f1",   "f2",   "f3",   "f4",   "f5",   "f6",   "f7",
 164   "f8",   "f9",   "f10",  "f11",  "f12",  "f13",  "f14",  "f15",
 165   "f16",  "f17",  "f18",  "f19",  "f20",  "f21",  "f22",  "f23",
 166   "f24",  "f25",  "f26",  "f27",  "f28",  "f29",  "f30",  "f31",
 167   "f32",  "f33",  "f34",  "f35",  "f36",  "f37",  "f38",  "f39",
 168   "f40",  "f41",  "f42",  "f43",  "f44",  "f45",  "f46",  "f47",
 169   "f48",  "f49",  "f50",  "f51",  "f52",  "f53",  "f54",  "f55",
 170   "f56",  "f57",  "f58",  "f59",  "f60",  "f61",  "f62",  "f63",
 171   "f64",  "f65",  "f66",  "f67",  "f68",  "f69",  "f70",  "f71",
 172   "f72",  "f73",  "f74",  "f75",  "f76",  "f77",  "f78",  "f79",
 173   "f80",  "f81",  "f82",  "f83",  "f84",  "f85",  "f86",  "f87",
 174   "f88",  "f89",  "f90",  "f91",  "f92",  "f93",  "f94",  "f95",
 175   "f96",  "f97",  "f98",  "f99",  "f100", "f101", "f102", "f103",
 176   "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
 177   "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
 178   "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
 179
 180   "",     "",     "",     "",     "",     "",     "",     "",
 181   "",     "",     "",     "",     "",     "",     "",     "",
 182   "",     "",     "",     "",     "",     "",     "",     "",
 183   "",     "",     "",     "",     "",     "",     "",     "",
 184   "",     "",     "",     "",     "",     "",     "",     "",
 185   "",     "",     "",     "",     "",     "",     "",     "",
 186   "",     "",     "",     "",     "",     "",     "",     "",
 187   "",     "",     "",     "",     "",     "",     "",     "",
 188
 189   "b0",   "b1",   "b2",   "b3",   "b4",   "b5",   "b6",   "b7",
 190
 191   "vfp", "vrap",
 192
 193   "pr", "ip", "psr", "cfm",
 194
 195   "kr0",   "kr1",   "kr2",   "kr3",   "kr4",   "kr5",   "kr6",   "kr7",
 196   "", "", "", "", "", "", "", "",
 197   "rsc", "bsp", "bspstore", "rnat",
 198   "", "fcr", "", "",
 199   "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr",  "",
 200   "ccv", "", "", "", "unat", "", "", "",
 201   "fpsr", "", "", "", "itc",
 202   "", "", "", "", "", "", "", "", "", "",
 203   "", "", "", "", "", "", "", "", "",
 204   "pfs", "lc", "ec",
 205   "", "", "", "", "", "", "", "", "", "",
 206   "", "", "", "", "", "", "", "", "", "",
 207   "", "", "", "", "", "", "", "", "", "",
 208   "", "", "", "", "", "", "", "", "", "",
 209   "", "", "", "", "", "", "", "", "", "",
 210   "", "", "", "", "", "", "", "", "", "",
 211   "",
 212   "nat0",  "nat1",  "nat2",  "nat3",  "nat4",  "nat5",  "nat6",  "nat7",
 213   "nat8",  "nat9",  "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
 214   "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
 215   "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
 216   "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
 217   "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
 218   "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
 219   "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
 220   "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
 221   "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
 222   "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
 223   "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
 224   "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
 225   "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
 226   "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
 227   "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
 228
 229   "bof",
 230
 231   "r32",  "r33",  "r34",  "r35",  "r36",  "r37",  "r38",  "r39",
 232   "r40",  "r41",  "r42",  "r43",  "r44",  "r45",  "r46",  "r47",
 233   "r48",  "r49",  "r50",  "r51",  "r52",  "r53",  "r54",  "r55",
 234   "r56",  "r57",  "r58",  "r59",  "r60",  "r61",  "r62",  "r63",
 235   "r64",  "r65",  "r66",  "r67",  "r68",  "r69",  "r70",  "r71",
 236   "r72",  "r73",  "r74",  "r75",  "r76",  "r77",  "r78",  "r79",
 237   "r80",  "r81",  "r82",  "r83",  "r84",  "r85",  "r86",  "r87",
 238   "r88",  "r89",  "r90",  "r91",  "r92",  "r93",  "r94",  "r95",
 239   "r96",  "r97",  "r98",  "r99",  "r100", "r101", "r102", "r103",
 240   "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
 241   "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
 242   "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
 243
 244   "p0",   "p1",   "p2",   "p3",   "p4",   "p5",   "p6",   "p7",
 245   "p8",   "p9",   "p10",  "p11",  "p12",  "p13",  "p14",  "p15",
 246   "p16",  "p17",  "p18",  "p19",  "p20",  "p21",  "p22",  "p23",
 247   "p24",  "p25",  "p26",  "p27",  "p28",  "p29",  "p30",  "p31",
 248   "p32",  "p33",  "p34",  "p35",  "p36",  "p37",  "p38",  "p39",
 249   "p40",  "p41",  "p42",  "p43",  "p44",  "p45",  "p46",  "p47",
 250   "p48",  "p49",  "p50",  "p51",  "p52",  "p53",  "p54",  "p55",
 251   "p56",  "p57",  "p58",  "p59",  "p60",  "p61",  "p62",  "p63",
 252 };
 253
 254 struct ia64_frame_cache
 255 {
 256   CORE_ADDR base;       /* frame pointer base for frame */
 257   CORE_ADDR pc;         /* function start pc for frame */
 258   CORE_ADDR saved_sp;   /* stack pointer for frame */
 259   CORE_ADDR bsp;        /* points at r32 for the current frame */
 260   CORE_ADDR cfm;        /* cfm value for current frame */
 261   CORE_ADDR prev_cfm;   /* cfm value for previous frame */
 262   int   frameless;
 263   int   sof;            /* Size of frame  (decoded from cfm value) */
 264   int   sol;            /* Size of locals (decoded from cfm value) */
 265   int   sor;            /* Number of rotating registers. (decoded from cfm value) */
 266   CORE_ADDR after_prologue;
 267   /* Address of first instruction after the last
 268      prologue instruction;  Note that there may
 269      be instructions from the function's body
 270      intermingled with the prologue. */
 271   int mem_stack_frame_size;
 272   /* Size of the memory stack frame (may be zero),
 273      or -1 if it has not been determined yet. */
 274   int   fp_reg;         /* Register number (if any) used a frame pointer
 275                            for this frame.  0 if no register is being used
 276                            as the frame pointer. */
 277
 278   /* Saved registers.  */
 279   CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
 280
 281 };
 282
 283 int
 284 ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 285                           struct reggroup *group)
 286 {
 287   int vector_p;
 288   int float_p;
 289   int raw_p;
 290   if (group == all_reggroup)
 291     return 1;
 292   vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
 293   float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
 294   raw_p = regnum < NUM_IA64_RAW_REGS;
 295   if (group == float_reggroup)
 296     return float_p;
 297   if (group == vector_reggroup)
 298     return vector_p;
 299   if (group == general_reggroup)
 300     return (!vector_p && !float_p);
 301   if (group == save_reggroup || group == restore_reggroup)
 302     return raw_p;
 303   return 0;
 304 }
 305
 306 static const char *
 307 ia64_register_name (struct gdbarch *gdbarch, int reg)
 308 {
 309   return ia64_register_names[reg];
 310 }
 311
 312 struct type *
 313 ia64_register_type (struct gdbarch *arch, int reg)
 314 {
 315   if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
 316     return builtin_type_ia64_ext;
 317   else
 318     return builtin_type (arch)->builtin_long;
 319 }
 320
 321 static int
 322 ia64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 323 {
 324   if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
 325     return V32_REGNUM + (reg - IA64_GR32_REGNUM);
 326   return reg;
 327 }
 328
 329 static int
 330 floatformat_valid (const struct floatformat *fmt, const void *from)
 331 {
 332   return 1;
 333 }
 334
 335 const struct floatformat floatformat_ia64_ext =
 336 {
 337   floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
 338   floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid, NULL
 339 };
 340
 341 const struct floatformat *floatformats_ia64_ext[2] =
 342 {
 343   &floatformat_ia64_ext,
 344   &floatformat_ia64_ext
 345 };
 346
 347
 348 /* Extract ``len'' bits from an instruction bundle starting at
 349    bit ``from''.  */
 350
 351 static long long
 352 extract_bit_field (const char *bundle, int from, int len)
 353 {
 354   long long result = 0LL;
 355   int to = from + len;
 356   int from_byte = from / 8;
 357   int to_byte = to / 8;
 358   unsigned char *b = (unsigned char *) bundle;
 359   unsigned char c;
 360   int lshift;
 361   int i;
 362
 363   c = b[from_byte];
 364   if (from_byte == to_byte)
 365     c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
 366   result = c >> (from % 8);
 367   lshift = 8 - (from % 8);
 368
 369   for (i = from_byte+1; i < to_byte; i++)
 370     {
 371       result |= ((long long) b[i]) << lshift;
 372       lshift += 8;
 373     }
 374
 375   if (from_byte < to_byte && (to % 8 != 0))
 376     {
 377       c = b[to_byte];
 378       c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
 379       result |= ((long long) c) << lshift;
 380     }
 381
 382   return result;
 383 }
 384
 385 /* Replace the specified bits in an instruction bundle */
 386
 387 static void
 388 replace_bit_field (char *bundle, long long val, int from, int len)
 389 {
 390   int to = from + len;
 391   int from_byte = from / 8;
 392   int to_byte = to / 8;
 393   unsigned char *b = (unsigned char *) bundle;
 394   unsigned char c;
 395
 396   if (from_byte == to_byte)
 397     {
 398       unsigned char left, right;
 399       c = b[from_byte];
 400       left = (c >> (to % 8)) << (to % 8);
 401       right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
 402       c = (unsigned char) (val & 0xff);
 403       c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
 404       c |= right | left;
 405       b[from_byte] = c;
 406     }
 407   else
 408     {
 409       int i;
 410       c = b[from_byte];
 411       c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
 412       c = c | (val << (from % 8));
 413       b[from_byte] = c;
 414       val >>= 8 - from % 8;
 415
 416       for (i = from_byte+1; i < to_byte; i++)
 417         {
 418           c = val & 0xff;
 419           val >>= 8;
 420           b[i] = c;
 421         }
 422
 423       if (to % 8 != 0)
 424         {
 425           unsigned char cv = (unsigned char) val;
 426           c = b[to_byte];
 427           c = c >> (to % 8) << (to % 8);
 428           c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
 429           b[to_byte] = c;
 430         }
 431     }
 432 }
 433
 434 /* Return the contents of slot N (for N = 0, 1, or 2) in
 435    and instruction bundle */
 436
 437 static long long
 438 slotN_contents (char *bundle, int slotnum)
 439 {
 440   return extract_bit_field (bundle, 5+41*slotnum, 41);
 441 }
 442
 443 /* Store an instruction in an instruction bundle */
 444
 445 static void
 446 replace_slotN_contents (char *bundle, long long instr, int slotnum)
 447 {
 448   replace_bit_field (bundle, instr, 5+41*slotnum, 41);
 449 }
 450
 451 static const enum instruction_type template_encoding_table[32][3] =
 452 {
 453   { M, I, I },                          /* 00 */
 454   { M, I, I },                          /* 01 */
 455   { M, I, I },                          /* 02 */
 456   { M, I, I },                          /* 03 */
 457   { M, L, X },                          /* 04 */
 458   { M, L, X },                          /* 05 */
 459   { undefined, undefined, undefined },  /* 06 */
 460   { undefined, undefined, undefined },  /* 07 */
 461   { M, M, I },                          /* 08 */
 462   { M, M, I },                          /* 09 */
 463   { M, M, I },                          /* 0A */
 464   { M, M, I },                          /* 0B */
 465   { M, F, I },                          /* 0C */
 466   { M, F, I },                          /* 0D */
 467   { M, M, F },                          /* 0E */
 468   { M, M, F },                          /* 0F */
 469   { M, I, B },                          /* 10 */
 470   { M, I, B },                          /* 11 */
 471   { M, B, B },                          /* 12 */
 472   { M, B, B },                          /* 13 */
 473   { undefined, undefined, undefined },  /* 14 */
 474   { undefined, undefined, undefined },  /* 15 */
 475   { B, B, B },                          /* 16 */
 476   { B, B, B },                          /* 17 */
 477   { M, M, B },                          /* 18 */
 478   { M, M, B },                          /* 19 */
 479   { undefined, undefined, undefined },  /* 1A */
 480   { undefined, undefined, undefined },  /* 1B */
 481   { M, F, B },                          /* 1C */
 482   { M, F, B },                          /* 1D */
 483   { undefined, undefined, undefined },  /* 1E */
 484   { undefined, undefined, undefined },  /* 1F */
 485 };
 486
 487 /* Fetch and (partially) decode an instruction at ADDR and return the
 488    address of the next instruction to fetch.  */
 489
 490 static CORE_ADDR
 491 fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
 492 {
 493   char bundle[BUNDLE_LEN];
 494   int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
 495   long long template;
 496   int val;
 497
 498   /* Warn about slot numbers greater than 2.  We used to generate
 499      an error here on the assumption that the user entered an invalid
 500      address.  But, sometimes GDB itself requests an invalid address.
 501      This can (easily) happen when execution stops in a function for
 502      which there are no symbols.  The prologue scanner will attempt to
 503      find the beginning of the function - if the nearest symbol
 504      happens to not be aligned on a bundle boundary (16 bytes), the
 505      resulting starting address will cause GDB to think that the slot
 506      number is too large.
 507
 508      So we warn about it and set the slot number to zero.  It is
 509      not necessarily a fatal condition, particularly if debugging
 510      at the assembly language level.  */
 511   if (slotnum > 2)
 512     {
 513       warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
 514                "Using slot 0 instead"));
 515       slotnum = 0;
 516     }
 517
 518   addr &= ~0x0f;
 519
 520   val = target_read_memory (addr, bundle, BUNDLE_LEN);
 521
 522   if (val != 0)
 523     return 0;
 524
 525   *instr = slotN_contents (bundle, slotnum);
 526   template = extract_bit_field (bundle, 0, 5);
 527   *it = template_encoding_table[(int)template][slotnum];
 528
 529   if (slotnum == 2 || (slotnum == 1 && *it == L))
 530     addr += 16;
 531   else
 532     addr += (slotnum + 1) * SLOT_MULTIPLIER;
 533
 534   return addr;
 535 }
 536
 537 /* There are 5 different break instructions (break.i, break.b,
 538    break.m, break.f, and break.x), but they all have the same
 539    encoding.  (The five bit template in the low five bits of the
 540    instruction bundle distinguishes one from another.)
 541
 542    The runtime architecture manual specifies that break instructions
 543    used for debugging purposes must have the upper two bits of the 21
 544    bit immediate set to a 0 and a 1 respectively.  A breakpoint
 545    instruction encodes the most significant bit of its 21 bit
 546    immediate at bit 36 of the 41 bit instruction.  The penultimate msb
 547    is at bit 25 which leads to the pattern below.
 548
 549    Originally, I had this set up to do, e.g, a "break.i 0x80000"  But
 550    it turns out that 0x80000 was used as the syscall break in the early
 551    simulators.  So I changed the pattern slightly to do "break.i 0x080001"
 552    instead.  But that didn't work either (I later found out that this
 553    pattern was used by the simulator that I was using.)  So I ended up
 554    using the pattern seen below.
 555
 556    SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
 557    while we need bit-based addressing as the instructions length is 41 bits and
 558    we must not modify/corrupt the adjacent slots in the same bundle.
 559    Fortunately we may store larger memory incl. the adjacent bits with the
 560    original memory content (not the possibly already stored breakpoints there).
 561    We need to be careful in ia64_memory_remove_breakpoint to always restore
 562    only the specific bits of this instruction ignoring any adjacent stored
 563    bits.
 564
 565    We use the original addressing with the low nibble in the range <0..2> which
 566    gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
 567    as the direct byte offset of SHADOW_CONTENTS.  We store whole BUNDLE_LEN
 568    bytes just without these two possibly skipped bytes to not to exceed to the
 569    next bundle.
 570
 571    If we would like to store the whole bundle to SHADOW_CONTENTS we would have
 572    to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
 573    In such case there is no other place where to store
 574    SLOTNUM (`adress & 0x0f', value in the range <0..2>).  We need to know
 575    SLOTNUM in ia64_memory_remove_breakpoint.
 576
 577    ia64 16-byte bundle layout:
 578    | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
 579
 580    The current addressing used by the code below:
 581    original PC   placed_address   placed_size             required    covered
 582                                   == bp_tgt->shadow_len   reqd \subset covered
 583    0xABCDE0      0xABCDE0         0xE                     <0x0...0x5> <0x0..0xD>
 584    0xABCDE1      0xABCDE1         0xE                     <0x5...0xA> <0x1..0xE>
 585    0xABCDE2      0xABCDE2         0xE                     <0xA...0xF> <0x2..0xF>
 586
 587    `objdump -d' and some other tools show a bit unjustified offsets:
 588    original PC   byte where starts the instruction   objdump offset
 589    0xABCDE0      0xABCDE0                            0xABCDE0
 590    0xABCDE1      0xABCDE5                            0xABCDE6
 591    0xABCDE2      0xABCDEA                            0xABCDEC
 592    */
 593
 594 #define IA64_BREAKPOINT 0x00003333300LL
 595
 596 static int
 597 ia64_memory_insert_breakpoint (struct gdbarch *gdbarch,
 598                                struct bp_target_info *bp_tgt)
 599 {
 600   CORE_ADDR addr = bp_tgt->placed_address;
 601   gdb_byte bundle[BUNDLE_LEN];
 602   int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
 603   long long instr_breakpoint;
 604   int val;
 605   int template;
 606   struct cleanup *cleanup;
 607
 608   if (slotnum > 2)
 609     error (_("Can't insert breakpoint for slot numbers greater than 2."));
 610
 611   addr &= ~0x0f;
 612
 613   /* Disable the automatic memory restoration from breakpoints while
 614      we read our instruction bundle.  Otherwise, the general restoration
 615      mechanism kicks in and we would possibly remove parts of the adjacent
 616      placed breakpoints.  It is due to our SHADOW_CONTENTS overlapping the real
 617      breakpoint instruction bits region.  */
 618   cleanup = make_show_memory_breakpoints_cleanup (1);
 619   val = target_read_memory (addr, bundle, BUNDLE_LEN);
 620
 621   /* Check for L type instruction in slot 1, if present then bump up the slot
 622      number to the slot 2.  */
 623   template = extract_bit_field (bundle, 0, 5);
 624   if (slotnum == 1 && template_encoding_table[template][slotnum] == L)
 625     slotnum = 2;
 626
 627   /* Slot number 2 may skip at most 2 bytes at the beginning.  */
 628   bp_tgt->placed_size = bp_tgt->shadow_len = BUNDLE_LEN - 2;
 629
 630   /* Store the whole bundle, except for the initial skipped bytes by the slot
 631      number interpreted as bytes offset in PLACED_ADDRESS.  */
 632   memcpy (bp_tgt->shadow_contents, bundle + slotnum, bp_tgt->shadow_len);
 633
 634   /* Breakpoints already present in the code will get deteacted and not get
 635      reinserted by bp_loc_is_permanent.  Multiple breakpoints at the same
 636      location cannot induce the internal error as they are optimized into
 637      a single instance by update_global_location_list.  */
 638   instr_breakpoint = slotN_contents (bundle, slotnum);
 639   if (instr_breakpoint == IA64_BREAKPOINT)
 640     internal_error (__FILE__, __LINE__,
 641                     _("Address %s already contains a breakpoint."),
 642                     paddr_nz (bp_tgt->placed_address));
 643   replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
 644
 645   if (val == 0)
 646     val = target_write_memory (addr + slotnum, bundle + slotnum,
 647                                bp_tgt->shadow_len);
 648
 649   do_cleanups (cleanup);
 650   return val;
 651 }
 652
 653 static int
 654 ia64_memory_remove_breakpoint (struct gdbarch *gdbarch,
 655                                struct bp_target_info *bp_tgt)
 656 {
 657   CORE_ADDR addr = bp_tgt->placed_address;
 658   gdb_byte bundle_mem[BUNDLE_LEN], bundle_saved[BUNDLE_LEN];
 659   int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
 660   long long instr_breakpoint, instr_saved;
 661   int val;
 662   int template;
 663   struct cleanup *cleanup;
 664
 665   addr &= ~0x0f;
 666
 667   /* Disable the automatic memory restoration from breakpoints while
 668      we read our instruction bundle.  Otherwise, the general restoration
 669      mechanism kicks in and we would possibly remove parts of the adjacent
 670      placed breakpoints.  It is due to our SHADOW_CONTENTS overlapping the real
 671      breakpoint instruction bits region.  */
 672   cleanup = make_show_memory_breakpoints_cleanup (1);
 673   val = target_read_memory (addr, bundle_mem, BUNDLE_LEN);
 674
 675   /* Check for L type instruction in slot 1, if present then bump up the slot
 676      number to the slot 2.  */
 677   template = extract_bit_field (bundle_mem, 0, 5);
 678   if (slotnum == 1 && template_encoding_table[template][slotnum] == L)
 679     slotnum = 2;
 680
 681   gdb_assert (bp_tgt->placed_size == BUNDLE_LEN - 2);
 682   gdb_assert (bp_tgt->placed_size == bp_tgt->shadow_len);
 683
 684   instr_breakpoint = slotN_contents (bundle_mem, slotnum);
 685   if (instr_breakpoint != IA64_BREAKPOINT)
 686     {
 687       warning (_("Cannot remove breakpoint at address %s, "
 688                  "no break instruction at such address."),
 689                paddr_nz (bp_tgt->placed_address));
 690       return -1;
 691     }
 692
 693   /* Extract the original saved instruction from SLOTNUM normalizing its
 694      bit-shift for INSTR_SAVED.  */
 695   memcpy (bundle_saved, bundle_mem, BUNDLE_LEN);
 696   memcpy (bundle_saved + slotnum, bp_tgt->shadow_contents, bp_tgt->shadow_len);
 697   instr_saved = slotN_contents (bundle_saved, slotnum);
 698
 699   /* In BUNDLE_MEM be careful to modify only the bits belonging to SLOTNUM and
 700      never any other possibly also stored in SHADOW_CONTENTS.  */
 701   replace_slotN_contents (bundle_mem, instr_saved, slotnum);
 702   if (val == 0)
 703     val = target_write_memory (addr, bundle_mem, BUNDLE_LEN);
 704
 705   do_cleanups (cleanup);
 706   return val;
 707 }
 708
 709 /* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
 710    instruction slots ranges are bit-granular (41 bits) we have to provide an
 711    extended range as described for ia64_memory_insert_breakpoint.  We also take
 712    care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
 713    make a match for permanent breakpoints.  */
 714
 715 static const gdb_byte *
 716 ia64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
 717 {
 718   CORE_ADDR addr = *pcptr;
 719   static gdb_byte bundle[BUNDLE_LEN];
 720   int slotnum = (int) (*pcptr & 0x0f) / SLOT_MULTIPLIER;
 721   long long instr_fetched;
 722   int val;
 723   int template;
 724   struct cleanup *cleanup;
 725
 726   if (slotnum > 2)
 727     error (_("Can't insert breakpoint for slot numbers greater than 2."));
 728
 729   addr &= ~0x0f;
 730
 731   /* Enable the automatic memory restoration from breakpoints while
 732      we read our instruction bundle to match bp_loc_is_permanent.  */
 733   cleanup = make_show_memory_breakpoints_cleanup (0);
 734   val = target_read_memory (addr, bundle, BUNDLE_LEN);
 735   do_cleanups (cleanup);
 736
 737   /* The memory might be unreachable.  This can happen, for instance,
 738      when the user inserts a breakpoint at an invalid address.  */
 739   if (val != 0)
 740     return NULL;
 741
 742   /* Check for L type instruction in slot 1, if present then bump up the slot
 743      number to the slot 2.  */
 744   template = extract_bit_field (bundle, 0, 5);
 745   if (slotnum == 1 && template_encoding_table[template][slotnum] == L)
 746     slotnum = 2;
 747
 748   /* A break instruction has its all its opcode bits cleared except for
 749      the parameter value.  For L+X slot pair we are at the X slot (slot 2) so
 750      we should not touch the L slot - the upper 41 bits of the parameter.  */
 751   instr_fetched = slotN_contents (bundle, slotnum);
 752   instr_fetched &= 0x1003ffffc0LL;
 753   replace_slotN_contents (bundle, instr_fetched, slotnum);
 754
 755   *lenptr = BUNDLE_LEN - 2;
 756
 757   /* SLOTNUM is possibly already locally modified - use caller's *PCPTR.  */
 758   return bundle + (*pcptr & 0x0f);
 759 }
 760
 761 static CORE_ADDR
 762 ia64_read_pc (struct regcache *regcache)
 763 {
 764   ULONGEST psr_value, pc_value;
 765   int slot_num;
 766
 767   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
 768   regcache_cooked_read_unsigned (regcache, IA64_IP_REGNUM, &pc_value);
 769   slot_num = (psr_value >> 41) & 3;
 770
 771   return pc_value | (slot_num * SLOT_MULTIPLIER);
 772 }
 773
 774 void
 775 ia64_write_pc (struct regcache *regcache, CORE_ADDR new_pc)
 776 {
 777   int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
 778   ULONGEST psr_value;
 779
 780   regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr_value);
 781   psr_value &= ~(3LL << 41);
 782   psr_value |= (ULONGEST)(slot_num & 0x3) << 41;
 783
 784   new_pc &= ~0xfLL;
 785
 786   regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr_value);
 787   regcache_cooked_write_unsigned (regcache, IA64_IP_REGNUM, new_pc);
 788 }
 789
 790 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
 791
 792 /* Returns the address of the slot that's NSLOTS slots away from
 793    the address ADDR. NSLOTS may be positive or negative. */
 794 static CORE_ADDR
 795 rse_address_add(CORE_ADDR addr, int nslots)
 796 {
 797   CORE_ADDR new_addr;
 798   int mandatory_nat_slots = nslots / 63;
 799   int direction = nslots < 0 ? -1 : 1;
 800
 801   new_addr = addr + 8 * (nslots + mandatory_nat_slots);
 802
 803   if ((new_addr >> 9)  != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
 804     new_addr += 8 * direction;
 805
 806   if (IS_NaT_COLLECTION_ADDR(new_addr))
 807     new_addr += 8 * direction;
 808
 809   return new_addr;
 810 }
 811
 812 static void
 813 ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
 814                            int regnum, gdb_byte *buf)
 815 {
 816   if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
 817     {
 818 #ifdef HAVE_LIBUNWIND_IA64_H
 819       /* First try and use the libunwind special reg accessor, otherwise fallback to
 820          standard logic.  */
 821       if (!libunwind_is_initialized ()
 822           || libunwind_get_reg_special (gdbarch, regcache, regnum, buf) != 0)
 823 #endif
 824         {
 825           /* The fallback position is to assume that r32-r127 are found sequentially
 826              in memory starting at $bof.  This isn't always true, but without libunwind,
 827              this is the best we can do.  */
 828           ULONGEST cfm;
 829           ULONGEST bsp;
 830           CORE_ADDR reg;
 831           regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
 832           regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 833
 834           /* The bsp points at the end of the register frame so we
 835              subtract the size of frame from it to get start of register frame.  */
 836           bsp = rse_address_add (bsp, -(cfm & 0x7f));
 837
 838           if ((cfm & 0x7f) > regnum - V32_REGNUM)
 839             {
 840               ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
 841               reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
 842               store_unsigned_integer (buf, register_size (gdbarch, regnum), reg);
 843             }
 844           else
 845             store_unsigned_integer (buf, register_size (gdbarch, regnum), 0);
 846         }
 847     }
 848   else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
 849     {
 850       ULONGEST unatN_val;
 851       ULONGEST unat;
 852       regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
 853       unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
 854       store_unsigned_integer (buf, register_size (gdbarch, regnum), unatN_val);
 855     }
 856   else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
 857     {
 858       ULONGEST natN_val = 0;
 859       ULONGEST bsp;
 860       ULONGEST cfm;
 861       CORE_ADDR gr_addr = 0;
 862       regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
 863       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 864
 865       /* The bsp points at the end of the register frame so we
 866          subtract the size of frame from it to get start of register frame.  */
 867       bsp = rse_address_add (bsp, -(cfm & 0x7f));
 868
 869       if ((cfm & 0x7f) > regnum - V32_REGNUM)
 870         gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
 871
 872       if (gr_addr != 0)
 873         {
 874           /* Compute address of nat collection bits.  */
 875           CORE_ADDR nat_addr = gr_addr | 0x1f8;
 876           CORE_ADDR nat_collection;
 877           int nat_bit;
 878           /* If our nat collection address is bigger than bsp, we have to get
 879              the nat collection from rnat.  Otherwise, we fetch the nat
 880              collection from the computed address.  */
 881           if (nat_addr >= bsp)
 882             regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
 883           else
 884             nat_collection = read_memory_integer (nat_addr, 8);
 885           nat_bit = (gr_addr >> 3) & 0x3f;
 886           natN_val = (nat_collection >> nat_bit) & 1;
 887         }
 888
 889       store_unsigned_integer (buf, register_size (gdbarch, regnum), natN_val);
 890     }
 891   else if (regnum == VBOF_REGNUM)
 892     {
 893       /* A virtual register frame start is provided for user convenience.
 894          It can be calculated as the bsp - sof (sizeof frame). */
 895       ULONGEST bsp, vbsp;
 896       ULONGEST cfm;
 897       CORE_ADDR reg;
 898       regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
 899       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 900
 901       /* The bsp points at the end of the register frame so we
 902          subtract the size of frame from it to get beginning of frame.  */
 903       vbsp = rse_address_add (bsp, -(cfm & 0x7f));
 904       store_unsigned_integer (buf, register_size (gdbarch, regnum), vbsp);
 905     }
 906   else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
 907     {
 908       ULONGEST pr;
 909       ULONGEST cfm;
 910       ULONGEST prN_val;
 911       CORE_ADDR reg;
 912       regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
 913       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 914
 915       if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
 916         {
 917           /* Fetch predicate register rename base from current frame
 918              marker for this frame. */
 919           int rrb_pr = (cfm >> 32) & 0x3f;
 920
 921           /* Adjust the register number to account for register rotation. */
 922           regnum = VP16_REGNUM
 923                  + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
 924         }
 925       prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
 926       store_unsigned_integer (buf, register_size (gdbarch, regnum), prN_val);
 927     }
 928   else
 929     memset (buf, 0, register_size (gdbarch, regnum));
 930 }
 931
 932 static void
 933 ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
 934                             int regnum, const gdb_byte *buf)
 935 {
 936   if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
 937     {
 938       ULONGEST bsp;
 939       ULONGEST cfm;
 940       CORE_ADDR reg;
 941       regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
 942       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 943
 944       bsp = rse_address_add (bsp, -(cfm & 0x7f));
 945
 946       if ((cfm & 0x7f) > regnum - V32_REGNUM)
 947         {
 948           ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
 949           write_memory (reg_addr, (void *)buf, 8);
 950         }
 951     }
 952   else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
 953     {
 954       ULONGEST unatN_val, unat, unatN_mask;
 955       regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
 956       unatN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
 957       unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
 958       if (unatN_val == 0)
 959         unat &= ~unatN_mask;
 960       else if (unatN_val == 1)
 961         unat |= unatN_mask;
 962       regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
 963     }
 964   else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
 965     {
 966       ULONGEST natN_val;
 967       ULONGEST bsp;
 968       ULONGEST cfm;
 969       CORE_ADDR gr_addr = 0;
 970       regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
 971       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
 972
 973       /* The bsp points at the end of the register frame so we
 974          subtract the size of frame from it to get start of register frame.  */
 975       bsp = rse_address_add (bsp, -(cfm & 0x7f));
 976
 977       if ((cfm & 0x7f) > regnum - V32_REGNUM)
 978         gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
 979
 980       natN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
 981
 982       if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
 983         {
 984           /* Compute address of nat collection bits.  */
 985           CORE_ADDR nat_addr = gr_addr | 0x1f8;
 986           CORE_ADDR nat_collection;
 987           int natN_bit = (gr_addr >> 3) & 0x3f;
 988           ULONGEST natN_mask = (1LL << natN_bit);
 989           /* If our nat collection address is bigger than bsp, we have to get
 990              the nat collection from rnat.  Otherwise, we fetch the nat
 991              collection from the computed address.  */
 992           if (nat_addr >= bsp)
 993             {
 994               regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
 995               if (natN_val)
 996                 nat_collection |= natN_mask;
 997               else
 998                 nat_collection &= ~natN_mask;
 999               regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
1000             }
1001           else
1002             {
1003               char nat_buf[8];
1004               nat_collection = read_memory_integer (nat_addr, 8);
1005               if (natN_val)
1006                 nat_collection |= natN_mask;
1007               else
1008                 nat_collection &= ~natN_mask;
1009               store_unsigned_integer (nat_buf, register_size (gdbarch, regnum), nat_collection);
1010               write_memory (nat_addr, nat_buf, 8);
1011             }
1012         }
1013     }
1014   else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1015     {
1016       ULONGEST pr;
1017       ULONGEST cfm;
1018       ULONGEST prN_val;
1019       ULONGEST prN_mask;
1020
1021       regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
1022       regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
1023
1024       if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1025         {
1026           /* Fetch predicate register rename base from current frame
1027              marker for this frame. */
1028           int rrb_pr = (cfm >> 32) & 0x3f;
1029
1030           /* Adjust the register number to account for register rotation. */
1031           regnum = VP16_REGNUM
1032                  + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1033         }
1034       prN_val = extract_unsigned_integer (buf, register_size (gdbarch, regnum));
1035       prN_mask = (1LL << (regnum - VP0_REGNUM));
1036       if (prN_val == 0)
1037         pr &= ~prN_mask;
1038       else if (prN_val == 1)
1039         pr |= prN_mask;
1040       regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
1041     }
1042 }
1043
1044 /* The ia64 needs to convert between various ieee floating-point formats
1045    and the special ia64 floating point register format.  */
1046
1047 static int
1048 ia64_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type)
1049 {
1050   return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM
1051           && type != builtin_type_ia64_ext);
1052 }
1053
1054 static void
1055 ia64_register_to_value (struct frame_info *frame, int regnum,
1056                          struct type *valtype, gdb_byte *out)
1057 {
1058   char in[MAX_REGISTER_SIZE];
1059   frame_register_read (frame, regnum, in);
1060   convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
1061 }
1062
1063 static void
1064 ia64_value_to_register (struct frame_info *frame, int regnum,
1065                          struct type *valtype, const gdb_byte *in)
1066 {
1067   char out[MAX_REGISTER_SIZE];
1068   convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
1069   put_frame_register (frame, regnum, out);
1070 }
1071
1072
1073 /* Limit the number of skipped non-prologue instructions since examining
1074    of the prologue is expensive.  */
1075 static int max_skip_non_prologue_insns = 40;
1076
1077 /* Given PC representing the starting address of a function, and
1078    LIM_PC which is the (sloppy) limit to which to scan when looking
1079    for a prologue, attempt to further refine this limit by using
1080    the line data in the symbol table.  If successful, a better guess
1081    on where the prologue ends is returned, otherwise the previous
1082    value of lim_pc is returned.  TRUST_LIMIT is a pointer to a flag
1083    which will be set to indicate whether the returned limit may be
1084    used with no further scanning in the event that the function is
1085    frameless.  */
1086
1087 /* FIXME: cagney/2004-02-14: This function and logic have largely been
1088    superseded by skip_prologue_using_sal.  */
1089
1090 static CORE_ADDR
1091 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
1092 {
1093   struct symtab_and_line prologue_sal;
1094   CORE_ADDR start_pc = pc;
1095   CORE_ADDR end_pc;
1096
1097   /* The prologue can not possibly go past the function end itself,
1098      so we can already adjust LIM_PC accordingly.  */
1099   if (find_pc_partial_function (pc, NULL, NULL, &end_pc) && end_pc < lim_pc)
1100     lim_pc = end_pc;
1101
1102   /* Start off not trusting the limit.  */
1103   *trust_limit = 0;
1104
1105   prologue_sal = find_pc_line (pc, 0);
1106   if (prologue_sal.line != 0)
1107     {
1108       int i;
1109       CORE_ADDR addr = prologue_sal.end;
1110
1111       /* Handle the case in which compiler's optimizer/scheduler
1112          has moved instructions into the prologue.  We scan ahead
1113          in the function looking for address ranges whose corresponding
1114          line number is less than or equal to the first one that we
1115          found for the function.  (It can be less than when the
1116          scheduler puts a body instruction before the first prologue
1117          instruction.)  */
1118       for (i = 2 * max_skip_non_prologue_insns;
1119            i > 0 && (lim_pc == 0 || addr < lim_pc);
1120            i--)
1121         {
1122           struct symtab_and_line sal;
1123
1124           sal = find_pc_line (addr, 0);
1125           if (sal.line == 0)
1126             break;
1127           if (sal.line <= prologue_sal.line
1128               && sal.symtab == prologue_sal.symtab)
1129             {
1130               prologue_sal = sal;
1131             }
1132           addr = sal.end;
1133         }
1134
1135       if (lim_pc == 0 || prologue_sal.end < lim_pc)
1136         {
1137           lim_pc = prologue_sal.end;
1138           if (start_pc == get_pc_function_start (lim_pc))
1139             *trust_limit = 1;
1140         }
1141     }
1142   return lim_pc;
1143 }
1144
1145 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1146   || (8 <= (_regnum_) && (_regnum_) <= 11) \
1147   || (14 <= (_regnum_) && (_regnum_) <= 31))
1148 #define imm9(_instr_) \
1149   ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1150    | (((_instr_) & 0x00008000000LL) >> 20) \
1151    | (((_instr_) & 0x00000001fc0LL) >> 6))
1152
1153 /* Allocate and initialize a frame cache.  */
1154
1155 static struct ia64_frame_cache *
1156 ia64_alloc_frame_cache (void)
1157 {
1158   struct ia64_frame_cache *cache;
1159   int i;
1160
1161   cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1162
1163   /* Base address.  */
1164   cache->base = 0;
1165   cache->pc = 0;
1166   cache->cfm = 0;
1167   cache->prev_cfm = 0;
1168   cache->sof = 0;
1169   cache->sol = 0;
1170   cache->sor = 0;
1171   cache->bsp = 0;
1172   cache->fp_reg = 0;
1173   cache->frameless = 1;
1174
1175   for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1176     cache->saved_regs[i] = 0;
1177
1178   return cache;
1179 }
1180
1181 static CORE_ADDR
1182 examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc,
1183                   struct frame_info *this_frame,
1184                   struct ia64_frame_cache *cache)
1185 {
1186   CORE_ADDR next_pc;
1187   CORE_ADDR last_prologue_pc = pc;
1188   instruction_type it;
1189   long long instr;
1190   int cfm_reg  = 0;
1191   int ret_reg  = 0;
1192   int fp_reg   = 0;
1193   int unat_save_reg = 0;
1194   int pr_save_reg = 0;
1195   int mem_stack_frame_size = 0;
1196   int spill_reg   = 0;
1197   CORE_ADDR spill_addr = 0;
1198   char instores[8];
1199   char infpstores[8];
1200   char reg_contents[256];
1201   int trust_limit;
1202   int frameless = 1;
1203   int i;
1204   CORE_ADDR addr;
1205   char buf[8];
1206   CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
1207
1208   memset (instores, 0, sizeof instores);
1209   memset (infpstores, 0, sizeof infpstores);
1210   memset (reg_contents, 0, sizeof reg_contents);
1211
1212   if (cache->after_prologue != 0
1213       && cache->after_prologue <= lim_pc)
1214     return cache->after_prologue;
1215
1216   lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
1217   next_pc = fetch_instruction (pc, &it, &instr);
1218
1219   /* We want to check if we have a recognizable function start before we
1220      look ahead for a prologue.  */
1221   if (pc < lim_pc && next_pc
1222       && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1223     {
1224       /* alloc - start of a regular function.  */
1225       int sor = (int) ((instr & 0x00078000000LL) >> 27);
1226       int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1227       int sof = (int) ((instr & 0x000000fe000LL) >> 13);
1228       int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1229
1230       /* Verify that the current cfm matches what we think is the
1231          function start.  If we have somehow jumped within a function,
1232          we do not want to interpret the prologue and calculate the
1233          addresses of various registers such as the return address.
1234          We will instead treat the frame as frameless. */
1235       if (!this_frame ||
1236           (sof == (cache->cfm & 0x7f) &&
1237            sol == ((cache->cfm >> 7) & 0x7f)))
1238         frameless = 0;
1239
1240       cfm_reg = rN;
1241       last_prologue_pc = next_pc;
1242       pc = next_pc;
1243     }
1244   else
1245     {
1246       /* Look for a leaf routine.  */
1247       if (pc < lim_pc && next_pc
1248           && (it == I || it == M)
1249           && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1250         {
1251           /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1252           int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1253                            | ((instr & 0x001f8000000LL) >> 20)
1254                            | ((instr & 0x000000fe000LL) >> 13));
1255           int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1256           int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1257           int qp = (int) (instr & 0x0000000003fLL);
1258           if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1259             {
1260               /* mov r2, r12 - beginning of leaf routine */
1261               fp_reg = rN;
1262               last_prologue_pc = next_pc;
1263             }
1264         }
1265
1266       /* If we don't recognize a regular function or leaf routine, we are
1267          done.  */
1268       if (!fp_reg)
1269         {
1270           pc = lim_pc;
1271           if (trust_limit)
1272             last_prologue_pc = lim_pc;
1273         }
1274     }
1275
1276   /* Loop, looking for prologue instructions, keeping track of
1277      where preserved registers were spilled. */
1278   while (pc < lim_pc)
1279     {
1280       next_pc = fetch_instruction (pc, &it, &instr);
1281       if (next_pc == 0)
1282         break;
1283
1284       if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
1285         {
1286           /* Exit loop upon hitting a non-nop branch instruction. */
1287           if (trust_limit)
1288             lim_pc = pc;
1289           break;
1290         }
1291       else if (((instr & 0x3fLL) != 0LL) &&
1292                (frameless || ret_reg != 0))
1293         {
1294           /* Exit loop upon hitting a predicated instruction if
1295              we already have the return register or if we are frameless.  */
1296           if (trust_limit)
1297             lim_pc = pc;
1298           break;
1299         }
1300       else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
1301         {
1302           /* Move from BR */
1303           int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1304           int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1305           int qp = (int) (instr & 0x0000000003f);
1306
1307           if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1308             {
1309               ret_reg = rN;
1310               last_prologue_pc = next_pc;
1311             }
1312         }
1313       else if ((it == I || it == M)
1314           && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1315         {
1316           /* adds rN = imm14, rM   (or mov rN, rM  when imm14 is 0) */
1317           int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1318                            | ((instr & 0x001f8000000LL) >> 20)
1319                            | ((instr & 0x000000fe000LL) >> 13));
1320           int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1321           int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1322           int qp = (int) (instr & 0x0000000003fLL);
1323
1324           if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1325             {
1326               /* mov rN, r12 */
1327               fp_reg = rN;
1328               last_prologue_pc = next_pc;
1329             }
1330           else if (qp == 0 && rN == 12 && rM == 12)
1331             {
1332               /* adds r12, -mem_stack_frame_size, r12 */
1333               mem_stack_frame_size -= imm;
1334               last_prologue_pc = next_pc;
1335             }
1336           else if (qp == 0 && rN == 2
1337                 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1338             {
1339               char buf[MAX_REGISTER_SIZE];
1340               CORE_ADDR saved_sp = 0;
1341               /* adds r2, spilloffset, rFramePointer
1342                    or
1343                  adds r2, spilloffset, r12
1344
1345                  Get ready for stf.spill or st8.spill instructions.
1346                  The address to start spilling at is loaded into r2.
1347                  FIXME:  Why r2?  That's what gcc currently uses; it
1348                  could well be different for other compilers.  */
1349
1350               /* Hmm... whether or not this will work will depend on
1351                  where the pc is.  If it's still early in the prologue
1352                  this'll be wrong.  FIXME */
1353               if (this_frame)
1354                 {
1355                   get_frame_register (this_frame, sp_regnum, buf);
1356                   saved_sp = extract_unsigned_integer (buf, 8);
1357                 }
1358               spill_addr  = saved_sp
1359                           + (rM == 12 ? 0 : mem_stack_frame_size)
1360                           + imm;
1361               spill_reg   = rN;
1362               last_prologue_pc = next_pc;
1363             }
1364           else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM-32] &&
1365                    rN < 256 && imm == 0)
1366             {
1367               /* mov rN, rM where rM is an input register */
1368               reg_contents[rN] = rM;
1369               last_prologue_pc = next_pc;
1370             }
1371           else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1372                    rM == 2)
1373             {
1374               /* mov r12, r2 */
1375               last_prologue_pc = next_pc;
1376               break;
1377             }
1378         }
1379       else if (it == M
1380             && (   ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1381                 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1382         {
1383           /* stf.spill [rN] = fM, imm9
1384              or
1385              stf.spill [rN] = fM  */
1386
1387           int imm = imm9(instr);
1388           int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1389           int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1390           int qp = (int) (instr & 0x0000000003fLL);
1391           if (qp == 0 && rN == spill_reg && spill_addr != 0
1392               && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1393             {
1394               cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
1395
1396               if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1397                 spill_addr += imm;
1398               else
1399                 spill_addr = 0;         /* last one; must be done */
1400               last_prologue_pc = next_pc;
1401             }
1402         }
1403       else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1404             || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1405         {
1406           /* mov.m rN = arM
1407                or
1408              mov.i rN = arM */
1409
1410           int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1411           int rN  = (int) ((instr & 0x00000001fc0LL) >> 6);
1412           int qp  = (int) (instr & 0x0000000003fLL);
1413           if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1414             {
1415               /* We have something like "mov.m r3 = ar.unat".  Remember the
1416                  r3 (or whatever) and watch for a store of this register... */
1417               unat_save_reg = rN;
1418               last_prologue_pc = next_pc;
1419             }
1420         }
1421       else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1422         {
1423           /* mov rN = pr */
1424           int rN  = (int) ((instr & 0x00000001fc0LL) >> 6);
1425           int qp  = (int) (instr & 0x0000000003fLL);
1426           if (qp == 0 && isScratch (rN))
1427             {
1428               pr_save_reg = rN;
1429               last_prologue_pc = next_pc;
1430             }
1431         }
1432       else if (it == M
1433             && (   ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1434                 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1435         {
1436           /* st8 [rN] = rM
1437               or
1438              st8 [rN] = rM, imm9 */
1439           int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1440           int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1441           int qp = (int) (instr & 0x0000000003fLL);
1442           int indirect = rM < 256 ? reg_contents[rM] : 0;
1443           if (qp == 0 && rN == spill_reg && spill_addr != 0
1444               && (rM == unat_save_reg || rM == pr_save_reg))
1445             {
1446               /* We've found a spill of either the UNAT register or the PR
1447                  register.  (Well, not exactly; what we've actually found is
1448                  a spill of the register that UNAT or PR was moved to).
1449                  Record that fact and move on... */
1450               if (rM == unat_save_reg)
1451                 {
1452                   /* Track UNAT register */
1453                   cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
1454                   unat_save_reg = 0;
1455                 }
1456               else
1457                 {
1458                   /* Track PR register */
1459                   cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
1460                   pr_save_reg = 0;
1461                 }
1462               if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1463                 /* st8 [rN] = rM, imm9 */
1464                 spill_addr += imm9(instr);
1465               else
1466                 spill_addr = 0;         /* must be done spilling */
1467               last_prologue_pc = next_pc;
1468             }
1469           else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1470             {
1471               /* Allow up to one store of each input register. */
1472               instores[rM-32] = 1;
1473               last_prologue_pc = next_pc;
1474             }
1475           else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1476                    !instores[indirect-32])
1477             {
1478               /* Allow an indirect store of an input register.  */
1479               instores[indirect-32] = 1;
1480               last_prologue_pc = next_pc;
1481             }
1482         }
1483       else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1484         {
1485           /* One of
1486                st1 [rN] = rM
1487                st2 [rN] = rM
1488                st4 [rN] = rM
1489                st8 [rN] = rM
1490              Note that the st8 case is handled in the clause above.
1491
1492              Advance over stores of input registers. One store per input
1493              register is permitted. */
1494           int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1495           int qp = (int) (instr & 0x0000000003fLL);
1496           int indirect = rM < 256 ? reg_contents[rM] : 0;
1497           if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1498             {
1499               instores[rM-32] = 1;
1500               last_prologue_pc = next_pc;
1501             }
1502           else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1503                    !instores[indirect-32])
1504             {
1505               /* Allow an indirect store of an input register.  */
1506               instores[indirect-32] = 1;
1507               last_prologue_pc = next_pc;
1508             }
1509         }
1510       else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1511         {
1512           /* Either
1513                stfs [rN] = fM
1514              or
1515                stfd [rN] = fM
1516
1517              Advance over stores of floating point input registers.  Again
1518              one store per register is permitted */
1519           int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1520           int qp = (int) (instr & 0x0000000003fLL);
1521           if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1522             {
1523               infpstores[fM-8] = 1;
1524               last_prologue_pc = next_pc;
1525             }
1526         }
1527       else if (it == M
1528             && (   ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1529                 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1530         {
1531           /* st8.spill [rN] = rM
1532                or
1533              st8.spill [rN] = rM, imm9 */
1534           int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1535           int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1536           int qp = (int) (instr & 0x0000000003fLL);
1537           if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1538             {
1539               /* We've found a spill of one of the preserved general purpose
1540                  regs.  Record the spill address and advance the spill
1541                  register if appropriate. */
1542               cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
1543               if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1544                 /* st8.spill [rN] = rM, imm9 */
1545                 spill_addr += imm9(instr);
1546               else
1547                 spill_addr = 0;         /* Done spilling */
1548               last_prologue_pc = next_pc;
1549             }
1550         }
1551
1552       pc = next_pc;
1553     }
1554
1555   /* If not frameless and we aren't called by skip_prologue, then we need
1556      to calculate registers for the previous frame which will be needed
1557      later.  */
1558
1559   if (!frameless && this_frame)
1560     {
1561       /* Extract the size of the rotating portion of the stack
1562          frame and the register rename base from the current
1563          frame marker. */
1564       cfm = cache->cfm;
1565       sor = cache->sor;
1566       sof = cache->sof;
1567       sol = cache->sol;
1568       rrb_gr = (cfm >> 18) & 0x7f;
1569
1570       /* Find the bof (beginning of frame).  */
1571       bof = rse_address_add (cache->bsp, -sof);
1572
1573       for (i = 0, addr = bof;
1574            i < sof;
1575            i++, addr += 8)
1576         {
1577           if (IS_NaT_COLLECTION_ADDR (addr))
1578             {
1579               addr += 8;
1580             }
1581           if (i+32 == cfm_reg)
1582             cache->saved_regs[IA64_CFM_REGNUM] = addr;
1583           if (i+32 == ret_reg)
1584             cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1585           if (i+32 == fp_reg)
1586             cache->saved_regs[IA64_VFP_REGNUM] = addr;
1587         }
1588
1589       /* For the previous argument registers we require the previous bof.
1590          If we can't find the previous cfm, then we can do nothing.  */
1591       cfm = 0;
1592       if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1593         {
1594           cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
1595         }
1596       else if (cfm_reg != 0)
1597         {
1598           get_frame_register (this_frame, cfm_reg, buf);
1599           cfm = extract_unsigned_integer (buf, 8);
1600         }
1601       cache->prev_cfm = cfm;
1602
1603       if (cfm != 0)
1604         {
1605           sor = ((cfm >> 14) & 0xf) * 8;
1606           sof = (cfm & 0x7f);
1607           sol = (cfm >> 7) & 0x7f;
1608           rrb_gr = (cfm >> 18) & 0x7f;
1609
1610           /* The previous bof only requires subtraction of the sol (size of
1611              locals) due to the overlap between output and input of
1612              subsequent frames.  */
1613           bof = rse_address_add (bof, -sol);
1614
1615           for (i = 0, addr = bof;
1616                i < sof;
1617                i++, addr += 8)
1618             {
1619               if (IS_NaT_COLLECTION_ADDR (addr))
1620                 {
1621                   addr += 8;
1622                 }
1623               if (i < sor)
1624                 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1625                   = addr;
1626               else
1627                 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1628             }
1629
1630         }
1631     }
1632
1633   /* Try and trust the lim_pc value whenever possible.  */
1634   if (trust_limit && lim_pc >= last_prologue_pc)
1635     last_prologue_pc = lim_pc;
1636
1637   cache->frameless = frameless;
1638   cache->after_prologue = last_prologue_pc;
1639   cache->mem_stack_frame_size = mem_stack_frame_size;
1640   cache->fp_reg = fp_reg;
1641
1642   return last_prologue_pc;
1643 }
1644
1645 CORE_ADDR
1646 ia64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1647 {
1648   struct ia64_frame_cache cache;
1649   cache.base = 0;
1650   cache.after_prologue = 0;
1651   cache.cfm = 0;
1652   cache.bsp = 0;
1653
1654   /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send.  */
1655   return examine_prologue (pc, pc+1024, 0, &cache);
1656 }
1657
1658
1659 /* Normal frames.  */
1660
1661 static struct ia64_frame_cache *
1662 ia64_frame_cache (struct frame_info *this_frame, void **this_cache)
1663 {
1664   struct ia64_frame_cache *cache;
1665   char buf[8];
1666   CORE_ADDR cfm, sof, sol, bsp, psr;
1667   int i;
1668
1669   if (*this_cache)
1670     return *this_cache;
1671
1672   cache = ia64_alloc_frame_cache ();
1673   *this_cache = cache;
1674
1675   get_frame_register (this_frame, sp_regnum, buf);
1676   cache->saved_sp = extract_unsigned_integer (buf, 8);
1677
1678   /* We always want the bsp to point to the end of frame.
1679      This way, we can always get the beginning of frame (bof)
1680      by subtracting frame size.  */
1681   get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
1682   cache->bsp = extract_unsigned_integer (buf, 8);
1683
1684   get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
1685   psr = extract_unsigned_integer (buf, 8);
1686
1687   get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
1688   cfm = extract_unsigned_integer (buf, 8);
1689
1690   cache->sof = (cfm & 0x7f);
1691   cache->sol = (cfm >> 7) & 0x7f;
1692   cache->sor = ((cfm >> 14) & 0xf) * 8;
1693
1694   cache->cfm = cfm;
1695
1696   cache->pc = get_frame_func (this_frame);
1697
1698   if (cache->pc != 0)
1699     examine_prologue (cache->pc, get_frame_pc (this_frame), this_frame, cache);
1700
1701   cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1702
1703   return cache;
1704 }
1705
1706 static void
1707 ia64_frame_this_id (struct frame_info *this_frame, void **this_cache,
1708                     struct frame_id *this_id)
1709 {
1710   struct ia64_frame_cache *cache =
1711     ia64_frame_cache (this_frame, this_cache);
1712
1713   /* If outermost frame, mark with null frame id.  */
1714   if (cache->base == 0)
1715     (*this_id) = null_frame_id;
1716   else
1717     (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
1718   if (gdbarch_debug >= 1)
1719     fprintf_unfiltered (gdb_stdlog,
1720                         "regular frame id: code 0x%s, stack 0x%s, special 0x%s, this_frame %p\n",
1721                         paddr_nz (this_id->code_addr),
1722                         paddr_nz (this_id->stack_addr),
1723                         paddr_nz (cache->bsp), this_frame);
1724 }
1725
1726 static struct value *
1727 ia64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
1728                           int regnum)
1729 {
1730   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1731   struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
1732   char buf[8];
1733
1734   gdb_assert (regnum >= 0);
1735
1736   if (!target_has_registers)
1737     error (_("No registers."));
1738
1739   if (regnum == gdbarch_sp_regnum (gdbarch))
1740     return frame_unwind_got_constant (this_frame, regnum, cache->base);
1741
1742   else if (regnum == IA64_BSP_REGNUM)
1743     {
1744       struct value *val;
1745       CORE_ADDR prev_cfm, bsp, prev_bsp;
1746
1747       /* We want to calculate the previous bsp as the end of the previous
1748          register stack frame.  This corresponds to what the hardware bsp
1749          register will be if we pop the frame back which is why we might
1750          have been called.  We know the beginning of the current frame is
1751          cache->bsp - cache->sof.  This value in the previous frame points
1752          to the start of the output registers.  We can calculate the end of
1753          that frame by adding the size of output:
1754             (sof (size of frame) - sol (size of locals)).  */
1755       val = ia64_frame_prev_register (this_frame, this_cache, IA64_CFM_REGNUM);
1756       prev_cfm = extract_unsigned_integer (value_contents_all (val), 8);
1757       bsp = rse_address_add (cache->bsp, -(cache->sof));
1758       prev_bsp =
1759         rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1760
1761       return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
1762     }
1763
1764   else if (regnum == IA64_CFM_REGNUM)
1765     {
1766       CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1767
1768       if (addr != 0)
1769         return frame_unwind_got_memory (this_frame, regnum, addr);
1770
1771       if (cache->prev_cfm)
1772         return frame_unwind_got_constant (this_frame, regnum, cache->prev_cfm);
1773
1774       if (cache->frameless)
1775         return frame_unwind_got_register (this_frame, IA64_PFS_REGNUM,
1776                                           IA64_PFS_REGNUM);
1777       return frame_unwind_got_register (this_frame, regnum, 0);
1778     }
1779
1780   else if (regnum == IA64_VFP_REGNUM)
1781     {
1782       /* If the function in question uses an automatic register (r32-r127)
1783          for the frame pointer, it'll be found by ia64_find_saved_register()
1784          above.  If the function lacks one of these frame pointers, we can
1785          still provide a value since we know the size of the frame.  */
1786       return frame_unwind_got_constant (this_frame, regnum, cache->base);
1787     }
1788
1789   else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
1790     {
1791       struct value *pr_val;
1792       ULONGEST prN;
1793
1794       pr_val = ia64_frame_prev_register (this_frame, this_cache,
1795                                          IA64_PR_REGNUM);
1796       if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
1797         {
1798           /* Fetch predicate register rename base from current frame
1799              marker for this frame.  */
1800           int rrb_pr = (cache->cfm >> 32) & 0x3f;
1801
1802           /* Adjust the register number to account for register rotation.  */
1803           regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
1804         }
1805       prN = extract_bit_field (value_contents_all (pr_val),
1806                                regnum - VP0_REGNUM, 1);
1807       return frame_unwind_got_constant (this_frame, regnum, prN);
1808     }
1809
1810   else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1811     {
1812       struct value *unat_val;
1813       ULONGEST unatN;
1814       unat_val = ia64_frame_prev_register (this_frame, this_cache,
1815                                            IA64_UNAT_REGNUM);
1816       unatN = extract_bit_field (value_contents_all (unat_val),
1817                                  regnum - IA64_NAT0_REGNUM, 1);
1818       return frame_unwind_got_constant (this_frame, regnum, unatN);
1819     }
1820
1821   else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1822     {
1823       int natval = 0;
1824       /* Find address of general register corresponding to nat bit we're
1825          interested in.  */
1826       CORE_ADDR gr_addr;
1827
1828       gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM + IA64_GR0_REGNUM];
1829
1830       if (gr_addr != 0)
1831         {
1832           /* Compute address of nat collection bits.  */
1833           CORE_ADDR nat_addr = gr_addr | 0x1f8;
1834           CORE_ADDR bsp;
1835           CORE_ADDR nat_collection;
1836           int nat_bit;
1837
1838           /* If our nat collection address is bigger than bsp, we have to get
1839              the nat collection from rnat.  Otherwise, we fetch the nat
1840              collection from the computed address.  */
1841           get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
1842           bsp = extract_unsigned_integer (buf, 8);
1843           if (nat_addr >= bsp)
1844             {
1845               get_frame_register (this_frame, IA64_RNAT_REGNUM, buf);
1846               nat_collection = extract_unsigned_integer (buf, 8);
1847             }
1848           else
1849             nat_collection = read_memory_integer (nat_addr, 8);
1850           nat_bit = (gr_addr >> 3) & 0x3f;
1851           natval = (nat_collection >> nat_bit) & 1;
1852         }
1853
1854       return frame_unwind_got_constant (this_frame, regnum, natval);
1855     }
1856
1857   else if (regnum == IA64_IP_REGNUM)
1858     {
1859       CORE_ADDR pc = 0;
1860       CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1861
1862       if (addr != 0)
1863         {
1864           read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
1865           pc = extract_unsigned_integer (buf, 8);
1866         }
1867       else if (cache->frameless)
1868         {
1869           get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
1870           pc = extract_unsigned_integer (buf, 8);
1871         }
1872       pc &= ~0xf;
1873       return frame_unwind_got_constant (this_frame, regnum, pc);
1874     }
1875
1876   else if (regnum == IA64_PSR_REGNUM)
1877     {
1878       /* We don't know how to get the complete previous PSR, but we need it
1879          for the slot information when we unwind the pc (pc is formed of IP
1880          register plus slot information from PSR).  To get the previous
1881          slot information, we mask it off the return address.  */
1882       ULONGEST slot_num = 0;
1883       CORE_ADDR pc = 0;
1884       CORE_ADDR psr = 0;
1885       CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
1886
1887       get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
1888       psr = extract_unsigned_integer (buf, 8);
1889
1890       if (addr != 0)
1891         {
1892           read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
1893           pc = extract_unsigned_integer (buf, 8);
1894         }
1895       else if (cache->frameless)
1896         {
1897           get_frame_register (this_frame, IA64_BR0_REGNUM, buf);
1898           pc = extract_unsigned_integer (buf, 8);
1899         }
1900       psr &= ~(3LL << 41);
1901       slot_num = pc & 0x3LL;
1902       psr |= (CORE_ADDR)slot_num << 41;
1903       return frame_unwind_got_constant (this_frame, regnum, psr);
1904     }
1905
1906   else if (regnum == IA64_BR0_REGNUM)
1907     {
1908       CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1909
1910       if (addr != 0)
1911         return frame_unwind_got_memory (this_frame, regnum, addr);
1912
1913       return frame_unwind_got_constant (this_frame, regnum, 0);
1914     }
1915
1916   else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
1917            || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1918     {
1919       CORE_ADDR addr = 0;
1920
1921       if (regnum >= V32_REGNUM)
1922         regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1923       addr = cache->saved_regs[regnum];
1924       if (addr != 0)
1925         return frame_unwind_got_memory (this_frame, regnum, addr);
1926
1927       if (cache->frameless)
1928         {
1929           struct value *reg_val;
1930           CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1931
1932           /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
1933              with the same code above?  */
1934           if (regnum >= V32_REGNUM)
1935             regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1936           reg_val = ia64_frame_prev_register (this_frame, this_cache,
1937                                               IA64_CFM_REGNUM);
1938           prev_cfm = extract_unsigned_integer (value_contents_all (reg_val),
1939                                                8);
1940           reg_val = ia64_frame_prev_register (this_frame, this_cache,
1941                                               IA64_BSP_REGNUM);
1942           prev_bsp = extract_unsigned_integer (value_contents_all (reg_val),
1943                                                8);
1944           prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1945
1946           addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1947           return frame_unwind_got_memory (this_frame, regnum, addr);
1948         }
1949
1950       return frame_unwind_got_constant (this_frame, regnum, 0);
1951     }
1952
1953   else /* All other registers.  */
1954     {
1955       CORE_ADDR addr = 0;
1956
1957       if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1958         {
1959           /* Fetch floating point register rename base from current
1960              frame marker for this frame.  */
1961           int rrb_fr = (cache->cfm >> 25) & 0x7f;
1962
1963           /* Adjust the floating point register number to account for
1964              register rotation.  */
1965           regnum = IA64_FR32_REGNUM
1966                  + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1967         }
1968
1969       /* If we have stored a memory address, access the register.  */
1970       addr = cache->saved_regs[regnum];
1971       if (addr != 0)
1972         return frame_unwind_got_memory (this_frame, regnum, addr);
1973       /* Otherwise, punt and get the current value of the register.  */
1974       else
1975         return frame_unwind_got_register (this_frame, regnum, regnum);
1976     }
1977 }
1978
1979 static const struct frame_unwind ia64_frame_unwind =
1980 {
1981   NORMAL_FRAME,
1982   &ia64_frame_this_id,
1983   &ia64_frame_prev_register,
1984   NULL,
1985   default_frame_sniffer
1986 };
1987
1988 /* Signal trampolines.  */
1989
1990 static void
1991 ia64_sigtramp_frame_init_saved_regs (struct frame_info *this_frame,
1992                                      struct ia64_frame_cache *cache)
1993 {
1994   struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
1995
1996   if (tdep->sigcontext_register_address)
1997     {
1998       int regno;
1999
2000       cache->saved_regs[IA64_VRAP_REGNUM] =
2001         tdep->sigcontext_register_address (cache->base, IA64_IP_REGNUM);
2002       cache->saved_regs[IA64_CFM_REGNUM] =
2003         tdep->sigcontext_register_address (cache->base, IA64_CFM_REGNUM);
2004       cache->saved_regs[IA64_PSR_REGNUM] =
2005         tdep->sigcontext_register_address (cache->base, IA64_PSR_REGNUM);
2006       cache->saved_regs[IA64_BSP_REGNUM] =
2007         tdep->sigcontext_register_address (cache->base, IA64_BSP_REGNUM);
2008       cache->saved_regs[IA64_RNAT_REGNUM] =
2009         tdep->sigcontext_register_address (cache->base, IA64_RNAT_REGNUM);
2010       cache->saved_regs[IA64_CCV_REGNUM] =
2011         tdep->sigcontext_register_address (cache->base, IA64_CCV_REGNUM);
2012       cache->saved_regs[IA64_UNAT_REGNUM] =
2013         tdep->sigcontext_register_address (cache->base, IA64_UNAT_REGNUM);
2014       cache->saved_regs[IA64_FPSR_REGNUM] =
2015         tdep->sigcontext_register_address (cache->base, IA64_FPSR_REGNUM);
2016       cache->saved_regs[IA64_PFS_REGNUM] =
2017         tdep->sigcontext_register_address (cache->base, IA64_PFS_REGNUM);
2018       cache->saved_regs[IA64_LC_REGNUM] =
2019         tdep->sigcontext_register_address (cache->base, IA64_LC_REGNUM);
2020       for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
2021         cache->saved_regs[regno] =
2022           tdep->sigcontext_register_address (cache->base, regno);
2023       for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
2024         cache->saved_regs[regno] =
2025           tdep->sigcontext_register_address (cache->base, regno);
2026       for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
2027         cache->saved_regs[regno] =
2028           tdep->sigcontext_register_address (cache->base, regno);
2029     }
2030 }
2031
2032 static struct ia64_frame_cache *
2033 ia64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
2034 {
2035   struct ia64_frame_cache *cache;
2036   CORE_ADDR addr;
2037   char buf[8];
2038   int i;
2039
2040   if (*this_cache)
2041     return *this_cache;
2042
2043   cache = ia64_alloc_frame_cache ();
2044
2045   get_frame_register (this_frame, sp_regnum, buf);
2046   /* Note that frame size is hard-coded below.  We cannot calculate it
2047      via prologue examination.  */
2048   cache->base = extract_unsigned_integer (buf, 8) + 16;
2049
2050   get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2051   cache->bsp = extract_unsigned_integer (buf, 8);
2052
2053   get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2054   cache->cfm = extract_unsigned_integer (buf, 8);
2055   cache->sof = cache->cfm & 0x7f;
2056
2057   ia64_sigtramp_frame_init_saved_regs (this_frame, cache);
2058
2059   *this_cache = cache;
2060   return cache;
2061 }
2062
2063 static void
2064 ia64_sigtramp_frame_this_id (struct frame_info *this_frame,
2065                              void **this_cache, struct frame_id *this_id)
2066 {
2067   struct ia64_frame_cache *cache =
2068     ia64_sigtramp_frame_cache (this_frame, this_cache);
2069
2070   (*this_id) = frame_id_build_special (cache->base,
2071                                        get_frame_pc (this_frame),
2072                                        cache->bsp);
2073   if (gdbarch_debug >= 1)
2074     fprintf_unfiltered (gdb_stdlog,
2075                         "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, this_frame %p\n",
2076                         paddr_nz (this_id->code_addr),
2077                         paddr_nz (this_id->stack_addr),
2078                         paddr_nz (cache->bsp), this_frame);
2079 }
2080
2081 static struct value *
2082 ia64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2083                                    void **this_cache, int regnum)
2084 {
2085   char buf[MAX_REGISTER_SIZE];
2086
2087   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2088   struct ia64_frame_cache *cache =
2089     ia64_sigtramp_frame_cache (this_frame, this_cache);
2090
2091   gdb_assert (regnum >= 0);
2092
2093   if (!target_has_registers)
2094     error (_("No registers."));
2095
2096   if (regnum == IA64_IP_REGNUM)
2097     {
2098       CORE_ADDR pc = 0;
2099       CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2100
2101       if (addr != 0)
2102         {
2103           read_memory (addr, buf, register_size (gdbarch, IA64_IP_REGNUM));
2104           pc = extract_unsigned_integer (buf, 8);
2105         }
2106       pc &= ~0xf;
2107       return frame_unwind_got_constant (this_frame, regnum, pc);
2108     }
2109
2110   else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM)
2111            || (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2112     {
2113       CORE_ADDR addr = 0;
2114
2115       if (regnum >= V32_REGNUM)
2116         regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2117       addr = cache->saved_regs[regnum];
2118       if (addr != 0)
2119         return frame_unwind_got_memory (this_frame, regnum, addr);
2120
2121       return frame_unwind_got_constant (this_frame, regnum, 0);
2122     }
2123
2124   else  /* All other registers not listed above.  */
2125     {
2126       CORE_ADDR addr = cache->saved_regs[regnum];
2127
2128       if (addr != 0)
2129         return frame_unwind_got_memory (this_frame, regnum, addr);
2130
2131       return frame_unwind_got_constant (this_frame, regnum, 0);
2132     }
2133 }
2134
2135 static int
2136 ia64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2137                              struct frame_info *this_frame,
2138                              void **this_cache)
2139 {
2140   struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
2141   if (tdep->pc_in_sigtramp)
2142     {
2143       CORE_ADDR pc = get_frame_pc (this_frame);
2144
2145       if (tdep->pc_in_sigtramp (pc))
2146         return 1;
2147     }
2148
2149   return 0;
2150 }
2151
2152 static const struct frame_unwind ia64_sigtramp_frame_unwind =
2153 {
2154   SIGTRAMP_FRAME,
2155   ia64_sigtramp_frame_this_id,
2156   ia64_sigtramp_frame_prev_register,
2157   NULL,
2158   ia64_sigtramp_frame_sniffer
2159 };
2160
2161 \f
2162
2163 static CORE_ADDR
2164 ia64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2165 {
2166   struct ia64_frame_cache *cache = ia64_frame_cache (this_frame, this_cache);
2167
2168   return cache->base;
2169 }
2170
2171 static const struct frame_base ia64_frame_base =
2172 {
2173   &ia64_frame_unwind,
2174   ia64_frame_base_address,
2175   ia64_frame_base_address,
2176   ia64_frame_base_address
2177 };
2178
2179 #ifdef HAVE_LIBUNWIND_IA64_H
2180
2181 struct ia64_unwind_table_entry
2182   {
2183     unw_word_t start_offset;
2184     unw_word_t end_offset;
2185     unw_word_t info_offset;
2186   };
2187
2188 static __inline__ uint64_t
2189 ia64_rse_slot_num (uint64_t addr)
2190 {
2191   return (addr >> 3) & 0x3f;
2192 }
2193
2194 /* Skip over a designated number of registers in the backing
2195    store, remembering every 64th position is for NAT.  */
2196 static __inline__ uint64_t
2197 ia64_rse_skip_regs (uint64_t addr, long num_regs)
2198 {
2199   long delta = ia64_rse_slot_num(addr) + num_regs;
2200
2201   if (num_regs < 0)
2202     delta -= 0x3e;
2203   return addr + ((num_regs + delta/0x3f) << 3);
2204 }
2205
2206 /* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2207    number to a libunwind register number.  */
2208 static int
2209 ia64_gdb2uw_regnum (int regnum)
2210 {
2211   if (regnum == sp_regnum)
2212     return UNW_IA64_SP;
2213   else if (regnum == IA64_BSP_REGNUM)
2214     return UNW_IA64_BSP;
2215   else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2216     return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2217   else if ((unsigned) (regnum - V32_REGNUM) < 95)
2218     return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2219   else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2220     return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2221   else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2222     return -1;
2223   else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2224     return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2225   else if (regnum == IA64_PR_REGNUM)
2226     return UNW_IA64_PR;
2227   else if (regnum == IA64_IP_REGNUM)
2228     return UNW_REG_IP;
2229   else if (regnum == IA64_CFM_REGNUM)
2230     return UNW_IA64_CFM;
2231   else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2232     return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2233   else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2234     return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2235   else
2236     return -1;
2237 }
2238
2239 /* Gdb libunwind-frame callback function to convert from a libunwind register
2240    number to a ia64 gdb register number.  */
2241 static int
2242 ia64_uw2gdb_regnum (int uw_regnum)
2243 {
2244   if (uw_regnum == UNW_IA64_SP)
2245     return sp_regnum;
2246   else if (uw_regnum == UNW_IA64_BSP)
2247     return IA64_BSP_REGNUM;
2248   else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2249     return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2250   else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2251     return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2252   else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2253     return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2254   else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2255     return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2256   else if (uw_regnum == UNW_IA64_PR)
2257     return IA64_PR_REGNUM;
2258   else if (uw_regnum == UNW_REG_IP)
2259     return IA64_IP_REGNUM;
2260   else if (uw_regnum == UNW_IA64_CFM)
2261     return IA64_CFM_REGNUM;
2262   else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2263     return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2264   else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2265     return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2266   else
2267     return -1;
2268 }
2269
2270 /* Gdb libunwind-frame callback function to reveal if register is a float
2271    register or not.  */
2272 static int
2273 ia64_is_fpreg (int uw_regnum)
2274 {
2275   return unw_is_fpreg (uw_regnum);
2276 }
2277
2278 /* Libunwind callback accessor function for general registers.  */
2279 static int
2280 ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2281                  int write, void *arg)
2282 {
2283   int regnum = ia64_uw2gdb_regnum (uw_regnum);
2284   unw_word_t bsp, sof, sol, cfm, psr, ip;
2285   struct frame_info *this_frame = arg;
2286   long new_sof, old_sof;
2287   char buf[MAX_REGISTER_SIZE];
2288
2289   /* We never call any libunwind routines that need to write registers.  */
2290   gdb_assert (!write);
2291
2292   switch (uw_regnum)
2293     {
2294       case UNW_REG_IP:
2295         /* Libunwind expects to see the pc value which means the slot number
2296            from the psr must be merged with the ip word address.  */
2297         get_frame_register (this_frame, IA64_IP_REGNUM, buf);
2298         ip = extract_unsigned_integer (buf, 8);
2299         get_frame_register (this_frame, IA64_PSR_REGNUM, buf);
2300         psr = extract_unsigned_integer (buf, 8);
2301         *val = ip | ((psr >> 41) & 0x3);
2302         break;
2303
2304       case UNW_IA64_AR_BSP:
2305         /* Libunwind expects to see the beginning of the current register
2306            frame so we must account for the fact that ptrace() will return a value
2307            for bsp that points *after* the current register frame.  */
2308         get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2309         bsp = extract_unsigned_integer (buf, 8);
2310         get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2311         cfm = extract_unsigned_integer (buf, 8);
2312         sof = (cfm & 0x7f);
2313         *val = ia64_rse_skip_regs (bsp, -sof);
2314         break;
2315
2316       case UNW_IA64_AR_BSPSTORE:
2317         /* Libunwind wants bspstore to be after the current register frame.
2318            This is what ptrace() and gdb treats as the regular bsp value.  */
2319         get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2320         *val = extract_unsigned_integer (buf, 8);
2321         break;
2322
2323       default:
2324         /* For all other registers, just unwind the value directly.  */
2325         get_frame_register (this_frame, regnum, buf);
2326         *val = extract_unsigned_integer (buf, 8);
2327         break;
2328     }
2329
2330   if (gdbarch_debug >= 1)
2331     fprintf_unfiltered (gdb_stdlog,
2332                         "  access_reg: from cache: %4s=0x%s\n",
2333                         (((unsigned) regnum <= IA64_NAT127_REGNUM)
2334                         ? ia64_register_names[regnum] : "r??"),
2335                         paddr_nz (*val));
2336   return 0;
2337 }
2338
2339 /* Libunwind callback accessor function for floating-point registers.  */
2340 static int
2341 ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2342                    int write, void *arg)
2343 {
2344   int regnum = ia64_uw2gdb_regnum (uw_regnum);
2345   struct frame_info *this_frame = arg;
2346
2347   /* We never call any libunwind routines that need to write registers.  */
2348   gdb_assert (!write);
2349
2350   get_frame_register (this_frame, regnum, (char *) val);
2351
2352   return 0;
2353 }
2354
2355 /* Libunwind callback accessor function for top-level rse registers.  */
2356 static int
2357 ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2358                      int write, void *arg)
2359 {
2360   int regnum = ia64_uw2gdb_regnum (uw_regnum);
2361   unw_word_t bsp, sof, sol, cfm, psr, ip;
2362   struct regcache *regcache = arg;
2363   long new_sof, old_sof;
2364   char buf[MAX_REGISTER_SIZE];
2365
2366   /* We never call any libunwind routines that need to write registers.  */
2367   gdb_assert (!write);
2368
2369   switch (uw_regnum)
2370     {
2371       case UNW_REG_IP:
2372         /* Libunwind expects to see the pc value which means the slot number
2373            from the psr must be merged with the ip word address.  */
2374         regcache_cooked_read (regcache, IA64_IP_REGNUM, buf);
2375         ip = extract_unsigned_integer (buf, 8);
2376         regcache_cooked_read (regcache, IA64_PSR_REGNUM, buf);
2377         psr = extract_unsigned_integer (buf, 8);
2378         *val = ip | ((psr >> 41) & 0x3);
2379         break;
2380
2381       case UNW_IA64_AR_BSP:
2382         /* Libunwind expects to see the beginning of the current register
2383            frame so we must account for the fact that ptrace() will return a value
2384            for bsp that points *after* the current register frame.  */
2385         regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2386         bsp = extract_unsigned_integer (buf, 8);
2387         regcache_cooked_read (regcache, IA64_CFM_REGNUM, buf);
2388         cfm = extract_unsigned_integer (buf, 8);
2389         sof = (cfm & 0x7f);
2390         *val = ia64_rse_skip_regs (bsp, -sof);
2391         break;
2392
2393       case UNW_IA64_AR_BSPSTORE:
2394         /* Libunwind wants bspstore to be after the current register frame.
2395            This is what ptrace() and gdb treats as the regular bsp value.  */
2396         regcache_cooked_read (regcache, IA64_BSP_REGNUM, buf);
2397         *val = extract_unsigned_integer (buf, 8);
2398         break;
2399
2400       default:
2401         /* For all other registers, just unwind the value directly.  */
2402         regcache_cooked_read (regcache, regnum, buf);
2403         *val = extract_unsigned_integer (buf, 8);
2404         break;
2405     }
2406
2407   if (gdbarch_debug >= 1)
2408     fprintf_unfiltered (gdb_stdlog,
2409                         "  access_rse_reg: from cache: %4s=0x%s\n",
2410                         (((unsigned) regnum <= IA64_NAT127_REGNUM)
2411                          ? ia64_register_names[regnum] : "r??"),
2412                         paddr_nz (*val));
2413
2414   return 0;
2415 }
2416
2417 /* Libunwind callback accessor function for top-level fp registers.  */
2418 static int
2419 ia64_access_rse_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum,
2420                        unw_fpreg_t *val, int write, void *arg)
2421 {
2422   int regnum = ia64_uw2gdb_regnum (uw_regnum);
2423   struct regcache *regcache = arg;
2424
2425   /* We never call any libunwind routines that need to write registers.  */
2426   gdb_assert (!write);
2427
2428   regcache_cooked_read (regcache, regnum, (char *) val);
2429
2430   return 0;
2431 }
2432
2433 /* Libunwind callback accessor function for accessing memory.  */
2434 static int
2435 ia64_access_mem (unw_addr_space_t as,
2436                  unw_word_t addr, unw_word_t *val,
2437                  int write, void *arg)
2438 {
2439   if (addr - KERNEL_START < ktab_size)
2440     {
2441       unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2442                           + (addr - KERNEL_START));
2443
2444       if (write)
2445         *laddr = *val;
2446       else
2447         *val = *laddr;
2448       return 0;
2449     }
2450
2451   /* XXX do we need to normalize byte-order here?  */
2452   if (write)
2453     return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2454   else
2455     return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2456 }
2457
2458 /* Call low-level function to access the kernel unwind table.  */
2459 static LONGEST
2460 getunwind_table (gdb_byte **buf_p)
2461 {
2462   LONGEST x;
2463
2464   /* FIXME drow/2005-09-10: This code used to call
2465      ia64_linux_xfer_unwind_table directly to fetch the unwind table
2466      for the currently running ia64-linux kernel.  That data should
2467      come from the core file and be accessed via the auxv vector; if
2468      we want to preserve fall back to the running kernel's table, then
2469      we should find a way to override the corefile layer's
2470      xfer_partial method.  */
2471
2472   x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2473                          NULL, buf_p);
2474
2475   return x;
2476 }
2477
2478 /* Get the kernel unwind table.  */
2479 static int
2480 get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2481 {
2482   static struct ia64_table_entry *etab;
2483
2484   if (!ktab)
2485     {
2486       gdb_byte *ktab_buf;
2487       LONGEST size;
2488
2489       size = getunwind_table (&ktab_buf);
2490       if (size <= 0)
2491         return -UNW_ENOINFO;
2492
2493       ktab = (struct ia64_table_entry *) ktab_buf;
2494       ktab_size = size;
2495
2496       for (etab = ktab; etab->start_offset; ++etab)
2497         etab->info_offset += KERNEL_START;
2498     }
2499
2500   if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2501     return -UNW_ENOINFO;
2502
2503   di->format = UNW_INFO_FORMAT_TABLE;
2504   di->gp = 0;
2505   di->start_ip = ktab[0].start_offset;
2506   di->end_ip = etab[-1].end_offset;
2507   di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2508   di->u.ti.segbase = 0;
2509   di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2510   di->u.ti.table_data = (unw_word_t *) ktab;
2511
2512   if (gdbarch_debug >= 1)
2513     fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
2514                         "segbase=0x%s, length=%s, gp=0x%s\n",
2515                         (char *) di->u.ti.name_ptr,
2516                         paddr_nz (di->u.ti.segbase),
2517                         pulongest (di->u.ti.table_len),
2518                         paddr_nz (di->gp));
2519   return 0;
2520 }
2521
2522 /* Find the unwind table entry for a specified address.  */
2523 static int
2524 ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2525                         unw_dyn_info_t *dip, void **buf)
2526 {
2527   Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2528   Elf_Internal_Ehdr *ehdr;
2529   unw_word_t segbase = 0;
2530   CORE_ADDR load_base;
2531   bfd *bfd;
2532   int i;
2533
2534   bfd = objfile->obfd;
2535
2536   ehdr = elf_tdata (bfd)->elf_header;
2537   phdr = elf_tdata (bfd)->phdr;
2538
2539   load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2540
2541   for (i = 0; i < ehdr->e_phnum; ++i)
2542     {
2543       switch (phdr[i].p_type)
2544         {
2545         case PT_LOAD:
2546           if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2547               < phdr[i].p_memsz)
2548             p_text = phdr + i;
2549           break;
2550
2551         case PT_IA_64_UNWIND:
2552           p_unwind = phdr + i;
2553           break;
2554
2555         default:
2556           break;
2557         }
2558     }
2559
2560   if (!p_text || !p_unwind)
2561     return -UNW_ENOINFO;
2562
2563   /* Verify that the segment that contains the IP also contains
2564      the static unwind table.  If not, we may be in the Linux kernel's
2565      DSO gate page in which case the unwind table is another segment.
2566      Otherwise, we are dealing with runtime-generated code, for which we
2567      have no info here.  */
2568   segbase = p_text->p_vaddr + load_base;
2569
2570   if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2571     {
2572       int ok = 0;
2573       for (i = 0; i < ehdr->e_phnum; ++i)
2574         {
2575           if (phdr[i].p_type == PT_LOAD
2576               && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2577             {
2578               ok = 1;
2579               /* Get the segbase from the section containing the
2580                  libunwind table.  */
2581               segbase = phdr[i].p_vaddr + load_base;
2582             }
2583         }
2584       if (!ok)
2585         return -UNW_ENOINFO;
2586     }
2587
2588   dip->start_ip = p_text->p_vaddr + load_base;
2589   dip->end_ip = dip->start_ip + p_text->p_memsz;
2590   dip->gp = ia64_find_global_pointer (ip);
2591   dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2592   dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2593   dip->u.rti.segbase = segbase;
2594   dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2595   dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
2596
2597   return 0;
2598 }
2599
2600 /* Libunwind callback accessor function to acquire procedure unwind-info.  */
2601 static int
2602 ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2603                        int need_unwind_info, void *arg)
2604 {
2605   struct obj_section *sec = find_pc_section (ip);
2606   unw_dyn_info_t di;
2607   int ret;
2608   void *buf = NULL;
2609
2610   if (!sec)
2611     {
2612       /* XXX This only works if the host and the target architecture are
2613          both ia64 and if the have (more or less) the same kernel
2614          version.  */
2615       if (get_kernel_table (ip, &di) < 0)
2616         return -UNW_ENOINFO;
2617
2618       if (gdbarch_debug >= 1)
2619         fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2620                             "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2621                             "length=%s,data=0x%s)\n",
2622                             paddr_nz (ip), (char *)di.u.ti.name_ptr,
2623                             paddr_nz (di.u.ti.segbase),
2624                             paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2625                             paddr_nz (di.gp),
2626                             pulongest (di.u.ti.table_len),
2627                             paddr_nz ((CORE_ADDR)di.u.ti.table_data));
2628     }
2629   else
2630     {
2631       ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2632       if (ret < 0)
2633         return ret;
2634
2635       if (gdbarch_debug >= 1)
2636         fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2637                             "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2638                             "length=%s,data=0x%s)\n",
2639                             paddr_nz (ip), (char *)di.u.rti.name_ptr,
2640                             paddr_nz (di.u.rti.segbase),
2641                             paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2642                             paddr_nz (di.gp),
2643                             pulongest (di.u.rti.table_len),
2644                             paddr_nz (di.u.rti.table_data));
2645     }
2646
2647   ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2648                                        arg);
2649
2650   /* We no longer need the dyn info storage so free it.  */
2651   xfree (buf);
2652
2653   return ret;
2654 }
2655
2656 /* Libunwind callback accessor function for cleanup.  */
2657 static void
2658 ia64_put_unwind_info (unw_addr_space_t as,
2659                       unw_proc_info_t *pip, void *arg)
2660 {
2661   /* Nothing required for now.  */
2662 }
2663
2664 /* Libunwind callback accessor function to get head of the dynamic
2665    unwind-info registration list.  */
2666 static int
2667 ia64_get_dyn_info_list (unw_addr_space_t as,
2668                         unw_word_t *dilap, void *arg)
2669 {
2670   struct obj_section *text_sec;
2671   struct objfile *objfile;
2672   unw_word_t ip, addr;
2673   unw_dyn_info_t di;
2674   int ret;
2675
2676   if (!libunwind_is_initialized ())
2677     return -UNW_ENOINFO;
2678
2679   for (objfile = object_files; objfile; objfile = objfile->next)
2680     {
2681       void *buf = NULL;
2682
2683       text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2684       ip = obj_section_addr (text_sec);
2685       ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2686       if (ret >= 0)
2687         {
2688           addr = libunwind_find_dyn_list (as, &di, arg);
2689           /* We no longer need the dyn info storage so free it.  */
2690           xfree (buf);
2691
2692           if (addr)
2693             {
2694               if (gdbarch_debug >= 1)
2695                 fprintf_unfiltered (gdb_stdlog,
2696                                     "dynamic unwind table in objfile %s "
2697                                     "at 0x%s (gp=0x%s)\n",
2698                                     bfd_get_filename (objfile->obfd),
2699                                     paddr_nz (addr), paddr_nz (di.gp));
2700               *dilap = addr;
2701               return 0;
2702             }
2703         }
2704     }
2705   return -UNW_ENOINFO;
2706 }
2707
2708
2709 /* Frame interface functions for libunwind.  */
2710
2711 static void
2712 ia64_libunwind_frame_this_id (struct frame_info *this_frame, void **this_cache,
2713                               struct frame_id *this_id)
2714 {
2715   struct frame_id id;
2716   char buf[8];
2717   CORE_ADDR bsp;
2718
2719
2720   libunwind_frame_this_id (this_frame, this_cache, &id);
2721   if (frame_id_eq (id, null_frame_id))
2722     {
2723       (*this_id) = null_frame_id;
2724       return;
2725     }
2726
2727   /* We must add the bsp as the special address for frame comparison
2728      purposes.  */
2729   get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2730   bsp = extract_unsigned_integer (buf, 8);
2731
2732   (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2733
2734   if (gdbarch_debug >= 1)
2735     fprintf_unfiltered (gdb_stdlog,
2736                         "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, this_frame %p\n",
2737                         paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2738                         paddr_nz (bsp), this_frame);
2739 }
2740
2741 static struct value *
2742 ia64_libunwind_frame_prev_register (struct frame_info *this_frame,
2743                                     void **this_cache, int regnum)
2744 {
2745   int reg = regnum;
2746   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2747   struct value *val;
2748
2749   if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2750     reg = IA64_PR_REGNUM;
2751   else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2752     reg = IA64_UNAT_REGNUM;
2753
2754   /* Let libunwind do most of the work.  */
2755   val = libunwind_frame_prev_register (this_frame, this_cache, reg);
2756
2757   if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2758     {
2759       ULONGEST prN_val;
2760
2761       if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2762         {
2763           int rrb_pr = 0;
2764           ULONGEST cfm;
2765           unsigned char buf[MAX_REGISTER_SIZE];
2766
2767           /* Fetch predicate register rename base from current frame
2768              marker for this frame.  */
2769           get_frame_register (this_frame, IA64_CFM_REGNUM, buf);
2770           cfm = extract_unsigned_integer (buf, 8);
2771           rrb_pr = (cfm >> 32) & 0x3f;
2772
2773           /* Adjust the register number to account for register rotation.  */
2774           regnum = VP16_REGNUM + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2775         }
2776       prN_val = extract_bit_field (value_contents_all (val),
2777                                    regnum - VP0_REGNUM, 1);
2778       return frame_unwind_got_constant (this_frame, regnum, prN_val);
2779     }
2780
2781   else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2782     {
2783       ULONGEST unatN_val;
2784
2785       unatN_val = extract_bit_field (value_contents_all (val),
2786                                      regnum - IA64_NAT0_REGNUM, 1);
2787       return frame_unwind_got_constant (this_frame, regnum, unatN_val);
2788     }
2789
2790   else if (regnum == IA64_BSP_REGNUM)
2791     {
2792       struct value *cfm_val;
2793       CORE_ADDR prev_bsp, prev_cfm;
2794
2795       /* We want to calculate the previous bsp as the end of the previous
2796          register stack frame.  This corresponds to what the hardware bsp
2797          register will be if we pop the frame back which is why we might
2798          have been called.  We know that libunwind will pass us back the
2799          beginning of the current frame so we should just add sof to it. */
2800       prev_bsp = extract_unsigned_integer (value_contents_all (val), 8);
2801       cfm_val = libunwind_frame_prev_register (this_frame, this_cache,
2802                                                IA64_CFM_REGNUM);
2803       prev_cfm = extract_unsigned_integer (value_contents_all (cfm_val), 8);
2804       prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2805
2806       return frame_unwind_got_constant (this_frame, regnum, prev_bsp);
2807     }
2808   else
2809     return val;
2810 }
2811
2812 static int
2813 ia64_libunwind_frame_sniffer (const struct frame_unwind *self,
2814                               struct frame_info *this_frame,
2815                               void **this_cache)
2816 {
2817   if (libunwind_is_initialized ()
2818       && libunwind_frame_sniffer (self, this_frame, this_cache))
2819     return 1;
2820
2821   return 0;
2822 }
2823
2824 static const struct frame_unwind ia64_libunwind_frame_unwind =
2825 {
2826   NORMAL_FRAME,
2827   ia64_libunwind_frame_this_id,
2828   ia64_libunwind_frame_prev_register,
2829   NULL,
2830   ia64_libunwind_frame_sniffer,
2831   libunwind_frame_dealloc_cache
2832 };
2833
2834 static void
2835 ia64_libunwind_sigtramp_frame_this_id (struct frame_info *this_frame,
2836                                        void **this_cache,
2837                                        struct frame_id *this_id)
2838 {
2839   char buf[8];
2840   CORE_ADDR bsp;
2841   struct frame_id id;
2842   CORE_ADDR prev_ip;
2843
2844   libunwind_frame_this_id (this_frame, this_cache, &id);
2845   if (frame_id_eq (id, null_frame_id))
2846     {
2847       (*this_id) = null_frame_id;
2848       return;
2849     }
2850
2851   /* We must add the bsp as the special address for frame comparison
2852      purposes.  */
2853   get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
2854   bsp = extract_unsigned_integer (buf, 8);
2855
2856   /* For a sigtramp frame, we don't make the check for previous ip being 0.  */
2857   (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2858
2859   if (gdbarch_debug >= 1)
2860     fprintf_unfiltered (gdb_stdlog,
2861                         "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, this_frame %p\n",
2862                         paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2863                         paddr_nz (bsp), this_frame);
2864 }
2865
2866 static struct value *
2867 ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *this_frame,
2868                                              void **this_cache, int regnum)
2869 {
2870   struct value *prev_ip_val;
2871   CORE_ADDR prev_ip;
2872
2873   /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2874      method of getting previous registers.  */
2875   prev_ip_val = libunwind_frame_prev_register (this_frame, this_cache,
2876                                                IA64_IP_REGNUM);
2877   prev_ip = extract_unsigned_integer (value_contents_all (prev_ip_val), 8);
2878
2879   if (prev_ip == 0)
2880     {
2881       void *tmp_cache = NULL;
2882       return ia64_sigtramp_frame_prev_register (this_frame, &tmp_cache,
2883                                                 regnum);
2884     }
2885   else
2886     return ia64_libunwind_frame_prev_register (this_frame, this_cache, regnum);
2887 }
2888
2889 static int
2890 ia64_libunwind_sigtramp_frame_sniffer (const struct frame_unwind *self,
2891                                        struct frame_info *this_frame,
2892                                        void **this_cache)
2893 {
2894   if (libunwind_is_initialized ())
2895     {
2896       if (libunwind_sigtramp_frame_sniffer (self, this_frame, this_cache))
2897         return 1;
2898       return 0;
2899     }
2900   else
2901     return ia64_sigtramp_frame_sniffer (self, this_frame, this_cache);
2902 }
2903
2904 static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2905 {
2906   SIGTRAMP_FRAME,
2907   ia64_libunwind_sigtramp_frame_this_id,
2908   ia64_libunwind_sigtramp_frame_prev_register,
2909   NULL,
2910   ia64_libunwind_sigtramp_frame_sniffer
2911 };
2912
2913 /* Set of libunwind callback acccessor functions.  */
2914 static unw_accessors_t ia64_unw_accessors =
2915 {
2916   ia64_find_proc_info_x,
2917   ia64_put_unwind_info,
2918   ia64_get_dyn_info_list,
2919   ia64_access_mem,
2920   ia64_access_reg,
2921   ia64_access_fpreg,
2922   /* resume */
2923   /* get_proc_name */
2924 };
2925
2926 /* Set of special libunwind callback acccessor functions specific for accessing
2927    the rse registers.  At the top of the stack, we want libunwind to figure out
2928    how to read r32 - r127.  Though usually they are found sequentially in memory
2929    starting from $bof, this is not always true.  */
2930 static unw_accessors_t ia64_unw_rse_accessors =
2931 {
2932   ia64_find_proc_info_x,
2933   ia64_put_unwind_info,
2934   ia64_get_dyn_info_list,
2935   ia64_access_mem,
2936   ia64_access_rse_reg,
2937   ia64_access_rse_fpreg,
2938   /* resume */
2939   /* get_proc_name */
2940 };
2941
2942 /* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use.  */
2943 static struct libunwind_descr ia64_libunwind_descr =
2944 {
2945   ia64_gdb2uw_regnum,
2946   ia64_uw2gdb_regnum,
2947   ia64_is_fpreg,
2948   &ia64_unw_accessors,
2949   &ia64_unw_rse_accessors,
2950 };
2951
2952 #endif /* HAVE_LIBUNWIND_IA64_H  */
2953
2954 static int
2955 ia64_use_struct_convention (struct type *type)
2956 {
2957   struct type *float_elt_type;
2958
2959   /* Don't use the struct convention for anything but structure,
2960      union, or array types.  */
2961   if (!(TYPE_CODE (type) == TYPE_CODE_STRUCT
2962         || TYPE_CODE (type) == TYPE_CODE_UNION
2963         || TYPE_CODE (type) == TYPE_CODE_ARRAY))
2964     return 0;
2965
2966   /* HFAs are structures (or arrays) consisting entirely of floating
2967      point values of the same length.  Up to 8 of these are returned
2968      in registers.  Don't use the struct convention when this is the
2969      case.  */
2970   float_elt_type = is_float_or_hfa_type (type);
2971   if (float_elt_type != NULL
2972       && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
2973     return 0;
2974
2975   /* Other structs of length 32 or less are returned in r8-r11.
2976      Don't use the struct convention for those either.  */
2977   return TYPE_LENGTH (type) > 32;
2978 }
2979
2980 static void
2981 ia64_extract_return_value (struct type *type, struct regcache *regcache,
2982                            gdb_byte *valbuf)
2983 {
2984   struct type *float_elt_type;
2985
2986   float_elt_type = is_float_or_hfa_type (type);
2987   if (float_elt_type != NULL)
2988     {
2989       char from[MAX_REGISTER_SIZE];
2990       int offset = 0;
2991       int regnum = IA64_FR8_REGNUM;
2992       int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
2993
2994       while (n-- > 0)
2995         {
2996           regcache_cooked_read (regcache, regnum, from);
2997           convert_typed_floating (from, builtin_type_ia64_ext,
2998                                   (char *)valbuf + offset, float_elt_type);
2999           offset += TYPE_LENGTH (float_elt_type);
3000           regnum++;
3001         }
3002     }
3003   else
3004     {
3005       ULONGEST val;
3006       int offset = 0;
3007       int regnum = IA64_GR8_REGNUM;
3008       int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
3009                                                IA64_GR8_REGNUM));
3010       int n = TYPE_LENGTH (type) / reglen;
3011       int m = TYPE_LENGTH (type) % reglen;
3012
3013       while (n-- > 0)
3014         {
3015           ULONGEST val;
3016           regcache_cooked_read_unsigned (regcache, regnum, &val);
3017           memcpy ((char *)valbuf + offset, &val, reglen);
3018           offset += reglen;
3019           regnum++;
3020         }
3021
3022       if (m)
3023         {
3024           regcache_cooked_read_unsigned (regcache, regnum, &val);
3025           memcpy ((char *)valbuf + offset, &val, m);
3026         }
3027     }
3028 }
3029
3030 static void
3031 ia64_store_return_value (struct type *type, struct regcache *regcache,
3032                          const gdb_byte *valbuf)
3033 {
3034   struct type *float_elt_type;
3035
3036   float_elt_type = is_float_or_hfa_type (type);
3037   if (float_elt_type != NULL)
3038     {
3039       char to[MAX_REGISTER_SIZE];
3040       int offset = 0;
3041       int regnum = IA64_FR8_REGNUM;
3042       int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3043
3044       while (n-- > 0)
3045         {
3046           convert_typed_floating ((char *)valbuf + offset, float_elt_type,
3047                                   to, builtin_type_ia64_ext);
3048           regcache_cooked_write (regcache, regnum, to);
3049           offset += TYPE_LENGTH (float_elt_type);
3050           regnum++;
3051         }
3052     }
3053   else
3054     {
3055       ULONGEST val;
3056       int offset = 0;
3057       int regnum = IA64_GR8_REGNUM;
3058       int reglen = TYPE_LENGTH (register_type (get_regcache_arch (regcache),
3059                                                IA64_GR8_REGNUM));
3060       int n = TYPE_LENGTH (type) / reglen;
3061       int m = TYPE_LENGTH (type) % reglen;
3062
3063       while (n-- > 0)
3064         {
3065           ULONGEST val;
3066           memcpy (&val, (char *)valbuf + offset, reglen);
3067           regcache_cooked_write_unsigned (regcache, regnum, val);
3068           offset += reglen;
3069           regnum++;
3070         }
3071
3072       if (m)
3073         {
3074           memcpy (&val, (char *)valbuf + offset, m);
3075           regcache_cooked_write_unsigned (regcache, regnum, val);
3076         }
3077     }
3078 }
3079
3080 static enum return_value_convention
3081 ia64_return_value (struct gdbarch *gdbarch, struct type *func_type,
3082                    struct type *valtype, struct regcache *regcache,
3083                    gdb_byte *readbuf, const gdb_byte *writebuf)
3084 {
3085   int struct_return = ia64_use_struct_convention (valtype);
3086
3087   if (writebuf != NULL)
3088     {
3089       gdb_assert (!struct_return);
3090       ia64_store_return_value (valtype, regcache, writebuf);
3091     }
3092
3093   if (readbuf != NULL)
3094     {
3095       gdb_assert (!struct_return);
3096       ia64_extract_return_value (valtype, regcache, readbuf);
3097     }
3098
3099   if (struct_return)
3100     return RETURN_VALUE_STRUCT_CONVENTION;
3101   else
3102     return RETURN_VALUE_REGISTER_CONVENTION;
3103 }
3104
3105 static int
3106 is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3107 {
3108   switch (TYPE_CODE (t))
3109     {
3110     case TYPE_CODE_FLT:
3111       if (*etp)
3112         return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3113       else
3114         {
3115           *etp = t;
3116           return 1;
3117         }
3118       break;
3119     case TYPE_CODE_ARRAY:
3120       return
3121         is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3122                                       etp);
3123       break;
3124     case TYPE_CODE_STRUCT:
3125       {
3126         int i;
3127
3128         for (i = 0; i < TYPE_NFIELDS (t); i++)
3129           if (!is_float_or_hfa_type_recurse
3130               (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
3131             return 0;
3132         return 1;
3133       }
3134       break;
3135     default:
3136       return 0;
3137       break;
3138     }
3139 }
3140
3141 /* Determine if the given type is one of the floating point types or
3142    and HFA (which is a struct, array, or combination thereof whose
3143    bottom-most elements are all of the same floating point type).  */
3144
3145 static struct type *
3146 is_float_or_hfa_type (struct type *t)
3147 {
3148   struct type *et = 0;
3149
3150   return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3151 }
3152
3153
3154 /* Return 1 if the alignment of T is such that the next even slot
3155    should be used.  Return 0, if the next available slot should
3156    be used.  (See section 8.5.1 of the IA-64 Software Conventions
3157    and Runtime manual).  */
3158
3159 static int
3160 slot_alignment_is_next_even (struct type *t)
3161 {
3162   switch (TYPE_CODE (t))
3163     {
3164     case TYPE_CODE_INT:
3165     case TYPE_CODE_FLT:
3166       if (TYPE_LENGTH (t) > 8)
3167         return 1;
3168       else
3169         return 0;
3170     case TYPE_CODE_ARRAY:
3171       return
3172         slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3173     case TYPE_CODE_STRUCT:
3174       {
3175         int i;
3176
3177         for (i = 0; i < TYPE_NFIELDS (t); i++)
3178           if (slot_alignment_is_next_even
3179               (check_typedef (TYPE_FIELD_TYPE (t, i))))
3180             return 1;
3181         return 0;
3182       }
3183     default:
3184       return 0;
3185     }
3186 }
3187
3188 /* Attempt to find (and return) the global pointer for the given
3189    function.
3190
3191    This is a rather nasty bit of code searchs for the .dynamic section
3192    in the objfile corresponding to the pc of the function we're trying
3193    to call.  Once it finds the addresses at which the .dynamic section
3194    lives in the child process, it scans the Elf64_Dyn entries for a
3195    DT_PLTGOT tag.  If it finds one of these, the corresponding
3196    d_un.d_ptr value is the global pointer.  */
3197
3198 static CORE_ADDR
3199 ia64_find_global_pointer (CORE_ADDR faddr)
3200 {
3201   struct obj_section *faddr_sect;
3202
3203   faddr_sect = find_pc_section (faddr);
3204   if (faddr_sect != NULL)
3205     {
3206       struct obj_section *osect;
3207
3208       ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3209         {
3210           if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3211             break;
3212         }
3213
3214       if (osect < faddr_sect->objfile->sections_end)
3215         {
3216           CORE_ADDR addr, endaddr;
3217
3218           addr = obj_section_addr (osect);
3219           endaddr = obj_section_endaddr (osect);
3220
3221           while (addr < endaddr)
3222             {
3223               int status;
3224               LONGEST tag;
3225               char buf[8];
3226
3227               status = target_read_memory (addr, buf, sizeof (buf));
3228               if (status != 0)
3229                 break;
3230               tag = extract_signed_integer (buf, sizeof (buf));
3231
3232               if (tag == DT_PLTGOT)
3233                 {
3234                   CORE_ADDR global_pointer;
3235
3236                   status = target_read_memory (addr + 8, buf, sizeof (buf));
3237                   if (status != 0)
3238                     break;
3239                   global_pointer = extract_unsigned_integer (buf, sizeof (buf));
3240
3241                   /* The payoff... */
3242                   return global_pointer;
3243                 }
3244
3245               if (tag == DT_NULL)
3246                 break;
3247
3248               addr += 16;
3249             }
3250         }
3251     }
3252   return 0;
3253 }
3254
3255 /* Given a function's address, attempt to find (and return) the
3256    corresponding (canonical) function descriptor.  Return 0 if
3257    not found.  */
3258 static CORE_ADDR
3259 find_extant_func_descr (CORE_ADDR faddr)
3260 {
3261   struct obj_section *faddr_sect;
3262
3263   /* Return early if faddr is already a function descriptor.  */
3264   faddr_sect = find_pc_section (faddr);
3265   if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
3266     return faddr;
3267
3268   if (faddr_sect != NULL)
3269     {
3270       struct obj_section *osect;
3271       ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
3272         {
3273           if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3274             break;
3275         }
3276
3277       if (osect < faddr_sect->objfile->sections_end)
3278         {
3279           CORE_ADDR addr, endaddr;
3280
3281           addr = obj_section_addr (osect);
3282           endaddr = obj_section_endaddr (osect);
3283
3284           while (addr < endaddr)
3285             {
3286               int status;
3287               LONGEST faddr2;
3288               char buf[8];
3289
3290               status = target_read_memory (addr, buf, sizeof (buf));
3291               if (status != 0)
3292                 break;
3293               faddr2 = extract_signed_integer (buf, sizeof (buf));
3294
3295               if (faddr == faddr2)
3296                 return addr;
3297
3298               addr += 16;
3299             }
3300         }
3301     }
3302   return 0;
3303 }
3304
3305 /* Attempt to find a function descriptor corresponding to the
3306    given address.  If none is found, construct one on the
3307    stack using the address at fdaptr.  */
3308
3309 static CORE_ADDR
3310 find_func_descr (struct regcache *regcache, CORE_ADDR faddr, CORE_ADDR *fdaptr)
3311 {
3312   CORE_ADDR fdesc;
3313
3314   fdesc = find_extant_func_descr (faddr);
3315
3316   if (fdesc == 0)
3317     {
3318       ULONGEST global_pointer;
3319       char buf[16];
3320
3321       fdesc = *fdaptr;
3322       *fdaptr += 16;
3323
3324       global_pointer = ia64_find_global_pointer (faddr);
3325
3326       if (global_pointer == 0)
3327         regcache_cooked_read_unsigned (regcache,
3328                                        IA64_GR1_REGNUM, &global_pointer);
3329
3330       store_unsigned_integer (buf, 8, faddr);
3331       store_unsigned_integer (buf + 8, 8, global_pointer);
3332
3333       write_memory (fdesc, buf, 16);
3334     }
3335
3336   return fdesc;
3337 }
3338
3339 /* Use the following routine when printing out function pointers
3340    so the user can see the function address rather than just the
3341    function descriptor.  */
3342 static CORE_ADDR
3343 ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3344                                  struct target_ops *targ)
3345 {
3346   struct obj_section *s;
3347
3348   s = find_pc_section (addr);
3349
3350   /* check if ADDR points to a function descriptor.  */
3351   if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3352     return read_memory_unsigned_integer (addr, 8);
3353
3354   /* Normally, functions live inside a section that is executable.
3355      So, if ADDR points to a non-executable section, then treat it
3356      as a function descriptor and return the target address iff
3357      the target address itself points to a section that is executable.  */
3358   if (s && (s->the_bfd_section->flags & SEC_CODE) == 0)
3359     {
3360       CORE_ADDR pc = read_memory_unsigned_integer (addr, 8);
3361       struct obj_section *pc_section = find_pc_section (pc);
3362
3363       if (pc_section && (pc_section->the_bfd_section->flags & SEC_CODE))
3364         return pc;
3365     }
3366
3367   /* There are also descriptors embedded in vtables.  */
3368   if (s)
3369     {
3370       struct minimal_symbol *minsym;
3371
3372       minsym = lookup_minimal_symbol_by_pc (addr);
3373
3374       if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3375         return read_memory_unsigned_integer (addr, 8);
3376     }
3377
3378   return addr;
3379 }
3380
3381 static CORE_ADDR
3382 ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3383 {
3384   return sp & ~0xfLL;
3385 }
3386
3387 static CORE_ADDR
3388 ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
3389                       struct regcache *regcache, CORE_ADDR bp_addr,
3390                       int nargs, struct value **args, CORE_ADDR sp,
3391                       int struct_return, CORE_ADDR struct_addr)
3392 {
3393   int argno;
3394   struct value *arg;
3395   struct type *type;
3396   int len, argoffset;
3397   int nslots, rseslots, memslots, slotnum, nfuncargs;
3398   int floatreg;
3399   ULONGEST bsp, cfm, pfs, new_bsp;
3400   CORE_ADDR funcdescaddr, pc, global_pointer;
3401   CORE_ADDR func_addr = find_function_addr (function, NULL);
3402
3403   nslots = 0;
3404   nfuncargs = 0;
3405   /* Count the number of slots needed for the arguments.  */
3406   for (argno = 0; argno < nargs; argno++)
3407     {
3408       arg = args[argno];
3409       type = check_typedef (value_type (arg));
3410       len = TYPE_LENGTH (type);
3411
3412       if ((nslots & 1) && slot_alignment_is_next_even (type))
3413         nslots++;
3414
3415       if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3416         nfuncargs++;
3417
3418       nslots += (len + 7) / 8;
3419     }
3420
3421   /* Divvy up the slots between the RSE and the memory stack.  */
3422   rseslots = (nslots > 8) ? 8 : nslots;
3423   memslots = nslots - rseslots;
3424
3425   /* Allocate a new RSE frame.  */
3426   regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
3427
3428   regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
3429   new_bsp = rse_address_add (bsp, rseslots);
3430   regcache_cooked_write_unsigned (regcache, IA64_BSP_REGNUM, new_bsp);
3431
3432   regcache_cooked_read_unsigned (regcache, IA64_PFS_REGNUM, &pfs);
3433   pfs &= 0xc000000000000000LL;
3434   pfs |= (cfm & 0xffffffffffffLL);
3435   regcache_cooked_write_unsigned (regcache, IA64_PFS_REGNUM, pfs);
3436
3437   cfm &= 0xc000000000000000LL;
3438   cfm |= rseslots;
3439   regcache_cooked_write_unsigned (regcache, IA64_CFM_REGNUM, cfm);
3440
3441   /* We will attempt to find function descriptors in the .opd segment,
3442      but if we can't we'll construct them ourselves.  That being the
3443      case, we'll need to reserve space on the stack for them.  */
3444   funcdescaddr = sp - nfuncargs * 16;
3445   funcdescaddr &= ~0xfLL;
3446
3447   /* Adjust the stack pointer to it's new value.  The calling conventions
3448      require us to have 16 bytes of scratch, plus whatever space is
3449      necessary for the memory slots and our function descriptors.  */
3450   sp = sp - 16 - (memslots + nfuncargs) * 8;
3451   sp &= ~0xfLL;                         /* Maintain 16 byte alignment.  */
3452
3453   /* Place the arguments where they belong.  The arguments will be
3454      either placed in the RSE backing store or on the memory stack.
3455      In addition, floating point arguments or HFAs are placed in
3456      floating point registers.  */
3457   slotnum = 0;
3458   floatreg = IA64_FR8_REGNUM;
3459   for (argno = 0; argno < nargs; argno++)
3460     {
3461       struct type *float_elt_type;
3462
3463       arg = args[argno];
3464       type = check_typedef (value_type (arg));
3465       len = TYPE_LENGTH (type);
3466
3467       /* Special handling for function parameters.  */
3468       if (len == 8
3469           && TYPE_CODE (type) == TYPE_CODE_PTR
3470           && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3471         {
3472           char val_buf[8];
3473           ULONGEST faddr = extract_unsigned_integer (value_contents (arg), 8);
3474           store_unsigned_integer (val_buf, 8,
3475                                   find_func_descr (regcache, faddr,
3476                                                    &funcdescaddr));
3477           if (slotnum < rseslots)
3478             write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3479           else
3480             write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3481           slotnum++;
3482           continue;
3483         }
3484
3485       /* Normal slots.  */
3486
3487       /* Skip odd slot if necessary...  */
3488       if ((slotnum & 1) && slot_alignment_is_next_even (type))
3489         slotnum++;
3490
3491       argoffset = 0;
3492       while (len > 0)
3493         {
3494           char val_buf[8];
3495
3496           memset (val_buf, 0, 8);
3497           memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
3498
3499           if (slotnum < rseslots)
3500             write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3501           else
3502             write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3503
3504           argoffset += 8;
3505           len -= 8;
3506           slotnum++;
3507         }
3508
3509       /* Handle floating point types (including HFAs).  */
3510       float_elt_type = is_float_or_hfa_type (type);
3511       if (float_elt_type != NULL)
3512         {
3513           argoffset = 0;
3514           len = TYPE_LENGTH (type);
3515           while (len > 0 && floatreg < IA64_FR16_REGNUM)
3516             {
3517               char to[MAX_REGISTER_SIZE];
3518               convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
3519                                       to, builtin_type_ia64_ext);
3520               regcache_cooked_write (regcache, floatreg, (void *)to);
3521               floatreg++;
3522               argoffset += TYPE_LENGTH (float_elt_type);
3523               len -= TYPE_LENGTH (float_elt_type);
3524             }
3525         }
3526     }
3527
3528   /* Store the struct return value in r8 if necessary.  */
3529   if (struct_return)
3530     {
3531       regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
3532     }
3533
3534   global_pointer = ia64_find_global_pointer (func_addr);
3535
3536   if (global_pointer != 0)
3537     regcache_cooked_write_unsigned (regcache, IA64_GR1_REGNUM, global_pointer);
3538
3539   regcache_cooked_write_unsigned (regcache, IA64_BR0_REGNUM, bp_addr);
3540
3541   regcache_cooked_write_unsigned (regcache, sp_regnum, sp);
3542
3543   return sp;
3544 }
3545
3546 static struct frame_id
3547 ia64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3548 {
3549   char buf[8];
3550   CORE_ADDR sp, bsp;
3551
3552   get_frame_register (this_frame, sp_regnum, buf);
3553   sp = extract_unsigned_integer (buf, 8);
3554
3555   get_frame_register (this_frame, IA64_BSP_REGNUM, buf);
3556   bsp = extract_unsigned_integer (buf, 8);
3557
3558   if (gdbarch_debug >= 1)
3559     fprintf_unfiltered (gdb_stdlog,
3560                         "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3561                         paddr_nz (get_frame_pc (this_frame)),
3562                         paddr_nz (sp), paddr_nz (bsp));
3563
3564   return frame_id_build_special (sp, get_frame_pc (this_frame), bsp);
3565 }
3566
3567 static CORE_ADDR
3568 ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3569 {
3570   char buf[8];
3571   CORE_ADDR ip, psr, pc;
3572
3573   frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3574   ip = extract_unsigned_integer (buf, 8);
3575   frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3576   psr = extract_unsigned_integer (buf, 8);
3577
3578   pc = (ip & ~0xf) | ((psr >> 41) & 3);
3579   return pc;
3580 }
3581
3582 static int
3583 ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3584 {
3585   info->bytes_per_line = SLOT_MULTIPLIER;
3586   return print_insn_ia64 (memaddr, info);
3587 }
3588
3589 static struct gdbarch *
3590 ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3591 {
3592   struct gdbarch *gdbarch;
3593   struct gdbarch_tdep *tdep;
3594
3595   /* If there is already a candidate, use it.  */
3596   arches = gdbarch_list_lookup_by_info (arches, &info);
3597   if (arches != NULL)
3598     return arches->gdbarch;
3599
3600   tdep = xmalloc (sizeof (struct gdbarch_tdep));
3601   gdbarch = gdbarch_alloc (&info, tdep);
3602
3603   tdep->sigcontext_register_address = 0;
3604   tdep->pc_in_sigtramp = 0;
3605
3606   /* According to the ia64 specs, instructions that store long double
3607      floats in memory use a long-double format different than that
3608      used in the floating registers.  The memory format matches the
3609      x86 extended float format which is 80 bits.  An OS may choose to
3610      use this format (e.g. GNU/Linux) or choose to use a different
3611      format for storing long doubles (e.g. HPUX).  In the latter case,
3612      the setting of the format may be moved/overridden in an
3613      OS-specific tdep file.  */
3614   set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext);
3615
3616   set_gdbarch_short_bit (gdbarch, 16);
3617   set_gdbarch_int_bit (gdbarch, 32);
3618   set_gdbarch_long_bit (gdbarch, 64);
3619   set_gdbarch_long_long_bit (gdbarch, 64);
3620   set_gdbarch_float_bit (gdbarch, 32);
3621   set_gdbarch_double_bit (gdbarch, 64);
3622   set_gdbarch_long_double_bit (gdbarch, 128);
3623   set_gdbarch_ptr_bit (gdbarch, 64);
3624
3625   set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3626   set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
3627   set_gdbarch_sp_regnum (gdbarch, sp_regnum);
3628   set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
3629
3630   set_gdbarch_register_name (gdbarch, ia64_register_name);
3631   set_gdbarch_register_type (gdbarch, ia64_register_type);
3632
3633   set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3634   set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3635   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3636   set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3637   set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3638   set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3639   set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
3640
3641   set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
3642
3643   set_gdbarch_return_value (gdbarch, ia64_return_value);
3644
3645   set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3646   set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3647   set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3648   set_gdbarch_read_pc (gdbarch, ia64_read_pc);
3649   set_gdbarch_write_pc (gdbarch, ia64_write_pc);
3650
3651   /* Settings for calling functions in the inferior.  */
3652   set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
3653   set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3654   set_gdbarch_dummy_id (gdbarch, ia64_dummy_id);
3655
3656   set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
3657 #ifdef HAVE_LIBUNWIND_IA64_H
3658   frame_unwind_append_unwinder (gdbarch,
3659                                 &ia64_libunwind_sigtramp_frame_unwind);
3660   frame_unwind_append_unwinder (gdbarch, &ia64_libunwind_frame_unwind);
3661   frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
3662   libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
3663 #else
3664   frame_unwind_append_unwinder (gdbarch, &ia64_sigtramp_frame_unwind);
3665 #endif
3666   frame_unwind_append_unwinder (gdbarch, &ia64_frame_unwind);
3667   frame_base_set_default (gdbarch, &ia64_frame_base);
3668
3669   /* Settings that should be unnecessary.  */
3670   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3671
3672   set_gdbarch_print_insn (gdbarch, ia64_print_insn);
3673   set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
3674
3675   /* The virtual table contains 16-byte descriptors, not pointers to
3676      descriptors.  */
3677   set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3678
3679   /* Hook in ABI-specific overrides, if they have been registered.  */
3680   gdbarch_init_osabi (info, gdbarch);
3681
3682   return gdbarch;
3683 }
3684
3685 extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3686
3687 void
3688 _initialize_ia64_tdep (void)
3689 {
3690   /* Define the ia64 floating-point format to gdb.  */
3691   builtin_type_ia64_ext =
3692     init_type (TYPE_CODE_FLT, 128 / 8,
3693                0, "builtin_type_ia64_ext", NULL);
3694   TYPE_FLOATFORMAT (builtin_type_ia64_ext) = floatformats_ia64_ext;
3695
3696   gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
3697 }