1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2/frame.h"
51 #include "user-regs.h"
53 #include "gdbsupport/common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
59 #include "riscv-ravenscar-thread.h"
61 /* The stack must be 16-byte aligned. */
62 #define SP_ALIGNMENT 16
64 /* The biggest alignment that the target supports. */
65 #define BIGGEST_ALIGNMENT 16
67 /* Define a series of is_XXX_insn functions to check if the value INSN
68 is an instance of instruction XXX. */
69 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
70 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
72 return (insn & INSN_MASK) == INSN_MATCH; \
74 #include "opcode/riscv-opc.h"
77 /* Cached information about a frame. */
79 struct riscv_unwind_cache
81 /* The register from which we can calculate the frame base. This is
82 usually $sp or $fp. */
85 /* The offset from the current value in register FRAME_BASE_REG to the
86 actual frame base address. */
87 int frame_base_offset
;
89 /* Information about previous register values. */
90 struct trad_frame_saved_reg
*regs
;
92 /* The id for this frame. */
93 struct frame_id this_id
;
95 /* The base (stack) address for this frame. This is the stack pointer
96 value on entry to this frame before any adjustments are made. */
100 /* RISC-V specific register group for CSRs. */
102 static reggroup
*csr_reggroup
= NULL
;
104 /* Callback function for user_reg_add. */
106 static struct value
*
107 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
109 const int *reg_p
= (const int *) baton
;
110 return value_of_register (*reg_p
, frame
);
113 /* Information about a register alias that needs to be set up for this
114 target. These are collected when the target's XML description is
115 analysed, and then processed later, once the gdbarch has been created. */
117 class riscv_pending_register_alias
122 riscv_pending_register_alias (const char *name
, const void *baton
)
127 /* Convert this into a user register for GDBARCH. */
129 void create (struct gdbarch
*gdbarch
) const
131 user_reg_add (gdbarch
, m_name
, value_of_riscv_user_reg
, m_baton
);
135 /* The name for this alias. */
138 /* The baton value for passing to user_reg_add. This must point to some
139 data that will live for at least as long as the gdbarch object to
140 which the user register is attached. */
144 /* Registers in the RISCV_REGISTER_FEATURE lists below are either optional,
145 or required. For example the $pc register is always going to be a
146 required register, you can't do much debugging without that. In
147 contrast, most of the CSRs are optional, GDB doesn't require them in
148 order to have a useful debug session. This enum models the difference
149 between these register types. */
151 enum riscv_register_required_status
153 /* This register is optional within this feature. */
156 /* This register is required within this feature. */
159 /* This register is required, the register must either be in this
160 feature, or it could appear within the CSR feature. */
161 RISCV_REG_REQUIRED_MAYBE_CSR
164 /* A set of registers that we expect to find in a tdesc_feature. These
165 are use in RISCV_GDBARCH_INIT when processing the target description. */
167 struct riscv_register_feature
169 /* Information for a single register. */
172 /* The GDB register number for this register. */
175 /* List of names for this register. The first name in this list is the
176 preferred name, the name GDB should use when describing this
178 std::vector
<const char *> names
;
180 /* Is this register required within this feature? In some cases the
181 register could be required, but might also be in the CSR feature. */
182 riscv_register_required_status required
;
184 /* Look in FEATURE for a register with a name from this classes names
185 list. If the register is found then register its number with
186 TDESC_DATA and add all its aliases to the ALIASES list. REG_SET is
187 used to help create the aliases. */
188 bool check (struct tdesc_arch_data
*tdesc_data
,
189 const struct tdesc_feature
*feature
,
190 const struct riscv_register_feature
*reg_set
,
191 std::vector
<riscv_pending_register_alias
> *aliases
) const;
194 /* The name for this feature. This is the name used to find this feature
195 within the target description. */
198 /* For x-regs and f-regs we always force GDB to use the first name from
199 the REGISTERS.NAMES vector, it is therefore important that we create
200 user-register aliases for all of the remaining names at indexes 1+ in
203 For CSRs we take a different approach, we prefer whatever name the
204 target description uses, in this case we want to create user-register
205 aliases for any other names that aren't the target description
208 When this flag is true we are dealing with the first case, and when
209 this is false we are dealing with the latter. */
210 bool prefer_first_name
;
212 /* List of all the registers that we expect that we might find in this
214 std::vector
<struct register_info
> registers
;
217 /* See description in the class declaration above. */
220 riscv_register_feature::register_info::check
221 (struct tdesc_arch_data
*tdesc_data
,
222 const struct tdesc_feature
*feature
,
223 const struct riscv_register_feature
*reg_set
,
224 std::vector
<riscv_pending_register_alias
> *aliases
) const
226 for (const char *name
: this->names
)
228 bool found
= tdesc_numbered_register (feature
, tdesc_data
,
232 /* We know that the target description mentions this
233 register. In RISCV_REGISTER_NAME we ensure that GDB
234 always uses the first name for each register, so here we
235 add aliases for all of the remaining names. */
236 bool prefer_first_name
= reg_set
->prefer_first_name
;
237 int start_index
= prefer_first_name
? 1 : 0;
238 for (int i
= start_index
; i
< this->names
.size (); ++i
)
240 const char *alias
= this->names
[i
];
241 if (alias
== name
&& !prefer_first_name
)
243 aliases
->emplace_back (alias
, (void *) &this->regnum
);
251 /* The general x-registers feature set. */
253 static const struct riscv_register_feature riscv_xreg_feature
=
255 "org.gnu.gdb.riscv.cpu", true,
257 { RISCV_ZERO_REGNUM
+ 0, { "zero", "x0" }, RISCV_REG_REQUIRED
},
258 { RISCV_ZERO_REGNUM
+ 1, { "ra", "x1" }, RISCV_REG_REQUIRED
},
259 { RISCV_ZERO_REGNUM
+ 2, { "sp", "x2" }, RISCV_REG_REQUIRED
},
260 { RISCV_ZERO_REGNUM
+ 3, { "gp", "x3" }, RISCV_REG_REQUIRED
},
261 { RISCV_ZERO_REGNUM
+ 4, { "tp", "x4" }, RISCV_REG_REQUIRED
},
262 { RISCV_ZERO_REGNUM
+ 5, { "t0", "x5" }, RISCV_REG_REQUIRED
},
263 { RISCV_ZERO_REGNUM
+ 6, { "t1", "x6" }, RISCV_REG_REQUIRED
},
264 { RISCV_ZERO_REGNUM
+ 7, { "t2", "x7" }, RISCV_REG_REQUIRED
},
265 { RISCV_ZERO_REGNUM
+ 8, { "fp", "x8", "s0" }, RISCV_REG_REQUIRED
},
266 { RISCV_ZERO_REGNUM
+ 9, { "s1", "x9" }, RISCV_REG_REQUIRED
},
267 { RISCV_ZERO_REGNUM
+ 10, { "a0", "x10" }, RISCV_REG_REQUIRED
},
268 { RISCV_ZERO_REGNUM
+ 11, { "a1", "x11" }, RISCV_REG_REQUIRED
},
269 { RISCV_ZERO_REGNUM
+ 12, { "a2", "x12" }, RISCV_REG_REQUIRED
},
270 { RISCV_ZERO_REGNUM
+ 13, { "a3", "x13" }, RISCV_REG_REQUIRED
},
271 { RISCV_ZERO_REGNUM
+ 14, { "a4", "x14" }, RISCV_REG_REQUIRED
},
272 { RISCV_ZERO_REGNUM
+ 15, { "a5", "x15" }, RISCV_REG_REQUIRED
},
273 { RISCV_ZERO_REGNUM
+ 16, { "a6", "x16" }, RISCV_REG_REQUIRED
},
274 { RISCV_ZERO_REGNUM
+ 17, { "a7", "x17" }, RISCV_REG_REQUIRED
},
275 { RISCV_ZERO_REGNUM
+ 18, { "s2", "x18" }, RISCV_REG_REQUIRED
},
276 { RISCV_ZERO_REGNUM
+ 19, { "s3", "x19" }, RISCV_REG_REQUIRED
},
277 { RISCV_ZERO_REGNUM
+ 20, { "s4", "x20" }, RISCV_REG_REQUIRED
},
278 { RISCV_ZERO_REGNUM
+ 21, { "s5", "x21" }, RISCV_REG_REQUIRED
},
279 { RISCV_ZERO_REGNUM
+ 22, { "s6", "x22" }, RISCV_REG_REQUIRED
},
280 { RISCV_ZERO_REGNUM
+ 23, { "s7", "x23" }, RISCV_REG_REQUIRED
},
281 { RISCV_ZERO_REGNUM
+ 24, { "s8", "x24" }, RISCV_REG_REQUIRED
},
282 { RISCV_ZERO_REGNUM
+ 25, { "s9", "x25" }, RISCV_REG_REQUIRED
},
283 { RISCV_ZERO_REGNUM
+ 26, { "s10", "x26" }, RISCV_REG_REQUIRED
},
284 { RISCV_ZERO_REGNUM
+ 27, { "s11", "x27" }, RISCV_REG_REQUIRED
},
285 { RISCV_ZERO_REGNUM
+ 28, { "t3", "x28" }, RISCV_REG_REQUIRED
},
286 { RISCV_ZERO_REGNUM
+ 29, { "t4", "x29" }, RISCV_REG_REQUIRED
},
287 { RISCV_ZERO_REGNUM
+ 30, { "t5", "x30" }, RISCV_REG_REQUIRED
},
288 { RISCV_ZERO_REGNUM
+ 31, { "t6", "x31" }, RISCV_REG_REQUIRED
},
289 { RISCV_ZERO_REGNUM
+ 32, { "pc" }, RISCV_REG_REQUIRED
}
293 /* The f-registers feature set. */
295 static const struct riscv_register_feature riscv_freg_feature
=
297 "org.gnu.gdb.riscv.fpu", true,
299 { RISCV_FIRST_FP_REGNUM
+ 0, { "ft0", "f0" }, RISCV_REG_REQUIRED
},
300 { RISCV_FIRST_FP_REGNUM
+ 1, { "ft1", "f1" }, RISCV_REG_REQUIRED
},
301 { RISCV_FIRST_FP_REGNUM
+ 2, { "ft2", "f2" }, RISCV_REG_REQUIRED
},
302 { RISCV_FIRST_FP_REGNUM
+ 3, { "ft3", "f3" }, RISCV_REG_REQUIRED
},
303 { RISCV_FIRST_FP_REGNUM
+ 4, { "ft4", "f4" }, RISCV_REG_REQUIRED
},
304 { RISCV_FIRST_FP_REGNUM
+ 5, { "ft5", "f5" }, RISCV_REG_REQUIRED
},
305 { RISCV_FIRST_FP_REGNUM
+ 6, { "ft6", "f6" }, RISCV_REG_REQUIRED
},
306 { RISCV_FIRST_FP_REGNUM
+ 7, { "ft7", "f7" }, RISCV_REG_REQUIRED
},
307 { RISCV_FIRST_FP_REGNUM
+ 8, { "fs0", "f8" }, RISCV_REG_REQUIRED
},
308 { RISCV_FIRST_FP_REGNUM
+ 9, { "fs1", "f9" }, RISCV_REG_REQUIRED
},
309 { RISCV_FIRST_FP_REGNUM
+ 10, { "fa0", "f10" }, RISCV_REG_REQUIRED
},
310 { RISCV_FIRST_FP_REGNUM
+ 11, { "fa1", "f11" }, RISCV_REG_REQUIRED
},
311 { RISCV_FIRST_FP_REGNUM
+ 12, { "fa2", "f12" }, RISCV_REG_REQUIRED
},
312 { RISCV_FIRST_FP_REGNUM
+ 13, { "fa3", "f13" }, RISCV_REG_REQUIRED
},
313 { RISCV_FIRST_FP_REGNUM
+ 14, { "fa4", "f14" }, RISCV_REG_REQUIRED
},
314 { RISCV_FIRST_FP_REGNUM
+ 15, { "fa5", "f15" }, RISCV_REG_REQUIRED
},
315 { RISCV_FIRST_FP_REGNUM
+ 16, { "fa6", "f16" }, RISCV_REG_REQUIRED
},
316 { RISCV_FIRST_FP_REGNUM
+ 17, { "fa7", "f17" }, RISCV_REG_REQUIRED
},
317 { RISCV_FIRST_FP_REGNUM
+ 18, { "fs2", "f18" }, RISCV_REG_REQUIRED
},
318 { RISCV_FIRST_FP_REGNUM
+ 19, { "fs3", "f19" }, RISCV_REG_REQUIRED
},
319 { RISCV_FIRST_FP_REGNUM
+ 20, { "fs4", "f20" }, RISCV_REG_REQUIRED
},
320 { RISCV_FIRST_FP_REGNUM
+ 21, { "fs5", "f21" }, RISCV_REG_REQUIRED
},
321 { RISCV_FIRST_FP_REGNUM
+ 22, { "fs6", "f22" }, RISCV_REG_REQUIRED
},
322 { RISCV_FIRST_FP_REGNUM
+ 23, { "fs7", "f23" }, RISCV_REG_REQUIRED
},
323 { RISCV_FIRST_FP_REGNUM
+ 24, { "fs8", "f24" }, RISCV_REG_REQUIRED
},
324 { RISCV_FIRST_FP_REGNUM
+ 25, { "fs9", "f25" }, RISCV_REG_REQUIRED
},
325 { RISCV_FIRST_FP_REGNUM
+ 26, { "fs10", "f26" }, RISCV_REG_REQUIRED
},
326 { RISCV_FIRST_FP_REGNUM
+ 27, { "fs11", "f27" }, RISCV_REG_REQUIRED
},
327 { RISCV_FIRST_FP_REGNUM
+ 28, { "ft8", "f28" }, RISCV_REG_REQUIRED
},
328 { RISCV_FIRST_FP_REGNUM
+ 29, { "ft9", "f29" }, RISCV_REG_REQUIRED
},
329 { RISCV_FIRST_FP_REGNUM
+ 30, { "ft10", "f30" }, RISCV_REG_REQUIRED
},
330 { RISCV_FIRST_FP_REGNUM
+ 31, { "ft11", "f31" }, RISCV_REG_REQUIRED
},
332 { RISCV_CSR_FFLAGS_REGNUM
, { "fflags", "csr1" }, RISCV_REG_REQUIRED_MAYBE_CSR
},
333 { RISCV_CSR_FRM_REGNUM
, { "frm", "csr2" }, RISCV_REG_REQUIRED_MAYBE_CSR
},
334 { RISCV_CSR_FCSR_REGNUM
, { "fcsr", "csr3" }, RISCV_REG_REQUIRED_MAYBE_CSR
},
339 /* Set of virtual registers. These are not physical registers on the
340 hardware, but might be available from the target. These are not pseudo
341 registers, reading these really does result in a register read from the
342 target, it is just that there might not be a physical register backing
345 static const struct riscv_register_feature riscv_virtual_feature
=
347 "org.gnu.gdb.riscv.virtual", false,
349 { RISCV_PRIV_REGNUM
, { "priv" }, RISCV_REG_OPTIONAL
}
353 /* Feature set for CSRs. This set is NOT constant as the register names
354 list for each register is not complete. The aliases are computed
355 during RISCV_CREATE_CSR_ALIASES. */
357 static struct riscv_register_feature riscv_csr_feature
=
359 "org.gnu.gdb.riscv.csr", false,
361 #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
362 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, RISCV_REG_OPTIONAL },
363 #include "opcode/riscv-opc.h"
368 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
369 to the name list for each register. */
372 riscv_create_csr_aliases ()
374 for (auto ®
: riscv_csr_feature
.registers
)
376 int csr_num
= reg
.regnum
- RISCV_FIRST_CSR_REGNUM
;
377 const char *alias
= xstrprintf ("csr%d", csr_num
);
378 reg
.names
.push_back (alias
);
380 /* Setup the other csr aliases. We don't use a switch table here in
381 case there are multiple aliases with the same value. Also filter
382 based on ABRT_VER in order to avoid a very old alias for misa that
383 duplicates the name "misa" but at a different CSR address. */
384 #define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \
385 if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \
386 reg.names.push_back ( # NAME );
387 #include "opcode/riscv-opc.h"
388 #undef DECLARE_CSR_ALIAS
392 /* Controls whether we place compressed breakpoints or not. When in auto
393 mode GDB tries to determine if the target supports compressed
394 breakpoints, and uses them if it does. */
396 static enum auto_boolean use_compressed_breakpoints
;
398 /* The show callback for 'show riscv use-compressed-breakpoints'. */
401 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
402 struct cmd_list_element
*c
,
405 fprintf_filtered (file
,
406 _("Debugger's use of compressed breakpoints is set "
410 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
412 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
413 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
415 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
417 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
418 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
420 /* The show callback for all 'show debug riscv VARNAME' variables. */
423 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
424 struct cmd_list_element
*c
,
427 fprintf_filtered (file
,
428 _("RiscV debug variable `%s' is set to: %s\n"),
432 /* When this is set to non-zero debugging information about breakpoint
433 kinds will be printed. */
435 static unsigned int riscv_debug_breakpoints
= 0;
437 /* When this is set to non-zero debugging information about inferior calls
440 static unsigned int riscv_debug_infcall
= 0;
442 /* When this is set to non-zero debugging information about stack unwinding
445 static unsigned int riscv_debug_unwinder
= 0;
447 /* When this is set to non-zero debugging information about gdbarch
448 initialisation will be printed. */
450 static unsigned int riscv_debug_gdbarch
= 0;
452 /* See riscv-tdep.h. */
455 riscv_isa_xlen (struct gdbarch
*gdbarch
)
457 return gdbarch_tdep (gdbarch
)->isa_features
.xlen
;
460 /* See riscv-tdep.h. */
463 riscv_abi_xlen (struct gdbarch
*gdbarch
)
465 return gdbarch_tdep (gdbarch
)->abi_features
.xlen
;
468 /* See riscv-tdep.h. */
471 riscv_isa_flen (struct gdbarch
*gdbarch
)
473 return gdbarch_tdep (gdbarch
)->isa_features
.flen
;
476 /* See riscv-tdep.h. */
479 riscv_abi_flen (struct gdbarch
*gdbarch
)
481 return gdbarch_tdep (gdbarch
)->abi_features
.flen
;
484 /* Return true if the target for GDBARCH has floating point hardware. */
487 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
489 return (riscv_isa_flen (gdbarch
) > 0);
492 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
495 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
497 return gdbarch_tdep (gdbarch
)->abi_features
.flen
> 0;
500 /* Return true if REGNO is a floating pointer register. */
503 riscv_is_fp_regno_p (int regno
)
505 return (regno
>= RISCV_FIRST_FP_REGNUM
506 && regno
<= RISCV_LAST_FP_REGNUM
);
509 /* Implement the breakpoint_kind_from_pc gdbarch method. */
512 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
514 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
516 bool unaligned_p
= false;
519 /* Some targets don't support unaligned reads. The address can only
520 be unaligned if the C extension is supported. So it is safe to
521 use a compressed breakpoint in this case. */
526 /* Read the opcode byte to determine the instruction length. If
527 the read fails this may be because we tried to set the
528 breakpoint at an invalid address, in this case we provide a
529 fake result which will give a breakpoint length of 4.
530 Hopefully when we try to actually insert the breakpoint we
531 will see a failure then too which will be reported to the
533 if (target_read_code (*pcptr
, buf
, 1) == -1)
535 read_code (*pcptr
, buf
, 1);
538 if (riscv_debug_breakpoints
)
540 const char *bp
= (unaligned_p
|| riscv_insn_length (buf
[0]) == 2
541 ? "C.EBREAK" : "EBREAK");
543 fprintf_unfiltered (gdb_stdlog
, "Using %s for breakpoint at %s ",
544 bp
, paddress (gdbarch
, *pcptr
));
546 fprintf_unfiltered (gdb_stdlog
, "(unaligned address)\n");
548 fprintf_unfiltered (gdb_stdlog
, "(instruction length %d)\n",
549 riscv_insn_length (buf
[0]));
551 if (unaligned_p
|| riscv_insn_length (buf
[0]) == 2)
556 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
562 /* Implement the sw_breakpoint_from_kind gdbarch method. */
564 static const gdb_byte
*
565 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
567 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
568 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
578 gdb_assert_not_reached (_("unhandled breakpoint kind"));
582 /* Implement the register_name gdbarch method. This is used instead of
583 the function supplied by calling TDESC_USE_REGISTERS so that we can
584 ensure the preferred names are offered for x-regs and f-regs. */
587 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
589 /* Lookup the name through the target description. If we get back NULL
590 then this is an unknown register. If we do get a name back then we
591 look up the registers preferred name below. */
592 const char *name
= tdesc_register_name (gdbarch
, regnum
);
593 if (name
== NULL
|| name
[0] == '\0')
596 /* We want GDB to use the ABI names for registers even if the target
597 gives us a target description with the architectural name. For
598 example we want to see 'ra' instead of 'x1' whatever the target
599 description called it. */
600 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
< RISCV_FIRST_FP_REGNUM
)
602 gdb_assert (regnum
< riscv_xreg_feature
.registers
.size ());
603 return riscv_xreg_feature
.registers
[regnum
].names
[0];
606 /* Like with the x-regs we prefer the abi names for the floating point
608 if (regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
610 if (riscv_has_fp_regs (gdbarch
))
612 regnum
-= RISCV_FIRST_FP_REGNUM
;
613 gdb_assert (regnum
< riscv_freg_feature
.registers
.size ());
614 return riscv_freg_feature
.registers
[regnum
].names
[0];
620 /* The remaining registers are different. For all other registers on the
621 machine we prefer to see the names that the target description
622 provides. This is particularly important for CSRs which might be
623 renamed over time. If GDB keeps track of the "latest" name, but a
624 particular target provides an older name then we don't want to force
625 users to see the newer name in register output.
627 The other case that reaches here are any registers that the target
628 provided that GDB is completely unaware of. For these we have no
629 choice but to accept the target description name.
631 Just accept whatever name TDESC_REGISTER_NAME returned. */
635 /* Construct a type for 64-bit FP registers. */
638 riscv_fpreg_d_type (struct gdbarch
*gdbarch
)
640 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
642 if (tdep
->riscv_fpreg_d_type
== nullptr)
644 const struct builtin_type
*bt
= builtin_type (gdbarch
);
646 /* The type we're building is this: */
648 union __gdb_builtin_type_fpreg_d
657 t
= arch_composite_type (gdbarch
,
658 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION
);
659 append_composite_type_field (t
, "float", bt
->builtin_float
);
660 append_composite_type_field (t
, "double", bt
->builtin_double
);
662 t
->set_name ("builtin_type_fpreg_d");
663 tdep
->riscv_fpreg_d_type
= t
;
666 return tdep
->riscv_fpreg_d_type
;
669 /* Implement the register_type gdbarch method. This is installed as an
670 for the override setup by TDESC_USE_REGISTERS, for most registers we
671 delegate the type choice to the target description, but for a few
672 registers we try to improve the types if the target description has
673 taken a simplistic approach. */
676 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
678 struct type
*type
= tdesc_register_type (gdbarch
, regnum
);
679 int xlen
= riscv_isa_xlen (gdbarch
);
681 /* We want to perform some specific type "fixes" in cases where we feel
682 that we really can do better than the target description. For all
683 other cases we just return what the target description says. */
684 if (riscv_is_fp_regno_p (regnum
))
686 /* This spots the case for RV64 where the double is defined as
687 either 'ieee_double' or 'float' (which is the generic name that
688 converts to 'double' on 64-bit). In these cases its better to
689 present the registers using a union type. */
690 int flen
= riscv_isa_flen (gdbarch
);
692 && type
->code () == TYPE_CODE_FLT
693 && TYPE_LENGTH (type
) == flen
694 && (strcmp (type
->name (), "builtin_type_ieee_double") == 0
695 || strcmp (type
->name (), "double") == 0))
696 type
= riscv_fpreg_d_type (gdbarch
);
699 if ((regnum
== gdbarch_pc_regnum (gdbarch
)
700 || regnum
== RISCV_RA_REGNUM
701 || regnum
== RISCV_FP_REGNUM
702 || regnum
== RISCV_SP_REGNUM
703 || regnum
== RISCV_GP_REGNUM
704 || regnum
== RISCV_TP_REGNUM
)
705 && type
->code () == TYPE_CODE_INT
706 && TYPE_LENGTH (type
) == xlen
)
708 /* This spots the case where some interesting registers are defined
709 as simple integers of the expected size, we force these registers
710 to be pointers as we believe that is more useful. */
711 if (regnum
== gdbarch_pc_regnum (gdbarch
)
712 || regnum
== RISCV_RA_REGNUM
)
713 type
= builtin_type (gdbarch
)->builtin_func_ptr
;
714 else if (regnum
== RISCV_FP_REGNUM
715 || regnum
== RISCV_SP_REGNUM
716 || regnum
== RISCV_GP_REGNUM
717 || regnum
== RISCV_TP_REGNUM
)
718 type
= builtin_type (gdbarch
)->builtin_data_ptr
;
724 /* Helper for riscv_print_registers_info, prints info for a single register
728 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
729 struct ui_file
*file
,
730 struct frame_info
*frame
,
733 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
735 struct type
*regtype
;
736 int print_raw_format
;
737 enum tab_stops
{ value_column_1
= 15 };
739 fputs_filtered (name
, file
);
740 print_spaces_filtered (value_column_1
- strlen (name
), file
);
744 val
= value_of_register (regnum
, frame
);
745 regtype
= value_type (val
);
747 catch (const gdb_exception_error
&ex
)
749 /* Handle failure to read a register without interrupting the entire
750 'info registers' flow. */
751 fprintf_filtered (file
, "%s\n", ex
.what ());
755 print_raw_format
= (value_entirely_available (val
)
756 && !value_optimized_out (val
));
758 if (regtype
->code () == TYPE_CODE_FLT
759 || (regtype
->code () == TYPE_CODE_UNION
760 && regtype
->num_fields () == 2
761 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
762 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
)
763 || (regtype
->code () == TYPE_CODE_UNION
764 && regtype
->num_fields () == 3
765 && regtype
->field (0).type ()->code () == TYPE_CODE_FLT
766 && regtype
->field (1).type ()->code () == TYPE_CODE_FLT
767 && regtype
->field (2).type ()->code () == TYPE_CODE_FLT
))
769 struct value_print_options opts
;
770 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
771 enum bfd_endian byte_order
= type_byte_order (regtype
);
773 get_user_print_options (&opts
);
776 common_val_print (val
, file
, 0, &opts
, current_language
);
778 if (print_raw_format
)
780 fprintf_filtered (file
, "\t(raw ");
781 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
783 fprintf_filtered (file
, ")");
788 struct value_print_options opts
;
790 /* Print the register in hex. */
791 get_formatted_print_options (&opts
, 'x');
793 common_val_print (val
, file
, 0, &opts
, current_language
);
795 if (print_raw_format
)
797 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
800 int size
= register_size (gdbarch
, regnum
);
803 /* The SD field is always in the upper bit of MSTATUS, regardless
804 of the number of bits in MSTATUS. */
805 d
= value_as_long (val
);
807 fprintf_filtered (file
,
808 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
809 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
810 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
811 (int) ((d
>> (xlen
- 1)) & 0x1),
812 (int) ((d
>> 24) & 0x1f),
813 (int) ((d
>> 19) & 0x1),
814 (int) ((d
>> 18) & 0x1),
815 (int) ((d
>> 17) & 0x1),
816 (int) ((d
>> 15) & 0x3),
817 (int) ((d
>> 13) & 0x3),
818 (int) ((d
>> 11) & 0x3),
819 (int) ((d
>> 9) & 0x3),
820 (int) ((d
>> 8) & 0x1),
821 (int) ((d
>> 7) & 0x1),
822 (int) ((d
>> 6) & 0x1),
823 (int) ((d
>> 5) & 0x1),
824 (int) ((d
>> 4) & 0x1),
825 (int) ((d
>> 3) & 0x1),
826 (int) ((d
>> 2) & 0x1),
827 (int) ((d
>> 1) & 0x1),
828 (int) ((d
>> 0) & 0x1));
830 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
835 int size
= register_size (gdbarch
, regnum
);
837 /* The MXL field is always in the upper two bits of MISA,
838 regardless of the number of bits in MISA. Mask out other
839 bits to ensure we have a positive value. */
840 d
= value_as_long (val
);
841 base
= (d
>> ((size
* 8) - 2)) & 0x3;
844 for (; base
> 0; base
--)
846 fprintf_filtered (file
, "\tRV%d", xlen
);
848 for (i
= 0; i
< 26; i
++)
851 fprintf_filtered (file
, "%c", 'A' + i
);
854 else if (regnum
== RISCV_CSR_FCSR_REGNUM
855 || regnum
== RISCV_CSR_FFLAGS_REGNUM
856 || regnum
== RISCV_CSR_FRM_REGNUM
)
860 d
= value_as_long (val
);
862 fprintf_filtered (file
, "\t");
863 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
864 fprintf_filtered (file
,
865 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
866 (int) ((d
>> 5) & 0x7),
867 (int) ((d
>> 4) & 0x1),
868 (int) ((d
>> 3) & 0x1),
869 (int) ((d
>> 2) & 0x1),
870 (int) ((d
>> 1) & 0x1),
871 (int) ((d
>> 0) & 0x1));
873 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
875 static const char * const sfrm
[] =
877 "RNE (round to nearest; ties to even)",
878 "RTZ (Round towards zero)",
879 "RDN (Round down towards -INF)",
880 "RUP (Round up towards +INF)",
881 "RMM (Round to nearest; ties to max magnitude)",
884 "dynamic rounding mode",
886 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
887 ? (d
>> 5) : d
) & 0x3;
889 fprintf_filtered (file
, "%sFRM:%i [%s]",
890 (regnum
== RISCV_CSR_FCSR_REGNUM
895 else if (regnum
== RISCV_PRIV_REGNUM
)
900 d
= value_as_long (val
);
905 static const char * const sprv
[] =
912 fprintf_filtered (file
, "\tprv:%d [%s]",
916 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
920 /* If not a vector register, print it also according to its
922 if (TYPE_VECTOR (regtype
) == 0)
924 get_user_print_options (&opts
);
926 fprintf_filtered (file
, "\t");
927 common_val_print (val
, file
, 0, &opts
, current_language
);
932 fprintf_filtered (file
, "\n");
935 /* Return true if REGNUM is a valid CSR register. The CSR register space
936 is sparsely populated, so not every number is a named CSR. */
939 riscv_is_regnum_a_named_csr (int regnum
)
941 gdb_assert (regnum
>= RISCV_FIRST_CSR_REGNUM
942 && regnum
<= RISCV_LAST_CSR_REGNUM
);
946 #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM:
947 #include "opcode/riscv-opc.h"
956 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
960 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
961 struct reggroup
*reggroup
)
963 /* Used by 'info registers' and 'info registers <groupname>'. */
965 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
966 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
969 if (regnum
> RISCV_LAST_REGNUM
)
971 int ret
= tdesc_register_in_reggroup_p (gdbarch
, regnum
, reggroup
);
975 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
978 if (reggroup
== all_reggroup
)
980 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
982 if (riscv_is_regnum_a_named_csr (regnum
))
986 else if (reggroup
== float_reggroup
)
987 return (riscv_is_fp_regno_p (regnum
)
988 || regnum
== RISCV_CSR_FCSR_REGNUM
989 || regnum
== RISCV_CSR_FFLAGS_REGNUM
990 || regnum
== RISCV_CSR_FRM_REGNUM
);
991 else if (reggroup
== general_reggroup
)
992 return regnum
< RISCV_FIRST_FP_REGNUM
;
993 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
995 if (riscv_has_fp_regs (gdbarch
))
996 return (regnum
<= RISCV_LAST_FP_REGNUM
997 || regnum
== RISCV_CSR_FCSR_REGNUM
998 || regnum
== RISCV_CSR_FFLAGS_REGNUM
999 || regnum
== RISCV_CSR_FRM_REGNUM
);
1001 return regnum
< RISCV_FIRST_FP_REGNUM
;
1003 else if (reggroup
== system_reggroup
|| reggroup
== csr_reggroup
)
1005 if (regnum
== RISCV_PRIV_REGNUM
)
1007 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
1009 if (riscv_is_regnum_a_named_csr (regnum
))
1013 else if (reggroup
== vector_reggroup
)
1019 /* Implement the print_registers_info gdbarch method. This is used by
1020 'info registers' and 'info all-registers'. */
1023 riscv_print_registers_info (struct gdbarch
*gdbarch
,
1024 struct ui_file
*file
,
1025 struct frame_info
*frame
,
1026 int regnum
, int print_all
)
1030 /* Print one specified register. */
1031 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1032 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1033 error (_("Not a valid register for the current processor type"));
1034 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1038 struct reggroup
*reggroup
;
1041 reggroup
= all_reggroup
;
1043 reggroup
= general_reggroup
;
1045 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
1047 /* Zero never changes, so might as well hide by default. */
1048 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
1051 /* Registers with no name are not valid on this ISA. */
1052 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1053 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
1056 /* Is the register in the group we're interested in? */
1057 if (!gdbarch_register_reggroup_p (gdbarch
, regnum
, reggroup
))
1060 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
1065 /* Class that handles one decoded RiscV instruction. */
1071 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1074 /* Unknown value is used at initialisation time. */
1077 /* These instructions are all the ones we are interested in during the
1087 /* These are needed for software breakpoint support. */
1096 /* These are needed for stepping over atomic sequences. */
1100 /* Other instructions are not interesting during the prologue scan, and
1115 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
1117 /* Get the length of the instruction in bytes. */
1119 { return m_length
; }
1121 /* Get the opcode for this instruction. */
1122 enum opcode
opcode () const
1123 { return m_opcode
; }
1125 /* Get destination register field for this instruction. This is only
1126 valid if the OPCODE implies there is such a field for this
1131 /* Get the RS1 register field for this instruction. This is only valid
1132 if the OPCODE implies there is such a field for this instruction. */
1136 /* Get the RS2 register field for this instruction. This is only valid
1137 if the OPCODE implies there is such a field for this instruction. */
1141 /* Get the immediate for this instruction in signed form. This is only
1142 valid if the OPCODE implies there is such a field for this
1144 int imm_signed () const
1149 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1150 int decode_register_index (unsigned long opcode
, int offset
)
1152 return (opcode
>> offset
) & 0x1F;
1155 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1156 int decode_register_index_short (unsigned long opcode
, int offset
)
1158 return ((opcode
>> offset
) & 0x7) + 8;
1161 /* Helper for DECODE, decode 32-bit R-type instruction. */
1162 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
1165 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1166 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1167 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1170 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1171 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
1174 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1175 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1178 /* Helper for DECODE, decode 32-bit I-type instruction. */
1179 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
1182 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1183 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1184 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
1187 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1188 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
1191 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
1192 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
1195 /* Helper for DECODE, decode 32-bit S-type instruction. */
1196 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
1199 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1200 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1201 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
1204 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1205 encoding is different for each CS format instruction, so extracting
1206 the immediate is left up to the caller, who should pass the extracted
1207 immediate value through in IMM. */
1208 void decode_cs_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1212 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1213 m_rs2
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1216 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1217 encoding is different for each CSS format instruction, so extracting
1218 the immediate is left up to the caller, who should pass the extracted
1219 immediate value through in IMM. */
1220 void decode_css_type_insn (enum opcode opcode
, ULONGEST ival
, int imm
)
1224 m_rs1
= RISCV_SP_REGNUM
;
1225 /* Not a compressed register number in this case. */
1226 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
1229 /* Helper for DECODE, decode 32-bit U-type instruction. */
1230 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
1233 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1234 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1237 /* Helper for DECODE, decode 32-bit J-type instruction. */
1238 void decode_j_type_insn (enum opcode opcode
, ULONGEST ival
)
1241 m_rd
= decode_register_index (ival
, OP_SH_RD
);
1242 m_imm
.s
= EXTRACT_UJTYPE_IMM (ival
);
1245 /* Helper for DECODE, decode 32-bit J-type instruction. */
1246 void decode_cj_type_insn (enum opcode opcode
, ULONGEST ival
)
1249 m_imm
.s
= EXTRACT_RVC_J_IMM (ival
);
1252 void decode_b_type_insn (enum opcode opcode
, ULONGEST ival
)
1255 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
1256 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
1257 m_imm
.s
= EXTRACT_SBTYPE_IMM (ival
);
1260 void decode_cb_type_insn (enum opcode opcode
, ULONGEST ival
)
1263 m_rs1
= decode_register_index_short (ival
, OP_SH_CRS1S
);
1264 m_imm
.s
= EXTRACT_RVC_B_IMM (ival
);
1267 /* Fetch instruction from target memory at ADDR, return the content of
1268 the instruction, and update LEN with the instruction length. */
1269 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1270 CORE_ADDR addr
, int *len
);
1272 /* The length of the instruction in bytes. Should be 2 or 4. */
1275 /* The instruction opcode. */
1276 enum opcode m_opcode
;
1278 /* The three possible registers an instruction might reference. Not
1279 every instruction fills in all of these registers. Which fields are
1280 valid depends on the opcode. The naming of these fields matches the
1281 naming in the riscv isa manual. */
1286 /* Possible instruction immediate. This is only valid if the instruction
1287 format contains an immediate, not all instruction, whether this is
1288 valid depends on the opcode. Despite only having one format for now
1289 the immediate is packed into a union, later instructions might require
1290 an unsigned formatted immediate, having the union in place now will
1291 reduce the need for code churn later. */
1292 union riscv_insn_immediate
1294 riscv_insn_immediate ()
1304 /* Fetch instruction from target memory at ADDR, return the content of the
1305 instruction, and update LEN with the instruction length. */
1308 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1309 CORE_ADDR addr
, int *len
)
1311 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1313 int instlen
, status
;
1315 /* All insns are at least 16 bits. */
1316 status
= target_read_memory (addr
, buf
, 2);
1318 memory_error (TARGET_XFER_E_IO
, addr
);
1320 /* If we need more, grab it now. */
1321 instlen
= riscv_insn_length (buf
[0]);
1322 gdb_assert (instlen
<= sizeof (buf
));
1327 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1329 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1332 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1335 /* Fetch from target memory an instruction at PC and decode it. This can
1336 throw an error if the memory access fails, callers are responsible for
1337 handling this error if that is appropriate. */
1340 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1344 /* Fetch the instruction, and the instructions length. */
1345 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1349 if (is_add_insn (ival
))
1350 decode_r_type_insn (ADD
, ival
);
1351 else if (is_addw_insn (ival
))
1352 decode_r_type_insn (ADDW
, ival
);
1353 else if (is_addi_insn (ival
))
1354 decode_i_type_insn (ADDI
, ival
);
1355 else if (is_addiw_insn (ival
))
1356 decode_i_type_insn (ADDIW
, ival
);
1357 else if (is_auipc_insn (ival
))
1358 decode_u_type_insn (AUIPC
, ival
);
1359 else if (is_lui_insn (ival
))
1360 decode_u_type_insn (LUI
, ival
);
1361 else if (is_sd_insn (ival
))
1362 decode_s_type_insn (SD
, ival
);
1363 else if (is_sw_insn (ival
))
1364 decode_s_type_insn (SW
, ival
);
1365 else if (is_jal_insn (ival
))
1366 decode_j_type_insn (JAL
, ival
);
1367 else if (is_jalr_insn (ival
))
1368 decode_i_type_insn (JALR
, ival
);
1369 else if (is_beq_insn (ival
))
1370 decode_b_type_insn (BEQ
, ival
);
1371 else if (is_bne_insn (ival
))
1372 decode_b_type_insn (BNE
, ival
);
1373 else if (is_blt_insn (ival
))
1374 decode_b_type_insn (BLT
, ival
);
1375 else if (is_bge_insn (ival
))
1376 decode_b_type_insn (BGE
, ival
);
1377 else if (is_bltu_insn (ival
))
1378 decode_b_type_insn (BLTU
, ival
);
1379 else if (is_bgeu_insn (ival
))
1380 decode_b_type_insn (BGEU
, ival
);
1381 else if (is_lr_w_insn (ival
))
1382 decode_r_type_insn (LR
, ival
);
1383 else if (is_lr_d_insn (ival
))
1384 decode_r_type_insn (LR
, ival
);
1385 else if (is_sc_w_insn (ival
))
1386 decode_r_type_insn (SC
, ival
);
1387 else if (is_sc_d_insn (ival
))
1388 decode_r_type_insn (SC
, ival
);
1390 /* None of the other fields are valid in this case. */
1393 else if (m_length
== 2)
1395 int xlen
= riscv_isa_xlen (gdbarch
);
1397 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1398 C_JALR. So must try to match C_JALR first as it has more bits in
1400 if (is_c_jalr_insn (ival
))
1401 decode_cr_type_insn (JALR
, ival
);
1402 else if (is_c_add_insn (ival
))
1403 decode_cr_type_insn (ADD
, ival
);
1404 /* C_ADDW is RV64 and RV128 only. */
1405 else if (xlen
!= 4 && is_c_addw_insn (ival
))
1406 decode_cr_type_insn (ADDW
, ival
);
1407 else if (is_c_addi_insn (ival
))
1408 decode_ci_type_insn (ADDI
, ival
);
1409 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1410 only and C_JAL is RV32 only. */
1411 else if (xlen
!= 4 && is_c_addiw_insn (ival
))
1412 decode_ci_type_insn (ADDIW
, ival
);
1413 else if (xlen
== 4 && is_c_jal_insn (ival
))
1414 decode_cj_type_insn (JAL
, ival
);
1415 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1416 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1418 else if (is_c_addi16sp_insn (ival
))
1421 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1422 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1424 else if (is_c_addi4spn_insn (ival
))
1427 m_rd
= decode_register_index_short (ival
, OP_SH_CRS2S
);
1428 m_rs1
= RISCV_SP_REGNUM
;
1429 m_imm
.s
= EXTRACT_RVC_ADDI4SPN_IMM (ival
);
1431 else if (is_c_lui_insn (ival
))
1434 m_rd
= decode_register_index (ival
, OP_SH_CRS1S
);
1435 m_imm
.s
= EXTRACT_RVC_LUI_IMM (ival
);
1437 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1438 and C_FSW is RV32 only. */
1439 else if (xlen
!= 4 && is_c_sd_insn (ival
))
1440 decode_cs_type_insn (SD
, ival
, EXTRACT_RVC_LD_IMM (ival
));
1441 else if (is_c_sw_insn (ival
))
1442 decode_cs_type_insn (SW
, ival
, EXTRACT_RVC_LW_IMM (ival
));
1443 else if (is_c_swsp_insn (ival
))
1444 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SWSP_IMM (ival
));
1445 else if (xlen
!= 4 && is_c_sdsp_insn (ival
))
1446 decode_css_type_insn (SW
, ival
, EXTRACT_RVC_SDSP_IMM (ival
));
1447 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1448 So must try to match C_JR first as it ahs more bits in mask. */
1449 else if (is_c_jr_insn (ival
))
1450 decode_cr_type_insn (JALR
, ival
);
1451 else if (is_c_j_insn (ival
))
1452 decode_cj_type_insn (JAL
, ival
);
1453 else if (is_c_beqz_insn (ival
))
1454 decode_cb_type_insn (BEQ
, ival
);
1455 else if (is_c_bnez_insn (ival
))
1456 decode_cb_type_insn (BNE
, ival
);
1458 /* None of the other fields of INSN are valid in this case. */
1463 /* This must be a 6 or 8 byte instruction, we don't currently decode
1464 any of these, so just ignore it. */
1465 gdb_assert (m_length
== 6 || m_length
== 8);
1470 /* The prologue scanner. This is currently only used for skipping the
1471 prologue of a function when the DWARF information is not sufficient.
1472 However, it is written with filling of the frame cache in mind, which
1473 is why different groups of stack setup instructions are split apart
1474 during the core of the inner loop. In the future, the intention is to
1475 extend this function to fully support building up a frame cache that
1476 can unwind register values when there is no DWARF information. */
1479 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1480 CORE_ADDR start_pc
, CORE_ADDR end_pc
,
1481 struct riscv_unwind_cache
*cache
)
1483 CORE_ADDR cur_pc
, next_pc
, after_prologue_pc
;
1484 CORE_ADDR end_prologue_addr
= 0;
1486 /* Find an upper limit on the function prologue using the debug
1487 information. If the debug information could not be used to provide
1488 that bound, then use an arbitrary large number as the upper bound. */
1489 after_prologue_pc
= skip_prologue_using_sal (gdbarch
, start_pc
);
1490 if (after_prologue_pc
== 0)
1491 after_prologue_pc
= start_pc
+ 100; /* Arbitrary large number. */
1492 if (after_prologue_pc
< end_pc
)
1493 end_pc
= after_prologue_pc
;
1495 pv_t regs
[RISCV_NUM_INTEGER_REGS
]; /* Number of GPR. */
1496 for (int regno
= 0; regno
< RISCV_NUM_INTEGER_REGS
; regno
++)
1497 regs
[regno
] = pv_register (regno
, 0);
1498 pv_area
stack (RISCV_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
1500 if (riscv_debug_unwinder
)
1503 "Prologue scan for function starting at %s (limit %s)\n",
1504 core_addr_to_string (start_pc
),
1505 core_addr_to_string (end_pc
));
1507 for (next_pc
= cur_pc
= start_pc
; cur_pc
< end_pc
; cur_pc
= next_pc
)
1509 struct riscv_insn insn
;
1511 /* Decode the current instruction, and decide where the next
1512 instruction lives based on the size of this instruction. */
1513 insn
.decode (gdbarch
, cur_pc
);
1514 gdb_assert (insn
.length () > 0);
1515 next_pc
= cur_pc
+ insn
.length ();
1517 /* Look for common stack adjustment insns. */
1518 if ((insn
.opcode () == riscv_insn::ADDI
1519 || insn
.opcode () == riscv_insn::ADDIW
)
1520 && insn
.rd () == RISCV_SP_REGNUM
1521 && insn
.rs1 () == RISCV_SP_REGNUM
)
1523 /* Handle: addi sp, sp, -i
1524 or: addiw sp, sp, -i */
1525 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1526 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1528 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1530 else if ((insn
.opcode () == riscv_insn::SW
1531 || insn
.opcode () == riscv_insn::SD
)
1532 && (insn
.rs1 () == RISCV_SP_REGNUM
1533 || insn
.rs1 () == RISCV_FP_REGNUM
))
1535 /* Handle: sw reg, offset(sp)
1536 or: sd reg, offset(sp)
1537 or: sw reg, offset(s0)
1538 or: sd reg, offset(s0) */
1539 /* Instruction storing a register onto the stack. */
1540 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1541 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1542 stack
.store (pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ()),
1543 (insn
.opcode () == riscv_insn::SW
? 4 : 8),
1546 else if (insn
.opcode () == riscv_insn::ADDI
1547 && insn
.rd () == RISCV_FP_REGNUM
1548 && insn
.rs1 () == RISCV_SP_REGNUM
)
1550 /* Handle: addi s0, sp, size */
1551 /* Instructions setting up the frame pointer. */
1552 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1553 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1555 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1557 else if ((insn
.opcode () == riscv_insn::ADD
1558 || insn
.opcode () == riscv_insn::ADDW
)
1559 && insn
.rd () == RISCV_FP_REGNUM
1560 && insn
.rs1 () == RISCV_SP_REGNUM
1561 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1563 /* Handle: add s0, sp, 0
1564 or: addw s0, sp, 0 */
1565 /* Instructions setting up the frame pointer. */
1566 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1567 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1568 regs
[insn
.rd ()] = pv_add_constant (regs
[insn
.rs1 ()], 0);
1570 else if ((insn
.opcode () == riscv_insn::ADDI
1571 && insn
.rd () == RISCV_ZERO_REGNUM
1572 && insn
.rs1 () == RISCV_ZERO_REGNUM
1573 && insn
.imm_signed () == 0))
1575 /* Handle: add x0, x0, 0 (NOP) */
1577 else if (insn
.opcode () == riscv_insn::AUIPC
)
1579 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1580 regs
[insn
.rd ()] = pv_constant (cur_pc
+ insn
.imm_signed ());
1582 else if (insn
.opcode () == riscv_insn::LUI
)
1584 /* Handle: lui REG, n
1585 Where REG is not gp register. */
1586 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1587 regs
[insn
.rd ()] = pv_constant (insn
.imm_signed ());
1589 else if (insn
.opcode () == riscv_insn::ADDI
)
1591 /* Handle: addi REG1, REG2, IMM */
1592 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1593 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1595 = pv_add_constant (regs
[insn
.rs1 ()], insn
.imm_signed ());
1597 else if (insn
.opcode () == riscv_insn::ADD
)
1599 /* Handle: addi REG1, REG2, IMM */
1600 gdb_assert (insn
.rd () < RISCV_NUM_INTEGER_REGS
);
1601 gdb_assert (insn
.rs1 () < RISCV_NUM_INTEGER_REGS
);
1602 gdb_assert (insn
.rs2 () < RISCV_NUM_INTEGER_REGS
);
1603 regs
[insn
.rd ()] = pv_add (regs
[insn
.rs1 ()], regs
[insn
.rs2 ()]);
1607 end_prologue_addr
= cur_pc
;
1612 if (end_prologue_addr
== 0)
1613 end_prologue_addr
= cur_pc
;
1615 if (riscv_debug_unwinder
)
1616 fprintf_unfiltered (gdb_stdlog
, "End of prologue at %s\n",
1617 core_addr_to_string (end_prologue_addr
));
1621 /* Figure out if it is a frame pointer or just a stack pointer. Also
1622 the offset held in the pv_t is from the original register value to
1623 the current value, which for a grows down stack means a negative
1624 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1625 from the current value to the original value. */
1626 if (pv_is_register (regs
[RISCV_FP_REGNUM
], RISCV_SP_REGNUM
))
1628 cache
->frame_base_reg
= RISCV_FP_REGNUM
;
1629 cache
->frame_base_offset
= -regs
[RISCV_FP_REGNUM
].k
;
1633 cache
->frame_base_reg
= RISCV_SP_REGNUM
;
1634 cache
->frame_base_offset
= -regs
[RISCV_SP_REGNUM
].k
;
1637 /* Assign offset from old SP to all saved registers. As we don't
1638 have the previous value for the frame base register at this
1639 point, we store the offset as the address in the trad_frame, and
1640 then convert this to an actual address later. */
1641 for (int i
= 0; i
<= RISCV_NUM_INTEGER_REGS
; i
++)
1644 if (stack
.find_reg (gdbarch
, i
, &offset
))
1646 if (riscv_debug_unwinder
)
1648 /* Display OFFSET as a signed value, the offsets are from
1649 the frame base address to the registers location on
1650 the stack, with a descending stack this means the
1651 offsets are always negative. */
1652 fprintf_unfiltered (gdb_stdlog
,
1653 "Register $%s at stack offset %s\n",
1654 gdbarch_register_name (gdbarch
, i
),
1655 plongest ((LONGEST
) offset
));
1657 trad_frame_set_addr (cache
->regs
, i
, offset
);
1662 return end_prologue_addr
;
1665 /* Implement the riscv_skip_prologue gdbarch method. */
1668 riscv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1670 CORE_ADDR func_addr
;
1672 /* See if we can determine the end of the prologue via the symbol
1673 table. If so, then return either PC, or the PC after the
1674 prologue, whichever is greater. */
1675 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1677 CORE_ADDR post_prologue_pc
1678 = skip_prologue_using_sal (gdbarch
, func_addr
);
1680 if (post_prologue_pc
!= 0)
1681 return std::max (pc
, post_prologue_pc
);
1684 /* Can't determine prologue from the symbol table, need to examine
1685 instructions. Pass -1 for the end address to indicate the prologue
1686 scanner can scan as far as it needs to find the end of the prologue. */
1687 return riscv_scan_prologue (gdbarch
, pc
, ((CORE_ADDR
) -1), NULL
);
1690 /* Implement the gdbarch push dummy code callback. */
1693 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1694 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1695 struct type
*value_type
, CORE_ADDR
*real_pc
,
1696 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1698 /* A nop instruction is 'add x0, x0, 0'. */
1699 static const gdb_byte nop_insn
[] = { 0x13, 0x00, 0x00, 0x00 };
1701 /* Allocate space for a breakpoint, and keep the stack correctly
1702 aligned. The space allocated here must be at least big enough to
1703 accommodate the NOP_INSN defined above. */
1708 /* When we insert a breakpoint we select whether to use a compressed
1709 breakpoint or not based on the existing contents of the memory.
1711 If the breakpoint is being placed onto the stack as part of setting up
1712 for an inferior call from GDB, then the existing stack contents may
1713 randomly appear to be a compressed instruction, causing GDB to insert
1714 a compressed breakpoint. If this happens on a target that does not
1715 support compressed instructions then this could cause problems.
1717 To prevent this issue we write an uncompressed nop onto the stack at
1718 the location where the breakpoint will be inserted. In this way we
1719 ensure that we always use an uncompressed breakpoint, which should
1720 work on all targets.
1722 We call TARGET_WRITE_MEMORY here so that if the write fails we don't
1723 throw an exception. Instead we ignore the error and move on. The
1724 assumption is that either GDB will error later when actually trying to
1725 insert a software breakpoint, or GDB will use hardware breakpoints and
1726 there will be no need to write to memory later. */
1727 int status
= target_write_memory (*bp_addr
, nop_insn
, sizeof (nop_insn
));
1729 if (riscv_debug_breakpoints
|| riscv_debug_infcall
)
1730 fprintf_unfiltered (gdb_stdlog
,
1731 "Writing %s-byte nop instruction to %s: %s\n",
1732 plongest (sizeof (nop_insn
)),
1733 paddress (gdbarch
, *bp_addr
),
1734 (status
== 0 ? "success" : "failed"));
1739 /* Implement the gdbarch type alignment method, overrides the generic
1740 alignment algorithm for anything that is RISC-V specific. */
1743 riscv_type_align (gdbarch
*gdbarch
, type
*type
)
1745 type
= check_typedef (type
);
1746 if (type
->code () == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
))
1747 return std::min (TYPE_LENGTH (type
), (ULONGEST
) BIGGEST_ALIGNMENT
);
1749 /* Anything else will be aligned by the generic code. */
1753 /* Holds information about a single argument either being passed to an
1754 inferior function, or returned from an inferior function. This includes
1755 information about the size, type, etc of the argument, and also
1756 information about how the argument will be passed (or returned). */
1758 struct riscv_arg_info
1760 /* Contents of the argument. */
1761 const gdb_byte
*contents
;
1763 /* Length of argument. */
1766 /* Alignment required for an argument of this type. */
1769 /* The type for this argument. */
1772 /* Each argument can have either 1 or 2 locations assigned to it. Each
1773 location describes where part of the argument will be placed. The
1774 second location is valid based on the LOC_TYPE and C_LENGTH fields
1775 of the first location (which is always valid). */
1778 /* What type of location this is. */
1781 /* Argument passed in a register. */
1784 /* Argument passed as an on stack argument. */
1787 /* Argument passed by reference. The second location is always
1788 valid for a BY_REF argument, and describes where the address
1789 of the BY_REF argument should be placed. */
1793 /* Information that depends on the location type. */
1796 /* Which register number to use. */
1799 /* The offset into the stack region. */
1803 /* The length of contents covered by this location. If this is less
1804 than the total length of the argument, then the second location
1805 will be valid, and will describe where the rest of the argument
1809 /* The offset within CONTENTS for this part of the argument. This can
1810 be non-zero even for the first part (the first field of a struct can
1811 have a non-zero offset due to padding). For the second part of the
1812 argument, this might be the C_LENGTH value of the first part,
1813 however, if we are passing a structure in two registers, and there's
1814 is padding between the first and second field, then this offset
1815 might be greater than the length of the first argument part. When
1816 the second argument location is not holding part of the argument
1817 value, but is instead holding the address of a reference argument,
1818 then this offset will be set to 0. */
1822 /* TRUE if this is an unnamed argument. */
1826 /* Information about a set of registers being used for passing arguments as
1827 part of a function call. The register set must be numerically
1828 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1829 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1831 struct riscv_arg_reg
1833 riscv_arg_reg (int first
, int last
)
1834 : next_regnum (first
),
1840 /* The GDB register number to use in this set. */
1843 /* The last GDB register number to use in this set. */
1847 /* Arguments can be passed as on stack arguments, or by reference. The
1848 on stack arguments must be in a continuous region starting from $sp,
1849 while the by reference arguments can be anywhere, but we'll put them
1850 on the stack after (at higher address) the on stack arguments.
1852 This might not be the right approach to take. The ABI is clear that
1853 an argument passed by reference can be modified by the callee, which
1854 us placing the argument (temporarily) onto the stack will not achieve
1855 (changes will be lost). There's also the possibility that very large
1856 arguments could overflow the stack.
1858 This struct is used to track offset into these two areas for where
1859 arguments are to be placed. */
1860 struct riscv_memory_offsets
1862 riscv_memory_offsets ()
1869 /* Offset into on stack argument area. */
1872 /* Offset into the pass by reference area. */
1876 /* Holds information about where arguments to a call will be placed. This
1877 is updated as arguments are added onto the call, and can be used to
1878 figure out where the next argument should be placed. */
1880 struct riscv_call_info
1882 riscv_call_info (struct gdbarch
*gdbarch
)
1883 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1884 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1886 xlen
= riscv_abi_xlen (gdbarch
);
1887 flen
= riscv_abi_flen (gdbarch
);
1889 /* Disable use of floating point registers if needed. */
1890 if (!riscv_has_fp_abi (gdbarch
))
1891 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1894 /* Track the memory areas used for holding in-memory arguments to a
1896 struct riscv_memory_offsets memory
;
1898 /* Holds information about the next integer register to use for passing
1900 struct riscv_arg_reg int_regs
;
1902 /* Holds information about the next floating point register to use for
1903 passing an argument. */
1904 struct riscv_arg_reg float_regs
;
1906 /* The XLEN and FLEN are copied in to this structure for convenience, and
1907 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1912 /* Return the number of registers available for use as parameters in the
1913 register set REG. Returned value can be 0 or more. */
1916 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1918 if (reg
->next_regnum
> reg
->last_regnum
)
1921 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1924 /* If there is at least one register available in the register set REG then
1925 the next register from REG is assigned to LOC and the length field of
1926 LOC is updated to LENGTH. The register set REG is updated to indicate
1927 that the assigned register is no longer available and the function
1930 If there are no registers available in REG then the function returns
1931 false, and LOC and REG are unchanged. */
1934 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1935 struct riscv_arg_reg
*reg
,
1936 int length
, int offset
)
1938 if (reg
->next_regnum
<= reg
->last_regnum
)
1940 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1941 loc
->loc_data
.regno
= reg
->next_regnum
;
1943 loc
->c_length
= length
;
1944 loc
->c_offset
= offset
;
1951 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1952 record that an area of stack has been used to hold the parameter
1955 The length field of LOC is updated to LENGTH, the length of the
1956 parameter being stored, and ALIGN is the alignment required by the
1957 parameter, which will affect how memory is allocated out of MEMORY. */
1960 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1961 struct riscv_memory_offsets
*memory
,
1962 int length
, int align
)
1964 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1966 = align_up (memory
->arg_offset
, align
);
1967 loc
->loc_data
.offset
= memory
->arg_offset
;
1968 memory
->arg_offset
+= length
;
1969 loc
->c_length
= length
;
1971 /* Offset is always 0, either we're the first location part, in which
1972 case we're reading content from the start of the argument, or we're
1973 passing the address of a reference argument, so 0. */
1977 /* Update AINFO, which describes an argument that should be passed or
1978 returned using the integer ABI. The argloc fields within AINFO are
1979 updated to describe the location in which the argument will be passed to
1980 a function, or returned from a function.
1982 The CINFO structure contains the ongoing call information, the holds
1983 information such as which argument registers are remaining to be
1984 assigned to parameter, and how much memory has been used by parameters
1987 By examining the state of CINFO a suitable location can be selected,
1988 and assigned to AINFO. */
1991 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1992 struct riscv_call_info
*cinfo
)
1994 if (ainfo
->length
> (2 * cinfo
->xlen
))
1996 /* Argument is going to be passed by reference. */
1997 ainfo
->argloc
[0].loc_type
1998 = riscv_arg_info::location::by_ref
;
1999 cinfo
->memory
.ref_offset
2000 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
2001 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
2002 cinfo
->memory
.ref_offset
+= ainfo
->length
;
2003 ainfo
->argloc
[0].c_length
= ainfo
->length
;
2005 /* The second location for this argument is given over to holding the
2006 address of the by-reference data. Pass 0 for the offset as this
2007 is not part of the actual argument value. */
2008 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2011 riscv_assign_stack_location (&ainfo
->argloc
[1],
2012 &cinfo
->memory
, cinfo
->xlen
,
2017 int len
= std::min (ainfo
->length
, cinfo
->xlen
);
2018 int align
= std::max (ainfo
->align
, cinfo
->xlen
);
2020 /* Unnamed arguments in registers that require 2*XLEN alignment are
2021 passed in an aligned register pair. */
2022 if (ainfo
->is_unnamed
&& (align
== cinfo
->xlen
* 2)
2023 && cinfo
->int_regs
.next_regnum
& 1)
2024 cinfo
->int_regs
.next_regnum
++;
2026 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2027 &cinfo
->int_regs
, len
, 0))
2028 riscv_assign_stack_location (&ainfo
->argloc
[0],
2029 &cinfo
->memory
, len
, align
);
2031 if (len
< ainfo
->length
)
2033 len
= ainfo
->length
- len
;
2034 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2035 &cinfo
->int_regs
, len
,
2037 riscv_assign_stack_location (&ainfo
->argloc
[1],
2038 &cinfo
->memory
, len
, cinfo
->xlen
);
2043 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2044 is being passed with the floating point ABI. */
2047 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
2048 struct riscv_call_info
*cinfo
)
2050 if (ainfo
->length
> cinfo
->flen
|| ainfo
->is_unnamed
)
2051 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2054 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2057 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2061 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2062 is a complex floating point argument, and is therefore handled
2063 differently to other argument types. */
2066 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
2067 struct riscv_call_info
*cinfo
)
2069 if (ainfo
->length
<= (2 * cinfo
->flen
)
2070 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2071 && !ainfo
->is_unnamed
)
2074 int len
= ainfo
->length
/ 2;
2076 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2077 &cinfo
->float_regs
, len
, 0);
2078 gdb_assert (result
);
2080 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2081 &cinfo
->float_regs
, len
, len
);
2082 gdb_assert (result
);
2085 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
2088 /* A structure used for holding information about a structure type within
2089 the inferior program. The RiscV ABI has special rules for handling some
2090 structures with a single field or with two fields. The counting of
2091 fields here is done after flattening out all nested structures. */
2093 class riscv_struct_info
2096 riscv_struct_info ()
2097 : m_number_of_fields (0),
2098 m_types
{ nullptr, nullptr },
2104 /* Analyse TYPE descending into nested structures, count the number of
2105 scalar fields and record the types of the first two fields found. */
2106 void analyse (struct type
*type
)
2108 analyse_inner (type
, 0);
2111 /* The number of scalar fields found in the analysed type. This is
2112 currently only accurate if the value returned is 0, 1, or 2 as the
2113 analysis stops counting when the number of fields is 3. This is
2114 because the RiscV ABI only has special cases for 1 or 2 fields,
2115 anything else we just don't care about. */
2116 int number_of_fields () const
2117 { return m_number_of_fields
; }
2119 /* Return the type for scalar field INDEX within the analysed type. Will
2120 return nullptr if there is no field at that index. Only INDEX values
2121 0 and 1 can be requested as the RiscV ABI only has special cases for
2122 structures with 1 or 2 fields. */
2123 struct type
*field_type (int index
) const
2125 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
2126 return m_types
[index
];
2129 /* Return the offset of scalar field INDEX within the analysed type. Will
2130 return 0 if there is no field at that index. Only INDEX values 0 and
2131 1 can be requested as the RiscV ABI only has special cases for
2132 structures with 1 or 2 fields. */
2133 int field_offset (int index
) const
2135 gdb_assert (index
< (sizeof (m_offsets
) / sizeof (m_offsets
[0])));
2136 return m_offsets
[index
];
2140 /* The number of scalar fields found within the structure after recursing
2141 into nested structures. */
2142 int m_number_of_fields
;
2144 /* The types of the first two scalar fields found within the structure
2145 after recursing into nested structures. */
2146 struct type
*m_types
[2];
2148 /* The offsets of the first two scalar fields found within the structure
2149 after recursing into nested structures. */
2152 /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
2153 offset from the start of the top level structure being analysed. */
2154 void analyse_inner (struct type
*type
, int offset
);
2157 /* See description in class declaration. */
2160 riscv_struct_info::analyse_inner (struct type
*type
, int offset
)
2162 unsigned int count
= type
->num_fields ();
2165 for (i
= 0; i
< count
; ++i
)
2167 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
2170 struct type
*field_type
= type
->field (i
).type ();
2171 field_type
= check_typedef (field_type
);
2173 = offset
+ TYPE_FIELD_BITPOS (type
, i
) / TARGET_CHAR_BIT
;
2175 switch (field_type
->code ())
2177 case TYPE_CODE_STRUCT
:
2178 analyse_inner (field_type
, field_offset
);
2182 /* RiscV only flattens out structures. Anything else does not
2183 need to be flattened, we just record the type, and when we
2184 look at the analysis results we'll realise this is not a
2185 structure we can special case, and pass the structure in
2187 if (m_number_of_fields
< 2)
2189 m_types
[m_number_of_fields
] = field_type
;
2190 m_offsets
[m_number_of_fields
] = field_offset
;
2192 m_number_of_fields
++;
2196 /* RiscV only has special handling for structures with 1 or 2 scalar
2197 fields, any more than that and the structure is just passed in
2198 memory. We can safely drop out early when we find 3 or more
2201 if (m_number_of_fields
> 2)
2206 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2207 is a structure. Small structures on RiscV have some special case
2208 handling in order that the structure might be passed in register.
2209 Larger structures are passed in memory. After assigning location
2210 information to AINFO, CINFO will have been updated. */
2213 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
2214 struct riscv_call_info
*cinfo
)
2216 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
2218 struct riscv_struct_info sinfo
;
2220 sinfo
.analyse (ainfo
->type
);
2221 if (sinfo
.number_of_fields () == 1
2222 && sinfo
.field_type(0)->code () == TYPE_CODE_COMPLEX
)
2224 /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
2225 except we use the type of the complex field instead of the
2226 type from AINFO, and the first location might be at a non-zero
2228 if (TYPE_LENGTH (sinfo
.field_type (0)) <= (2 * cinfo
->flen
)
2229 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2
2230 && !ainfo
->is_unnamed
)
2233 int len
= TYPE_LENGTH (sinfo
.field_type (0)) / 2;
2234 int offset
= sinfo
.field_offset (0);
2236 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
2237 &cinfo
->float_regs
, len
,
2239 gdb_assert (result
);
2241 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
2242 &cinfo
->float_regs
, len
,
2244 gdb_assert (result
);
2247 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2251 if (sinfo
.number_of_fields () == 1
2252 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
)
2254 /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
2255 except we use the type of the first scalar field instead of
2256 the type from AINFO. Also the location might be at a non-zero
2258 if (TYPE_LENGTH (sinfo
.field_type (0)) > cinfo
->flen
2259 || ainfo
->is_unnamed
)
2260 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2263 int offset
= sinfo
.field_offset (0);
2264 int len
= TYPE_LENGTH (sinfo
.field_type (0));
2266 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2269 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2274 if (sinfo
.number_of_fields () == 2
2275 && sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2276 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2277 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2278 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
2279 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
2281 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2282 int offset
= sinfo
.field_offset (0);
2283 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2284 &cinfo
->float_regs
, len0
, offset
))
2285 error (_("failed during argument setup"));
2287 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2288 offset
= sinfo
.field_offset (1);
2289 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
2290 - TYPE_LENGTH (sinfo
.field_type (0))));
2292 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2295 error (_("failed during argument setup"));
2299 if (sinfo
.number_of_fields () == 2
2300 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2301 && (sinfo
.field_type(0)->code () == TYPE_CODE_FLT
2302 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
2303 && is_integral_type (sinfo
.field_type (1))
2304 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
2306 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2307 int offset
= sinfo
.field_offset (0);
2308 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2309 &cinfo
->float_regs
, len0
, offset
))
2310 error (_("failed during argument setup"));
2312 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2313 offset
= sinfo
.field_offset (1);
2314 gdb_assert (len1
<= cinfo
->xlen
);
2315 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2316 &cinfo
->int_regs
, len1
, offset
))
2317 error (_("failed during argument setup"));
2321 if (sinfo
.number_of_fields () == 2
2322 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
2323 && (is_integral_type (sinfo
.field_type (0))
2324 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
2325 && sinfo
.field_type(1)->code () == TYPE_CODE_FLT
2326 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
2328 int len0
= TYPE_LENGTH (sinfo
.field_type (0));
2329 int len1
= TYPE_LENGTH (sinfo
.field_type (1));
2331 gdb_assert (len0
<= cinfo
->xlen
);
2332 gdb_assert (len1
<= cinfo
->flen
);
2334 int offset
= sinfo
.field_offset (0);
2335 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
2336 &cinfo
->int_regs
, len0
, offset
))
2337 error (_("failed during argument setup"));
2339 offset
= sinfo
.field_offset (1);
2340 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
2343 error (_("failed during argument setup"));
2349 /* Non of the structure flattening cases apply, so we just pass using
2351 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2354 /* Assign a location to call (or return) argument AINFO, the location is
2355 selected from CINFO which holds information about what call argument
2356 locations are available for use next. The TYPE is the type of the
2357 argument being passed, this information is recorded into AINFO (along
2358 with some additional information derived from the type). IS_UNNAMED
2359 is true if this is an unnamed (stdarg) argument, this info is also
2360 recorded into AINFO.
2362 After assigning a location to AINFO, CINFO will have been updated. */
2365 riscv_arg_location (struct gdbarch
*gdbarch
,
2366 struct riscv_arg_info
*ainfo
,
2367 struct riscv_call_info
*cinfo
,
2368 struct type
*type
, bool is_unnamed
)
2371 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
2372 ainfo
->align
= type_align (ainfo
->type
);
2373 ainfo
->is_unnamed
= is_unnamed
;
2374 ainfo
->contents
= nullptr;
2375 ainfo
->argloc
[0].c_length
= 0;
2376 ainfo
->argloc
[1].c_length
= 0;
2378 switch (ainfo
->type
->code ())
2381 case TYPE_CODE_BOOL
:
2382 case TYPE_CODE_CHAR
:
2383 case TYPE_CODE_RANGE
:
2384 case TYPE_CODE_ENUM
:
2386 if (ainfo
->length
<= cinfo
->xlen
)
2388 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
2389 ainfo
->length
= cinfo
->xlen
;
2391 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
2393 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
2394 ainfo
->length
= 2 * cinfo
->xlen
;
2397 /* Recalculate the alignment requirement. */
2398 ainfo
->align
= type_align (ainfo
->type
);
2399 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2403 riscv_call_arg_scalar_float (ainfo
, cinfo
);
2406 case TYPE_CODE_COMPLEX
:
2407 riscv_call_arg_complex_float (ainfo
, cinfo
);
2410 case TYPE_CODE_STRUCT
:
2411 riscv_call_arg_struct (ainfo
, cinfo
);
2415 riscv_call_arg_scalar_int (ainfo
, cinfo
);
2420 /* Used for printing debug information about the call argument location in
2421 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2422 addresses for the location of pass-by-reference and
2423 arguments-on-the-stack memory areas. */
2426 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
2427 struct riscv_arg_info
*info
,
2428 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
2430 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
2431 TYPE_SAFE_NAME (info
->type
), info
->length
, info
->align
);
2432 switch (info
->argloc
[0].loc_type
)
2434 case riscv_arg_info::location::in_reg
:
2436 (stream
, ", register %s",
2437 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
2438 if (info
->argloc
[0].c_length
< info
->length
)
2440 switch (info
->argloc
[1].loc_type
)
2442 case riscv_arg_info::location::in_reg
:
2444 (stream
, ", register %s",
2445 gdbarch_register_name (gdbarch
,
2446 info
->argloc
[1].loc_data
.regno
));
2449 case riscv_arg_info::location::on_stack
:
2450 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2451 info
->argloc
[1].loc_data
.offset
);
2454 case riscv_arg_info::location::by_ref
:
2456 /* The second location should never be a reference, any
2457 argument being passed by reference just places its address
2458 in the first location and is done. */
2459 error (_("invalid argument location"));
2463 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
2464 fprintf_unfiltered (stream
, " (offset 0x%x)",
2465 info
->argloc
[1].c_offset
);
2469 case riscv_arg_info::location::on_stack
:
2470 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
2471 info
->argloc
[0].loc_data
.offset
);
2474 case riscv_arg_info::location::by_ref
:
2476 (stream
, ", by reference, data at offset 0x%x (%s)",
2477 info
->argloc
[0].loc_data
.offset
,
2478 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
2479 if (info
->argloc
[1].loc_type
2480 == riscv_arg_info::location::in_reg
)
2482 (stream
, ", address in register %s",
2483 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2486 gdb_assert (info
->argloc
[1].loc_type
2487 == riscv_arg_info::location::on_stack
);
2489 (stream
, ", address on stack at offset 0x%x (%s)",
2490 info
->argloc
[1].loc_data
.offset
,
2491 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2496 gdb_assert_not_reached (_("unknown argument location type"));
2500 /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA
2501 into a buffer that is at least as big as the register REGNUM, padding
2502 out the DATA with either 0x00, or 0xff. For floating point registers
2503 0xff is used, for everyone else 0x00 is used. */
2506 riscv_regcache_cooked_write (int regnum
, const gdb_byte
*data
, int len
,
2507 struct regcache
*regcache
, int flen
)
2509 gdb_byte tmp
[sizeof (ULONGEST
)];
2511 /* FP values in FP registers must be NaN-boxed. */
2512 if (riscv_is_fp_regno_p (regnum
) && len
< flen
)
2513 memset (tmp
, -1, sizeof (tmp
));
2515 memset (tmp
, 0, sizeof (tmp
));
2516 memcpy (tmp
, data
, len
);
2517 regcache
->cooked_write (regnum
, tmp
);
2520 /* Implement the push dummy call gdbarch callback. */
2523 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2524 struct value
*function
,
2525 struct regcache
*regcache
,
2528 struct value
**args
,
2530 function_call_return_method return_method
,
2531 CORE_ADDR struct_addr
)
2534 CORE_ADDR sp_args
, sp_refs
;
2535 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2537 struct riscv_arg_info
*arg_info
=
2538 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2540 struct riscv_call_info
call_info (gdbarch
);
2544 struct type
*ftype
= check_typedef (value_type (function
));
2546 if (ftype
->code () == TYPE_CODE_PTR
)
2547 ftype
= check_typedef (TYPE_TARGET_TYPE (ftype
));
2549 /* We'll use register $a0 if we're returning a struct. */
2550 if (return_method
== return_method_struct
)
2551 ++call_info
.int_regs
.next_regnum
;
2553 for (i
= 0; i
< nargs
; ++i
)
2555 struct value
*arg_value
;
2556 struct type
*arg_type
;
2557 struct riscv_arg_info
*info
= &arg_info
[i
];
2559 arg_value
= args
[i
];
2560 arg_type
= check_typedef (value_type (arg_value
));
2562 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
,
2563 TYPE_VARARGS (ftype
) && i
>= ftype
->num_fields ());
2565 if (info
->type
!= arg_type
)
2566 arg_value
= value_cast (info
->type
, arg_value
);
2567 info
->contents
= value_contents (arg_value
);
2570 /* Adjust the stack pointer and align it. */
2571 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2572 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2574 if (riscv_debug_infcall
> 0)
2576 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2577 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2578 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2579 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2580 call_info
.xlen
, call_info
.flen
);
2581 if (return_method
== return_method_struct
)
2582 fprintf_unfiltered (gdb_stdlog
,
2583 "[*] struct return pointer in register $A0\n");
2584 for (i
= 0; i
< nargs
; ++i
)
2586 struct riscv_arg_info
*info
= &arg_info
[i
];
2588 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2589 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2590 fprintf_unfiltered (gdb_stdlog
, "\n");
2592 if (call_info
.memory
.arg_offset
> 0
2593 || call_info
.memory
.ref_offset
> 0)
2595 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2596 core_addr_to_string (osp
));
2597 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2598 call_info
.memory
.arg_offset
);
2599 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2600 call_info
.memory
.ref_offset
);
2601 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2602 core_addr_to_string_nz (osp
- sp
));
2606 /* Now load the argument into registers, or onto the stack. */
2608 if (return_method
== return_method_struct
)
2610 gdb_byte buf
[sizeof (LONGEST
)];
2612 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2613 regcache
->cooked_write (RISCV_A0_REGNUM
, buf
);
2616 for (i
= 0; i
< nargs
; ++i
)
2619 int second_arg_length
= 0;
2620 const gdb_byte
*second_arg_data
;
2621 struct riscv_arg_info
*info
= &arg_info
[i
];
2623 gdb_assert (info
->length
> 0);
2625 switch (info
->argloc
[0].loc_type
)
2627 case riscv_arg_info::location::in_reg
:
2629 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2631 riscv_regcache_cooked_write (info
->argloc
[0].loc_data
.regno
,
2633 + info
->argloc
[0].c_offset
),
2634 info
->argloc
[0].c_length
,
2635 regcache
, call_info
.flen
);
2637 (((info
->argloc
[0].c_length
+ info
->argloc
[0].c_offset
) < info
->length
)
2638 ? info
->argloc
[1].c_length
: 0);
2639 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2643 case riscv_arg_info::location::on_stack
:
2644 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2645 write_memory (dst
, info
->contents
, info
->length
);
2646 second_arg_length
= 0;
2649 case riscv_arg_info::location::by_ref
:
2650 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2651 write_memory (dst
, info
->contents
, info
->length
);
2653 second_arg_length
= call_info
.xlen
;
2654 second_arg_data
= (gdb_byte
*) &dst
;
2658 gdb_assert_not_reached (_("unknown argument location type"));
2661 if (second_arg_length
> 0)
2663 switch (info
->argloc
[1].loc_type
)
2665 case riscv_arg_info::location::in_reg
:
2667 gdb_assert ((riscv_is_fp_regno_p (info
->argloc
[1].loc_data
.regno
)
2668 && second_arg_length
<= call_info
.flen
)
2669 || second_arg_length
<= call_info
.xlen
);
2670 riscv_regcache_cooked_write (info
->argloc
[1].loc_data
.regno
,
2673 regcache
, call_info
.flen
);
2677 case riscv_arg_info::location::on_stack
:
2681 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2682 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2686 case riscv_arg_info::location::by_ref
:
2688 /* The second location should never be a reference, any
2689 argument being passed by reference just places its address
2690 in the first location and is done. */
2691 error (_("invalid argument location"));
2697 /* Set the dummy return value to bp_addr.
2698 A dummy breakpoint will be setup to execute the call. */
2700 if (riscv_debug_infcall
> 0)
2701 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2702 core_addr_to_string (bp_addr
));
2703 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2705 /* Finally, update the stack pointer. */
2707 if (riscv_debug_infcall
> 0)
2708 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2709 core_addr_to_string (sp
));
2710 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2715 /* Implement the return_value gdbarch method. */
2717 static enum return_value_convention
2718 riscv_return_value (struct gdbarch
*gdbarch
,
2719 struct value
*function
,
2721 struct regcache
*regcache
,
2723 const gdb_byte
*writebuf
)
2725 struct riscv_call_info
call_info (gdbarch
);
2726 struct riscv_arg_info info
;
2727 struct type
*arg_type
;
2729 arg_type
= check_typedef (type
);
2730 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
, false);
2732 if (riscv_debug_infcall
> 0)
2734 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2735 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2736 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2737 fprintf_unfiltered (gdb_stdlog
, "\n");
2740 if (readbuf
!= nullptr || writebuf
!= nullptr)
2742 unsigned int arg_len
;
2743 struct value
*abi_val
;
2744 gdb_byte
*old_readbuf
= nullptr;
2747 /* We only do one thing at a time. */
2748 gdb_assert (readbuf
== nullptr || writebuf
== nullptr);
2750 /* In some cases the argument is not returned as the declared type,
2751 and we need to cast to or from the ABI type in order to
2752 correctly access the argument. When writing to the machine we
2753 do the cast here, when reading from the machine the cast occurs
2754 later, after extracting the value. As the ABI type can be
2755 larger than the declared type, then the read or write buffers
2756 passed in might be too small. Here we ensure that we are using
2757 buffers of sufficient size. */
2758 if (writebuf
!= nullptr)
2760 struct value
*arg_val
= value_from_contents (arg_type
, writebuf
);
2761 abi_val
= value_cast (info
.type
, arg_val
);
2762 writebuf
= value_contents_raw (abi_val
);
2766 abi_val
= allocate_value (info
.type
);
2767 old_readbuf
= readbuf
;
2768 readbuf
= value_contents_raw (abi_val
);
2770 arg_len
= TYPE_LENGTH (info
.type
);
2772 switch (info
.argloc
[0].loc_type
)
2774 /* Return value in register(s). */
2775 case riscv_arg_info::location::in_reg
:
2777 regnum
= info
.argloc
[0].loc_data
.regno
;
2778 gdb_assert (info
.argloc
[0].c_length
<= arg_len
);
2779 gdb_assert (info
.argloc
[0].c_length
2780 <= register_size (gdbarch
, regnum
));
2784 gdb_byte
*ptr
= readbuf
+ info
.argloc
[0].c_offset
;
2785 regcache
->cooked_read_part (regnum
, 0,
2786 info
.argloc
[0].c_length
,
2792 const gdb_byte
*ptr
= writebuf
+ info
.argloc
[0].c_offset
;
2793 riscv_regcache_cooked_write (regnum
, ptr
,
2794 info
.argloc
[0].c_length
,
2795 regcache
, call_info
.flen
);
2798 /* A return value in register can have a second part in a
2800 if (info
.argloc
[1].c_length
> 0)
2802 switch (info
.argloc
[1].loc_type
)
2804 case riscv_arg_info::location::in_reg
:
2805 regnum
= info
.argloc
[1].loc_data
.regno
;
2807 gdb_assert ((info
.argloc
[0].c_length
2808 + info
.argloc
[1].c_length
) <= arg_len
);
2809 gdb_assert (info
.argloc
[1].c_length
2810 <= register_size (gdbarch
, regnum
));
2814 readbuf
+= info
.argloc
[1].c_offset
;
2815 regcache
->cooked_read_part (regnum
, 0,
2816 info
.argloc
[1].c_length
,
2823 = writebuf
+ info
.argloc
[1].c_offset
;
2824 riscv_regcache_cooked_write
2825 (regnum
, ptr
, info
.argloc
[1].c_length
,
2826 regcache
, call_info
.flen
);
2830 case riscv_arg_info::location::by_ref
:
2831 case riscv_arg_info::location::on_stack
:
2833 error (_("invalid argument location"));
2840 /* Return value by reference will have its address in A0. */
2841 case riscv_arg_info::location::by_ref
:
2845 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2847 if (readbuf
!= nullptr)
2848 read_memory (addr
, readbuf
, info
.length
);
2849 if (writebuf
!= nullptr)
2850 write_memory (addr
, writebuf
, info
.length
);
2854 case riscv_arg_info::location::on_stack
:
2856 error (_("invalid argument location"));
2860 /* This completes the cast from abi type back to the declared type
2861 in the case that we are reading from the machine. See the
2862 comment at the head of this block for more details. */
2863 if (readbuf
!= nullptr)
2865 struct value
*arg_val
= value_cast (arg_type
, abi_val
);
2866 memcpy (old_readbuf
, value_contents_raw (arg_val
),
2867 TYPE_LENGTH (arg_type
));
2871 switch (info
.argloc
[0].loc_type
)
2873 case riscv_arg_info::location::in_reg
:
2874 return RETURN_VALUE_REGISTER_CONVENTION
;
2875 case riscv_arg_info::location::by_ref
:
2876 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2877 case riscv_arg_info::location::on_stack
:
2879 error (_("invalid argument location"));
2883 /* Implement the frame_align gdbarch method. */
2886 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2888 return align_down (addr
, 16);
2891 /* Generate, or return the cached frame cache for the RiscV frame
2894 static struct riscv_unwind_cache
*
2895 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2897 CORE_ADDR pc
, start_addr
;
2898 struct riscv_unwind_cache
*cache
;
2899 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2902 if ((*this_cache
) != NULL
)
2903 return (struct riscv_unwind_cache
*) *this_cache
;
2905 cache
= FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache
);
2906 cache
->regs
= trad_frame_alloc_saved_regs (this_frame
);
2907 (*this_cache
) = cache
;
2909 /* Scan the prologue, filling in the cache. */
2910 start_addr
= get_frame_func (this_frame
);
2911 pc
= get_frame_pc (this_frame
);
2912 riscv_scan_prologue (gdbarch
, start_addr
, pc
, cache
);
2914 /* We can now calculate the frame base address. */
2916 = (get_frame_register_signed (this_frame
, cache
->frame_base_reg
)
2917 + cache
->frame_base_offset
);
2918 if (riscv_debug_unwinder
)
2919 fprintf_unfiltered (gdb_stdlog
, "Frame base is %s ($%s + 0x%x)\n",
2920 core_addr_to_string (cache
->frame_base
),
2921 gdbarch_register_name (gdbarch
,
2922 cache
->frame_base_reg
),
2923 cache
->frame_base_offset
);
2925 /* The prologue scanner sets the address of registers stored to the stack
2926 as the offset of that register from the frame base. The prologue
2927 scanner doesn't know the actual frame base value, and so is unable to
2928 compute the exact address. We do now know the frame base value, so
2929 update the address of registers stored to the stack. */
2930 numregs
= gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
2931 for (regno
= 0; regno
< numregs
; ++regno
)
2933 if (trad_frame_addr_p (cache
->regs
, regno
))
2934 cache
->regs
[regno
].addr
+= cache
->frame_base
;
2937 /* The previous $pc can be found wherever the $ra value can be found.
2938 The previous $ra value is gone, this would have been stored be the
2939 previous frame if required. */
2940 cache
->regs
[gdbarch_pc_regnum (gdbarch
)] = cache
->regs
[RISCV_RA_REGNUM
];
2941 trad_frame_set_unknown (cache
->regs
, RISCV_RA_REGNUM
);
2943 /* Build the frame id. */
2944 cache
->this_id
= frame_id_build (cache
->frame_base
, start_addr
);
2946 /* The previous $sp value is the frame base value. */
2947 trad_frame_set_value (cache
->regs
, gdbarch_sp_regnum (gdbarch
),
2953 /* Implement the this_id callback for RiscV frame unwinder. */
2956 riscv_frame_this_id (struct frame_info
*this_frame
,
2957 void **prologue_cache
,
2958 struct frame_id
*this_id
)
2960 struct riscv_unwind_cache
*cache
;
2964 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2965 *this_id
= cache
->this_id
;
2967 catch (const gdb_exception_error
&ex
)
2969 /* Ignore errors, this leaves the frame id as the predefined outer
2970 frame id which terminates the backtrace at this point. */
2974 /* Implement the prev_register callback for RiscV frame unwinder. */
2976 static struct value
*
2977 riscv_frame_prev_register (struct frame_info
*this_frame
,
2978 void **prologue_cache
,
2981 struct riscv_unwind_cache
*cache
;
2983 cache
= riscv_frame_cache (this_frame
, prologue_cache
);
2984 return trad_frame_get_prev_register (this_frame
, cache
->regs
, regnum
);
2987 /* Structure defining the RiscV normal frame unwind functions. Since we
2988 are the fallback unwinder (DWARF unwinder is used first), we use the
2989 default frame sniffer, which always accepts the frame. */
2991 static const struct frame_unwind riscv_frame_unwind
=
2993 /*.type =*/ NORMAL_FRAME
,
2994 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2995 /*.this_id =*/ riscv_frame_this_id
,
2996 /*.prev_register =*/ riscv_frame_prev_register
,
2997 /*.unwind_data =*/ NULL
,
2998 /*.sniffer =*/ default_frame_sniffer
,
2999 /*.dealloc_cache =*/ NULL
,
3000 /*.prev_arch =*/ NULL
,
3003 /* Extract a set of required target features out of INFO, specifically the
3004 bfd being executed is examined to see what target features it requires.
3005 IF there is no current bfd, or the bfd doesn't indicate any useful
3006 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
3008 static struct riscv_gdbarch_features
3009 riscv_features_from_gdbarch_info (const struct gdbarch_info info
)
3011 struct riscv_gdbarch_features features
;
3013 /* Now try to improve on the defaults by looking at the binary we are
3014 going to execute. We assume the user knows what they are doing and
3015 that the target will match the binary. Remember, this code path is
3016 only used at all if the target hasn't given us a description, so this
3017 is really a last ditched effort to do something sane before giving
3019 if (info
.abfd
!= NULL
3020 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3022 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
3023 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3025 if (eclass
== ELFCLASS32
)
3027 else if (eclass
== ELFCLASS64
)
3030 internal_error (__FILE__
, __LINE__
,
3031 _("unknown ELF header class %d"), eclass
);
3033 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
3035 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
3042 /* Find a suitable default target description. Use the contents of INFO,
3043 specifically the bfd object being executed, to guide the selection of a
3044 suitable default target description. */
3046 static const struct target_desc
*
3047 riscv_find_default_target_description (const struct gdbarch_info info
)
3049 /* Extract desired feature set from INFO. */
3050 struct riscv_gdbarch_features features
3051 = riscv_features_from_gdbarch_info (info
);
3053 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
3054 this case we fall back to a minimal useful target, 8-byte x-registers,
3055 with no floating point. */
3056 if (features
.xlen
== 0)
3059 /* Now build a target description based on the feature set. */
3060 return riscv_lookup_target_description (features
);
3063 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
3064 is updated with the register numbers for each register as listed in
3065 REG_SET. If any register marked as required in REG_SET is not found in
3066 FEATURE then this function returns false, otherwise, it returns true. */
3069 riscv_check_tdesc_feature (struct tdesc_arch_data
*tdesc_data
,
3070 const struct tdesc_feature
*main_feature
,
3071 const struct tdesc_feature
*csr_feature
,
3072 const struct riscv_register_feature
*reg_set
,
3073 std::vector
<riscv_pending_register_alias
> *aliases
)
3075 for (const auto ®
: reg_set
->registers
)
3077 bool found
= reg
.check (tdesc_data
, main_feature
, reg_set
, aliases
);
3079 if (!found
&& reg
.required
!= RISCV_REG_OPTIONAL
)
3081 if (reg
.required
== RISCV_REG_REQUIRED_MAYBE_CSR
3082 && csr_feature
!= nullptr)
3084 gdb_assert (main_feature
!= csr_feature
);
3085 found
= reg
.check (tdesc_data
, csr_feature
, reg_set
, aliases
);
3095 /* Add all the expected register sets into GDBARCH. */
3098 riscv_add_reggroups (struct gdbarch
*gdbarch
)
3100 /* Add predefined register groups. */
3101 reggroup_add (gdbarch
, all_reggroup
);
3102 reggroup_add (gdbarch
, save_reggroup
);
3103 reggroup_add (gdbarch
, restore_reggroup
);
3104 reggroup_add (gdbarch
, system_reggroup
);
3105 reggroup_add (gdbarch
, vector_reggroup
);
3106 reggroup_add (gdbarch
, general_reggroup
);
3107 reggroup_add (gdbarch
, float_reggroup
);
3109 /* Add RISC-V specific register groups. */
3110 reggroup_add (gdbarch
, csr_reggroup
);
3113 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3116 riscv_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
3118 if (reg
< RISCV_DWARF_REGNUM_X31
)
3119 return RISCV_ZERO_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_X0
);
3121 else if (reg
< RISCV_DWARF_REGNUM_F31
)
3122 return RISCV_FIRST_FP_REGNUM
+ (reg
- RISCV_DWARF_REGNUM_F0
);
3127 /* Implement the gcc_target_options method. We have to select the arch and abi
3128 from the feature info. We have enough feature info to select the abi, but
3129 not enough info for the arch given all of the possible architecture
3130 extensions. So choose reasonable defaults for now. */
3133 riscv_gcc_target_options (struct gdbarch
*gdbarch
)
3135 int isa_xlen
= riscv_isa_xlen (gdbarch
);
3136 int isa_flen
= riscv_isa_flen (gdbarch
);
3137 int abi_xlen
= riscv_abi_xlen (gdbarch
);
3138 int abi_flen
= riscv_abi_flen (gdbarch
);
3139 std::string target_options
;
3141 target_options
= "-march=rv";
3143 target_options
+= "64";
3145 target_options
+= "32";
3147 target_options
+= "gc";
3148 else if (isa_flen
== 4)
3149 target_options
+= "imafc";
3151 target_options
+= "imac";
3153 target_options
+= " -mabi=";
3155 target_options
+= "lp64";
3157 target_options
+= "ilp32";
3159 target_options
+= "d";
3160 else if (abi_flen
== 4)
3161 target_options
+= "f";
3163 /* The gdb loader doesn't handle link-time relaxation relocations. */
3164 target_options
+= " -mno-relax";
3166 return target_options
;
3169 /* Implement the gnu_triplet_regexp method. A single compiler supports both
3170 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
3171 recommended) riscv. */
3174 riscv_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
3176 return "riscv(32|64)?";
3179 /* Initialize the current architecture based on INFO. If possible,
3180 re-use an architecture from ARCHES, which is a list of
3181 architectures already created during this debugging session.
3183 Called e.g. at program startup, when reading a core file, and when
3184 reading a binary file. */
3186 static struct gdbarch
*
3187 riscv_gdbarch_init (struct gdbarch_info info
,
3188 struct gdbarch_list
*arches
)
3190 struct gdbarch
*gdbarch
;
3191 struct gdbarch_tdep
*tdep
;
3192 struct riscv_gdbarch_features features
;
3193 const struct target_desc
*tdesc
= info
.target_desc
;
3195 /* Ensure we always have a target description. */
3196 if (!tdesc_has_registers (tdesc
))
3197 tdesc
= riscv_find_default_target_description (info
);
3200 if (riscv_debug_gdbarch
)
3201 fprintf_unfiltered (gdb_stdlog
, "Have got a target description\n");
3203 const struct tdesc_feature
*feature_cpu
3204 = tdesc_find_feature (tdesc
, riscv_xreg_feature
.name
);
3205 const struct tdesc_feature
*feature_fpu
3206 = tdesc_find_feature (tdesc
, riscv_freg_feature
.name
);
3207 const struct tdesc_feature
*feature_virtual
3208 = tdesc_find_feature (tdesc
, riscv_virtual_feature
.name
);
3209 const struct tdesc_feature
*feature_csr
3210 = tdesc_find_feature (tdesc
, riscv_csr_feature
.name
);
3212 if (feature_cpu
== NULL
)
3215 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3216 std::vector
<riscv_pending_register_alias
> pending_aliases
;
3218 bool valid_p
= riscv_check_tdesc_feature (tdesc_data
,
3219 feature_cpu
, feature_csr
,
3220 &riscv_xreg_feature
,
3224 /* Check that all of the core cpu registers have the same bitsize. */
3225 int xlen_bitsize
= tdesc_register_bitsize (feature_cpu
, "pc");
3227 for (auto &tdesc_reg
: feature_cpu
->registers
)
3228 valid_p
&= (tdesc_reg
->bitsize
== xlen_bitsize
);
3230 if (riscv_debug_gdbarch
)
3233 "From target-description, xlen = %d\n", xlen_bitsize
);
3235 features
.xlen
= (xlen_bitsize
/ 8);
3238 if (feature_fpu
!= NULL
)
3240 valid_p
&= riscv_check_tdesc_feature (tdesc_data
, feature_fpu
,
3242 &riscv_freg_feature
,
3245 /* Search for the first floating point register (by any alias), to
3246 determine the bitsize. */
3248 const auto &fp0
= riscv_freg_feature
.registers
[0];
3250 for (const char *name
: fp0
.names
)
3252 if (tdesc_unnumbered_register (feature_fpu
, name
))
3254 bitsize
= tdesc_register_bitsize (feature_fpu
, name
);
3259 gdb_assert (bitsize
!= -1);
3260 features
.flen
= (bitsize
/ 8);
3262 if (riscv_debug_gdbarch
)
3265 "From target-description, flen = %d\n", bitsize
);
3271 if (riscv_debug_gdbarch
)
3274 "No FPU in target-description, assume soft-float ABI\n");
3277 if (feature_virtual
)
3278 riscv_check_tdesc_feature (tdesc_data
, feature_virtual
, feature_csr
,
3279 &riscv_virtual_feature
,
3283 riscv_check_tdesc_feature (tdesc_data
, feature_csr
, nullptr,
3289 if (riscv_debug_gdbarch
)
3290 fprintf_unfiltered (gdb_stdlog
, "Target description is not valid\n");
3291 tdesc_data_cleanup (tdesc_data
);
3295 /* Have a look at what the supplied (if any) bfd object requires of the
3296 target, then check that this matches with what the target is
3298 struct riscv_gdbarch_features abi_features
3299 = riscv_features_from_gdbarch_info (info
);
3300 /* In theory a binary compiled for RV32 could run on an RV64 target,
3301 however, this has not been tested in GDB yet, so for now we require
3302 that the requested xlen match the targets xlen. */
3303 if (abi_features
.xlen
!= 0 && abi_features
.xlen
!= features
.xlen
)
3304 error (_("bfd requires xlen %d, but target has xlen %d"),
3305 abi_features
.xlen
, features
.xlen
);
3306 /* We do support running binaries compiled for 32-bit float on targets
3307 with 64-bit float, so we only complain if the binary requires more
3308 than the target has available. */
3309 if (abi_features
.flen
> features
.flen
)
3310 error (_("bfd requires flen %d, but target has flen %d"),
3311 abi_features
.flen
, features
.flen
);
3313 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3314 features from the INFO object. In this case we assume that the xlen
3315 abi matches the hardware. */
3316 if (abi_features
.xlen
== 0)
3317 abi_features
.xlen
= features
.xlen
;
3319 /* Find a candidate among the list of pre-declared architectures. */
3320 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3322 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3324 /* Check that the feature set of the ARCHES matches the feature set
3325 we are looking for. If it doesn't then we can't reuse this
3327 struct gdbarch_tdep
*other_tdep
= gdbarch_tdep (arches
->gdbarch
);
3329 if (other_tdep
->isa_features
!= features
3330 || other_tdep
->abi_features
!= abi_features
)
3338 tdesc_data_cleanup (tdesc_data
);
3339 return arches
->gdbarch
;
3342 /* None found, so create a new architecture from the information provided. */
3343 tdep
= new (struct gdbarch_tdep
);
3344 gdbarch
= gdbarch_alloc (&info
, tdep
);
3345 tdep
->isa_features
= features
;
3346 tdep
->abi_features
= abi_features
;
3348 /* Target data types. */
3349 set_gdbarch_short_bit (gdbarch
, 16);
3350 set_gdbarch_int_bit (gdbarch
, 32);
3351 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3352 set_gdbarch_long_long_bit (gdbarch
, 64);
3353 set_gdbarch_float_bit (gdbarch
, 32);
3354 set_gdbarch_double_bit (gdbarch
, 64);
3355 set_gdbarch_long_double_bit (gdbarch
, 128);
3356 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3357 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
3358 set_gdbarch_char_signed (gdbarch
, 0);
3359 set_gdbarch_type_align (gdbarch
, riscv_type_align
);
3361 /* Information about the target architecture. */
3362 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
3363 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
3364 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
3365 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3367 /* Functions to analyze frames. */
3368 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
3369 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3370 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
3372 /* Functions handling dummy frames. */
3373 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3374 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
3375 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
3377 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3379 dwarf2_append_unwinders (gdbarch
);
3380 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
3382 /* Register architecture. */
3383 riscv_add_reggroups (gdbarch
);
3385 /* Internal <-> external register number maps. */
3386 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, riscv_dwarf_reg_to_regnum
);
3388 /* We reserve all possible register numbers for the known registers.
3389 This means the target description mechanism will add any target
3390 specific registers after this number. This helps make debugging GDB
3391 just a little easier. */
3392 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
3394 /* We don't have to provide the count of 0 here (its the default) but
3395 include this line to make it explicit that, right now, we don't have
3396 any pseudo registers on RISC-V. */
3397 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
3399 /* Some specific register numbers GDB likes to know about. */
3400 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
3401 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
3403 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
3405 /* Finalise the target description registers. */
3406 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3408 /* Override the register type callback setup by the target description
3409 mechanism. This allows us to provide special type for floating point
3411 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
3413 /* Override the register name callback setup by the target description
3414 mechanism. This allows us to force our preferred names for the
3415 registers, no matter what the target description called them. */
3416 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
3418 /* Override the register group callback setup by the target description
3419 mechanism. This allows us to force registers into the groups we
3420 want, ignoring what the target tells us. */
3421 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
3423 /* Create register aliases for alternative register names. We only
3424 create aliases for registers which were mentioned in the target
3426 for (const auto &alias
: pending_aliases
)
3427 alias
.create (gdbarch
);
3429 /* Compile command hooks. */
3430 set_gdbarch_gcc_target_options (gdbarch
, riscv_gcc_target_options
);
3431 set_gdbarch_gnu_triplet_regexp (gdbarch
, riscv_gnu_triplet_regexp
);
3433 /* Hook in OS ABI-specific overrides, if they have been registered. */
3434 gdbarch_init_osabi (info
, gdbarch
);
3436 register_riscv_ravenscar_ops (gdbarch
);
3441 /* This decodes the current instruction and determines the address of the
3442 next instruction. */
3445 riscv_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
3447 struct gdbarch
*gdbarch
= regcache
->arch ();
3448 struct riscv_insn insn
;
3451 insn
.decode (gdbarch
, pc
);
3452 next_pc
= pc
+ insn
.length ();
3454 if (insn
.opcode () == riscv_insn::JAL
)
3455 next_pc
= pc
+ insn
.imm_signed ();
3456 else if (insn
.opcode () == riscv_insn::JALR
)
3459 regcache
->cooked_read (insn
.rs1 (), &source
);
3460 next_pc
= (source
+ insn
.imm_signed ()) & ~(CORE_ADDR
) 0x1;
3462 else if (insn
.opcode () == riscv_insn::BEQ
)
3465 regcache
->cooked_read (insn
.rs1 (), &src1
);
3466 regcache
->cooked_read (insn
.rs2 (), &src2
);
3468 next_pc
= pc
+ insn
.imm_signed ();
3470 else if (insn
.opcode () == riscv_insn::BNE
)
3473 regcache
->cooked_read (insn
.rs1 (), &src1
);
3474 regcache
->cooked_read (insn
.rs2 (), &src2
);
3476 next_pc
= pc
+ insn
.imm_signed ();
3478 else if (insn
.opcode () == riscv_insn::BLT
)
3481 regcache
->cooked_read (insn
.rs1 (), &src1
);
3482 regcache
->cooked_read (insn
.rs2 (), &src2
);
3484 next_pc
= pc
+ insn
.imm_signed ();
3486 else if (insn
.opcode () == riscv_insn::BGE
)
3489 regcache
->cooked_read (insn
.rs1 (), &src1
);
3490 regcache
->cooked_read (insn
.rs2 (), &src2
);
3492 next_pc
= pc
+ insn
.imm_signed ();
3494 else if (insn
.opcode () == riscv_insn::BLTU
)
3496 ULONGEST src1
, src2
;
3497 regcache
->cooked_read (insn
.rs1 (), &src1
);
3498 regcache
->cooked_read (insn
.rs2 (), &src2
);
3500 next_pc
= pc
+ insn
.imm_signed ();
3502 else if (insn
.opcode () == riscv_insn::BGEU
)
3504 ULONGEST src1
, src2
;
3505 regcache
->cooked_read (insn
.rs1 (), &src1
);
3506 regcache
->cooked_read (insn
.rs2 (), &src2
);
3508 next_pc
= pc
+ insn
.imm_signed ();
3514 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3515 for the end of the sequence and put the breakpoint there. */
3518 riscv_next_pc_atomic_sequence (struct regcache
*regcache
, CORE_ADDR pc
,
3521 struct gdbarch
*gdbarch
= regcache
->arch ();
3522 struct riscv_insn insn
;
3523 CORE_ADDR cur_step_pc
= pc
;
3524 CORE_ADDR last_addr
= 0;
3526 /* First instruction has to be a load reserved. */
3527 insn
.decode (gdbarch
, cur_step_pc
);
3528 if (insn
.opcode () != riscv_insn::LR
)
3530 cur_step_pc
= cur_step_pc
+ insn
.length ();
3532 /* Next instruction should be branch to exit. */
3533 insn
.decode (gdbarch
, cur_step_pc
);
3534 if (insn
.opcode () != riscv_insn::BNE
)
3536 last_addr
= cur_step_pc
+ insn
.imm_signed ();
3537 cur_step_pc
= cur_step_pc
+ insn
.length ();
3539 /* Next instruction should be store conditional. */
3540 insn
.decode (gdbarch
, cur_step_pc
);
3541 if (insn
.opcode () != riscv_insn::SC
)
3543 cur_step_pc
= cur_step_pc
+ insn
.length ();
3545 /* Next instruction should be branch to start. */
3546 insn
.decode (gdbarch
, cur_step_pc
);
3547 if (insn
.opcode () != riscv_insn::BNE
)
3549 if (pc
!= (cur_step_pc
+ insn
.imm_signed ()))
3551 cur_step_pc
= cur_step_pc
+ insn
.length ();
3553 /* We should now be at the end of the sequence. */
3554 if (cur_step_pc
!= last_addr
)
3557 *next_pc
= cur_step_pc
;
3561 /* This is called just before we want to resume the inferior, if we want to
3562 single-step it but there is no hardware or kernel single-step support. We
3563 find the target of the coming instruction and breakpoint it. */
3565 std::vector
<CORE_ADDR
>
3566 riscv_software_single_step (struct regcache
*regcache
)
3568 CORE_ADDR pc
, next_pc
;
3570 pc
= regcache_read_pc (regcache
);
3572 if (riscv_next_pc_atomic_sequence (regcache
, pc
, &next_pc
))
3575 next_pc
= riscv_next_pc (regcache
, pc
);
3580 /* Create RISC-V specific reggroups. */
3583 riscv_init_reggroups ()
3585 csr_reggroup
= reggroup_new ("csr", USER_REGGROUP
);
3588 void _initialize_riscv_tdep ();
3590 _initialize_riscv_tdep ()
3592 riscv_create_csr_aliases ();
3593 riscv_init_reggroups ();
3595 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
3597 /* Add root prefix command for all "set debug riscv" and "show debug
3599 add_basic_prefix_cmd ("riscv", no_class
,
3600 _("RISC-V specific debug commands."),
3601 &setdebugriscvcmdlist
, "set debug riscv ", 0,
3604 add_show_prefix_cmd ("riscv", no_class
,
3605 _("RISC-V specific debug commands."),
3606 &showdebugriscvcmdlist
, "show debug riscv ", 0,
3609 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance
,
3610 &riscv_debug_breakpoints
, _("\
3611 Set riscv breakpoint debugging."), _("\
3612 Show riscv breakpoint debugging."), _("\
3613 When non-zero, print debugging information for the riscv specific parts\n\
3614 of the breakpoint mechanism."),
3616 show_riscv_debug_variable
,
3617 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3619 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
3620 &riscv_debug_infcall
, _("\
3621 Set riscv inferior call debugging."), _("\
3622 Show riscv inferior call debugging."), _("\
3623 When non-zero, print debugging information for the riscv specific parts\n\
3624 of the inferior call mechanism."),
3626 show_riscv_debug_variable
,
3627 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3629 add_setshow_zuinteger_cmd ("unwinder", class_maintenance
,
3630 &riscv_debug_unwinder
, _("\
3631 Set riscv stack unwinding debugging."), _("\
3632 Show riscv stack unwinding debugging."), _("\
3633 When non-zero, print debugging information for the riscv specific parts\n\
3634 of the stack unwinding mechanism."),
3636 show_riscv_debug_variable
,
3637 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3639 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance
,
3640 &riscv_debug_gdbarch
, _("\
3641 Set riscv gdbarch initialisation debugging."), _("\
3642 Show riscv gdbarch initialisation debugging."), _("\
3643 When non-zero, print debugging information for the riscv gdbarch\n\
3644 initialisation process."),
3646 show_riscv_debug_variable
,
3647 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
3649 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3650 add_basic_prefix_cmd ("riscv", no_class
,
3651 _("RISC-V specific commands."),
3652 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
3654 add_show_prefix_cmd ("riscv", no_class
,
3655 _("RISC-V specific commands."),
3656 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
3659 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
3660 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
3661 &use_compressed_breakpoints
,
3663 Set debugger's use of compressed breakpoints."), _(" \
3664 Show debugger's use of compressed breakpoints."), _("\
3665 Debugging compressed code requires compressed breakpoints to be used. If\n\
3666 left to 'auto' then gdb will use them if the existing instruction is a\n\
3667 compressed instruction. If that doesn't give the correct behavior, then\n\
3668 this option can be used."),
3670 show_use_compressed_breakpoints
,