gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29   const regs_info *get_regs_info () override;
  30
  31   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  32
  33   bool supports_z_point_type (char z_type) override;
  34
  35 protected:
  36
  37   void low_arch_setup () override;
  38
  39   bool low_cannot_fetch_register (int regno) override;
  40
  41   bool low_cannot_store_register (int regno) override;
  42
  43   bool low_supports_breakpoints () override;
  44
  45   CORE_ADDR low_get_pc (regcache *regcache) override;
  46
  47   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  48
  49   bool low_breakpoint_at (CORE_ADDR pc) override;
  50
  51   int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
  52                         int size, raw_breakpoint *bp) override;
  53
  54   int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
  55                         int size, raw_breakpoint *bp) override;
  56
  57   bool low_stopped_by_watchpoint () override;
  58
  59   CORE_ADDR low_stopped_data_address () override;
  60 };
  61
  62 /* The singleton target ops object.  */
  63
  64 static crisv32_target the_crisv32_target;
  65
  66 bool
  67 crisv32_target::low_cannot_fetch_register (int regno)
  68 {
  69   gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
  70                           "is not implemented by the target");
  71 }
  72
  73 bool
  74 crisv32_target::low_cannot_store_register (int regno)
  75 {
  76   gdb_assert_not_reached ("linux target op low_cannot_store_register "
  77                           "is not implemented by the target");
  78 }
  79
  80 bool
  81 crisv32_target::low_supports_breakpoints ()
  82 {
  83   return true;
  84 }
  85
  86 CORE_ADDR
  87 crisv32_target::low_get_pc (regcache *regcache)
  88 {
  89   return linux_get_pc_32bit (regcache);
  90 }
  91
  92 void
  93 crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
  94 {
  95   linux_set_pc_32bit (regcache, pc);
  96 }
  97
  98 /* Defined in auto-generated file reg-crisv32.c.  */
  99 void init_registers_crisv32 (void);
 100 extern const struct target_desc *tdesc_crisv32;
 101
 102 /* CRISv32 */
 103 #define cris_num_regs 49
 104
 105 #ifndef PTRACE_GET_THREAD_AREA
 106 #define PTRACE_GET_THREAD_AREA 25
 107 #endif
 108
 109 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
 110    without any significant gain).  */
 111
 112 /* Locations need to match <include/asm/arch/ptrace.h>.  */
 113 static int cris_regmap[] = {
 114   1*4, 2*4, 3*4, 4*4,
 115   5*4, 6*4, 7*4, 8*4,
 116   9*4, 10*4, 11*4, 12*4,
 117   13*4, 14*4, 24*4, 15*4,
 118
 119   -1, -1, -1, 16*4,
 120   -1, 22*4, 23*4, 17*4,
 121   -1, -1, 21*4, 20*4,
 122   -1, 19*4, -1, 18*4,
 123
 124   25*4,
 125
 126   26*4, -1,   -1,   29*4,
 127   30*4, 31*4, 32*4, 33*4,
 128   34*4, 35*4, 36*4, 37*4,
 129   38*4, 39*4, 40*4, -1
 130
 131 };
 132
 133 static const unsigned short cris_breakpoint = 0xe938;
 134 #define cris_breakpoint_len 2
 135
 136 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 137
 138 const gdb_byte *
 139 crisv32_target::sw_breakpoint_from_kind (int kind, int *size)
 140 {
 141   *size = cris_breakpoint_len;
 142   return (const gdb_byte *) &cris_breakpoint;
 143 }
 144
 145 bool
 146 crisv32_target::low_breakpoint_at (CORE_ADDR where)
 147 {
 148   unsigned short insn;
 149
 150   read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
 151   if (insn == cris_breakpoint)
 152     return true;
 153
 154   /* If necessary, recognize more trap instructions here.  GDB only uses the
 155      one.  */
 156   return false;
 157 }
 158
 159 static void
 160 cris_write_data_breakpoint (struct regcache *regcache,
 161                             int bp, unsigned long start, unsigned long end)
 162 {
 163   switch (bp)
 164     {
 165     case 0:
 166       supply_register_by_name (regcache, "s3", &start);
 167       supply_register_by_name (regcache, "s4", &end);
 168       break;
 169     case 1:
 170       supply_register_by_name (regcache, "s5", &start);
 171       supply_register_by_name (regcache, "s6", &end);
 172       break;
 173     case 2:
 174       supply_register_by_name (regcache, "s7", &start);
 175       supply_register_by_name (regcache, "s8", &end);
 176       break;
 177     case 3:
 178       supply_register_by_name (regcache, "s9", &start);
 179       supply_register_by_name (regcache, "s10", &end);
 180       break;
 181     case 4:
 182       supply_register_by_name (regcache, "s11", &start);
 183       supply_register_by_name (regcache, "s12", &end);
 184       break;
 185     case 5:
 186       supply_register_by_name (regcache, "s13", &start);
 187       supply_register_by_name (regcache, "s14", &end);
 188       break;
 189     }
 190 }
 191
 192 bool
 193 crisv32_target::supports_z_point_type (char z_type)
 194 {
 195   switch (z_type)
 196     {
 197     case Z_PACKET_WRITE_WP:
 198     case Z_PACKET_READ_WP:
 199     case Z_PACKET_ACCESS_WP:
 200       return true;
 201     default:
 202       return false;
 203     }
 204 }
 205
 206 int
 207 crisv32_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
 208                                   int len, raw_breakpoint *bp)
 209 {
 210   int bp;
 211   unsigned long bp_ctrl;
 212   unsigned long start, end;
 213   unsigned long ccs;
 214   struct regcache *regcache;
 215
 216   regcache = get_thread_regcache (current_thread, 1);
 217
 218   /* Read watchpoints are set as access watchpoints, because of GDB's
 219      inability to deal with pure read watchpoints.  */
 220   if (type == raw_bkpt_type_read_wp)
 221     type = raw_bkpt_type_access_wp;
 222
 223   /* Get the configuration register.  */
 224   collect_register_by_name (regcache, "s0", &bp_ctrl);
 225
 226   /* The watchpoint allocation scheme is the simplest possible.
 227      For example, if a region is watched for read and
 228      a write watch is requested, a new watchpoint will
 229      be used.  Also, if a watch for a region that is already
 230      covered by one or more existing watchpoints, a new
 231      watchpoint will be used.  */
 232
 233   /* First, find a free data watchpoint.  */
 234   for (bp = 0; bp < 6; bp++)
 235     {
 236       /* Each data watchpoint's control registers occupy 2 bits
 237          (hence the 3), starting at bit 2 for D0 (hence the 2)
 238          with 4 bits between for each watchpoint (yes, the 4).  */
 239       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 240         break;
 241     }
 242
 243   if (bp > 5)
 244     {
 245       /* We're out of watchpoints.  */
 246       return -1;
 247     }
 248
 249   /* Configure the control register first.  */
 250   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 251     {
 252       /* Trigger on read.  */
 253       bp_ctrl |= (1 << (2 + bp * 4));
 254     }
 255   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 256     {
 257       /* Trigger on write.  */
 258       bp_ctrl |= (2 << (2 + bp * 4));
 259     }
 260
 261   /* Setup the configuration register.  */
 262   supply_register_by_name (regcache, "s0", &bp_ctrl);
 263
 264   /* Setup the range.  */
 265   start = addr;
 266   end = addr + len - 1;
 267
 268   /* Configure the watchpoint register.  */
 269   cris_write_data_breakpoint (regcache, bp, start, end);
 270
 271   collect_register_by_name (regcache, "ccs", &ccs);
 272   /* Set the S1 flag to enable watchpoints.  */
 273   ccs |= (1 << 19);
 274   supply_register_by_name (regcache, "ccs", &ccs);
 275
 276   return 0;
 277 }
 278
 279 int
 280 crisv32_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
 281                                   int len, raw_breakpoint *bp)
 282 {
 283   int bp;
 284   unsigned long bp_ctrl;
 285   unsigned long start, end;
 286   struct regcache *regcache;
 287   unsigned long bp_d_regs[12];
 288
 289   regcache = get_thread_regcache (current_thread, 1);
 290
 291   /* Read watchpoints are set as access watchpoints, because of GDB's
 292      inability to deal with pure read watchpoints.  */
 293   if (type == raw_bkpt_type_read_wp)
 294     type = raw_bkpt_type_access_wp;
 295
 296   /* Get the configuration register.  */
 297   collect_register_by_name (regcache, "s0", &bp_ctrl);
 298
 299   /* Try to find a watchpoint that is configured for the
 300      specified range, then check that read/write also matches.  */
 301
 302   /* Ugly pointer arithmetic, since I cannot rely on a
 303      single switch (addr) as there may be several watchpoints with
 304      the same start address for example.  */
 305
 306   /* Get all range registers to simplify search.  */
 307   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 308   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 309   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 310   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 311   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 312   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 313   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 314   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 315   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 316   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 317   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 318   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 319
 320   for (bp = 0; bp < 6; bp++)
 321     {
 322       if (bp_d_regs[bp * 2] == addr
 323           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 324         /* Matching range.  */
 325         int bitpos = 2 + bp * 4;
 326         int rw_bits;
 327
 328         /* Read/write bits for this BP.  */
 329         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 330
 331         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 332             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 333             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 334           {
 335             /* Read/write matched.  */
 336             break;
 337           }
 338       }
 339     }
 340
 341   if (bp > 5)
 342     {
 343       /* No watchpoint matched.  */
 344       return -1;
 345     }
 346
 347   /* Found a matching watchpoint.  Now, deconfigure it by
 348      both disabling read/write in bp_ctrl and zeroing its
 349      start/end addresses.  */
 350   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 351   /* Setup the configuration register.  */
 352   supply_register_by_name (regcache, "s0", &bp_ctrl);
 353
 354   start = end = 0;
 355   /* Configure the watchpoint register.  */
 356   cris_write_data_breakpoint (regcache, bp, start, end);
 357
 358   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 359   return 0;
 360 }
 361
 362 bool
 363 crisv32_target::low_stopped_by_watchpoint ()
 364 {
 365   unsigned long exs;
 366   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 367
 368   collect_register_by_name (regcache, "exs", &exs);
 369
 370   return (((exs & 0xff00) >> 8) == 0xc);
 371 }
 372
 373 CORE_ADDR
 374 crisv32_target::low_stopped_data_address ()
 375 {
 376   unsigned long eda;
 377   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 378
 379   collect_register_by_name (regcache, "eda", &eda);
 380
 381   /* FIXME: Possibly adjust to match watched range.  */
 382   return eda;
 383 }
 384
 385 ps_err_e
 386 ps_get_thread_area (struct ps_prochandle *ph,
 387                     lwpid_t lwpid, int idx, void **base)
 388 {
 389   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 390     return PS_ERR;
 391
 392   /* IDX is the bias from the thread pointer to the beginning of the
 393      thread descriptor.  It has to be subtracted due to implementation
 394      quirks in libthread_db.  */
 395   *base = (void *) ((char *) *base - idx);
 396   return PS_OK;
 397 }
 398
 399 static void
 400 cris_fill_gregset (struct regcache *regcache, void *buf)
 401 {
 402   int i;
 403
 404   for (i = 0; i < cris_num_regs; i++)
 405     {
 406       if (cris_regmap[i] != -1)
 407         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 408     }
 409 }
 410
 411 static void
 412 cris_store_gregset (struct regcache *regcache, const void *buf)
 413 {
 414   int i;
 415
 416   for (i = 0; i < cris_num_regs; i++)
 417     {
 418       if (cris_regmap[i] != -1)
 419         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 420     }
 421 }
 422
 423 void
 424 crisv32_target::low_arch_setup ()
 425 {
 426   current_process ()->tdesc = tdesc_crisv32;
 427 }
 428
 429 static struct regset_info cris_regsets[] = {
 430   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 431     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 432   NULL_REGSET
 433 };
 434
 435
 436 static struct regsets_info cris_regsets_info =
 437   {
 438     cris_regsets, /* regsets */
 439     0, /* num_regsets */
 440     NULL, /* disabled_regsets */
 441   };
 442
 443 static struct usrregs_info cris_usrregs_info =
 444   {
 445     cris_num_regs,
 446     cris_regmap,
 447   };
 448
 449 static struct regs_info myregs_info =
 450   {
 451     NULL, /* regset_bitmap */
 452     &cris_usrregs_info,
 453     &cris_regsets_info
 454   };
 455
 456 const regs_info *
 457 crisv32_target::get_regs_info ()
 458 {
 459   return &myregs_info;
 460 }
 461
 462 /* The linux target ops object.  */
 463
 464 linux_process_target *the_linux_target = &the_crisv32_target;
 465
 466 void
 467 initialize_low_arch (void)
 468 {
 469   init_registers_crisv32 ();
 470
 471   initialize_regsets_info (&cris_regsets_info);
 472 }