include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 /* The offset for pc-relative addressing is currently defined to be 0.  */
  31 #define AARCH64_PCREL_OFFSET            0
  32
  33 typedef uint32_t aarch64_insn;
  34
  35 /* The following bitmasks control CPU features.  */
  36 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  37 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  38 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  39 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  40 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  41 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  42
  43 /* Architectures are the sum of the base and extensions.  */
  44 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  45                                                  AARCH64_FEATURE_FP  \
  46                                                  | AARCH64_FEATURE_SIMD)
  47 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  48 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  49
  50 /* CPU-specific features.  */
  51 typedef unsigned long aarch64_feature_set;
  52
  53 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  54   (((CPU) & (FEAT)) != 0)
  55
  56 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  57   do                                            \
  58     {                                           \
  59       (TARG) = (F1) | (F2);                     \
  60     }                                           \
  61   while (0)
  62
  63 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  64   do                                            \
  65     {                                           \
  66       (TARG) = (F1) &~ (F2);                    \
  67     }                                           \
  68   while (0)
  69
  70 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  71
  72 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
  73   (((OPC) & (FEAT)) != 0)
  74
  75 enum aarch64_operand_class
  76 {
  77   AARCH64_OPND_CLASS_NIL,
  78   AARCH64_OPND_CLASS_INT_REG,
  79   AARCH64_OPND_CLASS_MODIFIED_REG,
  80   AARCH64_OPND_CLASS_FP_REG,
  81   AARCH64_OPND_CLASS_SIMD_REG,
  82   AARCH64_OPND_CLASS_SIMD_ELEMENT,
  83   AARCH64_OPND_CLASS_SISD_REG,
  84   AARCH64_OPND_CLASS_SIMD_REGLIST,
  85   AARCH64_OPND_CLASS_CP_REG,
  86   AARCH64_OPND_CLASS_ADDRESS,
  87   AARCH64_OPND_CLASS_IMMEDIATE,
  88   AARCH64_OPND_CLASS_SYSTEM,
  89   AARCH64_OPND_CLASS_COND,
  90 };
  91
  92 /* Operand code that helps both parsing and coding.
  93    Keep AARCH64_OPERANDS synced.  */
  94
  95 enum aarch64_opnd
  96 {
  97   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
  98
  99   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 100   AARCH64_OPND_Rn,      /* Integer register as source.  */
 101   AARCH64_OPND_Rm,      /* Integer register as source.  */
 102   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 103   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 104   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 105   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 106   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 107
 108   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 109   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 110   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 111   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 112   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 113
 114   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 115   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 116   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 117   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 118   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 119   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 120
 121   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 122   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 123   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 124
 125   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 126   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 127   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 128   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 129   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 130   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 131   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 132   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 133   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 134   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 135   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 136                            structure to all lanes.  */
 137   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 138
 139   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 140   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 141
 142   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 143   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 144   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 145   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 146   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 147   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 148   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 149                            (no encoding).  */
 150   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 151   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 152   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 153   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 154   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 155   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 156   AARCH64_OPND_IMM,     /* Immediate.  */
 157   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 158   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 159   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 160   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 161   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 162   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 163   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 164   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 165                            each condition flag.  */
 166
 167   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 168   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 169   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 170   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 171   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 172
 173   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 174   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 175
 176   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 177   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 178   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 179   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 180   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 181
 182   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 183   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 184   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 185   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 186   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 187                                    negative or unaligned and there is
 188                                    no writeback allowed.  This operand code
 189                                    is only used to support the programmer-
 190                                    friendly feature of using LDR/STR as the
 191                                    the mnemonic name for LDUR/STUR instructions
 192                                    wherever there is no ambiguity.  */
 193   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 194   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 195   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 196
 197   AARCH64_OPND_SYSREG,          /* System register operand.  */
 198   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 199   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 200   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 201   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 202   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 203   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 204   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 205   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 206 };
 207
 208 /* Qualifier constrains an operand.  It either specifies a variant of an
 209    operand type or limits values available to an operand type.
 210
 211    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 212
 213 enum aarch64_opnd_qualifier
 214 {
 215   /* Indicating no further qualification on an operand.  */
 216   AARCH64_OPND_QLF_NIL,
 217
 218   /* Qualifying an operand which is a general purpose (integer) register;
 219      indicating the operand data size or a specific register.  */
 220   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 221   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 222   AARCH64_OPND_QLF_WSP, /* WSP.  */
 223   AARCH64_OPND_QLF_SP,  /* SP.  */
 224
 225   /* Qualifying an operand which is a floating-point register, a SIMD
 226      vector element or a SIMD vector element list; indicating operand data
 227      size or the size of each SIMD vector element in the case of a SIMD
 228      vector element list.
 229      These qualifiers are also used to qualify an address operand to
 230      indicate the size of data element a load/store instruction is
 231      accessing.
 232      They are also used for the immediate shift operand in e.g. SSHR.  Such
 233      a use is only for the ease of operand encoding/decoding and qualifier
 234      sequence matching; such a use should not be applied widely; use the value
 235      constraint qualifiers for immediate operands wherever possible.  */
 236   AARCH64_OPND_QLF_S_B,
 237   AARCH64_OPND_QLF_S_H,
 238   AARCH64_OPND_QLF_S_S,
 239   AARCH64_OPND_QLF_S_D,
 240   AARCH64_OPND_QLF_S_Q,
 241
 242   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 243      register list; indicating register shape.
 244      They are also used for the immediate shift operand in e.g. SSHR.  Such
 245      a use is only for the ease of operand encoding/decoding and qualifier
 246      sequence matching; such a use should not be applied widely; use the value
 247      constraint qualifiers for immediate operands wherever possible.  */
 248   AARCH64_OPND_QLF_V_8B,
 249   AARCH64_OPND_QLF_V_16B,
 250   AARCH64_OPND_QLF_V_4H,
 251   AARCH64_OPND_QLF_V_8H,
 252   AARCH64_OPND_QLF_V_2S,
 253   AARCH64_OPND_QLF_V_4S,
 254   AARCH64_OPND_QLF_V_1D,
 255   AARCH64_OPND_QLF_V_2D,
 256   AARCH64_OPND_QLF_V_1Q,
 257
 258   /* Constraint on value.  */
 259   AARCH64_OPND_QLF_imm_0_7,
 260   AARCH64_OPND_QLF_imm_0_15,
 261   AARCH64_OPND_QLF_imm_0_31,
 262   AARCH64_OPND_QLF_imm_0_63,
 263   AARCH64_OPND_QLF_imm_1_32,
 264   AARCH64_OPND_QLF_imm_1_64,
 265
 266   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 267      or shift-ones.  */
 268   AARCH64_OPND_QLF_LSL,
 269   AARCH64_OPND_QLF_MSL,
 270
 271   /* Special qualifier helping retrieve qualifier information during the
 272      decoding time (currently not in use).  */
 273   AARCH64_OPND_QLF_RETRIEVE,
 274 };
 275 \f
 276 /* Instruction class.  */
 277
 278 enum aarch64_insn_class
 279 {
 280   addsub_carry,
 281   addsub_ext,
 282   addsub_imm,
 283   addsub_shift,
 284   asimdall,
 285   asimddiff,
 286   asimdelem,
 287   asimdext,
 288   asimdimm,
 289   asimdins,
 290   asimdmisc,
 291   asimdperm,
 292   asimdsame,
 293   asimdshf,
 294   asimdtbl,
 295   asisddiff,
 296   asisdelem,
 297   asisdlse,
 298   asisdlsep,
 299   asisdlso,
 300   asisdlsop,
 301   asisdmisc,
 302   asisdone,
 303   asisdpair,
 304   asisdsame,
 305   asisdshf,
 306   bitfield,
 307   branch_imm,
 308   branch_reg,
 309   compbranch,
 310   condbranch,
 311   condcmp_imm,
 312   condcmp_reg,
 313   condsel,
 314   cryptoaes,
 315   cryptosha2,
 316   cryptosha3,
 317   dp_1src,
 318   dp_2src,
 319   dp_3src,
 320   exception,
 321   extract,
 322   float2fix,
 323   float2int,
 324   floatccmp,
 325   floatcmp,
 326   floatdp1,
 327   floatdp2,
 328   floatdp3,
 329   floatimm,
 330   floatsel,
 331   ldst_immpost,
 332   ldst_immpre,
 333   ldst_imm9,    /* immpost or immpre */
 334   ldst_pos,
 335   ldst_regoff,
 336   ldst_unpriv,
 337   ldst_unscaled,
 338   ldstexcl,
 339   ldstnapair_offs,
 340   ldstpair_off,
 341   ldstpair_indexed,
 342   loadlit,
 343   log_imm,
 344   log_shift,
 345   lse_atomic,
 346   movewide,
 347   pcreladdr,
 348   ic_system,
 349   testbranch,
 350 };
 351
 352 /* Opcode enumerators.  */
 353
 354 enum aarch64_op
 355 {
 356   OP_NIL,
 357   OP_STRB_POS,
 358   OP_LDRB_POS,
 359   OP_LDRSB_POS,
 360   OP_STRH_POS,
 361   OP_LDRH_POS,
 362   OP_LDRSH_POS,
 363   OP_STR_POS,
 364   OP_LDR_POS,
 365   OP_STRF_POS,
 366   OP_LDRF_POS,
 367   OP_LDRSW_POS,
 368   OP_PRFM_POS,
 369
 370   OP_STURB,
 371   OP_LDURB,
 372   OP_LDURSB,
 373   OP_STURH,
 374   OP_LDURH,
 375   OP_LDURSH,
 376   OP_STUR,
 377   OP_LDUR,
 378   OP_STURV,
 379   OP_LDURV,
 380   OP_LDURSW,
 381   OP_PRFUM,
 382
 383   OP_LDR_LIT,
 384   OP_LDRV_LIT,
 385   OP_LDRSW_LIT,
 386   OP_PRFM_LIT,
 387
 388   OP_ADD,
 389   OP_B,
 390   OP_BL,
 391
 392   OP_MOVN,
 393   OP_MOVZ,
 394   OP_MOVK,
 395
 396   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 397   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 398   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 399
 400   OP_MOV_V,             /* MOV alias for moving vector register.  */
 401
 402   OP_ASR_IMM,
 403   OP_LSR_IMM,
 404   OP_LSL_IMM,
 405
 406   OP_BIC,
 407
 408   OP_UBFX,
 409   OP_BFXIL,
 410   OP_SBFX,
 411   OP_SBFIZ,
 412   OP_BFI,
 413   OP_UBFIZ,
 414   OP_UXTB,
 415   OP_UXTH,
 416   OP_UXTW,
 417
 418   OP_CINC,
 419   OP_CINV,
 420   OP_CNEG,
 421   OP_CSET,
 422   OP_CSETM,
 423
 424   OP_FCVT,
 425   OP_FCVTN,
 426   OP_FCVTN2,
 427   OP_FCVTL,
 428   OP_FCVTL2,
 429   OP_FCVTXN_S,          /* Scalar version.  */
 430
 431   OP_ROR_IMM,
 432
 433   OP_SXTL,
 434   OP_SXTL2,
 435   OP_UXTL,
 436   OP_UXTL2,
 437
 438   OP_TOTAL_NUM,         /* Pseudo.  */
 439 };
 440
 441 /* Maximum number of operands an instruction can have.  */
 442 #define AARCH64_MAX_OPND_NUM 6
 443 /* Maximum number of qualifier sequences an instruction can have.  */
 444 #define AARCH64_MAX_QLF_SEQ_NUM 10
 445 /* Operand qualifier typedef; optimized for the size.  */
 446 typedef unsigned char aarch64_opnd_qualifier_t;
 447 /* Operand qualifier sequence typedef.  */
 448 typedef aarch64_opnd_qualifier_t        \
 449           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 450
 451 /* FIXME: improve the efficiency.  */
 452 static inline bfd_boolean
 453 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 454 {
 455   int i;
 456   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 457     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 458       return FALSE;
 459   return TRUE;
 460 }
 461
 462 /* This structure holds information for a particular opcode.  */
 463
 464 struct aarch64_opcode
 465 {
 466   /* The name of the mnemonic.  */
 467   const char *name;
 468
 469   /* The opcode itself.  Those bits which will be filled in with
 470      operands are zeroes.  */
 471   aarch64_insn opcode;
 472
 473   /* The opcode mask.  This is used by the disassembler.  This is a
 474      mask containing ones indicating those bits which must match the
 475      opcode field, and zeroes indicating those bits which need not
 476      match (and are presumably filled in by operands).  */
 477   aarch64_insn mask;
 478
 479   /* Instruction class.  */
 480   enum aarch64_insn_class iclass;
 481
 482   /* Enumerator identifier.  */
 483   enum aarch64_op op;
 484
 485   /* Which architecture variant provides this instruction.  */
 486   const aarch64_feature_set *avariant;
 487
 488   /* An array of operand codes.  Each code is an index into the
 489      operand table.  They appear in the order which the operands must
 490      appear in assembly code, and are terminated by a zero.  */
 491   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 492
 493   /* A list of operand qualifier code sequence.  Each operand qualifier
 494      code qualifies the corresponding operand code.  Each operand
 495      qualifier sequence specifies a valid opcode variant and related
 496      constraint on operands.  */
 497   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 498
 499   /* Flags providing information about this instruction */
 500   uint32_t flags;
 501 };
 502
 503 typedef struct aarch64_opcode aarch64_opcode;
 504
 505 /* Table describing all the AArch64 opcodes.  */
 506 extern aarch64_opcode aarch64_opcode_table[];
 507
 508 /* Opcode flags.  */
 509 #define F_ALIAS (1 << 0)
 510 #define F_HAS_ALIAS (1 << 1)
 511 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 512    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 513 #define F_P1 (1 << 2)
 514 #define F_P2 (2 << 2)
 515 #define F_P3 (3 << 2)
 516 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 517 #define F_COND (1 << 4)
 518 /* Instruction has the field of 'sf'.  */
 519 #define F_SF (1 << 5)
 520 /* Instruction has the field of 'size:Q'.  */
 521 #define F_SIZEQ (1 << 6)
 522 /* Floating-point instruction has the field of 'type'.  */
 523 #define F_FPTYPE (1 << 7)
 524 /* AdvSIMD scalar instruction has the field of 'size'.  */
 525 #define F_SSIZE (1 << 8)
 526 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 527 #define F_T (1 << 9)
 528 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 529 #define F_GPRSIZE_IN_Q (1 << 10)
 530 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 531 #define F_LDS_SIZE (1 << 11)
 532 /* Optional operand; assume maximum of 1 operand can be optional.  */
 533 #define F_OPD0_OPT (1 << 12)
 534 #define F_OPD1_OPT (2 << 12)
 535 #define F_OPD2_OPT (3 << 12)
 536 #define F_OPD3_OPT (4 << 12)
 537 #define F_OPD4_OPT (5 << 12)
 538 /* Default value for the optional operand when omitted from the assembly.  */
 539 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 540 /* Instruction that is an alias of another instruction needs to be
 541    encoded/decoded by converting it to/from the real form, followed by
 542    the encoding/decoding according to the rules of the real opcode.
 543    This compares to the direct coding using the alias's information.
 544    N.B. this flag requires F_ALIAS to be used together.  */
 545 #define F_CONV (1 << 20)
 546 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 547    friendly pseudo instruction available only in the assembly code (thus will
 548    not show up in the disassembly).  */
 549 #define F_PSEUDO (1 << 21)
 550 /* Instruction has miscellaneous encoding/decoding rules.  */
 551 #define F_MISC (1 << 22)
 552 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 553 #define F_N (1 << 23)
 554 /* Opcode dependent field.  */
 555 #define F_OD(X) (((X) & 0x7) << 24)
 556 /* Instruction has the field of 'sz'.  */
 557 #define F_LSE_SZ (1 << 27)
 558 /* Next bit is 28.  */
 559
 560 static inline bfd_boolean
 561 alias_opcode_p (const aarch64_opcode *opcode)
 562 {
 563   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 564 }
 565
 566 static inline bfd_boolean
 567 opcode_has_alias (const aarch64_opcode *opcode)
 568 {
 569   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 570 }
 571
 572 /* Priority for disassembling preference.  */
 573 static inline int
 574 opcode_priority (const aarch64_opcode *opcode)
 575 {
 576   return (opcode->flags >> 2) & 0x3;
 577 }
 578
 579 static inline bfd_boolean
 580 pseudo_opcode_p (const aarch64_opcode *opcode)
 581 {
 582   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 583 }
 584
 585 static inline bfd_boolean
 586 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 587 {
 588   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 589     ? TRUE : FALSE;
 590 }
 591
 592 static inline aarch64_insn
 593 get_optional_operand_default_value (const aarch64_opcode *opcode)
 594 {
 595   return (opcode->flags >> 15) & 0x1f;
 596 }
 597
 598 static inline unsigned int
 599 get_opcode_dependent_value (const aarch64_opcode *opcode)
 600 {
 601   return (opcode->flags >> 24) & 0x7;
 602 }
 603
 604 static inline bfd_boolean
 605 opcode_has_special_coder (const aarch64_opcode *opcode)
 606 {
 607   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 608           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 609     : FALSE;
 610 }
 611 \f
 612 struct aarch64_name_value_pair
 613 {
 614   const char *  name;
 615   aarch64_insn  value;
 616 };
 617
 618 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 619 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 620 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 621
 622 typedef struct
 623 {
 624   const char *  name;
 625   aarch64_insn  value;
 626   uint32_t      flags;
 627 } aarch64_sys_reg;
 628
 629 extern const aarch64_sys_reg aarch64_sys_regs [];
 630 extern const aarch64_sys_reg aarch64_pstatefields [];
 631 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 632
 633 typedef struct
 634 {
 635   const char *template;
 636   uint32_t value;
 637   int has_xt;
 638 } aarch64_sys_ins_reg;
 639
 640 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 641 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 642 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 643 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 644
 645 /* Shift/extending operator kinds.
 646    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 647 enum aarch64_modifier_kind
 648 {
 649   AARCH64_MOD_NONE,
 650   AARCH64_MOD_MSL,
 651   AARCH64_MOD_ROR,
 652   AARCH64_MOD_ASR,
 653   AARCH64_MOD_LSR,
 654   AARCH64_MOD_LSL,
 655   AARCH64_MOD_UXTB,
 656   AARCH64_MOD_UXTH,
 657   AARCH64_MOD_UXTW,
 658   AARCH64_MOD_UXTX,
 659   AARCH64_MOD_SXTB,
 660   AARCH64_MOD_SXTH,
 661   AARCH64_MOD_SXTW,
 662   AARCH64_MOD_SXTX,
 663 };
 664
 665 bfd_boolean
 666 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 667
 668 enum aarch64_modifier_kind
 669 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 670 /* Condition.  */
 671
 672 typedef struct
 673 {
 674   /* A list of names with the first one as the disassembly preference;
 675      terminated by NULL if fewer than 3.  */
 676   const char *names[3];
 677   aarch64_insn value;
 678 } aarch64_cond;
 679
 680 extern const aarch64_cond aarch64_conds[16];
 681
 682 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 683 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 684 \f
 685 /* Structure representing an operand.  */
 686
 687 struct aarch64_opnd_info
 688 {
 689   enum aarch64_opnd type;
 690   aarch64_opnd_qualifier_t qualifier;
 691   int idx;
 692
 693   union
 694     {
 695       struct
 696         {
 697           unsigned regno;
 698         } reg;
 699       struct
 700         {
 701           unsigned regno : 5;
 702           unsigned index : 4;
 703         } reglane;
 704       /* e.g. LVn.  */
 705       struct
 706         {
 707           unsigned first_regno : 5;
 708           unsigned num_regs : 3;
 709           /* 1 if it is a list of reg element.  */
 710           unsigned has_index : 1;
 711           /* Lane index; valid only when has_index is 1.  */
 712           unsigned index : 4;
 713         } reglist;
 714       /* e.g. immediate or pc relative address offset.  */
 715       struct
 716         {
 717           int64_t value;
 718           unsigned is_fp : 1;
 719         } imm;
 720       /* e.g. address in STR (register offset).  */
 721       struct
 722         {
 723           unsigned base_regno;
 724           struct
 725             {
 726               union
 727                 {
 728                   int imm;
 729                   unsigned regno;
 730                 };
 731               unsigned is_reg;
 732             } offset;
 733           unsigned pcrel : 1;           /* PC-relative.  */
 734           unsigned writeback : 1;
 735           unsigned preind : 1;          /* Pre-indexed.  */
 736           unsigned postind : 1;         /* Post-indexed.  */
 737         } addr;
 738       const aarch64_cond *cond;
 739       /* The encoding of the system register.  */
 740       aarch64_insn sysreg;
 741       /* The encoding of the PSTATE field.  */
 742       aarch64_insn pstatefield;
 743       const aarch64_sys_ins_reg *sysins_op;
 744       const struct aarch64_name_value_pair *barrier;
 745       const struct aarch64_name_value_pair *prfop;
 746     };
 747
 748   /* Operand shifter; in use when the operand is a register offset address,
 749      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 750   struct
 751     {
 752       enum aarch64_modifier_kind kind;
 753       int amount;
 754       unsigned operator_present: 1;     /* Only valid during encoding.  */
 755       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 756       unsigned amount_present: 1;
 757     } shifter;
 758
 759   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 760                            to be done on it.  In some (but not all) of these
 761                            cases, we need to tell libopcodes to skip the
 762                            constraint checking and the encoding for this
 763                            operand, so that the libopcodes can pick up the
 764                            right opcode before the operand is fixed-up.  This
 765                            flag should only be used during the
 766                            assembling/encoding.  */
 767   unsigned present:1;   /* Whether this operand is present in the assembly
 768                            line; not used during the disassembly.  */
 769 };
 770
 771 typedef struct aarch64_opnd_info aarch64_opnd_info;
 772
 773 /* Structure representing an instruction.
 774
 775    It is used during both the assembling and disassembling.  The assembler
 776    fills an aarch64_inst after a successful parsing and then passes it to the
 777    encoding routine to do the encoding.  During the disassembling, the
 778    disassembler calls the decoding routine to decode a binary instruction; on a
 779    successful return, such a structure will be filled with information of the
 780    instruction; then the disassembler uses the information to print out the
 781    instruction.  */
 782
 783 struct aarch64_inst
 784 {
 785   /* The value of the binary instruction.  */
 786   aarch64_insn value;
 787
 788   /* Corresponding opcode entry.  */
 789   const aarch64_opcode *opcode;
 790
 791   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 792   const aarch64_cond *cond;
 793
 794   /* Operands information.  */
 795   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 796 };
 797
 798 typedef struct aarch64_inst aarch64_inst;
 799 \f
 800 /* Diagnosis related declaration and interface.  */
 801
 802 /* Operand error kind enumerators.
 803
 804    AARCH64_OPDE_RECOVERABLE
 805      Less severe error found during the parsing, very possibly because that
 806      GAS has picked up a wrong instruction template for the parsing.
 807
 808    AARCH64_OPDE_SYNTAX_ERROR
 809      General syntax error; it can be either a user error, or simply because
 810      that GAS is trying a wrong instruction template.
 811
 812    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 813      Definitely a user syntax error.
 814
 815    AARCH64_OPDE_INVALID_VARIANT
 816      No syntax error, but the operands are not a valid combination, e.g.
 817      FMOV D0,S0
 818
 819    AARCH64_OPDE_OUT_OF_RANGE
 820      Error about some immediate value out of a valid range.
 821
 822    AARCH64_OPDE_UNALIGNED
 823      Error about some immediate value not properly aligned (i.e. not being a
 824      multiple times of a certain value).
 825
 826    AARCH64_OPDE_REG_LIST
 827      Error about the register list operand having unexpected number of
 828      registers.
 829
 830    AARCH64_OPDE_OTHER_ERROR
 831      Error of the highest severity and used for any severe issue that does not
 832      fall into any of the above categories.
 833
 834    The enumerators are only interesting to GAS.  They are declared here (in
 835    libopcodes) because that some errors are detected (and then notified to GAS)
 836    by libopcodes (rather than by GAS solely).
 837
 838    The first three errors are only deteced by GAS while the
 839    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 840    only libopcodes has the information about the valid variants of each
 841    instruction.
 842
 843    The enumerators have an increasing severity.  This is helpful when there are
 844    multiple instruction templates available for a given mnemonic name (e.g.
 845    FMOV); this mechanism will help choose the most suitable template from which
 846    the generated diagnostics can most closely describe the issues, if any.  */
 847
 848 enum aarch64_operand_error_kind
 849 {
 850   AARCH64_OPDE_NIL,
 851   AARCH64_OPDE_RECOVERABLE,
 852   AARCH64_OPDE_SYNTAX_ERROR,
 853   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 854   AARCH64_OPDE_INVALID_VARIANT,
 855   AARCH64_OPDE_OUT_OF_RANGE,
 856   AARCH64_OPDE_UNALIGNED,
 857   AARCH64_OPDE_REG_LIST,
 858   AARCH64_OPDE_OTHER_ERROR
 859 };
 860
 861 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 862 struct aarch64_operand_error
 863 {
 864   enum aarch64_operand_error_kind kind;
 865   int index;
 866   const char *error;
 867   int data[3];  /* Some data for extra information.  */
 868 };
 869
 870 typedef struct aarch64_operand_error aarch64_operand_error;
 871
 872 /* Encoding entrypoint.  */
 873
 874 extern int
 875 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 876                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 877                        aarch64_operand_error *);
 878
 879 extern const aarch64_opcode *
 880 aarch64_replace_opcode (struct aarch64_inst *,
 881                         const aarch64_opcode *);
 882
 883 /* Given the opcode enumerator OP, return the pointer to the corresponding
 884    opcode entry.  */
 885
 886 extern const aarch64_opcode *
 887 aarch64_get_opcode (enum aarch64_op);
 888
 889 /* Generate the string representation of an operand.  */
 890 extern void
 891 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 892                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 893
 894 /* Miscellaneous interface.  */
 895
 896 extern int
 897 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 898
 899 extern aarch64_opnd_qualifier_t
 900 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 901                                 const aarch64_opnd_qualifier_t, int);
 902
 903 extern int
 904 aarch64_num_of_operands (const aarch64_opcode *);
 905
 906 extern int
 907 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 908
 909 extern
 910 int aarch64_zero_register_p (const aarch64_opnd_info *);
 911
 912 /* Given an operand qualifier, return the expected data element size
 913    of a qualified operand.  */
 914 extern unsigned char
 915 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 916
 917 extern enum aarch64_operand_class
 918 aarch64_get_operand_class (enum aarch64_opnd);
 919
 920 extern const char *
 921 aarch64_get_operand_name (enum aarch64_opnd);
 922
 923 extern const char *
 924 aarch64_get_operand_desc (enum aarch64_opnd);
 925
 926 #ifdef DEBUG_AARCH64
 927 extern int debug_dump;
 928
 929 extern void
 930 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 931
 932 #define DEBUG_TRACE(M, ...)                                     \
 933   {                                                             \
 934     if (debug_dump)                                             \
 935       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 936   }
 937
 938 #define DEBUG_TRACE_IF(C, M, ...)                               \
 939   {                                                             \
 940     if (debug_dump && (C))                                      \
 941       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 942   }
 943 #else  /* !DEBUG_AARCH64 */
 944 #define DEBUG_TRACE(M, ...) ;
 945 #define DEBUG_TRACE_IF(C, M, ...) ;
 946 #endif /* DEBUG_AARCH64 */
 947
 948 #endif /* OPCODE_AARCH64_H */