include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2020 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit extensions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit extensions.  */
  39     return 8;
  40   /* Longer instructions not supported at the moment.  */
  41   return 2;
  42 }
  43
  44 static const char * const riscv_rm[8] =
  45 {
  46   "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
  47 };
  48
  49 static const char * const riscv_pred_succ[16] =
  50 {
  51   0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
  52   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
  53 };
  54
  55 #define RVC_JUMP_BITS 11
  56 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  57
  58 #define RVC_BRANCH_BITS 8
  59 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  60
  61 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  62 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  63
  64 #define EXTRACT_ITYPE_IMM(x) \
  65   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  66 #define EXTRACT_STYPE_IMM(x) \
  67   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  68 #define EXTRACT_SBTYPE_IMM(x) \
  69   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  70 #define EXTRACT_UTYPE_IMM(x) \
  71   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  72 #define EXTRACT_UJTYPE_IMM(x) \
  73   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  74 #define EXTRACT_RVC_IMM(x) \
  75   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  76 #define EXTRACT_RVC_LUI_IMM(x) \
  77   (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
  78 #define EXTRACT_RVC_SIMM3(x) \
  79   (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
  80 #define EXTRACT_RVC_UIMM8(x) \
  81   (RV_X(x, 5, 8))
  82 #define EXTRACT_RVC_ADDI4SPN_IMM(x) \
  83   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  84 #define EXTRACT_RVC_ADDI16SP_IMM(x) \
  85   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  86 #define EXTRACT_RVC_LW_IMM(x) \
  87   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  88 #define EXTRACT_RVC_LD_IMM(x) \
  89   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
  90 #define EXTRACT_RVC_LWSP_IMM(x) \
  91   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  92 #define EXTRACT_RVC_LDSP_IMM(x) \
  93   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  94 #define EXTRACT_RVC_SWSP_IMM(x) \
  95   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  96 #define EXTRACT_RVC_SDSP_IMM(x) \
  97   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  98 #define EXTRACT_RVC_B_IMM(x) \
  99   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
 100 #define EXTRACT_RVC_J_IMM(x) \
 101   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
 102
 103 #define ENCODE_ITYPE_IMM(x) \
 104   (RV_X(x, 0, 12) << 20)
 105 #define ENCODE_STYPE_IMM(x) \
 106   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 107 #define ENCODE_SBTYPE_IMM(x) \
 108   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 109 #define ENCODE_UTYPE_IMM(x) \
 110   (RV_X(x, 12, 20) << 12)
 111 #define ENCODE_UJTYPE_IMM(x) \
 112   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 113 #define ENCODE_RVC_IMM(x) \
 114   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 115 #define ENCODE_RVC_LUI_IMM(x) \
 116   ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
 117 #define ENCODE_RVC_SIMM3(x) \
 118   (RV_X(x, 0, 3) << 10)
 119 #define ENCODE_RVC_UIMM8(x) \
 120   (RV_X(x, 0, 8) << 5)
 121 #define ENCODE_RVC_ADDI4SPN_IMM(x) \
 122   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 123 #define ENCODE_RVC_ADDI16SP_IMM(x) \
 124   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 125 #define ENCODE_RVC_LW_IMM(x) \
 126   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 127 #define ENCODE_RVC_LD_IMM(x) \
 128   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 129 #define ENCODE_RVC_LWSP_IMM(x) \
 130   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 131 #define ENCODE_RVC_LDSP_IMM(x) \
 132   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 133 #define ENCODE_RVC_SWSP_IMM(x) \
 134   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 135 #define ENCODE_RVC_SDSP_IMM(x) \
 136   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 137 #define ENCODE_RVC_B_IMM(x) \
 138   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 139 #define ENCODE_RVC_J_IMM(x) \
 140   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 141
 142 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 143 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 144 #define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
 145 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 146 #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
 147 #define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
 148 #define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
 149 #define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
 150 #define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
 151 #define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
 152 #define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
 153 #define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
 154 #define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
 155 #define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
 156 #define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
 157 #define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
 158 #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
 159 #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
 160 #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
 161
 162 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 163   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 164 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 165   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 166 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 167   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 168 #define RISCV_SBTYPE(insn, rs1, rs2, target) \
 169   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
 170 #define RISCV_UTYPE(insn, rd, bigimm) \
 171   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 172 #define RISCV_UJTYPE(insn, rd, target) \
 173   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
 174
 175 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 176 #define RVC_NOP MATCH_C_ADDI
 177
 178 #define RISCV_CONST_HIGH_PART(VALUE) \
 179   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 180 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 181 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 182 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 183
 184 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 185 #define RISCV_JUMP_ALIGN_BITS 1
 186 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 187 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 188
 189 #define RISCV_IMM_BITS 12
 190 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 191 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 192 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 193 #define RISCV_RVC_IMM_REACH (1LL << 6)
 194 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 195 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 196 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 197 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 198
 199 /* RV fields.  */
 200
 201 #define OP_MASK_OP              0x7f
 202 #define OP_SH_OP                0
 203 #define OP_MASK_RS2             0x1f
 204 #define OP_SH_RS2               20
 205 #define OP_MASK_RS1             0x1f
 206 #define OP_SH_RS1               15
 207 #define OP_MASK_RS3             0x1f
 208 #define OP_SH_RS3               27
 209 #define OP_MASK_RD              0x1f
 210 #define OP_SH_RD                7
 211 #define OP_MASK_SHAMT           0x3f
 212 #define OP_SH_SHAMT             20
 213 #define OP_MASK_SHAMTW          0x1f
 214 #define OP_SH_SHAMTW            20
 215 #define OP_MASK_RM              0x7
 216 #define OP_SH_RM                12
 217 #define OP_MASK_PRED            0xf
 218 #define OP_SH_PRED              24
 219 #define OP_MASK_SUCC            0xf
 220 #define OP_SH_SUCC              20
 221 #define OP_MASK_AQ              0x1
 222 #define OP_SH_AQ                26
 223 #define OP_MASK_RL              0x1
 224 #define OP_SH_RL                25
 225
 226 #define OP_MASK_CUSTOM_IMM      0x7f
 227 #define OP_SH_CUSTOM_IMM        25
 228 #define OP_MASK_CSR             0xfff
 229 #define OP_SH_CSR               20
 230
 231 #define OP_MASK_FUNCT3         0x7
 232 #define OP_SH_FUNCT3           12
 233 #define OP_MASK_FUNCT7         0x7f
 234 #define OP_SH_FUNCT7           25
 235 #define OP_MASK_FUNCT2         0x3
 236 #define OP_SH_FUNCT2           25
 237
 238 /* RVC fields.  */
 239
 240 #define OP_MASK_OP2            0x3
 241 #define OP_SH_OP2              0
 242
 243 #define OP_MASK_CRS2 0x1f
 244 #define OP_SH_CRS2 2
 245 #define OP_MASK_CRS1S 0x7
 246 #define OP_SH_CRS1S 7
 247 #define OP_MASK_CRS2S 0x7
 248 #define OP_SH_CRS2S 2
 249
 250 #define OP_MASK_CFUNCT6                0x3f
 251 #define OP_SH_CFUNCT6          10
 252 #define OP_MASK_CFUNCT4                0xf
 253 #define OP_SH_CFUNCT4          12
 254 #define OP_MASK_CFUNCT3                0x7
 255 #define OP_SH_CFUNCT3          13
 256 #define OP_MASK_CFUNCT2                0x3
 257 #define OP_SH_CFUNCT2          5
 258
 259 /* ABI names for selected x-registers.  */
 260
 261 #define X_RA 1
 262 #define X_SP 2
 263 #define X_GP 3
 264 #define X_TP 4
 265 #define X_T0 5
 266 #define X_T1 6
 267 #define X_T2 7
 268 #define X_T3 28
 269
 270 #define NGPR 32
 271 #define NFPR 32
 272
 273 /* These fake label defines are use by both the assembler, and
 274    libopcodes.  The assembler uses this when it needs to generate a fake
 275    label, and libopcodes uses it to hide the fake labels in its output.  */
 276 #define RISCV_FAKE_LABEL_NAME ".L0 "
 277 #define RISCV_FAKE_LABEL_CHAR ' '
 278
 279 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 280    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 281 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 282   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 283               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 284
 285 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 286    SHIFT places.  */
 287 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 288   (((STRUCT) >> (SHIFT)) & (MASK))
 289
 290 /* Extract the operand given by FIELD from integer INSN.  */
 291 #define EXTRACT_OPERAND(FIELD, INSN) \
 292   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 293
 294 /* The maximal number of subset can be required. */
 295 #define MAX_SUBSET_NUM 4
 296
 297 /* All RISC-V instructions belong to at least one of these classes.  */
 298
 299 enum riscv_insn_class
 300   {
 301    INSN_CLASS_NONE,
 302
 303    INSN_CLASS_I,
 304    INSN_CLASS_C,
 305    INSN_CLASS_A,
 306    INSN_CLASS_M,
 307    INSN_CLASS_F,
 308    INSN_CLASS_D,
 309    INSN_CLASS_D_AND_C,
 310    INSN_CLASS_F_AND_C,
 311    INSN_CLASS_Q,
 312   };
 313
 314 /* This structure holds information for a particular instruction.  */
 315
 316 struct riscv_opcode
 317 {
 318   /* The name of the instruction.  */
 319   const char *name;
 320   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 321   unsigned xlen_requirement;
 322   /* Class to which this instruction belongs.  Used to decide whether or
 323      not this instruction is legal in the current -march context.  */
 324   enum riscv_insn_class insn_class;
 325   /* A string describing the arguments for this instruction.  */
 326   const char *args;
 327   /* The basic opcode for the instruction.  When assembling, this
 328      opcode is modified by the arguments to produce the actual opcode
 329      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 330   insn_t match;
 331   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 332      relevant portions of the opcode when disassembling.  If the
 333      actual opcode anded with the match field equals the opcode field,
 334      then we have found the correct instruction.  If pinfo is
 335      INSN_MACRO, then this field is the macro identifier.  */
 336   insn_t mask;
 337   /* A function to determine if a word corresponds to this instruction.
 338      Usually, this computes ((word & mask) == match).  */
 339   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 340   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 341      of bits describing the instruction, notably any relevant hazard
 342      information.  */
 343   unsigned long pinfo;
 344 };
 345
 346 /* The current supported ISA spec versions.  */
 347
 348 enum riscv_isa_spec_class
 349 {
 350   ISA_SPEC_CLASS_NONE,
 351
 352   ISA_SPEC_CLASS_2P2,
 353   ISA_SPEC_CLASS_20190608,
 354   ISA_SPEC_CLASS_20191213
 355 };
 356
 357 /* This structure holds version information for specific ISA.  */
 358
 359 struct riscv_ext_version
 360 {
 361   const char *name;
 362   enum riscv_isa_spec_class isa_spec_class;
 363   unsigned int major_version;
 364   unsigned int minor_version;
 365 };
 366
 367 /* All RISC-V CSR belong to one of these classes.  */
 368
 369 enum riscv_csr_class
 370 {
 371   CSR_CLASS_NONE,
 372
 373   CSR_CLASS_I,
 374   CSR_CLASS_I_32,      /* rv32 only */
 375   CSR_CLASS_F,         /* f-ext only */
 376 };
 377
 378 /* The current supported privilege spec versions.  */
 379
 380 enum riscv_priv_spec_class
 381 {
 382   PRIV_SPEC_CLASS_NONE,
 383
 384   PRIV_SPEC_CLASS_1P9,
 385   PRIV_SPEC_CLASS_1P9P1,
 386   PRIV_SPEC_CLASS_1P10,
 387   PRIV_SPEC_CLASS_1P11,
 388   PRIV_SPEC_CLASS_DRAFT
 389 };
 390
 391 /* This structure holds all restricted conditions for a CSR.  */
 392
 393 struct riscv_csr_extra
 394 {
 395   /* Class to which this CSR belongs.  Used to decide whether or
 396      not this CSR is legal in the current -march context.  */
 397   enum riscv_csr_class csr_class;
 398
 399   /* CSR may have differnet numbers in the previous priv spec.  */
 400   unsigned address;
 401
 402   /* Record the CSR is defined/valid in which versions.  */
 403   enum riscv_priv_spec_class define_version;
 404
 405   /* Record the CSR is aborted/invalid from which versions.  If it isn't
 406      aborted in the current version, then it should be CSR_CLASS_VDRAFT.  */
 407   enum riscv_priv_spec_class abort_version;
 408
 409   /* The CSR may have more than one setting.  */
 410   struct riscv_csr_extra *next;
 411 };
 412
 413 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 414 #define INSN_ALIAS              0x00000001
 415
 416 /* These are for setting insn_info fields.
 417
 418    Nonbranch is the default.  Noninsn is used only if there is no match.
 419    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 420    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 421 #define INSN_TYPE               0x0000000e
 422
 423 /* Instruction is an unconditional branch.  */
 424 #define INSN_BRANCH             0x00000002
 425 /* Instruction is a conditional branch.  */
 426 #define INSN_CONDBRANCH         0x00000004
 427 /* Instruction is a jump to subroutine.  */
 428 #define INSN_JSR                0x00000006
 429 /* Instruction is a data reference.  */
 430 #define INSN_DREF               0x00000008
 431
 432 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 433 #define INSN_DATA_SIZE          0x00000070
 434 #define INSN_DATA_SIZE_SHIFT    4
 435 #define INSN_1_BYTE             0x00000010
 436 #define INSN_2_BYTE             0x00000020
 437 #define INSN_4_BYTE             0x00000030
 438 #define INSN_8_BYTE             0x00000040
 439 #define INSN_16_BYTE            0x00000050
 440
 441 /* Instruction is actually a macro.  It should be ignored by the
 442    disassembler, and requires special treatment by the assembler.  */
 443 #define INSN_MACRO              0xffffffff
 444
 445 /* This is a list of macro expanded instructions.
 446
 447    _I appended means immediate
 448    _A appended means address
 449    _AB appended means address with base register
 450    _D appended means 64 bit floating point constant
 451    _S appended means 32 bit floating point constant.  */
 452
 453 enum
 454 {
 455   M_LA,
 456   M_LLA,
 457   M_LA_TLS_GD,
 458   M_LA_TLS_IE,
 459   M_LB,
 460   M_LBU,
 461   M_LH,
 462   M_LHU,
 463   M_LW,
 464   M_LWU,
 465   M_LD,
 466   M_SB,
 467   M_SH,
 468   M_SW,
 469   M_SD,
 470   M_FLW,
 471   M_FLD,
 472   M_FLQ,
 473   M_FSW,
 474   M_FSD,
 475   M_FSQ,
 476   M_CALL,
 477   M_J,
 478   M_LI,
 479   M_NUM_MACROS
 480 };
 481
 482
 483 extern const char * const riscv_gpr_names_numeric[NGPR];
 484 extern const char * const riscv_gpr_names_abi[NGPR];
 485 extern const char * const riscv_fpr_names_numeric[NFPR];
 486 extern const char * const riscv_fpr_names_abi[NFPR];
 487
 488 extern const struct riscv_opcode riscv_opcodes[];
 489 extern const struct riscv_opcode riscv_insn_types[];
 490 extern const struct riscv_ext_version riscv_ext_version_table[];
 491
 492 extern int
 493 riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class *);
 494 extern int
 495 riscv_get_priv_spec_class (const char *, enum riscv_priv_spec_class *);
 496 extern const char *
 497 riscv_get_priv_spec_name (enum riscv_priv_spec_class);
 498
 499 #endif /* _RISCV_H_ */