include/opcode/tic80.h

   1 /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
   2    Copyright (C) 1996-2019 Free Software Foundation, Inc.
   3    Written by Fred Fish (fnf@cygnus.com), Cygnus Support
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef TIC80_H
  23 #define TIC80_H
  24
  25 /* The opcode table is an array of struct tic80_opcode.  */
  26
  27 struct tic80_opcode
  28 {
  29   /* The opcode name.  */
  30
  31   const char *name;
  32
  33   /* The opcode itself.  Those bits which will be filled in with operands
  34      are zeroes.  */
  35
  36   unsigned long opcode;
  37
  38   /* The opcode mask.  This is used by the disassembler.  This is a mask
  39      containing ones indicating those bits which must match the opcode
  40      field, and zeroes indicating those bits which need not match (and are
  41      presumably filled in by operands).  */
  42
  43   unsigned long mask;
  44
  45   /* Special purpose flags for this opcode. */
  46
  47   unsigned char flags;
  48
  49   /* An array of operand codes.  Each code is an index into the operand
  50      table.  They appear in the order which the operands must appear in
  51      assembly code, and are terminated by a zero.  FIXME: Adjust size to
  52      match actual requirements when TIc80 support is complete */
  53
  54   unsigned char operands[8];
  55 };
  56
  57 /* The table itself is sorted by major opcode number, and is otherwise in
  58    the order in which the disassembler should consider instructions.
  59    FIXME: This isn't currently true. */
  60
  61 extern const struct tic80_opcode tic80_opcodes[];
  62 extern const int tic80_num_opcodes;
  63
  64 \f
  65 /* The operands table is an array of struct tic80_operand.  */
  66
  67 struct tic80_operand
  68 {
  69   /* The number of bits in the operand.  */
  70
  71   int bits;
  72
  73   /* How far the operand is left shifted in the instruction.  */
  74
  75   int shift;
  76
  77   /* Insertion function.  This is used by the assembler.  To insert an
  78      operand value into an instruction, check this field.
  79
  80      If it is NULL, execute
  81          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  82      (i is the instruction which we are filling in, o is a pointer to
  83      this structure, and op is the opcode value; this assumes twos
  84      complement arithmetic).
  85
  86      If this field is not NULL, then simply call it with the
  87      instruction and the operand value.  It will return the new value
  88      of the instruction.  If the ERRMSG argument is not NULL, then if
  89      the operand value is illegal, *ERRMSG will be set to a warning
  90      string (the operand will be inserted in any case).  If the
  91      operand value is legal, *ERRMSG will be unchanged (most operands
  92      can accept any value).  */
  93
  94   unsigned long (*insert)
  95     (unsigned long instruction, long op, const char **errmsg);
  96
  97   /* Extraction function.  This is used by the disassembler.  To
  98      extract this operand type from an instruction, check this field.
  99
 100      If it is NULL, compute
 101          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 102          if ((o->flags & TIC80_OPERAND_SIGNED) != 0
 103              && (op & (1 << (o->bits - 1))) != 0)
 104            op -= 1 << o->bits;
 105      (i is the instruction, o is a pointer to this structure, and op
 106      is the result; this assumes twos complement arithmetic).
 107
 108      If this field is not NULL, then simply call it with the
 109      instruction value.  It will return the value of the operand.  If
 110      the INVALID argument is not NULL, *INVALID will be set to
 111      non-zero if this operand type can not actually be extracted from
 112      this operand (i.e., the instruction does not match).  If the
 113      operand is valid, *INVALID will not be changed.  */
 114
 115   long (*extract) (unsigned long instruction, int *invalid);
 116
 117   /* One bit syntax flags.  */
 118
 119   unsigned long flags;
 120 };
 121
 122 /* Elements in the table are retrieved by indexing with values from
 123    the operands field of the tic80_opcodes table.  */
 124
 125 extern const struct tic80_operand tic80_operands[];
 126
 127 \f
 128 /* Values defined for the flags field of a struct tic80_operand.
 129
 130    Note that flags for all predefined symbols, such as the general purpose
 131    registers (ex: r10), control registers (ex: FPST), condition codes (ex:
 132    eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
 133    or'd into an int where the lower bits contain the actual numeric value
 134    that correponds to this predefined symbol.  This way a single int can
 135    contain both the value of the symbol and it's type.
 136  */
 137
 138 /* This operand must be an even register number.  Floating point numbers
 139    for example are stored in even/odd register pairs. */
 140
 141 #define TIC80_OPERAND_EVEN      (1u << 0)
 142
 143 /* This operand must be an odd register number and must be one greater than
 144    the register number of the previous operand.  I.E. the second register in
 145    an even/odd register pair. */
 146
 147 #define TIC80_OPERAND_ODD       (1u << 1)
 148
 149 /* This operand takes signed values.  */
 150
 151 #define TIC80_OPERAND_SIGNED    (1u << 2)
 152
 153 /* This operand may be either a predefined constant name or a numeric value.
 154    An example would be a condition code like "eq0.b" which has the numeric
 155    value 0x2. */
 156
 157 #define TIC80_OPERAND_NUM       (1u << 3)
 158
 159 /* This operand should be wrapped in parentheses rather than separated
 160    from the previous one by a comma.  This is used for various
 161    instructions, like the load and store instructions, which want
 162    their operands to look like "displacement(reg)" */
 163
 164 #define TIC80_OPERAND_PARENS    (1u << 4)
 165
 166 /* This operand is a PC relative branch offset.  The disassembler prints
 167    these symbolically if possible.  Note that the offsets are taken as word
 168    offsets. */
 169
 170 #define TIC80_OPERAND_PCREL     (1u << 5)
 171
 172 /* This flag is a hint to the disassembler for using hex as the prefered
 173    printing format, even for small positive or negative immediate values.
 174    Normally values in the range -999 to 999 are printed as signed decimal
 175    values and other values are printed in hex. */
 176
 177 #define TIC80_OPERAND_BITFIELD  (1u << 6)
 178
 179 /* This operand may have a ":m" modifier specified by bit 17 in a short
 180    immediate form instruction. */
 181
 182 #define TIC80_OPERAND_M_SI      (1u << 7)
 183
 184 /* This operand may have a ":m" modifier specified by bit 15 in a long
 185    immediate or register form instruction. */
 186
 187 #define TIC80_OPERAND_M_LI      (1u << 8)
 188
 189 /* This operand may have a ":s" modifier specified in bit 11 in a long
 190    immediate or register form instruction. */
 191
 192 #define TIC80_OPERAND_SCALED    (1u << 9)
 193
 194 /* This operand is a floating point value */
 195
 196 #define TIC80_OPERAND_FLOAT     (1u << 10)
 197
 198 /* This operand is an byte offset from a base relocation. The lower
 199  two bits of the final relocated address are ignored when the value is
 200  written to the program counter. */
 201
 202 #define TIC80_OPERAND_BASEREL   (1u << 11)
 203
 204 /* This operand is an "endmask" field for a shift instruction.
 205    It is treated special in that it can have values of 0-32,
 206    where 0 and 32 result in the same instruction.  The assembler
 207    must be able to accept both endmask values.  This disassembler
 208    has no way of knowing from the instruction which value was
 209    given at assembly time, so it just uses '0'. */
 210
 211 #define TIC80_OPERAND_ENDMASK   (1u << 12)
 212
 213 /* This operand is one of the 32 general purpose registers.
 214    The disassembler prints these with a leading 'r'. */
 215
 216 #define TIC80_OPERAND_GPR       (1u << 27)
 217
 218 /* This operand is a floating point accumulator register.
 219    The disassembler prints these with a leading 'a'. */
 220
 221 #define TIC80_OPERAND_FPA       (1u << 28)
 222
 223 /* This operand is a control register number, either numeric or
 224    symbolic (like "EIF", "EPC", etc).
 225    The disassembler prints these symbolically. */
 226
 227 #define TIC80_OPERAND_CR        (1u << 29)
 228
 229 /* This operand is a condition code, either numeric or
 230    symbolic (like "eq0.b", "ne0.w", etc).
 231    The disassembler prints these symbolically. */
 232
 233 #define TIC80_OPERAND_CC        (1u << 30)
 234
 235 /* This operand is a bit number, either numeric or
 236    symbolic (like "eq.b", "or.f", etc).
 237    The disassembler prints these symbolically.
 238    Note that they appear in the instruction in 1's complement relative
 239    to the values given in the manual. */
 240
 241 #define TIC80_OPERAND_BITNUM    (1u << 31)
 242
 243 /* This mask is used to strip operand bits from an int that contains
 244    both operand bits and a numeric value in the lsbs. */
 245
 246 #define TIC80_OPERAND_MASK      (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
 247
 248 \f
 249 /* Flag bits for the struct tic80_opcode flags field. */
 250
 251 #define TIC80_VECTOR            01      /* Is a vector instruction */
 252 #define TIC80_NO_R0_DEST        02      /* Register r0 cannot be a destination register */
 253
 254 \f
 255 /* The opcodes library contains a table that allows translation from predefined
 256    symbol names to numeric values, and vice versa. */
 257
 258 /* Structure to hold information about predefined symbols.  */
 259
 260 struct predefined_symbol
 261 {
 262   char *name;           /* name to recognize */
 263   int value;
 264 };
 265
 266 #define PDS_NAME(pdsp) ((pdsp) -> name)
 267 #define PDS_VALUE(pdsp) ((pdsp) -> value)
 268
 269 /* Translation array.  */
 270 extern const struct predefined_symbol tic80_predefined_symbols[];
 271 /* How many members in the array.  */
 272 extern const int tic80_num_predefined_symbols;
 273
 274 /* Translate value to symbolic name.  */
 275 const char *tic80_value_to_symbol (int val, int class);
 276
 277 /* Translate symbolic name to value.  */
 278 int tic80_symbol_to_value (char *name, int class);
 279
 280 const struct predefined_symbol *tic80_next_predefined_symbol
 281   (const struct predefined_symbol *);
 282
 283 #endif /* TIC80_H */