opcodes/ChangeLog-2011

   1 2011-12-15  Nick Clifton  <nickc@redhat.com>
   2
   3         * cgen-asm.c (cgen_parse_signed_integer): Add code to handle the
   4         sign extension of negative values on a 64-bit host.
   5         * frv-asm.c: Regenerate.
   6
   7 2011-12-13  Alan Modra  <amodra@gmail.com>
   8
   9         * ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.
  10         (valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from..
  11         (valid_bo): ..here.  When disassembling, accept either 'y' or 'at'
  12         type encoding on second pass.
  13         (powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
  14         POWER4.
  15         * ppc-dis.c (print_insn_powerpc): Delete dialect_orig.  Instead
  16         ignore deprecated on second pass.
  17
  18 2011-12-08  Andrew Pinski  <apinski@cavium.com>
  19
  20         * mips-opc.c (mips_builtin_opcodes): Add "pause".
  21
  22 2011-12-08  Andrew Pinski  <apinski@cavium.com>
  23             Adam Nemet  <anemet@caviumnetworks.com>
  24
  25         * mips-dis.c (mips_arch_choices): Add Octeon2.
  26         For "octeon+", just include OcteonP for the insn.
  27         * mips-opc.c (IOCT): Include Octeon2.
  28         (IOCTP): Include Octeon2.
  29         (IOCT2): New macro.
  30         (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
  31         "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
  32         Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
  33         loads are, and add IOCT2 to them.
  34         Add "lbx" and "lhux".
  35         Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
  36         "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
  37         Add "zcb" and "zcbt".
  38
  39 2011-11-29  Andrew Pinski  <apinski@cavium.com>
  40
  41         * mips-dis.c (mips_arch_choices): Add Octeon+.
  42         * mips-opc.c (IOCT): Include Octeon+.
  43         (IOCTP): New macro.
  44         (mips_builtin_opcodes): Add "saa" and "saad".
  45
  46 2011-11-25  Pierre Muller  <muller@ics.u-strasbg.fr>
  47
  48         * mips-dis.c (print_insn_micromips): Rename local variable iprintf
  49         to infprintf to avoid shadow warning.
  50
  51 2011-11-25  Nick Clifton  <nickc@redhat.com>
  52
  53         * po/it.po: Updated Italian translation.
  54
  55 2011-11-16  Maciej W. Rozycki  <macro@codesourcery.com>
  56
  57         * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
  58         for "alnv.ps".
  59
  60 2011-11-02  Nick Clifton  <nickc@redhat.com>
  61
  62         * po/it.po: New Italian translation.
  63         * configure.in (ALL_LINGUAS): Add it.
  64         * configure: Regenerate.
  65         * po/opcodes.pot: Regenerate.
  66
  67 2011-11-01  DJ Delorie  <dj@redhat.com>
  68
  69         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
  70         rl78-dis.c.
  71         (MAINTAINERCLEANFILES): Add rl78-decode.c.
  72         (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
  73         * Makefile.in: Regenerate.
  74         * configure.in: Add bfd_rl78_arch case.
  75         * configure: Regenerate.
  76         * disassemble.c: Define ARCH_rl78.
  77         (disassembler): Add ARCH_rl78 case.
  78         * rl78-decode.c: New file.
  79         * rl78-decode.opc: New file.
  80         * rl78-dis.c: New file.
  81
  82 2011-10-27  Peter Bergner  <bergner@vnet.ibm.com>
  83
  84         * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
  85         dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
  86         diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
  87         instructions.
  88
  89 2011-10-26  Nick Clifton  <nickc@redhat.com>
  90
  91         PR binutils/13348
  92         * i386-dis.c (print_insn): Fix testing of array subscript.
  93
  94 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
  95
  96         * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
  97         * epiphany-asm.c, epiphany-opc.h: Regenerate.
  98
  99 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
 100
 101         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
 102         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
 103         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
 104         (CLEANFILES): Add stamp-epiphany.
 105         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
 106         (stamp-epiphany): New rule.
 107         * configure.in: Handle bfd_epiphany_arch.
 108         * disassemble.c (ARCH_epiphany): Define.
 109         (disassembler): Handle bfd_arch_epiphany.
 110         * epiphany-asm.c: New file.
 111         * epiphany-desc.c: New file.
 112         * epiphany-desc.h: New file.
 113         * epiphany-dis.c: New file.
 114         * epiphany-ibld.c: New file.
 115         * epiphany-opc.c: New file.
 116         * epiphany-opc.h: New file.
 117         * Makefile.in: Regenerate.
 118         * configure: Regenerate.
 119         * po/POTFILES.in: Regenerate.
 120         * po/opcodes.pot: Regenerate.
 121
 122 2011-10-24  Julian Brown  <julian@codesourcery.com>
 123
 124         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
 125
 126 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
 127
 128         * s390-opc.txt: Add CPUMF instructions.
 129
 130 2011-10-18  Jie Zhang  <jie@codesourcery.com>
 131             Julian Brown  <julian@codesourcery.com>
 132
 133         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
 134
 135 2011-10-10  Nick Clifton  <nickc@redhat.com>
 136
 137         * po/es.po: Updated Spanish translation.
 138         * po/fi.po: Updated Finnish translation.
 139
 140 2011-09-28  Jan Beulich  <jbeulich@suse.com>
 141
 142         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
 143         RBX): New.
 144         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
 145         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
 146         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
 147         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
 148         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
 149         on DFP quad instructions.
 150
 151 2011-09-27  David S. Miller  <davem@davemloft.net>
 152
 153         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
 154         to a float instead of an integer register.
 155
 156 2011-09-26  David S. Miller  <davem@davemloft.net>
 157
 158         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
 159         instructions.
 160
 161 2011-09-21  David S. Miller  <davem@davemloft.net>
 162
 163         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
 164         bits.  Fix "fchksm16" mnemonic.
 165
 166 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
 167
 168         The changes below bring 'mov' and 'ticc' instructions into line
 169         with the V8 SPARC Architecture Manual.
 170         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
 171         * sparc-opc.c (sparc_opcodes): Add alias entries for
 172         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
 173         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
 174         * sparc-opc.c (sparc_opcodes): Move/Change entries for
 175         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
 176         and 'mov imm,%tbr'.
 177         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
 178         mov aliases.
 179
 180         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
 181         This has been reported as being accepted by the Sun assmebler.
 182
 183 2011-09-08  David S. Miller  <davem@davemloft.net>
 184
 185         * sparc-opc.c (pdistn): Destination is integer not float register.
 186
 187 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
 188
 189         PR gas/13145
 190         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
 191
 192 2011-08-26  Nick Clifton  <nickc@redhat.com>
 193
 194         * po/es.po: Updated Spanish translation.
 195
 196 2011-08-22  Nick Clifton  <nickc@redhat.com>
 197
 198         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 199         directory.
 200         (stamp-frv): Use CPUDIR.
 201         (stamp-iq2000): Likewise.
 202         (stamp-lm32): Likewise.
 203         (stamp-m32c): Likewise.
 204         (stamp-mt): Likewise.
 205         (stamp-xc16x): Likewise.
 206         * Makefile.in: Regenerate.
 207
 208 2011-08-09  Chao-ying Fu  <fu@mips.com>
 209             Maciej W. Rozycki  <macro@codesourcery.com>
 210
 211         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 212         and "mips64r2".
 213         (print_insn_args, print_insn_micromips): Handle MCU.
 214         * micromips-opc.c (MC): New macro.
 215         (micromips_opcodes): Add "aclr", "aset" and "iret".
 216         * mips-opc.c (MC): New macro.
 217         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 218
 219 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 220
 221         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 222         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 223         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 224         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 225         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 226         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 227         (WR_s): Update macro.
 228         (micromips_opcodes): Update register use flags of: "addiu",
 229         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 230         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 231         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 232         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 233         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 234         "swm" and "xor" instructions.
 235
 236 2011-08-05  David S. Miller  <davem@davemloft.net>
 237
 238         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 239         (X_RS3): New macro.
 240         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 241         Accept %asr numbers below 28.
 242         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 243         instructions.
 244
 245 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 246
 247         * i386-dis.c (xop_table): Remove spurious bextr insn.
 248
 249 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         PR ld/13048
 252         * i386-dis.c (print_insn): Optimize info->mach check.
 253
 254 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 255
 256         PR gas/13046
 257         * i386-opc.tbl: Add Disp32S to 64bit call.
 258         * i386-tbl.h: Regenerated.
 259
 260 2011-07-24  Chao-ying Fu  <fu@mips.com>
 261             Maciej W. Rozycki  <macro@codesourcery.com>
 262
 263         * micromips-opc.c: New file.
 264         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 265         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 266         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 267         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 268         (micromips_to_32_reg_q_map): Likewise.
 269         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 270         (micromips_ase): New variable.
 271         (is_micromips): New function.
 272         (set_default_mips_dis_options): Handle microMIPS ASE.
 273         (print_insn_micromips): New function.
 274         (is_compressed_mode_p): Likewise.
 275         (_print_insn_mips): Handle microMIPS instructions.
 276         * Makefile.am (CFILES): Add micromips-opc.c.
 277         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 278         * Makefile.in: Regenerate.
 279         * configure: Regenerate.
 280
 281         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 282         (micromips_to_32_reg_i_map): Likewise.
 283         (micromips_to_32_reg_m_map): Likewise.
 284         (micromips_to_32_reg_n_map): New macro.
 285
 286 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 287
 288         * mips-opc.c (NODS): New macro.
 289         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 290         (DSP_VOLA): Likewise.
 291         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 292         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 293         place of TRAP for "wait", "waiti" and "yield".
 294         * mips16-opc.c (NODS): New macro.
 295         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 296         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 297         "restore" and "save".
 298
 299 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 300
 301         * configure.in: Handle bfd_k1om_arch.
 302         * configure: Regenerated.
 303
 304         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 305
 306         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 307         bfd_mach_k1om_intel_syntax.
 308
 309         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 310         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 311         (cpu_flags): Add CpuK1OM.
 312
 313         * i386-opc.h (CpuK1OM): New.
 314         (i386_cpu_flags): Add cpuk1om.
 315
 316         * i386-init.h: Regenerated.
 317         * i386-tbl.h: Likewise.
 318
 319 2011-07-12  Nick Clifton  <nickc@redhat.com>
 320
 321         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 322         accidental change.
 323
 324 2011-07-01  Nick Clifton  <nickc@redhat.com>
 325
 326         PR binutils/12329
 327         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 328         insns using post-increment addressing.
 329
 330 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 331
 332         * i386-dis.c (vex_len_table): Update rorxS.
 333
 334 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         AVX Programming Reference (June, 2011)
 337         * i386-dis.c (vex_len_table): Correct rorxS.
 338
 339         * i386-opc.tbl: Correct rorx.
 340         * i386-tbl.h: Regenerated.
 341
 342 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 345         * tilepro-opc.c (find_opcode): Likewise.
 346
 347 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 348
 349         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 350
 351 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 352
 353         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 354         PREFIX_VEX_0F388E.
 355
 356 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 357
 358         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 359         (MOSTLYCLEANFILES): ... here.
 360         * Makefile.in: Regenerate.
 361
 362 2011-06-14  Alan Modra  <amodra@gmail.com>
 363
 364         * Makefile.in: Regenerate.
 365
 366 2011-06-13  Walter Lee  <walt@tilera.com>
 367
 368         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 369         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 370         * Makefile.in: Regenerate.
 371         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 372         * configure: Regenerate.
 373         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 374         * po/POTFILES.in: Regenerate.
 375         * tilegx-dis.c: New file.
 376         * tilegx-opc.c: New file.
 377         * tilepro-dis.c: New file.
 378         * tilepro-opc.c: New file.
 379
 380 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         AVX Programming Reference (June, 2011)
 383         * i386-dis.c (XMGatherQ): New.
 384         * i386-dis.c (EXxmm_mb): New.
 385         (EXxmm_mb): Likewise.
 386         (EXxmm_mw): Likewise.
 387         (EXxmm_md): Likewise.
 388         (EXxmm_mq): Likewise.
 389         (EXxmmdw): Likewise.
 390         (EXxmmqd): Likewise.
 391         (VexGatherQ): Likewise.
 392         (MVexVSIBDWpX): Likewise.
 393         (MVexVSIBQWpX): Likewise.
 394         (xmm_mb_mode): Likewise.
 395         (xmm_mw_mode): Likewise.
 396         (xmm_md_mode): Likewise.
 397         (xmm_mq_mode): Likewise.
 398         (xmmdw_mode): Likewise.
 399         (xmmqd_mode): Likewise.
 400         (ymmxmm_mode): Likewise.
 401         (vex_vsib_d_w_dq_mode): Likewise.
 402         (vex_vsib_q_w_dq_mode): Likewise.
 403         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 404         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 405         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 406         (PREFIX_0F3882): Likewise.
 407         (PREFIX_VEX_0F3816): Likewise.
 408         (PREFIX_VEX_0F3836): Likewise.
 409         (PREFIX_VEX_0F3845): Likewise.
 410         (PREFIX_VEX_0F3846): Likewise.
 411         (PREFIX_VEX_0F3847): Likewise.
 412         (PREFIX_VEX_0F3858): Likewise.
 413         (PREFIX_VEX_0F3859): Likewise.
 414         (PREFIX_VEX_0F385A): Likewise.
 415         (PREFIX_VEX_0F3878): Likewise.
 416         (PREFIX_VEX_0F3879): Likewise.
 417         (PREFIX_VEX_0F388C): Likewise.
 418         (PREFIX_VEX_0F388E): Likewise.
 419         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 420         (PREFIX_VEX_0F38F5): Likewise.
 421         (PREFIX_VEX_0F38F6): Likewise.
 422         (PREFIX_VEX_0F3A00): Likewise.
 423         (PREFIX_VEX_0F3A01): Likewise.
 424         (PREFIX_VEX_0F3A02): Likewise.
 425         (PREFIX_VEX_0F3A38): Likewise.
 426         (PREFIX_VEX_0F3A39): Likewise.
 427         (PREFIX_VEX_0F3A46): Likewise.
 428         (PREFIX_VEX_0F3AF0): Likewise.
 429         (VEX_LEN_0F3816_P_2): Likewise.
 430         (VEX_LEN_0F3819_P_2): Likewise.
 431         (VEX_LEN_0F3836_P_2): Likewise.
 432         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 433         (VEX_LEN_0F38F5_P_0): Likewise.
 434         (VEX_LEN_0F38F5_P_1): Likewise.
 435         (VEX_LEN_0F38F5_P_3): Likewise.
 436         (VEX_LEN_0F38F6_P_3): Likewise.
 437         (VEX_LEN_0F38F7_P_1): Likewise.
 438         (VEX_LEN_0F38F7_P_2): Likewise.
 439         (VEX_LEN_0F38F7_P_3): Likewise.
 440         (VEX_LEN_0F3A00_P_2): Likewise.
 441         (VEX_LEN_0F3A01_P_2): Likewise.
 442         (VEX_LEN_0F3A38_P_2): Likewise.
 443         (VEX_LEN_0F3A39_P_2): Likewise.
 444         (VEX_LEN_0F3A46_P_2): Likewise.
 445         (VEX_LEN_0F3AF0_P_3): Likewise.
 446         (VEX_W_0F3816_P_2): Likewise.
 447         (VEX_W_0F3818_P_2): Likewise.
 448         (VEX_W_0F3819_P_2): Likewise.
 449         (VEX_W_0F3836_P_2): Likewise.
 450         (VEX_W_0F3846_P_2): Likewise.
 451         (VEX_W_0F3858_P_2): Likewise.
 452         (VEX_W_0F3859_P_2): Likewise.
 453         (VEX_W_0F385A_P_2_M_0): Likewise.
 454         (VEX_W_0F3878_P_2): Likewise.
 455         (VEX_W_0F3879_P_2): Likewise.
 456         (VEX_W_0F3A00_P_2): Likewise.
 457         (VEX_W_0F3A01_P_2): Likewise.
 458         (VEX_W_0F3A02_P_2): Likewise.
 459         (VEX_W_0F3A38_P_2): Likewise.
 460         (VEX_W_0F3A39_P_2): Likewise.
 461         (VEX_W_0F3A46_P_2): Likewise.
 462         (MOD_VEX_0F3818_PREFIX_2): Removed.
 463         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 464         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 465         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 466         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 467         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 468         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 469         (VEX_LEN_0F3A0E_P_2): Likewise.
 470         (VEX_LEN_0F3A0F_P_2): Likewise.
 471         (VEX_LEN_0F3A42_P_2): Likewise.
 472         (VEX_LEN_0F3A4C_P_2): Likewise.
 473         (VEX_W_0F3818_P_2_M_0): Likewise.
 474         (VEX_W_0F3819_P_2_M_0): Likewise.
 475         (prefix_table): Updated.
 476         (three_byte_table): Likewise.
 477         (vex_table): Likewise.
 478         (vex_len_table): Likewise.
 479         (vex_w_table): Likewise.
 480         (mod_table): Likewise.
 481         (putop): Handle "LW".
 482         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 483         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 484         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 485         (OP_EX): Likewise.
 486         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 487         vex_vsib_q_w_dq_mode.
 488         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 489         (OP_VEX): Likewise.
 490
 491         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 492         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 493         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 494         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 495         (opcode_modifiers): Add VecSIB.
 496
 497         * i386-opc.h (CpuAVX2): New.
 498         (CpuBMI2): Likewise.
 499         (CpuLZCNT): Likewise.
 500         (CpuINVPCID): Likewise.
 501         (VecSIB128): Likewise.
 502         (VecSIB256): Likewise.
 503         (VecSIB): Likewise.
 504         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 505         (i386_opcode_modifier): Add vecsib.
 506
 507         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 508         * i386-init.h: Regenerated.
 509         * i386-tbl.h: Likewise.
 510
 511 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 512
 513         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 514         * i386-init.h: Regenerated.
 515
 516 2011-06-03  Nick Clifton  <nickc@redhat.com>
 517
 518         PR binutils/12752
 519         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 520         computing address offsets.
 521         (print_arm_address): Likewise.
 522         (print_insn_arm): Likewise.
 523         (print_insn_thumb16): Likewise.
 524         (print_insn_thumb32): Likewise.
 525
 526 2011-06-02  Jie Zhang <jie@codesourcery.com>
 527             Nathan Sidwell <nathan@codesourcery.com>
 528             Maciej Rozycki <macro@codesourcery.com>
 529
 530         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 531         as address offset.
 532         (print_arm_address): Likewise. Elide positive #0 appropriately.
 533         (print_insn_arm): Likewise.
 534
 535 2011-06-02  Nick Clifton  <nickc@redhat.com>
 536
 537         PR gas/12752
 538         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 539         passed to print_address_func.
 540
 541 2011-06-02  Nick Clifton  <nickc@redhat.com>
 542
 543         * arm-dis.c: Fix spelling mistakes.
 544         * op/opcodes.pot: Regenerate.
 545
 546 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 547
 548         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 549         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 550         * s390-opc.txt: Fix cxr instruction type.
 551
 552 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 553
 554         * s390-opc.c: Add new instruction types marking register pair
 555         operands.
 556         * s390-opc.txt: Match instructions having register pair operands
 557         to the new instruction types.
 558
 559 2011-05-19  Nick Clifton  <nickc@redhat.com>
 560
 561         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 562         operands.
 563
 564 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 565
 566         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 567         * i386-init.h: Regenerated.
 568
 569 2011-04-27  Nick Clifton  <nickc@redhat.com>
 570
 571         * po/da.po: Updated Danish translation.
 572
 573 2011-04-26  Anton Blanchard  <anton@samba.org>
 574
 575         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 576
 577 2011-04-21  DJ Delorie  <dj@redhat.com>
 578
 579         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 580         * rx-decode.c: Regenerate.
 581
 582 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 583
 584         * i386-init.h: Regenerated.
 585
 586 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 587
 588         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 589         from bdver1 flags.
 590
 591 2011-04-13  Nick Clifton  <nickc@redhat.com>
 592
 593         * v850-dis.c (disassemble): Always print a closing square brace if
 594         an opening square brace was printed.
 595
 596 2011-04-12  Nick Clifton  <nickc@redhat.com>
 597
 598         PR binutils/12534
 599         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 600         patterns.
 601         (print_insn_thumb32): Handle %L.
 602
 603 2011-04-11  Julian Brown  <julian@codesourcery.com>
 604
 605         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 606         (print_insn_thumb32): Add APSR bitmask support.
 607
 608 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 609
 610         * arm-dis.c (print_insn): init vars moved into private_data structure.
 611
 612 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 613
 614         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 615
 616 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 617
 618         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 619         post-increment to support LPM Z+ instruction. Add support for 'E'
 620         constraint for DES instruction.
 621         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 622
 623 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 624
 625         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 626
 627 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 628
 629         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 630         Use branch types instead.
 631         (print_insn): Likewise.
 632
 633 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 634
 635         * mips-opc.c (mips_builtin_opcodes): Correct register use
 636         annotation of "alnv.ps".
 637
 638 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 639
 640         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 641
 642 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 643
 644         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 645
 646 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 647
 648         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 649
 650 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 651
 652         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 653         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 654         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 655         exception, end_of_registers, msize, memory, bfd_mach.
 656         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 657         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 658         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 659         (get_allreg): Change to new defines.  Fallback to abort().
 660
 661 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 662
 663         * bfin-dis.c: Add whitespace/parenthesis where needed.
 664
 665 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 666
 667         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 668         than 7.
 669
 670 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 671
 672         * configure: Regenerate.
 673
 674 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 675
 676         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 677
 678 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 679
 680         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 681         dregs only when P is set, and dregs_lo otherwise.
 682
 683 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 684
 685         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 686
 687 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 688
 689         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 690
 691 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 692
 693         * bfin-dis.c (machine_registers): Delete REG_GP.
 694         (reg_names): Delete "GP".
 695         (decode_allregs): Change REG_GP to REG_LASTREG.
 696
 697 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 698
 699         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 700         M_IH, M_IU): Delete.
 701
 702 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 703
 704         * bfin-dis.c (reg_names): Add const.
 705         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 706         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 707         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 708         decode_counters, decode_allregs): Likewise.
 709
 710 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 711
 712         * i386-dis.c (OP_J): Parenthesize expression to prevent
 713         truncated addresses.
 714         (print_insn): Fix indentation off-by-one.
 715
 716 2011-02-01  Nick Clifton  <nickc@redhat.com>
 717
 718         * po/da.po: Updated Danish translation.
 719
 720 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 721
 722         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 723
 724 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 725
 726         * i386-dis.c (sIbT): New.
 727         (b_T_mode): Likewise.
 728         (dis386): Replace sIb with sIbT on "pushT".
 729         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 730         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 731
 732 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 733
 734         * i386-init.h: Regenerated.
 735         * i386-tbl.h: Regenerated
 736
 737 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 738
 739         * i386-dis.c (REG_XOP_TBM_01): New.
 740         (REG_XOP_TBM_02): New.
 741         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 742         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 743         entries, and add bextr instruction.
 744
 745         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 746         (cpu_flags): Add CpuTBM.
 747
 748         * i386-opc.h (CpuTBM) New.
 749         (i386_cpu_flags): Add bit cputbm.
 750
 751         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 752         blcs, blsfill, blsic, t1mskc, and tzmsk.
 753
 754 2011-01-12  DJ Delorie  <dj@redhat.com>
 755
 756         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 757
 758 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 759
 760         * mips-dis.c (print_insn_args): Adjust the value to print the real
 761         offset for "+c" argument.
 762
 763 2011-01-10  Nick Clifton  <nickc@redhat.com>
 764
 765         * po/da.po: Updated Danish translation.
 766
 767 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 768
 769         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 770
 771 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 772
 773         * i386-dis.c (REG_VEX_38F3): New.
 774         (PREFIX_0FBC): Likewise.
 775         (PREFIX_VEX_38F2): Likewise.
 776         (PREFIX_VEX_38F3_REG_1): Likewise.
 777         (PREFIX_VEX_38F3_REG_2): Likewise.
 778         (PREFIX_VEX_38F3_REG_3): Likewise.
 779         (PREFIX_VEX_38F7): Likewise.
 780         (VEX_LEN_38F2_P_0): Likewise.
 781         (VEX_LEN_38F3_R_1_P_0): Likewise.
 782         (VEX_LEN_38F3_R_2_P_0): Likewise.
 783         (VEX_LEN_38F3_R_3_P_0): Likewise.
 784         (VEX_LEN_38F7_P_0): Likewise.
 785         (dis386_twobyte): Use PREFIX_0FBC.
 786         (reg_table): Add REG_VEX_38F3.
 787         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 788         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 789         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 790         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 791         PREFIX_VEX_38F7.
 792         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 793         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 794         VEX_LEN_38F7_P_0.
 795
 796         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 797         (cpu_flags): Add CpuBMI.
 798
 799         * i386-opc.h (CpuBMI): New.
 800         (i386_cpu_flags): Add cpubmi.
 801
 802         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 803         * i386-init.h: Regenerated.
 804         * i386-tbl.h: Likewise.
 805
 806 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 807
 808         * i386-dis.c (VexGdq): New.
 809         (OP_VEX): Handle dq_mode.
 810
 811 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 812
 813         * i386-gen.c (process_copyright): Update copyright to 2011.
 814
 815 For older changes see ChangeLog-2010
 816 \f
 817 Copyright (C) 2011 Free Software Foundation, Inc.
 818
 819 Copying and distribution of this file, with or without modification,
 820 are permitted in any medium without royalty provided the copyright
 821 notice and this notice are preserved.
 822
 823 Local Variables:
 824 mode: change-log
 825 left-margin: 8
 826 fill-column: 74
 827 version-control: never
 828 End: