opcodes/ChangeLog

   1 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-opc.tbl: Add a blank line.
   4
   5 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
   8         (VecSIB128): Renamed to ...
   9         (VECSIB128): This.
  10         (VecSIB256): Renamed to ...
  11         (VECSIB256): This.
  12         (VecSIB512): Renamed to ...
  13         (VECSIB512): This.
  14         (VecSIB): Renamed to ...
  15         (SIB): This.
  16         (i386_opcode_modifier): Replace vecsib with sib.
  17         * i386-opc.tbl (VecSIB128): New.
  18         (VecSIB256): Likewise.
  19         (VecSIB512): Likewise.
  20         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  21         and VecSIB512, respectively.
  22
  23 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-dis.c: Adjust description of I macro.
  26         (x86_64_table): Drop use of I.
  27         (float_mem): Replace use of I.
  28         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  29
  30 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-dis.c: (print_insn): Avoid straight assignment to
  33         priv.orig_sizeflag when processing -M sub-options.
  34
  35 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  36
  37         * i386-dis.c: Adjust description of J macro.
  38         (dis386, x86_64_table, mod_table): Replace J.
  39         (putop): Remove handling of J.
  40
  41 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  44
  45 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  46
  47         * i386-dis.c: Adjust description of "LQ" macro.
  48         (dis386_twobyte): Use LQ for sysret.
  49         (putop): Adjust handling of LQ.
  50
  51 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  52
  53         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  54         * riscv-dis.c: Include elfxx-riscv.h.
  55
  56 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  59
  60 2020-06-17  Lili Cui  <lili.cui@intel.com>
  61
  62         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  63
  64 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  65
  66         PR gas/26115
  67         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  68         * i386-opc.tbl: Likewise.
  69         * i386-tbl.h: Regenerated.
  70
  71 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
  72
  73         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
  74
  75 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
  76
  77         * aarch64-opc.c (SYSREG): New macro for describing system registers.
  78         (SR_CORE): Likewise.
  79         (SR_FEAT): Likewise.
  80         (SR_RNG): Likewise.
  81         (SR_V8_1): Likewise.
  82         (SR_V8_2): Likewise.
  83         (SR_V8_3): Likewise.
  84         (SR_V8_4): Likewise.
  85         (SR_PAN): Likewise.
  86         (SR_RAS): Likewise.
  87         (SR_SSBS): Likewise.
  88         (SR_SVE): Likewise.
  89         (SR_ID_PFR2): Likewise.
  90         (SR_PROFILE): Likewise.
  91         (SR_MEMTAG): Likewise.
  92         (SR_SCXTNUM): Likewise.
  93         (aarch64_sys_regs): Refactor to store feature information in the table.
  94         (aarch64_sys_reg_supported_p): Collapse logic for system registers
  95         that now describe their own features.
  96         (aarch64_pstatefield_supported_p): Likewise.
  97
  98 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         * i386-dis.c (prefix_table): Fix a typo in comments.
 101
 102 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-dis.c (rex_ignored): Delete.
 105         (ckprefix): Drop rex_ignored initialization.
 106         (get_valid_dis386): Drop setting of rex_ignored.
 107         (print_insn): Drop checking of rex_ignored. Don't record data
 108         size prefix as used with VEX-and-alike encodings.
 109
 110 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 111
 112         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 113         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 114         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 115         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 116         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 117         VEX_0F12, and VEX_0F16.
 118         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 119         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 120         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 121         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 122         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 123         MOD_VEX_0F16_PREFIX_2 entries.
 124
 125 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 128         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 129         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 130         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 131         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 132         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 133         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 134         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 135         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 136         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 137         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 138         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 139         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 140         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 141         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 142         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 143         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 144         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 145         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 146         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 147         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 148         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 149         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 150         EVEX_W_0FC6_P_2): Delete.
 151         (print_insn): Add EVEX.W vs embedded prefix consistency check
 152         to prefix validation.
 153         * i386-dis-evex.h (evex_table): Don't further descend for
 154         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 155         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 156         and 0F2B.
 157         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 158         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 159         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 160         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 161         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 162         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 163         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 164         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 165         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 166         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 167         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 168         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 169         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 170         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 171         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 172         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 173         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 174         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 175         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 176         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 177         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 178         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 179         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 180         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 181         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 182         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 183         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 184
 185 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 188         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 189         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 190         vmovmskpX.
 191         (print_insn): Drop pointless check against bad_opcode. Split
 192         prefix validation into legacy and VEX-and-alike parts.
 193         (putop): Re-work 'X' macro handling.
 194
 195 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-dis.c (MOD_0F51): Rename to ...
 198         (MOD_0F50): ... this.
 199
 200 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 201
 202         * arm-dis.c (arm_opcodes): Add dfb.
 203         (thumb32_opcodes): Add dfb.
 204
 205 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 208
 209 2020-06-06  Alan Modra  <amodra@gmail.com>
 210
 211         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 212
 213 2020-06-05  Alan Modra  <amodra@gmail.com>
 214
 215         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 216         size is large enough.
 217
 218 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 219
 220         * disassemble.c (disassemble_init_for_target): Set endian_code for
 221         bpf targets.
 222         * bpf-desc.c: Regenerate.
 223         * bpf-opc.c: Likewise.
 224         * bpf-dis.c: Likewise.
 225
 226 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 227
 228         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 229         (cgen_put_insn_value): Likewise.
 230         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 231         * cgen-dis.in (print_insn): Likewise.
 232         * cgen-ibld.in (insert_1): Likewise.
 233         (insert_1): Likewise.
 234         (insert_insn_normal): Likewise.
 235         (extract_1): Likewise.
 236         * bpf-dis.c: Regenerate.
 237         * bpf-ibld.c: Likewise.
 238         * bpf-ibld.c: Likewise.
 239         * cgen-dis.in: Likewise.
 240         * cgen-ibld.in: Likewise.
 241         * cgen-opc.c: Likewise.
 242         * epiphany-dis.c: Likewise.
 243         * epiphany-ibld.c: Likewise.
 244         * fr30-dis.c: Likewise.
 245         * fr30-ibld.c: Likewise.
 246         * frv-dis.c: Likewise.
 247         * frv-ibld.c: Likewise.
 248         * ip2k-dis.c: Likewise.
 249         * ip2k-ibld.c: Likewise.
 250         * iq2000-dis.c: Likewise.
 251         * iq2000-ibld.c: Likewise.
 252         * lm32-dis.c: Likewise.
 253         * lm32-ibld.c: Likewise.
 254         * m32c-dis.c: Likewise.
 255         * m32c-ibld.c: Likewise.
 256         * m32r-dis.c: Likewise.
 257         * m32r-ibld.c: Likewise.
 258         * mep-dis.c: Likewise.
 259         * mep-ibld.c: Likewise.
 260         * mt-dis.c: Likewise.
 261         * mt-ibld.c: Likewise.
 262         * or1k-dis.c: Likewise.
 263         * or1k-ibld.c: Likewise.
 264         * xc16x-dis.c: Likewise.
 265         * xc16x-ibld.c: Likewise.
 266         * xstormy16-dis.c: Likewise.
 267         * xstormy16-ibld.c: Likewise.
 268
 269 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 270
 271         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 272         (print_insn_): Handle instruction endian.
 273         * bpf-dis.c: Regenerate.
 274         * bpf-desc.c: Regenerate.
 275         * epiphany-dis.c: Likewise.
 276         * epiphany-desc.c: Likewise.
 277         * fr30-dis.c: Likewise.
 278         * fr30-desc.c: Likewise.
 279         * frv-dis.c: Likewise.
 280         * frv-desc.c: Likewise.
 281         * ip2k-dis.c: Likewise.
 282         * ip2k-desc.c: Likewise.
 283         * iq2000-dis.c: Likewise.
 284         * iq2000-desc.c: Likewise.
 285         * lm32-dis.c: Likewise.
 286         * lm32-desc.c: Likewise.
 287         * m32c-dis.c: Likewise.
 288         * m32c-desc.c: Likewise.
 289         * m32r-dis.c: Likewise.
 290         * m32r-desc.c: Likewise.
 291         * mep-dis.c: Likewise.
 292         * mep-desc.c: Likewise.
 293         * mt-dis.c: Likewise.
 294         * mt-desc.c: Likewise.
 295         * or1k-dis.c: Likewise.
 296         * or1k-desc.c: Likewise.
 297         * xc16x-dis.c: Likewise.
 298         * xc16x-desc.c: Likewise.
 299         * xstormy16-dis.c: Likewise.
 300         * xstormy16-desc.c: Likewise.
 301
 302 2020-06-03  Nick Clifton  <nickc@redhat.com>
 303
 304         * po/sr.po: Updated Serbian translation.
 305
 306 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 307
 308         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 309         (riscv_get_priv_spec_class): Likewise.
 310
 311 2020-06-01  Alan Modra  <amodra@gmail.com>
 312
 313         * bpf-desc.c: Regenerate.
 314
 315 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 316             David Faust <david.faust@oracle.com>
 317
 318         * bpf-desc.c: Regenerate.
 319         * bpf-opc.h: Likewise.
 320         * bpf-opc.c: Likewise.
 321         * bpf-dis.c: Likewise.
 322
 323 2020-05-28  Alan Modra  <amodra@gmail.com>
 324
 325         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 326         values.
 327
 328 2020-05-28  Alan Modra  <amodra@gmail.com>
 329
 330         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 331         immediates.
 332         (print_insn_ns32k): Revert last change.
 333
 334 2020-05-28  Nick Clifton  <nickc@redhat.com>
 335
 336         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 337         static.
 338
 339 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 340
 341         Fix extraction of signed constants in nios2 disassembler (again).
 342
 343         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 344         extractions of signed fields.
 345
 346 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 347
 348         * s390-opc.txt: Relocate vector load/store instructions with
 349         additional alignment parameter and change architecture level
 350         constraint from z14 to z13.
 351
 352 2020-05-21  Alan Modra  <amodra@gmail.com>
 353
 354         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 355         * sparc-dis.c: Likewise.
 356         * tic4x-dis.c: Likewise.
 357         * xtensa-dis.c: Likewise.
 358         * bpf-desc.c: Regenerate.
 359         * epiphany-desc.c: Regenerate.
 360         * fr30-desc.c: Regenerate.
 361         * frv-desc.c: Regenerate.
 362         * ip2k-desc.c: Regenerate.
 363         * iq2000-desc.c: Regenerate.
 364         * lm32-desc.c: Regenerate.
 365         * m32c-desc.c: Regenerate.
 366         * m32r-desc.c: Regenerate.
 367         * mep-asm.c: Regenerate.
 368         * mep-desc.c: Regenerate.
 369         * mt-desc.c: Regenerate.
 370         * or1k-desc.c: Regenerate.
 371         * xc16x-desc.c: Regenerate.
 372         * xstormy16-desc.c: Regenerate.
 373
 374 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 375
 376         * riscv-opc.c (riscv_ext_version_table): The table used to store
 377         all information about the supported spec and the corresponding ISA
 378         versions.  Currently, only Zicsr is supported to verify the
 379         correctness of Z sub extension settings.  Others will be supported
 380         in the future patches.
 381         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 382         classes and the corresponding strings.
 383         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 384         spec class by giving a ISA spec string.
 385         * riscv-opc.c (struct priv_spec_t): New structure.
 386         (struct priv_spec_t priv_specs): List for all supported privilege spec
 387         classes and the corresponding strings.
 388         (riscv_get_priv_spec_class): New function.  Get the corresponding
 389         privilege spec class by giving a spec string.
 390         (riscv_get_priv_spec_name): New function.  Get the corresponding
 391         privilege spec string by giving a CSR version class.
 392         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 393         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 394         according to the chosen version.  Build a hash table riscv_csr_hash to
 395         store the valid CSR for the chosen pirv verison.  Dump the direct
 396         CSR address rather than it's name if it is invalid.
 397         (parse_riscv_dis_option_without_args): New function.  Parse the options
 398         without arguments.
 399         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 400         parse the options without arguments first, and then handle the options
 401         with arguments.  Add the new option -Mpriv-spec, which has argument.
 402         * riscv-dis.c (print_riscv_disassembler_options): Add description
 403         about the new OBJDUMP option.
 404
 405 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 406
 407         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 408         WC values on POWER10 sync, dcbf  and wait instructions.
 409         (insert_pl, extract_pl): New functions.
 410         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 411         (LS3): New , 3-bit L for sync.
 412         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 413         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 414         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 415         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 416         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 417         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 418         <wait>: Enable PL operand on POWER10.
 419         <dcbf>: Enable L3OPT operand on POWER10.
 420         <sync>: Enable SC2 operand on POWER10.
 421
 422 2020-05-19  Stafford Horne  <shorne@gmail.com>
 423
 424         PR 25184
 425         * or1k-asm.c: Regenerate.
 426         * or1k-desc.c: Regenerate.
 427         * or1k-desc.h: Regenerate.
 428         * or1k-dis.c: Regenerate.
 429         * or1k-ibld.c: Regenerate.
 430         * or1k-opc.c: Regenerate.
 431         * or1k-opc.h: Regenerate.
 432         * or1k-opinst.c: Regenerate.
 433
 434 2020-05-11  Alan Modra  <amodra@gmail.com>
 435
 436         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 437         xsmaxcqp, xsmincqp.
 438
 439 2020-05-11  Alan Modra  <amodra@gmail.com>
 440
 441         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 442         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 443
 444 2020-05-11  Alan Modra  <amodra@gmail.com>
 445
 446         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 447
 448 2020-05-11  Alan Modra  <amodra@gmail.com>
 449
 450         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 451         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 452
 453 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 454
 455         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 456         mnemonics.
 457
 458 2020-05-11  Alan Modra  <amodra@gmail.com>
 459
 460         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 461         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 462         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 463         (prefix_opcodes): Add xxeval.
 464
 465 2020-05-11  Alan Modra  <amodra@gmail.com>
 466
 467         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 468         xxgenpcvwm, xxgenpcvdm.
 469
 470 2020-05-11  Alan Modra  <amodra@gmail.com>
 471
 472         * ppc-opc.c (MP, VXVAM_MASK): Define.
 473         (VXVAPS_MASK): Use VXVA_MASK.
 474         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 475         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 476         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 477         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 478
 479 2020-05-11  Alan Modra  <amodra@gmail.com>
 480             Peter Bergner  <bergner@linux.ibm.com>
 481
 482         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 483         New functions.
 484         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 485         YMSK2, XA6a, XA6ap, XB6a entries.
 486         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 487         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 488         (PPCVSX4): Define.
 489         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 490         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 491         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 492         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 493         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 494         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 495         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 496         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 497         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 498         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 499         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 500         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 501         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 502         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 503
 504 2020-05-11  Alan Modra  <amodra@gmail.com>
 505
 506         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 507         (insert_xts, extract_xts): New functions.
 508         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 509         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 510         (VXRC_MASK, VXSH_MASK): Define.
 511         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 512         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 513         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 514         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 515         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 516         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 517         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 518
 519 2020-05-11  Alan Modra  <amodra@gmail.com>
 520
 521         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 522         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 523         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 524         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 525         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 526
 527 2020-05-11  Alan Modra  <amodra@gmail.com>
 528
 529         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 530         (XTP, DQXP, DQXP_MASK): Define.
 531         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 532         (prefix_opcodes): Add plxvp and pstxvp.
 533
 534 2020-05-11  Alan Modra  <amodra@gmail.com>
 535
 536         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 537         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 538         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 539
 540 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 541
 542         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 543
 544 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 545
 546         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 547         (L1OPT): Define.
 548         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 549
 550 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 551
 552         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 553
 554 2020-05-11  Alan Modra  <amodra@gmail.com>
 555
 556         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 557
 558 2020-05-11  Alan Modra  <amodra@gmail.com>
 559
 560         * ppc-dis.c (ppc_opts): Add "power10" entry.
 561         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 562         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 563
 564 2020-05-11  Nick Clifton  <nickc@redhat.com>
 565
 566         * po/fr.po: Updated French translation.
 567
 568 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 569
 570         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 571         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 572         (operand_general_constraint_met_p): validate
 573         AARCH64_OPND_UNDEFINED.
 574         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 575         for FLD_imm16_2.
 576         * aarch64-asm-2.c: Regenerated.
 577         * aarch64-dis-2.c: Regenerated.
 578         * aarch64-opc-2.c: Regenerated.
 579
 580 2020-04-29  Nick Clifton  <nickc@redhat.com>
 581
 582         PR 22699
 583         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 584         and SETRC insns.
 585
 586 2020-04-29  Nick Clifton  <nickc@redhat.com>
 587
 588         * po/sv.po: Updated Swedish translation.
 589
 590 2020-04-29  Nick Clifton  <nickc@redhat.com>
 591
 592         PR 22699
 593         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 594         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 595         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 596         IMM0_8U case.
 597
 598 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 599
 600         PR 25848
 601         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 602         cmpi only on m68020up and cpu32.
 603
 604 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 605
 606         * aarch64-asm.c (aarch64_ins_none): New.
 607         * aarch64-asm.h (ins_none): New declaration.
 608         * aarch64-dis.c (aarch64_ext_none): New.
 609         * aarch64-dis.h (ext_none): New declaration.
 610         * aarch64-opc.c (aarch64_print_operand): Update case for
 611         AARCH64_OPND_BARRIER_PSB.
 612         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 613         (AARCH64_OPERANDS): Update inserter/extracter for
 614         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 615         * aarch64-asm-2.c: Regenerated.
 616         * aarch64-dis-2.c: Regenerated.
 617         * aarch64-opc-2.c: Regenerated.
 618
 619 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 620
 621         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 622         (aarch64_feature_ras, RAS): Likewise.
 623         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 624         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 625         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 626         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 627         * aarch64-asm-2.c: Regenerated.
 628         * aarch64-dis-2.c: Regenerated.
 629         * aarch64-opc-2.c: Regenerated.
 630
 631 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 632
 633         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 634         (print_insn_neon): Support disassembly of conditional
 635         instructions.
 636
 637 2020-02-16  David Faust  <david.faust@oracle.com>
 638
 639         * bpf-desc.c: Regenerate.
 640         * bpf-desc.h: Likewise.
 641         * bpf-opc.c: Regenerate.
 642         * bpf-opc.h: Likewise.
 643
 644 2020-04-07  Lili Cui  <lili.cui@intel.com>
 645
 646         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 647         (prefix_table): New instructions (see prefixes above).
 648         (rm_table): Likewise
 649         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 650         CPU_ANY_TSXLDTRK_FLAGS.
 651         (cpu_flags): Add CpuTSXLDTRK.
 652         * i386-opc.h (enum): Add CpuTSXLDTRK.
 653         (i386_cpu_flags): Add cputsxldtrk.
 654         * i386-opc.tbl: Add XSUSPLDTRK insns.
 655         * i386-init.h: Regenerate.
 656         * i386-tbl.h: Likewise.
 657
 658 2020-04-02  Lili Cui  <lili.cui@intel.com>
 659
 660         * i386-dis.c (prefix_table): New instructions serialize.
 661         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 662         CPU_ANY_SERIALIZE_FLAGS.
 663         (cpu_flags): Add CpuSERIALIZE.
 664         * i386-opc.h (enum): Add CpuSERIALIZE.
 665         (i386_cpu_flags): Add cpuserialize.
 666         * i386-opc.tbl: Add SERIALIZE insns.
 667         * i386-init.h: Regenerate.
 668         * i386-tbl.h: Likewise.
 669
 670 2020-03-26  Alan Modra  <amodra@gmail.com>
 671
 672         * disassemble.h (opcodes_assert): Declare.
 673         (OPCODES_ASSERT): Define.
 674         * disassemble.c: Don't include assert.h.  Include opintl.h.
 675         (opcodes_assert): New function.
 676         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 677         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 678         calculate maxlen.  Omit insn decoding when insn length exceeds
 679         maxlen.  Exit from nibble loop when looking for E, before
 680         accessing next data byte.  Move processing of E outside loop.
 681         Replace tests of maxlen in loop with assertions.
 682
 683 2020-03-26  Alan Modra  <amodra@gmail.com>
 684
 685         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 686
 687 2020-03-25  Alan Modra  <amodra@gmail.com>
 688
 689         * z80-dis.c (suffix): Init mybuf.
 690
 691 2020-03-22  Alan Modra  <amodra@gmail.com>
 692
 693         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 694         successflly read from section.
 695
 696 2020-03-22  Alan Modra  <amodra@gmail.com>
 697
 698         * arc-dis.c (find_format): Use ISO C string concatenation rather
 699         than line continuation within a string.  Don't access needs_limm
 700         before testing opcode != NULL.
 701
 702 2020-03-22  Alan Modra  <amodra@gmail.com>
 703
 704         * ns32k-dis.c (print_insn_arg): Update comment.
 705         (print_insn_ns32k): Reduce size of index_offset array, and
 706         initialize, passing -1 to print_insn_arg for args that are not
 707         an index.  Don't exit arg loop early.  Abort on bad arg number.
 708
 709 2020-03-22  Alan Modra  <amodra@gmail.com>
 710
 711         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 712         * s12z-opc.c: Formatting.
 713         (operands_f): Return an int.
 714         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 715         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 716         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 717         (exg_sex_discrim): Likewise.
 718         (create_immediate_operand, create_bitfield_operand),
 719         (create_register_operand_with_size, create_register_all_operand),
 720         (create_register_all16_operand, create_simple_memory_operand),
 721         (create_memory_operand, create_memory_auto_operand): Don't
 722         segfault on malloc failure.
 723         (z_ext24_decode): Return an int status, negative on fail, zero
 724         on success.
 725         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 726         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 727         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 728         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 729         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 730         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 731         (loop_primitive_decode, shift_decode, psh_pul_decode),
 732         (bit_field_decode): Similarly.
 733         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 734         to return value, update callers.
 735         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 736         Don't segfault on NULL operand.
 737         (decode_operation): Return OP_INVALID on first fail.
 738         (decode_s12z): Check all reads, returning -1 on fail.
 739
 740 2020-03-20  Alan Modra  <amodra@gmail.com>
 741
 742         * metag-dis.c (print_insn_metag): Don't ignore status from
 743         read_memory_func.
 744
 745 2020-03-20  Alan Modra  <amodra@gmail.com>
 746
 747         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 748         Initialize parts of buffer not written when handling a possible
 749         2-byte insn at end of section.  Don't attempt decoding of such
 750         an insn by the 4-byte machinery.
 751
 752 2020-03-20  Alan Modra  <amodra@gmail.com>
 753
 754         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 755         partially filled buffer.  Prevent lookup of 4-byte insns when
 756         only VLE 2-byte insns are possible due to section size.  Print
 757         ".word" rather than ".long" for 2-byte leftovers.
 758
 759 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 760
 761         PR 25641
 762         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 763
 764 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-dis.c (X86_64_0D): Rename to ...
 767         (X86_64_0E): ... this.
 768
 769 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 770
 771         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 772         * Makefile.in: Regenerated.
 773
 774 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 777         3-operand pseudos.
 778         * i386-tbl.h: Re-generate.
 779
 780 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 783         vprot*, vpsha*, and vpshl*.
 784         * i386-tbl.h: Re-generate.
 785
 786 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 789         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 790         * i386-tbl.h: Re-generate.
 791
 792 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 795         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 796         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 797         * i386-tbl.h: Re-generate.
 798
 799 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-gen.c (struct template_arg, struct template_instance,
 802         struct template_param, struct template, templates,
 803         parse_template, expand_templates): New.
 804         (process_i386_opcodes): Various local variables moved to
 805         expand_templates. Call parse_template and expand_templates.
 806         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 807         * i386-tbl.h: Re-generate.
 808
 809 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 812         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 813         register and memory source templates. Replace VexW= by VexW*
 814         where applicable.
 815         * i386-tbl.h: Re-generate.
 816
 817 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 820         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 821         * i386-tbl.h: Re-generate.
 822
 823 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 826         * i386-tbl.h: Re-generate.
 827
 828 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 831         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 832         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 833         VexW0 on SSE2AVX variants.
 834         (vmovq): Drop NoRex64 from XMM/XMM variants.
 835         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 836         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 837         applicable use VexW0.
 838         * i386-tbl.h: Re-generate.
 839
 840 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 843         * i386-opc.h (Rex64): Delete.
 844         (struct i386_opcode_modifier): Remove rex64 field.
 845         * i386-opc.tbl (crc32): Drop Rex64.
 846         Replace Rex64 with Size64 everywhere else.
 847         * i386-tbl.h: Re-generate.
 848
 849 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 850
 851         * i386-dis.c (OP_E_memory): Exclude recording of used address
 852         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 853         addressed memory operands for MPX insns.
 854
 855 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 858         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 859         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 860         (ptwrite): Split into non-64-bit and 64-bit forms.
 861         * i386-tbl.h: Re-generate.
 862
 863 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 866         template.
 867         * i386-tbl.h: Re-generate.
 868
 869 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 870
 871         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 872         (prefix_table): Move vmmcall here. Add vmgexit.
 873         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 874         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 875         (cpu_flags): Add CpuSEV_ES entry.
 876         * i386-opc.h (CpuSEV_ES): New.
 877         (union i386_cpu_flags): Add cpusev_es field.
 878         * i386-opc.tbl (vmgexit): New.
 879         * i386-init.h, i386-tbl.h: Re-generate.
 880
 881 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 882
 883         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 884         with MnemonicSize.
 885         * i386-opc.h (IGNORESIZE): New.
 886         (DEFAULTSIZE): Likewise.
 887         (IgnoreSize): Removed.
 888         (DefaultSize): Likewise.
 889         (MnemonicSize): New.
 890         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 891         mnemonicsize.
 892         * i386-opc.tbl (IgnoreSize): New.
 893         (DefaultSize): Likewise.
 894         * i386-tbl.h: Regenerated.
 895
 896 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 897
 898         PR 25627
 899         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 900         instructions.
 901
 902 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 903
 904         PR gas/25622
 905         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 906         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 907         * i386-tbl.h: Regenerated.
 908
 909 2020-02-26  Alan Modra  <amodra@gmail.com>
 910
 911         * aarch64-asm.c: Indent labels correctly.
 912         * aarch64-dis.c: Likewise.
 913         * aarch64-gen.c: Likewise.
 914         * aarch64-opc.c: Likewise.
 915         * alpha-dis.c: Likewise.
 916         * i386-dis.c: Likewise.
 917         * nds32-asm.c: Likewise.
 918         * nfp-dis.c: Likewise.
 919         * visium-dis.c: Likewise.
 920
 921 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 922
 923         * arc-regs.h (int_vector_base): Make it available for all ARC
 924         CPUs.
 925
 926 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 927
 928         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 929         changed.
 930
 931 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 932
 933         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 934         c.mv/c.li if rs1 is zero.
 935
 936 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 937
 938         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 939         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 940         CPU_POPCNT_FLAGS.
 941         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 942         * i386-opc.h (CpuABM): Removed.
 943         (CpuPOPCNT): New.
 944         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 945         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 946         popcnt.  Remove CpuABM from lzcnt.
 947         * i386-init.h: Regenerated.
 948         * i386-tbl.h: Likewise.
 949
 950 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 953         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 954         VexW1 instead of open-coding them.
 955         * i386-tbl.h: Re-generate.
 956
 957 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-opc.tbl (AddrPrefixOpReg): Define.
 960         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 961         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 962         templates. Drop NoRex64.
 963         * i386-tbl.h: Re-generate.
 964
 965 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 966
 967         PR gas/6518
 968         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 969         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 970         into Intel syntax instance (with Unpsecified) and AT&T one
 971         (without).
 972         (vcvtneps2bf16): Likewise, along with folding the two so far
 973         separate ones.
 974         * i386-tbl.h: Re-generate.
 975
 976 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 977
 978         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 979         CPU_ANY_SSE4A_FLAGS.
 980
 981 2020-02-17  Alan Modra  <amodra@gmail.com>
 982
 983         * i386-gen.c (cpu_flag_init): Correct last change.
 984
 985 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 986
 987         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 988         CPU_ANY_SSE4_FLAGS.
 989
 990 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 991
 992         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 993         (movzx): Likewise.
 994
 995 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 996
 997         PR gas/25438
 998         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 999         destination for Cpu64-only variant.
1000         (movzx): Fold patterns.
1001         * i386-tbl.h: Re-generate.
1002
1003 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1006         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1007         CPU_ANY_SSE4_FLAGS entry.
1008         * i386-init.h: Re-generate.
1009
1010 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1011
1012         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1013         with Unspecified, making the present one AT&T syntax only.
1014         * i386-tbl.h: Re-generate.
1015
1016 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1019         * i386-tbl.h: Re-generate.
1020
1021 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1022
1023         PR gas/24546
1024         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1025         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1026         Amd64 and Intel64 templates.
1027         (call, jmp): Likewise for far indirect variants. Dro
1028         Unspecified.
1029         * i386-tbl.h: Re-generate.
1030
1031 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1034         * i386-opc.h (ShortForm): Delete.
1035         (struct i386_opcode_modifier): Remove shortform field.
1036         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1037         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1038         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1039         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1040         Drop ShortForm.
1041         * i386-tbl.h: Re-generate.
1042
1043 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1046         fucompi): Drop ShortForm from operand-less templates.
1047         * i386-tbl.h: Re-generate.
1048
1049 2020-02-11  Alan Modra  <amodra@gmail.com>
1050
1051         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1052         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1053         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1054         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1055         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1056
1057 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1058
1059         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1060         (cde_opcodes): Add VCX* instructions.
1061
1062 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1063             Matthew Malcomson  <matthew.malcomson@arm.com>
1064
1065         * arm-dis.c (struct cdeopcode32): New.
1066         (CDE_OPCODE): New macro.
1067         (cde_opcodes): New disassembly table.
1068         (regnames): New option to table.
1069         (cde_coprocs): New global variable.
1070         (print_insn_cde): New
1071         (print_insn_thumb32): Use print_insn_cde.
1072         (parse_arm_disassembler_options): Parse coprocN args.
1073
1074 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1075
1076         PR gas/25516
1077         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1078         with ISA64.
1079         * i386-opc.h (AMD64): Removed.
1080         (Intel64): Likewose.
1081         (AMD64): New.
1082         (INTEL64): Likewise.
1083         (INTEL64ONLY): Likewise.
1084         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1085         * i386-opc.tbl (Amd64): New.
1086         (Intel64): Likewise.
1087         (Intel64Only): Likewise.
1088         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1089         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1090         * i386-tbl.h: Regenerated.
1091
1092 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1093
1094         PR 25469
1095         * z80-dis.c: Add support for GBZ80 opcodes.
1096
1097 2020-02-04  Alan Modra  <amodra@gmail.com>
1098
1099         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1100
1101 2020-02-03  Alan Modra  <amodra@gmail.com>
1102
1103         * m32c-ibld.c: Regenerate.
1104
1105 2020-02-01  Alan Modra  <amodra@gmail.com>
1106
1107         * frv-ibld.c: Regenerate.
1108
1109 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1110
1111         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1112         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1113         (OP_E_memory): Replace xmm_mdq_mode case label by
1114         vex_scalar_w_dq_mode one.
1115         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1116
1117 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1118
1119         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1120         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1121         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1122         (intel_operand_size): Drop vex_w_dq_mode case label.
1123
1124 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1125
1126         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1127         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1128
1129 2020-01-30  Alan Modra  <amodra@gmail.com>
1130
1131         * m32c-ibld.c: Regenerate.
1132
1133 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1134
1135         * bpf-opc.c: Regenerate.
1136
1137 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1140         (dis386): Use them to replace C2/C3 table entries.
1141         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1142         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1143         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1144         * i386-tbl.h: Re-generate.
1145
1146 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1147
1148         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1149         forms.
1150         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1151         DefaultSize.
1152         * i386-tbl.h: Re-generate.
1153
1154 2020-01-30  Alan Modra  <amodra@gmail.com>
1155
1156         * tic4x-dis.c (tic4x_dp): Make unsigned.
1157
1158 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1159             Jan Beulich  <jbeulich@suse.com>
1160
1161         PR binutils/25445
1162         * i386-dis.c (MOVSXD_Fixup): New function.
1163         (movsxd_mode): New enum.
1164         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1165         (intel_operand_size): Handle movsxd_mode.
1166         (OP_E_register): Likewise.
1167         (OP_G): Likewise.
1168         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1169         register on movsxd.  Add movsxd with 16-bit destination register
1170         for AMD64 and Intel64 ISAs.
1171         * i386-tbl.h: Regenerated.
1172
1173 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1174
1175         PR 25403
1176         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1177         * aarch64-asm-2.c: Regenerate
1178         * aarch64-dis-2.c: Likewise.
1179         * aarch64-opc-2.c: Likewise.
1180
1181 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-opc.tbl (sysret): Drop DefaultSize.
1184         * i386-tbl.h: Re-generate.
1185
1186 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1187
1188         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1189         Dword.
1190         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1191         * i386-tbl.h: Re-generate.
1192
1193 2020-01-20  Nick Clifton  <nickc@redhat.com>
1194
1195         * po/de.po: Updated German translation.
1196         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1197         * po/uk.po: Updated Ukranian translation.
1198
1199 2020-01-20  Alan Modra  <amodra@gmail.com>
1200
1201         * hppa-dis.c (fput_const): Remove useless cast.
1202
1203 2020-01-20  Alan Modra  <amodra@gmail.com>
1204
1205         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1206
1207 2020-01-18  Nick Clifton  <nickc@redhat.com>
1208
1209         * configure: Regenerate.
1210         * po/opcodes.pot: Regenerate.
1211
1212 2020-01-18  Nick Clifton  <nickc@redhat.com>
1213
1214         Binutils 2.34 branch created.
1215
1216 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1217
1218         * opintl.h: Fix spelling error (seperate).
1219
1220 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1221
1222         * i386-opc.tbl: Add {vex} pseudo prefix.
1223         * i386-tbl.h: Regenerated.
1224
1225 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1226
1227         PR 25376
1228         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1229         (neon_opcodes): Likewise.
1230         (select_arm_features): Make sure we enable MVE bits when selecting
1231         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1232         any architecture.
1233
1234 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-opc.tbl: Drop stale comment from XOP section.
1237
1238 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1239
1240         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1241         (extractps): Add VexWIG to SSE2AVX forms.
1242         * i386-tbl.h: Re-generate.
1243
1244 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1245
1246         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1247         Size64 from and use VexW1 on SSE2AVX forms.
1248         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1249         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1250         * i386-tbl.h: Re-generate.
1251
1252 2020-01-15  Alan Modra  <amodra@gmail.com>
1253
1254         * tic4x-dis.c (tic4x_version): Make unsigned long.
1255         (optab, optab_special, registernames): New file scope vars.
1256         (tic4x_print_register): Set up registernames rather than
1257         malloc'd registertable.
1258         (tic4x_disassemble): Delete optable and optable_special.  Use
1259         optab and optab_special instead.  Throw away old optab,
1260         optab_special and registernames when info->mach changes.
1261
1262 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1263
1264         PR 25377
1265         * z80-dis.c (suffix): Use .db instruction to generate double
1266         prefix.
1267
1268 2020-01-14  Alan Modra  <amodra@gmail.com>
1269
1270         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1271         values to unsigned before shifting.
1272
1273 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1274
1275         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1276         flow instructions.
1277         (print_insn_thumb16, print_insn_thumb32): Likewise.
1278         (print_insn): Initialize the insn info.
1279         * i386-dis.c (print_insn): Initialize the insn info fields, and
1280         detect jumps.
1281
1282 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1283
1284         * arc-opc.c (C_NE): Make it required.
1285
1286 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1287
1288         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1289         reserved register name.
1290
1291 2020-01-13  Alan Modra  <amodra@gmail.com>
1292
1293         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1294         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1295
1296 2020-01-13  Alan Modra  <amodra@gmail.com>
1297
1298         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1299         result of wasm_read_leb128 in a uint64_t and check that bits
1300         are not lost when copying to other locals.  Use uint32_t for
1301         most locals.  Use PRId64 when printing int64_t.
1302
1303 2020-01-13  Alan Modra  <amodra@gmail.com>
1304
1305         * score-dis.c: Formatting.
1306         * score7-dis.c: Formatting.
1307
1308 2020-01-13  Alan Modra  <amodra@gmail.com>
1309
1310         * score-dis.c (print_insn_score48): Use unsigned variables for
1311         unsigned values.  Don't left shift negative values.
1312         (print_insn_score32): Likewise.
1313         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1314
1315 2020-01-13  Alan Modra  <amodra@gmail.com>
1316
1317         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1318
1319 2020-01-13  Alan Modra  <amodra@gmail.com>
1320
1321         * fr30-ibld.c: Regenerate.
1322
1323 2020-01-13  Alan Modra  <amodra@gmail.com>
1324
1325         * xgate-dis.c (print_insn): Don't left shift signed value.
1326         (ripBits): Formatting, use 1u.
1327
1328 2020-01-10  Alan Modra  <amodra@gmail.com>
1329
1330         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1331         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1332
1333 2020-01-10  Alan Modra  <amodra@gmail.com>
1334
1335         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1336         and XRREG value earlier to avoid a shift with negative exponent.
1337         * m10200-dis.c (disassemble): Similarly.
1338
1339 2020-01-09  Nick Clifton  <nickc@redhat.com>
1340
1341         PR 25224
1342         * z80-dis.c (ld_ii_ii): Use correct cast.
1343
1344 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1345
1346         PR 25224
1347         * z80-dis.c (ld_ii_ii): Use character constant when checking
1348         opcode byte value.
1349
1350 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1351
1352         * i386-dis.c (SEP_Fixup): New.
1353         (SEP): Define.
1354         (dis386_twobyte): Use it for sysenter/sysexit.
1355         (enum x86_64_isa): Change amd64 enumerator to value 1.
1356         (OP_J): Compare isa64 against intel64 instead of amd64.
1357         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1358         forms.
1359         * i386-tbl.h: Re-generate.
1360
1361 2020-01-08  Alan Modra  <amodra@gmail.com>
1362
1363         * z8k-dis.c: Include libiberty.h
1364         (instr_data_s): Make max_fetched unsigned.
1365         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1366         Don't exceed byte_info bounds.
1367         (output_instr): Make num_bytes unsigned.
1368         (unpack_instr): Likewise for nibl_count and loop.
1369         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1370         idx unsigned.
1371         * z8k-opc.h: Regenerate.
1372
1373 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1374
1375         * arc-tbl.h (llock): Use 'LLOCK' as class.
1376         (llockd): Likewise.
1377         (scond): Use 'SCOND' as class.
1378         (scondd): Likewise.
1379         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1380         (scondd): Likewise.
1381
1382 2020-01-06  Alan Modra  <amodra@gmail.com>
1383
1384         * m32c-ibld.c: Regenerate.
1385
1386 2020-01-06  Alan Modra  <amodra@gmail.com>
1387
1388         PR 25344
1389         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1390         Peek at next byte to prevent recursion on repeated prefix bytes.
1391         Ensure uninitialised "mybuf" is not accessed.
1392         (print_insn_z80): Don't zero n_fetch and n_used here,..
1393         (print_insn_z80_buf): ..do it here instead.
1394
1395 2020-01-04  Alan Modra  <amodra@gmail.com>
1396
1397         * m32r-ibld.c: Regenerate.
1398
1399 2020-01-04  Alan Modra  <amodra@gmail.com>
1400
1401         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1402
1403 2020-01-04  Alan Modra  <amodra@gmail.com>
1404
1405         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1406
1407 2020-01-04  Alan Modra  <amodra@gmail.com>
1408
1409         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1410
1411 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1412
1413         * aarch64-tbl.h (aarch64_opcode_table): Use
1414         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1415
1416 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1417
1418         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1419         forms of SUDOT and USDOT.
1420
1421 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1422
1423         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1424         uzip{1,2}.
1425         * opcodes/aarch64-dis-2.c: Re-generate.
1426
1427 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1428
1429         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1430         FMMLA encoding.
1431         * opcodes/aarch64-dis-2.c: Re-generate.
1432
1433 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1434
1435         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1436
1437 2020-01-01  Alan Modra  <amodra@gmail.com>
1438
1439         Update year range in copyright notice of all files.
1440
1441 For older changes see ChangeLog-2019
1442 \f
1443 Copyright (C) 2020 Free Software Foundation, Inc.
1444
1445 Copying and distribution of this file, with or without modification,
1446 are permitted in any medium without royalty provided the copyright
1447 notice and this notice are preserved.
1448
1449 Local Variables:
1450 mode: change-log
1451 left-margin: 8
1452 fill-column: 74
1453 version-control: never
1454 End: