opcodes/ChangeLog

   1 2019-12-16  Alan Modra  <amodra@gmail.com>
   2
   3         * xstormy16-ibld.c: Regenerate.
   4
   5 2019-12-16  Alan Modra  <amodra@gmail.com>
   6
   7         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
   8         value adjustment so that it doesn't affect reg field too.
   9
  10 2019-12-16  Alan Modra  <amodra@gmail.com>
  11
  12         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
  13         (get_number_of_operands, getargtype, getbits, getregname),
  14         (getcopregname, getprocregname, gettrapstring, getcinvstring),
  15         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
  16         (powerof2, match_opcode, make_instruction, print_arguments),
  17         (print_arg): Delete forward declarations, moving static to..
  18         (getregname, getcopregname, getregliststring): ..these definitions.
  19         (build_mask): Return unsigned int mask.
  20         (match_opcode): Use unsigned int vars.
  21
  22 2019-12-16  Alan Modra  <amodra@gmail.com>
  23
  24         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
  25
  26 2019-12-16  Alan Modra  <amodra@gmail.com>
  27
  28         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
  29         (struct objdump_disasm_info): Delete.
  30         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
  31         N32_IMMS to unsigned before shifting left.
  32
  33 2019-12-16  Alan Modra  <amodra@gmail.com>
  34
  35         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
  36         (print_insn_moxie): Remove unnecessary cast.
  37
  38 2019-12-12  Alan Modra  <amodra@gmail.com>
  39
  40         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
  41         mask.
  42
  43 2019-12-11  Alan Modra  <amodra@gmail.com>
  44
  45         * arc-dis.c (BITS): Don't truncate high bits with shifts.
  46         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
  47         * tic54x-dis.c (print_instruction): Likewise.
  48         * tilegx-opc.c (parse_insn_tilegx): Likewise.
  49         * tilepro-opc.c (parse_insn_tilepro): Likewise.
  50         * visium-dis.c (disassem_class0): Likewise.
  51         * pdp11-dis.c (sign_extend): Likewise.
  52         (SIGN_BITS): Delete.
  53         * epiphany-ibld.c: Regenerate.
  54         * lm32-ibld.c: Regenerate.
  55         * m32c-ibld.c: Regenerate.
  56
  57 2019-12-11  Alan Modra  <amodra@gmail.com>
  58
  59         * ns32k-dis.c (sign_extend): Correct last patch.
  60
  61 2019-12-11  Alan Modra  <amodra@gmail.com>
  62
  63         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  64
  65 2019-12-11  Alan Modra  <amodra@gmail.com>
  66
  67         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  68         sign extend using shifts.
  69
  70 2019-12-11  Alan Modra  <amodra@gmail.com>
  71
  72         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  73
  74 2019-12-11  Alan Modra  <amodra@gmail.com>
  75
  76         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  77         on NULL registertable entry.
  78         (tic4x_hash_opcode): Use unsigned arithmetic.
  79
  80 2019-12-11  Alan Modra  <amodra@gmail.com>
  81
  82         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  83
  84 2019-12-11  Alan Modra  <amodra@gmail.com>
  85
  86         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  87         (bit_extract_simple, sign_extend): Likewise.
  88
  89 2019-12-11  Alan Modra  <amodra@gmail.com>
  90
  91         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  92
  93 2019-12-11  Alan Modra  <amodra@gmail.com>
  94
  95         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  96
  97 2019-12-11  Alan Modra  <amodra@gmail.com>
  98
  99         * m68k-dis.c (COERCE32): Cast value first.
 100         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 101
 102 2019-12-11  Alan Modra  <amodra@gmail.com>
 103
 104         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 105         (bfd_h8_disassemble): Likewise.
 106
 107 2019-12-11  Alan Modra  <amodra@gmail.com>
 108
 109         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 110         past end of operands array.
 111
 112 2019-12-11  Alan Modra  <amodra@gmail.com>
 113
 114         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 115         overflow when collecting bytes of a number.
 116
 117 2019-12-11  Alan Modra  <amodra@gmail.com>
 118
 119         * cris-dis.c (print_with_operands): Avoid signed integer
 120         overflow when collecting bytes of a 32-bit integer.
 121
 122 2019-12-11  Alan Modra  <amodra@gmail.com>
 123
 124         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 125         (cr16_match_opcode): Delete duplicate bcond test.
 126
 127 2019-12-11  Alan Modra  <amodra@gmail.com>
 128
 129         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 130         (SIGNBIT): New.
 131         (MASKBITS, SIGNEXTEND): Rewrite.
 132         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 133         unsigned arithmetic, instead assign result of SIGNEXTEND back
 134         to x.
 135         (fmtconst_val): Use 1u in shift expression.
 136
 137 2019-12-11  Alan Modra  <amodra@gmail.com>
 138
 139         * arc-dis.c (find_format_from_table): Use ull constant when
 140         shifting by up to 32.
 141
 142 2019-12-11  Alan Modra  <amodra@gmail.com>
 143
 144         PR 25270
 145         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 146         false when field is zero for sve_size_tsz_bhs.
 147
 148 2019-12-11  Alan Modra  <amodra@gmail.com>
 149
 150         * epiphany-ibld.c: Regenerate.
 151
 152 2019-12-10  Alan Modra  <amodra@gmail.com>
 153
 154         PR 24960
 155         * disassemble.c (disassemble_free_target): New function.
 156
 157 2019-12-10  Alan Modra  <amodra@gmail.com>
 158
 159         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 160         * disassemble.c (disassemble_init_for_target): Likewise.
 161         * bpf-dis.c: Regenerate.
 162         * epiphany-dis.c: Regenerate.
 163         * fr30-dis.c: Regenerate.
 164         * frv-dis.c: Regenerate.
 165         * ip2k-dis.c: Regenerate.
 166         * iq2000-dis.c: Regenerate.
 167         * lm32-dis.c: Regenerate.
 168         * m32c-dis.c: Regenerate.
 169         * m32r-dis.c: Regenerate.
 170         * mep-dis.c: Regenerate.
 171         * mt-dis.c: Regenerate.
 172         * or1k-dis.c: Regenerate.
 173         * xc16x-dis.c: Regenerate.
 174         * xstormy16-dis.c: Regenerate.
 175
 176 2019-12-10  Alan Modra  <amodra@gmail.com>
 177
 178         * ppc-dis.c (private): Delete variable.
 179         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 180         (powerpc_init_dialect): Don't use global private.
 181
 182 2019-12-10  Alan Modra  <amodra@gmail.com>
 183
 184         * s12z-opc.c: Formatting.
 185
 186 2019-12-08  Alan Modra  <amodra@gmail.com>
 187
 188         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 189         registers.
 190
 191 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 192
 193         * aarch64-tbl.h (aarch64_feature_crypto,
 194         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 195         CRYPTO_V8_2_INSN): Delete.
 196
 197 2019-12-05  Alan Modra  <amodra@gmail.com>
 198
 199         PR 25249
 200         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 201         (struct string_buf): New.
 202         (strbuf): New function.
 203         (get_field): Use strbuf rather than strdup of local temp.
 204         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 205         (get_field_rfsl, get_field_imm15): Likewise.
 206         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 207         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 208         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 209         get_field functions.
 210
 211 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 214         * i386-tbl.h: Re-generate.
 215
 216 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 219
 220 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 223         forms.
 224         (xbegin): Drop DefaultSize.
 225         * i386-tbl.h: Re-generate.
 226
 227 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 228
 229         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 230         Change the coproc CRC conditions to use the extension
 231         feature set, second word, base on ARM_EXT2_CRC.
 232
 233 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 236         * i386-tbl.h: Re-generate.
 237
 238 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 241         JumpInterSegment, and JumpAbsolute entries.
 242         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 243         JUMP_ABSOLUTE): Define.
 244         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 245         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 246         fields.
 247         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 248         JumpInterSegment): Define.
 249         * i386-tbl.h: Re-generate.
 250
 251 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-gen.c (operand_type_init): Remove
 254         OPERAND_TYPE_JUMPABSOLUTE entry.
 255         (opcode_modifiers): Add JumpAbsolute entry.
 256         (operand_types): Remove JumpAbsolute entry.
 257         * i386-opc.h (JumpAbsolute): Move between enums.
 258         (struct i386_opcode_modifier): Add jumpabsolute field.
 259         (union i386_operand_type): Remove jumpabsolute field.
 260         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 261         * i386-init.h, i386-tbl.h: Re-generate.
 262
 263 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 266         (operand_types): Remove AnySize entry.
 267         * i386-opc.h (AnySize): Move between enums.
 268         (struct i386_opcode_modifier): Add anysize field.
 269         (OTUnused): Un-comment.
 270         (union i386_operand_type): Remove anysize field.
 271         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 272         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 273         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 274         AnySize.
 275         * i386-tbl.h: Re-generate.
 276
 277 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 278
 279         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 280         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 281         use the floating point register (FPR).
 282
 283 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 284
 285         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 286         cmode 1101.
 287         (is_mve_encoding_conflict): Update cmode conflict checks for
 288         MVE_VMVN_IMM.
 289
 290 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 293         entry.
 294         (operand_types): Remove EsSeg entry.
 295         (main): Replace stale use of OTMax.
 296         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 297         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 298         (EsSeg): Delete.
 299         (OTUnused): Comment out.
 300         (union i386_operand_type): Remove esseg field.
 301         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 302         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 303         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 304         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 305         * i386-init.h, i386-tbl.h: Re-generate.
 306
 307 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-gen.c (operand_instances): Add RegB entry.
 310         * i386-opc.h (enum operand_instance): Add RegB.
 311         * i386-opc.tbl (RegC, RegD, RegB): Define.
 312         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 313         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 314         monitorx, mwaitx): Drop ImmExt and convert encodings
 315         accordingly.
 316         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 317         (edx, rdx): Add Instance=RegD.
 318         (ebx, rbx): Add Instance=RegB.
 319         * i386-tbl.h: Re-generate.
 320
 321 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-gen.c (operand_type_init): Adjust
 324         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 325         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 326         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 327         (operand_instances): New.
 328         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 329         (output_operand_type): New parameter "instance". Process it.
 330         (process_i386_operand_type): New local variable "instance".
 331         (main): Adjust static assertions.
 332         * i386-opc.h (INSTANCE_WIDTH): Define.
 333         (enum operand_instance): New.
 334         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 335         (union i386_operand_type): Replace acc, inoutportreg, and
 336         shiftcount by instance.
 337         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 338         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 339         Add Instance=.
 340         * i386-init.h, i386-tbl.h: Re-generate.
 341
 342 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 343
 344         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 345         smaxp/sminp entries' "tied_operand" field to 2.
 346
 347 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 348
 349         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 350         "index" local variable by that of the already existing "num".
 351
 352 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 353
 354         PR gas/25167
 355         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 356         * i386-tbl.h: Regenerated.
 357
 358 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-gen.c (operand_type_init): Add Class= to
 361         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 362         OPERAND_TYPE_REGBND entry.
 363         (operand_classes): Add RegMask and RegBND entries.
 364         (operand_types): Drop RegMask and RegBND entry.
 365         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 366         (RegMask, RegBND): Delete.
 367         (union i386_operand_type): Remove regmask and regbnd fields.
 368         * i386-opc.tbl (RegMask, RegBND): Define.
 369         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 370         Class=RegBND.
 371         * i386-init.h, i386-tbl.h: Re-generate.
 372
 373 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-gen.c (operand_type_init): Add Class= to
 376         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 377         OPERAND_TYPE_REGZMM entries.
 378         (operand_classes): Add RegMMX and RegSIMD entries.
 379         (operand_types): Drop RegMMX and RegSIMD entries.
 380         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 381         (RegMMX, RegSIMD): Delete.
 382         (union i386_operand_type): Remove regmmx and regsimd fields.
 383         * i386-opc.tbl (RegMMX): Define.
 384         (RegXMM, RegYMM, RegZMM): Add Class=.
 385         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 386         Class=RegSIMD.
 387         * i386-init.h, i386-tbl.h: Re-generate.
 388
 389 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 390
 391         * i386-gen.c (operand_type_init): Add Class= to
 392         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 393         entries.
 394         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 395         (operand_types): Drop Control, Debug, and Test entries.
 396         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 397         (Control, Debug, Test): Delete.
 398         (union i386_operand_type): Remove control, debug, and test
 399         fields.
 400         * i386-opc.tbl (Control, Debug, Test): Define.
 401         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 402         Class=RegDR, and Test by Class=RegTR.
 403         * i386-init.h, i386-tbl.h: Re-generate.
 404
 405 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-gen.c (operand_type_init): Add Class= to
 408         OPERAND_TYPE_SREG entry.
 409         (operand_classes): Add SReg entry.
 410         (operand_types): Drop SReg entry.
 411         * i386-opc.h (enum operand_class): Add SReg.
 412         (SReg): Delete.
 413         (union i386_operand_type): Remove sreg field.
 414         * i386-opc.tbl (SReg): Define.
 415         * i386-reg.tbl: Replace SReg by Class=SReg.
 416         * i386-init.h, i386-tbl.h: Re-generate.
 417
 418 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-gen.c (operand_type_init): Add Class=. New
 421         OPERAND_TYPE_ANYIMM entry.
 422         (operand_classes): New.
 423         (operand_types): Drop Reg entry.
 424         (output_operand_type): New parameter "class". Process it.
 425         (process_i386_operand_type): New local variable "class".
 426         (main): Adjust static assertions.
 427         * i386-opc.h (CLASS_WIDTH): Define.
 428         (enum operand_class): New.
 429         (Reg): Replace by Class. Adjust comment.
 430         (union i386_operand_type): Replace reg by class.
 431         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 432         Class=.
 433         * i386-reg.tbl: Replace Reg by Class=Reg.
 434         * i386-init.h: Re-generate.
 435
 436 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 437
 438         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 439         (aarch64_opcode_table): Add data gathering hint mnemonic.
 440         * opcodes/aarch64-dis-2.c: Account for new instruction.
 441
 442 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 443
 444         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 445
 446
 447 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 448
 449         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 450         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 451         aarch64_feature_f64mm): New feature sets.
 452         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 453         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 454         instructions.
 455         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 456         macros.
 457         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 458         (OP_SVE_QQQ): New qualifier.
 459         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 460         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 461         the movprfx constraint.
 462         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 463         (aarch64_opcode_table): Define new instructions smmla,
 464         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 465         uzip{1/2}, trn{1/2}.
 466         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 467         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 468         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 469         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 470         Account for new instructions.
 471         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 472         S4x32 operand.
 473         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 474
 475 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 476 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 477
 478         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 479         Armv8.6-A.
 480         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 481         (neon_opcodes): Add bfloat SIMD instructions.
 482         (print_insn_coprocessor): Add new control character %b to print
 483         condition code without checking cp_num.
 484         (print_insn_neon): Account for BFloat16 instructions that have no
 485         special top-byte handling.
 486
 487 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 488 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 489
 490         * arm-dis.c (print_insn_coprocessor,
 491         print_insn_generic_coprocessor): Create wrapper functions around
 492         the implementation of the print_insn_coprocessor control codes.
 493         (print_insn_coprocessor_1): Original print_insn_coprocessor
 494         function that now takes which array to look at as an argument.
 495         (print_insn_arm): Use both print_insn_coprocessor and
 496         print_insn_generic_coprocessor.
 497         (print_insn_thumb32): As above.
 498
 499 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 500 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 501
 502         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 503         in reglane special case.
 504         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 505         aarch64_find_next_opcode): Account for new instructions.
 506         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 507         in reglane special case.
 508         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 509         new AARCH64_OPND_QLF_S_2H qualifier.
 510         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 511         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 512         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 513         sets.
 514         (BFLOAT_SVE, BFLOAT): New feature set macros.
 515         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 516         instructions.
 517         (aarch64_opcode_table): Define new instructions bfdot,
 518         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 519         bfcvtn2, bfcvt.
 520
 521 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 522 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 523
 524         * aarch64-tbl.h (ARMV8_6): New macro.
 525
 526 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-dis.c (prefix_table): Add mcommit.
 529         (rm_table): Add rdpru.
 530         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 531         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 532         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 533         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 534         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 535         * i386-opc.tbl (mcommit, rdpru): New.
 536         * i386-init.h, i386-tbl.h: Re-generate.
 537
 538 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 541         "names32" instead.
 542         (OP_Monitor): Drop local variable "op1_names", re-purpose
 543         "names" for it instead, and replace former "names" uses by
 544         "names32" ones.
 545
 546 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 547
 548         PR/gas 25167
 549         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 550         operand-less forms.
 551         * opcodes/i386-tbl.h: Re-generate.
 552
 553 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-dis.c (OP_Mwaitx): Delete.
 556         (prefix_table): Use OP_Mwait for mwaitx entry.
 557         (OP_Mwait): Also handle mwaitx.
 558
 559 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 562         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 563         (prefix_table): Add respective entries.
 564         (rm_table): Link to those entries.
 565
 566 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 569         (REG_0F1C_P_0_MOD_0): ... this.
 570         (REG_0F1E_MOD_3): Rename to ...
 571         (REG_0F1E_P_1_MOD_3): ... this.
 572         (RM_0F01_REG_5): Rename to ...
 573         (RM_0F01_REG_5_MOD_3): ... this.
 574         (RM_0F01_REG_7): Rename to ...
 575         (RM_0F01_REG_7_MOD_3): ... this.
 576         (RM_0F1E_MOD_3_REG_7): Rename to ...
 577         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 578         (RM_0FAE_REG_6): Rename to ...
 579         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 580         (RM_0FAE_REG_7): Rename to ...
 581         (RM_0FAE_REG_7_MOD_3): ... this.
 582         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 583         (PREFIX_0F01_REG_5_MOD_0): ... this.
 584         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 585         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 586         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 587         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 588         (PREFIX_0FAE_REG_0): Rename to ...
 589         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 590         (PREFIX_0FAE_REG_1): Rename to ...
 591         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 592         (PREFIX_0FAE_REG_2): Rename to ...
 593         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 594         (PREFIX_0FAE_REG_3): Rename to ...
 595         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 596         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 597         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 598         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 599         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 600         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 601         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 602         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 603         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 604         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 605         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 606         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 607         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 608         (PREFIX_0FAE_REG_7): Rename to ...
 609         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 610         (PREFIX_MOD_0_0FC3): Rename to ...
 611         (PREFIX_0FC3_MOD_0): ... this.
 612         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 613         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 614         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 615         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 616         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 617         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 618         (reg_table, prefix_table, mod_table, rm_table): Adjust
 619         accordingly.
 620
 621 2019-11-04  Nick Clifton  <nickc@redhat.com>
 622
 623         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 624         of a v850 system register.  Move the v850_sreg_names array into
 625         this function.
 626         (get_v850_reg_name): Likewise for ordinary register names.
 627         (get_v850_vreg_name): Likewise for vector register names.
 628         (get_v850_cc_name): Likewise for condition codes.
 629         * get_v850_float_cc_name): Likewise for floating point condition
 630         codes.
 631         (get_v850_cacheop_name): Likewise for cache-ops.
 632         (get_v850_prefop_name): Likewise for pref-ops.
 633         (disassemble): Use the new accessor functions.
 634
 635 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 636
 637         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 638         immediate for the writeback form of ldraa/ldrab if it is 0.
 639         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 640         * aarch64-opc-2.c: Regenerated.
 641
 642 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 643
 644         * i386-gen.c (operand_type_shorthands): Delete.
 645         (operand_type_init): Expand previous shorthands.
 646         (set_bitfield_from_shorthand): Rename back to ...
 647         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 648         of operand_type_init[].
 649         (set_bitfield): Adjust call to the above function.
 650         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 651         RegXMM, RegYMM, RegZMM): Define.
 652         * i386-reg.tbl: Expand prior shorthands.
 653
 654 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 655
 656         * i386-gen.c (output_i386_opcode): Change order of fields
 657         emitted to output.
 658         * i386-opc.h (struct insn_template): Move operands field.
 659         Convert extension_opcode field to unsigned short.
 660         * i386-tbl.h: Re-generate.
 661
 662 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 665         of W.
 666         * i386-opc.h (W): Extend comment.
 667         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 668         general purpose variants not allowing for byte operands.
 669         * i386-tbl.h: Re-generate.
 670
 671 2019-10-29  Nick Clifton  <nickc@redhat.com>
 672
 673         * tic30-dis.c (print_branch): Correct size of operand array.
 674
 675 2019-10-29  Nick Clifton  <nickc@redhat.com>
 676
 677         * d30v-dis.c (print_insn): Check that operand index is valid
 678         before attempting to access the operands array.
 679
 680 2019-10-29  Nick Clifton  <nickc@redhat.com>
 681
 682         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 683         locating the bit to be tested.
 684
 685 2019-10-29  Nick Clifton  <nickc@redhat.com>
 686
 687         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 688         values.
 689         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 690         (print_insn_s12z):  Check for illegal size values.
 691
 692 2019-10-28  Nick Clifton  <nickc@redhat.com>
 693
 694         * csky-dis.c (csky_chars_to_number): Check for a negative
 695         count. Use an unsigned integer to construct the return value.
 696
 697 2019-10-28  Nick Clifton  <nickc@redhat.com>
 698
 699         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 700         operand buffer.  Set value to 15 not 13.
 701         (get_register_operand): Use OPERAND_BUFFER_LEN.
 702         (get_indirect_operand): Likewise.
 703         (print_two_operand): Likewise.
 704         (print_three_operand): Likewise.
 705         (print_oar_insn): Likewise.
 706
 707 2019-10-28  Nick Clifton  <nickc@redhat.com>
 708
 709         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 710         (bit_extract_simple): Likewise.
 711         (bit_copy): Likewise.
 712         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 713         index_offset array are not accessed.
 714
 715 2019-10-28  Nick Clifton  <nickc@redhat.com>
 716
 717         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 718         operand.
 719
 720 2019-10-25  Nick Clifton  <nickc@redhat.com>
 721
 722         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 723         access to opcodes.op array element.
 724
 725 2019-10-23  Nick Clifton  <nickc@redhat.com>
 726
 727         * rx-dis.c (get_register_name): Fix spelling typo in error
 728         message.
 729         (get_condition_name, get_flag_name, get_double_register_name)
 730         (get_double_register_high_name, get_double_register_low_name)
 731         (get_double_control_register_name, get_double_condition_name)
 732         (get_opsize_name, get_size_name): Likewise.
 733
 734 2019-10-22  Nick Clifton  <nickc@redhat.com>
 735
 736         * rx-dis.c (get_size_name): New function.  Provides safe
 737         access to name array.
 738         (get_opsize_name): Likewise.
 739         (print_insn_rx): Use the accessor functions.
 740
 741 2019-10-16  Nick Clifton  <nickc@redhat.com>
 742
 743         * rx-dis.c (get_register_name): New function.  Provides safe
 744         access to name array.
 745         (get_condition_name, get_flag_name, get_double_register_name)
 746         (get_double_register_high_name, get_double_register_low_name)
 747         (get_double_control_register_name, get_double_condition_name):
 748         Likewise.
 749         (print_insn_rx): Use the accessor functions.
 750
 751 2019-10-09  Nick Clifton  <nickc@redhat.com>
 752
 753         PR 25041
 754         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 755         instructions.
 756
 757 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 758
 759         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 760         (cmpsd): Likewise. Move EsSeg to other operand.
 761         * opcodes/i386-tbl.h: Re-generate.
 762
 763 2019-09-23  Alan Modra  <amodra@gmail.com>
 764
 765         * m68k-dis.c: Include cpu-m68k.h
 766
 767 2019-09-23  Alan Modra  <amodra@gmail.com>
 768
 769         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 770         "elf/mips.h" earlier.
 771
 772 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 773
 774         PR gas/25012
 775         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 776         with SReg operand.
 777         * i386-tbl.h: Re-generate.
 778
 779 2019-09-18  Alan Modra  <amodra@gmail.com>
 780
 781         * arc-ext.c: Update throughout for bfd section macro changes.
 782
 783 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 784
 785         * Makefile.in: Re-generate.
 786         * configure: Re-generate.
 787
 788 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 789
 790         * riscv-opc.c (riscv_opcodes): Change subset field
 791         to insn_class field for all instructions.
 792         (riscv_insn_types): Likewise.
 793
 794 2019-09-16  Phil Blundell  <pb@pbcl.net>
 795
 796         * configure: Regenerated.
 797
 798 2019-09-10  Miod Vallat  <miod@online.fr>
 799
 800         PR 24982
 801         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 802
 803 2019-09-09  Phil Blundell  <pb@pbcl.net>
 804
 805         binutils 2.33 branch created.
 806
 807 2019-09-03  Nick Clifton  <nickc@redhat.com>
 808
 809         PR 24961
 810         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 811         greater than zero before indexing via (bufcnt -1).
 812
 813 2019-09-03  Nick Clifton  <nickc@redhat.com>
 814
 815         PR 24958
 816         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 817         (MAX_SPEC_REG_NAME_LEN): Define.
 818         (struct mmix_dis_info): Use defined constants for array lengths.
 819         (get_reg_name): New function.
 820         (get_sprec_reg_name): New function.
 821         (print_insn_mmix): Use new functions.
 822
 823 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 824
 825         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 826         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 827         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 828
 829 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 830
 831         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 832         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 833         (aarch64_sys_reg_supported_p): Update checks for the above.
 834
 835 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 836
 837         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 838         cases MVE_SQRSHRL and MVE_UQRSHLL.
 839         (print_insn_mve): Add case for specifier 'k' to check
 840         specific bit of the instruction.
 841
 842 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 843
 844         PR 24854
 845         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 846         encountering an unknown machine type.
 847         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 848         cases return -1 rather than calling abort.
 849
 850 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 853         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 854         IgnoreSize.
 855         * i386-tbl.h: Re-generate.
 856
 857 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 858
 859         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 860         instructions.
 861
 862 2019-07-30  Mel Chen <mel.chen@sifive.com>
 863
 864         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 865         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 866
 867         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 868         fscsr.
 869
 870 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 871
 872         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 873         and MPY class instructions.
 874         (parse_option): Add nps400 option.
 875         (print_arc_disassembler_options): Add nps400 info.
 876
 877 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 878
 879         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 880         (bspop): Likewise.
 881         (modapp): Likewise.
 882         * arc-opc.c (RAD_CHK): Add.
 883         * arc-tbl.h: Regenerate.
 884
 885 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 886
 887         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 888         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 889
 890 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 891
 892         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 893         instructions as UNPREDICTABLE.
 894
 895 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 896
 897         * bpf-desc.c: Regenerated.
 898
 899 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-gen.c (static_assert): Define.
 902         (main): Use it.
 903         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 904         (Opcode_Modifier_Num): ... this.
 905         (Mem): Delete.
 906
 907 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-gen.c (operand_types): Move RegMem ...
 910         (opcode_modifiers): ... here.
 911         * i386-opc.h (RegMem): Move to opcode modifer enum.
 912         (union i386_operand_type): Move regmem field ...
 913         (struct i386_opcode_modifier): ... here.
 914         * i386-opc.tbl (RegMem): Define.
 915         (mov, movq): Move RegMem on segment, control, debug, and test
 916         register flavors.
 917         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 918         to non-SSE2AVX flavor.
 919         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 920         Move RegMem on register only flavors. Drop IgnoreSize from
 921         legacy encoding flavors.
 922         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 923         flavors.
 924         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 925         register only flavors.
 926         (vmovd): Move RegMem and drop IgnoreSize on register only
 927         flavor. Change opcode and operand order to store form.
 928         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 929
 930 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 933         entries.
 934         * i386-opc.h (SReg2, SReg3): Replace by ...
 935         (SReg): ... this.
 936         (union i386_operand_type): Replace sreg fields.
 937         * i386-opc.tbl (mov, ): Use SReg.
 938         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 939         register flavors.
 940         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 941         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 942
 943 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 944
 945         * bpf-desc.c: Regenerate.
 946         * bpf-opc.c: Likewise.
 947         * bpf-opc.h: Likewise.
 948
 949 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 950
 951         * bpf-desc.c: Regenerate.
 952         * bpf-opc.c: Likewise.
 953
 954 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 955
 956         * arm-dis.c (print_insn_coprocessor): Rename index to
 957         index_operand.
 958
 959 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 960
 961         * riscv-opc.c (riscv_insn_types): Add r4 type.
 962
 963         * riscv-opc.c (riscv_insn_types): Add b and j type.
 964
 965         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 966         format for sb type and correct s type.
 967
 968 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 969
 970         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 971         SVE FMOV alias of FCPY.
 972
 973 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 974
 975         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 976         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 977
 978 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 979
 980         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 981         registers in an instruction prefixed by MOVPRFX.
 982
 983 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 984
 985         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 986         sve_size_13 icode to account for variant behaviour of
 987         pmull{t,b}.
 988         * aarch64-dis-2.c: Regenerate.
 989         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 990         sve_size_13 icode to account for variant behaviour of
 991         pmull{t,b}.
 992         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 993         (OP_SVE_VVV_Q_D): Add new qualifier.
 994         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 995         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 996         AES and those not.
 997
 998 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 999
1000         * opcodes/i386-gen.c (operand_type_init): Remove
1001         OPERAND_TYPE_VEC_IMM4 entry.
1002         (operand_types): Remove Vec_Imm4.
1003         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1004         (union i386_operand_type): Remove vec_imm4.
1005         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1006         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1007
1008 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1011         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1012         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1013         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1014         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1015         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1016         * i386-tbl.h: Re-generate.
1017
1018 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1019
1020         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1021         register operands.
1022         * i386-tbl.h: Re-generate.
1023
1024 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1025
1026         * i386-opc.tbl (C): New.
1027         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1028         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1029         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1030         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1031         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1032         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1033         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1034         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1035         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1036         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1037         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1038         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1039         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1040         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1041         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1042         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1043         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1044         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1045         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1046         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1047         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1048         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1049         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1050         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1051         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1052         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1053         flavors.
1054         * i386-tbl.h: Re-generate.
1055
1056 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1059         register operands.
1060         * i386-tbl.h: Re-generate.
1061
1062 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1065         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1066         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1067         * i386-tbl.h: Re-generate.
1068
1069 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1070
1071         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1072         Disp8MemShift from register only templates.
1073         * i386-tbl.h: Re-generate.
1074
1075 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1076
1077         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1078         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1079         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1080         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1081         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1082         EVEX_W_0F11_P_3_M_1): Delete.
1083         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1084         EVEX_W_0F11_P_3): New.
1085         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1086         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1087         MOD_EVEX_0F11_PREFIX_3 table entries.
1088         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1089         PREFIX_EVEX_0F11 table entries.
1090         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1091         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1092         EVEX_W_0F11_P_3_M_{0,1} table entries.
1093
1094 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1097         Delete.
1098
1099 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1100
1101         PR binutils/24719
1102         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1103         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1104         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1105         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1106         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1107         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1108         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1109         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1110         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1111         PREFIX_EVEX_0F38C6_REG_6 entries.
1112         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1113         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1114         EVEX_W_0F38C7_R_6_P_2 entries.
1115         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1116         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1117         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1118         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1119         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1120         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1121         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1122
1123 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1124
1125         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1126         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1127         VEX_LEN_0F2D_P_3): Delete.
1128         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1129         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1130         (prefix_table): ... here.
1131
1132 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-dis.c (Iq): Delete.
1135         (Id): New.
1136         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1137         TBM insns.
1138         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1139         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1140         (OP_E_memory): Also honor needindex when deciding whether an
1141         address size prefix needs printing.
1142         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1143
1144 2019-06-26  Jim Wilson  <jimw@sifive.com>
1145
1146         PR binutils/24739
1147         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1148         Set info->display_endian to info->endian_code.
1149
1150 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1151
1152         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1153         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1154         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1155         OPERAND_TYPE_ACC64 entries.
1156         * i386-init.h: Re-generate.
1157
1158 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1159
1160         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1161         Delete.
1162         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1163         of dqa_mode.
1164         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1165         entries here.
1166         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1167         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1168
1169 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1170
1171         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1172         variables.
1173
1174 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1177         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1178         movnti.
1179         * i386-opc.tbl (movnti): Add IgnoreSize.
1180         * i386-tbl.h: Re-generate.
1181
1182 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1183
1184         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1185         * i386-tbl.h: Re-generate.
1186
1187 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1188
1189         * i386-dis-evex.h: Break into ...
1190         * i386-dis-evex-len.h: New file.
1191         * i386-dis-evex-mod.h: Likewise.
1192         * i386-dis-evex-prefix.h: Likewise.
1193         * i386-dis-evex-reg.h: Likewise.
1194         * i386-dis-evex-w.h: Likewise.
1195         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1196         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1197         i386-dis-evex-mod.h.
1198
1199 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1200
1201         PR binutils/24700
1202         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1203         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1204         EVEX_W_0F385B_P_2.
1205         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1206         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1207         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1208         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1209         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1210         EVEX_LEN_0F385B_P_2_W_1.
1211         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1212         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1213         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1214         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1215         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1216         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1217         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1218         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1219         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1220         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1221
1222 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1223
1224         PR binutils/24691
1225         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1226         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1227         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1228         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1229         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1230         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1231         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1232         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1233         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1234         EVEX_LEN_0F3A43_P_2_W_1.
1235         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1236         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1237         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1238         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1239         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1240         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1241         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1242         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1243         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1244         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1245         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1246         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1247
1248 2019-06-14  Nick Clifton  <nickc@redhat.com>
1249
1250         * po/fr.po; Updated French translation.
1251
1252 2019-06-13  Stafford Horne  <shorne@gmail.com>
1253
1254         * or1k-asm.c: Regenerated.
1255         * or1k-desc.c: Regenerated.
1256         * or1k-desc.h: Regenerated.
1257         * or1k-dis.c: Regenerated.
1258         * or1k-ibld.c: Regenerated.
1259         * or1k-opc.c: Regenerated.
1260         * or1k-opc.h: Regenerated.
1261         * or1k-opinst.c: Regenerated.
1262
1263 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1264
1265         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1266
1267 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         PR binutils/24633
1270         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1271         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1272         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1273         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1274         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1275         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1276         EVEX_LEN_0F3A1B_P_2_W_1.
1277         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1278         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1279         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1280         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1281         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1282         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1283         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1284         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1285
1286 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1287
1288         PR binutils/24626
1289         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1290         EVEX.vvvv when disassembling VEX and EVEX instructions.
1291         (OP_VEX): Set vex.register_specifier to 0 after readding
1292         vex.register_specifier.
1293         (OP_Vex_2src_1): Likewise.
1294         (OP_Vex_2src_2): Likewise.
1295         (OP_LWP_E): Likewise.
1296         (OP_EX_Vex): Don't check vex.register_specifier.
1297         (OP_XMM_Vex): Likewise.
1298
1299 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1300             Lili Cui  <lili.cui@intel.com>
1301
1302         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1303         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1304         instructions.
1305         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1306         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1307         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1308         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1309         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1310         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1311         * i386-init.h: Regenerated.
1312         * i386-tbl.h: Likewise.
1313
1314 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1315             Lili Cui  <lili.cui@intel.com>
1316
1317         * doc/c-i386.texi: Document enqcmd.
1318         * testsuite/gas/i386/enqcmd-intel.d: New file.
1319         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1320         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1321         * testsuite/gas/i386/enqcmd.d: Likewise.
1322         * testsuite/gas/i386/enqcmd.s: Likewise.
1323         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1324         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1325         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1326         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1327         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1328         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1329         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1330         and x86-64-enqcmd.
1331
1332 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1333
1334         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1335
1336 2019-06-03  Alan Modra  <amodra@gmail.com>
1337
1338         * ppc-dis.c (prefix_opcd_indices): Correct size.
1339
1340 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1341
1342         PR gas/24625
1343         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1344         Disp8ShiftVL.
1345         * i386-tbl.h: Regenerated.
1346
1347 2019-05-24  Alan Modra  <amodra@gmail.com>
1348
1349         * po/POTFILES.in: Regenerate.
1350
1351 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1352             Alan Modra  <amodra@gmail.com>
1353
1354         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1355         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1356         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1357         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1358         XTOP>): Define and add entries.
1359         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1360         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1361         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1362         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1363
1364 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1365             Alan Modra  <amodra@gmail.com>
1366
1367         * ppc-dis.c (ppc_opts): Add "future" entry.
1368         (PREFIX_OPCD_SEGS): Define.
1369         (prefix_opcd_indices): New array.
1370         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1371         (lookup_prefix): New function.
1372         (print_insn_powerpc): Handle 64-bit prefix instructions.
1373         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1374         (PMRR, POWERXX): Define.
1375         (prefix_opcodes): New instruction table.
1376         (prefix_num_opcodes): New constant.
1377
1378 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1379
1380         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1381         * configure: Regenerated.
1382         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1383         and cpu/bpf.opc.
1384         (HFILES): Add bpf-desc.h and bpf-opc.h.
1385         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1386         bpf-ibld.c and bpf-opc.c.
1387         (BPF_DEPS): Define.
1388         * Makefile.in: Regenerated.
1389         * disassemble.c (ARCH_bpf): Define.
1390         (disassembler): Add case for bfd_arch_bpf.
1391         (disassemble_init_for_target): Likewise.
1392         (enum epbf_isa_attr): Define.
1393         * disassemble.h: extern print_insn_bpf.
1394         * bpf-asm.c: Generated.
1395         * bpf-opc.h: Likewise.
1396         * bpf-opc.c: Likewise.
1397         * bpf-ibld.c: Likewise.
1398         * bpf-dis.c: Likewise.
1399         * bpf-desc.h: Likewise.
1400         * bpf-desc.c: Likewise.
1401
1402 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1403
1404         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1405         and VMSR with the new operands.
1406
1407 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1408
1409         * arm-dis.c (enum mve_instructions): New enum
1410         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1411         and cneg.
1412         (mve_opcodes): New instructions as above.
1413         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1414         csneg and csel.
1415         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1416
1417 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1418
1419         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1420         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1421         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1422         uqshl, urshrl and urshr.
1423         (is_mve_okay_in_it): Add new instructions to TRUE list.
1424         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1425         (print_insn_mve): Updated to accept new %j,
1426         %<bitfield>m and %<bitfield>n patterns.
1427
1428 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1429
1430         * mips-opc.c (mips_builtin_opcodes): Change source register
1431         constraint for DAUI.
1432
1433 2019-05-20  Nick Clifton  <nickc@redhat.com>
1434
1435         * po/fr.po: Updated French translation.
1436
1437 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1438             Michael Collison <michael.collison@arm.com>
1439
1440         * arm-dis.c (thumb32_opcodes): Add new instructions.
1441         (enum mve_instructions): Likewise.
1442         (enum mve_undefined): Add new reasons.
1443         (is_mve_encoding_conflict): Handle new instructions.
1444         (is_mve_undefined): Likewise.
1445         (is_mve_unpredictable): Likewise.
1446         (print_mve_undefined): Likewise.
1447         (print_mve_size): Likewise.
1448
1449 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1450             Michael Collison <michael.collison@arm.com>
1451
1452         * arm-dis.c (thumb32_opcodes): Add new instructions.
1453         (enum mve_instructions): Likewise.
1454         (is_mve_encoding_conflict): Handle new instructions.
1455         (is_mve_undefined): Likewise.
1456         (is_mve_unpredictable): Likewise.
1457         (print_mve_size): Likewise.
1458
1459 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1460             Michael Collison <michael.collison@arm.com>
1461
1462         * arm-dis.c (thumb32_opcodes): Add new instructions.
1463         (enum mve_instructions): Likewise.
1464         (is_mve_encoding_conflict): Likewise.
1465         (is_mve_unpredictable): Likewise.
1466         (print_mve_size): Likewise.
1467
1468 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1469             Michael Collison <michael.collison@arm.com>
1470
1471         * arm-dis.c (thumb32_opcodes): Add new instructions.
1472         (enum mve_instructions): Likewise.
1473         (is_mve_encoding_conflict): Handle new instructions.
1474         (is_mve_undefined): Likewise.
1475         (is_mve_unpredictable): Likewise.
1476         (print_mve_size): Likewise.
1477
1478 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1479             Michael Collison <michael.collison@arm.com>
1480
1481         * arm-dis.c (thumb32_opcodes): Add new instructions.
1482         (enum mve_instructions): Likewise.
1483         (is_mve_encoding_conflict): Handle new instructions.
1484         (is_mve_undefined): Likewise.
1485         (is_mve_unpredictable): Likewise.
1486         (print_mve_size): Likewise.
1487         (print_insn_mve): Likewise.
1488
1489 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1490             Michael Collison <michael.collison@arm.com>
1491
1492         * arm-dis.c (thumb32_opcodes): Add new instructions.
1493         (print_insn_thumb32): Handle new instructions.
1494
1495 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1496             Michael Collison <michael.collison@arm.com>
1497
1498         * arm-dis.c (enum mve_instructions): Add new instructions.
1499         (enum mve_undefined): Add new reasons.
1500         (is_mve_encoding_conflict): Handle new instructions.
1501         (is_mve_undefined): Likewise.
1502         (is_mve_unpredictable): Likewise.
1503         (print_mve_undefined): Likewise.
1504         (print_mve_size): Likewise.
1505         (print_mve_shift_n): Likewise.
1506         (print_insn_mve): Likewise.
1507
1508 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1509             Michael Collison <michael.collison@arm.com>
1510
1511         * arm-dis.c (enum mve_instructions): Add new instructions.
1512         (is_mve_encoding_conflict): Handle new instructions.
1513         (is_mve_unpredictable): Likewise.
1514         (print_mve_rotate): Likewise.
1515         (print_mve_size): Likewise.
1516         (print_insn_mve): Likewise.
1517
1518 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1519             Michael Collison <michael.collison@arm.com>
1520
1521         * arm-dis.c (enum mve_instructions): Add new instructions.
1522         (is_mve_encoding_conflict): Handle new instructions.
1523         (is_mve_unpredictable): Likewise.
1524         (print_mve_size): Likewise.
1525         (print_insn_mve): Likewise.
1526
1527 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1528             Michael Collison <michael.collison@arm.com>
1529
1530         * arm-dis.c (enum mve_instructions): Add new instructions.
1531         (enum mve_undefined): Add new reasons.
1532         (is_mve_encoding_conflict): Handle new instructions.
1533         (is_mve_undefined): Likewise.
1534         (is_mve_unpredictable): Likewise.
1535         (print_mve_undefined): Likewise.
1536         (print_mve_size): Likewise.
1537         (print_insn_mve): Likewise.
1538
1539 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1540             Michael Collison <michael.collison@arm.com>
1541
1542         * arm-dis.c (enum mve_instructions): Add new instructions.
1543         (is_mve_encoding_conflict): Handle new instructions.
1544         (is_mve_undefined): Likewise.
1545         (is_mve_unpredictable): Likewise.
1546         (print_mve_size): Likewise.
1547         (print_insn_mve): Likewise.
1548
1549 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1550             Michael Collison <michael.collison@arm.com>
1551
1552         * arm-dis.c (enum mve_instructions): Add new instructions.
1553         (enum mve_unpredictable): Add new reasons.
1554         (enum mve_undefined): Likewise.
1555         (is_mve_okay_in_it): Handle new isntructions.
1556         (is_mve_encoding_conflict): Likewise.
1557         (is_mve_undefined): Likewise.
1558         (is_mve_unpredictable): Likewise.
1559         (print_mve_vmov_index): Likewise.
1560         (print_simd_imm8): Likewise.
1561         (print_mve_undefined): Likewise.
1562         (print_mve_unpredictable): Likewise.
1563         (print_mve_size): Likewise.
1564         (print_insn_mve): Likewise.
1565
1566 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1567             Michael Collison <michael.collison@arm.com>
1568
1569         * arm-dis.c (enum mve_instructions): Add new instructions.
1570         (enum mve_unpredictable): Add new reasons.
1571         (enum mve_undefined): Likewise.
1572         (is_mve_encoding_conflict): Handle new instructions.
1573         (is_mve_undefined): Likewise.
1574         (is_mve_unpredictable): Likewise.
1575         (print_mve_undefined): Likewise.
1576         (print_mve_unpredictable): Likewise.
1577         (print_mve_rounding_mode): Likewise.
1578         (print_mve_vcvt_size): Likewise.
1579         (print_mve_size): Likewise.
1580         (print_insn_mve): Likewise.
1581
1582 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1583             Michael Collison <michael.collison@arm.com>
1584
1585         * arm-dis.c (enum mve_instructions): Add new instructions.
1586         (enum mve_unpredictable): Add new reasons.
1587         (enum mve_undefined): Likewise.
1588         (is_mve_undefined): Handle new instructions.
1589         (is_mve_unpredictable): Likewise.
1590         (print_mve_undefined): Likewise.
1591         (print_mve_unpredictable): Likewise.
1592         (print_mve_size): Likewise.
1593         (print_insn_mve): Likewise.
1594
1595 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1596             Michael Collison <michael.collison@arm.com>
1597
1598         * arm-dis.c (enum mve_instructions): Add new instructions.
1599         (enum mve_undefined): Add new reasons.
1600         (insns): Add new instructions.
1601         (is_mve_encoding_conflict):
1602         (print_mve_vld_str_addr): New print function.
1603         (is_mve_undefined): Handle new instructions.
1604         (is_mve_unpredictable): Likewise.
1605         (print_mve_undefined): Likewise.
1606         (print_mve_size): Likewise.
1607         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1608         (print_insn_mve):  Handle new operands.
1609
1610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1611             Michael Collison <michael.collison@arm.com>
1612
1613         * arm-dis.c (enum mve_instructions): Add new instructions.
1614         (enum mve_unpredictable): Add new reasons.
1615         (is_mve_encoding_conflict): Handle new instructions.
1616         (is_mve_unpredictable): Likewise.
1617         (mve_opcodes): Add new instructions.
1618         (print_mve_unpredictable): Handle new reasons.
1619         (print_mve_register_blocks): New print function.
1620         (print_mve_size): Handle new instructions.
1621         (print_insn_mve): Likewise.
1622
1623 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1624             Michael Collison <michael.collison@arm.com>
1625
1626         * arm-dis.c (enum mve_instructions): Add new instructions.
1627         (enum mve_unpredictable): Add new reasons.
1628         (enum mve_undefined): Likewise.
1629         (is_mve_encoding_conflict): Handle new instructions.
1630         (is_mve_undefined): Likewise.
1631         (is_mve_unpredictable): Likewise.
1632         (coprocessor_opcodes): Move NEON VDUP from here...
1633         (neon_opcodes): ... to here.
1634         (mve_opcodes): Add new instructions.
1635         (print_mve_undefined):  Handle new reasons.
1636         (print_mve_unpredictable): Likewise.
1637         (print_mve_size): Handle new instructions.
1638         (print_insn_neon): Handle vdup.
1639         (print_insn_mve): Handle new operands.
1640
1641 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1642             Michael Collison <michael.collison@arm.com>
1643
1644         * arm-dis.c (enum mve_instructions): Add new instructions.
1645         (enum mve_unpredictable): Add new values.
1646         (mve_opcodes): Add new instructions.
1647         (vec_condnames): New array with vector conditions.
1648         (mve_predicatenames): New array with predicate suffixes.
1649         (mve_vec_sizename): New array with vector sizes.
1650         (enum vpt_pred_state): New enum with vector predication states.
1651         (struct vpt_block): New struct type for vpt blocks.
1652         (vpt_block_state): Global struct to keep track of state.
1653         (mve_extract_pred_mask): New helper function.
1654         (num_instructions_vpt_block): Likewise.
1655         (mark_outside_vpt_block): Likewise.
1656         (mark_inside_vpt_block): Likewise.
1657         (invert_next_predicate_state): Likewise.
1658         (update_next_predicate_state): Likewise.
1659         (update_vpt_block_state): Likewise.
1660         (is_vpt_instruction): Likewise.
1661         (is_mve_encoding_conflict): Add entries for new instructions.
1662         (is_mve_unpredictable): Likewise.
1663         (print_mve_unpredictable): Handle new cases.
1664         (print_instruction_predicate): Likewise.
1665         (print_mve_size): New function.
1666         (print_vec_condition): New function.
1667         (print_insn_mve): Handle vpt blocks and new print operands.
1668
1669 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1670
1671         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1672         8, 14 and 15 for Armv8.1-M Mainline.
1673
1674 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1675             Michael Collison <michael.collison@arm.com>
1676
1677         * arm-dis.c (enum mve_instructions): New enum.
1678         (enum mve_unpredictable): Likewise.
1679         (enum mve_undefined): Likewise.
1680         (struct mopcode32): New struct.
1681         (is_mve_okay_in_it): New function.
1682         (is_mve_architecture): Likewise.
1683         (arm_decode_field): Likewise.
1684         (arm_decode_field_multiple): Likewise.
1685         (is_mve_encoding_conflict): Likewise.
1686         (is_mve_undefined): Likewise.
1687         (is_mve_unpredictable): Likewise.
1688         (print_mve_undefined): Likewise.
1689         (print_mve_unpredictable): Likewise.
1690         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1691         (print_insn_mve): New function.
1692         (print_insn_thumb32): Handle MVE architecture.
1693         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1694
1695 2019-05-10  Nick Clifton  <nickc@redhat.com>
1696
1697         PR 24538
1698         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1699         end of the table prematurely.
1700
1701 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1702
1703         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1704         macros for R6.
1705
1706 2019-05-11  Alan Modra  <amodra@gmail.com>
1707
1708         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1709         when -Mraw is in effect.
1710
1711 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1712
1713         * aarch64-dis-2.c: Regenerate.
1714         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1715         (OP_SVE_BBB): New variant set.
1716         (OP_SVE_DDDD): New variant set.
1717         (OP_SVE_HHH): New variant set.
1718         (OP_SVE_HHHU): New variant set.
1719         (OP_SVE_SSS): New variant set.
1720         (OP_SVE_SSSU): New variant set.
1721         (OP_SVE_SHH): New variant set.
1722         (OP_SVE_SBBU): New variant set.
1723         (OP_SVE_DSS): New variant set.
1724         (OP_SVE_DHHU): New variant set.
1725         (OP_SVE_VMV_HSD_BHS): New variant set.
1726         (OP_SVE_VVU_HSD_BHS): New variant set.
1727         (OP_SVE_VVVU_SD_BH): New variant set.
1728         (OP_SVE_VVVU_BHSD): New variant set.
1729         (OP_SVE_VVV_QHD_DBS): New variant set.
1730         (OP_SVE_VVV_HSD_BHS): New variant set.
1731         (OP_SVE_VVV_HSD_BHS2): New variant set.
1732         (OP_SVE_VVV_BHS_HSD): New variant set.
1733         (OP_SVE_VV_BHS_HSD): New variant set.
1734         (OP_SVE_VVV_SD): New variant set.
1735         (OP_SVE_VVU_BHS_HSD): New variant set.
1736         (OP_SVE_VZVV_SD): New variant set.
1737         (OP_SVE_VZVV_BH): New variant set.
1738         (OP_SVE_VZV_SD): New variant set.
1739         (aarch64_opcode_table): Add sve2 instructions.
1740
1741 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1742
1743         * aarch64-asm-2.c: Regenerated.
1744         * aarch64-dis-2.c: Regenerated.
1745         * aarch64-opc-2.c: Regenerated.
1746         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1747         for SVE_SHLIMM_UNPRED_22.
1748         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1749         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1750         operand.
1751
1752 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1753
1754         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1755         sve_size_tsz_bhs iclass encode.
1756         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1757         sve_size_tsz_bhs iclass decode.
1758
1759 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1760
1761         * aarch64-asm-2.c: Regenerated.
1762         * aarch64-dis-2.c: Regenerated.
1763         * aarch64-opc-2.c: Regenerated.
1764         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1765         for SVE_Zm4_11_INDEX.
1766         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1767         (fields): Handle SVE_i2h field.
1768         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1769         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1770
1771 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1772
1773         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1774         sve_shift_tsz_bhsd iclass encode.
1775         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1776         sve_shift_tsz_bhsd iclass decode.
1777
1778 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1779
1780         * aarch64-asm-2.c: Regenerated.
1781         * aarch64-dis-2.c: Regenerated.
1782         * aarch64-opc-2.c: Regenerated.
1783         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1784         (aarch64_encode_variant_using_iclass): Handle
1785         sve_shift_tsz_hsd iclass encode.
1786         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1787         sve_shift_tsz_hsd iclass decode.
1788         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1789         for SVE_SHRIMM_UNPRED_22.
1790         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1791         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1792         operand.
1793
1794 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1795
1796         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1797         sve_size_013 iclass encode.
1798         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1799         sve_size_013 iclass decode.
1800
1801 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1802
1803         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1804         sve_size_bh iclass encode.
1805         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1806         sve_size_bh iclass decode.
1807
1808 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1809
1810         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1811         sve_size_sd2 iclass encode.
1812         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1813         sve_size_sd2 iclass decode.
1814         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1815         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1816
1817 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1818
1819         * aarch64-asm-2.c: Regenerated.
1820         * aarch64-dis-2.c: Regenerated.
1821         * aarch64-opc-2.c: Regenerated.
1822         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1823         for SVE_ADDR_ZX.
1824         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1825         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1826
1827 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1828
1829         * aarch64-asm-2.c: Regenerated.
1830         * aarch64-dis-2.c: Regenerated.
1831         * aarch64-opc-2.c: Regenerated.
1832         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1833         for SVE_Zm3_11_INDEX.
1834         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1835         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1836         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1837         fields.
1838         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1839
1840 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1841
1842         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1843         sve_size_hsd2 iclass encode.
1844         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1845         sve_size_hsd2 iclass decode.
1846         * aarch64-opc.c (fields): Handle SVE_size field.
1847         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1848
1849 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1850
1851         * aarch64-asm-2.c: Regenerated.
1852         * aarch64-dis-2.c: Regenerated.
1853         * aarch64-opc-2.c: Regenerated.
1854         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1855         for SVE_IMM_ROT3.
1856         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1857         (fields): Handle SVE_rot3 field.
1858         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1859         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1860
1861 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1862
1863         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1864         instructions.
1865
1866 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1867
1868         * aarch64-tbl.h
1869         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1870         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1871         aarch64_feature_sve2bitperm): New feature sets.
1872         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1873         for feature set addresses.
1874         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1875         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1876
1877 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1878             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1879
1880         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1881         argument and set ASE_EVA_R6 appropriately.
1882         (set_default_mips_dis_options): Pass ISA to above.
1883         (parse_mips_dis_option): Likewise.
1884         * mips-opc.c (EVAR6): New macro.
1885         (mips_builtin_opcodes): Add llwpe, scwpe.
1886
1887 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1888
1889         * aarch64-asm-2.c: Regenerated.
1890         * aarch64-dis-2.c: Regenerated.
1891         * aarch64-opc-2.c: Regenerated.
1892         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1893         AARCH64_OPND_TME_UIMM16.
1894         (aarch64_print_operand): Likewise.
1895         * aarch64-tbl.h (QL_IMM_NIL): New.
1896         (TME): New.
1897         (_TME_INSN): New.
1898         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1899
1900 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1901
1902         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1903
1904 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1905             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1906
1907         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1908
1909 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1910
1911         * s12z-opc.h: Add extern "C" bracketing to help
1912         users who wish to use this interface in c++ code.
1913
1914 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1915
1916         * s12z-opc.c (bm_decode): Handle bit map operations with the
1917         "reserved0" mode.
1918
1919 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1920
1921         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1922         specifier.  Add entries for VLDR and VSTR of system registers.
1923         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1924         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1925         of %J and %K format specifier.
1926
1927 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1928
1929         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1930         Add new entries for VSCCLRM instruction.
1931         (print_insn_coprocessor): Handle new %C format control code.
1932
1933 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1934
1935         * arm-dis.c (enum isa): New enum.
1936         (struct sopcode32): New structure.
1937         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1938         set isa field of all current entries to ANY.
1939         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1940         Only match an entry if its isa field allows the current mode.
1941
1942 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1943
1944         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1945         CLRM.
1946         (print_insn_thumb32): Add logic to print %n CLRM register list.
1947
1948 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1949
1950         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1951         and %Q patterns.
1952
1953 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1954
1955         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1956         (print_insn_thumb32): Edit the switch case for %Z.
1957
1958 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1959
1960         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1961
1962 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1963
1964         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1965
1966 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1967
1968         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1969
1970 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1971
1972         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1973         Arm register with r13 and r15 unpredictable.
1974         (thumb32_opcodes): New instructions for bfx and bflx.
1975
1976 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1977
1978         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1979
1980 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1981
1982         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1983
1984 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1985
1986         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1987
1988 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1989
1990         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1991
1992 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1993
1994         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1995         "optr". ("operator" is a reserved word in c++).
1996
1997 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1998
1999         * aarch64-opc.c (aarch64_print_operand): Add case for
2000         AARCH64_OPND_Rt_SP.
2001         (verify_constraints): Likewise.
2002         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2003         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2004         to accept Rt|SP as first operand.
2005         (AARCH64_OPERANDS): Add new Rt_SP.
2006         * aarch64-asm-2.c: Regenerated.
2007         * aarch64-dis-2.c: Regenerated.
2008         * aarch64-opc-2.c: Regenerated.
2009
2010 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2011
2012         * aarch64-asm-2.c: Regenerated.
2013         * aarch64-dis-2.c: Likewise.
2014         * aarch64-opc-2.c: Likewise.
2015         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2016
2017 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2018
2019         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2020
2021 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2022
2023         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2024         * i386-init.h: Regenerated.
2025
2026 2019-04-07  Alan Modra  <amodra@gmail.com>
2027
2028         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2029         op_separator to control printing of spaces, comma and parens
2030         rather than need_comma, need_paren and spaces vars.
2031
2032 2019-04-07  Alan Modra  <amodra@gmail.com>
2033
2034         PR 24421
2035         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2036         (print_insn_neon, print_insn_arm): Likewise.
2037
2038 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2039
2040         * i386-dis-evex.h (evex_table): Updated to support BF16
2041         instructions.
2042         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2043         and EVEX_W_0F3872_P_3.
2044         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2045         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2046         * i386-opc.h (enum): Add CpuAVX512_BF16.
2047         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2048         * i386-opc.tbl: Add AVX512 BF16 instructions.
2049         * i386-init.h: Regenerated.
2050         * i386-tbl.h: Likewise.
2051
2052 2019-04-05  Alan Modra  <amodra@gmail.com>
2053
2054         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2055         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2056         to favour printing of "-" branch hint when using the "y" bit.
2057         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2058
2059 2019-04-05  Alan Modra  <amodra@gmail.com>
2060
2061         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2062         opcode until first operand is output.
2063
2064 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2065
2066         PR gas/24349
2067         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2068         (valid_bo_post_v2): Add support for 'at' branch hints.
2069         (insert_bo): Only error on branch on ctr.
2070         (get_bo_hint_mask): New function.
2071         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2072         for inserting 'at' branch hints.
2073         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2074         for extracting 'at' branch hints.
2075         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2076         (BOE): Delete operand.
2077         (BOM, BOP): New operands.
2078         (RM): Update value.
2079         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2080         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2081         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2082         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2083         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2084         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2085         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2086         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2087         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2088         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2089         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2090         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2091         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2092         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2093         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2094         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2095         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2096         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2097         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2098         bttarl+>: New extended mnemonics.
2099
2100 2019-03-28  Alan Modra  <amodra@gmail.com>
2101
2102         PR 24390
2103         * ppc-opc.c (BTF): Define.
2104         (powerpc_opcodes): Use for mtfsb*.
2105         * ppc-dis.c (print_insn_powerpc): Print fields with both
2106         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2107
2108 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2109
2110         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2111         (mapping_symbol_for_insn): Implement new algorithm.
2112         (print_insn): Remove duplicate code.
2113
2114 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2115
2116         * aarch64-dis.c (print_insn_aarch64):
2117         Implement override.
2118
2119 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2120
2121         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2122         order.
2123
2124 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2125
2126         * aarch64-dis.c (last_stop_offset): New.
2127         (print_insn_aarch64): Use stop_offset.
2128
2129 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2130
2131         PR gas/24359
2132         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2133         CPU_ANY_AVX2_FLAGS.
2134         * i386-init.h: Regenerated.
2135
2136 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2137
2138         PR gas/24348
2139         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2140         vmovdqu16, vmovdqu32 and vmovdqu64.
2141         * i386-tbl.h: Regenerated.
2142
2143 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2144
2145         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2146         from vstrszb, vstrszh, and vstrszf.
2147
2148 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2149
2150         * s390-opc.txt: Add instruction descriptions.
2151
2152 2019-02-08  Jim Wilson  <jimw@sifive.com>
2153
2154         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2155         <bne>: Likewise.
2156
2157 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2158
2159         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2160
2161 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2162
2163         PR binutils/23212
2164         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2165         * aarch64-opc.c (verify_elem_sd): New.
2166         (fields): Add FLD_sz entr.
2167         * aarch64-tbl.h (_SIMD_INSN): New.
2168         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2169         fmulx scalar and vector by element isns.
2170
2171 2019-02-07  Nick Clifton  <nickc@redhat.com>
2172
2173         * po/sv.po: Updated Swedish translation.
2174
2175 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2176
2177         * s390-mkopc.c (main): Accept arch13 as cpu string.
2178         * s390-opc.c: Add new instruction formats and instruction opcode
2179         masks.
2180         * s390-opc.txt: Add new arch13 instructions.
2181
2182 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2183
2184         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2185         (aarch64_opcode): Change encoding for stg, stzg
2186         st2g and st2zg.
2187         * aarch64-asm-2.c: Regenerated.
2188         * aarch64-dis-2.c: Regenerated.
2189         * aarch64-opc-2.c: Regenerated.
2190
2191 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2192
2193         * aarch64-asm-2.c: Regenerated.
2194         * aarch64-dis-2.c: Likewise.
2195         * aarch64-opc-2.c: Likewise.
2196         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2197
2198 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2199             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2200
2201         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2202         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2203         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2204         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2205         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2206         case for ldstgv_indexed.
2207         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2208         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2209         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2210         * aarch64-asm-2.c: Regenerated.
2211         * aarch64-dis-2.c: Regenerated.
2212         * aarch64-opc-2.c: Regenerated.
2213
2214 2019-01-23  Nick Clifton  <nickc@redhat.com>
2215
2216         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2217
2218 2019-01-21  Nick Clifton  <nickc@redhat.com>
2219
2220         * po/de.po: Updated German translation.
2221         * po/uk.po: Updated Ukranian translation.
2222
2223 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2224         * mips-dis.c (mips_arch_choices): Fix typo in
2225         gs464, gs464e and gs264e descriptors.
2226
2227 2019-01-19  Nick Clifton  <nickc@redhat.com>
2228
2229         * configure: Regenerate.
2230         * po/opcodes.pot: Regenerate.
2231
2232 2018-06-24  Nick Clifton  <nickc@redhat.com>
2233
2234         2.32 branch created.
2235
2236 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2237
2238         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2239         if it is null.
2240         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2241         zero.
2242
2243 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2244
2245         * configure: Regenerate.
2246
2247 2019-01-07  Alan Modra  <amodra@gmail.com>
2248
2249         * configure: Regenerate.
2250         * po/POTFILES.in: Regenerate.
2251
2252 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2253
2254         * s12z-opc.c: New file.
2255         * s12z-opc.h: New file.
2256         * s12z-dis.c: Removed all code not directly related to display
2257         of instructions.  Used the interface provided by the new files
2258         instead.
2259         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2260         * Makefile.in: Regenerate.
2261         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2262         * configure: Regenerate.
2263
2264 2019-01-01  Alan Modra  <amodra@gmail.com>
2265
2266         Update year range in copyright notice of all files.
2267
2268 For older changes see ChangeLog-2018
2269 \f
2270 Copyright (C) 2019 Free Software Foundation, Inc.
2271
2272 Copying and distribution of this file, with or without modification,
2273 are permitted in any medium without royalty provided the copyright
2274 notice and this notice are preserved.
2275
2276 Local Variables:
2277 mode: change-log
2278 left-margin: 8
2279 fill-column: 74
2280 version-control: never
2281 End: